1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20ac330f44SAndy Shevchenko #include <linux/kernel.h> 21d900f712SDenis Karpov #include <linux/debugfs.h> 22c5c98927SRussell King #include <linux/dmaengine.h> 23d900f712SDenis Karpov #include <linux/seq_file.h> 24031cd037SFelipe Balbi #include <linux/sizes.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 29a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 30a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 3146856a68SRajendra Nayak #include <linux/of.h> 3246856a68SRajendra Nayak #include <linux/of_gpio.h> 3346856a68SRajendra Nayak #include <linux/of_device.h> 343451c067SRussell King #include <linux/omap-dma.h> 35a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 3613189e78SJarkko Lavinen #include <linux/mmc/core.h> 3793caf8e6SAdrian Hunter #include <linux/mmc/mmc.h> 38a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 39db0fefc5SAdrian Hunter #include <linux/gpio.h> 40db0fefc5SAdrian Hunter #include <linux/regulator/consumer.h> 4146b76035SDaniel Mack #include <linux/pinctrl/consumer.h> 42fa4aa2d4SBalaji T K #include <linux/pm_runtime.h> 4368f39e74STony Lindgren #include <linux/platform_data/mmc-omap.h> 44a45c6cb8SMadhusudhan Chikkature 45a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 4611dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS 0x0014 47a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 48a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 49a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 50a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 51a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 52a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 57a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 58a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 59a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 60a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 61a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 62a45c6cb8SMadhusudhan Chikkature 63a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 64a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 65cd587096SHebbar, Gururaja #define HSS (1 << 21) 66a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 67a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 68eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 691b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 70a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 71a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 72a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 73a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 74a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 75a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 76a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 77a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 78ed164182SBalaji T K #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ 79a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 80a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 81a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 82a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 83a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 84a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 85a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 86a7e96879SVenkatraman S #define DMAE 0x1 87a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 88a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 89a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 90cd587096SHebbar, Gururaja #define HSPE (1 << 2) 9103b5d924SBalaji T K #define DDR (1 << 19) 9273153010SJarkko Lavinen #define DW8 (1 << 5) 93a45c6cb8SMadhusudhan Chikkature #define OD 0x1 94a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 95a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 96a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 97a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 98a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 9911dd62a7SDenis Karpov #define SOFTRESET (1 << 1) 10011dd62a7SDenis Karpov #define RESETDONE (1 << 0) 101a45c6cb8SMadhusudhan Chikkature 102a7e96879SVenkatraman S /* Interrupt masks for IE and ISE register */ 103a7e96879SVenkatraman S #define CC_EN (1 << 0) 104a7e96879SVenkatraman S #define TC_EN (1 << 1) 105a7e96879SVenkatraman S #define BWR_EN (1 << 4) 106a7e96879SVenkatraman S #define BRR_EN (1 << 5) 107a7e96879SVenkatraman S #define ERR_EN (1 << 15) 108a7e96879SVenkatraman S #define CTO_EN (1 << 16) 109a7e96879SVenkatraman S #define CCRC_EN (1 << 17) 110a7e96879SVenkatraman S #define CEB_EN (1 << 18) 111a7e96879SVenkatraman S #define CIE_EN (1 << 19) 112a7e96879SVenkatraman S #define DTO_EN (1 << 20) 113a7e96879SVenkatraman S #define DCRC_EN (1 << 21) 114a7e96879SVenkatraman S #define DEB_EN (1 << 22) 115a7e96879SVenkatraman S #define CERR_EN (1 << 28) 116a7e96879SVenkatraman S #define BADA_EN (1 << 29) 117a7e96879SVenkatraman S 118a7e96879SVenkatraman S #define INT_EN_MASK (BADA_EN | CERR_EN | DEB_EN | DCRC_EN |\ 119a7e96879SVenkatraman S DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ 120a7e96879SVenkatraman S BRR_EN | BWR_EN | TC_EN | CC_EN) 121a7e96879SVenkatraman S 122fa4aa2d4SBalaji T K #define MMC_AUTOSUSPEND_DELAY 100 1231e881786SJianpeng Ma #define MMC_TIMEOUT_MS 20 /* 20 mSec */ 1241e881786SJianpeng Ma #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ 1256b206efeSAndy Shevchenko #define OMAP_MMC_MIN_CLOCK 400000 1266b206efeSAndy Shevchenko #define OMAP_MMC_MAX_CLOCK 52000000 1270005ae73SKishore Kadiyala #define DRIVER_NAME "omap_hsmmc" 128a45c6cb8SMadhusudhan Chikkature 129a45c6cb8SMadhusudhan Chikkature /* 130a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 131a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 132a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 133a45c6cb8SMadhusudhan Chikkature */ 134a45c6cb8SMadhusudhan Chikkature #define mmc_slot(host) (host->pdata->slots[host->slot_id]) 135a45c6cb8SMadhusudhan Chikkature 136a45c6cb8SMadhusudhan Chikkature /* 137a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 138a45c6cb8SMadhusudhan Chikkature */ 139a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 140a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 141a45c6cb8SMadhusudhan Chikkature 142a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 143a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 144a45c6cb8SMadhusudhan Chikkature 1459782aff8SPer Forlin struct omap_hsmmc_next { 1469782aff8SPer Forlin unsigned int dma_len; 1479782aff8SPer Forlin s32 cookie; 1489782aff8SPer Forlin }; 1499782aff8SPer Forlin 15070a3341aSDenis Karpov struct omap_hsmmc_host { 151a45c6cb8SMadhusudhan Chikkature struct device *dev; 152a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 153a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 154a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 155a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 156a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 157a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 158db0fefc5SAdrian Hunter /* 159db0fefc5SAdrian Hunter * vcc == configured supply 160db0fefc5SAdrian Hunter * vcc_aux == optional 161db0fefc5SAdrian Hunter * - MMC1, supply for DAT4..DAT7 162db0fefc5SAdrian Hunter * - MMC2/MMC2, external level shifter voltage supply, for 163db0fefc5SAdrian Hunter * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) 164db0fefc5SAdrian Hunter */ 165db0fefc5SAdrian Hunter struct regulator *vcc; 166db0fefc5SAdrian Hunter struct regulator *vcc_aux; 167cf5ae40bSTony Lindgren int pbias_disable; 168a45c6cb8SMadhusudhan Chikkature void __iomem *base; 169a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 1704dffd7a2SAdrian Hunter spinlock_t irq_lock; /* Prevent races with irq handler */ 171a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 1720ccd76d4SJuha Yrjola unsigned int dma_sg_idx; 173a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 174a3621465SAdrian Hunter unsigned char power_mode; 175a45c6cb8SMadhusudhan Chikkature int suspended; 1760a82e06eSTony Lindgren u32 con; 1770a82e06eSTony Lindgren u32 hctl; 1780a82e06eSTony Lindgren u32 sysctl; 1790a82e06eSTony Lindgren u32 capa; 180a45c6cb8SMadhusudhan Chikkature int irq; 181a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 182c5c98927SRussell King struct dma_chan *tx_chan; 183c5c98927SRussell King struct dma_chan *rx_chan; 184a45c6cb8SMadhusudhan Chikkature int slot_id; 1854a694dc9SAdrian Hunter int response_busy; 18611dd62a7SDenis Karpov int context_loss; 187b62f6228SAdrian Hunter int protect_card; 188b62f6228SAdrian Hunter int reqs_blocked; 189db0fefc5SAdrian Hunter int use_reg; 190b417577dSAdrian Hunter int req_in_progress; 1919782aff8SPer Forlin struct omap_hsmmc_next next_data; 192a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata; 193a45c6cb8SMadhusudhan Chikkature }; 194a45c6cb8SMadhusudhan Chikkature 19559445b10SNishanth Menon struct omap_mmc_of_data { 19659445b10SNishanth Menon u32 reg_offset; 19759445b10SNishanth Menon u8 controller_flags; 19859445b10SNishanth Menon }; 19959445b10SNishanth Menon 200db0fefc5SAdrian Hunter static int omap_hsmmc_card_detect(struct device *dev, int slot) 201db0fefc5SAdrian Hunter { 2029ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2039ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 204db0fefc5SAdrian Hunter 205db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 206db0fefc5SAdrian Hunter return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 207db0fefc5SAdrian Hunter } 208db0fefc5SAdrian Hunter 209db0fefc5SAdrian Hunter static int omap_hsmmc_get_wp(struct device *dev, int slot) 210db0fefc5SAdrian Hunter { 2119ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2129ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 213db0fefc5SAdrian Hunter 214db0fefc5SAdrian Hunter /* NOTE: assumes write protect signal is active-high */ 215db0fefc5SAdrian Hunter return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); 216db0fefc5SAdrian Hunter } 217db0fefc5SAdrian Hunter 218db0fefc5SAdrian Hunter static int omap_hsmmc_get_cover_state(struct device *dev, int slot) 219db0fefc5SAdrian Hunter { 2209ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2219ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 222db0fefc5SAdrian Hunter 223db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 224db0fefc5SAdrian Hunter return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 225db0fefc5SAdrian Hunter } 226db0fefc5SAdrian Hunter 227db0fefc5SAdrian Hunter #ifdef CONFIG_PM 228db0fefc5SAdrian Hunter 229db0fefc5SAdrian Hunter static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) 230db0fefc5SAdrian Hunter { 2319ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2329ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 233db0fefc5SAdrian Hunter 234db0fefc5SAdrian Hunter disable_irq(mmc->slots[0].card_detect_irq); 235db0fefc5SAdrian Hunter return 0; 236db0fefc5SAdrian Hunter } 237db0fefc5SAdrian Hunter 238db0fefc5SAdrian Hunter static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) 239db0fefc5SAdrian Hunter { 2409ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2419ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 242db0fefc5SAdrian Hunter 243db0fefc5SAdrian Hunter enable_irq(mmc->slots[0].card_detect_irq); 244db0fefc5SAdrian Hunter return 0; 245db0fefc5SAdrian Hunter } 246db0fefc5SAdrian Hunter 247db0fefc5SAdrian Hunter #else 248db0fefc5SAdrian Hunter 249db0fefc5SAdrian Hunter #define omap_hsmmc_suspend_cdirq NULL 250db0fefc5SAdrian Hunter #define omap_hsmmc_resume_cdirq NULL 251db0fefc5SAdrian Hunter 252db0fefc5SAdrian Hunter #endif 253db0fefc5SAdrian Hunter 254b702b106SAdrian Hunter #ifdef CONFIG_REGULATOR 255b702b106SAdrian Hunter 25669b07eceSRajendra Nayak static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on, 257db0fefc5SAdrian Hunter int vdd) 258db0fefc5SAdrian Hunter { 259db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 260db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 261db0fefc5SAdrian Hunter int ret = 0; 262db0fefc5SAdrian Hunter 263db0fefc5SAdrian Hunter /* 264db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 265db0fefc5SAdrian Hunter * voltage always-on regulator. 266db0fefc5SAdrian Hunter */ 267db0fefc5SAdrian Hunter if (!host->vcc) 268db0fefc5SAdrian Hunter return 0; 2691f84b71bSRajendra Nayak /* 270cf5ae40bSTony Lindgren * With DT, never turn OFF the regulator for MMC1. This is because 2711f84b71bSRajendra Nayak * the pbias cell programming support is still missing when 2721f84b71bSRajendra Nayak * booting with Device tree 2731f84b71bSRajendra Nayak */ 274cf5ae40bSTony Lindgren if (host->pbias_disable && !vdd) 2751f84b71bSRajendra Nayak return 0; 276db0fefc5SAdrian Hunter 277db0fefc5SAdrian Hunter if (mmc_slot(host).before_set_reg) 278db0fefc5SAdrian Hunter mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 279db0fefc5SAdrian Hunter 280db0fefc5SAdrian Hunter /* 281db0fefc5SAdrian Hunter * Assume Vcc regulator is used only to power the card ... OMAP 282db0fefc5SAdrian Hunter * VDDS is used to power the pins, optionally with a transceiver to 283db0fefc5SAdrian Hunter * support cards using voltages other than VDDS (1.8V nominal). When a 284db0fefc5SAdrian Hunter * transceiver is used, DAT3..7 are muxed as transceiver control pins. 285db0fefc5SAdrian Hunter * 286db0fefc5SAdrian Hunter * In some cases this regulator won't support enable/disable; 287db0fefc5SAdrian Hunter * e.g. it's a fixed rail for a WLAN chip. 288db0fefc5SAdrian Hunter * 289db0fefc5SAdrian Hunter * In other cases vcc_aux switches interface power. Example, for 290db0fefc5SAdrian Hunter * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 291db0fefc5SAdrian Hunter * chips/cards need an interface voltage rail too. 292db0fefc5SAdrian Hunter */ 293db0fefc5SAdrian Hunter if (power_on) { 29499fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 295db0fefc5SAdrian Hunter /* Enable interface voltage rail, if needed */ 296db0fefc5SAdrian Hunter if (ret == 0 && host->vcc_aux) { 297db0fefc5SAdrian Hunter ret = regulator_enable(host->vcc_aux); 298db0fefc5SAdrian Hunter if (ret < 0) 29999fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 30099fc5131SLinus Walleij host->vcc, 0); 301db0fefc5SAdrian Hunter } 302db0fefc5SAdrian Hunter } else { 30399fc5131SLinus Walleij /* Shut down the rail */ 3046da20c89SAdrian Hunter if (host->vcc_aux) 305db0fefc5SAdrian Hunter ret = regulator_disable(host->vcc_aux); 30699fc5131SLinus Walleij if (!ret) { 30799fc5131SLinus Walleij /* Then proceed to shut down the local regulator */ 30899fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 30999fc5131SLinus Walleij host->vcc, 0); 31099fc5131SLinus Walleij } 311db0fefc5SAdrian Hunter } 312db0fefc5SAdrian Hunter 313db0fefc5SAdrian Hunter if (mmc_slot(host).after_set_reg) 314db0fefc5SAdrian Hunter mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 315db0fefc5SAdrian Hunter 316db0fefc5SAdrian Hunter return ret; 317db0fefc5SAdrian Hunter } 318db0fefc5SAdrian Hunter 319db0fefc5SAdrian Hunter static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 320db0fefc5SAdrian Hunter { 321db0fefc5SAdrian Hunter struct regulator *reg; 32264be9782Skishore kadiyala int ocr_value = 0; 323db0fefc5SAdrian Hunter 324db0fefc5SAdrian Hunter reg = regulator_get(host->dev, "vmmc"); 325db0fefc5SAdrian Hunter if (IS_ERR(reg)) { 326b1e056aeSVenkatraman S dev_err(host->dev, "vmmc regulator missing\n"); 3271fdc90fbSNeilBrown return PTR_ERR(reg); 328db0fefc5SAdrian Hunter } else { 3291fdc90fbSNeilBrown mmc_slot(host).set_power = omap_hsmmc_set_power; 330db0fefc5SAdrian Hunter host->vcc = reg; 33164be9782Skishore kadiyala ocr_value = mmc_regulator_get_ocrmask(reg); 33264be9782Skishore kadiyala if (!mmc_slot(host).ocr_mask) { 33364be9782Skishore kadiyala mmc_slot(host).ocr_mask = ocr_value; 33464be9782Skishore kadiyala } else { 33564be9782Skishore kadiyala if (!(mmc_slot(host).ocr_mask & ocr_value)) { 3362cecdf00SRajendra Nayak dev_err(host->dev, "ocrmask %x is not supported\n", 337e3f1adb6SRajendra Nayak mmc_slot(host).ocr_mask); 33864be9782Skishore kadiyala mmc_slot(host).ocr_mask = 0; 33964be9782Skishore kadiyala return -EINVAL; 34064be9782Skishore kadiyala } 34164be9782Skishore kadiyala } 342db0fefc5SAdrian Hunter 343db0fefc5SAdrian Hunter /* Allow an aux regulator */ 344db0fefc5SAdrian Hunter reg = regulator_get(host->dev, "vmmc_aux"); 345db0fefc5SAdrian Hunter host->vcc_aux = IS_ERR(reg) ? NULL : reg; 346db0fefc5SAdrian Hunter 347b1c1df7aSBalaji T K /* For eMMC do not power off when not in sleep state */ 348b1c1df7aSBalaji T K if (mmc_slot(host).no_regulator_off_init) 349b1c1df7aSBalaji T K return 0; 350db0fefc5SAdrian Hunter /* 351db0fefc5SAdrian Hunter * UGLY HACK: workaround regulator framework bugs. 352db0fefc5SAdrian Hunter * When the bootloader leaves a supply active, it's 353db0fefc5SAdrian Hunter * initialized with zero usecount ... and we can't 354db0fefc5SAdrian Hunter * disable it without first enabling it. Until the 355db0fefc5SAdrian Hunter * framework is fixed, we need a workaround like this 356db0fefc5SAdrian Hunter * (which is safe for MMC, but not in general). 357db0fefc5SAdrian Hunter */ 358e840ce13SAdrian Hunter if (regulator_is_enabled(host->vcc) > 0 || 359e840ce13SAdrian Hunter (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) { 360e840ce13SAdrian Hunter int vdd = ffs(mmc_slot(host).ocr_mask) - 1; 361e840ce13SAdrian Hunter 362e840ce13SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 363e840ce13SAdrian Hunter 1, vdd); 364e840ce13SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 365e840ce13SAdrian Hunter 0, 0); 366db0fefc5SAdrian Hunter } 367db0fefc5SAdrian Hunter } 368db0fefc5SAdrian Hunter 369db0fefc5SAdrian Hunter return 0; 370db0fefc5SAdrian Hunter } 371db0fefc5SAdrian Hunter 372db0fefc5SAdrian Hunter static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 373db0fefc5SAdrian Hunter { 374db0fefc5SAdrian Hunter regulator_put(host->vcc); 375db0fefc5SAdrian Hunter regulator_put(host->vcc_aux); 376db0fefc5SAdrian Hunter mmc_slot(host).set_power = NULL; 377db0fefc5SAdrian Hunter } 378db0fefc5SAdrian Hunter 379b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 380b702b106SAdrian Hunter { 381b702b106SAdrian Hunter return 1; 382b702b106SAdrian Hunter } 383b702b106SAdrian Hunter 384b702b106SAdrian Hunter #else 385b702b106SAdrian Hunter 386b702b106SAdrian Hunter static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 387b702b106SAdrian Hunter { 388b702b106SAdrian Hunter return -EINVAL; 389b702b106SAdrian Hunter } 390b702b106SAdrian Hunter 391b702b106SAdrian Hunter static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 392b702b106SAdrian Hunter { 393b702b106SAdrian Hunter } 394b702b106SAdrian Hunter 395b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 396b702b106SAdrian Hunter { 397b702b106SAdrian Hunter return 0; 398b702b106SAdrian Hunter } 399b702b106SAdrian Hunter 400b702b106SAdrian Hunter #endif 401b702b106SAdrian Hunter 402b702b106SAdrian Hunter static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) 403b702b106SAdrian Hunter { 404b702b106SAdrian Hunter int ret; 405b702b106SAdrian Hunter 406b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) { 407b702b106SAdrian Hunter if (pdata->slots[0].cover) 408b702b106SAdrian Hunter pdata->slots[0].get_cover_state = 409b702b106SAdrian Hunter omap_hsmmc_get_cover_state; 410b702b106SAdrian Hunter else 411b702b106SAdrian Hunter pdata->slots[0].card_detect = omap_hsmmc_card_detect; 412b702b106SAdrian Hunter pdata->slots[0].card_detect_irq = 413b702b106SAdrian Hunter gpio_to_irq(pdata->slots[0].switch_pin); 414b702b106SAdrian Hunter ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd"); 415b702b106SAdrian Hunter if (ret) 416b702b106SAdrian Hunter return ret; 417b702b106SAdrian Hunter ret = gpio_direction_input(pdata->slots[0].switch_pin); 418b702b106SAdrian Hunter if (ret) 419b702b106SAdrian Hunter goto err_free_sp; 420b702b106SAdrian Hunter } else 421b702b106SAdrian Hunter pdata->slots[0].switch_pin = -EINVAL; 422b702b106SAdrian Hunter 423b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].gpio_wp)) { 424b702b106SAdrian Hunter pdata->slots[0].get_ro = omap_hsmmc_get_wp; 425b702b106SAdrian Hunter ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp"); 426b702b106SAdrian Hunter if (ret) 427b702b106SAdrian Hunter goto err_free_cd; 428b702b106SAdrian Hunter ret = gpio_direction_input(pdata->slots[0].gpio_wp); 429b702b106SAdrian Hunter if (ret) 430b702b106SAdrian Hunter goto err_free_wp; 431b702b106SAdrian Hunter } else 432b702b106SAdrian Hunter pdata->slots[0].gpio_wp = -EINVAL; 433b702b106SAdrian Hunter 434b702b106SAdrian Hunter return 0; 435b702b106SAdrian Hunter 436b702b106SAdrian Hunter err_free_wp: 437b702b106SAdrian Hunter gpio_free(pdata->slots[0].gpio_wp); 438b702b106SAdrian Hunter err_free_cd: 439b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) 440b702b106SAdrian Hunter err_free_sp: 441b702b106SAdrian Hunter gpio_free(pdata->slots[0].switch_pin); 442b702b106SAdrian Hunter return ret; 443b702b106SAdrian Hunter } 444b702b106SAdrian Hunter 445b702b106SAdrian Hunter static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) 446b702b106SAdrian Hunter { 447b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].gpio_wp)) 448b702b106SAdrian Hunter gpio_free(pdata->slots[0].gpio_wp); 449b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) 450b702b106SAdrian Hunter gpio_free(pdata->slots[0].switch_pin); 451b702b106SAdrian Hunter } 452b702b106SAdrian Hunter 453a45c6cb8SMadhusudhan Chikkature /* 454e0c7f99bSAndy Shevchenko * Start clock to the card 455e0c7f99bSAndy Shevchenko */ 456e0c7f99bSAndy Shevchenko static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 457e0c7f99bSAndy Shevchenko { 458e0c7f99bSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 459e0c7f99bSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 460e0c7f99bSAndy Shevchenko } 461e0c7f99bSAndy Shevchenko 462e0c7f99bSAndy Shevchenko /* 463a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 464a45c6cb8SMadhusudhan Chikkature */ 46570a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 466a45c6cb8SMadhusudhan Chikkature { 467a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 468a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 469a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 4707122bbb0SMasanari Iida dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); 471a45c6cb8SMadhusudhan Chikkature } 472a45c6cb8SMadhusudhan Chikkature 47393caf8e6SAdrian Hunter static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 47493caf8e6SAdrian Hunter struct mmc_command *cmd) 475b417577dSAdrian Hunter { 476b417577dSAdrian Hunter unsigned int irq_mask; 477b417577dSAdrian Hunter 478b417577dSAdrian Hunter if (host->use_dma) 479a7e96879SVenkatraman S irq_mask = INT_EN_MASK & ~(BRR_EN | BWR_EN); 480b417577dSAdrian Hunter else 481b417577dSAdrian Hunter irq_mask = INT_EN_MASK; 482b417577dSAdrian Hunter 48393caf8e6SAdrian Hunter /* Disable timeout for erases */ 48493caf8e6SAdrian Hunter if (cmd->opcode == MMC_ERASE) 485a7e96879SVenkatraman S irq_mask &= ~DTO_EN; 48693caf8e6SAdrian Hunter 487b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 488b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 489b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 490b417577dSAdrian Hunter } 491b417577dSAdrian Hunter 492b417577dSAdrian Hunter static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 493b417577dSAdrian Hunter { 494b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, 0); 495b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, 0); 496b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 497b417577dSAdrian Hunter } 498b417577dSAdrian Hunter 499ac330f44SAndy Shevchenko /* Calculate divisor for the given clock frequency */ 500d83b6e03SBalaji TK static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 501ac330f44SAndy Shevchenko { 502ac330f44SAndy Shevchenko u16 dsor = 0; 503ac330f44SAndy Shevchenko 504ac330f44SAndy Shevchenko if (ios->clock) { 505d83b6e03SBalaji TK dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 506ed164182SBalaji T K if (dsor > CLKD_MAX) 507ed164182SBalaji T K dsor = CLKD_MAX; 508ac330f44SAndy Shevchenko } 509ac330f44SAndy Shevchenko 510ac330f44SAndy Shevchenko return dsor; 511ac330f44SAndy Shevchenko } 512ac330f44SAndy Shevchenko 5135934df2fSAndy Shevchenko static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 5145934df2fSAndy Shevchenko { 5155934df2fSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5165934df2fSAndy Shevchenko unsigned long regval; 5175934df2fSAndy Shevchenko unsigned long timeout; 518cd587096SHebbar, Gururaja unsigned long clkdiv; 5195934df2fSAndy Shevchenko 5208986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 5215934df2fSAndy Shevchenko 5225934df2fSAndy Shevchenko omap_hsmmc_stop_clock(host); 5235934df2fSAndy Shevchenko 5245934df2fSAndy Shevchenko regval = OMAP_HSMMC_READ(host->base, SYSCTL); 5255934df2fSAndy Shevchenko regval = regval & ~(CLKD_MASK | DTO_MASK); 526cd587096SHebbar, Gururaja clkdiv = calc_divisor(host, ios); 527cd587096SHebbar, Gururaja regval = regval | (clkdiv << 6) | (DTO << 16); 5285934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 5295934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 5305934df2fSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 5315934df2fSAndy Shevchenko 5325934df2fSAndy Shevchenko /* Wait till the ICS bit is set */ 5335934df2fSAndy Shevchenko timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 5345934df2fSAndy Shevchenko while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 5355934df2fSAndy Shevchenko && time_before(jiffies, timeout)) 5365934df2fSAndy Shevchenko cpu_relax(); 5375934df2fSAndy Shevchenko 538cd587096SHebbar, Gururaja /* 539cd587096SHebbar, Gururaja * Enable High-Speed Support 540cd587096SHebbar, Gururaja * Pre-Requisites 541cd587096SHebbar, Gururaja * - Controller should support High-Speed-Enable Bit 542cd587096SHebbar, Gururaja * - Controller should not be using DDR Mode 543cd587096SHebbar, Gururaja * - Controller should advertise that it supports High Speed 544cd587096SHebbar, Gururaja * in capabilities register 545cd587096SHebbar, Gururaja * - MMC/SD clock coming out of controller > 25MHz 546cd587096SHebbar, Gururaja */ 547cd587096SHebbar, Gururaja if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) && 548cd587096SHebbar, Gururaja (ios->timing != MMC_TIMING_UHS_DDR50) && 549cd587096SHebbar, Gururaja ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 550cd587096SHebbar, Gururaja regval = OMAP_HSMMC_READ(host->base, HCTL); 551cd587096SHebbar, Gururaja if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 552cd587096SHebbar, Gururaja regval |= HSPE; 553cd587096SHebbar, Gururaja else 554cd587096SHebbar, Gururaja regval &= ~HSPE; 555cd587096SHebbar, Gururaja 556cd587096SHebbar, Gururaja OMAP_HSMMC_WRITE(host->base, HCTL, regval); 557cd587096SHebbar, Gururaja } 558cd587096SHebbar, Gururaja 5595934df2fSAndy Shevchenko omap_hsmmc_start_clock(host); 5605934df2fSAndy Shevchenko } 5615934df2fSAndy Shevchenko 5623796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 5633796fb8aSAndy Shevchenko { 5643796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5653796fb8aSAndy Shevchenko u32 con; 5663796fb8aSAndy Shevchenko 5673796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 56803b5d924SBalaji T K if (ios->timing == MMC_TIMING_UHS_DDR50) 56903b5d924SBalaji T K con |= DDR; /* configure in DDR mode */ 57003b5d924SBalaji T K else 57103b5d924SBalaji T K con &= ~DDR; 5723796fb8aSAndy Shevchenko switch (ios->bus_width) { 5733796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_8: 5743796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 5753796fb8aSAndy Shevchenko break; 5763796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_4: 5773796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 5783796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 5793796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 5803796fb8aSAndy Shevchenko break; 5813796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_1: 5823796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 5833796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 5843796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 5853796fb8aSAndy Shevchenko break; 5863796fb8aSAndy Shevchenko } 5873796fb8aSAndy Shevchenko } 5883796fb8aSAndy Shevchenko 5893796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 5903796fb8aSAndy Shevchenko { 5913796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5923796fb8aSAndy Shevchenko u32 con; 5933796fb8aSAndy Shevchenko 5943796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 5953796fb8aSAndy Shevchenko if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 5963796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | OD); 5973796fb8aSAndy Shevchenko else 5983796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 5993796fb8aSAndy Shevchenko } 6003796fb8aSAndy Shevchenko 60111dd62a7SDenis Karpov #ifdef CONFIG_PM 60211dd62a7SDenis Karpov 60311dd62a7SDenis Karpov /* 60411dd62a7SDenis Karpov * Restore the MMC host context, if it was lost as result of a 60511dd62a7SDenis Karpov * power state change. 60611dd62a7SDenis Karpov */ 60770a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 60811dd62a7SDenis Karpov { 60911dd62a7SDenis Karpov struct mmc_ios *ios = &host->mmc->ios; 6103796fb8aSAndy Shevchenko u32 hctl, capa; 61111dd62a7SDenis Karpov unsigned long timeout; 61211dd62a7SDenis Karpov 6136c31b215SVenkatraman S if (!OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) 6146c31b215SVenkatraman S return 1; 61511dd62a7SDenis Karpov 6160a82e06eSTony Lindgren if (host->con == OMAP_HSMMC_READ(host->base, CON) && 6170a82e06eSTony Lindgren host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && 6180a82e06eSTony Lindgren host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && 6190a82e06eSTony Lindgren host->capa == OMAP_HSMMC_READ(host->base, CAPA)) 6200a82e06eSTony Lindgren return 0; 6210a82e06eSTony Lindgren 6220a82e06eSTony Lindgren host->context_loss++; 6230a82e06eSTony Lindgren 624c2200efbSBalaji T K if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 62511dd62a7SDenis Karpov if (host->power_mode != MMC_POWER_OFF && 62611dd62a7SDenis Karpov (1 << ios->vdd) <= MMC_VDD_23_24) 62711dd62a7SDenis Karpov hctl = SDVS18; 62811dd62a7SDenis Karpov else 62911dd62a7SDenis Karpov hctl = SDVS30; 63011dd62a7SDenis Karpov capa = VS30 | VS18; 63111dd62a7SDenis Karpov } else { 63211dd62a7SDenis Karpov hctl = SDVS18; 63311dd62a7SDenis Karpov capa = VS18; 63411dd62a7SDenis Karpov } 63511dd62a7SDenis Karpov 63611dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 63711dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | hctl); 63811dd62a7SDenis Karpov 63911dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CAPA, 64011dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA) | capa); 64111dd62a7SDenis Karpov 64211dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 64311dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 64411dd62a7SDenis Karpov 64511dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 64611dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 64711dd62a7SDenis Karpov && time_before(jiffies, timeout)) 64811dd62a7SDenis Karpov ; 64911dd62a7SDenis Karpov 650b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 65111dd62a7SDenis Karpov 65211dd62a7SDenis Karpov /* Do not initialize card-specific things if the power is off */ 65311dd62a7SDenis Karpov if (host->power_mode == MMC_POWER_OFF) 65411dd62a7SDenis Karpov goto out; 65511dd62a7SDenis Karpov 6563796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 65711dd62a7SDenis Karpov 6585934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 65911dd62a7SDenis Karpov 6603796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 6613796fb8aSAndy Shevchenko 66211dd62a7SDenis Karpov out: 6630a82e06eSTony Lindgren dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", 6640a82e06eSTony Lindgren host->context_loss); 66511dd62a7SDenis Karpov return 0; 66611dd62a7SDenis Karpov } 66711dd62a7SDenis Karpov 66811dd62a7SDenis Karpov /* 66911dd62a7SDenis Karpov * Save the MMC host context (store the number of power state changes so far). 67011dd62a7SDenis Karpov */ 67170a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 67211dd62a7SDenis Karpov { 6730a82e06eSTony Lindgren host->con = OMAP_HSMMC_READ(host->base, CON); 6740a82e06eSTony Lindgren host->hctl = OMAP_HSMMC_READ(host->base, HCTL); 6750a82e06eSTony Lindgren host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); 6760a82e06eSTony Lindgren host->capa = OMAP_HSMMC_READ(host->base, CAPA); 67711dd62a7SDenis Karpov } 67811dd62a7SDenis Karpov 67911dd62a7SDenis Karpov #else 68011dd62a7SDenis Karpov 68170a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 68211dd62a7SDenis Karpov { 68311dd62a7SDenis Karpov return 0; 68411dd62a7SDenis Karpov } 68511dd62a7SDenis Karpov 68670a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 68711dd62a7SDenis Karpov { 68811dd62a7SDenis Karpov } 68911dd62a7SDenis Karpov 69011dd62a7SDenis Karpov #endif 69111dd62a7SDenis Karpov 692a45c6cb8SMadhusudhan Chikkature /* 693a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 694a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 695a45c6cb8SMadhusudhan Chikkature */ 69670a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host) 697a45c6cb8SMadhusudhan Chikkature { 698a45c6cb8SMadhusudhan Chikkature int reg = 0; 699a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 700a45c6cb8SMadhusudhan Chikkature 701b62f6228SAdrian Hunter if (host->protect_card) 702b62f6228SAdrian Hunter return; 703b62f6228SAdrian Hunter 704a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 705b417577dSAdrian Hunter 706b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 707a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 708a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 709a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 710a45c6cb8SMadhusudhan Chikkature 711a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 712a7e96879SVenkatraman S while ((reg != CC_EN) && time_before(jiffies, timeout)) 713a7e96879SVenkatraman S reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; 714a45c6cb8SMadhusudhan Chikkature 715a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 716a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 717c653a6d4SAdrian Hunter 718c653a6d4SAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 719c653a6d4SAdrian Hunter OMAP_HSMMC_READ(host->base, STAT); 720c653a6d4SAdrian Hunter 721a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 722a45c6cb8SMadhusudhan Chikkature } 723a45c6cb8SMadhusudhan Chikkature 724a45c6cb8SMadhusudhan Chikkature static inline 72570a3341aSDenis Karpov int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 726a45c6cb8SMadhusudhan Chikkature { 727a45c6cb8SMadhusudhan Chikkature int r = 1; 728a45c6cb8SMadhusudhan Chikkature 729191d1f1dSDenis Karpov if (mmc_slot(host).get_cover_state) 730191d1f1dSDenis Karpov r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); 731a45c6cb8SMadhusudhan Chikkature return r; 732a45c6cb8SMadhusudhan Chikkature } 733a45c6cb8SMadhusudhan Chikkature 734a45c6cb8SMadhusudhan Chikkature static ssize_t 73570a3341aSDenis Karpov omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 736a45c6cb8SMadhusudhan Chikkature char *buf) 737a45c6cb8SMadhusudhan Chikkature { 738a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 73970a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 740a45c6cb8SMadhusudhan Chikkature 74170a3341aSDenis Karpov return sprintf(buf, "%s\n", 74270a3341aSDenis Karpov omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 743a45c6cb8SMadhusudhan Chikkature } 744a45c6cb8SMadhusudhan Chikkature 74570a3341aSDenis Karpov static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 746a45c6cb8SMadhusudhan Chikkature 747a45c6cb8SMadhusudhan Chikkature static ssize_t 74870a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 749a45c6cb8SMadhusudhan Chikkature char *buf) 750a45c6cb8SMadhusudhan Chikkature { 751a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 75270a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 753a45c6cb8SMadhusudhan Chikkature 754191d1f1dSDenis Karpov return sprintf(buf, "%s\n", mmc_slot(host).name); 755a45c6cb8SMadhusudhan Chikkature } 756a45c6cb8SMadhusudhan Chikkature 75770a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 758a45c6cb8SMadhusudhan Chikkature 759a45c6cb8SMadhusudhan Chikkature /* 760a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 761a45c6cb8SMadhusudhan Chikkature */ 762a45c6cb8SMadhusudhan Chikkature static void 76370a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 764a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 765a45c6cb8SMadhusudhan Chikkature { 766a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 767a45c6cb8SMadhusudhan Chikkature 7688986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 769a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 770a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 771a45c6cb8SMadhusudhan Chikkature 77293caf8e6SAdrian Hunter omap_hsmmc_enable_irq(host, cmd); 773a45c6cb8SMadhusudhan Chikkature 7744a694dc9SAdrian Hunter host->response_busy = 0; 775a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 776a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 777a45c6cb8SMadhusudhan Chikkature resptype = 1; 7784a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 7794a694dc9SAdrian Hunter resptype = 3; 7804a694dc9SAdrian Hunter host->response_busy = 1; 7814a694dc9SAdrian Hunter } else 782a45c6cb8SMadhusudhan Chikkature resptype = 2; 783a45c6cb8SMadhusudhan Chikkature } 784a45c6cb8SMadhusudhan Chikkature 785a45c6cb8SMadhusudhan Chikkature /* 786a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 787a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 788a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 789a45c6cb8SMadhusudhan Chikkature */ 790a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 791a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 792a45c6cb8SMadhusudhan Chikkature 793a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 794a45c6cb8SMadhusudhan Chikkature 795a45c6cb8SMadhusudhan Chikkature if (data) { 796a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 797a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 798a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 799a45c6cb8SMadhusudhan Chikkature else 800a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 801a45c6cb8SMadhusudhan Chikkature } 802a45c6cb8SMadhusudhan Chikkature 803a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 804a7e96879SVenkatraman S cmdreg |= DMAE; 805a45c6cb8SMadhusudhan Chikkature 806b417577dSAdrian Hunter host->req_in_progress = 1; 8074dffd7a2SAdrian Hunter 808a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 809a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 810a45c6cb8SMadhusudhan Chikkature } 811a45c6cb8SMadhusudhan Chikkature 8120ccd76d4SJuha Yrjola static int 81370a3341aSDenis Karpov omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 8140ccd76d4SJuha Yrjola { 8150ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) 8160ccd76d4SJuha Yrjola return DMA_TO_DEVICE; 8170ccd76d4SJuha Yrjola else 8180ccd76d4SJuha Yrjola return DMA_FROM_DEVICE; 8190ccd76d4SJuha Yrjola } 8200ccd76d4SJuha Yrjola 821c5c98927SRussell King static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 822c5c98927SRussell King struct mmc_data *data) 823c5c98927SRussell King { 824c5c98927SRussell King return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 825c5c98927SRussell King } 826c5c98927SRussell King 827b417577dSAdrian Hunter static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 828b417577dSAdrian Hunter { 829b417577dSAdrian Hunter int dma_ch; 83031463b14SVenkatraman S unsigned long flags; 831b417577dSAdrian Hunter 83231463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 833b417577dSAdrian Hunter host->req_in_progress = 0; 834b417577dSAdrian Hunter dma_ch = host->dma_ch; 83531463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 836b417577dSAdrian Hunter 837b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 838b417577dSAdrian Hunter /* Do not complete the request if DMA is still in progress */ 839b417577dSAdrian Hunter if (mrq->data && host->use_dma && dma_ch != -1) 840b417577dSAdrian Hunter return; 841b417577dSAdrian Hunter host->mrq = NULL; 842b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 843b417577dSAdrian Hunter } 844b417577dSAdrian Hunter 845a45c6cb8SMadhusudhan Chikkature /* 846a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 847a45c6cb8SMadhusudhan Chikkature */ 848a45c6cb8SMadhusudhan Chikkature static void 84970a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 850a45c6cb8SMadhusudhan Chikkature { 8514a694dc9SAdrian Hunter if (!data) { 8524a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 8534a694dc9SAdrian Hunter 85423050103SAdrian Hunter /* TC before CC from CMD6 - don't know why, but it happens */ 85523050103SAdrian Hunter if (host->cmd && host->cmd->opcode == 6 && 85623050103SAdrian Hunter host->response_busy) { 85723050103SAdrian Hunter host->response_busy = 0; 85823050103SAdrian Hunter return; 85923050103SAdrian Hunter } 86023050103SAdrian Hunter 861b417577dSAdrian Hunter omap_hsmmc_request_done(host, mrq); 8624a694dc9SAdrian Hunter return; 8634a694dc9SAdrian Hunter } 8644a694dc9SAdrian Hunter 865a45c6cb8SMadhusudhan Chikkature host->data = NULL; 866a45c6cb8SMadhusudhan Chikkature 867a45c6cb8SMadhusudhan Chikkature if (!data->error) 868a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 869a45c6cb8SMadhusudhan Chikkature else 870a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 871a45c6cb8SMadhusudhan Chikkature 872fe852273SMing Lei if (!data->stop) { 873dba3c29eSBalaji T K omap_hsmmc_request_done(host, data->mrq); 874fe852273SMing Lei return; 875dba3c29eSBalaji T K } 876fe852273SMing Lei omap_hsmmc_start_command(host, data->stop, NULL); 877a45c6cb8SMadhusudhan Chikkature } 878a45c6cb8SMadhusudhan Chikkature 879a45c6cb8SMadhusudhan Chikkature /* 880a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 881a45c6cb8SMadhusudhan Chikkature */ 882a45c6cb8SMadhusudhan Chikkature static void 88370a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 884a45c6cb8SMadhusudhan Chikkature { 885a45c6cb8SMadhusudhan Chikkature host->cmd = NULL; 886a45c6cb8SMadhusudhan Chikkature 887a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 888a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 889a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 890a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 891a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 892a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 893a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 894a45c6cb8SMadhusudhan Chikkature } else { 895a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 896a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 897a45c6cb8SMadhusudhan Chikkature } 898a45c6cb8SMadhusudhan Chikkature } 899b417577dSAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) 900b417577dSAdrian Hunter omap_hsmmc_request_done(host, cmd->mrq); 901a45c6cb8SMadhusudhan Chikkature } 902a45c6cb8SMadhusudhan Chikkature 903a45c6cb8SMadhusudhan Chikkature /* 904a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 905a45c6cb8SMadhusudhan Chikkature */ 90670a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 907a45c6cb8SMadhusudhan Chikkature { 908b417577dSAdrian Hunter int dma_ch; 90931463b14SVenkatraman S unsigned long flags; 910b417577dSAdrian Hunter 91182788ff5SJarkko Lavinen host->data->error = errno; 912a45c6cb8SMadhusudhan Chikkature 91331463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 914b417577dSAdrian Hunter dma_ch = host->dma_ch; 915b417577dSAdrian Hunter host->dma_ch = -1; 91631463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 917b417577dSAdrian Hunter 918b417577dSAdrian Hunter if (host->use_dma && dma_ch != -1) { 919c5c98927SRussell King struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 920c5c98927SRussell King 921c5c98927SRussell King dmaengine_terminate_all(chan); 922c5c98927SRussell King dma_unmap_sg(chan->device->dev, 923c5c98927SRussell King host->data->sg, host->data->sg_len, 92470a3341aSDenis Karpov omap_hsmmc_get_dma_dir(host, host->data)); 925c5c98927SRussell King 926053bf34fSPer Forlin host->data->host_cookie = 0; 927a45c6cb8SMadhusudhan Chikkature } 928a45c6cb8SMadhusudhan Chikkature host->data = NULL; 929a45c6cb8SMadhusudhan Chikkature } 930a45c6cb8SMadhusudhan Chikkature 931a45c6cb8SMadhusudhan Chikkature /* 932a45c6cb8SMadhusudhan Chikkature * Readable error output 933a45c6cb8SMadhusudhan Chikkature */ 934a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 935699b958bSAdrian Hunter static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 936a45c6cb8SMadhusudhan Chikkature { 937a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 93870a3341aSDenis Karpov static const char *omap_hsmmc_status_bits[] = { 939699b958bSAdrian Hunter "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 940699b958bSAdrian Hunter "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 941699b958bSAdrian Hunter "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 942699b958bSAdrian Hunter "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 943a45c6cb8SMadhusudhan Chikkature }; 944a45c6cb8SMadhusudhan Chikkature char res[256]; 945a45c6cb8SMadhusudhan Chikkature char *buf = res; 946a45c6cb8SMadhusudhan Chikkature int len, i; 947a45c6cb8SMadhusudhan Chikkature 948a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 949a45c6cb8SMadhusudhan Chikkature buf += len; 950a45c6cb8SMadhusudhan Chikkature 95170a3341aSDenis Karpov for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 952a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 95370a3341aSDenis Karpov len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 954a45c6cb8SMadhusudhan Chikkature buf += len; 955a45c6cb8SMadhusudhan Chikkature } 956a45c6cb8SMadhusudhan Chikkature 9578986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 958a45c6cb8SMadhusudhan Chikkature } 959699b958bSAdrian Hunter #else 960699b958bSAdrian Hunter static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 961699b958bSAdrian Hunter u32 status) 962699b958bSAdrian Hunter { 963699b958bSAdrian Hunter } 964a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 965a45c6cb8SMadhusudhan Chikkature 9663ebf74b1SJean Pihet /* 9673ebf74b1SJean Pihet * MMC controller internal state machines reset 9683ebf74b1SJean Pihet * 9693ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 9703ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 9713ebf74b1SJean Pihet * Can be called from interrupt context 9723ebf74b1SJean Pihet */ 97370a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 9743ebf74b1SJean Pihet unsigned long bit) 9753ebf74b1SJean Pihet { 9763ebf74b1SJean Pihet unsigned long i = 0; 9771e881786SJianpeng Ma unsigned long limit = MMC_TIMEOUT_US; 9783ebf74b1SJean Pihet 9793ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 9803ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 9813ebf74b1SJean Pihet 98207ad64b6SMadhusudhan Chikkature /* 98307ad64b6SMadhusudhan Chikkature * OMAP4 ES2 and greater has an updated reset logic. 98407ad64b6SMadhusudhan Chikkature * Monitor a 0->1 transition first 98507ad64b6SMadhusudhan Chikkature */ 98607ad64b6SMadhusudhan Chikkature if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) { 987b432b4b3Skishore kadiyala while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 98807ad64b6SMadhusudhan Chikkature && (i++ < limit)) 9891e881786SJianpeng Ma udelay(1); 99007ad64b6SMadhusudhan Chikkature } 99107ad64b6SMadhusudhan Chikkature i = 0; 99207ad64b6SMadhusudhan Chikkature 9933ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 9943ebf74b1SJean Pihet (i++ < limit)) 9951e881786SJianpeng Ma udelay(1); 9963ebf74b1SJean Pihet 9973ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 9983ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 9993ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 10003ebf74b1SJean Pihet __func__); 10013ebf74b1SJean Pihet } 1002a45c6cb8SMadhusudhan Chikkature 100325e1897bSBalaji T K static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, 100425e1897bSBalaji T K int err, int end_cmd) 1005ae4bf788SVenkatraman S { 100625e1897bSBalaji T K if (end_cmd) { 100794d4f272SBalaji T K omap_hsmmc_reset_controller_fsm(host, SRC); 100825e1897bSBalaji T K if (host->cmd) 1009ae4bf788SVenkatraman S host->cmd->error = err; 101025e1897bSBalaji T K } 1011ae4bf788SVenkatraman S 1012ae4bf788SVenkatraman S if (host->data) { 1013ae4bf788SVenkatraman S omap_hsmmc_reset_controller_fsm(host, SRD); 1014ae4bf788SVenkatraman S omap_hsmmc_dma_cleanup(host, err); 1015dc7745bdSBalaji T K } else if (host->mrq && host->mrq->cmd) 1016dc7745bdSBalaji T K host->mrq->cmd->error = err; 1017ae4bf788SVenkatraman S } 1018ae4bf788SVenkatraman S 1019b417577dSAdrian Hunter static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1020a45c6cb8SMadhusudhan Chikkature { 1021a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 1022b417577dSAdrian Hunter int end_cmd = 0, end_trans = 0; 1023a45c6cb8SMadhusudhan Chikkature 1024a45c6cb8SMadhusudhan Chikkature data = host->data; 10258986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1026a45c6cb8SMadhusudhan Chikkature 1027a7e96879SVenkatraman S if (status & ERR_EN) { 1028699b958bSAdrian Hunter omap_hsmmc_dbg_report_irq(host, status); 10294a694dc9SAdrian Hunter 1030a7e96879SVenkatraman S if (status & (CTO_EN | CCRC_EN)) 1031a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1032a7e96879SVenkatraman S if (status & (CTO_EN | DTO_EN)) 103325e1897bSBalaji T K hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); 1034a7e96879SVenkatraman S else if (status & (CCRC_EN | DCRC_EN)) 103525e1897bSBalaji T K hsmmc_command_incomplete(host, -EILSEQ, end_cmd); 103625e1897bSBalaji T K 1037ae4bf788SVenkatraman S if (host->data || host->response_busy) { 103825e1897bSBalaji T K end_trans = !end_cmd; 1039ae4bf788SVenkatraman S host->response_busy = 0; 1040a45c6cb8SMadhusudhan Chikkature } 1041a45c6cb8SMadhusudhan Chikkature } 1042a45c6cb8SMadhusudhan Chikkature 10437472bab2SFrancesco Lavra OMAP_HSMMC_WRITE(host->base, STAT, status); 1044a7e96879SVenkatraman S if (end_cmd || ((status & CC_EN) && host->cmd)) 104570a3341aSDenis Karpov omap_hsmmc_cmd_done(host, host->cmd); 1046a7e96879SVenkatraman S if ((end_trans || (status & TC_EN)) && host->mrq) 104770a3341aSDenis Karpov omap_hsmmc_xfer_done(host, data); 1048b417577dSAdrian Hunter } 1049a45c6cb8SMadhusudhan Chikkature 1050b417577dSAdrian Hunter /* 1051b417577dSAdrian Hunter * MMC controller IRQ handler 1052b417577dSAdrian Hunter */ 1053b417577dSAdrian Hunter static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1054b417577dSAdrian Hunter { 1055b417577dSAdrian Hunter struct omap_hsmmc_host *host = dev_id; 1056b417577dSAdrian Hunter int status; 1057b417577dSAdrian Hunter 1058b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 10591f6b9fa4SVenkatraman S while (status & INT_EN_MASK && host->req_in_progress) { 1060b417577dSAdrian Hunter omap_hsmmc_do_irq(host, status); 10611f6b9fa4SVenkatraman S 1062b417577dSAdrian Hunter /* Flush posted write */ 1063b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 10641f6b9fa4SVenkatraman S } 10654dffd7a2SAdrian Hunter 1066a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1067a45c6cb8SMadhusudhan Chikkature } 1068a45c6cb8SMadhusudhan Chikkature 106970a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host) 1070e13bb300SAdrian Hunter { 1071e13bb300SAdrian Hunter unsigned long i; 1072e13bb300SAdrian Hunter 1073e13bb300SAdrian Hunter OMAP_HSMMC_WRITE(host->base, HCTL, 1074e13bb300SAdrian Hunter OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1075e13bb300SAdrian Hunter for (i = 0; i < loops_per_jiffy; i++) { 1076e13bb300SAdrian Hunter if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1077e13bb300SAdrian Hunter break; 1078e13bb300SAdrian Hunter cpu_relax(); 1079e13bb300SAdrian Hunter } 1080e13bb300SAdrian Hunter } 1081e13bb300SAdrian Hunter 1082a45c6cb8SMadhusudhan Chikkature /* 1083eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 1084eb250826SDavid Brownell * 1085eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1086eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1087eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 1088a45c6cb8SMadhusudhan Chikkature */ 108970a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1090a45c6cb8SMadhusudhan Chikkature { 1091a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 1092a45c6cb8SMadhusudhan Chikkature int ret; 1093a45c6cb8SMadhusudhan Chikkature 1094a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 1095fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 1096cd03d9a8SRajendra Nayak if (host->dbclk) 109794c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 1098a45c6cb8SMadhusudhan Chikkature 1099a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 1100a45c6cb8SMadhusudhan Chikkature ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 1101a45c6cb8SMadhusudhan Chikkature 1102a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 11032bec0893SAdrian Hunter if (!ret) 11042bec0893SAdrian Hunter ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, 11052bec0893SAdrian Hunter vdd); 1106fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1107cd03d9a8SRajendra Nayak if (host->dbclk) 110894c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 11092bec0893SAdrian Hunter 1110a45c6cb8SMadhusudhan Chikkature if (ret != 0) 1111a45c6cb8SMadhusudhan Chikkature goto err; 1112a45c6cb8SMadhusudhan Chikkature 1113a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1114a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1115a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1116eb250826SDavid Brownell 1117a45c6cb8SMadhusudhan Chikkature /* 1118a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 1119a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 112070a3341aSDenis Karpov * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1121a45c6cb8SMadhusudhan Chikkature * 1122eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 1123eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1124eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 1125eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1126eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 1127eb250826SDavid Brownell * 1128eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 1129eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1130eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1131a45c6cb8SMadhusudhan Chikkature */ 1132eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 1133a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 1134eb250826SDavid Brownell else 1135eb250826SDavid Brownell reg_val |= SDVS30; 1136a45c6cb8SMadhusudhan Chikkature 1137a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1138e13bb300SAdrian Hunter set_sd_bus_power(host); 1139a45c6cb8SMadhusudhan Chikkature 1140a45c6cb8SMadhusudhan Chikkature return 0; 1141a45c6cb8SMadhusudhan Chikkature err: 1142b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1143a45c6cb8SMadhusudhan Chikkature return ret; 1144a45c6cb8SMadhusudhan Chikkature } 1145a45c6cb8SMadhusudhan Chikkature 1146b62f6228SAdrian Hunter /* Protect the card while the cover is open */ 1147b62f6228SAdrian Hunter static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1148b62f6228SAdrian Hunter { 1149b62f6228SAdrian Hunter if (!mmc_slot(host).get_cover_state) 1150b62f6228SAdrian Hunter return; 1151b62f6228SAdrian Hunter 1152b62f6228SAdrian Hunter host->reqs_blocked = 0; 1153b62f6228SAdrian Hunter if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) { 1154b62f6228SAdrian Hunter if (host->protect_card) { 11552cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is closed, " 1156b62f6228SAdrian Hunter "card is now accessible\n", 1157b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1158b62f6228SAdrian Hunter host->protect_card = 0; 1159b62f6228SAdrian Hunter } 1160b62f6228SAdrian Hunter } else { 1161b62f6228SAdrian Hunter if (!host->protect_card) { 11622cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is open, " 1163b62f6228SAdrian Hunter "card is now inaccessible\n", 1164b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1165b62f6228SAdrian Hunter host->protect_card = 1; 1166b62f6228SAdrian Hunter } 1167b62f6228SAdrian Hunter } 1168b62f6228SAdrian Hunter } 1169b62f6228SAdrian Hunter 1170a45c6cb8SMadhusudhan Chikkature /* 11717efab4f3SNeilBrown * irq handler to notify the core about card insertion/removal 1172a45c6cb8SMadhusudhan Chikkature */ 11737efab4f3SNeilBrown static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id) 1174a45c6cb8SMadhusudhan Chikkature { 11757efab4f3SNeilBrown struct omap_hsmmc_host *host = dev_id; 1176249d0fa9SDavid Brownell struct omap_mmc_slot_data *slot = &mmc_slot(host); 1177a6b2240dSAdrian Hunter int carddetect; 1178249d0fa9SDavid Brownell 1179a45c6cb8SMadhusudhan Chikkature sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1180a6b2240dSAdrian Hunter 1181191d1f1dSDenis Karpov if (slot->card_detect) 1182db0fefc5SAdrian Hunter carddetect = slot->card_detect(host->dev, host->slot_id); 1183b62f6228SAdrian Hunter else { 1184b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 1185a6b2240dSAdrian Hunter carddetect = -ENOSYS; 1186b62f6228SAdrian Hunter } 1187a6b2240dSAdrian Hunter 1188cdeebaddSMadhusudhan Chikkature if (carddetect) 1189a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1190cdeebaddSMadhusudhan Chikkature else 1191a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 50) / 1000); 1192a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1193a45c6cb8SMadhusudhan Chikkature } 1194a45c6cb8SMadhusudhan Chikkature 1195c5c98927SRussell King static void omap_hsmmc_dma_callback(void *param) 11960ccd76d4SJuha Yrjola { 1197c5c98927SRussell King struct omap_hsmmc_host *host = param; 1198c5c98927SRussell King struct dma_chan *chan; 1199770d7432SAdrian Hunter struct mmc_data *data; 1200c5c98927SRussell King int req_in_progress; 1201a45c6cb8SMadhusudhan Chikkature 1202c5c98927SRussell King spin_lock_irq(&host->irq_lock); 1203b417577dSAdrian Hunter if (host->dma_ch < 0) { 1204c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1205a45c6cb8SMadhusudhan Chikkature return; 1206b417577dSAdrian Hunter } 1207a45c6cb8SMadhusudhan Chikkature 1208770d7432SAdrian Hunter data = host->mrq->data; 1209c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 12109782aff8SPer Forlin if (!data->host_cookie) 1211c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1212c5c98927SRussell King data->sg, data->sg_len, 1213b417577dSAdrian Hunter omap_hsmmc_get_dma_dir(host, data)); 1214b417577dSAdrian Hunter 1215b417577dSAdrian Hunter req_in_progress = host->req_in_progress; 1216a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1217c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1218b417577dSAdrian Hunter 1219b417577dSAdrian Hunter /* If DMA has finished after TC, complete the request */ 1220b417577dSAdrian Hunter if (!req_in_progress) { 1221b417577dSAdrian Hunter struct mmc_request *mrq = host->mrq; 1222b417577dSAdrian Hunter 1223b417577dSAdrian Hunter host->mrq = NULL; 1224b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 1225b417577dSAdrian Hunter } 1226a45c6cb8SMadhusudhan Chikkature } 1227a45c6cb8SMadhusudhan Chikkature 12289782aff8SPer Forlin static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 12299782aff8SPer Forlin struct mmc_data *data, 1230c5c98927SRussell King struct omap_hsmmc_next *next, 123126b88520SRussell King struct dma_chan *chan) 12329782aff8SPer Forlin { 12339782aff8SPer Forlin int dma_len; 12349782aff8SPer Forlin 12359782aff8SPer Forlin if (!next && data->host_cookie && 12369782aff8SPer Forlin data->host_cookie != host->next_data.cookie) { 12372cecdf00SRajendra Nayak dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 12389782aff8SPer Forlin " host->next_data.cookie %d\n", 12399782aff8SPer Forlin __func__, data->host_cookie, host->next_data.cookie); 12409782aff8SPer Forlin data->host_cookie = 0; 12419782aff8SPer Forlin } 12429782aff8SPer Forlin 12439782aff8SPer Forlin /* Check if next job is already prepared */ 1244b38313d6SDan Carpenter if (next || data->host_cookie != host->next_data.cookie) { 124526b88520SRussell King dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 12469782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 12479782aff8SPer Forlin 12489782aff8SPer Forlin } else { 12499782aff8SPer Forlin dma_len = host->next_data.dma_len; 12509782aff8SPer Forlin host->next_data.dma_len = 0; 12519782aff8SPer Forlin } 12529782aff8SPer Forlin 12539782aff8SPer Forlin 12549782aff8SPer Forlin if (dma_len == 0) 12559782aff8SPer Forlin return -EINVAL; 12569782aff8SPer Forlin 12579782aff8SPer Forlin if (next) { 12589782aff8SPer Forlin next->dma_len = dma_len; 12599782aff8SPer Forlin data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 12609782aff8SPer Forlin } else 12619782aff8SPer Forlin host->dma_len = dma_len; 12629782aff8SPer Forlin 12639782aff8SPer Forlin return 0; 12649782aff8SPer Forlin } 12659782aff8SPer Forlin 1266a45c6cb8SMadhusudhan Chikkature /* 1267a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 1268a45c6cb8SMadhusudhan Chikkature */ 126970a3341aSDenis Karpov static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host, 127070a3341aSDenis Karpov struct mmc_request *req) 1271a45c6cb8SMadhusudhan Chikkature { 127226b88520SRussell King struct dma_slave_config cfg; 127326b88520SRussell King struct dma_async_tx_descriptor *tx; 127426b88520SRussell King int ret = 0, i; 1275a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 1276c5c98927SRussell King struct dma_chan *chan; 1277a45c6cb8SMadhusudhan Chikkature 12780ccd76d4SJuha Yrjola /* Sanity check: all the SG entries must be aligned by block size. */ 1279a3f406f8SJarkko Lavinen for (i = 0; i < data->sg_len; i++) { 12800ccd76d4SJuha Yrjola struct scatterlist *sgl; 12810ccd76d4SJuha Yrjola 12820ccd76d4SJuha Yrjola sgl = data->sg + i; 12830ccd76d4SJuha Yrjola if (sgl->length % data->blksz) 12840ccd76d4SJuha Yrjola return -EINVAL; 12850ccd76d4SJuha Yrjola } 12860ccd76d4SJuha Yrjola if ((data->blksz % 4) != 0) 12870ccd76d4SJuha Yrjola /* REVISIT: The MMC buffer increments only when MSB is written. 12880ccd76d4SJuha Yrjola * Return error for blksz which is non multiple of four. 12890ccd76d4SJuha Yrjola */ 12900ccd76d4SJuha Yrjola return -EINVAL; 12910ccd76d4SJuha Yrjola 1292b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1293a45c6cb8SMadhusudhan Chikkature 1294c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 1295c5c98927SRussell King 1296c5c98927SRussell King cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA; 1297c5c98927SRussell King cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA; 1298c5c98927SRussell King cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1299c5c98927SRussell King cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1300c5c98927SRussell King cfg.src_maxburst = data->blksz / 4; 1301c5c98927SRussell King cfg.dst_maxburst = data->blksz / 4; 1302c5c98927SRussell King 1303c5c98927SRussell King ret = dmaengine_slave_config(chan, &cfg); 13049782aff8SPer Forlin if (ret) 13059782aff8SPer Forlin return ret; 1306a45c6cb8SMadhusudhan Chikkature 130726b88520SRussell King ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1308c5c98927SRussell King if (ret) 1309c5c98927SRussell King return ret; 1310a45c6cb8SMadhusudhan Chikkature 1311c5c98927SRussell King tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1312c5c98927SRussell King data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1313c5c98927SRussell King DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1314c5c98927SRussell King if (!tx) { 1315c5c98927SRussell King dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1316c5c98927SRussell King /* FIXME: cleanup */ 1317c5c98927SRussell King return -1; 1318c5c98927SRussell King } 1319c5c98927SRussell King 1320c5c98927SRussell King tx->callback = omap_hsmmc_dma_callback; 1321c5c98927SRussell King tx->callback_param = host; 1322c5c98927SRussell King 1323c5c98927SRussell King /* Does not fail */ 1324c5c98927SRussell King dmaengine_submit(tx); 1325c5c98927SRussell King 132626b88520SRussell King host->dma_ch = 1; 1327c5c98927SRussell King 1328c5c98927SRussell King dma_async_issue_pending(chan); 1329a45c6cb8SMadhusudhan Chikkature 1330a45c6cb8SMadhusudhan Chikkature return 0; 1331a45c6cb8SMadhusudhan Chikkature } 1332a45c6cb8SMadhusudhan Chikkature 133370a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host, 1334e2bf08d6SAdrian Hunter unsigned int timeout_ns, 1335e2bf08d6SAdrian Hunter unsigned int timeout_clks) 1336a45c6cb8SMadhusudhan Chikkature { 1337a45c6cb8SMadhusudhan Chikkature unsigned int timeout, cycle_ns; 1338a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 1339a45c6cb8SMadhusudhan Chikkature 1340a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1341a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1342a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 1343a45c6cb8SMadhusudhan Chikkature clkd = 1; 1344a45c6cb8SMadhusudhan Chikkature 1345a45c6cb8SMadhusudhan Chikkature cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); 1346e2bf08d6SAdrian Hunter timeout = timeout_ns / cycle_ns; 1347e2bf08d6SAdrian Hunter timeout += timeout_clks; 1348a45c6cb8SMadhusudhan Chikkature if (timeout) { 1349a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 1350a45c6cb8SMadhusudhan Chikkature dto += 1; 1351a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1352a45c6cb8SMadhusudhan Chikkature } 1353a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 1354a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1355a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 1356a45c6cb8SMadhusudhan Chikkature dto += 1; 1357a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 1358a45c6cb8SMadhusudhan Chikkature dto -= 13; 1359a45c6cb8SMadhusudhan Chikkature else 1360a45c6cb8SMadhusudhan Chikkature dto = 0; 1361a45c6cb8SMadhusudhan Chikkature if (dto > 14) 1362a45c6cb8SMadhusudhan Chikkature dto = 14; 1363a45c6cb8SMadhusudhan Chikkature } 1364a45c6cb8SMadhusudhan Chikkature 1365a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 1366a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 1367a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1368a45c6cb8SMadhusudhan Chikkature } 1369a45c6cb8SMadhusudhan Chikkature 1370a45c6cb8SMadhusudhan Chikkature /* 1371a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 1372a45c6cb8SMadhusudhan Chikkature */ 1373a45c6cb8SMadhusudhan Chikkature static int 137470a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1375a45c6cb8SMadhusudhan Chikkature { 1376a45c6cb8SMadhusudhan Chikkature int ret; 1377a45c6cb8SMadhusudhan Chikkature host->data = req->data; 1378a45c6cb8SMadhusudhan Chikkature 1379a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 1380a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 1381e2bf08d6SAdrian Hunter /* 1382e2bf08d6SAdrian Hunter * Set an arbitrary 100ms data timeout for commands with 1383e2bf08d6SAdrian Hunter * busy signal. 1384e2bf08d6SAdrian Hunter */ 1385e2bf08d6SAdrian Hunter if (req->cmd->flags & MMC_RSP_BUSY) 1386e2bf08d6SAdrian Hunter set_data_timeout(host, 100000000U, 0); 1387a45c6cb8SMadhusudhan Chikkature return 0; 1388a45c6cb8SMadhusudhan Chikkature } 1389a45c6cb8SMadhusudhan Chikkature 1390a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 1391a45c6cb8SMadhusudhan Chikkature | (req->data->blocks << 16)); 1392e2bf08d6SAdrian Hunter set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks); 1393a45c6cb8SMadhusudhan Chikkature 1394a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 139570a3341aSDenis Karpov ret = omap_hsmmc_start_dma_transfer(host, req); 1396a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 1397b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); 1398a45c6cb8SMadhusudhan Chikkature return ret; 1399a45c6cb8SMadhusudhan Chikkature } 1400a45c6cb8SMadhusudhan Chikkature } 1401a45c6cb8SMadhusudhan Chikkature return 0; 1402a45c6cb8SMadhusudhan Chikkature } 1403a45c6cb8SMadhusudhan Chikkature 14049782aff8SPer Forlin static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 14059782aff8SPer Forlin int err) 14069782aff8SPer Forlin { 14079782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 14089782aff8SPer Forlin struct mmc_data *data = mrq->data; 14099782aff8SPer Forlin 141026b88520SRussell King if (host->use_dma && data->host_cookie) { 1411c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1412c5c98927SRussell King 141326b88520SRussell King dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 14149782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 14159782aff8SPer Forlin data->host_cookie = 0; 14169782aff8SPer Forlin } 14179782aff8SPer Forlin } 14189782aff8SPer Forlin 14199782aff8SPer Forlin static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 14209782aff8SPer Forlin bool is_first_req) 14219782aff8SPer Forlin { 14229782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 14239782aff8SPer Forlin 14249782aff8SPer Forlin if (mrq->data->host_cookie) { 14259782aff8SPer Forlin mrq->data->host_cookie = 0; 14269782aff8SPer Forlin return ; 14279782aff8SPer Forlin } 14289782aff8SPer Forlin 1429c5c98927SRussell King if (host->use_dma) { 1430c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1431c5c98927SRussell King 14329782aff8SPer Forlin if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 143326b88520SRussell King &host->next_data, c)) 14349782aff8SPer Forlin mrq->data->host_cookie = 0; 14359782aff8SPer Forlin } 1436c5c98927SRussell King } 14379782aff8SPer Forlin 1438a45c6cb8SMadhusudhan Chikkature /* 1439a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 1440a45c6cb8SMadhusudhan Chikkature */ 144170a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1442a45c6cb8SMadhusudhan Chikkature { 144370a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1444a3f406f8SJarkko Lavinen int err; 1445a45c6cb8SMadhusudhan Chikkature 1446b417577dSAdrian Hunter BUG_ON(host->req_in_progress); 1447b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1448b62f6228SAdrian Hunter if (host->protect_card) { 1449b62f6228SAdrian Hunter if (host->reqs_blocked < 3) { 1450b62f6228SAdrian Hunter /* 1451b62f6228SAdrian Hunter * Ensure the controller is left in a consistent 1452b62f6228SAdrian Hunter * state by resetting the command and data state 1453b62f6228SAdrian Hunter * machines. 1454b62f6228SAdrian Hunter */ 1455b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRD); 1456b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRC); 1457b62f6228SAdrian Hunter host->reqs_blocked += 1; 1458b62f6228SAdrian Hunter } 1459b62f6228SAdrian Hunter req->cmd->error = -EBADF; 1460b62f6228SAdrian Hunter if (req->data) 1461b62f6228SAdrian Hunter req->data->error = -EBADF; 1462b417577dSAdrian Hunter req->cmd->retries = 0; 1463b62f6228SAdrian Hunter mmc_request_done(mmc, req); 1464b62f6228SAdrian Hunter return; 1465b62f6228SAdrian Hunter } else if (host->reqs_blocked) 1466b62f6228SAdrian Hunter host->reqs_blocked = 0; 1467a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 1468a45c6cb8SMadhusudhan Chikkature host->mrq = req; 146970a3341aSDenis Karpov err = omap_hsmmc_prepare_data(host, req); 1470a3f406f8SJarkko Lavinen if (err) { 1471a3f406f8SJarkko Lavinen req->cmd->error = err; 1472a3f406f8SJarkko Lavinen if (req->data) 1473a3f406f8SJarkko Lavinen req->data->error = err; 1474a3f406f8SJarkko Lavinen host->mrq = NULL; 1475a3f406f8SJarkko Lavinen mmc_request_done(mmc, req); 1476a3f406f8SJarkko Lavinen return; 1477a3f406f8SJarkko Lavinen } 1478a3f406f8SJarkko Lavinen 147970a3341aSDenis Karpov omap_hsmmc_start_command(host, req->cmd, req->data); 1480a45c6cb8SMadhusudhan Chikkature } 1481a45c6cb8SMadhusudhan Chikkature 1482a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 148370a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1484a45c6cb8SMadhusudhan Chikkature { 148570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1486a3621465SAdrian Hunter int do_send_init_stream = 0; 1487a45c6cb8SMadhusudhan Chikkature 1488fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 14895e2ea617SAdrian Hunter 1490a3621465SAdrian Hunter if (ios->power_mode != host->power_mode) { 1491a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 1492a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 1493a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1494a3621465SAdrian Hunter 0, 0); 1495a45c6cb8SMadhusudhan Chikkature break; 1496a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 1497a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1498a3621465SAdrian Hunter 1, ios->vdd); 1499a45c6cb8SMadhusudhan Chikkature break; 1500a3621465SAdrian Hunter case MMC_POWER_ON: 1501a3621465SAdrian Hunter do_send_init_stream = 1; 1502a3621465SAdrian Hunter break; 1503a3621465SAdrian Hunter } 1504a3621465SAdrian Hunter host->power_mode = ios->power_mode; 1505a45c6cb8SMadhusudhan Chikkature } 1506a45c6cb8SMadhusudhan Chikkature 1507dd498effSDenis Karpov /* FIXME: set registers based only on changes to ios */ 1508dd498effSDenis Karpov 15093796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 1510a45c6cb8SMadhusudhan Chikkature 15114621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1512eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 1513eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 1514eb250826SDavid Brownell */ 1515a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 15161f84b71bSRajendra Nayak (ios->vdd == DUAL_VOLT_OCR_BIT) && 15171f84b71bSRajendra Nayak /* 15181f84b71bSRajendra Nayak * With pbias cell programming missing, this 1519cf5ae40bSTony Lindgren * can't be allowed on MMC1 when booting with device 15201f84b71bSRajendra Nayak * tree. 15211f84b71bSRajendra Nayak */ 1522cf5ae40bSTony Lindgren !host->pbias_disable) { 1523a45c6cb8SMadhusudhan Chikkature /* 1524a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 1525a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 1526a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 1527a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 1528a45c6cb8SMadhusudhan Chikkature */ 152970a3341aSDenis Karpov if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1530a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1531a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 1532a45c6cb8SMadhusudhan Chikkature } 1533a45c6cb8SMadhusudhan Chikkature } 1534a45c6cb8SMadhusudhan Chikkature 15355934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 1536a45c6cb8SMadhusudhan Chikkature 1537a3621465SAdrian Hunter if (do_send_init_stream) 1538a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 1539a45c6cb8SMadhusudhan Chikkature 15403796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 15415e2ea617SAdrian Hunter 1542fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1543a45c6cb8SMadhusudhan Chikkature } 1544a45c6cb8SMadhusudhan Chikkature 1545a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1546a45c6cb8SMadhusudhan Chikkature { 154770a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1548a45c6cb8SMadhusudhan Chikkature 1549191d1f1dSDenis Karpov if (!mmc_slot(host).card_detect) 1550a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1551db0fefc5SAdrian Hunter return mmc_slot(host).card_detect(host->dev, host->slot_id); 1552a45c6cb8SMadhusudhan Chikkature } 1553a45c6cb8SMadhusudhan Chikkature 1554a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_ro(struct mmc_host *mmc) 1555a45c6cb8SMadhusudhan Chikkature { 155670a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1557a45c6cb8SMadhusudhan Chikkature 1558191d1f1dSDenis Karpov if (!mmc_slot(host).get_ro) 1559a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1560191d1f1dSDenis Karpov return mmc_slot(host).get_ro(host->dev, 0); 1561a45c6cb8SMadhusudhan Chikkature } 1562a45c6cb8SMadhusudhan Chikkature 15634816858cSGrazvydas Ignotas static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 15644816858cSGrazvydas Ignotas { 15654816858cSGrazvydas Ignotas struct omap_hsmmc_host *host = mmc_priv(mmc); 15664816858cSGrazvydas Ignotas 15674816858cSGrazvydas Ignotas if (mmc_slot(host).init_card) 15684816858cSGrazvydas Ignotas mmc_slot(host).init_card(card); 15694816858cSGrazvydas Ignotas } 15704816858cSGrazvydas Ignotas 157170a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 15721b331e69SKim Kyuwon { 15731b331e69SKim Kyuwon u32 hctl, capa, value; 15741b331e69SKim Kyuwon 15751b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 15764621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 15771b331e69SKim Kyuwon hctl = SDVS30; 15781b331e69SKim Kyuwon capa = VS30 | VS18; 15791b331e69SKim Kyuwon } else { 15801b331e69SKim Kyuwon hctl = SDVS18; 15811b331e69SKim Kyuwon capa = VS18; 15821b331e69SKim Kyuwon } 15831b331e69SKim Kyuwon 15841b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 15851b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 15861b331e69SKim Kyuwon 15871b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 15881b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 15891b331e69SKim Kyuwon 15901b331e69SKim Kyuwon /* Set SD bus power bit */ 1591e13bb300SAdrian Hunter set_sd_bus_power(host); 15921b331e69SKim Kyuwon } 15931b331e69SKim Kyuwon 159470a3341aSDenis Karpov static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) 1595dd498effSDenis Karpov { 159670a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1597dd498effSDenis Karpov 1598fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1599fa4aa2d4SBalaji T K 1600dd498effSDenis Karpov return 0; 1601dd498effSDenis Karpov } 1602dd498effSDenis Karpov 1603907d2e7cSAdrian Hunter static int omap_hsmmc_disable_fclk(struct mmc_host *mmc) 1604dd498effSDenis Karpov { 160570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1606dd498effSDenis Karpov 1607fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1608fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1609fa4aa2d4SBalaji T K 1610dd498effSDenis Karpov return 0; 1611dd498effSDenis Karpov } 1612dd498effSDenis Karpov 161370a3341aSDenis Karpov static const struct mmc_host_ops omap_hsmmc_ops = { 161470a3341aSDenis Karpov .enable = omap_hsmmc_enable_fclk, 161570a3341aSDenis Karpov .disable = omap_hsmmc_disable_fclk, 16169782aff8SPer Forlin .post_req = omap_hsmmc_post_req, 16179782aff8SPer Forlin .pre_req = omap_hsmmc_pre_req, 161870a3341aSDenis Karpov .request = omap_hsmmc_request, 161970a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1620dd498effSDenis Karpov .get_cd = omap_hsmmc_get_cd, 1621dd498effSDenis Karpov .get_ro = omap_hsmmc_get_ro, 16224816858cSGrazvydas Ignotas .init_card = omap_hsmmc_init_card, 1623dd498effSDenis Karpov /* NYET -- enable_sdio_irq */ 1624dd498effSDenis Karpov }; 1625dd498effSDenis Karpov 1626d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS 1627d900f712SDenis Karpov 162870a3341aSDenis Karpov static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1629d900f712SDenis Karpov { 1630d900f712SDenis Karpov struct mmc_host *mmc = s->private; 163170a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 163211dd62a7SDenis Karpov 16330a82e06eSTony Lindgren seq_printf(s, "mmc%d:\n ctx_loss:\t%d\n\nregs:\n", 16340a82e06eSTony Lindgren mmc->index, host->context_loss); 16355e2ea617SAdrian Hunter 1636fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1637d900f712SDenis Karpov 1638d900f712SDenis Karpov seq_printf(s, "CON:\t\t0x%08x\n", 1639d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CON)); 1640d900f712SDenis Karpov seq_printf(s, "HCTL:\t\t0x%08x\n", 1641d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL)); 1642d900f712SDenis Karpov seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1643d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL)); 1644d900f712SDenis Karpov seq_printf(s, "IE:\t\t0x%08x\n", 1645d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, IE)); 1646d900f712SDenis Karpov seq_printf(s, "ISE:\t\t0x%08x\n", 1647d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, ISE)); 1648d900f712SDenis Karpov seq_printf(s, "CAPA:\t\t0x%08x\n", 1649d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA)); 16505e2ea617SAdrian Hunter 1651fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1652fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1653dd498effSDenis Karpov 1654d900f712SDenis Karpov return 0; 1655d900f712SDenis Karpov } 1656d900f712SDenis Karpov 165770a3341aSDenis Karpov static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1658d900f712SDenis Karpov { 165970a3341aSDenis Karpov return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1660d900f712SDenis Karpov } 1661d900f712SDenis Karpov 1662d900f712SDenis Karpov static const struct file_operations mmc_regs_fops = { 166370a3341aSDenis Karpov .open = omap_hsmmc_regs_open, 1664d900f712SDenis Karpov .read = seq_read, 1665d900f712SDenis Karpov .llseek = seq_lseek, 1666d900f712SDenis Karpov .release = single_release, 1667d900f712SDenis Karpov }; 1668d900f712SDenis Karpov 166970a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1670d900f712SDenis Karpov { 1671d900f712SDenis Karpov if (mmc->debugfs_root) 1672d900f712SDenis Karpov debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1673d900f712SDenis Karpov mmc, &mmc_regs_fops); 1674d900f712SDenis Karpov } 1675d900f712SDenis Karpov 1676d900f712SDenis Karpov #else 1677d900f712SDenis Karpov 167870a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1679d900f712SDenis Karpov { 1680d900f712SDenis Karpov } 1681d900f712SDenis Karpov 1682d900f712SDenis Karpov #endif 1683d900f712SDenis Karpov 168446856a68SRajendra Nayak #ifdef CONFIG_OF 168559445b10SNishanth Menon static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = { 168659445b10SNishanth Menon /* See 35xx errata 2.1.1.128 in SPRZ278F */ 168759445b10SNishanth Menon .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 168859445b10SNishanth Menon }; 168959445b10SNishanth Menon 169059445b10SNishanth Menon static const struct omap_mmc_of_data omap4_mmc_of_data = { 169159445b10SNishanth Menon .reg_offset = 0x100, 169259445b10SNishanth Menon }; 169346856a68SRajendra Nayak 169446856a68SRajendra Nayak static const struct of_device_id omap_mmc_of_match[] = { 169546856a68SRajendra Nayak { 169646856a68SRajendra Nayak .compatible = "ti,omap2-hsmmc", 169746856a68SRajendra Nayak }, 169846856a68SRajendra Nayak { 169959445b10SNishanth Menon .compatible = "ti,omap3-pre-es3-hsmmc", 170059445b10SNishanth Menon .data = &omap3_pre_es3_mmc_of_data, 170159445b10SNishanth Menon }, 170259445b10SNishanth Menon { 170346856a68SRajendra Nayak .compatible = "ti,omap3-hsmmc", 170446856a68SRajendra Nayak }, 170546856a68SRajendra Nayak { 170646856a68SRajendra Nayak .compatible = "ti,omap4-hsmmc", 170759445b10SNishanth Menon .data = &omap4_mmc_of_data, 170846856a68SRajendra Nayak }, 170946856a68SRajendra Nayak {}, 1710b6d085f6SChris Ball }; 171146856a68SRajendra Nayak MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 171246856a68SRajendra Nayak 171346856a68SRajendra Nayak static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 171446856a68SRajendra Nayak { 171546856a68SRajendra Nayak struct omap_mmc_platform_data *pdata; 171646856a68SRajendra Nayak struct device_node *np = dev->of_node; 1717d8714e87SDaniel Mack u32 bus_width, max_freq; 1718dc642c28SJan Luebbe int cd_gpio, wp_gpio; 1719dc642c28SJan Luebbe 1720dc642c28SJan Luebbe cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); 1721dc642c28SJan Luebbe wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 1722dc642c28SJan Luebbe if (cd_gpio == -EPROBE_DEFER || wp_gpio == -EPROBE_DEFER) 1723dc642c28SJan Luebbe return ERR_PTR(-EPROBE_DEFER); 172446856a68SRajendra Nayak 172546856a68SRajendra Nayak pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 172646856a68SRajendra Nayak if (!pdata) 172746856a68SRajendra Nayak return NULL; /* out of memory */ 172846856a68SRajendra Nayak 172946856a68SRajendra Nayak if (of_find_property(np, "ti,dual-volt", NULL)) 173046856a68SRajendra Nayak pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 173146856a68SRajendra Nayak 173246856a68SRajendra Nayak /* This driver only supports 1 slot */ 173346856a68SRajendra Nayak pdata->nr_slots = 1; 1734dc642c28SJan Luebbe pdata->slots[0].switch_pin = cd_gpio; 1735dc642c28SJan Luebbe pdata->slots[0].gpio_wp = wp_gpio; 173646856a68SRajendra Nayak 173746856a68SRajendra Nayak if (of_find_property(np, "ti,non-removable", NULL)) { 173846856a68SRajendra Nayak pdata->slots[0].nonremovable = true; 173946856a68SRajendra Nayak pdata->slots[0].no_regulator_off_init = true; 174046856a68SRajendra Nayak } 17417f217794SArnd Bergmann of_property_read_u32(np, "bus-width", &bus_width); 174246856a68SRajendra Nayak if (bus_width == 4) 174346856a68SRajendra Nayak pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA; 174446856a68SRajendra Nayak else if (bus_width == 8) 174546856a68SRajendra Nayak pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA; 174646856a68SRajendra Nayak 174746856a68SRajendra Nayak if (of_find_property(np, "ti,needs-special-reset", NULL)) 174846856a68SRajendra Nayak pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET; 174946856a68SRajendra Nayak 1750d8714e87SDaniel Mack if (!of_property_read_u32(np, "max-frequency", &max_freq)) 1751d8714e87SDaniel Mack pdata->max_freq = max_freq; 1752d8714e87SDaniel Mack 1753cd587096SHebbar, Gururaja if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) 1754cd587096SHebbar, Gururaja pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT; 1755cd587096SHebbar, Gururaja 175646856a68SRajendra Nayak return pdata; 175746856a68SRajendra Nayak } 175846856a68SRajendra Nayak #else 175946856a68SRajendra Nayak static inline struct omap_mmc_platform_data 176046856a68SRajendra Nayak *of_get_hsmmc_pdata(struct device *dev) 176146856a68SRajendra Nayak { 176246856a68SRajendra Nayak return NULL; 176346856a68SRajendra Nayak } 176446856a68SRajendra Nayak #endif 176546856a68SRajendra Nayak 1766c3be1efdSBill Pemberton static int omap_hsmmc_probe(struct platform_device *pdev) 1767a45c6cb8SMadhusudhan Chikkature { 1768a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 1769a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 177070a3341aSDenis Karpov struct omap_hsmmc_host *host = NULL; 1771a45c6cb8SMadhusudhan Chikkature struct resource *res; 1772db0fefc5SAdrian Hunter int ret, irq; 177346856a68SRajendra Nayak const struct of_device_id *match; 177426b88520SRussell King dma_cap_mask_t mask; 177526b88520SRussell King unsigned tx_req, rx_req; 177646b76035SDaniel Mack struct pinctrl *pinctrl; 177759445b10SNishanth Menon const struct omap_mmc_of_data *data; 177846856a68SRajendra Nayak 177946856a68SRajendra Nayak match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 178046856a68SRajendra Nayak if (match) { 178146856a68SRajendra Nayak pdata = of_get_hsmmc_pdata(&pdev->dev); 1782dc642c28SJan Luebbe 1783dc642c28SJan Luebbe if (IS_ERR(pdata)) 1784dc642c28SJan Luebbe return PTR_ERR(pdata); 1785dc642c28SJan Luebbe 178646856a68SRajendra Nayak if (match->data) { 178759445b10SNishanth Menon data = match->data; 178859445b10SNishanth Menon pdata->reg_offset = data->reg_offset; 178959445b10SNishanth Menon pdata->controller_flags |= data->controller_flags; 179046856a68SRajendra Nayak } 179146856a68SRajendra Nayak } 1792a45c6cb8SMadhusudhan Chikkature 1793a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 1794a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 1795a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1796a45c6cb8SMadhusudhan Chikkature } 1797a45c6cb8SMadhusudhan Chikkature 1798a45c6cb8SMadhusudhan Chikkature if (pdata->nr_slots == 0) { 1799a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "No Slots\n"); 1800a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1801a45c6cb8SMadhusudhan Chikkature } 1802a45c6cb8SMadhusudhan Chikkature 1803a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1804a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 1805a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 1806a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1807a45c6cb8SMadhusudhan Chikkature 1808984b203aSChris Ball res = request_mem_region(res->start, resource_size(res), pdev->name); 1809a45c6cb8SMadhusudhan Chikkature if (res == NULL) 1810a45c6cb8SMadhusudhan Chikkature return -EBUSY; 1811a45c6cb8SMadhusudhan Chikkature 1812db0fefc5SAdrian Hunter ret = omap_hsmmc_gpio_init(pdata); 1813db0fefc5SAdrian Hunter if (ret) 1814db0fefc5SAdrian Hunter goto err; 1815db0fefc5SAdrian Hunter 181670a3341aSDenis Karpov mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 1817a45c6cb8SMadhusudhan Chikkature if (!mmc) { 1818a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 1819db0fefc5SAdrian Hunter goto err_alloc; 1820a45c6cb8SMadhusudhan Chikkature } 1821a45c6cb8SMadhusudhan Chikkature 1822a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 1823a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 1824a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 1825a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 1826a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 1827a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1828a45c6cb8SMadhusudhan Chikkature host->irq = irq; 1829a45c6cb8SMadhusudhan Chikkature host->slot_id = 0; 1830fc307df8SBalaji T K host->mapbase = res->start + pdata->reg_offset; 1831a45c6cb8SMadhusudhan Chikkature host->base = ioremap(host->mapbase, SZ_4K); 18326da20c89SAdrian Hunter host->power_mode = MMC_POWER_OFF; 18339782aff8SPer Forlin host->next_data.cookie = 1; 1834a45c6cb8SMadhusudhan Chikkature 1835a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 1836a45c6cb8SMadhusudhan Chikkature 183770a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ops; 1838dd498effSDenis Karpov 18396b206efeSAndy Shevchenko mmc->f_min = OMAP_MMC_MIN_CLOCK; 1840d418ed87SDaniel Mack 1841d418ed87SDaniel Mack if (pdata->max_freq > 0) 1842d418ed87SDaniel Mack mmc->f_max = pdata->max_freq; 1843d418ed87SDaniel Mack else 18446b206efeSAndy Shevchenko mmc->f_max = OMAP_MMC_MAX_CLOCK; 1845a45c6cb8SMadhusudhan Chikkature 18464dffd7a2SAdrian Hunter spin_lock_init(&host->irq_lock); 1847a45c6cb8SMadhusudhan Chikkature 18486f7607ccSRussell King host->fclk = clk_get(&pdev->dev, "fck"); 1849a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 1850a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 1851a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 1852a45c6cb8SMadhusudhan Chikkature goto err1; 1853a45c6cb8SMadhusudhan Chikkature } 1854a45c6cb8SMadhusudhan Chikkature 18559b68256cSPaul Walmsley if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 18569b68256cSPaul Walmsley dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 18579b68256cSPaul Walmsley mmc->caps2 |= MMC_CAP2_NO_MULTI_READ; 18589b68256cSPaul Walmsley } 1859dd498effSDenis Karpov 1860fa4aa2d4SBalaji T K pm_runtime_enable(host->dev); 1861fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1862fa4aa2d4SBalaji T K pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 1863fa4aa2d4SBalaji T K pm_runtime_use_autosuspend(host->dev); 1864a45c6cb8SMadhusudhan Chikkature 186592a3aebfSBalaji T K omap_hsmmc_context_save(host); 186692a3aebfSBalaji T K 1867cf5ae40bSTony Lindgren /* This can be removed once we support PBIAS with DT */ 1868e002264fSBalaji T K if (host->dev->of_node && res->start == 0x4809c000) 1869cf5ae40bSTony Lindgren host->pbias_disable = 1; 1870cf5ae40bSTony Lindgren 1871a45c6cb8SMadhusudhan Chikkature host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); 1872a45c6cb8SMadhusudhan Chikkature /* 1873a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 1874a45c6cb8SMadhusudhan Chikkature */ 1875cd03d9a8SRajendra Nayak if (IS_ERR(host->dbclk)) { 1876cd03d9a8SRajendra Nayak host->dbclk = NULL; 187794c18149SRajendra Nayak } else if (clk_prepare_enable(host->dbclk) != 0) { 1878cd03d9a8SRajendra Nayak dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 1879cd03d9a8SRajendra Nayak clk_put(host->dbclk); 1880cd03d9a8SRajendra Nayak host->dbclk = NULL; 18812bec0893SAdrian Hunter } 1882a45c6cb8SMadhusudhan Chikkature 18830ccd76d4SJuha Yrjola /* Since we do only SG emulation, we can have as many segs 18840ccd76d4SJuha Yrjola * as we want. */ 1885a36274e0SMartin K. Petersen mmc->max_segs = 1024; 18860ccd76d4SJuha Yrjola 1887a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 1888a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 1889a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1890a45c6cb8SMadhusudhan Chikkature mmc->max_seg_size = mmc->max_req_size; 1891a45c6cb8SMadhusudhan Chikkature 189213189e78SJarkko Lavinen mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 189393caf8e6SAdrian Hunter MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 1894a45c6cb8SMadhusudhan Chikkature 18953a63833eSSukumar Ghorai mmc->caps |= mmc_slot(host).caps; 18963a63833eSSukumar Ghorai if (mmc->caps & MMC_CAP_8_BIT_DATA) 1897a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 1898a45c6cb8SMadhusudhan Chikkature 1899191d1f1dSDenis Karpov if (mmc_slot(host).nonremovable) 190023d99bb9SAdrian Hunter mmc->caps |= MMC_CAP_NONREMOVABLE; 190123d99bb9SAdrian Hunter 19026fdc75deSEliad Peller mmc->pm_caps = mmc_slot(host).pm_caps; 19036fdc75deSEliad Peller 190470a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 1905a45c6cb8SMadhusudhan Chikkature 19064a29b559SSantosh Shilimkar if (!pdev->dev.of_node) { 1907b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 1908b7bf773bSBalaji T K if (!res) { 1909b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n"); 19109c17d08cSKevin Hilman ret = -ENXIO; 1911f3e2f1ddSGrazvydas Ignotas goto err_irq; 1912a45c6cb8SMadhusudhan Chikkature } 191326b88520SRussell King tx_req = res->start; 1914b7bf773bSBalaji T K 1915b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 1916b7bf773bSBalaji T K if (!res) { 1917b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n"); 19189c17d08cSKevin Hilman ret = -ENXIO; 1919b7bf773bSBalaji T K goto err_irq; 1920b7bf773bSBalaji T K } 192126b88520SRussell King rx_req = res->start; 19224a29b559SSantosh Shilimkar } 1923c5c98927SRussell King 1924c5c98927SRussell King dma_cap_zero(mask); 1925c5c98927SRussell King dma_cap_set(DMA_SLAVE, mask); 192626b88520SRussell King 1927d272fbf0SMatt Porter host->rx_chan = 1928d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 1929d272fbf0SMatt Porter &rx_req, &pdev->dev, "rx"); 1930d272fbf0SMatt Porter 1931c5c98927SRussell King if (!host->rx_chan) { 193226b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req); 193304e8c7bcSKevin Hilman ret = -ENXIO; 193426b88520SRussell King goto err_irq; 1935c5c98927SRussell King } 193626b88520SRussell King 1937d272fbf0SMatt Porter host->tx_chan = 1938d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 1939d272fbf0SMatt Porter &tx_req, &pdev->dev, "tx"); 1940d272fbf0SMatt Porter 1941c5c98927SRussell King if (!host->tx_chan) { 194226b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req); 194304e8c7bcSKevin Hilman ret = -ENXIO; 194426b88520SRussell King goto err_irq; 1945c5c98927SRussell King } 1946a45c6cb8SMadhusudhan Chikkature 1947a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 1948d9618e9fSYong Zhang ret = request_irq(host->irq, omap_hsmmc_irq, 0, 1949a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 1950a45c6cb8SMadhusudhan Chikkature if (ret) { 1951b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 1952a45c6cb8SMadhusudhan Chikkature goto err_irq; 1953a45c6cb8SMadhusudhan Chikkature } 1954a45c6cb8SMadhusudhan Chikkature 1955a45c6cb8SMadhusudhan Chikkature if (pdata->init != NULL) { 1956a45c6cb8SMadhusudhan Chikkature if (pdata->init(&pdev->dev) != 0) { 1957b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), 195870a3341aSDenis Karpov "Unable to configure MMC IRQs\n"); 1959a45c6cb8SMadhusudhan Chikkature goto err_irq_cd_init; 1960a45c6cb8SMadhusudhan Chikkature } 1961a45c6cb8SMadhusudhan Chikkature } 1962db0fefc5SAdrian Hunter 1963b702b106SAdrian Hunter if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) { 1964db0fefc5SAdrian Hunter ret = omap_hsmmc_reg_get(host); 1965db0fefc5SAdrian Hunter if (ret) 1966db0fefc5SAdrian Hunter goto err_reg; 1967db0fefc5SAdrian Hunter host->use_reg = 1; 1968db0fefc5SAdrian Hunter } 1969db0fefc5SAdrian Hunter 1970b583f26dSDavid Brownell mmc->ocr_avail = mmc_slot(host).ocr_mask; 1971a45c6cb8SMadhusudhan Chikkature 1972a45c6cb8SMadhusudhan Chikkature /* Request IRQ for card detect */ 1973e1a55f5eSAdrian Hunter if ((mmc_slot(host).card_detect_irq)) { 19747efab4f3SNeilBrown ret = request_threaded_irq(mmc_slot(host).card_detect_irq, 19757efab4f3SNeilBrown NULL, 19767efab4f3SNeilBrown omap_hsmmc_detect, 1977db35f83eSMing Lei IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1978a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 1979a45c6cb8SMadhusudhan Chikkature if (ret) { 1980b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), 1981a45c6cb8SMadhusudhan Chikkature "Unable to grab MMC CD IRQ\n"); 1982a45c6cb8SMadhusudhan Chikkature goto err_irq_cd; 1983a45c6cb8SMadhusudhan Chikkature } 198472f2e2c7Skishore kadiyala pdata->suspend = omap_hsmmc_suspend_cdirq; 198572f2e2c7Skishore kadiyala pdata->resume = omap_hsmmc_resume_cdirq; 1986a45c6cb8SMadhusudhan Chikkature } 1987a45c6cb8SMadhusudhan Chikkature 1988b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 1989a45c6cb8SMadhusudhan Chikkature 199046b76035SDaniel Mack pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 199146b76035SDaniel Mack if (IS_ERR(pinctrl)) 199246b76035SDaniel Mack dev_warn(&pdev->dev, 199346b76035SDaniel Mack "pins are not configured from the driver\n"); 199446b76035SDaniel Mack 1995b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 1996b62f6228SAdrian Hunter 1997a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 1998a45c6cb8SMadhusudhan Chikkature 1999191d1f1dSDenis Karpov if (mmc_slot(host).name != NULL) { 2000a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2001a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2002a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 2003a45c6cb8SMadhusudhan Chikkature } 2004191d1f1dSDenis Karpov if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { 2005a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, 2006a45c6cb8SMadhusudhan Chikkature &dev_attr_cover_switch); 2007a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2008db0fefc5SAdrian Hunter goto err_slot_name; 2009a45c6cb8SMadhusudhan Chikkature } 2010a45c6cb8SMadhusudhan Chikkature 201170a3341aSDenis Karpov omap_hsmmc_debugfs(mmc); 2012fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2013fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2014d900f712SDenis Karpov 2015a45c6cb8SMadhusudhan Chikkature return 0; 2016a45c6cb8SMadhusudhan Chikkature 2017a45c6cb8SMadhusudhan Chikkature err_slot_name: 2018a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 2019a45c6cb8SMadhusudhan Chikkature free_irq(mmc_slot(host).card_detect_irq, host); 2020db0fefc5SAdrian Hunter err_irq_cd: 2021db0fefc5SAdrian Hunter if (host->use_reg) 2022db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2023db0fefc5SAdrian Hunter err_reg: 2024db0fefc5SAdrian Hunter if (host->pdata->cleanup) 2025db0fefc5SAdrian Hunter host->pdata->cleanup(&pdev->dev); 2026a45c6cb8SMadhusudhan Chikkature err_irq_cd_init: 2027a45c6cb8SMadhusudhan Chikkature free_irq(host->irq, host); 2028a45c6cb8SMadhusudhan Chikkature err_irq: 2029c5c98927SRussell King if (host->tx_chan) 2030c5c98927SRussell King dma_release_channel(host->tx_chan); 2031c5c98927SRussell King if (host->rx_chan) 2032c5c98927SRussell King dma_release_channel(host->rx_chan); 2033d59d77edSBalaji T K pm_runtime_put_sync(host->dev); 203437f6190dSTony Lindgren pm_runtime_disable(host->dev); 2035a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 2036cd03d9a8SRajendra Nayak if (host->dbclk) { 203794c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2038a45c6cb8SMadhusudhan Chikkature clk_put(host->dbclk); 2039a45c6cb8SMadhusudhan Chikkature } 2040a45c6cb8SMadhusudhan Chikkature err1: 2041a45c6cb8SMadhusudhan Chikkature iounmap(host->base); 2042a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 2043db0fefc5SAdrian Hunter err_alloc: 2044db0fefc5SAdrian Hunter omap_hsmmc_gpio_free(pdata); 2045db0fefc5SAdrian Hunter err: 204648b332f9SRussell King res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 204748b332f9SRussell King if (res) 2048984b203aSChris Ball release_mem_region(res->start, resource_size(res)); 2049a45c6cb8SMadhusudhan Chikkature return ret; 2050a45c6cb8SMadhusudhan Chikkature } 2051a45c6cb8SMadhusudhan Chikkature 20526e0ee714SBill Pemberton static int omap_hsmmc_remove(struct platform_device *pdev) 2053a45c6cb8SMadhusudhan Chikkature { 205470a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2055a45c6cb8SMadhusudhan Chikkature struct resource *res; 2056a45c6cb8SMadhusudhan Chikkature 2057fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2058a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 2059db0fefc5SAdrian Hunter if (host->use_reg) 2060db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2061a45c6cb8SMadhusudhan Chikkature if (host->pdata->cleanup) 2062a45c6cb8SMadhusudhan Chikkature host->pdata->cleanup(&pdev->dev); 2063a45c6cb8SMadhusudhan Chikkature free_irq(host->irq, host); 2064a45c6cb8SMadhusudhan Chikkature if (mmc_slot(host).card_detect_irq) 2065a45c6cb8SMadhusudhan Chikkature free_irq(mmc_slot(host).card_detect_irq, host); 2066a45c6cb8SMadhusudhan Chikkature 2067c5c98927SRussell King if (host->tx_chan) 2068c5c98927SRussell King dma_release_channel(host->tx_chan); 2069c5c98927SRussell King if (host->rx_chan) 2070c5c98927SRussell King dma_release_channel(host->rx_chan); 2071c5c98927SRussell King 2072fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2073fa4aa2d4SBalaji T K pm_runtime_disable(host->dev); 2074a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 2075cd03d9a8SRajendra Nayak if (host->dbclk) { 207694c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2077a45c6cb8SMadhusudhan Chikkature clk_put(host->dbclk); 2078a45c6cb8SMadhusudhan Chikkature } 2079a45c6cb8SMadhusudhan Chikkature 20809ea28ecbSBalaji T K omap_hsmmc_gpio_free(host->pdata); 2081a45c6cb8SMadhusudhan Chikkature iounmap(host->base); 20829d1f0286SBalaji T K mmc_free_host(host->mmc); 2083a45c6cb8SMadhusudhan Chikkature 2084a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2085a45c6cb8SMadhusudhan Chikkature if (res) 2086984b203aSChris Ball release_mem_region(res->start, resource_size(res)); 2087a45c6cb8SMadhusudhan Chikkature 2088a45c6cb8SMadhusudhan Chikkature return 0; 2089a45c6cb8SMadhusudhan Chikkature } 2090a45c6cb8SMadhusudhan Chikkature 2091a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_PM 2092a48ce884SFelipe Balbi static int omap_hsmmc_prepare(struct device *dev) 2093a48ce884SFelipe Balbi { 2094a48ce884SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2095a48ce884SFelipe Balbi 2096a48ce884SFelipe Balbi if (host->pdata->suspend) 2097a48ce884SFelipe Balbi return host->pdata->suspend(dev, host->slot_id); 2098a48ce884SFelipe Balbi 2099a48ce884SFelipe Balbi return 0; 2100a48ce884SFelipe Balbi } 2101a48ce884SFelipe Balbi 2102a48ce884SFelipe Balbi static void omap_hsmmc_complete(struct device *dev) 2103a48ce884SFelipe Balbi { 2104a48ce884SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2105a48ce884SFelipe Balbi 2106a48ce884SFelipe Balbi if (host->pdata->resume) 2107a48ce884SFelipe Balbi host->pdata->resume(dev, host->slot_id); 2108a48ce884SFelipe Balbi 2109a48ce884SFelipe Balbi } 2110a48ce884SFelipe Balbi 2111a791daa1SKevin Hilman static int omap_hsmmc_suspend(struct device *dev) 2112a45c6cb8SMadhusudhan Chikkature { 2113927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2114927ce944SFelipe Balbi 2115927ce944SFelipe Balbi if (!host) 2116927ce944SFelipe Balbi return 0; 2117a45c6cb8SMadhusudhan Chikkature 2118fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 211931f9d463SEliad Peller 212031f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 212131f9d463SEliad Peller omap_hsmmc_disable_irq(host); 212231f9d463SEliad Peller OMAP_HSMMC_WRITE(host->base, HCTL, 212331f9d463SEliad Peller OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 212431f9d463SEliad Peller } 2125927ce944SFelipe Balbi 2126cd03d9a8SRajendra Nayak if (host->dbclk) 212794c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 21283932afd5SUlf Hansson 2129fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 21303932afd5SUlf Hansson return 0; 2131a45c6cb8SMadhusudhan Chikkature } 2132a45c6cb8SMadhusudhan Chikkature 2133a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 2134a791daa1SKevin Hilman static int omap_hsmmc_resume(struct device *dev) 2135a45c6cb8SMadhusudhan Chikkature { 2136927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2137927ce944SFelipe Balbi 2138927ce944SFelipe Balbi if (!host) 2139927ce944SFelipe Balbi return 0; 2140a45c6cb8SMadhusudhan Chikkature 2141fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 214211dd62a7SDenis Karpov 2143cd03d9a8SRajendra Nayak if (host->dbclk) 214494c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 21452bec0893SAdrian Hunter 214631f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 214770a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 21481b331e69SKim Kyuwon 2149b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2150b62f6228SAdrian Hunter 2151fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2152fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 21533932afd5SUlf Hansson return 0; 2154a45c6cb8SMadhusudhan Chikkature } 2155a45c6cb8SMadhusudhan Chikkature 2156a45c6cb8SMadhusudhan Chikkature #else 2157a48ce884SFelipe Balbi #define omap_hsmmc_prepare NULL 2158a48ce884SFelipe Balbi #define omap_hsmmc_complete NULL 215970a3341aSDenis Karpov #define omap_hsmmc_suspend NULL 216070a3341aSDenis Karpov #define omap_hsmmc_resume NULL 2161a45c6cb8SMadhusudhan Chikkature #endif 2162a45c6cb8SMadhusudhan Chikkature 2163fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_suspend(struct device *dev) 2164fa4aa2d4SBalaji T K { 2165fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 2166fa4aa2d4SBalaji T K 2167fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2168fa4aa2d4SBalaji T K omap_hsmmc_context_save(host); 2169927ce944SFelipe Balbi dev_dbg(dev, "disabled\n"); 2170fa4aa2d4SBalaji T K 2171fa4aa2d4SBalaji T K return 0; 2172fa4aa2d4SBalaji T K } 2173fa4aa2d4SBalaji T K 2174fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_resume(struct device *dev) 2175fa4aa2d4SBalaji T K { 2176fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 2177fa4aa2d4SBalaji T K 2178fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2179fa4aa2d4SBalaji T K omap_hsmmc_context_restore(host); 2180927ce944SFelipe Balbi dev_dbg(dev, "enabled\n"); 2181fa4aa2d4SBalaji T K 2182fa4aa2d4SBalaji T K return 0; 2183fa4aa2d4SBalaji T K } 2184fa4aa2d4SBalaji T K 2185a791daa1SKevin Hilman static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 218670a3341aSDenis Karpov .suspend = omap_hsmmc_suspend, 218770a3341aSDenis Karpov .resume = omap_hsmmc_resume, 2188a48ce884SFelipe Balbi .prepare = omap_hsmmc_prepare, 2189a48ce884SFelipe Balbi .complete = omap_hsmmc_complete, 2190fa4aa2d4SBalaji T K .runtime_suspend = omap_hsmmc_runtime_suspend, 2191fa4aa2d4SBalaji T K .runtime_resume = omap_hsmmc_runtime_resume, 2192a791daa1SKevin Hilman }; 2193a791daa1SKevin Hilman 2194a791daa1SKevin Hilman static struct platform_driver omap_hsmmc_driver = { 2195efa25fd3SFelipe Balbi .probe = omap_hsmmc_probe, 21960433c143SBill Pemberton .remove = omap_hsmmc_remove, 2197a45c6cb8SMadhusudhan Chikkature .driver = { 2198a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 2199a45c6cb8SMadhusudhan Chikkature .owner = THIS_MODULE, 2200a791daa1SKevin Hilman .pm = &omap_hsmmc_dev_pm_ops, 220146856a68SRajendra Nayak .of_match_table = of_match_ptr(omap_mmc_of_match), 2202a45c6cb8SMadhusudhan Chikkature }, 2203a45c6cb8SMadhusudhan Chikkature }; 2204a45c6cb8SMadhusudhan Chikkature 2205b796450bSFelipe Balbi module_platform_driver(omap_hsmmc_driver); 2206a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2207a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 2208a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 2209a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 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