1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 21a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 22a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 23a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 24a45c6cb8SMadhusudhan Chikkature #include <linux/workqueue.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 29a45c6cb8SMadhusudhan Chikkature #include <linux/semaphore.h> 30a45c6cb8SMadhusudhan Chikkature #include <mach/dma.h> 31a45c6cb8SMadhusudhan Chikkature #include <mach/hardware.h> 32a45c6cb8SMadhusudhan Chikkature #include <mach/board.h> 33a45c6cb8SMadhusudhan Chikkature #include <mach/mmc.h> 34a45c6cb8SMadhusudhan Chikkature #include <mach/cpu.h> 35a45c6cb8SMadhusudhan Chikkature 36a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 37a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCONFIG 0x0010 38a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 39a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 40a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 41a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 42a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 43a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 44a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 45a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 46a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 47a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 48a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 49a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 50a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 51a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 52a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 53a45c6cb8SMadhusudhan Chikkature 54a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 55a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 56a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 57a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 58eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 591b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 60a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 61a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 62a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 63a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 64a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 65a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 66a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 67a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 68a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 69a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 70a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 71a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 72a45c6cb8SMadhusudhan Chikkature #define INT_EN_MASK 0x307F0033 73a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 74a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 75a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 76a45c6cb8SMadhusudhan Chikkature #define DMA_EN 0x1 77a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 78a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 79a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 80a45c6cb8SMadhusudhan Chikkature #define CC 0x1 81a45c6cb8SMadhusudhan Chikkature #define TC 0x02 82a45c6cb8SMadhusudhan Chikkature #define OD 0x1 83a45c6cb8SMadhusudhan Chikkature #define ERR (1 << 15) 84a45c6cb8SMadhusudhan Chikkature #define CMD_TIMEOUT (1 << 16) 85a45c6cb8SMadhusudhan Chikkature #define DATA_TIMEOUT (1 << 20) 86a45c6cb8SMadhusudhan Chikkature #define CMD_CRC (1 << 17) 87a45c6cb8SMadhusudhan Chikkature #define DATA_CRC (1 << 21) 88a45c6cb8SMadhusudhan Chikkature #define CARD_ERR (1 << 28) 89a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 90a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 91a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 92a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 93a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 94a45c6cb8SMadhusudhan Chikkature 95a45c6cb8SMadhusudhan Chikkature /* 96a45c6cb8SMadhusudhan Chikkature * FIXME: Most likely all the data using these _DEVID defines should come 97a45c6cb8SMadhusudhan Chikkature * from the platform_data, or implemented in controller and slot specific 98a45c6cb8SMadhusudhan Chikkature * functions. 99a45c6cb8SMadhusudhan Chikkature */ 100a45c6cb8SMadhusudhan Chikkature #define OMAP_MMC1_DEVID 0 101a45c6cb8SMadhusudhan Chikkature #define OMAP_MMC2_DEVID 1 102a45c6cb8SMadhusudhan Chikkature 103a45c6cb8SMadhusudhan Chikkature #define OMAP_MMC_DATADIR_NONE 0 104a45c6cb8SMadhusudhan Chikkature #define OMAP_MMC_DATADIR_READ 1 105a45c6cb8SMadhusudhan Chikkature #define OMAP_MMC_DATADIR_WRITE 2 106a45c6cb8SMadhusudhan Chikkature #define MMC_TIMEOUT_MS 20 107a45c6cb8SMadhusudhan Chikkature #define OMAP_MMC_MASTER_CLOCK 96000000 108a45c6cb8SMadhusudhan Chikkature #define DRIVER_NAME "mmci-omap-hs" 109a45c6cb8SMadhusudhan Chikkature 110a45c6cb8SMadhusudhan Chikkature /* 111a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 112a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 113a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 114a45c6cb8SMadhusudhan Chikkature */ 115a45c6cb8SMadhusudhan Chikkature #define mmc_slot(host) (host->pdata->slots[host->slot_id]) 116a45c6cb8SMadhusudhan Chikkature 117a45c6cb8SMadhusudhan Chikkature /* 118a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 119a45c6cb8SMadhusudhan Chikkature */ 120a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 121a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 122a45c6cb8SMadhusudhan Chikkature 123a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 124a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 125a45c6cb8SMadhusudhan Chikkature 126a45c6cb8SMadhusudhan Chikkature struct mmc_omap_host { 127a45c6cb8SMadhusudhan Chikkature struct device *dev; 128a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 129a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 130a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 131a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 132a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 133a45c6cb8SMadhusudhan Chikkature struct clk *iclk; 134a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 135a45c6cb8SMadhusudhan Chikkature struct semaphore sem; 136a45c6cb8SMadhusudhan Chikkature struct work_struct mmc_carddetect_work; 137a45c6cb8SMadhusudhan Chikkature void __iomem *base; 138a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 139a45c6cb8SMadhusudhan Chikkature unsigned int id; 140a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 141a45c6cb8SMadhusudhan Chikkature unsigned int dma_dir; 142a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 143a45c6cb8SMadhusudhan Chikkature unsigned char datadir; 144a45c6cb8SMadhusudhan Chikkature u32 *buffer; 145a45c6cb8SMadhusudhan Chikkature u32 bytesleft; 146a45c6cb8SMadhusudhan Chikkature int suspended; 147a45c6cb8SMadhusudhan Chikkature int irq; 148a45c6cb8SMadhusudhan Chikkature int carddetect; 149a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 150a45c6cb8SMadhusudhan Chikkature int initstr; 151a45c6cb8SMadhusudhan Chikkature int slot_id; 152a45c6cb8SMadhusudhan Chikkature int dbclk_enabled; 1534a694dc9SAdrian Hunter int response_busy; 154a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata; 155a45c6cb8SMadhusudhan Chikkature }; 156a45c6cb8SMadhusudhan Chikkature 157a45c6cb8SMadhusudhan Chikkature /* 158a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 159a45c6cb8SMadhusudhan Chikkature */ 160a45c6cb8SMadhusudhan Chikkature static void omap_mmc_stop_clock(struct mmc_omap_host *host) 161a45c6cb8SMadhusudhan Chikkature { 162a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 163a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 164a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 165a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n"); 166a45c6cb8SMadhusudhan Chikkature } 167a45c6cb8SMadhusudhan Chikkature 168a45c6cb8SMadhusudhan Chikkature /* 169a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 170a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 171a45c6cb8SMadhusudhan Chikkature */ 172a45c6cb8SMadhusudhan Chikkature static void send_init_stream(struct mmc_omap_host *host) 173a45c6cb8SMadhusudhan Chikkature { 174a45c6cb8SMadhusudhan Chikkature int reg = 0; 175a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 176a45c6cb8SMadhusudhan Chikkature 177a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 178a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 179a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 180a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 181a45c6cb8SMadhusudhan Chikkature 182a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 183a45c6cb8SMadhusudhan Chikkature while ((reg != CC) && time_before(jiffies, timeout)) 184a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, STAT) & CC; 185a45c6cb8SMadhusudhan Chikkature 186a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 187a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 188a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 189a45c6cb8SMadhusudhan Chikkature } 190a45c6cb8SMadhusudhan Chikkature 191a45c6cb8SMadhusudhan Chikkature static inline 192a45c6cb8SMadhusudhan Chikkature int mmc_omap_cover_is_closed(struct mmc_omap_host *host) 193a45c6cb8SMadhusudhan Chikkature { 194a45c6cb8SMadhusudhan Chikkature int r = 1; 195a45c6cb8SMadhusudhan Chikkature 196a45c6cb8SMadhusudhan Chikkature if (host->pdata->slots[host->slot_id].get_cover_state) 197a45c6cb8SMadhusudhan Chikkature r = host->pdata->slots[host->slot_id].get_cover_state(host->dev, 198a45c6cb8SMadhusudhan Chikkature host->slot_id); 199a45c6cb8SMadhusudhan Chikkature return r; 200a45c6cb8SMadhusudhan Chikkature } 201a45c6cb8SMadhusudhan Chikkature 202a45c6cb8SMadhusudhan Chikkature static ssize_t 203a45c6cb8SMadhusudhan Chikkature mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr, 204a45c6cb8SMadhusudhan Chikkature char *buf) 205a45c6cb8SMadhusudhan Chikkature { 206a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 207a45c6cb8SMadhusudhan Chikkature struct mmc_omap_host *host = mmc_priv(mmc); 208a45c6cb8SMadhusudhan Chikkature 209a45c6cb8SMadhusudhan Chikkature return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" : 210a45c6cb8SMadhusudhan Chikkature "open"); 211a45c6cb8SMadhusudhan Chikkature } 212a45c6cb8SMadhusudhan Chikkature 213a45c6cb8SMadhusudhan Chikkature static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL); 214a45c6cb8SMadhusudhan Chikkature 215a45c6cb8SMadhusudhan Chikkature static ssize_t 216a45c6cb8SMadhusudhan Chikkature mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr, 217a45c6cb8SMadhusudhan Chikkature char *buf) 218a45c6cb8SMadhusudhan Chikkature { 219a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 220a45c6cb8SMadhusudhan Chikkature struct mmc_omap_host *host = mmc_priv(mmc); 221a45c6cb8SMadhusudhan Chikkature struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id]; 222a45c6cb8SMadhusudhan Chikkature 223a45c6cb8SMadhusudhan Chikkature return sprintf(buf, "slot:%s\n", slot.name); 224a45c6cb8SMadhusudhan Chikkature } 225a45c6cb8SMadhusudhan Chikkature 226a45c6cb8SMadhusudhan Chikkature static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL); 227a45c6cb8SMadhusudhan Chikkature 228a45c6cb8SMadhusudhan Chikkature /* 229a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 230a45c6cb8SMadhusudhan Chikkature */ 231a45c6cb8SMadhusudhan Chikkature static void 232a45c6cb8SMadhusudhan Chikkature mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd, 233a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 234a45c6cb8SMadhusudhan Chikkature { 235a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 236a45c6cb8SMadhusudhan Chikkature 237a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 238a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 239a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 240a45c6cb8SMadhusudhan Chikkature 241a45c6cb8SMadhusudhan Chikkature /* 242a45c6cb8SMadhusudhan Chikkature * Clear status bits and enable interrupts 243a45c6cb8SMadhusudhan Chikkature */ 244a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 245a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK); 246a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 247a45c6cb8SMadhusudhan Chikkature 2484a694dc9SAdrian Hunter host->response_busy = 0; 249a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 250a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 251a45c6cb8SMadhusudhan Chikkature resptype = 1; 2524a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 2534a694dc9SAdrian Hunter resptype = 3; 2544a694dc9SAdrian Hunter host->response_busy = 1; 2554a694dc9SAdrian Hunter } else 256a45c6cb8SMadhusudhan Chikkature resptype = 2; 257a45c6cb8SMadhusudhan Chikkature } 258a45c6cb8SMadhusudhan Chikkature 259a45c6cb8SMadhusudhan Chikkature /* 260a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 261a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 262a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 263a45c6cb8SMadhusudhan Chikkature */ 264a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 265a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 266a45c6cb8SMadhusudhan Chikkature 267a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 268a45c6cb8SMadhusudhan Chikkature 269a45c6cb8SMadhusudhan Chikkature if (data) { 270a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 271a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 272a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 273a45c6cb8SMadhusudhan Chikkature else 274a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 275a45c6cb8SMadhusudhan Chikkature } 276a45c6cb8SMadhusudhan Chikkature 277a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 278a45c6cb8SMadhusudhan Chikkature cmdreg |= DMA_EN; 279a45c6cb8SMadhusudhan Chikkature 280a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 281a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 282a45c6cb8SMadhusudhan Chikkature } 283a45c6cb8SMadhusudhan Chikkature 284a45c6cb8SMadhusudhan Chikkature /* 285a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 286a45c6cb8SMadhusudhan Chikkature */ 287a45c6cb8SMadhusudhan Chikkature static void 288a45c6cb8SMadhusudhan Chikkature mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data) 289a45c6cb8SMadhusudhan Chikkature { 2904a694dc9SAdrian Hunter if (!data) { 2914a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 2924a694dc9SAdrian Hunter 2934a694dc9SAdrian Hunter host->mrq = NULL; 2944a694dc9SAdrian Hunter mmc_omap_fclk_lazy_disable(host); 2954a694dc9SAdrian Hunter mmc_request_done(host->mmc, mrq); 2964a694dc9SAdrian Hunter return; 2974a694dc9SAdrian Hunter } 2984a694dc9SAdrian Hunter 299a45c6cb8SMadhusudhan Chikkature host->data = NULL; 300a45c6cb8SMadhusudhan Chikkature 301a45c6cb8SMadhusudhan Chikkature if (host->use_dma && host->dma_ch != -1) 302a45c6cb8SMadhusudhan Chikkature dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len, 303a45c6cb8SMadhusudhan Chikkature host->dma_dir); 304a45c6cb8SMadhusudhan Chikkature 305a45c6cb8SMadhusudhan Chikkature host->datadir = OMAP_MMC_DATADIR_NONE; 306a45c6cb8SMadhusudhan Chikkature 307a45c6cb8SMadhusudhan Chikkature if (!data->error) 308a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 309a45c6cb8SMadhusudhan Chikkature else 310a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 311a45c6cb8SMadhusudhan Chikkature 312a45c6cb8SMadhusudhan Chikkature if (!data->stop) { 313a45c6cb8SMadhusudhan Chikkature host->mrq = NULL; 314a45c6cb8SMadhusudhan Chikkature mmc_request_done(host->mmc, data->mrq); 315a45c6cb8SMadhusudhan Chikkature return; 316a45c6cb8SMadhusudhan Chikkature } 317a45c6cb8SMadhusudhan Chikkature mmc_omap_start_command(host, data->stop, NULL); 318a45c6cb8SMadhusudhan Chikkature } 319a45c6cb8SMadhusudhan Chikkature 320a45c6cb8SMadhusudhan Chikkature /* 321a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 322a45c6cb8SMadhusudhan Chikkature */ 323a45c6cb8SMadhusudhan Chikkature static void 324a45c6cb8SMadhusudhan Chikkature mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd) 325a45c6cb8SMadhusudhan Chikkature { 326a45c6cb8SMadhusudhan Chikkature host->cmd = NULL; 327a45c6cb8SMadhusudhan Chikkature 328a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 329a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 330a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 331a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 332a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 333a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 334a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 335a45c6cb8SMadhusudhan Chikkature } else { 336a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 337a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 338a45c6cb8SMadhusudhan Chikkature } 339a45c6cb8SMadhusudhan Chikkature } 3404a694dc9SAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) { 341a45c6cb8SMadhusudhan Chikkature host->mrq = NULL; 342a45c6cb8SMadhusudhan Chikkature mmc_request_done(host->mmc, cmd->mrq); 343a45c6cb8SMadhusudhan Chikkature } 344a45c6cb8SMadhusudhan Chikkature } 345a45c6cb8SMadhusudhan Chikkature 346a45c6cb8SMadhusudhan Chikkature /* 347a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 348a45c6cb8SMadhusudhan Chikkature */ 34982788ff5SJarkko Lavinen static void mmc_dma_cleanup(struct mmc_omap_host *host, int errno) 350a45c6cb8SMadhusudhan Chikkature { 35182788ff5SJarkko Lavinen host->data->error = errno; 352a45c6cb8SMadhusudhan Chikkature 353a45c6cb8SMadhusudhan Chikkature if (host->use_dma && host->dma_ch != -1) { 354a45c6cb8SMadhusudhan Chikkature dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len, 355a45c6cb8SMadhusudhan Chikkature host->dma_dir); 356a45c6cb8SMadhusudhan Chikkature omap_free_dma(host->dma_ch); 357a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 358a45c6cb8SMadhusudhan Chikkature up(&host->sem); 359a45c6cb8SMadhusudhan Chikkature } 360a45c6cb8SMadhusudhan Chikkature host->data = NULL; 361a45c6cb8SMadhusudhan Chikkature host->datadir = OMAP_MMC_DATADIR_NONE; 362a45c6cb8SMadhusudhan Chikkature } 363a45c6cb8SMadhusudhan Chikkature 364a45c6cb8SMadhusudhan Chikkature /* 365a45c6cb8SMadhusudhan Chikkature * Readable error output 366a45c6cb8SMadhusudhan Chikkature */ 367a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 368a45c6cb8SMadhusudhan Chikkature static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status) 369a45c6cb8SMadhusudhan Chikkature { 370a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 371a45c6cb8SMadhusudhan Chikkature static const char *mmc_omap_status_bits[] = { 372a45c6cb8SMadhusudhan Chikkature "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ", 373a45c6cb8SMadhusudhan Chikkature "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC", 374a45c6cb8SMadhusudhan Chikkature "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---", 375a45c6cb8SMadhusudhan Chikkature "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---" 376a45c6cb8SMadhusudhan Chikkature }; 377a45c6cb8SMadhusudhan Chikkature char res[256]; 378a45c6cb8SMadhusudhan Chikkature char *buf = res; 379a45c6cb8SMadhusudhan Chikkature int len, i; 380a45c6cb8SMadhusudhan Chikkature 381a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 382a45c6cb8SMadhusudhan Chikkature buf += len; 383a45c6cb8SMadhusudhan Chikkature 384a45c6cb8SMadhusudhan Chikkature for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++) 385a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 386a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, " %s", mmc_omap_status_bits[i]); 387a45c6cb8SMadhusudhan Chikkature buf += len; 388a45c6cb8SMadhusudhan Chikkature } 389a45c6cb8SMadhusudhan Chikkature 390a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "%s\n", res); 391a45c6cb8SMadhusudhan Chikkature } 392a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 393a45c6cb8SMadhusudhan Chikkature 3943ebf74b1SJean Pihet /* 3953ebf74b1SJean Pihet * MMC controller internal state machines reset 3963ebf74b1SJean Pihet * 3973ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 3983ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 3993ebf74b1SJean Pihet * Can be called from interrupt context 4003ebf74b1SJean Pihet */ 4013ebf74b1SJean Pihet static inline void mmc_omap_reset_controller_fsm(struct mmc_omap_host *host, 4023ebf74b1SJean Pihet unsigned long bit) 4033ebf74b1SJean Pihet { 4043ebf74b1SJean Pihet unsigned long i = 0; 4053ebf74b1SJean Pihet unsigned long limit = (loops_per_jiffy * 4063ebf74b1SJean Pihet msecs_to_jiffies(MMC_TIMEOUT_MS)); 4073ebf74b1SJean Pihet 4083ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 4093ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 4103ebf74b1SJean Pihet 4113ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 4123ebf74b1SJean Pihet (i++ < limit)) 4133ebf74b1SJean Pihet cpu_relax(); 4143ebf74b1SJean Pihet 4153ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 4163ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 4173ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 4183ebf74b1SJean Pihet __func__); 4193ebf74b1SJean Pihet } 420a45c6cb8SMadhusudhan Chikkature 421a45c6cb8SMadhusudhan Chikkature /* 422a45c6cb8SMadhusudhan Chikkature * MMC controller IRQ handler 423a45c6cb8SMadhusudhan Chikkature */ 424a45c6cb8SMadhusudhan Chikkature static irqreturn_t mmc_omap_irq(int irq, void *dev_id) 425a45c6cb8SMadhusudhan Chikkature { 426a45c6cb8SMadhusudhan Chikkature struct mmc_omap_host *host = dev_id; 427a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 428a45c6cb8SMadhusudhan Chikkature int end_cmd = 0, end_trans = 0, status; 429a45c6cb8SMadhusudhan Chikkature 4304a694dc9SAdrian Hunter if (host->mrq == NULL) { 431a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, STAT, 432a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, STAT)); 433a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 434a45c6cb8SMadhusudhan Chikkature } 435a45c6cb8SMadhusudhan Chikkature 436a45c6cb8SMadhusudhan Chikkature data = host->data; 437a45c6cb8SMadhusudhan Chikkature status = OMAP_HSMMC_READ(host->base, STAT); 438a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 439a45c6cb8SMadhusudhan Chikkature 440a45c6cb8SMadhusudhan Chikkature if (status & ERR) { 441a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 442a45c6cb8SMadhusudhan Chikkature mmc_omap_report_irq(host, status); 443a45c6cb8SMadhusudhan Chikkature #endif 444a45c6cb8SMadhusudhan Chikkature if ((status & CMD_TIMEOUT) || 445a45c6cb8SMadhusudhan Chikkature (status & CMD_CRC)) { 446a45c6cb8SMadhusudhan Chikkature if (host->cmd) { 447a45c6cb8SMadhusudhan Chikkature if (status & CMD_TIMEOUT) { 4483ebf74b1SJean Pihet mmc_omap_reset_controller_fsm(host, SRC); 449a45c6cb8SMadhusudhan Chikkature host->cmd->error = -ETIMEDOUT; 450a45c6cb8SMadhusudhan Chikkature } else { 451a45c6cb8SMadhusudhan Chikkature host->cmd->error = -EILSEQ; 452a45c6cb8SMadhusudhan Chikkature } 453a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 454a45c6cb8SMadhusudhan Chikkature } 4554a694dc9SAdrian Hunter if (host->data || host->response_busy) { 4564a694dc9SAdrian Hunter if (host->data) 45782788ff5SJarkko Lavinen mmc_dma_cleanup(host, -ETIMEDOUT); 4584a694dc9SAdrian Hunter host->response_busy = 0; 4593ebf74b1SJean Pihet mmc_omap_reset_controller_fsm(host, SRD); 460c232f457SJean Pihet } 461a45c6cb8SMadhusudhan Chikkature } 462a45c6cb8SMadhusudhan Chikkature if ((status & DATA_TIMEOUT) || 463a45c6cb8SMadhusudhan Chikkature (status & DATA_CRC)) { 4644a694dc9SAdrian Hunter if (host->data || host->response_busy) { 4654a694dc9SAdrian Hunter int err = (status & DATA_TIMEOUT) ? 4664a694dc9SAdrian Hunter -ETIMEDOUT : -EILSEQ; 4674a694dc9SAdrian Hunter 4684a694dc9SAdrian Hunter if (host->data) 4694a694dc9SAdrian Hunter mmc_dma_cleanup(host, err); 470a45c6cb8SMadhusudhan Chikkature else 4714a694dc9SAdrian Hunter host->mrq->cmd->error = err; 4724a694dc9SAdrian Hunter host->response_busy = 0; 4733ebf74b1SJean Pihet mmc_omap_reset_controller_fsm(host, SRD); 474a45c6cb8SMadhusudhan Chikkature end_trans = 1; 475a45c6cb8SMadhusudhan Chikkature } 476a45c6cb8SMadhusudhan Chikkature } 477a45c6cb8SMadhusudhan Chikkature if (status & CARD_ERR) { 478a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 479a45c6cb8SMadhusudhan Chikkature "Ignoring card err CMD%d\n", host->cmd->opcode); 480a45c6cb8SMadhusudhan Chikkature if (host->cmd) 481a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 482a45c6cb8SMadhusudhan Chikkature if (host->data) 483a45c6cb8SMadhusudhan Chikkature end_trans = 1; 484a45c6cb8SMadhusudhan Chikkature } 485a45c6cb8SMadhusudhan Chikkature } 486a45c6cb8SMadhusudhan Chikkature 487a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, STAT, status); 488a45c6cb8SMadhusudhan Chikkature 489a45c6cb8SMadhusudhan Chikkature if (end_cmd || (status & CC)) 490a45c6cb8SMadhusudhan Chikkature mmc_omap_cmd_done(host, host->cmd); 491a45c6cb8SMadhusudhan Chikkature if (end_trans || (status & TC)) 492a45c6cb8SMadhusudhan Chikkature mmc_omap_xfer_done(host, data); 493a45c6cb8SMadhusudhan Chikkature 494a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 495a45c6cb8SMadhusudhan Chikkature } 496a45c6cb8SMadhusudhan Chikkature 497a45c6cb8SMadhusudhan Chikkature /* 498eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 499eb250826SDavid Brownell * 500eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 501eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 502eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 503a45c6cb8SMadhusudhan Chikkature */ 504a45c6cb8SMadhusudhan Chikkature static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd) 505a45c6cb8SMadhusudhan Chikkature { 506a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 507a45c6cb8SMadhusudhan Chikkature int ret; 508a45c6cb8SMadhusudhan Chikkature 509a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 510a45c6cb8SMadhusudhan Chikkature clk_disable(host->fclk); 511a45c6cb8SMadhusudhan Chikkature clk_disable(host->iclk); 512a45c6cb8SMadhusudhan Chikkature clk_disable(host->dbclk); 513a45c6cb8SMadhusudhan Chikkature 514a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 515a45c6cb8SMadhusudhan Chikkature ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 516a45c6cb8SMadhusudhan Chikkature if (ret != 0) 517a45c6cb8SMadhusudhan Chikkature goto err; 518a45c6cb8SMadhusudhan Chikkature 519a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 520a45c6cb8SMadhusudhan Chikkature ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd); 521a45c6cb8SMadhusudhan Chikkature if (ret != 0) 522a45c6cb8SMadhusudhan Chikkature goto err; 523a45c6cb8SMadhusudhan Chikkature 524a45c6cb8SMadhusudhan Chikkature clk_enable(host->fclk); 525a45c6cb8SMadhusudhan Chikkature clk_enable(host->iclk); 526a45c6cb8SMadhusudhan Chikkature clk_enable(host->dbclk); 527a45c6cb8SMadhusudhan Chikkature 528a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 529a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 530a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 531eb250826SDavid Brownell 532a45c6cb8SMadhusudhan Chikkature /* 533a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 534a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 535a45c6cb8SMadhusudhan Chikkature * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 536a45c6cb8SMadhusudhan Chikkature * 537eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 538eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 539eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 540eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 541eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 542eb250826SDavid Brownell * 543eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 544eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 545eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 546a45c6cb8SMadhusudhan Chikkature */ 547eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 548a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 549eb250826SDavid Brownell else 550eb250826SDavid Brownell reg_val |= SDVS30; 551a45c6cb8SMadhusudhan Chikkature 552a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 553a45c6cb8SMadhusudhan Chikkature 554a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 555a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 556a45c6cb8SMadhusudhan Chikkature 557a45c6cb8SMadhusudhan Chikkature return 0; 558a45c6cb8SMadhusudhan Chikkature err: 559a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 560a45c6cb8SMadhusudhan Chikkature return ret; 561a45c6cb8SMadhusudhan Chikkature } 562a45c6cb8SMadhusudhan Chikkature 563a45c6cb8SMadhusudhan Chikkature /* 564a45c6cb8SMadhusudhan Chikkature * Work Item to notify the core about card insertion/removal 565a45c6cb8SMadhusudhan Chikkature */ 566a45c6cb8SMadhusudhan Chikkature static void mmc_omap_detect(struct work_struct *work) 567a45c6cb8SMadhusudhan Chikkature { 568a45c6cb8SMadhusudhan Chikkature struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, 569a45c6cb8SMadhusudhan Chikkature mmc_carddetect_work); 570249d0fa9SDavid Brownell struct omap_mmc_slot_data *slot = &mmc_slot(host); 571249d0fa9SDavid Brownell 572249d0fa9SDavid Brownell host->carddetect = slot->card_detect(slot->card_detect_irq); 573a45c6cb8SMadhusudhan Chikkature 574a45c6cb8SMadhusudhan Chikkature sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 575a45c6cb8SMadhusudhan Chikkature if (host->carddetect) { 576a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 200) / 1000); 577a45c6cb8SMadhusudhan Chikkature } else { 5783ebf74b1SJean Pihet mmc_omap_reset_controller_fsm(host, SRD); 579a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 50) / 1000); 580a45c6cb8SMadhusudhan Chikkature } 581a45c6cb8SMadhusudhan Chikkature } 582a45c6cb8SMadhusudhan Chikkature 583a45c6cb8SMadhusudhan Chikkature /* 584a45c6cb8SMadhusudhan Chikkature * ISR for handling card insertion and removal 585a45c6cb8SMadhusudhan Chikkature */ 586a45c6cb8SMadhusudhan Chikkature static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id) 587a45c6cb8SMadhusudhan Chikkature { 588a45c6cb8SMadhusudhan Chikkature struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id; 589a45c6cb8SMadhusudhan Chikkature 590a45c6cb8SMadhusudhan Chikkature schedule_work(&host->mmc_carddetect_work); 591a45c6cb8SMadhusudhan Chikkature 592a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 593a45c6cb8SMadhusudhan Chikkature } 594a45c6cb8SMadhusudhan Chikkature 595a45c6cb8SMadhusudhan Chikkature /* 596a45c6cb8SMadhusudhan Chikkature * DMA call back function 597a45c6cb8SMadhusudhan Chikkature */ 598a45c6cb8SMadhusudhan Chikkature static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data) 599a45c6cb8SMadhusudhan Chikkature { 600a45c6cb8SMadhusudhan Chikkature struct mmc_omap_host *host = data; 601a45c6cb8SMadhusudhan Chikkature 602a45c6cb8SMadhusudhan Chikkature if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ) 603a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n"); 604a45c6cb8SMadhusudhan Chikkature 605a45c6cb8SMadhusudhan Chikkature if (host->dma_ch < 0) 606a45c6cb8SMadhusudhan Chikkature return; 607a45c6cb8SMadhusudhan Chikkature 608a45c6cb8SMadhusudhan Chikkature omap_free_dma(host->dma_ch); 609a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 610a45c6cb8SMadhusudhan Chikkature /* 611a45c6cb8SMadhusudhan Chikkature * DMA Callback: run in interrupt context. 612a45c6cb8SMadhusudhan Chikkature * mutex_unlock will through a kernel warning if used. 613a45c6cb8SMadhusudhan Chikkature */ 614a45c6cb8SMadhusudhan Chikkature up(&host->sem); 615a45c6cb8SMadhusudhan Chikkature } 616a45c6cb8SMadhusudhan Chikkature 617a45c6cb8SMadhusudhan Chikkature /* 618a45c6cb8SMadhusudhan Chikkature * Configure dma src and destination parameters 619a45c6cb8SMadhusudhan Chikkature */ 620a45c6cb8SMadhusudhan Chikkature static int mmc_omap_config_dma_param(int sync_dir, struct mmc_omap_host *host, 621a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 622a45c6cb8SMadhusudhan Chikkature { 623a45c6cb8SMadhusudhan Chikkature if (sync_dir == 0) { 624a45c6cb8SMadhusudhan Chikkature omap_set_dma_dest_params(host->dma_ch, 0, 625a45c6cb8SMadhusudhan Chikkature OMAP_DMA_AMODE_CONSTANT, 626a45c6cb8SMadhusudhan Chikkature (host->mapbase + OMAP_HSMMC_DATA), 0, 0); 627a45c6cb8SMadhusudhan Chikkature omap_set_dma_src_params(host->dma_ch, 0, 628a45c6cb8SMadhusudhan Chikkature OMAP_DMA_AMODE_POST_INC, 629a45c6cb8SMadhusudhan Chikkature sg_dma_address(&data->sg[0]), 0, 0); 630a45c6cb8SMadhusudhan Chikkature } else { 631a45c6cb8SMadhusudhan Chikkature omap_set_dma_src_params(host->dma_ch, 0, 632a45c6cb8SMadhusudhan Chikkature OMAP_DMA_AMODE_CONSTANT, 633a45c6cb8SMadhusudhan Chikkature (host->mapbase + OMAP_HSMMC_DATA), 0, 0); 634a45c6cb8SMadhusudhan Chikkature omap_set_dma_dest_params(host->dma_ch, 0, 635a45c6cb8SMadhusudhan Chikkature OMAP_DMA_AMODE_POST_INC, 636a45c6cb8SMadhusudhan Chikkature sg_dma_address(&data->sg[0]), 0, 0); 637a45c6cb8SMadhusudhan Chikkature } 638a45c6cb8SMadhusudhan Chikkature return 0; 639a45c6cb8SMadhusudhan Chikkature } 640a45c6cb8SMadhusudhan Chikkature /* 641a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 642a45c6cb8SMadhusudhan Chikkature */ 643a45c6cb8SMadhusudhan Chikkature static int 644a45c6cb8SMadhusudhan Chikkature mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req) 645a45c6cb8SMadhusudhan Chikkature { 646a45c6cb8SMadhusudhan Chikkature int sync_dev, sync_dir = 0; 647a45c6cb8SMadhusudhan Chikkature int dma_ch = 0, ret = 0, err = 1; 648a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 649a45c6cb8SMadhusudhan Chikkature 650a45c6cb8SMadhusudhan Chikkature /* 651a45c6cb8SMadhusudhan Chikkature * If for some reason the DMA transfer is still active, 652a45c6cb8SMadhusudhan Chikkature * we wait for timeout period and free the dma 653a45c6cb8SMadhusudhan Chikkature */ 654a45c6cb8SMadhusudhan Chikkature if (host->dma_ch != -1) { 655a45c6cb8SMadhusudhan Chikkature set_current_state(TASK_UNINTERRUPTIBLE); 656a45c6cb8SMadhusudhan Chikkature schedule_timeout(100); 657a45c6cb8SMadhusudhan Chikkature if (down_trylock(&host->sem)) { 658a45c6cb8SMadhusudhan Chikkature omap_free_dma(host->dma_ch); 659a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 660a45c6cb8SMadhusudhan Chikkature up(&host->sem); 661a45c6cb8SMadhusudhan Chikkature return err; 662a45c6cb8SMadhusudhan Chikkature } 663a45c6cb8SMadhusudhan Chikkature } else { 664a45c6cb8SMadhusudhan Chikkature if (down_trylock(&host->sem)) 665a45c6cb8SMadhusudhan Chikkature return err; 666a45c6cb8SMadhusudhan Chikkature } 667a45c6cb8SMadhusudhan Chikkature 668a45c6cb8SMadhusudhan Chikkature if (!(data->flags & MMC_DATA_WRITE)) { 669a45c6cb8SMadhusudhan Chikkature host->dma_dir = DMA_FROM_DEVICE; 670a45c6cb8SMadhusudhan Chikkature if (host->id == OMAP_MMC1_DEVID) 671a45c6cb8SMadhusudhan Chikkature sync_dev = OMAP24XX_DMA_MMC1_RX; 672a45c6cb8SMadhusudhan Chikkature else 673a45c6cb8SMadhusudhan Chikkature sync_dev = OMAP24XX_DMA_MMC2_RX; 674a45c6cb8SMadhusudhan Chikkature } else { 675a45c6cb8SMadhusudhan Chikkature host->dma_dir = DMA_TO_DEVICE; 676a45c6cb8SMadhusudhan Chikkature if (host->id == OMAP_MMC1_DEVID) 677a45c6cb8SMadhusudhan Chikkature sync_dev = OMAP24XX_DMA_MMC1_TX; 678a45c6cb8SMadhusudhan Chikkature else 679a45c6cb8SMadhusudhan Chikkature sync_dev = OMAP24XX_DMA_MMC2_TX; 680a45c6cb8SMadhusudhan Chikkature } 681a45c6cb8SMadhusudhan Chikkature 682a45c6cb8SMadhusudhan Chikkature ret = omap_request_dma(sync_dev, "MMC/SD", mmc_omap_dma_cb, 683a45c6cb8SMadhusudhan Chikkature host, &dma_ch); 684a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 685a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 686a45c6cb8SMadhusudhan Chikkature "%s: omap_request_dma() failed with %d\n", 687a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), ret); 688a45c6cb8SMadhusudhan Chikkature return ret; 689a45c6cb8SMadhusudhan Chikkature } 690a45c6cb8SMadhusudhan Chikkature 691a45c6cb8SMadhusudhan Chikkature host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, 692a45c6cb8SMadhusudhan Chikkature data->sg_len, host->dma_dir); 693a45c6cb8SMadhusudhan Chikkature host->dma_ch = dma_ch; 694a45c6cb8SMadhusudhan Chikkature 695a45c6cb8SMadhusudhan Chikkature if (!(data->flags & MMC_DATA_WRITE)) 696a45c6cb8SMadhusudhan Chikkature mmc_omap_config_dma_param(1, host, data); 697a45c6cb8SMadhusudhan Chikkature else 698a45c6cb8SMadhusudhan Chikkature mmc_omap_config_dma_param(0, host, data); 699a45c6cb8SMadhusudhan Chikkature 700a45c6cb8SMadhusudhan Chikkature if ((data->blksz % 4) == 0) 701a45c6cb8SMadhusudhan Chikkature omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32, 702a45c6cb8SMadhusudhan Chikkature (data->blksz / 4), data->blocks, OMAP_DMA_SYNC_FRAME, 703a45c6cb8SMadhusudhan Chikkature sync_dev, sync_dir); 704a45c6cb8SMadhusudhan Chikkature else 705a45c6cb8SMadhusudhan Chikkature /* REVISIT: The MMC buffer increments only when MSB is written. 706a45c6cb8SMadhusudhan Chikkature * Return error for blksz which is non multiple of four. 707a45c6cb8SMadhusudhan Chikkature */ 708a45c6cb8SMadhusudhan Chikkature return -EINVAL; 709a45c6cb8SMadhusudhan Chikkature 710a45c6cb8SMadhusudhan Chikkature omap_start_dma(dma_ch); 711a45c6cb8SMadhusudhan Chikkature return 0; 712a45c6cb8SMadhusudhan Chikkature } 713a45c6cb8SMadhusudhan Chikkature 714a45c6cb8SMadhusudhan Chikkature static void set_data_timeout(struct mmc_omap_host *host, 715a45c6cb8SMadhusudhan Chikkature struct mmc_request *req) 716a45c6cb8SMadhusudhan Chikkature { 717a45c6cb8SMadhusudhan Chikkature unsigned int timeout, cycle_ns; 718a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 719a45c6cb8SMadhusudhan Chikkature 720a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 721a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 722a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 723a45c6cb8SMadhusudhan Chikkature clkd = 1; 724a45c6cb8SMadhusudhan Chikkature 725a45c6cb8SMadhusudhan Chikkature cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); 726a45c6cb8SMadhusudhan Chikkature timeout = req->data->timeout_ns / cycle_ns; 727a45c6cb8SMadhusudhan Chikkature timeout += req->data->timeout_clks; 728a45c6cb8SMadhusudhan Chikkature if (timeout) { 729a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 730a45c6cb8SMadhusudhan Chikkature dto += 1; 731a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 732a45c6cb8SMadhusudhan Chikkature } 733a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 734a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 735a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 736a45c6cb8SMadhusudhan Chikkature dto += 1; 737a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 738a45c6cb8SMadhusudhan Chikkature dto -= 13; 739a45c6cb8SMadhusudhan Chikkature else 740a45c6cb8SMadhusudhan Chikkature dto = 0; 741a45c6cb8SMadhusudhan Chikkature if (dto > 14) 742a45c6cb8SMadhusudhan Chikkature dto = 14; 743a45c6cb8SMadhusudhan Chikkature } 744a45c6cb8SMadhusudhan Chikkature 745a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 746a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 747a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 748a45c6cb8SMadhusudhan Chikkature } 749a45c6cb8SMadhusudhan Chikkature 750a45c6cb8SMadhusudhan Chikkature /* 751a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 752a45c6cb8SMadhusudhan Chikkature */ 753a45c6cb8SMadhusudhan Chikkature static int 754a45c6cb8SMadhusudhan Chikkature mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req) 755a45c6cb8SMadhusudhan Chikkature { 756a45c6cb8SMadhusudhan Chikkature int ret; 757a45c6cb8SMadhusudhan Chikkature host->data = req->data; 758a45c6cb8SMadhusudhan Chikkature 759a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 760a45c6cb8SMadhusudhan Chikkature host->datadir = OMAP_MMC_DATADIR_NONE; 761a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 762a45c6cb8SMadhusudhan Chikkature return 0; 763a45c6cb8SMadhusudhan Chikkature } 764a45c6cb8SMadhusudhan Chikkature 765a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 766a45c6cb8SMadhusudhan Chikkature | (req->data->blocks << 16)); 767a45c6cb8SMadhusudhan Chikkature set_data_timeout(host, req); 768a45c6cb8SMadhusudhan Chikkature 769a45c6cb8SMadhusudhan Chikkature host->datadir = (req->data->flags & MMC_DATA_WRITE) ? 770a45c6cb8SMadhusudhan Chikkature OMAP_MMC_DATADIR_WRITE : OMAP_MMC_DATADIR_READ; 771a45c6cb8SMadhusudhan Chikkature 772a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 773a45c6cb8SMadhusudhan Chikkature ret = mmc_omap_start_dma_transfer(host, req); 774a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 775a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n"); 776a45c6cb8SMadhusudhan Chikkature return ret; 777a45c6cb8SMadhusudhan Chikkature } 778a45c6cb8SMadhusudhan Chikkature } 779a45c6cb8SMadhusudhan Chikkature return 0; 780a45c6cb8SMadhusudhan Chikkature } 781a45c6cb8SMadhusudhan Chikkature 782a45c6cb8SMadhusudhan Chikkature /* 783a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 784a45c6cb8SMadhusudhan Chikkature */ 785a45c6cb8SMadhusudhan Chikkature static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req) 786a45c6cb8SMadhusudhan Chikkature { 787a45c6cb8SMadhusudhan Chikkature struct mmc_omap_host *host = mmc_priv(mmc); 788a45c6cb8SMadhusudhan Chikkature 789a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 790a45c6cb8SMadhusudhan Chikkature host->mrq = req; 791a45c6cb8SMadhusudhan Chikkature mmc_omap_prepare_data(host, req); 792a45c6cb8SMadhusudhan Chikkature mmc_omap_start_command(host, req->cmd, req->data); 793a45c6cb8SMadhusudhan Chikkature } 794a45c6cb8SMadhusudhan Chikkature 795a45c6cb8SMadhusudhan Chikkature 796a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 797a45c6cb8SMadhusudhan Chikkature static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 798a45c6cb8SMadhusudhan Chikkature { 799a45c6cb8SMadhusudhan Chikkature struct mmc_omap_host *host = mmc_priv(mmc); 800a45c6cb8SMadhusudhan Chikkature u16 dsor = 0; 801a45c6cb8SMadhusudhan Chikkature unsigned long regval; 802a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 803a45c6cb8SMadhusudhan Chikkature 804a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 805a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 806a45c6cb8SMadhusudhan Chikkature mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 807a45c6cb8SMadhusudhan Chikkature break; 808a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 809a45c6cb8SMadhusudhan Chikkature mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd); 810a45c6cb8SMadhusudhan Chikkature break; 811a45c6cb8SMadhusudhan Chikkature } 812a45c6cb8SMadhusudhan Chikkature 813a45c6cb8SMadhusudhan Chikkature switch (mmc->ios.bus_width) { 814a45c6cb8SMadhusudhan Chikkature case MMC_BUS_WIDTH_4: 815a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 816a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 817a45c6cb8SMadhusudhan Chikkature break; 818a45c6cb8SMadhusudhan Chikkature case MMC_BUS_WIDTH_1: 819a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 820a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 821a45c6cb8SMadhusudhan Chikkature break; 822a45c6cb8SMadhusudhan Chikkature } 823a45c6cb8SMadhusudhan Chikkature 824a45c6cb8SMadhusudhan Chikkature if (host->id == OMAP_MMC1_DEVID) { 825eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 826eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 827eb250826SDavid Brownell */ 828a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 829a45c6cb8SMadhusudhan Chikkature (ios->vdd == DUAL_VOLT_OCR_BIT)) { 830a45c6cb8SMadhusudhan Chikkature /* 831a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 832a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 833a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 834a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 835a45c6cb8SMadhusudhan Chikkature */ 836a45c6cb8SMadhusudhan Chikkature if (omap_mmc_switch_opcond(host, ios->vdd) != 0) 837a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 838a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 839a45c6cb8SMadhusudhan Chikkature } 840a45c6cb8SMadhusudhan Chikkature } 841a45c6cb8SMadhusudhan Chikkature 842a45c6cb8SMadhusudhan Chikkature if (ios->clock) { 843a45c6cb8SMadhusudhan Chikkature dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; 844a45c6cb8SMadhusudhan Chikkature if (dsor < 1) 845a45c6cb8SMadhusudhan Chikkature dsor = 1; 846a45c6cb8SMadhusudhan Chikkature 847a45c6cb8SMadhusudhan Chikkature if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) 848a45c6cb8SMadhusudhan Chikkature dsor++; 849a45c6cb8SMadhusudhan Chikkature 850a45c6cb8SMadhusudhan Chikkature if (dsor > 250) 851a45c6cb8SMadhusudhan Chikkature dsor = 250; 852a45c6cb8SMadhusudhan Chikkature } 853a45c6cb8SMadhusudhan Chikkature omap_mmc_stop_clock(host); 854a45c6cb8SMadhusudhan Chikkature regval = OMAP_HSMMC_READ(host->base, SYSCTL); 855a45c6cb8SMadhusudhan Chikkature regval = regval & ~(CLKD_MASK); 856a45c6cb8SMadhusudhan Chikkature regval = regval | (dsor << 6) | (DTO << 16); 857a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 858a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 859a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 860a45c6cb8SMadhusudhan Chikkature 861a45c6cb8SMadhusudhan Chikkature /* Wait till the ICS bit is set */ 862a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 863a45c6cb8SMadhusudhan Chikkature while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2 864a45c6cb8SMadhusudhan Chikkature && time_before(jiffies, timeout)) 865a45c6cb8SMadhusudhan Chikkature msleep(1); 866a45c6cb8SMadhusudhan Chikkature 867a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 868a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 869a45c6cb8SMadhusudhan Chikkature 870a45c6cb8SMadhusudhan Chikkature if (ios->power_mode == MMC_POWER_ON) 871a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 872a45c6cb8SMadhusudhan Chikkature 873a45c6cb8SMadhusudhan Chikkature if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 874a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 875a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | OD); 876a45c6cb8SMadhusudhan Chikkature } 877a45c6cb8SMadhusudhan Chikkature 878a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc) 879a45c6cb8SMadhusudhan Chikkature { 880a45c6cb8SMadhusudhan Chikkature struct mmc_omap_host *host = mmc_priv(mmc); 881a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata = host->pdata; 882a45c6cb8SMadhusudhan Chikkature 883a45c6cb8SMadhusudhan Chikkature if (!pdata->slots[0].card_detect) 884a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 885a45c6cb8SMadhusudhan Chikkature return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq); 886a45c6cb8SMadhusudhan Chikkature } 887a45c6cb8SMadhusudhan Chikkature 888a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_ro(struct mmc_host *mmc) 889a45c6cb8SMadhusudhan Chikkature { 890a45c6cb8SMadhusudhan Chikkature struct mmc_omap_host *host = mmc_priv(mmc); 891a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata = host->pdata; 892a45c6cb8SMadhusudhan Chikkature 893a45c6cb8SMadhusudhan Chikkature if (!pdata->slots[0].get_ro) 894a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 895a45c6cb8SMadhusudhan Chikkature return pdata->slots[0].get_ro(host->dev, 0); 896a45c6cb8SMadhusudhan Chikkature } 897a45c6cb8SMadhusudhan Chikkature 8981b331e69SKim Kyuwon static void omap_hsmmc_init(struct mmc_omap_host *host) 8991b331e69SKim Kyuwon { 9001b331e69SKim Kyuwon u32 hctl, capa, value; 9011b331e69SKim Kyuwon 9021b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 9031b331e69SKim Kyuwon if (host->id == OMAP_MMC1_DEVID) { 9041b331e69SKim Kyuwon hctl = SDVS30; 9051b331e69SKim Kyuwon capa = VS30 | VS18; 9061b331e69SKim Kyuwon } else { 9071b331e69SKim Kyuwon hctl = SDVS18; 9081b331e69SKim Kyuwon capa = VS18; 9091b331e69SKim Kyuwon } 9101b331e69SKim Kyuwon 9111b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 9121b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 9131b331e69SKim Kyuwon 9141b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 9151b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 9161b331e69SKim Kyuwon 9171b331e69SKim Kyuwon /* Set the controller to AUTO IDLE mode */ 9181b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, SYSCONFIG); 9191b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE); 9201b331e69SKim Kyuwon 9211b331e69SKim Kyuwon /* Set SD bus power bit */ 9221b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL); 9231b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | SDBP); 9241b331e69SKim Kyuwon } 9251b331e69SKim Kyuwon 926a45c6cb8SMadhusudhan Chikkature static struct mmc_host_ops mmc_omap_ops = { 927a45c6cb8SMadhusudhan Chikkature .request = omap_mmc_request, 928a45c6cb8SMadhusudhan Chikkature .set_ios = omap_mmc_set_ios, 929a45c6cb8SMadhusudhan Chikkature .get_cd = omap_hsmmc_get_cd, 930a45c6cb8SMadhusudhan Chikkature .get_ro = omap_hsmmc_get_ro, 931a45c6cb8SMadhusudhan Chikkature /* NYET -- enable_sdio_irq */ 932a45c6cb8SMadhusudhan Chikkature }; 933a45c6cb8SMadhusudhan Chikkature 934a45c6cb8SMadhusudhan Chikkature static int __init omap_mmc_probe(struct platform_device *pdev) 935a45c6cb8SMadhusudhan Chikkature { 936a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 937a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 938a45c6cb8SMadhusudhan Chikkature struct mmc_omap_host *host = NULL; 939a45c6cb8SMadhusudhan Chikkature struct resource *res; 940a45c6cb8SMadhusudhan Chikkature int ret = 0, irq; 941a45c6cb8SMadhusudhan Chikkature 942a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 943a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 944a45c6cb8SMadhusudhan Chikkature return -ENXIO; 945a45c6cb8SMadhusudhan Chikkature } 946a45c6cb8SMadhusudhan Chikkature 947a45c6cb8SMadhusudhan Chikkature if (pdata->nr_slots == 0) { 948a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "No Slots\n"); 949a45c6cb8SMadhusudhan Chikkature return -ENXIO; 950a45c6cb8SMadhusudhan Chikkature } 951a45c6cb8SMadhusudhan Chikkature 952a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 953a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 954a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 955a45c6cb8SMadhusudhan Chikkature return -ENXIO; 956a45c6cb8SMadhusudhan Chikkature 957a45c6cb8SMadhusudhan Chikkature res = request_mem_region(res->start, res->end - res->start + 1, 958a45c6cb8SMadhusudhan Chikkature pdev->name); 959a45c6cb8SMadhusudhan Chikkature if (res == NULL) 960a45c6cb8SMadhusudhan Chikkature return -EBUSY; 961a45c6cb8SMadhusudhan Chikkature 962a45c6cb8SMadhusudhan Chikkature mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev); 963a45c6cb8SMadhusudhan Chikkature if (!mmc) { 964a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 965a45c6cb8SMadhusudhan Chikkature goto err; 966a45c6cb8SMadhusudhan Chikkature } 967a45c6cb8SMadhusudhan Chikkature 968a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 969a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 970a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 971a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 972a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 973a45c6cb8SMadhusudhan Chikkature host->dev->dma_mask = &pdata->dma_mask; 974a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 975a45c6cb8SMadhusudhan Chikkature host->irq = irq; 976a45c6cb8SMadhusudhan Chikkature host->id = pdev->id; 977a45c6cb8SMadhusudhan Chikkature host->slot_id = 0; 978a45c6cb8SMadhusudhan Chikkature host->mapbase = res->start; 979a45c6cb8SMadhusudhan Chikkature host->base = ioremap(host->mapbase, SZ_4K); 980a45c6cb8SMadhusudhan Chikkature 981a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 982a45c6cb8SMadhusudhan Chikkature INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect); 983a45c6cb8SMadhusudhan Chikkature 984a45c6cb8SMadhusudhan Chikkature mmc->ops = &mmc_omap_ops; 985a45c6cb8SMadhusudhan Chikkature mmc->f_min = 400000; 986a45c6cb8SMadhusudhan Chikkature mmc->f_max = 52000000; 987a45c6cb8SMadhusudhan Chikkature 988a45c6cb8SMadhusudhan Chikkature sema_init(&host->sem, 1); 989a45c6cb8SMadhusudhan Chikkature 990a45c6cb8SMadhusudhan Chikkature host->iclk = clk_get(&pdev->dev, "mmchs_ick"); 991a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->iclk)) { 992a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->iclk); 993a45c6cb8SMadhusudhan Chikkature host->iclk = NULL; 994a45c6cb8SMadhusudhan Chikkature goto err1; 995a45c6cb8SMadhusudhan Chikkature } 996a45c6cb8SMadhusudhan Chikkature host->fclk = clk_get(&pdev->dev, "mmchs_fck"); 997a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 998a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 999a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 1000a45c6cb8SMadhusudhan Chikkature clk_put(host->iclk); 1001a45c6cb8SMadhusudhan Chikkature goto err1; 1002a45c6cb8SMadhusudhan Chikkature } 1003a45c6cb8SMadhusudhan Chikkature 1004a45c6cb8SMadhusudhan Chikkature if (clk_enable(host->fclk) != 0) { 1005a45c6cb8SMadhusudhan Chikkature clk_put(host->iclk); 1006a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 1007a45c6cb8SMadhusudhan Chikkature goto err1; 1008a45c6cb8SMadhusudhan Chikkature } 1009a45c6cb8SMadhusudhan Chikkature 1010a45c6cb8SMadhusudhan Chikkature if (clk_enable(host->iclk) != 0) { 1011a45c6cb8SMadhusudhan Chikkature clk_disable(host->fclk); 1012a45c6cb8SMadhusudhan Chikkature clk_put(host->iclk); 1013a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 1014a45c6cb8SMadhusudhan Chikkature goto err1; 1015a45c6cb8SMadhusudhan Chikkature } 1016a45c6cb8SMadhusudhan Chikkature 1017a45c6cb8SMadhusudhan Chikkature host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); 1018a45c6cb8SMadhusudhan Chikkature /* 1019a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 1020a45c6cb8SMadhusudhan Chikkature */ 1021a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->dbclk)) 1022a45c6cb8SMadhusudhan Chikkature dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n"); 1023a45c6cb8SMadhusudhan Chikkature else 1024a45c6cb8SMadhusudhan Chikkature if (clk_enable(host->dbclk) != 0) 1025a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "Enabling debounce" 1026a45c6cb8SMadhusudhan Chikkature " clk failed\n"); 1027a45c6cb8SMadhusudhan Chikkature else 1028a45c6cb8SMadhusudhan Chikkature host->dbclk_enabled = 1; 1029a45c6cb8SMadhusudhan Chikkature 1030a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_BLOCK_BOUNCE 1031a45c6cb8SMadhusudhan Chikkature mmc->max_phys_segs = 1; 1032a45c6cb8SMadhusudhan Chikkature mmc->max_hw_segs = 1; 1033a45c6cb8SMadhusudhan Chikkature #endif 1034a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 1035a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 1036a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1037a45c6cb8SMadhusudhan Chikkature mmc->max_seg_size = mmc->max_req_size; 1038a45c6cb8SMadhusudhan Chikkature 1039a45c6cb8SMadhusudhan Chikkature mmc->ocr_avail = mmc_slot(host).ocr_mask; 1040a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED; 1041a45c6cb8SMadhusudhan Chikkature 1042a45c6cb8SMadhusudhan Chikkature if (pdata->slots[host->slot_id].wires >= 4) 1043a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 1044a45c6cb8SMadhusudhan Chikkature 10451b331e69SKim Kyuwon omap_hsmmc_init(host); 1046a45c6cb8SMadhusudhan Chikkature 1047a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 1048a45c6cb8SMadhusudhan Chikkature ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED, 1049a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 1050a45c6cb8SMadhusudhan Chikkature if (ret) { 1051a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 1052a45c6cb8SMadhusudhan Chikkature goto err_irq; 1053a45c6cb8SMadhusudhan Chikkature } 1054a45c6cb8SMadhusudhan Chikkature 1055a45c6cb8SMadhusudhan Chikkature if (pdata->init != NULL) { 1056a45c6cb8SMadhusudhan Chikkature if (pdata->init(&pdev->dev) != 0) { 1057a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1058a45c6cb8SMadhusudhan Chikkature "Unable to configure MMC IRQs\n"); 1059a45c6cb8SMadhusudhan Chikkature goto err_irq_cd_init; 1060a45c6cb8SMadhusudhan Chikkature } 1061a45c6cb8SMadhusudhan Chikkature } 1062a45c6cb8SMadhusudhan Chikkature 1063a45c6cb8SMadhusudhan Chikkature /* Request IRQ for card detect */ 1064a45c6cb8SMadhusudhan Chikkature if ((mmc_slot(host).card_detect_irq) && (mmc_slot(host).card_detect)) { 1065a45c6cb8SMadhusudhan Chikkature ret = request_irq(mmc_slot(host).card_detect_irq, 1066a45c6cb8SMadhusudhan Chikkature omap_mmc_cd_handler, 1067a45c6cb8SMadhusudhan Chikkature IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 1068a45c6cb8SMadhusudhan Chikkature | IRQF_DISABLED, 1069a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 1070a45c6cb8SMadhusudhan Chikkature if (ret) { 1071a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1072a45c6cb8SMadhusudhan Chikkature "Unable to grab MMC CD IRQ\n"); 1073a45c6cb8SMadhusudhan Chikkature goto err_irq_cd; 1074a45c6cb8SMadhusudhan Chikkature } 1075a45c6cb8SMadhusudhan Chikkature } 1076a45c6cb8SMadhusudhan Chikkature 1077a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK); 1078a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 1079a45c6cb8SMadhusudhan Chikkature 1080a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 1081a45c6cb8SMadhusudhan Chikkature 1082a45c6cb8SMadhusudhan Chikkature if (host->pdata->slots[host->slot_id].name != NULL) { 1083a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 1084a45c6cb8SMadhusudhan Chikkature if (ret < 0) 1085a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 1086a45c6cb8SMadhusudhan Chikkature } 1087a45c6cb8SMadhusudhan Chikkature if (mmc_slot(host).card_detect_irq && mmc_slot(host).card_detect && 1088a45c6cb8SMadhusudhan Chikkature host->pdata->slots[host->slot_id].get_cover_state) { 1089a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, 1090a45c6cb8SMadhusudhan Chikkature &dev_attr_cover_switch); 1091a45c6cb8SMadhusudhan Chikkature if (ret < 0) 1092a45c6cb8SMadhusudhan Chikkature goto err_cover_switch; 1093a45c6cb8SMadhusudhan Chikkature } 1094a45c6cb8SMadhusudhan Chikkature 1095a45c6cb8SMadhusudhan Chikkature return 0; 1096a45c6cb8SMadhusudhan Chikkature 1097a45c6cb8SMadhusudhan Chikkature err_cover_switch: 1098a45c6cb8SMadhusudhan Chikkature device_remove_file(&mmc->class_dev, &dev_attr_cover_switch); 1099a45c6cb8SMadhusudhan Chikkature err_slot_name: 1100a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 1101a45c6cb8SMadhusudhan Chikkature err_irq_cd: 1102a45c6cb8SMadhusudhan Chikkature free_irq(mmc_slot(host).card_detect_irq, host); 1103a45c6cb8SMadhusudhan Chikkature err_irq_cd_init: 1104a45c6cb8SMadhusudhan Chikkature free_irq(host->irq, host); 1105a45c6cb8SMadhusudhan Chikkature err_irq: 1106a45c6cb8SMadhusudhan Chikkature clk_disable(host->fclk); 1107a45c6cb8SMadhusudhan Chikkature clk_disable(host->iclk); 1108a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 1109a45c6cb8SMadhusudhan Chikkature clk_put(host->iclk); 1110a45c6cb8SMadhusudhan Chikkature if (host->dbclk_enabled) { 1111a45c6cb8SMadhusudhan Chikkature clk_disable(host->dbclk); 1112a45c6cb8SMadhusudhan Chikkature clk_put(host->dbclk); 1113a45c6cb8SMadhusudhan Chikkature } 1114a45c6cb8SMadhusudhan Chikkature 1115a45c6cb8SMadhusudhan Chikkature err1: 1116a45c6cb8SMadhusudhan Chikkature iounmap(host->base); 1117a45c6cb8SMadhusudhan Chikkature err: 1118a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "Probe Failed\n"); 1119a45c6cb8SMadhusudhan Chikkature release_mem_region(res->start, res->end - res->start + 1); 1120a45c6cb8SMadhusudhan Chikkature if (host) 1121a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 1122a45c6cb8SMadhusudhan Chikkature return ret; 1123a45c6cb8SMadhusudhan Chikkature } 1124a45c6cb8SMadhusudhan Chikkature 1125a45c6cb8SMadhusudhan Chikkature static int omap_mmc_remove(struct platform_device *pdev) 1126a45c6cb8SMadhusudhan Chikkature { 1127a45c6cb8SMadhusudhan Chikkature struct mmc_omap_host *host = platform_get_drvdata(pdev); 1128a45c6cb8SMadhusudhan Chikkature struct resource *res; 1129a45c6cb8SMadhusudhan Chikkature 1130a45c6cb8SMadhusudhan Chikkature if (host) { 1131a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 1132a45c6cb8SMadhusudhan Chikkature if (host->pdata->cleanup) 1133a45c6cb8SMadhusudhan Chikkature host->pdata->cleanup(&pdev->dev); 1134a45c6cb8SMadhusudhan Chikkature free_irq(host->irq, host); 1135a45c6cb8SMadhusudhan Chikkature if (mmc_slot(host).card_detect_irq) 1136a45c6cb8SMadhusudhan Chikkature free_irq(mmc_slot(host).card_detect_irq, host); 1137a45c6cb8SMadhusudhan Chikkature flush_scheduled_work(); 1138a45c6cb8SMadhusudhan Chikkature 1139a45c6cb8SMadhusudhan Chikkature clk_disable(host->fclk); 1140a45c6cb8SMadhusudhan Chikkature clk_disable(host->iclk); 1141a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 1142a45c6cb8SMadhusudhan Chikkature clk_put(host->iclk); 1143a45c6cb8SMadhusudhan Chikkature if (host->dbclk_enabled) { 1144a45c6cb8SMadhusudhan Chikkature clk_disable(host->dbclk); 1145a45c6cb8SMadhusudhan Chikkature clk_put(host->dbclk); 1146a45c6cb8SMadhusudhan Chikkature } 1147a45c6cb8SMadhusudhan Chikkature 1148a45c6cb8SMadhusudhan Chikkature mmc_free_host(host->mmc); 1149a45c6cb8SMadhusudhan Chikkature iounmap(host->base); 1150a45c6cb8SMadhusudhan Chikkature } 1151a45c6cb8SMadhusudhan Chikkature 1152a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1153a45c6cb8SMadhusudhan Chikkature if (res) 1154a45c6cb8SMadhusudhan Chikkature release_mem_region(res->start, res->end - res->start + 1); 1155a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, NULL); 1156a45c6cb8SMadhusudhan Chikkature 1157a45c6cb8SMadhusudhan Chikkature return 0; 1158a45c6cb8SMadhusudhan Chikkature } 1159a45c6cb8SMadhusudhan Chikkature 1160a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_PM 1161a45c6cb8SMadhusudhan Chikkature static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state) 1162a45c6cb8SMadhusudhan Chikkature { 1163a45c6cb8SMadhusudhan Chikkature int ret = 0; 1164a45c6cb8SMadhusudhan Chikkature struct mmc_omap_host *host = platform_get_drvdata(pdev); 1165a45c6cb8SMadhusudhan Chikkature 1166a45c6cb8SMadhusudhan Chikkature if (host && host->suspended) 1167a45c6cb8SMadhusudhan Chikkature return 0; 1168a45c6cb8SMadhusudhan Chikkature 1169a45c6cb8SMadhusudhan Chikkature if (host) { 1170a45c6cb8SMadhusudhan Chikkature ret = mmc_suspend_host(host->mmc, state); 1171a45c6cb8SMadhusudhan Chikkature if (ret == 0) { 1172a45c6cb8SMadhusudhan Chikkature host->suspended = 1; 1173a45c6cb8SMadhusudhan Chikkature 1174a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ISE, 0); 1175a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, IE, 0); 1176a45c6cb8SMadhusudhan Chikkature 1177a45c6cb8SMadhusudhan Chikkature if (host->pdata->suspend) { 1178a45c6cb8SMadhusudhan Chikkature ret = host->pdata->suspend(&pdev->dev, 1179a45c6cb8SMadhusudhan Chikkature host->slot_id); 1180a45c6cb8SMadhusudhan Chikkature if (ret) 1181a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1182a45c6cb8SMadhusudhan Chikkature "Unable to handle MMC board" 1183a45c6cb8SMadhusudhan Chikkature " level suspend\n"); 1184a45c6cb8SMadhusudhan Chikkature } 1185a45c6cb8SMadhusudhan Chikkature 1186eb250826SDavid Brownell if (host->id == OMAP_MMC1_DEVID 1187eb250826SDavid Brownell && !(OMAP_HSMMC_READ(host->base, HCTL) 1188eb250826SDavid Brownell & SDVSDET)) { 1189a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1190a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) 1191a45c6cb8SMadhusudhan Chikkature & SDVSCLR); 1192a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1193a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) 1194a45c6cb8SMadhusudhan Chikkature | SDVS30); 1195a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1196a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) 1197a45c6cb8SMadhusudhan Chikkature | SDBP); 1198a45c6cb8SMadhusudhan Chikkature } 1199a45c6cb8SMadhusudhan Chikkature 1200a45c6cb8SMadhusudhan Chikkature clk_disable(host->fclk); 1201a45c6cb8SMadhusudhan Chikkature clk_disable(host->iclk); 1202a45c6cb8SMadhusudhan Chikkature clk_disable(host->dbclk); 1203a45c6cb8SMadhusudhan Chikkature } 1204a45c6cb8SMadhusudhan Chikkature 1205a45c6cb8SMadhusudhan Chikkature } 1206a45c6cb8SMadhusudhan Chikkature return ret; 1207a45c6cb8SMadhusudhan Chikkature } 1208a45c6cb8SMadhusudhan Chikkature 1209a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 1210a45c6cb8SMadhusudhan Chikkature static int omap_mmc_resume(struct platform_device *pdev) 1211a45c6cb8SMadhusudhan Chikkature { 1212a45c6cb8SMadhusudhan Chikkature int ret = 0; 1213a45c6cb8SMadhusudhan Chikkature struct mmc_omap_host *host = platform_get_drvdata(pdev); 1214a45c6cb8SMadhusudhan Chikkature 1215a45c6cb8SMadhusudhan Chikkature if (host && !host->suspended) 1216a45c6cb8SMadhusudhan Chikkature return 0; 1217a45c6cb8SMadhusudhan Chikkature 1218a45c6cb8SMadhusudhan Chikkature if (host) { 1219a45c6cb8SMadhusudhan Chikkature 1220a45c6cb8SMadhusudhan Chikkature ret = clk_enable(host->fclk); 1221a45c6cb8SMadhusudhan Chikkature if (ret) 1222a45c6cb8SMadhusudhan Chikkature goto clk_en_err; 1223a45c6cb8SMadhusudhan Chikkature 1224a45c6cb8SMadhusudhan Chikkature ret = clk_enable(host->iclk); 1225a45c6cb8SMadhusudhan Chikkature if (ret) { 1226a45c6cb8SMadhusudhan Chikkature clk_disable(host->fclk); 1227a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 1228a45c6cb8SMadhusudhan Chikkature goto clk_en_err; 1229a45c6cb8SMadhusudhan Chikkature } 1230a45c6cb8SMadhusudhan Chikkature 1231a45c6cb8SMadhusudhan Chikkature if (clk_enable(host->dbclk) != 0) 1232a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1233a45c6cb8SMadhusudhan Chikkature "Enabling debounce clk failed\n"); 1234a45c6cb8SMadhusudhan Chikkature 12351b331e69SKim Kyuwon omap_hsmmc_init(host); 12361b331e69SKim Kyuwon 1237a45c6cb8SMadhusudhan Chikkature if (host->pdata->resume) { 1238a45c6cb8SMadhusudhan Chikkature ret = host->pdata->resume(&pdev->dev, host->slot_id); 1239a45c6cb8SMadhusudhan Chikkature if (ret) 1240a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1241a45c6cb8SMadhusudhan Chikkature "Unmask interrupt failed\n"); 1242a45c6cb8SMadhusudhan Chikkature } 1243a45c6cb8SMadhusudhan Chikkature 1244a45c6cb8SMadhusudhan Chikkature /* Notify the core to resume the host */ 1245a45c6cb8SMadhusudhan Chikkature ret = mmc_resume_host(host->mmc); 1246a45c6cb8SMadhusudhan Chikkature if (ret == 0) 1247a45c6cb8SMadhusudhan Chikkature host->suspended = 0; 1248a45c6cb8SMadhusudhan Chikkature } 1249a45c6cb8SMadhusudhan Chikkature 1250a45c6cb8SMadhusudhan Chikkature return ret; 1251a45c6cb8SMadhusudhan Chikkature 1252a45c6cb8SMadhusudhan Chikkature clk_en_err: 1253a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1254a45c6cb8SMadhusudhan Chikkature "Failed to enable MMC clocks during resume\n"); 1255a45c6cb8SMadhusudhan Chikkature return ret; 1256a45c6cb8SMadhusudhan Chikkature } 1257a45c6cb8SMadhusudhan Chikkature 1258a45c6cb8SMadhusudhan Chikkature #else 1259a45c6cb8SMadhusudhan Chikkature #define omap_mmc_suspend NULL 1260a45c6cb8SMadhusudhan Chikkature #define omap_mmc_resume NULL 1261a45c6cb8SMadhusudhan Chikkature #endif 1262a45c6cb8SMadhusudhan Chikkature 1263a45c6cb8SMadhusudhan Chikkature static struct platform_driver omap_mmc_driver = { 1264a45c6cb8SMadhusudhan Chikkature .probe = omap_mmc_probe, 1265a45c6cb8SMadhusudhan Chikkature .remove = omap_mmc_remove, 1266a45c6cb8SMadhusudhan Chikkature .suspend = omap_mmc_suspend, 1267a45c6cb8SMadhusudhan Chikkature .resume = omap_mmc_resume, 1268a45c6cb8SMadhusudhan Chikkature .driver = { 1269a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 1270a45c6cb8SMadhusudhan Chikkature .owner = THIS_MODULE, 1271a45c6cb8SMadhusudhan Chikkature }, 1272a45c6cb8SMadhusudhan Chikkature }; 1273a45c6cb8SMadhusudhan Chikkature 1274a45c6cb8SMadhusudhan Chikkature static int __init omap_mmc_init(void) 1275a45c6cb8SMadhusudhan Chikkature { 1276a45c6cb8SMadhusudhan Chikkature /* Register the MMC driver */ 1277a45c6cb8SMadhusudhan Chikkature return platform_driver_register(&omap_mmc_driver); 1278a45c6cb8SMadhusudhan Chikkature } 1279a45c6cb8SMadhusudhan Chikkature 1280a45c6cb8SMadhusudhan Chikkature static void __exit omap_mmc_cleanup(void) 1281a45c6cb8SMadhusudhan Chikkature { 1282a45c6cb8SMadhusudhan Chikkature /* Unregister MMC driver */ 1283a45c6cb8SMadhusudhan Chikkature platform_driver_unregister(&omap_mmc_driver); 1284a45c6cb8SMadhusudhan Chikkature } 1285a45c6cb8SMadhusudhan Chikkature 1286a45c6cb8SMadhusudhan Chikkature module_init(omap_mmc_init); 1287a45c6cb8SMadhusudhan Chikkature module_exit(omap_mmc_cleanup); 1288a45c6cb8SMadhusudhan Chikkature 1289a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 1290a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 1291a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 1292a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 1293