1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20ac330f44SAndy Shevchenko #include <linux/kernel.h> 21d900f712SDenis Karpov #include <linux/debugfs.h> 22c5c98927SRussell King #include <linux/dmaengine.h> 23d900f712SDenis Karpov #include <linux/seq_file.h> 24031cd037SFelipe Balbi #include <linux/sizes.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 29a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 30a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 3146856a68SRajendra Nayak #include <linux/of.h> 322cd3a2a5SAndreas Fenkart #include <linux/of_irq.h> 3346856a68SRajendra Nayak #include <linux/of_gpio.h> 3446856a68SRajendra Nayak #include <linux/of_device.h> 35ee526d51SBalaji T K #include <linux/omap-dmaengine.h> 36a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 3713189e78SJarkko Lavinen #include <linux/mmc/core.h> 3893caf8e6SAdrian Hunter #include <linux/mmc/mmc.h> 3941afa314SNeilBrown #include <linux/mmc/slot-gpio.h> 40a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 412cd3a2a5SAndreas Fenkart #include <linux/irq.h> 42db0fefc5SAdrian Hunter #include <linux/gpio.h> 43db0fefc5SAdrian Hunter #include <linux/regulator/consumer.h> 4446b76035SDaniel Mack #include <linux/pinctrl/consumer.h> 45fa4aa2d4SBalaji T K #include <linux/pm_runtime.h> 4655143438SAndreas Fenkart #include <linux/platform_data/hsmmc-omap.h> 47a45c6cb8SMadhusudhan Chikkature 48a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 4911dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS 0x0014 50a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 51a2e77152SBalaji T K #define OMAP_HSMMC_SDMASA 0x0100 52a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 57a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 58a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 59a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 60bb0635f0SAndreas Fenkart #define OMAP_HSMMC_PSTATE 0x0124 61a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 62a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 63a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 64a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 65a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 66a2e77152SBalaji T K #define OMAP_HSMMC_AC12 0x013C 67a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 68a45c6cb8SMadhusudhan Chikkature 69a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 70a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 71cd587096SHebbar, Gururaja #define HSS (1 << 21) 72a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 73a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 74eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 751b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 76a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 77a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 78a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 79a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 80a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 81a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 82a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 83a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 84ed164182SBalaji T K #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ 85a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 86a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 87a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 88a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 89a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 90a2e77152SBalaji T K #define ACEN_ACMD23 (2 << 2) 91a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 92a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 93a7e96879SVenkatraman S #define DMAE 0x1 94a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 95a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 96a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 97cd587096SHebbar, Gururaja #define HSPE (1 << 2) 985a52b08bSBalaji T K #define IWE (1 << 24) 9903b5d924SBalaji T K #define DDR (1 << 19) 1005a52b08bSBalaji T K #define CLKEXTFREE (1 << 16) 1015a52b08bSBalaji T K #define CTPL (1 << 11) 10273153010SJarkko Lavinen #define DW8 (1 << 5) 103a45c6cb8SMadhusudhan Chikkature #define OD 0x1 104a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 105a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 106a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 107a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 108a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 10911dd62a7SDenis Karpov #define SOFTRESET (1 << 1) 110a45c6cb8SMadhusudhan Chikkature 111f945901fSAndreas Fenkart /* PSTATE */ 112f945901fSAndreas Fenkart #define DLEV_DAT(x) (1 << (20 + (x))) 113f945901fSAndreas Fenkart 114a7e96879SVenkatraman S /* Interrupt masks for IE and ISE register */ 115a7e96879SVenkatraman S #define CC_EN (1 << 0) 116a7e96879SVenkatraman S #define TC_EN (1 << 1) 117a7e96879SVenkatraman S #define BWR_EN (1 << 4) 118a7e96879SVenkatraman S #define BRR_EN (1 << 5) 1192cd3a2a5SAndreas Fenkart #define CIRQ_EN (1 << 8) 120a7e96879SVenkatraman S #define ERR_EN (1 << 15) 121a7e96879SVenkatraman S #define CTO_EN (1 << 16) 122a7e96879SVenkatraman S #define CCRC_EN (1 << 17) 123a7e96879SVenkatraman S #define CEB_EN (1 << 18) 124a7e96879SVenkatraman S #define CIE_EN (1 << 19) 125a7e96879SVenkatraman S #define DTO_EN (1 << 20) 126a7e96879SVenkatraman S #define DCRC_EN (1 << 21) 127a7e96879SVenkatraman S #define DEB_EN (1 << 22) 128a2e77152SBalaji T K #define ACE_EN (1 << 24) 129a7e96879SVenkatraman S #define CERR_EN (1 << 28) 130a7e96879SVenkatraman S #define BADA_EN (1 << 29) 131a7e96879SVenkatraman S 132a2e77152SBalaji T K #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\ 133a7e96879SVenkatraman S DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ 134a7e96879SVenkatraman S BRR_EN | BWR_EN | TC_EN | CC_EN) 135a7e96879SVenkatraman S 136a2e77152SBalaji T K #define CNI (1 << 7) 137a2e77152SBalaji T K #define ACIE (1 << 4) 138a2e77152SBalaji T K #define ACEB (1 << 3) 139a2e77152SBalaji T K #define ACCE (1 << 2) 140a2e77152SBalaji T K #define ACTO (1 << 1) 141a2e77152SBalaji T K #define ACNE (1 << 0) 142a2e77152SBalaji T K 143fa4aa2d4SBalaji T K #define MMC_AUTOSUSPEND_DELAY 100 1441e881786SJianpeng Ma #define MMC_TIMEOUT_MS 20 /* 20 mSec */ 1451e881786SJianpeng Ma #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ 1466b206efeSAndy Shevchenko #define OMAP_MMC_MIN_CLOCK 400000 1476b206efeSAndy Shevchenko #define OMAP_MMC_MAX_CLOCK 52000000 1480005ae73SKishore Kadiyala #define DRIVER_NAME "omap_hsmmc" 149a45c6cb8SMadhusudhan Chikkature 150e99448ffSBalaji T K #define VDD_1V8 1800000 /* 180000 uV */ 151e99448ffSBalaji T K #define VDD_3V0 3000000 /* 300000 uV */ 152e99448ffSBalaji T K #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1) 153e99448ffSBalaji T K 154a45c6cb8SMadhusudhan Chikkature /* 155a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 156a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 157a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 158a45c6cb8SMadhusudhan Chikkature */ 159326119c9SAndreas Fenkart #define mmc_pdata(host) host->pdata 160a45c6cb8SMadhusudhan Chikkature 161a45c6cb8SMadhusudhan Chikkature /* 162a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 163a45c6cb8SMadhusudhan Chikkature */ 164a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 165a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 166a45c6cb8SMadhusudhan Chikkature 167a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 168a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 169a45c6cb8SMadhusudhan Chikkature 1709782aff8SPer Forlin struct omap_hsmmc_next { 1719782aff8SPer Forlin unsigned int dma_len; 1729782aff8SPer Forlin s32 cookie; 1739782aff8SPer Forlin }; 1749782aff8SPer Forlin 17570a3341aSDenis Karpov struct omap_hsmmc_host { 176a45c6cb8SMadhusudhan Chikkature struct device *dev; 177a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 178a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 179a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 180a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 181a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 182a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 183db0fefc5SAdrian Hunter /* 184db0fefc5SAdrian Hunter * vcc == configured supply 185db0fefc5SAdrian Hunter * vcc_aux == optional 186db0fefc5SAdrian Hunter * - MMC1, supply for DAT4..DAT7 187db0fefc5SAdrian Hunter * - MMC2/MMC2, external level shifter voltage supply, for 188db0fefc5SAdrian Hunter * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) 189db0fefc5SAdrian Hunter */ 190db0fefc5SAdrian Hunter struct regulator *vcc; 191db0fefc5SAdrian Hunter struct regulator *vcc_aux; 192e99448ffSBalaji T K struct regulator *pbias; 193e99448ffSBalaji T K bool pbias_enabled; 194a45c6cb8SMadhusudhan Chikkature void __iomem *base; 195a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 1964dffd7a2SAdrian Hunter spinlock_t irq_lock; /* Prevent races with irq handler */ 197a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 1980ccd76d4SJuha Yrjola unsigned int dma_sg_idx; 199a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 200a3621465SAdrian Hunter unsigned char power_mode; 201a45c6cb8SMadhusudhan Chikkature int suspended; 2020a82e06eSTony Lindgren u32 con; 2030a82e06eSTony Lindgren u32 hctl; 2040a82e06eSTony Lindgren u32 sysctl; 2050a82e06eSTony Lindgren u32 capa; 206a45c6cb8SMadhusudhan Chikkature int irq; 2072cd3a2a5SAndreas Fenkart int wake_irq; 208a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 209c5c98927SRussell King struct dma_chan *tx_chan; 210c5c98927SRussell King struct dma_chan *rx_chan; 2114a694dc9SAdrian Hunter int response_busy; 21211dd62a7SDenis Karpov int context_loss; 213b62f6228SAdrian Hunter int protect_card; 214b62f6228SAdrian Hunter int reqs_blocked; 215db0fefc5SAdrian Hunter int use_reg; 216b417577dSAdrian Hunter int req_in_progress; 2176e3076c2SBalaji T K unsigned long clk_rate; 218a2e77152SBalaji T K unsigned int flags; 2192cd3a2a5SAndreas Fenkart #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */ 2202cd3a2a5SAndreas Fenkart #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */ 2212cd3a2a5SAndreas Fenkart #define HSMMC_WAKE_IRQ_ENABLED (1 << 2) 2229782aff8SPer Forlin struct omap_hsmmc_next next_data; 22355143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata; 224b5cd43f0SAndreas Fenkart 225b5cd43f0SAndreas Fenkart /* To handle board related suspend/resume functionality for MMC */ 22680412ca8SAndreas Fenkart int (*suspend)(struct device *dev); 22780412ca8SAndreas Fenkart int (*resume)(struct device *dev); 228b5cd43f0SAndreas Fenkart 229b5cd43f0SAndreas Fenkart /* return MMC cover switch state, can be NULL if not supported. 230b5cd43f0SAndreas Fenkart * 231b5cd43f0SAndreas Fenkart * possible return values: 232b5cd43f0SAndreas Fenkart * 0 - closed 233b5cd43f0SAndreas Fenkart * 1 - open 234b5cd43f0SAndreas Fenkart */ 23580412ca8SAndreas Fenkart int (*get_cover_state)(struct device *dev); 236b5cd43f0SAndreas Fenkart 237b5cd43f0SAndreas Fenkart /* Card detection IRQs */ 238b5cd43f0SAndreas Fenkart int card_detect_irq; 239b5cd43f0SAndreas Fenkart 24080412ca8SAndreas Fenkart int (*card_detect)(struct device *dev); 24180412ca8SAndreas Fenkart int (*get_ro)(struct device *dev); 242b5cd43f0SAndreas Fenkart 243a45c6cb8SMadhusudhan Chikkature }; 244a45c6cb8SMadhusudhan Chikkature 24559445b10SNishanth Menon struct omap_mmc_of_data { 24659445b10SNishanth Menon u32 reg_offset; 24759445b10SNishanth Menon u8 controller_flags; 24859445b10SNishanth Menon }; 24959445b10SNishanth Menon 250bf129e1cSBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host); 251bf129e1cSBalaji T K 25280412ca8SAndreas Fenkart static int omap_hsmmc_card_detect(struct device *dev) 253db0fefc5SAdrian Hunter { 2549ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 255db0fefc5SAdrian Hunter 25641afa314SNeilBrown return mmc_gpio_get_cd(host->mmc); 257db0fefc5SAdrian Hunter } 258db0fefc5SAdrian Hunter 25980412ca8SAndreas Fenkart static int omap_hsmmc_get_wp(struct device *dev) 260db0fefc5SAdrian Hunter { 2619ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 262db0fefc5SAdrian Hunter 26341afa314SNeilBrown return mmc_gpio_get_ro(host->mmc); 264db0fefc5SAdrian Hunter } 265db0fefc5SAdrian Hunter 26680412ca8SAndreas Fenkart static int omap_hsmmc_get_cover_state(struct device *dev) 267db0fefc5SAdrian Hunter { 2689ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 269db0fefc5SAdrian Hunter 27041afa314SNeilBrown return mmc_gpio_get_cd(host->mmc); 271db0fefc5SAdrian Hunter } 272db0fefc5SAdrian Hunter 273b702b106SAdrian Hunter #ifdef CONFIG_REGULATOR 274b702b106SAdrian Hunter 27580412ca8SAndreas Fenkart static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd) 276db0fefc5SAdrian Hunter { 277db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 278db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 279db0fefc5SAdrian Hunter int ret = 0; 280db0fefc5SAdrian Hunter 281db0fefc5SAdrian Hunter /* 282db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 283db0fefc5SAdrian Hunter * voltage always-on regulator. 284db0fefc5SAdrian Hunter */ 285db0fefc5SAdrian Hunter if (!host->vcc) 286db0fefc5SAdrian Hunter return 0; 287db0fefc5SAdrian Hunter 288326119c9SAndreas Fenkart if (mmc_pdata(host)->before_set_reg) 28980412ca8SAndreas Fenkart mmc_pdata(host)->before_set_reg(dev, power_on, vdd); 290db0fefc5SAdrian Hunter 291e99448ffSBalaji T K if (host->pbias) { 292e99448ffSBalaji T K if (host->pbias_enabled == 1) { 293e99448ffSBalaji T K ret = regulator_disable(host->pbias); 294e99448ffSBalaji T K if (!ret) 295e99448ffSBalaji T K host->pbias_enabled = 0; 296e99448ffSBalaji T K } 297e99448ffSBalaji T K regulator_set_voltage(host->pbias, VDD_3V0, VDD_3V0); 298e99448ffSBalaji T K } 299e99448ffSBalaji T K 300db0fefc5SAdrian Hunter /* 301db0fefc5SAdrian Hunter * Assume Vcc regulator is used only to power the card ... OMAP 302db0fefc5SAdrian Hunter * VDDS is used to power the pins, optionally with a transceiver to 303db0fefc5SAdrian Hunter * support cards using voltages other than VDDS (1.8V nominal). When a 304db0fefc5SAdrian Hunter * transceiver is used, DAT3..7 are muxed as transceiver control pins. 305db0fefc5SAdrian Hunter * 306db0fefc5SAdrian Hunter * In some cases this regulator won't support enable/disable; 307db0fefc5SAdrian Hunter * e.g. it's a fixed rail for a WLAN chip. 308db0fefc5SAdrian Hunter * 309db0fefc5SAdrian Hunter * In other cases vcc_aux switches interface power. Example, for 310db0fefc5SAdrian Hunter * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 311db0fefc5SAdrian Hunter * chips/cards need an interface voltage rail too. 312db0fefc5SAdrian Hunter */ 313db0fefc5SAdrian Hunter if (power_on) { 314987fd49bSBalaji T K if (host->vcc) 31599fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 316db0fefc5SAdrian Hunter /* Enable interface voltage rail, if needed */ 317db0fefc5SAdrian Hunter if (ret == 0 && host->vcc_aux) { 318db0fefc5SAdrian Hunter ret = regulator_enable(host->vcc_aux); 319987fd49bSBalaji T K if (ret < 0 && host->vcc) 32099fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 32199fc5131SLinus Walleij host->vcc, 0); 322db0fefc5SAdrian Hunter } 323db0fefc5SAdrian Hunter } else { 32499fc5131SLinus Walleij /* Shut down the rail */ 3256da20c89SAdrian Hunter if (host->vcc_aux) 326db0fefc5SAdrian Hunter ret = regulator_disable(host->vcc_aux); 327987fd49bSBalaji T K if (host->vcc) { 32899fc5131SLinus Walleij /* Then proceed to shut down the local regulator */ 32999fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 33099fc5131SLinus Walleij host->vcc, 0); 33199fc5131SLinus Walleij } 332db0fefc5SAdrian Hunter } 333db0fefc5SAdrian Hunter 334e99448ffSBalaji T K if (host->pbias) { 335e99448ffSBalaji T K if (vdd <= VDD_165_195) 336e99448ffSBalaji T K ret = regulator_set_voltage(host->pbias, VDD_1V8, 337e99448ffSBalaji T K VDD_1V8); 338e99448ffSBalaji T K else 339e99448ffSBalaji T K ret = regulator_set_voltage(host->pbias, VDD_3V0, 340e99448ffSBalaji T K VDD_3V0); 341e99448ffSBalaji T K if (ret < 0) 342e99448ffSBalaji T K goto error_set_power; 343e99448ffSBalaji T K 344e99448ffSBalaji T K if (host->pbias_enabled == 0) { 345e99448ffSBalaji T K ret = regulator_enable(host->pbias); 346e99448ffSBalaji T K if (!ret) 347e99448ffSBalaji T K host->pbias_enabled = 1; 348e99448ffSBalaji T K } 349e99448ffSBalaji T K } 350e99448ffSBalaji T K 351326119c9SAndreas Fenkart if (mmc_pdata(host)->after_set_reg) 35280412ca8SAndreas Fenkart mmc_pdata(host)->after_set_reg(dev, power_on, vdd); 353db0fefc5SAdrian Hunter 354e99448ffSBalaji T K error_set_power: 355db0fefc5SAdrian Hunter return ret; 356db0fefc5SAdrian Hunter } 357db0fefc5SAdrian Hunter 358db0fefc5SAdrian Hunter static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 359db0fefc5SAdrian Hunter { 360db0fefc5SAdrian Hunter struct regulator *reg; 36164be9782Skishore kadiyala int ocr_value = 0; 362db0fefc5SAdrian Hunter 363f2ddc1daSBalaji T K reg = devm_regulator_get(host->dev, "vmmc"); 364db0fefc5SAdrian Hunter if (IS_ERR(reg)) { 365987fd49bSBalaji T K dev_err(host->dev, "unable to get vmmc regulator %ld\n", 366987fd49bSBalaji T K PTR_ERR(reg)); 3671fdc90fbSNeilBrown return PTR_ERR(reg); 368db0fefc5SAdrian Hunter } else { 369db0fefc5SAdrian Hunter host->vcc = reg; 37064be9782Skishore kadiyala ocr_value = mmc_regulator_get_ocrmask(reg); 371326119c9SAndreas Fenkart if (!mmc_pdata(host)->ocr_mask) { 372326119c9SAndreas Fenkart mmc_pdata(host)->ocr_mask = ocr_value; 37364be9782Skishore kadiyala } else { 374326119c9SAndreas Fenkart if (!(mmc_pdata(host)->ocr_mask & ocr_value)) { 3752cecdf00SRajendra Nayak dev_err(host->dev, "ocrmask %x is not supported\n", 376326119c9SAndreas Fenkart mmc_pdata(host)->ocr_mask); 377326119c9SAndreas Fenkart mmc_pdata(host)->ocr_mask = 0; 37864be9782Skishore kadiyala return -EINVAL; 37964be9782Skishore kadiyala } 38064be9782Skishore kadiyala } 381987fd49bSBalaji T K } 382326119c9SAndreas Fenkart mmc_pdata(host)->set_power = omap_hsmmc_set_power; 383db0fefc5SAdrian Hunter 384db0fefc5SAdrian Hunter /* Allow an aux regulator */ 385f2ddc1daSBalaji T K reg = devm_regulator_get_optional(host->dev, "vmmc_aux"); 386db0fefc5SAdrian Hunter host->vcc_aux = IS_ERR(reg) ? NULL : reg; 387db0fefc5SAdrian Hunter 388e99448ffSBalaji T K reg = devm_regulator_get_optional(host->dev, "pbias"); 389e99448ffSBalaji T K host->pbias = IS_ERR(reg) ? NULL : reg; 390e99448ffSBalaji T K 391b1c1df7aSBalaji T K /* For eMMC do not power off when not in sleep state */ 392326119c9SAndreas Fenkart if (mmc_pdata(host)->no_regulator_off_init) 393b1c1df7aSBalaji T K return 0; 394db0fefc5SAdrian Hunter /* 395987fd49bSBalaji T K * To disable boot_on regulator, enable regulator 396987fd49bSBalaji T K * to increase usecount and then disable it. 397db0fefc5SAdrian Hunter */ 398987fd49bSBalaji T K if ((host->vcc && regulator_is_enabled(host->vcc) > 0) || 399e840ce13SAdrian Hunter (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) { 400326119c9SAndreas Fenkart int vdd = ffs(mmc_pdata(host)->ocr_mask) - 1; 401e840ce13SAdrian Hunter 40280412ca8SAndreas Fenkart mmc_pdata(host)->set_power(host->dev, 1, vdd); 40380412ca8SAndreas Fenkart mmc_pdata(host)->set_power(host->dev, 0, 0); 404db0fefc5SAdrian Hunter } 405db0fefc5SAdrian Hunter 406db0fefc5SAdrian Hunter return 0; 407db0fefc5SAdrian Hunter } 408db0fefc5SAdrian Hunter 409db0fefc5SAdrian Hunter static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 410db0fefc5SAdrian Hunter { 411326119c9SAndreas Fenkart mmc_pdata(host)->set_power = NULL; 412db0fefc5SAdrian Hunter } 413db0fefc5SAdrian Hunter 414b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 415b702b106SAdrian Hunter { 416b702b106SAdrian Hunter return 1; 417b702b106SAdrian Hunter } 418b702b106SAdrian Hunter 419b702b106SAdrian Hunter #else 420b702b106SAdrian Hunter 421b702b106SAdrian Hunter static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 422b702b106SAdrian Hunter { 423b702b106SAdrian Hunter return -EINVAL; 424b702b106SAdrian Hunter } 425b702b106SAdrian Hunter 426b702b106SAdrian Hunter static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 427b702b106SAdrian Hunter { 428b702b106SAdrian Hunter } 429b702b106SAdrian Hunter 430b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 431b702b106SAdrian Hunter { 432b702b106SAdrian Hunter return 0; 433b702b106SAdrian Hunter } 434b702b106SAdrian Hunter 435b702b106SAdrian Hunter #endif 436b702b106SAdrian Hunter 43741afa314SNeilBrown static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id); 43841afa314SNeilBrown 43941afa314SNeilBrown static int omap_hsmmc_gpio_init(struct mmc_host *mmc, 44041afa314SNeilBrown struct omap_hsmmc_host *host, 4411e363e3bSAndreas Fenkart struct omap_hsmmc_platform_data *pdata) 442b702b106SAdrian Hunter { 443b702b106SAdrian Hunter int ret; 444b702b106SAdrian Hunter 445326119c9SAndreas Fenkart if (gpio_is_valid(pdata->switch_pin)) { 446326119c9SAndreas Fenkart if (pdata->cover) 447b5cd43f0SAndreas Fenkart host->get_cover_state = 448b702b106SAdrian Hunter omap_hsmmc_get_cover_state; 449b702b106SAdrian Hunter else 450b5cd43f0SAndreas Fenkart host->card_detect = omap_hsmmc_card_detect; 451b5cd43f0SAndreas Fenkart host->card_detect_irq = 452326119c9SAndreas Fenkart gpio_to_irq(pdata->switch_pin); 45341afa314SNeilBrown mmc_gpio_set_cd_isr(mmc, omap_hsmmc_detect); 45441afa314SNeilBrown ret = mmc_gpio_request_cd(mmc, pdata->switch_pin, 0); 455b702b106SAdrian Hunter if (ret) 456b702b106SAdrian Hunter return ret; 457326119c9SAndreas Fenkart } else { 458326119c9SAndreas Fenkart pdata->switch_pin = -EINVAL; 459326119c9SAndreas Fenkart } 460b702b106SAdrian Hunter 461326119c9SAndreas Fenkart if (gpio_is_valid(pdata->gpio_wp)) { 462b5cd43f0SAndreas Fenkart host->get_ro = omap_hsmmc_get_wp; 46341afa314SNeilBrown ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp); 464b702b106SAdrian Hunter if (ret) 46541afa314SNeilBrown return ret; 466326119c9SAndreas Fenkart } else { 467326119c9SAndreas Fenkart pdata->gpio_wp = -EINVAL; 468326119c9SAndreas Fenkart } 469b702b106SAdrian Hunter 470b702b106SAdrian Hunter return 0; 471b702b106SAdrian Hunter } 472b702b106SAdrian Hunter 473a45c6cb8SMadhusudhan Chikkature /* 474e0c7f99bSAndy Shevchenko * Start clock to the card 475e0c7f99bSAndy Shevchenko */ 476e0c7f99bSAndy Shevchenko static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 477e0c7f99bSAndy Shevchenko { 478e0c7f99bSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 479e0c7f99bSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 480e0c7f99bSAndy Shevchenko } 481e0c7f99bSAndy Shevchenko 482e0c7f99bSAndy Shevchenko /* 483a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 484a45c6cb8SMadhusudhan Chikkature */ 48570a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 486a45c6cb8SMadhusudhan Chikkature { 487a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 488a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 489a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 4907122bbb0SMasanari Iida dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); 491a45c6cb8SMadhusudhan Chikkature } 492a45c6cb8SMadhusudhan Chikkature 49393caf8e6SAdrian Hunter static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 49493caf8e6SAdrian Hunter struct mmc_command *cmd) 495b417577dSAdrian Hunter { 4962cd3a2a5SAndreas Fenkart u32 irq_mask = INT_EN_MASK; 4972cd3a2a5SAndreas Fenkart unsigned long flags; 498b417577dSAdrian Hunter 499b417577dSAdrian Hunter if (host->use_dma) 5002cd3a2a5SAndreas Fenkart irq_mask &= ~(BRR_EN | BWR_EN); 501b417577dSAdrian Hunter 50293caf8e6SAdrian Hunter /* Disable timeout for erases */ 50393caf8e6SAdrian Hunter if (cmd->opcode == MMC_ERASE) 504a7e96879SVenkatraman S irq_mask &= ~DTO_EN; 50593caf8e6SAdrian Hunter 5062cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 507b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 508b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 5092cd3a2a5SAndreas Fenkart 5102cd3a2a5SAndreas Fenkart /* latch pending CIRQ, but don't signal MMC core */ 5112cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 5122cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 513b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 5142cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 515b417577dSAdrian Hunter } 516b417577dSAdrian Hunter 517b417577dSAdrian Hunter static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 518b417577dSAdrian Hunter { 5192cd3a2a5SAndreas Fenkart u32 irq_mask = 0; 5202cd3a2a5SAndreas Fenkart unsigned long flags; 5212cd3a2a5SAndreas Fenkart 5222cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 5232cd3a2a5SAndreas Fenkart /* no transfer running but need to keep cirq if enabled */ 5242cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 5252cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 5262cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 5272cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 528b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 5292cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 530b417577dSAdrian Hunter } 531b417577dSAdrian Hunter 532ac330f44SAndy Shevchenko /* Calculate divisor for the given clock frequency */ 533d83b6e03SBalaji TK static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 534ac330f44SAndy Shevchenko { 535ac330f44SAndy Shevchenko u16 dsor = 0; 536ac330f44SAndy Shevchenko 537ac330f44SAndy Shevchenko if (ios->clock) { 538d83b6e03SBalaji TK dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 539ed164182SBalaji T K if (dsor > CLKD_MAX) 540ed164182SBalaji T K dsor = CLKD_MAX; 541ac330f44SAndy Shevchenko } 542ac330f44SAndy Shevchenko 543ac330f44SAndy Shevchenko return dsor; 544ac330f44SAndy Shevchenko } 545ac330f44SAndy Shevchenko 5465934df2fSAndy Shevchenko static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 5475934df2fSAndy Shevchenko { 5485934df2fSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5495934df2fSAndy Shevchenko unsigned long regval; 5505934df2fSAndy Shevchenko unsigned long timeout; 551cd587096SHebbar, Gururaja unsigned long clkdiv; 5525934df2fSAndy Shevchenko 5538986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 5545934df2fSAndy Shevchenko 5555934df2fSAndy Shevchenko omap_hsmmc_stop_clock(host); 5565934df2fSAndy Shevchenko 5575934df2fSAndy Shevchenko regval = OMAP_HSMMC_READ(host->base, SYSCTL); 5585934df2fSAndy Shevchenko regval = regval & ~(CLKD_MASK | DTO_MASK); 559cd587096SHebbar, Gururaja clkdiv = calc_divisor(host, ios); 560cd587096SHebbar, Gururaja regval = regval | (clkdiv << 6) | (DTO << 16); 5615934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 5625934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 5635934df2fSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 5645934df2fSAndy Shevchenko 5655934df2fSAndy Shevchenko /* Wait till the ICS bit is set */ 5665934df2fSAndy Shevchenko timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 5675934df2fSAndy Shevchenko while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 5685934df2fSAndy Shevchenko && time_before(jiffies, timeout)) 5695934df2fSAndy Shevchenko cpu_relax(); 5705934df2fSAndy Shevchenko 571cd587096SHebbar, Gururaja /* 572cd587096SHebbar, Gururaja * Enable High-Speed Support 573cd587096SHebbar, Gururaja * Pre-Requisites 574cd587096SHebbar, Gururaja * - Controller should support High-Speed-Enable Bit 575cd587096SHebbar, Gururaja * - Controller should not be using DDR Mode 576cd587096SHebbar, Gururaja * - Controller should advertise that it supports High Speed 577cd587096SHebbar, Gururaja * in capabilities register 578cd587096SHebbar, Gururaja * - MMC/SD clock coming out of controller > 25MHz 579cd587096SHebbar, Gururaja */ 580326119c9SAndreas Fenkart if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) && 5815438ad95SSeungwon Jeon (ios->timing != MMC_TIMING_MMC_DDR52) && 582903101a8SUlf Hansson (ios->timing != MMC_TIMING_UHS_DDR50) && 583cd587096SHebbar, Gururaja ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 584cd587096SHebbar, Gururaja regval = OMAP_HSMMC_READ(host->base, HCTL); 585cd587096SHebbar, Gururaja if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 586cd587096SHebbar, Gururaja regval |= HSPE; 587cd587096SHebbar, Gururaja else 588cd587096SHebbar, Gururaja regval &= ~HSPE; 589cd587096SHebbar, Gururaja 590cd587096SHebbar, Gururaja OMAP_HSMMC_WRITE(host->base, HCTL, regval); 591cd587096SHebbar, Gururaja } 592cd587096SHebbar, Gururaja 5935934df2fSAndy Shevchenko omap_hsmmc_start_clock(host); 5945934df2fSAndy Shevchenko } 5955934df2fSAndy Shevchenko 5963796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 5973796fb8aSAndy Shevchenko { 5983796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5993796fb8aSAndy Shevchenko u32 con; 6003796fb8aSAndy Shevchenko 6013796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 602903101a8SUlf Hansson if (ios->timing == MMC_TIMING_MMC_DDR52 || 603903101a8SUlf Hansson ios->timing == MMC_TIMING_UHS_DDR50) 60403b5d924SBalaji T K con |= DDR; /* configure in DDR mode */ 60503b5d924SBalaji T K else 60603b5d924SBalaji T K con &= ~DDR; 6073796fb8aSAndy Shevchenko switch (ios->bus_width) { 6083796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_8: 6093796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 6103796fb8aSAndy Shevchenko break; 6113796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_4: 6123796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 6133796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 6143796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 6153796fb8aSAndy Shevchenko break; 6163796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_1: 6173796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 6183796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 6193796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 6203796fb8aSAndy Shevchenko break; 6213796fb8aSAndy Shevchenko } 6223796fb8aSAndy Shevchenko } 6233796fb8aSAndy Shevchenko 6243796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 6253796fb8aSAndy Shevchenko { 6263796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6273796fb8aSAndy Shevchenko u32 con; 6283796fb8aSAndy Shevchenko 6293796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 6303796fb8aSAndy Shevchenko if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 6313796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | OD); 6323796fb8aSAndy Shevchenko else 6333796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 6343796fb8aSAndy Shevchenko } 6353796fb8aSAndy Shevchenko 63611dd62a7SDenis Karpov #ifdef CONFIG_PM 63711dd62a7SDenis Karpov 63811dd62a7SDenis Karpov /* 63911dd62a7SDenis Karpov * Restore the MMC host context, if it was lost as result of a 64011dd62a7SDenis Karpov * power state change. 64111dd62a7SDenis Karpov */ 64270a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 64311dd62a7SDenis Karpov { 64411dd62a7SDenis Karpov struct mmc_ios *ios = &host->mmc->ios; 6453796fb8aSAndy Shevchenko u32 hctl, capa; 64611dd62a7SDenis Karpov unsigned long timeout; 64711dd62a7SDenis Karpov 6480a82e06eSTony Lindgren if (host->con == OMAP_HSMMC_READ(host->base, CON) && 6490a82e06eSTony Lindgren host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && 6500a82e06eSTony Lindgren host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && 6510a82e06eSTony Lindgren host->capa == OMAP_HSMMC_READ(host->base, CAPA)) 6520a82e06eSTony Lindgren return 0; 6530a82e06eSTony Lindgren 6540a82e06eSTony Lindgren host->context_loss++; 6550a82e06eSTony Lindgren 656c2200efbSBalaji T K if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 65711dd62a7SDenis Karpov if (host->power_mode != MMC_POWER_OFF && 65811dd62a7SDenis Karpov (1 << ios->vdd) <= MMC_VDD_23_24) 65911dd62a7SDenis Karpov hctl = SDVS18; 66011dd62a7SDenis Karpov else 66111dd62a7SDenis Karpov hctl = SDVS30; 66211dd62a7SDenis Karpov capa = VS30 | VS18; 66311dd62a7SDenis Karpov } else { 66411dd62a7SDenis Karpov hctl = SDVS18; 66511dd62a7SDenis Karpov capa = VS18; 66611dd62a7SDenis Karpov } 66711dd62a7SDenis Karpov 6685a52b08bSBalaji T K if (host->mmc->caps & MMC_CAP_SDIO_IRQ) 6695a52b08bSBalaji T K hctl |= IWE; 6705a52b08bSBalaji T K 67111dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 67211dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | hctl); 67311dd62a7SDenis Karpov 67411dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CAPA, 67511dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA) | capa); 67611dd62a7SDenis Karpov 67711dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 67811dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 67911dd62a7SDenis Karpov 68011dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 68111dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 68211dd62a7SDenis Karpov && time_before(jiffies, timeout)) 68311dd62a7SDenis Karpov ; 68411dd62a7SDenis Karpov 6852cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 6862cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 6872cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 68811dd62a7SDenis Karpov 68911dd62a7SDenis Karpov /* Do not initialize card-specific things if the power is off */ 69011dd62a7SDenis Karpov if (host->power_mode == MMC_POWER_OFF) 69111dd62a7SDenis Karpov goto out; 69211dd62a7SDenis Karpov 6933796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 69411dd62a7SDenis Karpov 6955934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 69611dd62a7SDenis Karpov 6973796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 6983796fb8aSAndy Shevchenko 69911dd62a7SDenis Karpov out: 7000a82e06eSTony Lindgren dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", 7010a82e06eSTony Lindgren host->context_loss); 70211dd62a7SDenis Karpov return 0; 70311dd62a7SDenis Karpov } 70411dd62a7SDenis Karpov 70511dd62a7SDenis Karpov /* 70611dd62a7SDenis Karpov * Save the MMC host context (store the number of power state changes so far). 70711dd62a7SDenis Karpov */ 70870a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 70911dd62a7SDenis Karpov { 7100a82e06eSTony Lindgren host->con = OMAP_HSMMC_READ(host->base, CON); 7110a82e06eSTony Lindgren host->hctl = OMAP_HSMMC_READ(host->base, HCTL); 7120a82e06eSTony Lindgren host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); 7130a82e06eSTony Lindgren host->capa = OMAP_HSMMC_READ(host->base, CAPA); 71411dd62a7SDenis Karpov } 71511dd62a7SDenis Karpov 71611dd62a7SDenis Karpov #else 71711dd62a7SDenis Karpov 71870a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 71911dd62a7SDenis Karpov { 72011dd62a7SDenis Karpov return 0; 72111dd62a7SDenis Karpov } 72211dd62a7SDenis Karpov 72370a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 72411dd62a7SDenis Karpov { 72511dd62a7SDenis Karpov } 72611dd62a7SDenis Karpov 72711dd62a7SDenis Karpov #endif 72811dd62a7SDenis Karpov 729a45c6cb8SMadhusudhan Chikkature /* 730a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 731a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 732a45c6cb8SMadhusudhan Chikkature */ 73370a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host) 734a45c6cb8SMadhusudhan Chikkature { 735a45c6cb8SMadhusudhan Chikkature int reg = 0; 736a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 737a45c6cb8SMadhusudhan Chikkature 738b62f6228SAdrian Hunter if (host->protect_card) 739b62f6228SAdrian Hunter return; 740b62f6228SAdrian Hunter 741a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 742b417577dSAdrian Hunter 743b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 744a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 745a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 746a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 747a45c6cb8SMadhusudhan Chikkature 748a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 749a7e96879SVenkatraman S while ((reg != CC_EN) && time_before(jiffies, timeout)) 750a7e96879SVenkatraman S reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; 751a45c6cb8SMadhusudhan Chikkature 752a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 753a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 754c653a6d4SAdrian Hunter 755c653a6d4SAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 756c653a6d4SAdrian Hunter OMAP_HSMMC_READ(host->base, STAT); 757c653a6d4SAdrian Hunter 758a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 759a45c6cb8SMadhusudhan Chikkature } 760a45c6cb8SMadhusudhan Chikkature 761a45c6cb8SMadhusudhan Chikkature static inline 76270a3341aSDenis Karpov int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 763a45c6cb8SMadhusudhan Chikkature { 764a45c6cb8SMadhusudhan Chikkature int r = 1; 765a45c6cb8SMadhusudhan Chikkature 766b5cd43f0SAndreas Fenkart if (host->get_cover_state) 76780412ca8SAndreas Fenkart r = host->get_cover_state(host->dev); 768a45c6cb8SMadhusudhan Chikkature return r; 769a45c6cb8SMadhusudhan Chikkature } 770a45c6cb8SMadhusudhan Chikkature 771a45c6cb8SMadhusudhan Chikkature static ssize_t 77270a3341aSDenis Karpov omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 773a45c6cb8SMadhusudhan Chikkature char *buf) 774a45c6cb8SMadhusudhan Chikkature { 775a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 77670a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 777a45c6cb8SMadhusudhan Chikkature 77870a3341aSDenis Karpov return sprintf(buf, "%s\n", 77970a3341aSDenis Karpov omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 780a45c6cb8SMadhusudhan Chikkature } 781a45c6cb8SMadhusudhan Chikkature 78270a3341aSDenis Karpov static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 783a45c6cb8SMadhusudhan Chikkature 784a45c6cb8SMadhusudhan Chikkature static ssize_t 78570a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 786a45c6cb8SMadhusudhan Chikkature char *buf) 787a45c6cb8SMadhusudhan Chikkature { 788a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 78970a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 790a45c6cb8SMadhusudhan Chikkature 791326119c9SAndreas Fenkart return sprintf(buf, "%s\n", mmc_pdata(host)->name); 792a45c6cb8SMadhusudhan Chikkature } 793a45c6cb8SMadhusudhan Chikkature 79470a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 795a45c6cb8SMadhusudhan Chikkature 796a45c6cb8SMadhusudhan Chikkature /* 797a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 798a45c6cb8SMadhusudhan Chikkature */ 799a45c6cb8SMadhusudhan Chikkature static void 80070a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 801a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 802a45c6cb8SMadhusudhan Chikkature { 803a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 804a45c6cb8SMadhusudhan Chikkature 8058986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 806a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 807a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 808a45c6cb8SMadhusudhan Chikkature 80993caf8e6SAdrian Hunter omap_hsmmc_enable_irq(host, cmd); 810a45c6cb8SMadhusudhan Chikkature 8114a694dc9SAdrian Hunter host->response_busy = 0; 812a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 813a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 814a45c6cb8SMadhusudhan Chikkature resptype = 1; 8154a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 8164a694dc9SAdrian Hunter resptype = 3; 8174a694dc9SAdrian Hunter host->response_busy = 1; 8184a694dc9SAdrian Hunter } else 819a45c6cb8SMadhusudhan Chikkature resptype = 2; 820a45c6cb8SMadhusudhan Chikkature } 821a45c6cb8SMadhusudhan Chikkature 822a45c6cb8SMadhusudhan Chikkature /* 823a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 824a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 825a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 826a45c6cb8SMadhusudhan Chikkature */ 827a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 828a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 829a45c6cb8SMadhusudhan Chikkature 830a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 831a45c6cb8SMadhusudhan Chikkature 832a2e77152SBalaji T K if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) && 833a2e77152SBalaji T K host->mrq->sbc) { 834a2e77152SBalaji T K cmdreg |= ACEN_ACMD23; 835a2e77152SBalaji T K OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg); 836a2e77152SBalaji T K } 837a45c6cb8SMadhusudhan Chikkature if (data) { 838a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 839a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 840a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 841a45c6cb8SMadhusudhan Chikkature else 842a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 843a45c6cb8SMadhusudhan Chikkature } 844a45c6cb8SMadhusudhan Chikkature 845a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 846a7e96879SVenkatraman S cmdreg |= DMAE; 847a45c6cb8SMadhusudhan Chikkature 848b417577dSAdrian Hunter host->req_in_progress = 1; 8494dffd7a2SAdrian Hunter 850a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 851a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 852a45c6cb8SMadhusudhan Chikkature } 853a45c6cb8SMadhusudhan Chikkature 8540ccd76d4SJuha Yrjola static int 85570a3341aSDenis Karpov omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 8560ccd76d4SJuha Yrjola { 8570ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) 8580ccd76d4SJuha Yrjola return DMA_TO_DEVICE; 8590ccd76d4SJuha Yrjola else 8600ccd76d4SJuha Yrjola return DMA_FROM_DEVICE; 8610ccd76d4SJuha Yrjola } 8620ccd76d4SJuha Yrjola 863c5c98927SRussell King static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 864c5c98927SRussell King struct mmc_data *data) 865c5c98927SRussell King { 866c5c98927SRussell King return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 867c5c98927SRussell King } 868c5c98927SRussell King 869b417577dSAdrian Hunter static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 870b417577dSAdrian Hunter { 871b417577dSAdrian Hunter int dma_ch; 87231463b14SVenkatraman S unsigned long flags; 873b417577dSAdrian Hunter 87431463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 875b417577dSAdrian Hunter host->req_in_progress = 0; 876b417577dSAdrian Hunter dma_ch = host->dma_ch; 87731463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 878b417577dSAdrian Hunter 879b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 880b417577dSAdrian Hunter /* Do not complete the request if DMA is still in progress */ 881b417577dSAdrian Hunter if (mrq->data && host->use_dma && dma_ch != -1) 882b417577dSAdrian Hunter return; 883b417577dSAdrian Hunter host->mrq = NULL; 884b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 885b417577dSAdrian Hunter } 886b417577dSAdrian Hunter 887a45c6cb8SMadhusudhan Chikkature /* 888a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 889a45c6cb8SMadhusudhan Chikkature */ 890a45c6cb8SMadhusudhan Chikkature static void 89170a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 892a45c6cb8SMadhusudhan Chikkature { 8934a694dc9SAdrian Hunter if (!data) { 8944a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 8954a694dc9SAdrian Hunter 89623050103SAdrian Hunter /* TC before CC from CMD6 - don't know why, but it happens */ 89723050103SAdrian Hunter if (host->cmd && host->cmd->opcode == 6 && 89823050103SAdrian Hunter host->response_busy) { 89923050103SAdrian Hunter host->response_busy = 0; 90023050103SAdrian Hunter return; 90123050103SAdrian Hunter } 90223050103SAdrian Hunter 903b417577dSAdrian Hunter omap_hsmmc_request_done(host, mrq); 9044a694dc9SAdrian Hunter return; 9054a694dc9SAdrian Hunter } 9064a694dc9SAdrian Hunter 907a45c6cb8SMadhusudhan Chikkature host->data = NULL; 908a45c6cb8SMadhusudhan Chikkature 909a45c6cb8SMadhusudhan Chikkature if (!data->error) 910a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 911a45c6cb8SMadhusudhan Chikkature else 912a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 913a45c6cb8SMadhusudhan Chikkature 914bf129e1cSBalaji T K if (data->stop && (data->error || !host->mrq->sbc)) 915fe852273SMing Lei omap_hsmmc_start_command(host, data->stop, NULL); 916bf129e1cSBalaji T K else 917bf129e1cSBalaji T K omap_hsmmc_request_done(host, data->mrq); 918a45c6cb8SMadhusudhan Chikkature } 919a45c6cb8SMadhusudhan Chikkature 920a45c6cb8SMadhusudhan Chikkature /* 921a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 922a45c6cb8SMadhusudhan Chikkature */ 923a45c6cb8SMadhusudhan Chikkature static void 92470a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 925a45c6cb8SMadhusudhan Chikkature { 926bf129e1cSBalaji T K if (host->mrq->sbc && (host->cmd == host->mrq->sbc) && 927a2e77152SBalaji T K !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) { 9282177fa94SBalaji T K host->cmd = NULL; 929bf129e1cSBalaji T K omap_hsmmc_start_dma_transfer(host); 930bf129e1cSBalaji T K omap_hsmmc_start_command(host, host->mrq->cmd, 931bf129e1cSBalaji T K host->mrq->data); 932bf129e1cSBalaji T K return; 933bf129e1cSBalaji T K } 934bf129e1cSBalaji T K 9352177fa94SBalaji T K host->cmd = NULL; 9362177fa94SBalaji T K 937a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 938a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 939a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 940a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 941a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 942a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 943a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 944a45c6cb8SMadhusudhan Chikkature } else { 945a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 946a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 947a45c6cb8SMadhusudhan Chikkature } 948a45c6cb8SMadhusudhan Chikkature } 949b417577dSAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) 950d4b2c375SBalaji T K omap_hsmmc_request_done(host, host->mrq); 951a45c6cb8SMadhusudhan Chikkature } 952a45c6cb8SMadhusudhan Chikkature 953a45c6cb8SMadhusudhan Chikkature /* 954a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 955a45c6cb8SMadhusudhan Chikkature */ 95670a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 957a45c6cb8SMadhusudhan Chikkature { 958b417577dSAdrian Hunter int dma_ch; 95931463b14SVenkatraman S unsigned long flags; 960b417577dSAdrian Hunter 96182788ff5SJarkko Lavinen host->data->error = errno; 962a45c6cb8SMadhusudhan Chikkature 96331463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 964b417577dSAdrian Hunter dma_ch = host->dma_ch; 965b417577dSAdrian Hunter host->dma_ch = -1; 96631463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 967b417577dSAdrian Hunter 968b417577dSAdrian Hunter if (host->use_dma && dma_ch != -1) { 969c5c98927SRussell King struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 970c5c98927SRussell King 971c5c98927SRussell King dmaengine_terminate_all(chan); 972c5c98927SRussell King dma_unmap_sg(chan->device->dev, 973c5c98927SRussell King host->data->sg, host->data->sg_len, 97470a3341aSDenis Karpov omap_hsmmc_get_dma_dir(host, host->data)); 975c5c98927SRussell King 976053bf34fSPer Forlin host->data->host_cookie = 0; 977a45c6cb8SMadhusudhan Chikkature } 978a45c6cb8SMadhusudhan Chikkature host->data = NULL; 979a45c6cb8SMadhusudhan Chikkature } 980a45c6cb8SMadhusudhan Chikkature 981a45c6cb8SMadhusudhan Chikkature /* 982a45c6cb8SMadhusudhan Chikkature * Readable error output 983a45c6cb8SMadhusudhan Chikkature */ 984a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 985699b958bSAdrian Hunter static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 986a45c6cb8SMadhusudhan Chikkature { 987a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 98870a3341aSDenis Karpov static const char *omap_hsmmc_status_bits[] = { 989699b958bSAdrian Hunter "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 990699b958bSAdrian Hunter "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 991699b958bSAdrian Hunter "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 992699b958bSAdrian Hunter "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 993a45c6cb8SMadhusudhan Chikkature }; 994a45c6cb8SMadhusudhan Chikkature char res[256]; 995a45c6cb8SMadhusudhan Chikkature char *buf = res; 996a45c6cb8SMadhusudhan Chikkature int len, i; 997a45c6cb8SMadhusudhan Chikkature 998a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 999a45c6cb8SMadhusudhan Chikkature buf += len; 1000a45c6cb8SMadhusudhan Chikkature 100170a3341aSDenis Karpov for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 1002a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 100370a3341aSDenis Karpov len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 1004a45c6cb8SMadhusudhan Chikkature buf += len; 1005a45c6cb8SMadhusudhan Chikkature } 1006a45c6cb8SMadhusudhan Chikkature 10078986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 1008a45c6cb8SMadhusudhan Chikkature } 1009699b958bSAdrian Hunter #else 1010699b958bSAdrian Hunter static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 1011699b958bSAdrian Hunter u32 status) 1012699b958bSAdrian Hunter { 1013699b958bSAdrian Hunter } 1014a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 1015a45c6cb8SMadhusudhan Chikkature 10163ebf74b1SJean Pihet /* 10173ebf74b1SJean Pihet * MMC controller internal state machines reset 10183ebf74b1SJean Pihet * 10193ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 10203ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 10213ebf74b1SJean Pihet * Can be called from interrupt context 10223ebf74b1SJean Pihet */ 102370a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 10243ebf74b1SJean Pihet unsigned long bit) 10253ebf74b1SJean Pihet { 10263ebf74b1SJean Pihet unsigned long i = 0; 10271e881786SJianpeng Ma unsigned long limit = MMC_TIMEOUT_US; 10283ebf74b1SJean Pihet 10293ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 10303ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 10313ebf74b1SJean Pihet 103207ad64b6SMadhusudhan Chikkature /* 103307ad64b6SMadhusudhan Chikkature * OMAP4 ES2 and greater has an updated reset logic. 103407ad64b6SMadhusudhan Chikkature * Monitor a 0->1 transition first 103507ad64b6SMadhusudhan Chikkature */ 1036326119c9SAndreas Fenkart if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) { 1037b432b4b3Skishore kadiyala while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 103807ad64b6SMadhusudhan Chikkature && (i++ < limit)) 10391e881786SJianpeng Ma udelay(1); 104007ad64b6SMadhusudhan Chikkature } 104107ad64b6SMadhusudhan Chikkature i = 0; 104207ad64b6SMadhusudhan Chikkature 10433ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 10443ebf74b1SJean Pihet (i++ < limit)) 10451e881786SJianpeng Ma udelay(1); 10463ebf74b1SJean Pihet 10473ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 10483ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 10493ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 10503ebf74b1SJean Pihet __func__); 10513ebf74b1SJean Pihet } 1052a45c6cb8SMadhusudhan Chikkature 105325e1897bSBalaji T K static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, 105425e1897bSBalaji T K int err, int end_cmd) 1055ae4bf788SVenkatraman S { 105625e1897bSBalaji T K if (end_cmd) { 105794d4f272SBalaji T K omap_hsmmc_reset_controller_fsm(host, SRC); 105825e1897bSBalaji T K if (host->cmd) 1059ae4bf788SVenkatraman S host->cmd->error = err; 106025e1897bSBalaji T K } 1061ae4bf788SVenkatraman S 1062ae4bf788SVenkatraman S if (host->data) { 1063ae4bf788SVenkatraman S omap_hsmmc_reset_controller_fsm(host, SRD); 1064ae4bf788SVenkatraman S omap_hsmmc_dma_cleanup(host, err); 1065dc7745bdSBalaji T K } else if (host->mrq && host->mrq->cmd) 1066dc7745bdSBalaji T K host->mrq->cmd->error = err; 1067ae4bf788SVenkatraman S } 1068ae4bf788SVenkatraman S 1069b417577dSAdrian Hunter static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1070a45c6cb8SMadhusudhan Chikkature { 1071a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 1072b417577dSAdrian Hunter int end_cmd = 0, end_trans = 0; 1073a2e77152SBalaji T K int error = 0; 1074a45c6cb8SMadhusudhan Chikkature 1075a45c6cb8SMadhusudhan Chikkature data = host->data; 10768986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1077a45c6cb8SMadhusudhan Chikkature 1078a7e96879SVenkatraman S if (status & ERR_EN) { 1079699b958bSAdrian Hunter omap_hsmmc_dbg_report_irq(host, status); 10804a694dc9SAdrian Hunter 1081a7e96879SVenkatraman S if (status & (CTO_EN | CCRC_EN)) 1082a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1083a7e96879SVenkatraman S if (status & (CTO_EN | DTO_EN)) 108425e1897bSBalaji T K hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); 1085a7e96879SVenkatraman S else if (status & (CCRC_EN | DCRC_EN)) 108625e1897bSBalaji T K hsmmc_command_incomplete(host, -EILSEQ, end_cmd); 108725e1897bSBalaji T K 1088a2e77152SBalaji T K if (status & ACE_EN) { 1089a2e77152SBalaji T K u32 ac12; 1090a2e77152SBalaji T K ac12 = OMAP_HSMMC_READ(host->base, AC12); 1091a2e77152SBalaji T K if (!(ac12 & ACNE) && host->mrq->sbc) { 1092a2e77152SBalaji T K end_cmd = 1; 1093a2e77152SBalaji T K if (ac12 & ACTO) 1094a2e77152SBalaji T K error = -ETIMEDOUT; 1095a2e77152SBalaji T K else if (ac12 & (ACCE | ACEB | ACIE)) 1096a2e77152SBalaji T K error = -EILSEQ; 1097a2e77152SBalaji T K host->mrq->sbc->error = error; 1098a2e77152SBalaji T K hsmmc_command_incomplete(host, error, end_cmd); 1099a2e77152SBalaji T K } 1100a2e77152SBalaji T K dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12); 1101a2e77152SBalaji T K } 1102ae4bf788SVenkatraman S if (host->data || host->response_busy) { 110325e1897bSBalaji T K end_trans = !end_cmd; 1104ae4bf788SVenkatraman S host->response_busy = 0; 1105a45c6cb8SMadhusudhan Chikkature } 1106a45c6cb8SMadhusudhan Chikkature } 1107a45c6cb8SMadhusudhan Chikkature 11087472bab2SFrancesco Lavra OMAP_HSMMC_WRITE(host->base, STAT, status); 1109a7e96879SVenkatraman S if (end_cmd || ((status & CC_EN) && host->cmd)) 111070a3341aSDenis Karpov omap_hsmmc_cmd_done(host, host->cmd); 1111a7e96879SVenkatraman S if ((end_trans || (status & TC_EN)) && host->mrq) 111270a3341aSDenis Karpov omap_hsmmc_xfer_done(host, data); 1113b417577dSAdrian Hunter } 1114a45c6cb8SMadhusudhan Chikkature 1115b417577dSAdrian Hunter /* 1116b417577dSAdrian Hunter * MMC controller IRQ handler 1117b417577dSAdrian Hunter */ 1118b417577dSAdrian Hunter static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1119b417577dSAdrian Hunter { 1120b417577dSAdrian Hunter struct omap_hsmmc_host *host = dev_id; 1121b417577dSAdrian Hunter int status; 1122b417577dSAdrian Hunter 1123b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 11242cd3a2a5SAndreas Fenkart while (status & (INT_EN_MASK | CIRQ_EN)) { 11252cd3a2a5SAndreas Fenkart if (host->req_in_progress) 1126b417577dSAdrian Hunter omap_hsmmc_do_irq(host, status); 11271f6b9fa4SVenkatraman S 11282cd3a2a5SAndreas Fenkart if (status & CIRQ_EN) 11292cd3a2a5SAndreas Fenkart mmc_signal_sdio_irq(host->mmc); 11302cd3a2a5SAndreas Fenkart 1131b417577dSAdrian Hunter /* Flush posted write */ 1132b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 11331f6b9fa4SVenkatraman S } 11344dffd7a2SAdrian Hunter 1135a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1136a45c6cb8SMadhusudhan Chikkature } 1137a45c6cb8SMadhusudhan Chikkature 11382cd3a2a5SAndreas Fenkart static irqreturn_t omap_hsmmc_wake_irq(int irq, void *dev_id) 11392cd3a2a5SAndreas Fenkart { 11402cd3a2a5SAndreas Fenkart struct omap_hsmmc_host *host = dev_id; 11412cd3a2a5SAndreas Fenkart 11422cd3a2a5SAndreas Fenkart /* cirq is level triggered, disable to avoid infinite loop */ 11432cd3a2a5SAndreas Fenkart spin_lock(&host->irq_lock); 11442cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_WAKE_IRQ_ENABLED) { 11452cd3a2a5SAndreas Fenkart disable_irq_nosync(host->wake_irq); 11462cd3a2a5SAndreas Fenkart host->flags &= ~HSMMC_WAKE_IRQ_ENABLED; 11472cd3a2a5SAndreas Fenkart } 11482cd3a2a5SAndreas Fenkart spin_unlock(&host->irq_lock); 11492cd3a2a5SAndreas Fenkart pm_request_resume(host->dev); /* no use counter */ 11502cd3a2a5SAndreas Fenkart 11512cd3a2a5SAndreas Fenkart return IRQ_HANDLED; 11522cd3a2a5SAndreas Fenkart } 11532cd3a2a5SAndreas Fenkart 115470a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host) 1155e13bb300SAdrian Hunter { 1156e13bb300SAdrian Hunter unsigned long i; 1157e13bb300SAdrian Hunter 1158e13bb300SAdrian Hunter OMAP_HSMMC_WRITE(host->base, HCTL, 1159e13bb300SAdrian Hunter OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1160e13bb300SAdrian Hunter for (i = 0; i < loops_per_jiffy; i++) { 1161e13bb300SAdrian Hunter if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1162e13bb300SAdrian Hunter break; 1163e13bb300SAdrian Hunter cpu_relax(); 1164e13bb300SAdrian Hunter } 1165e13bb300SAdrian Hunter } 1166e13bb300SAdrian Hunter 1167a45c6cb8SMadhusudhan Chikkature /* 1168eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 1169eb250826SDavid Brownell * 1170eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1171eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1172eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 1173a45c6cb8SMadhusudhan Chikkature */ 117470a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1175a45c6cb8SMadhusudhan Chikkature { 1176a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 1177a45c6cb8SMadhusudhan Chikkature int ret; 1178a45c6cb8SMadhusudhan Chikkature 1179a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 1180fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 1181cd03d9a8SRajendra Nayak if (host->dbclk) 118294c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 1183a45c6cb8SMadhusudhan Chikkature 1184a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 118580412ca8SAndreas Fenkart ret = mmc_pdata(host)->set_power(host->dev, 0, 0); 1186a45c6cb8SMadhusudhan Chikkature 1187a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 11882bec0893SAdrian Hunter if (!ret) 118980412ca8SAndreas Fenkart ret = mmc_pdata(host)->set_power(host->dev, 1, vdd); 1190fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1191cd03d9a8SRajendra Nayak if (host->dbclk) 119294c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 11932bec0893SAdrian Hunter 1194a45c6cb8SMadhusudhan Chikkature if (ret != 0) 1195a45c6cb8SMadhusudhan Chikkature goto err; 1196a45c6cb8SMadhusudhan Chikkature 1197a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1198a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1199a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1200eb250826SDavid Brownell 1201a45c6cb8SMadhusudhan Chikkature /* 1202a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 1203a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 120470a3341aSDenis Karpov * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1205a45c6cb8SMadhusudhan Chikkature * 1206eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 1207eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1208eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 1209eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1210eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 1211eb250826SDavid Brownell * 1212eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 1213eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1214eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1215a45c6cb8SMadhusudhan Chikkature */ 1216eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 1217a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 1218eb250826SDavid Brownell else 1219eb250826SDavid Brownell reg_val |= SDVS30; 1220a45c6cb8SMadhusudhan Chikkature 1221a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1222e13bb300SAdrian Hunter set_sd_bus_power(host); 1223a45c6cb8SMadhusudhan Chikkature 1224a45c6cb8SMadhusudhan Chikkature return 0; 1225a45c6cb8SMadhusudhan Chikkature err: 1226b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1227a45c6cb8SMadhusudhan Chikkature return ret; 1228a45c6cb8SMadhusudhan Chikkature } 1229a45c6cb8SMadhusudhan Chikkature 1230b62f6228SAdrian Hunter /* Protect the card while the cover is open */ 1231b62f6228SAdrian Hunter static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1232b62f6228SAdrian Hunter { 1233b5cd43f0SAndreas Fenkart if (!host->get_cover_state) 1234b62f6228SAdrian Hunter return; 1235b62f6228SAdrian Hunter 1236b62f6228SAdrian Hunter host->reqs_blocked = 0; 123780412ca8SAndreas Fenkart if (host->get_cover_state(host->dev)) { 1238b62f6228SAdrian Hunter if (host->protect_card) { 12392cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is closed, " 1240b62f6228SAdrian Hunter "card is now accessible\n", 1241b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1242b62f6228SAdrian Hunter host->protect_card = 0; 1243b62f6228SAdrian Hunter } 1244b62f6228SAdrian Hunter } else { 1245b62f6228SAdrian Hunter if (!host->protect_card) { 12462cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is open, " 1247b62f6228SAdrian Hunter "card is now inaccessible\n", 1248b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1249b62f6228SAdrian Hunter host->protect_card = 1; 1250b62f6228SAdrian Hunter } 1251b62f6228SAdrian Hunter } 1252b62f6228SAdrian Hunter } 1253b62f6228SAdrian Hunter 1254a45c6cb8SMadhusudhan Chikkature /* 12557efab4f3SNeilBrown * irq handler to notify the core about card insertion/removal 1256a45c6cb8SMadhusudhan Chikkature */ 12577efab4f3SNeilBrown static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id) 1258a45c6cb8SMadhusudhan Chikkature { 12597efab4f3SNeilBrown struct omap_hsmmc_host *host = dev_id; 1260a6b2240dSAdrian Hunter int carddetect; 1261249d0fa9SDavid Brownell 1262a45c6cb8SMadhusudhan Chikkature sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1263a6b2240dSAdrian Hunter 1264b5cd43f0SAndreas Fenkart if (host->card_detect) 126580412ca8SAndreas Fenkart carddetect = host->card_detect(host->dev); 1266b62f6228SAdrian Hunter else { 1267b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 1268a6b2240dSAdrian Hunter carddetect = -ENOSYS; 1269b62f6228SAdrian Hunter } 1270a6b2240dSAdrian Hunter 1271cdeebaddSMadhusudhan Chikkature if (carddetect) 1272a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1273cdeebaddSMadhusudhan Chikkature else 1274a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 50) / 1000); 1275a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1276a45c6cb8SMadhusudhan Chikkature } 1277a45c6cb8SMadhusudhan Chikkature 1278c5c98927SRussell King static void omap_hsmmc_dma_callback(void *param) 12790ccd76d4SJuha Yrjola { 1280c5c98927SRussell King struct omap_hsmmc_host *host = param; 1281c5c98927SRussell King struct dma_chan *chan; 1282770d7432SAdrian Hunter struct mmc_data *data; 1283c5c98927SRussell King int req_in_progress; 1284a45c6cb8SMadhusudhan Chikkature 1285c5c98927SRussell King spin_lock_irq(&host->irq_lock); 1286b417577dSAdrian Hunter if (host->dma_ch < 0) { 1287c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1288a45c6cb8SMadhusudhan Chikkature return; 1289b417577dSAdrian Hunter } 1290a45c6cb8SMadhusudhan Chikkature 1291770d7432SAdrian Hunter data = host->mrq->data; 1292c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 12939782aff8SPer Forlin if (!data->host_cookie) 1294c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1295c5c98927SRussell King data->sg, data->sg_len, 1296b417577dSAdrian Hunter omap_hsmmc_get_dma_dir(host, data)); 1297b417577dSAdrian Hunter 1298b417577dSAdrian Hunter req_in_progress = host->req_in_progress; 1299a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1300c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1301b417577dSAdrian Hunter 1302b417577dSAdrian Hunter /* If DMA has finished after TC, complete the request */ 1303b417577dSAdrian Hunter if (!req_in_progress) { 1304b417577dSAdrian Hunter struct mmc_request *mrq = host->mrq; 1305b417577dSAdrian Hunter 1306b417577dSAdrian Hunter host->mrq = NULL; 1307b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 1308b417577dSAdrian Hunter } 1309a45c6cb8SMadhusudhan Chikkature } 1310a45c6cb8SMadhusudhan Chikkature 13119782aff8SPer Forlin static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 13129782aff8SPer Forlin struct mmc_data *data, 1313c5c98927SRussell King struct omap_hsmmc_next *next, 131426b88520SRussell King struct dma_chan *chan) 13159782aff8SPer Forlin { 13169782aff8SPer Forlin int dma_len; 13179782aff8SPer Forlin 13189782aff8SPer Forlin if (!next && data->host_cookie && 13199782aff8SPer Forlin data->host_cookie != host->next_data.cookie) { 13202cecdf00SRajendra Nayak dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 13219782aff8SPer Forlin " host->next_data.cookie %d\n", 13229782aff8SPer Forlin __func__, data->host_cookie, host->next_data.cookie); 13239782aff8SPer Forlin data->host_cookie = 0; 13249782aff8SPer Forlin } 13259782aff8SPer Forlin 13269782aff8SPer Forlin /* Check if next job is already prepared */ 1327b38313d6SDan Carpenter if (next || data->host_cookie != host->next_data.cookie) { 132826b88520SRussell King dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 13299782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 13309782aff8SPer Forlin 13319782aff8SPer Forlin } else { 13329782aff8SPer Forlin dma_len = host->next_data.dma_len; 13339782aff8SPer Forlin host->next_data.dma_len = 0; 13349782aff8SPer Forlin } 13359782aff8SPer Forlin 13369782aff8SPer Forlin 13379782aff8SPer Forlin if (dma_len == 0) 13389782aff8SPer Forlin return -EINVAL; 13399782aff8SPer Forlin 13409782aff8SPer Forlin if (next) { 13419782aff8SPer Forlin next->dma_len = dma_len; 13429782aff8SPer Forlin data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 13439782aff8SPer Forlin } else 13449782aff8SPer Forlin host->dma_len = dma_len; 13459782aff8SPer Forlin 13469782aff8SPer Forlin return 0; 13479782aff8SPer Forlin } 13489782aff8SPer Forlin 1349a45c6cb8SMadhusudhan Chikkature /* 1350a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 1351a45c6cb8SMadhusudhan Chikkature */ 13529d025334SBalaji T K static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host, 135370a3341aSDenis Karpov struct mmc_request *req) 1354a45c6cb8SMadhusudhan Chikkature { 135526b88520SRussell King struct dma_slave_config cfg; 135626b88520SRussell King struct dma_async_tx_descriptor *tx; 135726b88520SRussell King int ret = 0, i; 1358a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 1359c5c98927SRussell King struct dma_chan *chan; 1360a45c6cb8SMadhusudhan Chikkature 13610ccd76d4SJuha Yrjola /* Sanity check: all the SG entries must be aligned by block size. */ 1362a3f406f8SJarkko Lavinen for (i = 0; i < data->sg_len; i++) { 13630ccd76d4SJuha Yrjola struct scatterlist *sgl; 13640ccd76d4SJuha Yrjola 13650ccd76d4SJuha Yrjola sgl = data->sg + i; 13660ccd76d4SJuha Yrjola if (sgl->length % data->blksz) 13670ccd76d4SJuha Yrjola return -EINVAL; 13680ccd76d4SJuha Yrjola } 13690ccd76d4SJuha Yrjola if ((data->blksz % 4) != 0) 13700ccd76d4SJuha Yrjola /* REVISIT: The MMC buffer increments only when MSB is written. 13710ccd76d4SJuha Yrjola * Return error for blksz which is non multiple of four. 13720ccd76d4SJuha Yrjola */ 13730ccd76d4SJuha Yrjola return -EINVAL; 13740ccd76d4SJuha Yrjola 1375b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1376a45c6cb8SMadhusudhan Chikkature 1377c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 1378c5c98927SRussell King 1379c5c98927SRussell King cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA; 1380c5c98927SRussell King cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA; 1381c5c98927SRussell King cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1382c5c98927SRussell King cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1383c5c98927SRussell King cfg.src_maxburst = data->blksz / 4; 1384c5c98927SRussell King cfg.dst_maxburst = data->blksz / 4; 1385c5c98927SRussell King 1386c5c98927SRussell King ret = dmaengine_slave_config(chan, &cfg); 13879782aff8SPer Forlin if (ret) 13889782aff8SPer Forlin return ret; 1389a45c6cb8SMadhusudhan Chikkature 139026b88520SRussell King ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1391c5c98927SRussell King if (ret) 1392c5c98927SRussell King return ret; 1393a45c6cb8SMadhusudhan Chikkature 1394c5c98927SRussell King tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1395c5c98927SRussell King data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1396c5c98927SRussell King DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1397c5c98927SRussell King if (!tx) { 1398c5c98927SRussell King dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1399c5c98927SRussell King /* FIXME: cleanup */ 1400c5c98927SRussell King return -1; 1401c5c98927SRussell King } 1402c5c98927SRussell King 1403c5c98927SRussell King tx->callback = omap_hsmmc_dma_callback; 1404c5c98927SRussell King tx->callback_param = host; 1405c5c98927SRussell King 1406c5c98927SRussell King /* Does not fail */ 1407c5c98927SRussell King dmaengine_submit(tx); 1408c5c98927SRussell King 140926b88520SRussell King host->dma_ch = 1; 1410c5c98927SRussell King 1411a45c6cb8SMadhusudhan Chikkature return 0; 1412a45c6cb8SMadhusudhan Chikkature } 1413a45c6cb8SMadhusudhan Chikkature 141470a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host, 1415e2bf08d6SAdrian Hunter unsigned int timeout_ns, 1416e2bf08d6SAdrian Hunter unsigned int timeout_clks) 1417a45c6cb8SMadhusudhan Chikkature { 1418a45c6cb8SMadhusudhan Chikkature unsigned int timeout, cycle_ns; 1419a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 1420a45c6cb8SMadhusudhan Chikkature 1421a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1422a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1423a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 1424a45c6cb8SMadhusudhan Chikkature clkd = 1; 1425a45c6cb8SMadhusudhan Chikkature 14266e3076c2SBalaji T K cycle_ns = 1000000000 / (host->clk_rate / clkd); 1427e2bf08d6SAdrian Hunter timeout = timeout_ns / cycle_ns; 1428e2bf08d6SAdrian Hunter timeout += timeout_clks; 1429a45c6cb8SMadhusudhan Chikkature if (timeout) { 1430a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 1431a45c6cb8SMadhusudhan Chikkature dto += 1; 1432a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1433a45c6cb8SMadhusudhan Chikkature } 1434a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 1435a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1436a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 1437a45c6cb8SMadhusudhan Chikkature dto += 1; 1438a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 1439a45c6cb8SMadhusudhan Chikkature dto -= 13; 1440a45c6cb8SMadhusudhan Chikkature else 1441a45c6cb8SMadhusudhan Chikkature dto = 0; 1442a45c6cb8SMadhusudhan Chikkature if (dto > 14) 1443a45c6cb8SMadhusudhan Chikkature dto = 14; 1444a45c6cb8SMadhusudhan Chikkature } 1445a45c6cb8SMadhusudhan Chikkature 1446a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 1447a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 1448a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1449a45c6cb8SMadhusudhan Chikkature } 1450a45c6cb8SMadhusudhan Chikkature 14519d025334SBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host) 14529d025334SBalaji T K { 14539d025334SBalaji T K struct mmc_request *req = host->mrq; 14549d025334SBalaji T K struct dma_chan *chan; 14559d025334SBalaji T K 14569d025334SBalaji T K if (!req->data) 14579d025334SBalaji T K return; 14589d025334SBalaji T K OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 14599d025334SBalaji T K | (req->data->blocks << 16)); 14609d025334SBalaji T K set_data_timeout(host, req->data->timeout_ns, 14619d025334SBalaji T K req->data->timeout_clks); 14629d025334SBalaji T K chan = omap_hsmmc_get_dma_chan(host, req->data); 14639d025334SBalaji T K dma_async_issue_pending(chan); 14649d025334SBalaji T K } 14659d025334SBalaji T K 1466a45c6cb8SMadhusudhan Chikkature /* 1467a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 1468a45c6cb8SMadhusudhan Chikkature */ 1469a45c6cb8SMadhusudhan Chikkature static int 147070a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1471a45c6cb8SMadhusudhan Chikkature { 1472a45c6cb8SMadhusudhan Chikkature int ret; 1473a45c6cb8SMadhusudhan Chikkature host->data = req->data; 1474a45c6cb8SMadhusudhan Chikkature 1475a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 1476a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 1477e2bf08d6SAdrian Hunter /* 1478e2bf08d6SAdrian Hunter * Set an arbitrary 100ms data timeout for commands with 1479e2bf08d6SAdrian Hunter * busy signal. 1480e2bf08d6SAdrian Hunter */ 1481e2bf08d6SAdrian Hunter if (req->cmd->flags & MMC_RSP_BUSY) 1482e2bf08d6SAdrian Hunter set_data_timeout(host, 100000000U, 0); 1483a45c6cb8SMadhusudhan Chikkature return 0; 1484a45c6cb8SMadhusudhan Chikkature } 1485a45c6cb8SMadhusudhan Chikkature 1486a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 14879d025334SBalaji T K ret = omap_hsmmc_setup_dma_transfer(host, req); 1488a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 1489b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); 1490a45c6cb8SMadhusudhan Chikkature return ret; 1491a45c6cb8SMadhusudhan Chikkature } 1492a45c6cb8SMadhusudhan Chikkature } 1493a45c6cb8SMadhusudhan Chikkature return 0; 1494a45c6cb8SMadhusudhan Chikkature } 1495a45c6cb8SMadhusudhan Chikkature 14969782aff8SPer Forlin static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 14979782aff8SPer Forlin int err) 14989782aff8SPer Forlin { 14999782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15009782aff8SPer Forlin struct mmc_data *data = mrq->data; 15019782aff8SPer Forlin 150226b88520SRussell King if (host->use_dma && data->host_cookie) { 1503c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1504c5c98927SRussell King 150526b88520SRussell King dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 15069782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 15079782aff8SPer Forlin data->host_cookie = 0; 15089782aff8SPer Forlin } 15099782aff8SPer Forlin } 15109782aff8SPer Forlin 15119782aff8SPer Forlin static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 15129782aff8SPer Forlin bool is_first_req) 15139782aff8SPer Forlin { 15149782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15159782aff8SPer Forlin 15169782aff8SPer Forlin if (mrq->data->host_cookie) { 15179782aff8SPer Forlin mrq->data->host_cookie = 0; 15189782aff8SPer Forlin return ; 15199782aff8SPer Forlin } 15209782aff8SPer Forlin 1521c5c98927SRussell King if (host->use_dma) { 1522c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1523c5c98927SRussell King 15249782aff8SPer Forlin if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 152526b88520SRussell King &host->next_data, c)) 15269782aff8SPer Forlin mrq->data->host_cookie = 0; 15279782aff8SPer Forlin } 1528c5c98927SRussell King } 15299782aff8SPer Forlin 1530a45c6cb8SMadhusudhan Chikkature /* 1531a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 1532a45c6cb8SMadhusudhan Chikkature */ 153370a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1534a45c6cb8SMadhusudhan Chikkature { 153570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1536a3f406f8SJarkko Lavinen int err; 1537a45c6cb8SMadhusudhan Chikkature 1538b417577dSAdrian Hunter BUG_ON(host->req_in_progress); 1539b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1540b62f6228SAdrian Hunter if (host->protect_card) { 1541b62f6228SAdrian Hunter if (host->reqs_blocked < 3) { 1542b62f6228SAdrian Hunter /* 1543b62f6228SAdrian Hunter * Ensure the controller is left in a consistent 1544b62f6228SAdrian Hunter * state by resetting the command and data state 1545b62f6228SAdrian Hunter * machines. 1546b62f6228SAdrian Hunter */ 1547b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRD); 1548b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRC); 1549b62f6228SAdrian Hunter host->reqs_blocked += 1; 1550b62f6228SAdrian Hunter } 1551b62f6228SAdrian Hunter req->cmd->error = -EBADF; 1552b62f6228SAdrian Hunter if (req->data) 1553b62f6228SAdrian Hunter req->data->error = -EBADF; 1554b417577dSAdrian Hunter req->cmd->retries = 0; 1555b62f6228SAdrian Hunter mmc_request_done(mmc, req); 1556b62f6228SAdrian Hunter return; 1557b62f6228SAdrian Hunter } else if (host->reqs_blocked) 1558b62f6228SAdrian Hunter host->reqs_blocked = 0; 1559a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 1560a45c6cb8SMadhusudhan Chikkature host->mrq = req; 15616e3076c2SBalaji T K host->clk_rate = clk_get_rate(host->fclk); 156270a3341aSDenis Karpov err = omap_hsmmc_prepare_data(host, req); 1563a3f406f8SJarkko Lavinen if (err) { 1564a3f406f8SJarkko Lavinen req->cmd->error = err; 1565a3f406f8SJarkko Lavinen if (req->data) 1566a3f406f8SJarkko Lavinen req->data->error = err; 1567a3f406f8SJarkko Lavinen host->mrq = NULL; 1568a3f406f8SJarkko Lavinen mmc_request_done(mmc, req); 1569a3f406f8SJarkko Lavinen return; 1570a3f406f8SJarkko Lavinen } 1571a2e77152SBalaji T K if (req->sbc && !(host->flags & AUTO_CMD23)) { 1572bf129e1cSBalaji T K omap_hsmmc_start_command(host, req->sbc, NULL); 1573bf129e1cSBalaji T K return; 1574bf129e1cSBalaji T K } 1575a3f406f8SJarkko Lavinen 15769d025334SBalaji T K omap_hsmmc_start_dma_transfer(host); 157770a3341aSDenis Karpov omap_hsmmc_start_command(host, req->cmd, req->data); 1578a45c6cb8SMadhusudhan Chikkature } 1579a45c6cb8SMadhusudhan Chikkature 1580a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 158170a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1582a45c6cb8SMadhusudhan Chikkature { 158370a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1584a3621465SAdrian Hunter int do_send_init_stream = 0; 1585a45c6cb8SMadhusudhan Chikkature 1586fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 15875e2ea617SAdrian Hunter 1588a3621465SAdrian Hunter if (ios->power_mode != host->power_mode) { 1589a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 1590a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 159180412ca8SAndreas Fenkart mmc_pdata(host)->set_power(host->dev, 0, 0); 1592a45c6cb8SMadhusudhan Chikkature break; 1593a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 159480412ca8SAndreas Fenkart mmc_pdata(host)->set_power(host->dev, 1, ios->vdd); 1595a45c6cb8SMadhusudhan Chikkature break; 1596a3621465SAdrian Hunter case MMC_POWER_ON: 1597a3621465SAdrian Hunter do_send_init_stream = 1; 1598a3621465SAdrian Hunter break; 1599a3621465SAdrian Hunter } 1600a3621465SAdrian Hunter host->power_mode = ios->power_mode; 1601a45c6cb8SMadhusudhan Chikkature } 1602a45c6cb8SMadhusudhan Chikkature 1603dd498effSDenis Karpov /* FIXME: set registers based only on changes to ios */ 1604dd498effSDenis Karpov 16053796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 1606a45c6cb8SMadhusudhan Chikkature 16074621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1608eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 1609eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 1610eb250826SDavid Brownell */ 1611a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 16122cf171cbSBalaji T K (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1613a45c6cb8SMadhusudhan Chikkature /* 1614a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 1615a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 1616a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 1617a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 1618a45c6cb8SMadhusudhan Chikkature */ 161970a3341aSDenis Karpov if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1620a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1621a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 1622a45c6cb8SMadhusudhan Chikkature } 1623a45c6cb8SMadhusudhan Chikkature } 1624a45c6cb8SMadhusudhan Chikkature 16255934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 1626a45c6cb8SMadhusudhan Chikkature 1627a3621465SAdrian Hunter if (do_send_init_stream) 1628a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 1629a45c6cb8SMadhusudhan Chikkature 16303796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 16315e2ea617SAdrian Hunter 1632fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1633a45c6cb8SMadhusudhan Chikkature } 1634a45c6cb8SMadhusudhan Chikkature 1635a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1636a45c6cb8SMadhusudhan Chikkature { 163770a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1638a45c6cb8SMadhusudhan Chikkature 1639b5cd43f0SAndreas Fenkart if (!host->card_detect) 1640a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 164180412ca8SAndreas Fenkart return host->card_detect(host->dev); 1642a45c6cb8SMadhusudhan Chikkature } 1643a45c6cb8SMadhusudhan Chikkature 1644a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_ro(struct mmc_host *mmc) 1645a45c6cb8SMadhusudhan Chikkature { 164670a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1647a45c6cb8SMadhusudhan Chikkature 1648b5cd43f0SAndreas Fenkart if (!host->get_ro) 1649a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 165080412ca8SAndreas Fenkart return host->get_ro(host->dev); 1651a45c6cb8SMadhusudhan Chikkature } 1652a45c6cb8SMadhusudhan Chikkature 16534816858cSGrazvydas Ignotas static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 16544816858cSGrazvydas Ignotas { 16554816858cSGrazvydas Ignotas struct omap_hsmmc_host *host = mmc_priv(mmc); 16564816858cSGrazvydas Ignotas 1657326119c9SAndreas Fenkart if (mmc_pdata(host)->init_card) 1658326119c9SAndreas Fenkart mmc_pdata(host)->init_card(card); 16594816858cSGrazvydas Ignotas } 16604816858cSGrazvydas Ignotas 16612cd3a2a5SAndreas Fenkart static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 16622cd3a2a5SAndreas Fenkart { 16632cd3a2a5SAndreas Fenkart struct omap_hsmmc_host *host = mmc_priv(mmc); 16645a52b08bSBalaji T K u32 irq_mask, con; 16652cd3a2a5SAndreas Fenkart unsigned long flags; 16662cd3a2a5SAndreas Fenkart 16672cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 16682cd3a2a5SAndreas Fenkart 16695a52b08bSBalaji T K con = OMAP_HSMMC_READ(host->base, CON); 16702cd3a2a5SAndreas Fenkart irq_mask = OMAP_HSMMC_READ(host->base, ISE); 16712cd3a2a5SAndreas Fenkart if (enable) { 16722cd3a2a5SAndreas Fenkart host->flags |= HSMMC_SDIO_IRQ_ENABLED; 16732cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 16745a52b08bSBalaji T K con |= CTPL | CLKEXTFREE; 16752cd3a2a5SAndreas Fenkart } else { 16762cd3a2a5SAndreas Fenkart host->flags &= ~HSMMC_SDIO_IRQ_ENABLED; 16772cd3a2a5SAndreas Fenkart irq_mask &= ~CIRQ_EN; 16785a52b08bSBalaji T K con &= ~(CTPL | CLKEXTFREE); 16792cd3a2a5SAndreas Fenkart } 16805a52b08bSBalaji T K OMAP_HSMMC_WRITE(host->base, CON, con); 16812cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 16822cd3a2a5SAndreas Fenkart 16832cd3a2a5SAndreas Fenkart /* 16842cd3a2a5SAndreas Fenkart * if enable, piggy back detection on current request 16852cd3a2a5SAndreas Fenkart * but always disable immediately 16862cd3a2a5SAndreas Fenkart */ 16872cd3a2a5SAndreas Fenkart if (!host->req_in_progress || !enable) 16882cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 16892cd3a2a5SAndreas Fenkart 16902cd3a2a5SAndreas Fenkart /* flush posted write */ 16912cd3a2a5SAndreas Fenkart OMAP_HSMMC_READ(host->base, IE); 16922cd3a2a5SAndreas Fenkart 16932cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 16942cd3a2a5SAndreas Fenkart } 16952cd3a2a5SAndreas Fenkart 16962cd3a2a5SAndreas Fenkart static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host) 16972cd3a2a5SAndreas Fenkart { 16982cd3a2a5SAndreas Fenkart struct mmc_host *mmc = host->mmc; 16992cd3a2a5SAndreas Fenkart int ret; 17002cd3a2a5SAndreas Fenkart 17012cd3a2a5SAndreas Fenkart /* 17022cd3a2a5SAndreas Fenkart * For omaps with wake-up path, wakeirq will be irq from pinctrl and 17032cd3a2a5SAndreas Fenkart * for other omaps, wakeirq will be from GPIO (dat line remuxed to 17042cd3a2a5SAndreas Fenkart * gpio). wakeirq is needed to detect sdio irq in runtime suspend state 17052cd3a2a5SAndreas Fenkart * with functional clock disabled. 17062cd3a2a5SAndreas Fenkart */ 17072cd3a2a5SAndreas Fenkart if (!host->dev->of_node || !host->wake_irq) 17082cd3a2a5SAndreas Fenkart return -ENODEV; 17092cd3a2a5SAndreas Fenkart 17102cd3a2a5SAndreas Fenkart /* Prevent auto-enabling of IRQ */ 17112cd3a2a5SAndreas Fenkart irq_set_status_flags(host->wake_irq, IRQ_NOAUTOEN); 17122cd3a2a5SAndreas Fenkart ret = devm_request_irq(host->dev, host->wake_irq, omap_hsmmc_wake_irq, 17132cd3a2a5SAndreas Fenkart IRQF_TRIGGER_LOW | IRQF_ONESHOT, 17142cd3a2a5SAndreas Fenkart mmc_hostname(mmc), host); 17152cd3a2a5SAndreas Fenkart if (ret) { 17162cd3a2a5SAndreas Fenkart dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n"); 17172cd3a2a5SAndreas Fenkart goto err; 17182cd3a2a5SAndreas Fenkart } 17192cd3a2a5SAndreas Fenkart 17202cd3a2a5SAndreas Fenkart /* 17212cd3a2a5SAndreas Fenkart * Some omaps don't have wake-up path from deeper idle states 17222cd3a2a5SAndreas Fenkart * and need to remux SDIO DAT1 to GPIO for wake-up from idle. 17232cd3a2a5SAndreas Fenkart */ 17242cd3a2a5SAndreas Fenkart if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) { 1725455e5cd6SAndreas Fenkart struct pinctrl *p = devm_pinctrl_get(host->dev); 1726455e5cd6SAndreas Fenkart if (!p) { 17272cd3a2a5SAndreas Fenkart ret = -ENODEV; 1728455e5cd6SAndreas Fenkart goto err_free_irq; 1729455e5cd6SAndreas Fenkart } 1730455e5cd6SAndreas Fenkart if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) { 1731455e5cd6SAndreas Fenkart dev_info(host->dev, "missing default pinctrl state\n"); 1732455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 1733455e5cd6SAndreas Fenkart ret = -EINVAL; 1734455e5cd6SAndreas Fenkart goto err_free_irq; 1735455e5cd6SAndreas Fenkart } 1736455e5cd6SAndreas Fenkart 1737455e5cd6SAndreas Fenkart if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) { 1738455e5cd6SAndreas Fenkart dev_info(host->dev, "missing idle pinctrl state\n"); 1739455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 1740455e5cd6SAndreas Fenkart ret = -EINVAL; 1741455e5cd6SAndreas Fenkart goto err_free_irq; 1742455e5cd6SAndreas Fenkart } 1743455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 17442cd3a2a5SAndreas Fenkart } 17452cd3a2a5SAndreas Fenkart 17465a52b08bSBalaji T K OMAP_HSMMC_WRITE(host->base, HCTL, 17475a52b08bSBalaji T K OMAP_HSMMC_READ(host->base, HCTL) | IWE); 17482cd3a2a5SAndreas Fenkart return 0; 17492cd3a2a5SAndreas Fenkart 1750455e5cd6SAndreas Fenkart err_free_irq: 1751455e5cd6SAndreas Fenkart devm_free_irq(host->dev, host->wake_irq, host); 17522cd3a2a5SAndreas Fenkart err: 17532cd3a2a5SAndreas Fenkart dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n"); 17542cd3a2a5SAndreas Fenkart host->wake_irq = 0; 17552cd3a2a5SAndreas Fenkart return ret; 17562cd3a2a5SAndreas Fenkart } 17572cd3a2a5SAndreas Fenkart 175870a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 17591b331e69SKim Kyuwon { 17601b331e69SKim Kyuwon u32 hctl, capa, value; 17611b331e69SKim Kyuwon 17621b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 17634621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 17641b331e69SKim Kyuwon hctl = SDVS30; 17651b331e69SKim Kyuwon capa = VS30 | VS18; 17661b331e69SKim Kyuwon } else { 17671b331e69SKim Kyuwon hctl = SDVS18; 17681b331e69SKim Kyuwon capa = VS18; 17691b331e69SKim Kyuwon } 17701b331e69SKim Kyuwon 17711b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 17721b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 17731b331e69SKim Kyuwon 17741b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 17751b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 17761b331e69SKim Kyuwon 17771b331e69SKim Kyuwon /* Set SD bus power bit */ 1778e13bb300SAdrian Hunter set_sd_bus_power(host); 17791b331e69SKim Kyuwon } 17801b331e69SKim Kyuwon 178170a3341aSDenis Karpov static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) 1782dd498effSDenis Karpov { 178370a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1784dd498effSDenis Karpov 1785fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1786fa4aa2d4SBalaji T K 1787dd498effSDenis Karpov return 0; 1788dd498effSDenis Karpov } 1789dd498effSDenis Karpov 1790907d2e7cSAdrian Hunter static int omap_hsmmc_disable_fclk(struct mmc_host *mmc) 1791dd498effSDenis Karpov { 179270a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1793dd498effSDenis Karpov 1794fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1795fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1796fa4aa2d4SBalaji T K 1797dd498effSDenis Karpov return 0; 1798dd498effSDenis Karpov } 1799dd498effSDenis Karpov 1800afd8c29dSKuninori Morimoto static int omap_hsmmc_multi_io_quirk(struct mmc_card *card, 1801afd8c29dSKuninori Morimoto unsigned int direction, int blk_size) 1802afd8c29dSKuninori Morimoto { 1803afd8c29dSKuninori Morimoto /* This controller can't do multiblock reads due to hw bugs */ 1804afd8c29dSKuninori Morimoto if (direction == MMC_DATA_READ) 1805afd8c29dSKuninori Morimoto return 1; 1806afd8c29dSKuninori Morimoto 1807afd8c29dSKuninori Morimoto return blk_size; 1808afd8c29dSKuninori Morimoto } 1809afd8c29dSKuninori Morimoto 1810afd8c29dSKuninori Morimoto static struct mmc_host_ops omap_hsmmc_ops = { 181170a3341aSDenis Karpov .enable = omap_hsmmc_enable_fclk, 181270a3341aSDenis Karpov .disable = omap_hsmmc_disable_fclk, 18139782aff8SPer Forlin .post_req = omap_hsmmc_post_req, 18149782aff8SPer Forlin .pre_req = omap_hsmmc_pre_req, 181570a3341aSDenis Karpov .request = omap_hsmmc_request, 181670a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1817dd498effSDenis Karpov .get_cd = omap_hsmmc_get_cd, 1818dd498effSDenis Karpov .get_ro = omap_hsmmc_get_ro, 18194816858cSGrazvydas Ignotas .init_card = omap_hsmmc_init_card, 18202cd3a2a5SAndreas Fenkart .enable_sdio_irq = omap_hsmmc_enable_sdio_irq, 1821dd498effSDenis Karpov }; 1822dd498effSDenis Karpov 1823d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS 1824d900f712SDenis Karpov 182570a3341aSDenis Karpov static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1826d900f712SDenis Karpov { 1827d900f712SDenis Karpov struct mmc_host *mmc = s->private; 182870a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 182911dd62a7SDenis Karpov 1830bb0635f0SAndreas Fenkart seq_printf(s, "mmc%d:\n", mmc->index); 1831bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq mode\t%s\n", 1832bb0635f0SAndreas Fenkart (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling"); 1833bb0635f0SAndreas Fenkart 1834bb0635f0SAndreas Fenkart if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1835bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq \t%s\n", 1836bb0635f0SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled" 1837bb0635f0SAndreas Fenkart : "disabled"); 1838bb0635f0SAndreas Fenkart } 1839bb0635f0SAndreas Fenkart seq_printf(s, "ctx_loss:\t%d\n", host->context_loss); 18405e2ea617SAdrian Hunter 1841fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1842bb0635f0SAndreas Fenkart seq_puts(s, "\nregs:\n"); 1843d900f712SDenis Karpov seq_printf(s, "CON:\t\t0x%08x\n", 1844d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CON)); 1845bb0635f0SAndreas Fenkart seq_printf(s, "PSTATE:\t\t0x%08x\n", 1846bb0635f0SAndreas Fenkart OMAP_HSMMC_READ(host->base, PSTATE)); 1847d900f712SDenis Karpov seq_printf(s, "HCTL:\t\t0x%08x\n", 1848d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL)); 1849d900f712SDenis Karpov seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1850d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL)); 1851d900f712SDenis Karpov seq_printf(s, "IE:\t\t0x%08x\n", 1852d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, IE)); 1853d900f712SDenis Karpov seq_printf(s, "ISE:\t\t0x%08x\n", 1854d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, ISE)); 1855d900f712SDenis Karpov seq_printf(s, "CAPA:\t\t0x%08x\n", 1856d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA)); 18575e2ea617SAdrian Hunter 1858fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1859fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1860dd498effSDenis Karpov 1861d900f712SDenis Karpov return 0; 1862d900f712SDenis Karpov } 1863d900f712SDenis Karpov 186470a3341aSDenis Karpov static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1865d900f712SDenis Karpov { 186670a3341aSDenis Karpov return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1867d900f712SDenis Karpov } 1868d900f712SDenis Karpov 1869d900f712SDenis Karpov static const struct file_operations mmc_regs_fops = { 187070a3341aSDenis Karpov .open = omap_hsmmc_regs_open, 1871d900f712SDenis Karpov .read = seq_read, 1872d900f712SDenis Karpov .llseek = seq_lseek, 1873d900f712SDenis Karpov .release = single_release, 1874d900f712SDenis Karpov }; 1875d900f712SDenis Karpov 187670a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1877d900f712SDenis Karpov { 1878d900f712SDenis Karpov if (mmc->debugfs_root) 1879d900f712SDenis Karpov debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1880d900f712SDenis Karpov mmc, &mmc_regs_fops); 1881d900f712SDenis Karpov } 1882d900f712SDenis Karpov 1883d900f712SDenis Karpov #else 1884d900f712SDenis Karpov 188570a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1886d900f712SDenis Karpov { 1887d900f712SDenis Karpov } 1888d900f712SDenis Karpov 1889d900f712SDenis Karpov #endif 1890d900f712SDenis Karpov 189146856a68SRajendra Nayak #ifdef CONFIG_OF 189259445b10SNishanth Menon static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = { 189359445b10SNishanth Menon /* See 35xx errata 2.1.1.128 in SPRZ278F */ 189459445b10SNishanth Menon .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 189559445b10SNishanth Menon }; 189659445b10SNishanth Menon 189759445b10SNishanth Menon static const struct omap_mmc_of_data omap4_mmc_of_data = { 189859445b10SNishanth Menon .reg_offset = 0x100, 189959445b10SNishanth Menon }; 19002cd3a2a5SAndreas Fenkart static const struct omap_mmc_of_data am33xx_mmc_of_data = { 19012cd3a2a5SAndreas Fenkart .reg_offset = 0x100, 19022cd3a2a5SAndreas Fenkart .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING, 19032cd3a2a5SAndreas Fenkart }; 190446856a68SRajendra Nayak 190546856a68SRajendra Nayak static const struct of_device_id omap_mmc_of_match[] = { 190646856a68SRajendra Nayak { 190746856a68SRajendra Nayak .compatible = "ti,omap2-hsmmc", 190846856a68SRajendra Nayak }, 190946856a68SRajendra Nayak { 191059445b10SNishanth Menon .compatible = "ti,omap3-pre-es3-hsmmc", 191159445b10SNishanth Menon .data = &omap3_pre_es3_mmc_of_data, 191259445b10SNishanth Menon }, 191359445b10SNishanth Menon { 191446856a68SRajendra Nayak .compatible = "ti,omap3-hsmmc", 191546856a68SRajendra Nayak }, 191646856a68SRajendra Nayak { 191746856a68SRajendra Nayak .compatible = "ti,omap4-hsmmc", 191859445b10SNishanth Menon .data = &omap4_mmc_of_data, 191946856a68SRajendra Nayak }, 19202cd3a2a5SAndreas Fenkart { 19212cd3a2a5SAndreas Fenkart .compatible = "ti,am33xx-hsmmc", 19222cd3a2a5SAndreas Fenkart .data = &am33xx_mmc_of_data, 19232cd3a2a5SAndreas Fenkart }, 192446856a68SRajendra Nayak {}, 1925b6d085f6SChris Ball }; 192646856a68SRajendra Nayak MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 192746856a68SRajendra Nayak 192855143438SAndreas Fenkart static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 192946856a68SRajendra Nayak { 193055143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata; 193146856a68SRajendra Nayak struct device_node *np = dev->of_node; 1932d8714e87SDaniel Mack u32 bus_width, max_freq; 1933dc642c28SJan Luebbe int cd_gpio, wp_gpio; 1934dc642c28SJan Luebbe 1935dc642c28SJan Luebbe cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); 1936dc642c28SJan Luebbe wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 1937dc642c28SJan Luebbe if (cd_gpio == -EPROBE_DEFER || wp_gpio == -EPROBE_DEFER) 1938dc642c28SJan Luebbe return ERR_PTR(-EPROBE_DEFER); 193946856a68SRajendra Nayak 194046856a68SRajendra Nayak pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 194146856a68SRajendra Nayak if (!pdata) 194219df45bcSBalaji T K return ERR_PTR(-ENOMEM); /* out of memory */ 194346856a68SRajendra Nayak 194446856a68SRajendra Nayak if (of_find_property(np, "ti,dual-volt", NULL)) 194546856a68SRajendra Nayak pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 194646856a68SRajendra Nayak 1947326119c9SAndreas Fenkart pdata->switch_pin = cd_gpio; 1948326119c9SAndreas Fenkart pdata->gpio_wp = wp_gpio; 194946856a68SRajendra Nayak 195046856a68SRajendra Nayak if (of_find_property(np, "ti,non-removable", NULL)) { 1951326119c9SAndreas Fenkart pdata->nonremovable = true; 1952326119c9SAndreas Fenkart pdata->no_regulator_off_init = true; 195346856a68SRajendra Nayak } 19547f217794SArnd Bergmann of_property_read_u32(np, "bus-width", &bus_width); 195546856a68SRajendra Nayak if (bus_width == 4) 1956326119c9SAndreas Fenkart pdata->caps |= MMC_CAP_4_BIT_DATA; 195746856a68SRajendra Nayak else if (bus_width == 8) 1958326119c9SAndreas Fenkart pdata->caps |= MMC_CAP_8_BIT_DATA; 195946856a68SRajendra Nayak 196046856a68SRajendra Nayak if (of_find_property(np, "ti,needs-special-reset", NULL)) 1961326119c9SAndreas Fenkart pdata->features |= HSMMC_HAS_UPDATED_RESET; 196246856a68SRajendra Nayak 1963d8714e87SDaniel Mack if (!of_property_read_u32(np, "max-frequency", &max_freq)) 1964d8714e87SDaniel Mack pdata->max_freq = max_freq; 1965d8714e87SDaniel Mack 1966cd587096SHebbar, Gururaja if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) 1967326119c9SAndreas Fenkart pdata->features |= HSMMC_HAS_HSPE_SUPPORT; 1968cd587096SHebbar, Gururaja 1969c9ae64dbSDaniel Mack if (of_find_property(np, "keep-power-in-suspend", NULL)) 1970326119c9SAndreas Fenkart pdata->pm_caps |= MMC_PM_KEEP_POWER; 1971c9ae64dbSDaniel Mack 1972c9ae64dbSDaniel Mack if (of_find_property(np, "enable-sdio-wakeup", NULL)) 1973326119c9SAndreas Fenkart pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 1974c9ae64dbSDaniel Mack 197546856a68SRajendra Nayak return pdata; 197646856a68SRajendra Nayak } 197746856a68SRajendra Nayak #else 197855143438SAndreas Fenkart static inline struct omap_hsmmc_platform_data 197946856a68SRajendra Nayak *of_get_hsmmc_pdata(struct device *dev) 198046856a68SRajendra Nayak { 198119df45bcSBalaji T K return ERR_PTR(-EINVAL); 198246856a68SRajendra Nayak } 198346856a68SRajendra Nayak #endif 198446856a68SRajendra Nayak 1985c3be1efdSBill Pemberton static int omap_hsmmc_probe(struct platform_device *pdev) 1986a45c6cb8SMadhusudhan Chikkature { 198755143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data; 1988a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 198970a3341aSDenis Karpov struct omap_hsmmc_host *host = NULL; 1990a45c6cb8SMadhusudhan Chikkature struct resource *res; 1991db0fefc5SAdrian Hunter int ret, irq; 199246856a68SRajendra Nayak const struct of_device_id *match; 199326b88520SRussell King dma_cap_mask_t mask; 199426b88520SRussell King unsigned tx_req, rx_req; 199559445b10SNishanth Menon const struct omap_mmc_of_data *data; 199677fae219SBalaji T K void __iomem *base; 199746856a68SRajendra Nayak 199846856a68SRajendra Nayak match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 199946856a68SRajendra Nayak if (match) { 200046856a68SRajendra Nayak pdata = of_get_hsmmc_pdata(&pdev->dev); 2001dc642c28SJan Luebbe 2002dc642c28SJan Luebbe if (IS_ERR(pdata)) 2003dc642c28SJan Luebbe return PTR_ERR(pdata); 2004dc642c28SJan Luebbe 200546856a68SRajendra Nayak if (match->data) { 200659445b10SNishanth Menon data = match->data; 200759445b10SNishanth Menon pdata->reg_offset = data->reg_offset; 200859445b10SNishanth Menon pdata->controller_flags |= data->controller_flags; 200946856a68SRajendra Nayak } 201046856a68SRajendra Nayak } 2011a45c6cb8SMadhusudhan Chikkature 2012a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 2013a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 2014a45c6cb8SMadhusudhan Chikkature return -ENXIO; 2015a45c6cb8SMadhusudhan Chikkature } 2016a45c6cb8SMadhusudhan Chikkature 2017a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2018a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 2019a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 2020a45c6cb8SMadhusudhan Chikkature return -ENXIO; 2021a45c6cb8SMadhusudhan Chikkature 202277fae219SBalaji T K base = devm_ioremap_resource(&pdev->dev, res); 202377fae219SBalaji T K if (IS_ERR(base)) 202477fae219SBalaji T K return PTR_ERR(base); 2025a45c6cb8SMadhusudhan Chikkature 202670a3341aSDenis Karpov mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 2027a45c6cb8SMadhusudhan Chikkature if (!mmc) { 2028a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 20291e363e3bSAndreas Fenkart goto err; 2030a45c6cb8SMadhusudhan Chikkature } 2031a45c6cb8SMadhusudhan Chikkature 2032a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 2033a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 2034a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 2035a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 2036a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 2037a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 2038a45c6cb8SMadhusudhan Chikkature host->irq = irq; 2039fc307df8SBalaji T K host->mapbase = res->start + pdata->reg_offset; 204077fae219SBalaji T K host->base = base + pdata->reg_offset; 20416da20c89SAdrian Hunter host->power_mode = MMC_POWER_OFF; 20429782aff8SPer Forlin host->next_data.cookie = 1; 2043e99448ffSBalaji T K host->pbias_enabled = 0; 2044a45c6cb8SMadhusudhan Chikkature 204541afa314SNeilBrown ret = omap_hsmmc_gpio_init(mmc, host, pdata); 20461e363e3bSAndreas Fenkart if (ret) 20471e363e3bSAndreas Fenkart goto err_gpio; 20481e363e3bSAndreas Fenkart 2049a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 2050a45c6cb8SMadhusudhan Chikkature 20512cd3a2a5SAndreas Fenkart if (pdev->dev.of_node) 20522cd3a2a5SAndreas Fenkart host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1); 20532cd3a2a5SAndreas Fenkart 205470a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ops; 2055dd498effSDenis Karpov 20566b206efeSAndy Shevchenko mmc->f_min = OMAP_MMC_MIN_CLOCK; 2057d418ed87SDaniel Mack 2058d418ed87SDaniel Mack if (pdata->max_freq > 0) 2059d418ed87SDaniel Mack mmc->f_max = pdata->max_freq; 2060d418ed87SDaniel Mack else 20616b206efeSAndy Shevchenko mmc->f_max = OMAP_MMC_MAX_CLOCK; 2062a45c6cb8SMadhusudhan Chikkature 20634dffd7a2SAdrian Hunter spin_lock_init(&host->irq_lock); 2064a45c6cb8SMadhusudhan Chikkature 20659618195eSBalaji T K host->fclk = devm_clk_get(&pdev->dev, "fck"); 2066a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 2067a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 2068a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 2069a45c6cb8SMadhusudhan Chikkature goto err1; 2070a45c6cb8SMadhusudhan Chikkature } 2071a45c6cb8SMadhusudhan Chikkature 20729b68256cSPaul Walmsley if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 20739b68256cSPaul Walmsley dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 2074afd8c29dSKuninori Morimoto omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk; 20759b68256cSPaul Walmsley } 2076dd498effSDenis Karpov 2077fa4aa2d4SBalaji T K pm_runtime_enable(host->dev); 2078fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2079fa4aa2d4SBalaji T K pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 2080fa4aa2d4SBalaji T K pm_runtime_use_autosuspend(host->dev); 2081a45c6cb8SMadhusudhan Chikkature 208292a3aebfSBalaji T K omap_hsmmc_context_save(host); 208392a3aebfSBalaji T K 20849618195eSBalaji T K host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck"); 2085a45c6cb8SMadhusudhan Chikkature /* 2086a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 2087a45c6cb8SMadhusudhan Chikkature */ 2088cd03d9a8SRajendra Nayak if (IS_ERR(host->dbclk)) { 2089cd03d9a8SRajendra Nayak host->dbclk = NULL; 209094c18149SRajendra Nayak } else if (clk_prepare_enable(host->dbclk) != 0) { 2091cd03d9a8SRajendra Nayak dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 2092cd03d9a8SRajendra Nayak host->dbclk = NULL; 20932bec0893SAdrian Hunter } 2094a45c6cb8SMadhusudhan Chikkature 20950ccd76d4SJuha Yrjola /* Since we do only SG emulation, we can have as many segs 20960ccd76d4SJuha Yrjola * as we want. */ 2097a36274e0SMartin K. Petersen mmc->max_segs = 1024; 20980ccd76d4SJuha Yrjola 2099a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 2100a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 2101a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2102a45c6cb8SMadhusudhan Chikkature mmc->max_seg_size = mmc->max_req_size; 2103a45c6cb8SMadhusudhan Chikkature 210413189e78SJarkko Lavinen mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 210593caf8e6SAdrian Hunter MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 2106a45c6cb8SMadhusudhan Chikkature 2107326119c9SAndreas Fenkart mmc->caps |= mmc_pdata(host)->caps; 21083a63833eSSukumar Ghorai if (mmc->caps & MMC_CAP_8_BIT_DATA) 2109a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 2110a45c6cb8SMadhusudhan Chikkature 2111326119c9SAndreas Fenkart if (mmc_pdata(host)->nonremovable) 211223d99bb9SAdrian Hunter mmc->caps |= MMC_CAP_NONREMOVABLE; 211323d99bb9SAdrian Hunter 2114326119c9SAndreas Fenkart mmc->pm_caps = mmc_pdata(host)->pm_caps; 21156fdc75deSEliad Peller 211670a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 2117a45c6cb8SMadhusudhan Chikkature 21184a29b559SSantosh Shilimkar if (!pdev->dev.of_node) { 2119b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 2120b7bf773bSBalaji T K if (!res) { 2121b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n"); 21229c17d08cSKevin Hilman ret = -ENXIO; 2123f3e2f1ddSGrazvydas Ignotas goto err_irq; 2124a45c6cb8SMadhusudhan Chikkature } 212526b88520SRussell King tx_req = res->start; 2126b7bf773bSBalaji T K 2127b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 2128b7bf773bSBalaji T K if (!res) { 2129b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n"); 21309c17d08cSKevin Hilman ret = -ENXIO; 2131b7bf773bSBalaji T K goto err_irq; 2132b7bf773bSBalaji T K } 213326b88520SRussell King rx_req = res->start; 21344a29b559SSantosh Shilimkar } 2135c5c98927SRussell King 2136c5c98927SRussell King dma_cap_zero(mask); 2137c5c98927SRussell King dma_cap_set(DMA_SLAVE, mask); 213826b88520SRussell King 2139d272fbf0SMatt Porter host->rx_chan = 2140d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 2141d272fbf0SMatt Porter &rx_req, &pdev->dev, "rx"); 2142d272fbf0SMatt Porter 2143c5c98927SRussell King if (!host->rx_chan) { 214426b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req); 214504e8c7bcSKevin Hilman ret = -ENXIO; 214626b88520SRussell King goto err_irq; 2147c5c98927SRussell King } 214826b88520SRussell King 2149d272fbf0SMatt Porter host->tx_chan = 2150d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 2151d272fbf0SMatt Porter &tx_req, &pdev->dev, "tx"); 2152d272fbf0SMatt Porter 2153c5c98927SRussell King if (!host->tx_chan) { 215426b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req); 215504e8c7bcSKevin Hilman ret = -ENXIO; 215626b88520SRussell King goto err_irq; 2157c5c98927SRussell King } 2158a45c6cb8SMadhusudhan Chikkature 2159a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 2160e1538ed7SBalaji T K ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0, 2161a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 2162a45c6cb8SMadhusudhan Chikkature if (ret) { 2163b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 2164a45c6cb8SMadhusudhan Chikkature goto err_irq; 2165a45c6cb8SMadhusudhan Chikkature } 2166a45c6cb8SMadhusudhan Chikkature 2167326119c9SAndreas Fenkart if (omap_hsmmc_have_reg() && !mmc_pdata(host)->set_power) { 2168db0fefc5SAdrian Hunter ret = omap_hsmmc_reg_get(host); 2169db0fefc5SAdrian Hunter if (ret) 2170bb09d151SAndreas Fenkart goto err_irq; 2171db0fefc5SAdrian Hunter host->use_reg = 1; 2172db0fefc5SAdrian Hunter } 2173db0fefc5SAdrian Hunter 2174326119c9SAndreas Fenkart mmc->ocr_avail = mmc_pdata(host)->ocr_mask; 2175a45c6cb8SMadhusudhan Chikkature 2176b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 2177a45c6cb8SMadhusudhan Chikkature 21782cd3a2a5SAndreas Fenkart /* 21792cd3a2a5SAndreas Fenkart * For now, only support SDIO interrupt if we have a separate 21802cd3a2a5SAndreas Fenkart * wake-up interrupt configured from device tree. This is because 21812cd3a2a5SAndreas Fenkart * the wake-up interrupt is needed for idle state and some 21822cd3a2a5SAndreas Fenkart * platforms need special quirks. And we don't want to add new 21832cd3a2a5SAndreas Fenkart * legacy mux platform init code callbacks any longer as we 21842cd3a2a5SAndreas Fenkart * are moving to DT based booting anyways. 21852cd3a2a5SAndreas Fenkart */ 21862cd3a2a5SAndreas Fenkart ret = omap_hsmmc_configure_wake_irq(host); 21872cd3a2a5SAndreas Fenkart if (!ret) 21882cd3a2a5SAndreas Fenkart mmc->caps |= MMC_CAP_SDIO_IRQ; 21892cd3a2a5SAndreas Fenkart 2190b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2191b62f6228SAdrian Hunter 2192a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 2193a45c6cb8SMadhusudhan Chikkature 2194326119c9SAndreas Fenkart if (mmc_pdata(host)->name != NULL) { 2195a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2196a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2197a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 2198a45c6cb8SMadhusudhan Chikkature } 2199b5cd43f0SAndreas Fenkart if (host->card_detect_irq && host->get_cover_state) { 2200a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, 2201a45c6cb8SMadhusudhan Chikkature &dev_attr_cover_switch); 2202a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2203db0fefc5SAdrian Hunter goto err_slot_name; 2204a45c6cb8SMadhusudhan Chikkature } 2205a45c6cb8SMadhusudhan Chikkature 220670a3341aSDenis Karpov omap_hsmmc_debugfs(mmc); 2207fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2208fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2209d900f712SDenis Karpov 2210a45c6cb8SMadhusudhan Chikkature return 0; 2211a45c6cb8SMadhusudhan Chikkature 2212a45c6cb8SMadhusudhan Chikkature err_slot_name: 2213a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 2214db0fefc5SAdrian Hunter if (host->use_reg) 2215db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2216a45c6cb8SMadhusudhan Chikkature err_irq: 2217c5c98927SRussell King if (host->tx_chan) 2218c5c98927SRussell King dma_release_channel(host->tx_chan); 2219c5c98927SRussell King if (host->rx_chan) 2220c5c98927SRussell King dma_release_channel(host->rx_chan); 2221d59d77edSBalaji T K pm_runtime_put_sync(host->dev); 222237f6190dSTony Lindgren pm_runtime_disable(host->dev); 22239618195eSBalaji T K if (host->dbclk) 222494c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2225a45c6cb8SMadhusudhan Chikkature err1: 22261e363e3bSAndreas Fenkart err_gpio: 2227a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 2228db0fefc5SAdrian Hunter err: 2229a45c6cb8SMadhusudhan Chikkature return ret; 2230a45c6cb8SMadhusudhan Chikkature } 2231a45c6cb8SMadhusudhan Chikkature 22326e0ee714SBill Pemberton static int omap_hsmmc_remove(struct platform_device *pdev) 2233a45c6cb8SMadhusudhan Chikkature { 223470a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2235a45c6cb8SMadhusudhan Chikkature 2236fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2237a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 2238db0fefc5SAdrian Hunter if (host->use_reg) 2239db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2240a45c6cb8SMadhusudhan Chikkature 2241c5c98927SRussell King if (host->tx_chan) 2242c5c98927SRussell King dma_release_channel(host->tx_chan); 2243c5c98927SRussell King if (host->rx_chan) 2244c5c98927SRussell King dma_release_channel(host->rx_chan); 2245c5c98927SRussell King 2246fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2247fa4aa2d4SBalaji T K pm_runtime_disable(host->dev); 22489618195eSBalaji T K if (host->dbclk) 224994c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2250a45c6cb8SMadhusudhan Chikkature 22519d1f0286SBalaji T K mmc_free_host(host->mmc); 2252a45c6cb8SMadhusudhan Chikkature 2253a45c6cb8SMadhusudhan Chikkature return 0; 2254a45c6cb8SMadhusudhan Chikkature } 2255a45c6cb8SMadhusudhan Chikkature 2256a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_PM 2257a791daa1SKevin Hilman static int omap_hsmmc_suspend(struct device *dev) 2258a45c6cb8SMadhusudhan Chikkature { 2259927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2260927ce944SFelipe Balbi 2261927ce944SFelipe Balbi if (!host) 2262927ce944SFelipe Balbi return 0; 2263a45c6cb8SMadhusudhan Chikkature 2264fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 226531f9d463SEliad Peller 226631f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 22672cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 22682cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 22692cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 227031f9d463SEliad Peller OMAP_HSMMC_WRITE(host->base, HCTL, 227131f9d463SEliad Peller OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 227231f9d463SEliad Peller } 2273927ce944SFelipe Balbi 22742cd3a2a5SAndreas Fenkart /* do not wake up due to sdio irq */ 22752cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 22762cd3a2a5SAndreas Fenkart !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 22772cd3a2a5SAndreas Fenkart disable_irq(host->wake_irq); 22782cd3a2a5SAndreas Fenkart 2279cd03d9a8SRajendra Nayak if (host->dbclk) 228094c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 22813932afd5SUlf Hansson 2282fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 22833932afd5SUlf Hansson return 0; 2284a45c6cb8SMadhusudhan Chikkature } 2285a45c6cb8SMadhusudhan Chikkature 2286a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 2287a791daa1SKevin Hilman static int omap_hsmmc_resume(struct device *dev) 2288a45c6cb8SMadhusudhan Chikkature { 2289927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2290927ce944SFelipe Balbi 2291927ce944SFelipe Balbi if (!host) 2292927ce944SFelipe Balbi return 0; 2293a45c6cb8SMadhusudhan Chikkature 2294fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 229511dd62a7SDenis Karpov 2296cd03d9a8SRajendra Nayak if (host->dbclk) 229794c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 22982bec0893SAdrian Hunter 229931f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 230070a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 23011b331e69SKim Kyuwon 2302b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2303b62f6228SAdrian Hunter 23042cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 23052cd3a2a5SAndreas Fenkart !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 23062cd3a2a5SAndreas Fenkart enable_irq(host->wake_irq); 23072cd3a2a5SAndreas Fenkart 2308fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2309fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 23103932afd5SUlf Hansson return 0; 2311a45c6cb8SMadhusudhan Chikkature } 2312a45c6cb8SMadhusudhan Chikkature 2313a45c6cb8SMadhusudhan Chikkature #else 231470a3341aSDenis Karpov #define omap_hsmmc_suspend NULL 231570a3341aSDenis Karpov #define omap_hsmmc_resume NULL 2316a45c6cb8SMadhusudhan Chikkature #endif 2317a45c6cb8SMadhusudhan Chikkature 2318fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_suspend(struct device *dev) 2319fa4aa2d4SBalaji T K { 2320fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 23212cd3a2a5SAndreas Fenkart unsigned long flags; 2322f945901fSAndreas Fenkart int ret = 0; 2323fa4aa2d4SBalaji T K 2324fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2325fa4aa2d4SBalaji T K omap_hsmmc_context_save(host); 2326927ce944SFelipe Balbi dev_dbg(dev, "disabled\n"); 2327fa4aa2d4SBalaji T K 23282cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 23292cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 23302cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 23312cd3a2a5SAndreas Fenkart /* disable sdio irq handling to prevent race */ 23322cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 23332cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 2334f945901fSAndreas Fenkart 2335f945901fSAndreas Fenkart if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) { 2336f945901fSAndreas Fenkart /* 2337f945901fSAndreas Fenkart * dat1 line low, pending sdio irq 2338f945901fSAndreas Fenkart * race condition: possible irq handler running on 2339f945901fSAndreas Fenkart * multi-core, abort 2340f945901fSAndreas Fenkart */ 2341f945901fSAndreas Fenkart dev_dbg(dev, "pending sdio irq, abort suspend\n"); 23422cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 2343f945901fSAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 2344f945901fSAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 2345f945901fSAndreas Fenkart pm_runtime_mark_last_busy(dev); 2346f945901fSAndreas Fenkart ret = -EBUSY; 2347f945901fSAndreas Fenkart goto abort; 2348f945901fSAndreas Fenkart } 23492cd3a2a5SAndreas Fenkart 235097978a44SAndreas Fenkart pinctrl_pm_select_idle_state(dev); 235197978a44SAndreas Fenkart 23522cd3a2a5SAndreas Fenkart WARN_ON(host->flags & HSMMC_WAKE_IRQ_ENABLED); 23532cd3a2a5SAndreas Fenkart enable_irq(host->wake_irq); 23542cd3a2a5SAndreas Fenkart host->flags |= HSMMC_WAKE_IRQ_ENABLED; 235597978a44SAndreas Fenkart } else { 235697978a44SAndreas Fenkart pinctrl_pm_select_idle_state(dev); 23572cd3a2a5SAndreas Fenkart } 235897978a44SAndreas Fenkart 2359f945901fSAndreas Fenkart abort: 23602cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2361f945901fSAndreas Fenkart return ret; 2362fa4aa2d4SBalaji T K } 2363fa4aa2d4SBalaji T K 2364fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_resume(struct device *dev) 2365fa4aa2d4SBalaji T K { 2366fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 23672cd3a2a5SAndreas Fenkart unsigned long flags; 2368fa4aa2d4SBalaji T K 2369fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2370fa4aa2d4SBalaji T K omap_hsmmc_context_restore(host); 2371927ce944SFelipe Balbi dev_dbg(dev, "enabled\n"); 2372fa4aa2d4SBalaji T K 23732cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 23742cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 23752cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 23762cd3a2a5SAndreas Fenkart /* sdio irq flag can't change while in runtime suspend */ 23772cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_WAKE_IRQ_ENABLED) { 23782cd3a2a5SAndreas Fenkart disable_irq_nosync(host->wake_irq); 23792cd3a2a5SAndreas Fenkart host->flags &= ~HSMMC_WAKE_IRQ_ENABLED; 23802cd3a2a5SAndreas Fenkart } 23812cd3a2a5SAndreas Fenkart 238297978a44SAndreas Fenkart pinctrl_pm_select_default_state(host->dev); 238397978a44SAndreas Fenkart 238497978a44SAndreas Fenkart /* irq lost, if pinmux incorrect */ 23852cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 23862cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 23872cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 238897978a44SAndreas Fenkart } else { 238997978a44SAndreas Fenkart pinctrl_pm_select_default_state(host->dev); 23902cd3a2a5SAndreas Fenkart } 23912cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2392fa4aa2d4SBalaji T K return 0; 2393fa4aa2d4SBalaji T K } 2394fa4aa2d4SBalaji T K 2395a791daa1SKevin Hilman static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 239670a3341aSDenis Karpov .suspend = omap_hsmmc_suspend, 239770a3341aSDenis Karpov .resume = omap_hsmmc_resume, 2398fa4aa2d4SBalaji T K .runtime_suspend = omap_hsmmc_runtime_suspend, 2399fa4aa2d4SBalaji T K .runtime_resume = omap_hsmmc_runtime_resume, 2400a791daa1SKevin Hilman }; 2401a791daa1SKevin Hilman 2402a791daa1SKevin Hilman static struct platform_driver omap_hsmmc_driver = { 2403efa25fd3SFelipe Balbi .probe = omap_hsmmc_probe, 24040433c143SBill Pemberton .remove = omap_hsmmc_remove, 2405a45c6cb8SMadhusudhan Chikkature .driver = { 2406a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 2407a791daa1SKevin Hilman .pm = &omap_hsmmc_dev_pm_ops, 240846856a68SRajendra Nayak .of_match_table = of_match_ptr(omap_mmc_of_match), 2409a45c6cb8SMadhusudhan Chikkature }, 2410a45c6cb8SMadhusudhan Chikkature }; 2411a45c6cb8SMadhusudhan Chikkature 2412b796450bSFelipe Balbi module_platform_driver(omap_hsmmc_driver); 2413a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2414a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 2415a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 2416a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 2417