1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20ac330f44SAndy Shevchenko #include <linux/kernel.h> 21d900f712SDenis Karpov #include <linux/debugfs.h> 22c5c98927SRussell King #include <linux/dmaengine.h> 23d900f712SDenis Karpov #include <linux/seq_file.h> 24031cd037SFelipe Balbi #include <linux/sizes.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 29a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 30a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 3146856a68SRajendra Nayak #include <linux/of.h> 322cd3a2a5SAndreas Fenkart #include <linux/of_irq.h> 3346856a68SRajendra Nayak #include <linux/of_gpio.h> 3446856a68SRajendra Nayak #include <linux/of_device.h> 35ee526d51SBalaji T K #include <linux/omap-dmaengine.h> 36a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 3713189e78SJarkko Lavinen #include <linux/mmc/core.h> 3893caf8e6SAdrian Hunter #include <linux/mmc/mmc.h> 3941afa314SNeilBrown #include <linux/mmc/slot-gpio.h> 40a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 412cd3a2a5SAndreas Fenkart #include <linux/irq.h> 42db0fefc5SAdrian Hunter #include <linux/gpio.h> 43db0fefc5SAdrian Hunter #include <linux/regulator/consumer.h> 4446b76035SDaniel Mack #include <linux/pinctrl/consumer.h> 45fa4aa2d4SBalaji T K #include <linux/pm_runtime.h> 465b83b223STony Lindgren #include <linux/pm_wakeirq.h> 4755143438SAndreas Fenkart #include <linux/platform_data/hsmmc-omap.h> 48a45c6cb8SMadhusudhan Chikkature 49a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 5011dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS 0x0014 51a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 52a2e77152SBalaji T K #define OMAP_HSMMC_SDMASA 0x0100 53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 57a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 58a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 59a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 60a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 61bb0635f0SAndreas Fenkart #define OMAP_HSMMC_PSTATE 0x0124 62a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 63a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 64a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 65a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 66a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 67a2e77152SBalaji T K #define OMAP_HSMMC_AC12 0x013C 68a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 69a45c6cb8SMadhusudhan Chikkature 70a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 71a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 72cd587096SHebbar, Gururaja #define HSS (1 << 21) 73a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 74a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 75eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 761b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 77a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 78a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 79a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 80a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 81a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 82a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 83a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 84a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 85ed164182SBalaji T K #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ 86a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 87a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 88a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 89a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 90a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 91a2e77152SBalaji T K #define ACEN_ACMD23 (2 << 2) 92a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 93a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 94a7e96879SVenkatraman S #define DMAE 0x1 95a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 96a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 97a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 98cd587096SHebbar, Gururaja #define HSPE (1 << 2) 995a52b08bSBalaji T K #define IWE (1 << 24) 10003b5d924SBalaji T K #define DDR (1 << 19) 1015a52b08bSBalaji T K #define CLKEXTFREE (1 << 16) 1025a52b08bSBalaji T K #define CTPL (1 << 11) 10373153010SJarkko Lavinen #define DW8 (1 << 5) 104a45c6cb8SMadhusudhan Chikkature #define OD 0x1 105a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 106a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 107a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 108a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 109a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 11011dd62a7SDenis Karpov #define SOFTRESET (1 << 1) 111a45c6cb8SMadhusudhan Chikkature 112f945901fSAndreas Fenkart /* PSTATE */ 113f945901fSAndreas Fenkart #define DLEV_DAT(x) (1 << (20 + (x))) 114f945901fSAndreas Fenkart 115a7e96879SVenkatraman S /* Interrupt masks for IE and ISE register */ 116a7e96879SVenkatraman S #define CC_EN (1 << 0) 117a7e96879SVenkatraman S #define TC_EN (1 << 1) 118a7e96879SVenkatraman S #define BWR_EN (1 << 4) 119a7e96879SVenkatraman S #define BRR_EN (1 << 5) 1202cd3a2a5SAndreas Fenkart #define CIRQ_EN (1 << 8) 121a7e96879SVenkatraman S #define ERR_EN (1 << 15) 122a7e96879SVenkatraman S #define CTO_EN (1 << 16) 123a7e96879SVenkatraman S #define CCRC_EN (1 << 17) 124a7e96879SVenkatraman S #define CEB_EN (1 << 18) 125a7e96879SVenkatraman S #define CIE_EN (1 << 19) 126a7e96879SVenkatraman S #define DTO_EN (1 << 20) 127a7e96879SVenkatraman S #define DCRC_EN (1 << 21) 128a7e96879SVenkatraman S #define DEB_EN (1 << 22) 129a2e77152SBalaji T K #define ACE_EN (1 << 24) 130a7e96879SVenkatraman S #define CERR_EN (1 << 28) 131a7e96879SVenkatraman S #define BADA_EN (1 << 29) 132a7e96879SVenkatraman S 133a2e77152SBalaji T K #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\ 134a7e96879SVenkatraman S DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ 135a7e96879SVenkatraman S BRR_EN | BWR_EN | TC_EN | CC_EN) 136a7e96879SVenkatraman S 137a2e77152SBalaji T K #define CNI (1 << 7) 138a2e77152SBalaji T K #define ACIE (1 << 4) 139a2e77152SBalaji T K #define ACEB (1 << 3) 140a2e77152SBalaji T K #define ACCE (1 << 2) 141a2e77152SBalaji T K #define ACTO (1 << 1) 142a2e77152SBalaji T K #define ACNE (1 << 0) 143a2e77152SBalaji T K 144fa4aa2d4SBalaji T K #define MMC_AUTOSUSPEND_DELAY 100 1451e881786SJianpeng Ma #define MMC_TIMEOUT_MS 20 /* 20 mSec */ 1461e881786SJianpeng Ma #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ 1476b206efeSAndy Shevchenko #define OMAP_MMC_MIN_CLOCK 400000 1486b206efeSAndy Shevchenko #define OMAP_MMC_MAX_CLOCK 52000000 1490005ae73SKishore Kadiyala #define DRIVER_NAME "omap_hsmmc" 150a45c6cb8SMadhusudhan Chikkature 151e99448ffSBalaji T K #define VDD_1V8 1800000 /* 180000 uV */ 152e99448ffSBalaji T K #define VDD_3V0 3000000 /* 300000 uV */ 153e99448ffSBalaji T K #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1) 154e99448ffSBalaji T K 155a45c6cb8SMadhusudhan Chikkature /* 156a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 157a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 158a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 159a45c6cb8SMadhusudhan Chikkature */ 160326119c9SAndreas Fenkart #define mmc_pdata(host) host->pdata 161a45c6cb8SMadhusudhan Chikkature 162a45c6cb8SMadhusudhan Chikkature /* 163a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 164a45c6cb8SMadhusudhan Chikkature */ 165a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 166a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 167a45c6cb8SMadhusudhan Chikkature 168a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 169a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 170a45c6cb8SMadhusudhan Chikkature 1719782aff8SPer Forlin struct omap_hsmmc_next { 1729782aff8SPer Forlin unsigned int dma_len; 1739782aff8SPer Forlin s32 cookie; 1749782aff8SPer Forlin }; 1759782aff8SPer Forlin 17670a3341aSDenis Karpov struct omap_hsmmc_host { 177a45c6cb8SMadhusudhan Chikkature struct device *dev; 178a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 179a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 180a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 181a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 182a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 183a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 184e99448ffSBalaji T K struct regulator *pbias; 185e99448ffSBalaji T K bool pbias_enabled; 186a45c6cb8SMadhusudhan Chikkature void __iomem *base; 1873f77f702SKishon Vijay Abraham I int vqmmc_enabled; 188a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 1894dffd7a2SAdrian Hunter spinlock_t irq_lock; /* Prevent races with irq handler */ 190a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 1910ccd76d4SJuha Yrjola unsigned int dma_sg_idx; 192a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 193a3621465SAdrian Hunter unsigned char power_mode; 194a45c6cb8SMadhusudhan Chikkature int suspended; 1950a82e06eSTony Lindgren u32 con; 1960a82e06eSTony Lindgren u32 hctl; 1970a82e06eSTony Lindgren u32 sysctl; 1980a82e06eSTony Lindgren u32 capa; 199a45c6cb8SMadhusudhan Chikkature int irq; 2002cd3a2a5SAndreas Fenkart int wake_irq; 201a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 202c5c98927SRussell King struct dma_chan *tx_chan; 203c5c98927SRussell King struct dma_chan *rx_chan; 2044a694dc9SAdrian Hunter int response_busy; 20511dd62a7SDenis Karpov int context_loss; 206b62f6228SAdrian Hunter int protect_card; 207b62f6228SAdrian Hunter int reqs_blocked; 208b417577dSAdrian Hunter int req_in_progress; 2096e3076c2SBalaji T K unsigned long clk_rate; 210a2e77152SBalaji T K unsigned int flags; 2112cd3a2a5SAndreas Fenkart #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */ 2122cd3a2a5SAndreas Fenkart #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */ 2139782aff8SPer Forlin struct omap_hsmmc_next next_data; 21455143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata; 215b5cd43f0SAndreas Fenkart 216b5cd43f0SAndreas Fenkart /* return MMC cover switch state, can be NULL if not supported. 217b5cd43f0SAndreas Fenkart * 218b5cd43f0SAndreas Fenkart * possible return values: 219b5cd43f0SAndreas Fenkart * 0 - closed 220b5cd43f0SAndreas Fenkart * 1 - open 221b5cd43f0SAndreas Fenkart */ 22280412ca8SAndreas Fenkart int (*get_cover_state)(struct device *dev); 223b5cd43f0SAndreas Fenkart 22480412ca8SAndreas Fenkart int (*card_detect)(struct device *dev); 225a45c6cb8SMadhusudhan Chikkature }; 226a45c6cb8SMadhusudhan Chikkature 22759445b10SNishanth Menon struct omap_mmc_of_data { 22859445b10SNishanth Menon u32 reg_offset; 22959445b10SNishanth Menon u8 controller_flags; 23059445b10SNishanth Menon }; 23159445b10SNishanth Menon 232bf129e1cSBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host); 233bf129e1cSBalaji T K 23480412ca8SAndreas Fenkart static int omap_hsmmc_card_detect(struct device *dev) 235db0fefc5SAdrian Hunter { 2369ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 237db0fefc5SAdrian Hunter 23841afa314SNeilBrown return mmc_gpio_get_cd(host->mmc); 239db0fefc5SAdrian Hunter } 240db0fefc5SAdrian Hunter 24180412ca8SAndreas Fenkart static int omap_hsmmc_get_cover_state(struct device *dev) 242db0fefc5SAdrian Hunter { 2439ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 244db0fefc5SAdrian Hunter 24541afa314SNeilBrown return mmc_gpio_get_cd(host->mmc); 246db0fefc5SAdrian Hunter } 247db0fefc5SAdrian Hunter 248b702b106SAdrian Hunter #ifdef CONFIG_REGULATOR 249b702b106SAdrian Hunter 2502a17f844SKishon Vijay Abraham I static int omap_hsmmc_enable_supply(struct mmc_host *mmc, int vdd) 2512a17f844SKishon Vijay Abraham I { 2522a17f844SKishon Vijay Abraham I int ret; 2533f77f702SKishon Vijay Abraham I struct omap_hsmmc_host *host = mmc_priv(mmc); 2542a17f844SKishon Vijay Abraham I 2552a17f844SKishon Vijay Abraham I if (mmc->supply.vmmc) { 2562a17f844SKishon Vijay Abraham I ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 2572a17f844SKishon Vijay Abraham I if (ret) 2582a17f844SKishon Vijay Abraham I return ret; 2592a17f844SKishon Vijay Abraham I } 2602a17f844SKishon Vijay Abraham I 2612a17f844SKishon Vijay Abraham I /* Enable interface voltage rail, if needed */ 2623f77f702SKishon Vijay Abraham I if (mmc->supply.vqmmc && !host->vqmmc_enabled) { 2632a17f844SKishon Vijay Abraham I ret = regulator_enable(mmc->supply.vqmmc); 2642a17f844SKishon Vijay Abraham I if (ret) { 2652a17f844SKishon Vijay Abraham I dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n"); 2662a17f844SKishon Vijay Abraham I goto err_vqmmc; 2672a17f844SKishon Vijay Abraham I } 2683f77f702SKishon Vijay Abraham I host->vqmmc_enabled = 1; 2692a17f844SKishon Vijay Abraham I } 2702a17f844SKishon Vijay Abraham I 2712a17f844SKishon Vijay Abraham I return 0; 2722a17f844SKishon Vijay Abraham I 2732a17f844SKishon Vijay Abraham I err_vqmmc: 2742a17f844SKishon Vijay Abraham I if (mmc->supply.vmmc) 2752a17f844SKishon Vijay Abraham I mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 2762a17f844SKishon Vijay Abraham I 2772a17f844SKishon Vijay Abraham I return ret; 2782a17f844SKishon Vijay Abraham I } 2792a17f844SKishon Vijay Abraham I 2802a17f844SKishon Vijay Abraham I static int omap_hsmmc_disable_supply(struct mmc_host *mmc) 2812a17f844SKishon Vijay Abraham I { 2822a17f844SKishon Vijay Abraham I int ret; 2832a17f844SKishon Vijay Abraham I int status; 2843f77f702SKishon Vijay Abraham I struct omap_hsmmc_host *host = mmc_priv(mmc); 2852a17f844SKishon Vijay Abraham I 2863f77f702SKishon Vijay Abraham I if (mmc->supply.vqmmc && host->vqmmc_enabled) { 2872a17f844SKishon Vijay Abraham I ret = regulator_disable(mmc->supply.vqmmc); 2882a17f844SKishon Vijay Abraham I if (ret) { 2892a17f844SKishon Vijay Abraham I dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n"); 2902a17f844SKishon Vijay Abraham I return ret; 2912a17f844SKishon Vijay Abraham I } 2923f77f702SKishon Vijay Abraham I host->vqmmc_enabled = 0; 2932a17f844SKishon Vijay Abraham I } 2942a17f844SKishon Vijay Abraham I 2952a17f844SKishon Vijay Abraham I if (mmc->supply.vmmc) { 2962a17f844SKishon Vijay Abraham I ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 2972a17f844SKishon Vijay Abraham I if (ret) 2982a17f844SKishon Vijay Abraham I goto err_set_ocr; 2992a17f844SKishon Vijay Abraham I } 3002a17f844SKishon Vijay Abraham I 3012a17f844SKishon Vijay Abraham I return 0; 3022a17f844SKishon Vijay Abraham I 3032a17f844SKishon Vijay Abraham I err_set_ocr: 3042a17f844SKishon Vijay Abraham I if (mmc->supply.vqmmc) { 3052a17f844SKishon Vijay Abraham I status = regulator_enable(mmc->supply.vqmmc); 3062a17f844SKishon Vijay Abraham I if (status) 3072a17f844SKishon Vijay Abraham I dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n"); 3082a17f844SKishon Vijay Abraham I } 3092a17f844SKishon Vijay Abraham I 3102a17f844SKishon Vijay Abraham I return ret; 3112a17f844SKishon Vijay Abraham I } 3122a17f844SKishon Vijay Abraham I 313ec85c95eSKishon Vijay Abraham I static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on, 314ec85c95eSKishon Vijay Abraham I int vdd) 315ec85c95eSKishon Vijay Abraham I { 316ec85c95eSKishon Vijay Abraham I int ret; 317ec85c95eSKishon Vijay Abraham I 318ec85c95eSKishon Vijay Abraham I if (!host->pbias) 319ec85c95eSKishon Vijay Abraham I return 0; 320ec85c95eSKishon Vijay Abraham I 321ec85c95eSKishon Vijay Abraham I if (power_on) { 322ec85c95eSKishon Vijay Abraham I if (vdd <= VDD_165_195) 323ec85c95eSKishon Vijay Abraham I ret = regulator_set_voltage(host->pbias, VDD_1V8, 324ec85c95eSKishon Vijay Abraham I VDD_1V8); 325ec85c95eSKishon Vijay Abraham I else 326ec85c95eSKishon Vijay Abraham I ret = regulator_set_voltage(host->pbias, VDD_3V0, 327ec85c95eSKishon Vijay Abraham I VDD_3V0); 328ec85c95eSKishon Vijay Abraham I if (ret < 0) { 329ec85c95eSKishon Vijay Abraham I dev_err(host->dev, "pbias set voltage fail\n"); 330ec85c95eSKishon Vijay Abraham I return ret; 331ec85c95eSKishon Vijay Abraham I } 332ec85c95eSKishon Vijay Abraham I 333ec85c95eSKishon Vijay Abraham I if (host->pbias_enabled == 0) { 334ec85c95eSKishon Vijay Abraham I ret = regulator_enable(host->pbias); 335ec85c95eSKishon Vijay Abraham I if (ret) { 336ec85c95eSKishon Vijay Abraham I dev_err(host->dev, "pbias reg enable fail\n"); 337ec85c95eSKishon Vijay Abraham I return ret; 338ec85c95eSKishon Vijay Abraham I } 339ec85c95eSKishon Vijay Abraham I host->pbias_enabled = 1; 340ec85c95eSKishon Vijay Abraham I } 341ec85c95eSKishon Vijay Abraham I } else { 342ec85c95eSKishon Vijay Abraham I if (host->pbias_enabled == 1) { 343ec85c95eSKishon Vijay Abraham I ret = regulator_disable(host->pbias); 344ec85c95eSKishon Vijay Abraham I if (ret) { 345ec85c95eSKishon Vijay Abraham I dev_err(host->dev, "pbias reg disable fail\n"); 346ec85c95eSKishon Vijay Abraham I return ret; 347ec85c95eSKishon Vijay Abraham I } 348ec85c95eSKishon Vijay Abraham I host->pbias_enabled = 0; 349ec85c95eSKishon Vijay Abraham I } 350ec85c95eSKishon Vijay Abraham I } 351ec85c95eSKishon Vijay Abraham I 352ec85c95eSKishon Vijay Abraham I return 0; 353ec85c95eSKishon Vijay Abraham I } 354ec85c95eSKishon Vijay Abraham I 35580412ca8SAndreas Fenkart static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd) 356db0fefc5SAdrian Hunter { 357db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 358db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 359aa9a6801SKishon Vijay Abraham I struct mmc_host *mmc = host->mmc; 360db0fefc5SAdrian Hunter int ret = 0; 361db0fefc5SAdrian Hunter 362f7f0f035SAndreas Fenkart if (mmc_pdata(host)->set_power) 363f7f0f035SAndreas Fenkart return mmc_pdata(host)->set_power(dev, power_on, vdd); 364f7f0f035SAndreas Fenkart 365db0fefc5SAdrian Hunter /* 366db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 367db0fefc5SAdrian Hunter * voltage always-on regulator. 368db0fefc5SAdrian Hunter */ 369aa9a6801SKishon Vijay Abraham I if (!mmc->supply.vmmc) 370db0fefc5SAdrian Hunter return 0; 371db0fefc5SAdrian Hunter 372326119c9SAndreas Fenkart if (mmc_pdata(host)->before_set_reg) 37380412ca8SAndreas Fenkart mmc_pdata(host)->before_set_reg(dev, power_on, vdd); 374db0fefc5SAdrian Hunter 375ec85c95eSKishon Vijay Abraham I ret = omap_hsmmc_set_pbias(host, false, 0); 376ec85c95eSKishon Vijay Abraham I if (ret) 377229f3292SKishon Vijay Abraham I return ret; 378e99448ffSBalaji T K 379db0fefc5SAdrian Hunter /* 380db0fefc5SAdrian Hunter * Assume Vcc regulator is used only to power the card ... OMAP 381db0fefc5SAdrian Hunter * VDDS is used to power the pins, optionally with a transceiver to 382db0fefc5SAdrian Hunter * support cards using voltages other than VDDS (1.8V nominal). When a 383db0fefc5SAdrian Hunter * transceiver is used, DAT3..7 are muxed as transceiver control pins. 384db0fefc5SAdrian Hunter * 385db0fefc5SAdrian Hunter * In some cases this regulator won't support enable/disable; 386db0fefc5SAdrian Hunter * e.g. it's a fixed rail for a WLAN chip. 387db0fefc5SAdrian Hunter * 388db0fefc5SAdrian Hunter * In other cases vcc_aux switches interface power. Example, for 389db0fefc5SAdrian Hunter * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 390db0fefc5SAdrian Hunter * chips/cards need an interface voltage rail too. 391db0fefc5SAdrian Hunter */ 392db0fefc5SAdrian Hunter if (power_on) { 3932a17f844SKishon Vijay Abraham I ret = omap_hsmmc_enable_supply(mmc, vdd); 394229f3292SKishon Vijay Abraham I if (ret) 395229f3292SKishon Vijay Abraham I return ret; 39697fe7e5aSKishon Vijay Abraham I 39797fe7e5aSKishon Vijay Abraham I ret = omap_hsmmc_set_pbias(host, true, vdd); 39897fe7e5aSKishon Vijay Abraham I if (ret) 39997fe7e5aSKishon Vijay Abraham I goto err_set_voltage; 400db0fefc5SAdrian Hunter } else { 4012a17f844SKishon Vijay Abraham I ret = omap_hsmmc_disable_supply(mmc); 402229f3292SKishon Vijay Abraham I if (ret) 403229f3292SKishon Vijay Abraham I return ret; 40499fc5131SLinus Walleij } 405db0fefc5SAdrian Hunter 406326119c9SAndreas Fenkart if (mmc_pdata(host)->after_set_reg) 40780412ca8SAndreas Fenkart mmc_pdata(host)->after_set_reg(dev, power_on, vdd); 408db0fefc5SAdrian Hunter 409229f3292SKishon Vijay Abraham I return 0; 410229f3292SKishon Vijay Abraham I 411229f3292SKishon Vijay Abraham I err_set_voltage: 4122a17f844SKishon Vijay Abraham I omap_hsmmc_disable_supply(mmc); 413229f3292SKishon Vijay Abraham I 414db0fefc5SAdrian Hunter return ret; 415db0fefc5SAdrian Hunter } 416db0fefc5SAdrian Hunter 417c8518efaSKishon Vijay Abraham I static int omap_hsmmc_disable_boot_regulator(struct regulator *reg) 418c8518efaSKishon Vijay Abraham I { 419c8518efaSKishon Vijay Abraham I int ret; 420c8518efaSKishon Vijay Abraham I 421c8518efaSKishon Vijay Abraham I if (!reg) 422c8518efaSKishon Vijay Abraham I return 0; 423c8518efaSKishon Vijay Abraham I 424c8518efaSKishon Vijay Abraham I if (regulator_is_enabled(reg)) { 425c8518efaSKishon Vijay Abraham I ret = regulator_enable(reg); 426c8518efaSKishon Vijay Abraham I if (ret) 427c8518efaSKishon Vijay Abraham I return ret; 428c8518efaSKishon Vijay Abraham I 429c8518efaSKishon Vijay Abraham I ret = regulator_disable(reg); 430c8518efaSKishon Vijay Abraham I if (ret) 431c8518efaSKishon Vijay Abraham I return ret; 432c8518efaSKishon Vijay Abraham I } 433c8518efaSKishon Vijay Abraham I 434c8518efaSKishon Vijay Abraham I return 0; 435c8518efaSKishon Vijay Abraham I } 436c8518efaSKishon Vijay Abraham I 437c8518efaSKishon Vijay Abraham I static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host) 438c8518efaSKishon Vijay Abraham I { 439c8518efaSKishon Vijay Abraham I struct mmc_host *mmc = host->mmc; 440c8518efaSKishon Vijay Abraham I int ret; 441c8518efaSKishon Vijay Abraham I 442c8518efaSKishon Vijay Abraham I /* 443c8518efaSKishon Vijay Abraham I * disable regulators enabled during boot and get the usecount 444c8518efaSKishon Vijay Abraham I * right so that regulators can be enabled/disabled by checking 445c8518efaSKishon Vijay Abraham I * the return value of regulator_is_enabled 446c8518efaSKishon Vijay Abraham I */ 447c8518efaSKishon Vijay Abraham I ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc); 448c8518efaSKishon Vijay Abraham I if (ret) { 449c8518efaSKishon Vijay Abraham I dev_err(host->dev, "fail to disable boot enabled vmmc reg\n"); 450c8518efaSKishon Vijay Abraham I return ret; 451c8518efaSKishon Vijay Abraham I } 452c8518efaSKishon Vijay Abraham I 453c8518efaSKishon Vijay Abraham I ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc); 454c8518efaSKishon Vijay Abraham I if (ret) { 455c8518efaSKishon Vijay Abraham I dev_err(host->dev, 456c8518efaSKishon Vijay Abraham I "fail to disable boot enabled vmmc_aux reg\n"); 457c8518efaSKishon Vijay Abraham I return ret; 458c8518efaSKishon Vijay Abraham I } 459c8518efaSKishon Vijay Abraham I 460c8518efaSKishon Vijay Abraham I ret = omap_hsmmc_disable_boot_regulator(host->pbias); 461c8518efaSKishon Vijay Abraham I if (ret) { 462c8518efaSKishon Vijay Abraham I dev_err(host->dev, 463c8518efaSKishon Vijay Abraham I "failed to disable boot enabled pbias reg\n"); 464c8518efaSKishon Vijay Abraham I return ret; 465c8518efaSKishon Vijay Abraham I } 466c8518efaSKishon Vijay Abraham I 467c8518efaSKishon Vijay Abraham I return 0; 468c8518efaSKishon Vijay Abraham I } 469c8518efaSKishon Vijay Abraham I 470db0fefc5SAdrian Hunter static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 471db0fefc5SAdrian Hunter { 47264be9782Skishore kadiyala int ocr_value = 0; 4737d607f91SKishon Vijay Abraham I int ret; 474aa9a6801SKishon Vijay Abraham I struct mmc_host *mmc = host->mmc; 475db0fefc5SAdrian Hunter 476f7f0f035SAndreas Fenkart if (mmc_pdata(host)->set_power) 477f7f0f035SAndreas Fenkart return 0; 478f7f0f035SAndreas Fenkart 479aa9a6801SKishon Vijay Abraham I mmc->supply.vmmc = devm_regulator_get_optional(host->dev, "vmmc"); 480aa9a6801SKishon Vijay Abraham I if (IS_ERR(mmc->supply.vmmc)) { 481aa9a6801SKishon Vijay Abraham I ret = PTR_ERR(mmc->supply.vmmc); 4827d607f91SKishon Vijay Abraham I if (ret != -ENODEV) 4837d607f91SKishon Vijay Abraham I return ret; 4847d607f91SKishon Vijay Abraham I dev_dbg(host->dev, "unable to get vmmc regulator %ld\n", 485aa9a6801SKishon Vijay Abraham I PTR_ERR(mmc->supply.vmmc)); 486aa9a6801SKishon Vijay Abraham I mmc->supply.vmmc = NULL; 487db0fefc5SAdrian Hunter } else { 488aa9a6801SKishon Vijay Abraham I ocr_value = mmc_regulator_get_ocrmask(mmc->supply.vmmc); 489b49069fcSKishon Vijay Abraham I if (ocr_value > 0) 490326119c9SAndreas Fenkart mmc_pdata(host)->ocr_mask = ocr_value; 491987fd49bSBalaji T K } 492db0fefc5SAdrian Hunter 493db0fefc5SAdrian Hunter /* Allow an aux regulator */ 494aa9a6801SKishon Vijay Abraham I mmc->supply.vqmmc = devm_regulator_get_optional(host->dev, "vmmc_aux"); 495aa9a6801SKishon Vijay Abraham I if (IS_ERR(mmc->supply.vqmmc)) { 496aa9a6801SKishon Vijay Abraham I ret = PTR_ERR(mmc->supply.vqmmc); 4976a9b2ff0SKishon Vijay Abraham I if (ret != -ENODEV) 4986a9b2ff0SKishon Vijay Abraham I return ret; 4996a9b2ff0SKishon Vijay Abraham I dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n", 500aa9a6801SKishon Vijay Abraham I PTR_ERR(mmc->supply.vqmmc)); 501aa9a6801SKishon Vijay Abraham I mmc->supply.vqmmc = NULL; 5026a9b2ff0SKishon Vijay Abraham I } 503db0fefc5SAdrian Hunter 504c299dc39SKishon Vijay Abraham I host->pbias = devm_regulator_get_optional(host->dev, "pbias"); 505c299dc39SKishon Vijay Abraham I if (IS_ERR(host->pbias)) { 506c299dc39SKishon Vijay Abraham I ret = PTR_ERR(host->pbias); 5076a9b2ff0SKishon Vijay Abraham I if (ret != -ENODEV) 5086a9b2ff0SKishon Vijay Abraham I return ret; 5096a9b2ff0SKishon Vijay Abraham I dev_dbg(host->dev, "unable to get pbias regulator %ld\n", 510c299dc39SKishon Vijay Abraham I PTR_ERR(host->pbias)); 511c299dc39SKishon Vijay Abraham I host->pbias = NULL; 5126a9b2ff0SKishon Vijay Abraham I } 513e99448ffSBalaji T K 514b1c1df7aSBalaji T K /* For eMMC do not power off when not in sleep state */ 515326119c9SAndreas Fenkart if (mmc_pdata(host)->no_regulator_off_init) 516b1c1df7aSBalaji T K return 0; 517e840ce13SAdrian Hunter 518c8518efaSKishon Vijay Abraham I ret = omap_hsmmc_disable_boot_regulators(host); 519c8518efaSKishon Vijay Abraham I if (ret) 520c8518efaSKishon Vijay Abraham I return ret; 521db0fefc5SAdrian Hunter 522db0fefc5SAdrian Hunter return 0; 523db0fefc5SAdrian Hunter } 524db0fefc5SAdrian Hunter 525b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 526b702b106SAdrian Hunter { 527b702b106SAdrian Hunter return 1; 528b702b106SAdrian Hunter } 529b702b106SAdrian Hunter 530b702b106SAdrian Hunter #else 531b702b106SAdrian Hunter 532f7f0f035SAndreas Fenkart static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd) 533f7f0f035SAndreas Fenkart { 534f7f0f035SAndreas Fenkart return 0; 535f7f0f035SAndreas Fenkart } 536f7f0f035SAndreas Fenkart 537b702b106SAdrian Hunter static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 538b702b106SAdrian Hunter { 539b702b106SAdrian Hunter return -EINVAL; 540b702b106SAdrian Hunter } 541b702b106SAdrian Hunter 542b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 543b702b106SAdrian Hunter { 544b702b106SAdrian Hunter return 0; 545b702b106SAdrian Hunter } 546b702b106SAdrian Hunter 547b702b106SAdrian Hunter #endif 548b702b106SAdrian Hunter 549cde592cbSAndreas Fenkart static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id); 55041afa314SNeilBrown 55141afa314SNeilBrown static int omap_hsmmc_gpio_init(struct mmc_host *mmc, 55241afa314SNeilBrown struct omap_hsmmc_host *host, 5531e363e3bSAndreas Fenkart struct omap_hsmmc_platform_data *pdata) 554b702b106SAdrian Hunter { 555b702b106SAdrian Hunter int ret; 556b702b106SAdrian Hunter 557b7a5646fSAndreas Fenkart if (gpio_is_valid(pdata->gpio_cod)) { 558b7a5646fSAndreas Fenkart ret = mmc_gpio_request_cd(mmc, pdata->gpio_cod, 0); 559b702b106SAdrian Hunter if (ret) 560b702b106SAdrian Hunter return ret; 561cde592cbSAndreas Fenkart 562cde592cbSAndreas Fenkart host->get_cover_state = omap_hsmmc_get_cover_state; 563cde592cbSAndreas Fenkart mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq); 564b7a5646fSAndreas Fenkart } else if (gpio_is_valid(pdata->gpio_cd)) { 565b7a5646fSAndreas Fenkart ret = mmc_gpio_request_cd(mmc, pdata->gpio_cd, 0); 566cde592cbSAndreas Fenkart if (ret) 567cde592cbSAndreas Fenkart return ret; 568cde592cbSAndreas Fenkart 569cde592cbSAndreas Fenkart host->card_detect = omap_hsmmc_card_detect; 570326119c9SAndreas Fenkart } 571b702b106SAdrian Hunter 572326119c9SAndreas Fenkart if (gpio_is_valid(pdata->gpio_wp)) { 57341afa314SNeilBrown ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp); 574b702b106SAdrian Hunter if (ret) 57541afa314SNeilBrown return ret; 576326119c9SAndreas Fenkart } 577b702b106SAdrian Hunter 578b702b106SAdrian Hunter return 0; 579b702b106SAdrian Hunter } 580b702b106SAdrian Hunter 581a45c6cb8SMadhusudhan Chikkature /* 582e0c7f99bSAndy Shevchenko * Start clock to the card 583e0c7f99bSAndy Shevchenko */ 584e0c7f99bSAndy Shevchenko static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 585e0c7f99bSAndy Shevchenko { 586e0c7f99bSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 587e0c7f99bSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 588e0c7f99bSAndy Shevchenko } 589e0c7f99bSAndy Shevchenko 590e0c7f99bSAndy Shevchenko /* 591a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 592a45c6cb8SMadhusudhan Chikkature */ 59370a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 594a45c6cb8SMadhusudhan Chikkature { 595a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 596a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 597a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 5987122bbb0SMasanari Iida dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); 599a45c6cb8SMadhusudhan Chikkature } 600a45c6cb8SMadhusudhan Chikkature 60193caf8e6SAdrian Hunter static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 60293caf8e6SAdrian Hunter struct mmc_command *cmd) 603b417577dSAdrian Hunter { 6042cd3a2a5SAndreas Fenkart u32 irq_mask = INT_EN_MASK; 6052cd3a2a5SAndreas Fenkart unsigned long flags; 606b417577dSAdrian Hunter 607b417577dSAdrian Hunter if (host->use_dma) 6082cd3a2a5SAndreas Fenkart irq_mask &= ~(BRR_EN | BWR_EN); 609b417577dSAdrian Hunter 61093caf8e6SAdrian Hunter /* Disable timeout for erases */ 61193caf8e6SAdrian Hunter if (cmd->opcode == MMC_ERASE) 612a7e96879SVenkatraman S irq_mask &= ~DTO_EN; 61393caf8e6SAdrian Hunter 6142cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 615b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 616b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 6172cd3a2a5SAndreas Fenkart 6182cd3a2a5SAndreas Fenkart /* latch pending CIRQ, but don't signal MMC core */ 6192cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 6202cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 621b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 6222cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 623b417577dSAdrian Hunter } 624b417577dSAdrian Hunter 625b417577dSAdrian Hunter static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 626b417577dSAdrian Hunter { 6272cd3a2a5SAndreas Fenkart u32 irq_mask = 0; 6282cd3a2a5SAndreas Fenkart unsigned long flags; 6292cd3a2a5SAndreas Fenkart 6302cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 6312cd3a2a5SAndreas Fenkart /* no transfer running but need to keep cirq if enabled */ 6322cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 6332cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 6342cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 6352cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 636b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 6372cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 638b417577dSAdrian Hunter } 639b417577dSAdrian Hunter 640ac330f44SAndy Shevchenko /* Calculate divisor for the given clock frequency */ 641d83b6e03SBalaji TK static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 642ac330f44SAndy Shevchenko { 643ac330f44SAndy Shevchenko u16 dsor = 0; 644ac330f44SAndy Shevchenko 645ac330f44SAndy Shevchenko if (ios->clock) { 646d83b6e03SBalaji TK dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 647ed164182SBalaji T K if (dsor > CLKD_MAX) 648ed164182SBalaji T K dsor = CLKD_MAX; 649ac330f44SAndy Shevchenko } 650ac330f44SAndy Shevchenko 651ac330f44SAndy Shevchenko return dsor; 652ac330f44SAndy Shevchenko } 653ac330f44SAndy Shevchenko 6545934df2fSAndy Shevchenko static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 6555934df2fSAndy Shevchenko { 6565934df2fSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6575934df2fSAndy Shevchenko unsigned long regval; 6585934df2fSAndy Shevchenko unsigned long timeout; 659cd587096SHebbar, Gururaja unsigned long clkdiv; 6605934df2fSAndy Shevchenko 6618986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 6625934df2fSAndy Shevchenko 6635934df2fSAndy Shevchenko omap_hsmmc_stop_clock(host); 6645934df2fSAndy Shevchenko 6655934df2fSAndy Shevchenko regval = OMAP_HSMMC_READ(host->base, SYSCTL); 6665934df2fSAndy Shevchenko regval = regval & ~(CLKD_MASK | DTO_MASK); 667cd587096SHebbar, Gururaja clkdiv = calc_divisor(host, ios); 668cd587096SHebbar, Gururaja regval = regval | (clkdiv << 6) | (DTO << 16); 6695934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 6705934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 6715934df2fSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 6725934df2fSAndy Shevchenko 6735934df2fSAndy Shevchenko /* Wait till the ICS bit is set */ 6745934df2fSAndy Shevchenko timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 6755934df2fSAndy Shevchenko while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 6765934df2fSAndy Shevchenko && time_before(jiffies, timeout)) 6775934df2fSAndy Shevchenko cpu_relax(); 6785934df2fSAndy Shevchenko 679cd587096SHebbar, Gururaja /* 680cd587096SHebbar, Gururaja * Enable High-Speed Support 681cd587096SHebbar, Gururaja * Pre-Requisites 682cd587096SHebbar, Gururaja * - Controller should support High-Speed-Enable Bit 683cd587096SHebbar, Gururaja * - Controller should not be using DDR Mode 684cd587096SHebbar, Gururaja * - Controller should advertise that it supports High Speed 685cd587096SHebbar, Gururaja * in capabilities register 686cd587096SHebbar, Gururaja * - MMC/SD clock coming out of controller > 25MHz 687cd587096SHebbar, Gururaja */ 688326119c9SAndreas Fenkart if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) && 6895438ad95SSeungwon Jeon (ios->timing != MMC_TIMING_MMC_DDR52) && 690903101a8SUlf Hansson (ios->timing != MMC_TIMING_UHS_DDR50) && 691cd587096SHebbar, Gururaja ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 692cd587096SHebbar, Gururaja regval = OMAP_HSMMC_READ(host->base, HCTL); 693cd587096SHebbar, Gururaja if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 694cd587096SHebbar, Gururaja regval |= HSPE; 695cd587096SHebbar, Gururaja else 696cd587096SHebbar, Gururaja regval &= ~HSPE; 697cd587096SHebbar, Gururaja 698cd587096SHebbar, Gururaja OMAP_HSMMC_WRITE(host->base, HCTL, regval); 699cd587096SHebbar, Gururaja } 700cd587096SHebbar, Gururaja 7015934df2fSAndy Shevchenko omap_hsmmc_start_clock(host); 7025934df2fSAndy Shevchenko } 7035934df2fSAndy Shevchenko 7043796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 7053796fb8aSAndy Shevchenko { 7063796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 7073796fb8aSAndy Shevchenko u32 con; 7083796fb8aSAndy Shevchenko 7093796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 710903101a8SUlf Hansson if (ios->timing == MMC_TIMING_MMC_DDR52 || 711903101a8SUlf Hansson ios->timing == MMC_TIMING_UHS_DDR50) 71203b5d924SBalaji T K con |= DDR; /* configure in DDR mode */ 71303b5d924SBalaji T K else 71403b5d924SBalaji T K con &= ~DDR; 7153796fb8aSAndy Shevchenko switch (ios->bus_width) { 7163796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_8: 7173796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 7183796fb8aSAndy Shevchenko break; 7193796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_4: 7203796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 7213796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 7223796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 7233796fb8aSAndy Shevchenko break; 7243796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_1: 7253796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 7263796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 7273796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 7283796fb8aSAndy Shevchenko break; 7293796fb8aSAndy Shevchenko } 7303796fb8aSAndy Shevchenko } 7313796fb8aSAndy Shevchenko 7323796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 7333796fb8aSAndy Shevchenko { 7343796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 7353796fb8aSAndy Shevchenko u32 con; 7363796fb8aSAndy Shevchenko 7373796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 7383796fb8aSAndy Shevchenko if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 7393796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | OD); 7403796fb8aSAndy Shevchenko else 7413796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 7423796fb8aSAndy Shevchenko } 7433796fb8aSAndy Shevchenko 74411dd62a7SDenis Karpov #ifdef CONFIG_PM 74511dd62a7SDenis Karpov 74611dd62a7SDenis Karpov /* 74711dd62a7SDenis Karpov * Restore the MMC host context, if it was lost as result of a 74811dd62a7SDenis Karpov * power state change. 74911dd62a7SDenis Karpov */ 75070a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 75111dd62a7SDenis Karpov { 75211dd62a7SDenis Karpov struct mmc_ios *ios = &host->mmc->ios; 7533796fb8aSAndy Shevchenko u32 hctl, capa; 75411dd62a7SDenis Karpov unsigned long timeout; 75511dd62a7SDenis Karpov 7560a82e06eSTony Lindgren if (host->con == OMAP_HSMMC_READ(host->base, CON) && 7570a82e06eSTony Lindgren host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && 7580a82e06eSTony Lindgren host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && 7590a82e06eSTony Lindgren host->capa == OMAP_HSMMC_READ(host->base, CAPA)) 7600a82e06eSTony Lindgren return 0; 7610a82e06eSTony Lindgren 7620a82e06eSTony Lindgren host->context_loss++; 7630a82e06eSTony Lindgren 764c2200efbSBalaji T K if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 76511dd62a7SDenis Karpov if (host->power_mode != MMC_POWER_OFF && 76611dd62a7SDenis Karpov (1 << ios->vdd) <= MMC_VDD_23_24) 76711dd62a7SDenis Karpov hctl = SDVS18; 76811dd62a7SDenis Karpov else 76911dd62a7SDenis Karpov hctl = SDVS30; 77011dd62a7SDenis Karpov capa = VS30 | VS18; 77111dd62a7SDenis Karpov } else { 77211dd62a7SDenis Karpov hctl = SDVS18; 77311dd62a7SDenis Karpov capa = VS18; 77411dd62a7SDenis Karpov } 77511dd62a7SDenis Karpov 7765a52b08bSBalaji T K if (host->mmc->caps & MMC_CAP_SDIO_IRQ) 7775a52b08bSBalaji T K hctl |= IWE; 7785a52b08bSBalaji T K 77911dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 78011dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | hctl); 78111dd62a7SDenis Karpov 78211dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CAPA, 78311dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA) | capa); 78411dd62a7SDenis Karpov 78511dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 78611dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 78711dd62a7SDenis Karpov 78811dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 78911dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 79011dd62a7SDenis Karpov && time_before(jiffies, timeout)) 79111dd62a7SDenis Karpov ; 79211dd62a7SDenis Karpov 7932cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 7942cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 7952cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 79611dd62a7SDenis Karpov 79711dd62a7SDenis Karpov /* Do not initialize card-specific things if the power is off */ 79811dd62a7SDenis Karpov if (host->power_mode == MMC_POWER_OFF) 79911dd62a7SDenis Karpov goto out; 80011dd62a7SDenis Karpov 8013796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 80211dd62a7SDenis Karpov 8035934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 80411dd62a7SDenis Karpov 8053796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 8063796fb8aSAndy Shevchenko 80711dd62a7SDenis Karpov out: 8080a82e06eSTony Lindgren dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", 8090a82e06eSTony Lindgren host->context_loss); 81011dd62a7SDenis Karpov return 0; 81111dd62a7SDenis Karpov } 81211dd62a7SDenis Karpov 81311dd62a7SDenis Karpov /* 81411dd62a7SDenis Karpov * Save the MMC host context (store the number of power state changes so far). 81511dd62a7SDenis Karpov */ 81670a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 81711dd62a7SDenis Karpov { 8180a82e06eSTony Lindgren host->con = OMAP_HSMMC_READ(host->base, CON); 8190a82e06eSTony Lindgren host->hctl = OMAP_HSMMC_READ(host->base, HCTL); 8200a82e06eSTony Lindgren host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); 8210a82e06eSTony Lindgren host->capa = OMAP_HSMMC_READ(host->base, CAPA); 82211dd62a7SDenis Karpov } 82311dd62a7SDenis Karpov 82411dd62a7SDenis Karpov #else 82511dd62a7SDenis Karpov 82670a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 82711dd62a7SDenis Karpov { 82811dd62a7SDenis Karpov return 0; 82911dd62a7SDenis Karpov } 83011dd62a7SDenis Karpov 83170a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 83211dd62a7SDenis Karpov { 83311dd62a7SDenis Karpov } 83411dd62a7SDenis Karpov 83511dd62a7SDenis Karpov #endif 83611dd62a7SDenis Karpov 837a45c6cb8SMadhusudhan Chikkature /* 838a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 839a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 840a45c6cb8SMadhusudhan Chikkature */ 84170a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host) 842a45c6cb8SMadhusudhan Chikkature { 843a45c6cb8SMadhusudhan Chikkature int reg = 0; 844a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 845a45c6cb8SMadhusudhan Chikkature 846b62f6228SAdrian Hunter if (host->protect_card) 847b62f6228SAdrian Hunter return; 848b62f6228SAdrian Hunter 849a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 850b417577dSAdrian Hunter 851b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 852a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 853a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 854a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 855a45c6cb8SMadhusudhan Chikkature 856a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 857a7e96879SVenkatraman S while ((reg != CC_EN) && time_before(jiffies, timeout)) 858a7e96879SVenkatraman S reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; 859a45c6cb8SMadhusudhan Chikkature 860a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 861a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 862c653a6d4SAdrian Hunter 863c653a6d4SAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 864c653a6d4SAdrian Hunter OMAP_HSMMC_READ(host->base, STAT); 865c653a6d4SAdrian Hunter 866a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 867a45c6cb8SMadhusudhan Chikkature } 868a45c6cb8SMadhusudhan Chikkature 869a45c6cb8SMadhusudhan Chikkature static inline 87070a3341aSDenis Karpov int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 871a45c6cb8SMadhusudhan Chikkature { 872a45c6cb8SMadhusudhan Chikkature int r = 1; 873a45c6cb8SMadhusudhan Chikkature 874b5cd43f0SAndreas Fenkart if (host->get_cover_state) 87580412ca8SAndreas Fenkart r = host->get_cover_state(host->dev); 876a45c6cb8SMadhusudhan Chikkature return r; 877a45c6cb8SMadhusudhan Chikkature } 878a45c6cb8SMadhusudhan Chikkature 879a45c6cb8SMadhusudhan Chikkature static ssize_t 88070a3341aSDenis Karpov omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 881a45c6cb8SMadhusudhan Chikkature char *buf) 882a45c6cb8SMadhusudhan Chikkature { 883a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 88470a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 885a45c6cb8SMadhusudhan Chikkature 88670a3341aSDenis Karpov return sprintf(buf, "%s\n", 88770a3341aSDenis Karpov omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 888a45c6cb8SMadhusudhan Chikkature } 889a45c6cb8SMadhusudhan Chikkature 89070a3341aSDenis Karpov static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 891a45c6cb8SMadhusudhan Chikkature 892a45c6cb8SMadhusudhan Chikkature static ssize_t 89370a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 894a45c6cb8SMadhusudhan Chikkature char *buf) 895a45c6cb8SMadhusudhan Chikkature { 896a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 89770a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 898a45c6cb8SMadhusudhan Chikkature 899326119c9SAndreas Fenkart return sprintf(buf, "%s\n", mmc_pdata(host)->name); 900a45c6cb8SMadhusudhan Chikkature } 901a45c6cb8SMadhusudhan Chikkature 90270a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 903a45c6cb8SMadhusudhan Chikkature 904a45c6cb8SMadhusudhan Chikkature /* 905a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 906a45c6cb8SMadhusudhan Chikkature */ 907a45c6cb8SMadhusudhan Chikkature static void 90870a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 909a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 910a45c6cb8SMadhusudhan Chikkature { 911a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 912a45c6cb8SMadhusudhan Chikkature 9138986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 914a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 915a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 916a45c6cb8SMadhusudhan Chikkature 91793caf8e6SAdrian Hunter omap_hsmmc_enable_irq(host, cmd); 918a45c6cb8SMadhusudhan Chikkature 9194a694dc9SAdrian Hunter host->response_busy = 0; 920a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 921a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 922a45c6cb8SMadhusudhan Chikkature resptype = 1; 9234a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 9244a694dc9SAdrian Hunter resptype = 3; 9254a694dc9SAdrian Hunter host->response_busy = 1; 9264a694dc9SAdrian Hunter } else 927a45c6cb8SMadhusudhan Chikkature resptype = 2; 928a45c6cb8SMadhusudhan Chikkature } 929a45c6cb8SMadhusudhan Chikkature 930a45c6cb8SMadhusudhan Chikkature /* 931a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 932a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 933a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 934a45c6cb8SMadhusudhan Chikkature */ 935a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 936a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 937a45c6cb8SMadhusudhan Chikkature 938a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 939a45c6cb8SMadhusudhan Chikkature 940a2e77152SBalaji T K if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) && 941a2e77152SBalaji T K host->mrq->sbc) { 942a2e77152SBalaji T K cmdreg |= ACEN_ACMD23; 943a2e77152SBalaji T K OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg); 944a2e77152SBalaji T K } 945a45c6cb8SMadhusudhan Chikkature if (data) { 946a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 947a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 948a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 949a45c6cb8SMadhusudhan Chikkature else 950a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 951a45c6cb8SMadhusudhan Chikkature } 952a45c6cb8SMadhusudhan Chikkature 953a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 954a7e96879SVenkatraman S cmdreg |= DMAE; 955a45c6cb8SMadhusudhan Chikkature 956b417577dSAdrian Hunter host->req_in_progress = 1; 9574dffd7a2SAdrian Hunter 958a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 959a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 960a45c6cb8SMadhusudhan Chikkature } 961a45c6cb8SMadhusudhan Chikkature 9620ccd76d4SJuha Yrjola static int 96370a3341aSDenis Karpov omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 9640ccd76d4SJuha Yrjola { 9650ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) 9660ccd76d4SJuha Yrjola return DMA_TO_DEVICE; 9670ccd76d4SJuha Yrjola else 9680ccd76d4SJuha Yrjola return DMA_FROM_DEVICE; 9690ccd76d4SJuha Yrjola } 9700ccd76d4SJuha Yrjola 971c5c98927SRussell King static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 972c5c98927SRussell King struct mmc_data *data) 973c5c98927SRussell King { 974c5c98927SRussell King return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 975c5c98927SRussell King } 976c5c98927SRussell King 977b417577dSAdrian Hunter static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 978b417577dSAdrian Hunter { 979b417577dSAdrian Hunter int dma_ch; 98031463b14SVenkatraman S unsigned long flags; 981b417577dSAdrian Hunter 98231463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 983b417577dSAdrian Hunter host->req_in_progress = 0; 984b417577dSAdrian Hunter dma_ch = host->dma_ch; 98531463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 986b417577dSAdrian Hunter 987b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 988b417577dSAdrian Hunter /* Do not complete the request if DMA is still in progress */ 989b417577dSAdrian Hunter if (mrq->data && host->use_dma && dma_ch != -1) 990b417577dSAdrian Hunter return; 991b417577dSAdrian Hunter host->mrq = NULL; 992b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 993f57ba4caSNeilBrown pm_runtime_mark_last_busy(host->dev); 994f57ba4caSNeilBrown pm_runtime_put_autosuspend(host->dev); 995b417577dSAdrian Hunter } 996b417577dSAdrian Hunter 997a45c6cb8SMadhusudhan Chikkature /* 998a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 999a45c6cb8SMadhusudhan Chikkature */ 1000a45c6cb8SMadhusudhan Chikkature static void 100170a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 1002a45c6cb8SMadhusudhan Chikkature { 10034a694dc9SAdrian Hunter if (!data) { 10044a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 10054a694dc9SAdrian Hunter 100623050103SAdrian Hunter /* TC before CC from CMD6 - don't know why, but it happens */ 100723050103SAdrian Hunter if (host->cmd && host->cmd->opcode == 6 && 100823050103SAdrian Hunter host->response_busy) { 100923050103SAdrian Hunter host->response_busy = 0; 101023050103SAdrian Hunter return; 101123050103SAdrian Hunter } 101223050103SAdrian Hunter 1013b417577dSAdrian Hunter omap_hsmmc_request_done(host, mrq); 10144a694dc9SAdrian Hunter return; 10154a694dc9SAdrian Hunter } 10164a694dc9SAdrian Hunter 1017a45c6cb8SMadhusudhan Chikkature host->data = NULL; 1018a45c6cb8SMadhusudhan Chikkature 1019a45c6cb8SMadhusudhan Chikkature if (!data->error) 1020a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 1021a45c6cb8SMadhusudhan Chikkature else 1022a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 1023a45c6cb8SMadhusudhan Chikkature 1024bf129e1cSBalaji T K if (data->stop && (data->error || !host->mrq->sbc)) 1025fe852273SMing Lei omap_hsmmc_start_command(host, data->stop, NULL); 1026bf129e1cSBalaji T K else 1027bf129e1cSBalaji T K omap_hsmmc_request_done(host, data->mrq); 1028a45c6cb8SMadhusudhan Chikkature } 1029a45c6cb8SMadhusudhan Chikkature 1030a45c6cb8SMadhusudhan Chikkature /* 1031a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 1032a45c6cb8SMadhusudhan Chikkature */ 1033a45c6cb8SMadhusudhan Chikkature static void 103470a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 1035a45c6cb8SMadhusudhan Chikkature { 1036bf129e1cSBalaji T K if (host->mrq->sbc && (host->cmd == host->mrq->sbc) && 1037a2e77152SBalaji T K !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) { 10382177fa94SBalaji T K host->cmd = NULL; 1039bf129e1cSBalaji T K omap_hsmmc_start_dma_transfer(host); 1040bf129e1cSBalaji T K omap_hsmmc_start_command(host, host->mrq->cmd, 1041bf129e1cSBalaji T K host->mrq->data); 1042bf129e1cSBalaji T K return; 1043bf129e1cSBalaji T K } 1044bf129e1cSBalaji T K 10452177fa94SBalaji T K host->cmd = NULL; 10462177fa94SBalaji T K 1047a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 1048a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 1049a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 1050a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 1051a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 1052a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 1053a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 1054a45c6cb8SMadhusudhan Chikkature } else { 1055a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 1056a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 1057a45c6cb8SMadhusudhan Chikkature } 1058a45c6cb8SMadhusudhan Chikkature } 1059b417577dSAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) 1060d4b2c375SBalaji T K omap_hsmmc_request_done(host, host->mrq); 1061a45c6cb8SMadhusudhan Chikkature } 1062a45c6cb8SMadhusudhan Chikkature 1063a45c6cb8SMadhusudhan Chikkature /* 1064a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 1065a45c6cb8SMadhusudhan Chikkature */ 106670a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 1067a45c6cb8SMadhusudhan Chikkature { 1068b417577dSAdrian Hunter int dma_ch; 106931463b14SVenkatraman S unsigned long flags; 1070b417577dSAdrian Hunter 107182788ff5SJarkko Lavinen host->data->error = errno; 1072a45c6cb8SMadhusudhan Chikkature 107331463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 1074b417577dSAdrian Hunter dma_ch = host->dma_ch; 1075b417577dSAdrian Hunter host->dma_ch = -1; 107631463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 1077b417577dSAdrian Hunter 1078b417577dSAdrian Hunter if (host->use_dma && dma_ch != -1) { 1079c5c98927SRussell King struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 1080c5c98927SRussell King 1081c5c98927SRussell King dmaengine_terminate_all(chan); 1082c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1083c5c98927SRussell King host->data->sg, host->data->sg_len, 108470a3341aSDenis Karpov omap_hsmmc_get_dma_dir(host, host->data)); 1085c5c98927SRussell King 1086053bf34fSPer Forlin host->data->host_cookie = 0; 1087a45c6cb8SMadhusudhan Chikkature } 1088a45c6cb8SMadhusudhan Chikkature host->data = NULL; 1089a45c6cb8SMadhusudhan Chikkature } 1090a45c6cb8SMadhusudhan Chikkature 1091a45c6cb8SMadhusudhan Chikkature /* 1092a45c6cb8SMadhusudhan Chikkature * Readable error output 1093a45c6cb8SMadhusudhan Chikkature */ 1094a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 1095699b958bSAdrian Hunter static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 1096a45c6cb8SMadhusudhan Chikkature { 1097a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 109870a3341aSDenis Karpov static const char *omap_hsmmc_status_bits[] = { 1099699b958bSAdrian Hunter "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 1100699b958bSAdrian Hunter "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 1101699b958bSAdrian Hunter "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 1102699b958bSAdrian Hunter "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 1103a45c6cb8SMadhusudhan Chikkature }; 1104a45c6cb8SMadhusudhan Chikkature char res[256]; 1105a45c6cb8SMadhusudhan Chikkature char *buf = res; 1106a45c6cb8SMadhusudhan Chikkature int len, i; 1107a45c6cb8SMadhusudhan Chikkature 1108a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 1109a45c6cb8SMadhusudhan Chikkature buf += len; 1110a45c6cb8SMadhusudhan Chikkature 111170a3341aSDenis Karpov for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 1112a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 111370a3341aSDenis Karpov len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 1114a45c6cb8SMadhusudhan Chikkature buf += len; 1115a45c6cb8SMadhusudhan Chikkature } 1116a45c6cb8SMadhusudhan Chikkature 11178986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 1118a45c6cb8SMadhusudhan Chikkature } 1119699b958bSAdrian Hunter #else 1120699b958bSAdrian Hunter static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 1121699b958bSAdrian Hunter u32 status) 1122699b958bSAdrian Hunter { 1123699b958bSAdrian Hunter } 1124a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 1125a45c6cb8SMadhusudhan Chikkature 11263ebf74b1SJean Pihet /* 11273ebf74b1SJean Pihet * MMC controller internal state machines reset 11283ebf74b1SJean Pihet * 11293ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 11303ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 11313ebf74b1SJean Pihet * Can be called from interrupt context 11323ebf74b1SJean Pihet */ 113370a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 11343ebf74b1SJean Pihet unsigned long bit) 11353ebf74b1SJean Pihet { 11363ebf74b1SJean Pihet unsigned long i = 0; 11371e881786SJianpeng Ma unsigned long limit = MMC_TIMEOUT_US; 11383ebf74b1SJean Pihet 11393ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 11403ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 11413ebf74b1SJean Pihet 114207ad64b6SMadhusudhan Chikkature /* 114307ad64b6SMadhusudhan Chikkature * OMAP4 ES2 and greater has an updated reset logic. 114407ad64b6SMadhusudhan Chikkature * Monitor a 0->1 transition first 114507ad64b6SMadhusudhan Chikkature */ 1146326119c9SAndreas Fenkart if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) { 1147b432b4b3Skishore kadiyala while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 114807ad64b6SMadhusudhan Chikkature && (i++ < limit)) 11491e881786SJianpeng Ma udelay(1); 115007ad64b6SMadhusudhan Chikkature } 115107ad64b6SMadhusudhan Chikkature i = 0; 115207ad64b6SMadhusudhan Chikkature 11533ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 11543ebf74b1SJean Pihet (i++ < limit)) 11551e881786SJianpeng Ma udelay(1); 11563ebf74b1SJean Pihet 11573ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 11583ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 11593ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 11603ebf74b1SJean Pihet __func__); 11613ebf74b1SJean Pihet } 1162a45c6cb8SMadhusudhan Chikkature 116325e1897bSBalaji T K static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, 116425e1897bSBalaji T K int err, int end_cmd) 1165ae4bf788SVenkatraman S { 116625e1897bSBalaji T K if (end_cmd) { 116794d4f272SBalaji T K omap_hsmmc_reset_controller_fsm(host, SRC); 116825e1897bSBalaji T K if (host->cmd) 1169ae4bf788SVenkatraman S host->cmd->error = err; 117025e1897bSBalaji T K } 1171ae4bf788SVenkatraman S 1172ae4bf788SVenkatraman S if (host->data) { 1173ae4bf788SVenkatraman S omap_hsmmc_reset_controller_fsm(host, SRD); 1174ae4bf788SVenkatraman S omap_hsmmc_dma_cleanup(host, err); 1175dc7745bdSBalaji T K } else if (host->mrq && host->mrq->cmd) 1176dc7745bdSBalaji T K host->mrq->cmd->error = err; 1177ae4bf788SVenkatraman S } 1178ae4bf788SVenkatraman S 1179b417577dSAdrian Hunter static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1180a45c6cb8SMadhusudhan Chikkature { 1181a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 1182b417577dSAdrian Hunter int end_cmd = 0, end_trans = 0; 1183a2e77152SBalaji T K int error = 0; 1184a45c6cb8SMadhusudhan Chikkature 1185a45c6cb8SMadhusudhan Chikkature data = host->data; 11868986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1187a45c6cb8SMadhusudhan Chikkature 1188a7e96879SVenkatraman S if (status & ERR_EN) { 1189699b958bSAdrian Hunter omap_hsmmc_dbg_report_irq(host, status); 11904a694dc9SAdrian Hunter 1191a7e96879SVenkatraman S if (status & (CTO_EN | CCRC_EN)) 1192a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1193408806f7SKishon Vijay Abraham I if (host->data || host->response_busy) { 1194408806f7SKishon Vijay Abraham I end_trans = !end_cmd; 1195408806f7SKishon Vijay Abraham I host->response_busy = 0; 1196408806f7SKishon Vijay Abraham I } 1197a7e96879SVenkatraman S if (status & (CTO_EN | DTO_EN)) 119825e1897bSBalaji T K hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); 11995027cd1eSVignesh R else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN | 12005027cd1eSVignesh R BADA_EN)) 120125e1897bSBalaji T K hsmmc_command_incomplete(host, -EILSEQ, end_cmd); 120225e1897bSBalaji T K 1203a2e77152SBalaji T K if (status & ACE_EN) { 1204a2e77152SBalaji T K u32 ac12; 1205a2e77152SBalaji T K ac12 = OMAP_HSMMC_READ(host->base, AC12); 1206a2e77152SBalaji T K if (!(ac12 & ACNE) && host->mrq->sbc) { 1207a2e77152SBalaji T K end_cmd = 1; 1208a2e77152SBalaji T K if (ac12 & ACTO) 1209a2e77152SBalaji T K error = -ETIMEDOUT; 1210a2e77152SBalaji T K else if (ac12 & (ACCE | ACEB | ACIE)) 1211a2e77152SBalaji T K error = -EILSEQ; 1212a2e77152SBalaji T K host->mrq->sbc->error = error; 1213a2e77152SBalaji T K hsmmc_command_incomplete(host, error, end_cmd); 1214a2e77152SBalaji T K } 1215a2e77152SBalaji T K dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12); 1216a2e77152SBalaji T K } 1217a45c6cb8SMadhusudhan Chikkature } 1218a45c6cb8SMadhusudhan Chikkature 12197472bab2SFrancesco Lavra OMAP_HSMMC_WRITE(host->base, STAT, status); 1220a7e96879SVenkatraman S if (end_cmd || ((status & CC_EN) && host->cmd)) 122170a3341aSDenis Karpov omap_hsmmc_cmd_done(host, host->cmd); 1222a7e96879SVenkatraman S if ((end_trans || (status & TC_EN)) && host->mrq) 122370a3341aSDenis Karpov omap_hsmmc_xfer_done(host, data); 1224b417577dSAdrian Hunter } 1225a45c6cb8SMadhusudhan Chikkature 1226b417577dSAdrian Hunter /* 1227b417577dSAdrian Hunter * MMC controller IRQ handler 1228b417577dSAdrian Hunter */ 1229b417577dSAdrian Hunter static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1230b417577dSAdrian Hunter { 1231b417577dSAdrian Hunter struct omap_hsmmc_host *host = dev_id; 1232b417577dSAdrian Hunter int status; 1233b417577dSAdrian Hunter 1234b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 12352cd3a2a5SAndreas Fenkart while (status & (INT_EN_MASK | CIRQ_EN)) { 12362cd3a2a5SAndreas Fenkart if (host->req_in_progress) 1237b417577dSAdrian Hunter omap_hsmmc_do_irq(host, status); 12381f6b9fa4SVenkatraman S 12392cd3a2a5SAndreas Fenkart if (status & CIRQ_EN) 12402cd3a2a5SAndreas Fenkart mmc_signal_sdio_irq(host->mmc); 12412cd3a2a5SAndreas Fenkart 1242b417577dSAdrian Hunter /* Flush posted write */ 1243b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 12441f6b9fa4SVenkatraman S } 12454dffd7a2SAdrian Hunter 1246a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1247a45c6cb8SMadhusudhan Chikkature } 1248a45c6cb8SMadhusudhan Chikkature 124970a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host) 1250e13bb300SAdrian Hunter { 1251e13bb300SAdrian Hunter unsigned long i; 1252e13bb300SAdrian Hunter 1253e13bb300SAdrian Hunter OMAP_HSMMC_WRITE(host->base, HCTL, 1254e13bb300SAdrian Hunter OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1255e13bb300SAdrian Hunter for (i = 0; i < loops_per_jiffy; i++) { 1256e13bb300SAdrian Hunter if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1257e13bb300SAdrian Hunter break; 1258e13bb300SAdrian Hunter cpu_relax(); 1259e13bb300SAdrian Hunter } 1260e13bb300SAdrian Hunter } 1261e13bb300SAdrian Hunter 1262a45c6cb8SMadhusudhan Chikkature /* 1263eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 1264eb250826SDavid Brownell * 1265eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1266eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1267eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 1268a45c6cb8SMadhusudhan Chikkature */ 126970a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1270a45c6cb8SMadhusudhan Chikkature { 1271a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 1272a45c6cb8SMadhusudhan Chikkature int ret; 1273a45c6cb8SMadhusudhan Chikkature 1274a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 1275fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 1276cd03d9a8SRajendra Nayak if (host->dbclk) 127794c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 1278a45c6cb8SMadhusudhan Chikkature 1279a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 1280f7f0f035SAndreas Fenkart ret = omap_hsmmc_set_power(host->dev, 0, 0); 1281a45c6cb8SMadhusudhan Chikkature 1282a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 12832bec0893SAdrian Hunter if (!ret) 1284f7f0f035SAndreas Fenkart ret = omap_hsmmc_set_power(host->dev, 1, vdd); 1285fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1286cd03d9a8SRajendra Nayak if (host->dbclk) 128794c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 12882bec0893SAdrian Hunter 1289a45c6cb8SMadhusudhan Chikkature if (ret != 0) 1290a45c6cb8SMadhusudhan Chikkature goto err; 1291a45c6cb8SMadhusudhan Chikkature 1292a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1293a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1294a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1295eb250826SDavid Brownell 1296a45c6cb8SMadhusudhan Chikkature /* 1297a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 1298a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 129970a3341aSDenis Karpov * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1300a45c6cb8SMadhusudhan Chikkature * 1301eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 1302eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1303eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 1304eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1305eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 1306eb250826SDavid Brownell * 1307eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 1308eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1309eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1310a45c6cb8SMadhusudhan Chikkature */ 1311eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 1312a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 1313eb250826SDavid Brownell else 1314eb250826SDavid Brownell reg_val |= SDVS30; 1315a45c6cb8SMadhusudhan Chikkature 1316a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1317e13bb300SAdrian Hunter set_sd_bus_power(host); 1318a45c6cb8SMadhusudhan Chikkature 1319a45c6cb8SMadhusudhan Chikkature return 0; 1320a45c6cb8SMadhusudhan Chikkature err: 1321b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1322a45c6cb8SMadhusudhan Chikkature return ret; 1323a45c6cb8SMadhusudhan Chikkature } 1324a45c6cb8SMadhusudhan Chikkature 1325b62f6228SAdrian Hunter /* Protect the card while the cover is open */ 1326b62f6228SAdrian Hunter static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1327b62f6228SAdrian Hunter { 1328b5cd43f0SAndreas Fenkart if (!host->get_cover_state) 1329b62f6228SAdrian Hunter return; 1330b62f6228SAdrian Hunter 1331b62f6228SAdrian Hunter host->reqs_blocked = 0; 133280412ca8SAndreas Fenkart if (host->get_cover_state(host->dev)) { 1333b62f6228SAdrian Hunter if (host->protect_card) { 13342cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is closed, " 1335b62f6228SAdrian Hunter "card is now accessible\n", 1336b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1337b62f6228SAdrian Hunter host->protect_card = 0; 1338b62f6228SAdrian Hunter } 1339b62f6228SAdrian Hunter } else { 1340b62f6228SAdrian Hunter if (!host->protect_card) { 13412cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is open, " 1342b62f6228SAdrian Hunter "card is now inaccessible\n", 1343b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1344b62f6228SAdrian Hunter host->protect_card = 1; 1345b62f6228SAdrian Hunter } 1346b62f6228SAdrian Hunter } 1347b62f6228SAdrian Hunter } 1348b62f6228SAdrian Hunter 1349a45c6cb8SMadhusudhan Chikkature /* 1350cde592cbSAndreas Fenkart * irq handler when (cell-phone) cover is mounted/removed 1351cde592cbSAndreas Fenkart */ 1352cde592cbSAndreas Fenkart static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id) 1353cde592cbSAndreas Fenkart { 1354cde592cbSAndreas Fenkart struct omap_hsmmc_host *host = dev_id; 1355cde592cbSAndreas Fenkart 1356cde592cbSAndreas Fenkart sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1357cde592cbSAndreas Fenkart 1358cde592cbSAndreas Fenkart omap_hsmmc_protect_card(host); 1359cde592cbSAndreas Fenkart mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1360cde592cbSAndreas Fenkart return IRQ_HANDLED; 1361cde592cbSAndreas Fenkart } 1362cde592cbSAndreas Fenkart 1363c5c98927SRussell King static void omap_hsmmc_dma_callback(void *param) 13640ccd76d4SJuha Yrjola { 1365c5c98927SRussell King struct omap_hsmmc_host *host = param; 1366c5c98927SRussell King struct dma_chan *chan; 1367770d7432SAdrian Hunter struct mmc_data *data; 1368c5c98927SRussell King int req_in_progress; 1369a45c6cb8SMadhusudhan Chikkature 1370c5c98927SRussell King spin_lock_irq(&host->irq_lock); 1371b417577dSAdrian Hunter if (host->dma_ch < 0) { 1372c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1373a45c6cb8SMadhusudhan Chikkature return; 1374b417577dSAdrian Hunter } 1375a45c6cb8SMadhusudhan Chikkature 1376770d7432SAdrian Hunter data = host->mrq->data; 1377c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 13789782aff8SPer Forlin if (!data->host_cookie) 1379c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1380c5c98927SRussell King data->sg, data->sg_len, 1381b417577dSAdrian Hunter omap_hsmmc_get_dma_dir(host, data)); 1382b417577dSAdrian Hunter 1383b417577dSAdrian Hunter req_in_progress = host->req_in_progress; 1384a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1385c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1386b417577dSAdrian Hunter 1387b417577dSAdrian Hunter /* If DMA has finished after TC, complete the request */ 1388b417577dSAdrian Hunter if (!req_in_progress) { 1389b417577dSAdrian Hunter struct mmc_request *mrq = host->mrq; 1390b417577dSAdrian Hunter 1391b417577dSAdrian Hunter host->mrq = NULL; 1392b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 1393f57ba4caSNeilBrown pm_runtime_mark_last_busy(host->dev); 1394f57ba4caSNeilBrown pm_runtime_put_autosuspend(host->dev); 1395b417577dSAdrian Hunter } 1396a45c6cb8SMadhusudhan Chikkature } 1397a45c6cb8SMadhusudhan Chikkature 13989782aff8SPer Forlin static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 13999782aff8SPer Forlin struct mmc_data *data, 1400c5c98927SRussell King struct omap_hsmmc_next *next, 140126b88520SRussell King struct dma_chan *chan) 14029782aff8SPer Forlin { 14039782aff8SPer Forlin int dma_len; 14049782aff8SPer Forlin 14059782aff8SPer Forlin if (!next && data->host_cookie && 14069782aff8SPer Forlin data->host_cookie != host->next_data.cookie) { 14072cecdf00SRajendra Nayak dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 14089782aff8SPer Forlin " host->next_data.cookie %d\n", 14099782aff8SPer Forlin __func__, data->host_cookie, host->next_data.cookie); 14109782aff8SPer Forlin data->host_cookie = 0; 14119782aff8SPer Forlin } 14129782aff8SPer Forlin 14139782aff8SPer Forlin /* Check if next job is already prepared */ 1414b38313d6SDan Carpenter if (next || data->host_cookie != host->next_data.cookie) { 141526b88520SRussell King dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 14169782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 14179782aff8SPer Forlin 14189782aff8SPer Forlin } else { 14199782aff8SPer Forlin dma_len = host->next_data.dma_len; 14209782aff8SPer Forlin host->next_data.dma_len = 0; 14219782aff8SPer Forlin } 14229782aff8SPer Forlin 14239782aff8SPer Forlin 14249782aff8SPer Forlin if (dma_len == 0) 14259782aff8SPer Forlin return -EINVAL; 14269782aff8SPer Forlin 14279782aff8SPer Forlin if (next) { 14289782aff8SPer Forlin next->dma_len = dma_len; 14299782aff8SPer Forlin data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 14309782aff8SPer Forlin } else 14319782aff8SPer Forlin host->dma_len = dma_len; 14329782aff8SPer Forlin 14339782aff8SPer Forlin return 0; 14349782aff8SPer Forlin } 14359782aff8SPer Forlin 1436a45c6cb8SMadhusudhan Chikkature /* 1437a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 1438a45c6cb8SMadhusudhan Chikkature */ 14399d025334SBalaji T K static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host, 144070a3341aSDenis Karpov struct mmc_request *req) 1441a45c6cb8SMadhusudhan Chikkature { 144226b88520SRussell King struct dma_slave_config cfg; 144326b88520SRussell King struct dma_async_tx_descriptor *tx; 144426b88520SRussell King int ret = 0, i; 1445a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 1446c5c98927SRussell King struct dma_chan *chan; 1447a45c6cb8SMadhusudhan Chikkature 14480ccd76d4SJuha Yrjola /* Sanity check: all the SG entries must be aligned by block size. */ 1449a3f406f8SJarkko Lavinen for (i = 0; i < data->sg_len; i++) { 14500ccd76d4SJuha Yrjola struct scatterlist *sgl; 14510ccd76d4SJuha Yrjola 14520ccd76d4SJuha Yrjola sgl = data->sg + i; 14530ccd76d4SJuha Yrjola if (sgl->length % data->blksz) 14540ccd76d4SJuha Yrjola return -EINVAL; 14550ccd76d4SJuha Yrjola } 14560ccd76d4SJuha Yrjola if ((data->blksz % 4) != 0) 14570ccd76d4SJuha Yrjola /* REVISIT: The MMC buffer increments only when MSB is written. 14580ccd76d4SJuha Yrjola * Return error for blksz which is non multiple of four. 14590ccd76d4SJuha Yrjola */ 14600ccd76d4SJuha Yrjola return -EINVAL; 14610ccd76d4SJuha Yrjola 1462b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1463a45c6cb8SMadhusudhan Chikkature 1464c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 1465c5c98927SRussell King 1466c5c98927SRussell King cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA; 1467c5c98927SRussell King cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA; 1468c5c98927SRussell King cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1469c5c98927SRussell King cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1470c5c98927SRussell King cfg.src_maxburst = data->blksz / 4; 1471c5c98927SRussell King cfg.dst_maxburst = data->blksz / 4; 1472c5c98927SRussell King 1473c5c98927SRussell King ret = dmaengine_slave_config(chan, &cfg); 14749782aff8SPer Forlin if (ret) 14759782aff8SPer Forlin return ret; 1476a45c6cb8SMadhusudhan Chikkature 147726b88520SRussell King ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1478c5c98927SRussell King if (ret) 1479c5c98927SRussell King return ret; 1480a45c6cb8SMadhusudhan Chikkature 1481c5c98927SRussell King tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1482c5c98927SRussell King data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1483c5c98927SRussell King DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1484c5c98927SRussell King if (!tx) { 1485c5c98927SRussell King dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1486c5c98927SRussell King /* FIXME: cleanup */ 1487c5c98927SRussell King return -1; 1488c5c98927SRussell King } 1489c5c98927SRussell King 1490c5c98927SRussell King tx->callback = omap_hsmmc_dma_callback; 1491c5c98927SRussell King tx->callback_param = host; 1492c5c98927SRussell King 1493c5c98927SRussell King /* Does not fail */ 1494c5c98927SRussell King dmaengine_submit(tx); 1495c5c98927SRussell King 149626b88520SRussell King host->dma_ch = 1; 1497c5c98927SRussell King 1498a45c6cb8SMadhusudhan Chikkature return 0; 1499a45c6cb8SMadhusudhan Chikkature } 1500a45c6cb8SMadhusudhan Chikkature 150170a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host, 1502e2bf08d6SAdrian Hunter unsigned int timeout_ns, 1503e2bf08d6SAdrian Hunter unsigned int timeout_clks) 1504a45c6cb8SMadhusudhan Chikkature { 1505a45c6cb8SMadhusudhan Chikkature unsigned int timeout, cycle_ns; 1506a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 1507a45c6cb8SMadhusudhan Chikkature 1508a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1509a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1510a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 1511a45c6cb8SMadhusudhan Chikkature clkd = 1; 1512a45c6cb8SMadhusudhan Chikkature 15136e3076c2SBalaji T K cycle_ns = 1000000000 / (host->clk_rate / clkd); 1514e2bf08d6SAdrian Hunter timeout = timeout_ns / cycle_ns; 1515e2bf08d6SAdrian Hunter timeout += timeout_clks; 1516a45c6cb8SMadhusudhan Chikkature if (timeout) { 1517a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 1518a45c6cb8SMadhusudhan Chikkature dto += 1; 1519a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1520a45c6cb8SMadhusudhan Chikkature } 1521a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 1522a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1523a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 1524a45c6cb8SMadhusudhan Chikkature dto += 1; 1525a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 1526a45c6cb8SMadhusudhan Chikkature dto -= 13; 1527a45c6cb8SMadhusudhan Chikkature else 1528a45c6cb8SMadhusudhan Chikkature dto = 0; 1529a45c6cb8SMadhusudhan Chikkature if (dto > 14) 1530a45c6cb8SMadhusudhan Chikkature dto = 14; 1531a45c6cb8SMadhusudhan Chikkature } 1532a45c6cb8SMadhusudhan Chikkature 1533a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 1534a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 1535a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1536a45c6cb8SMadhusudhan Chikkature } 1537a45c6cb8SMadhusudhan Chikkature 15389d025334SBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host) 15399d025334SBalaji T K { 15409d025334SBalaji T K struct mmc_request *req = host->mrq; 15419d025334SBalaji T K struct dma_chan *chan; 15429d025334SBalaji T K 15439d025334SBalaji T K if (!req->data) 15449d025334SBalaji T K return; 15459d025334SBalaji T K OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 15469d025334SBalaji T K | (req->data->blocks << 16)); 15479d025334SBalaji T K set_data_timeout(host, req->data->timeout_ns, 15489d025334SBalaji T K req->data->timeout_clks); 15499d025334SBalaji T K chan = omap_hsmmc_get_dma_chan(host, req->data); 15509d025334SBalaji T K dma_async_issue_pending(chan); 15519d025334SBalaji T K } 15529d025334SBalaji T K 1553a45c6cb8SMadhusudhan Chikkature /* 1554a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 1555a45c6cb8SMadhusudhan Chikkature */ 1556a45c6cb8SMadhusudhan Chikkature static int 155770a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1558a45c6cb8SMadhusudhan Chikkature { 1559a45c6cb8SMadhusudhan Chikkature int ret; 1560a45c6cb8SMadhusudhan Chikkature host->data = req->data; 1561a45c6cb8SMadhusudhan Chikkature 1562a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 1563a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 1564e2bf08d6SAdrian Hunter /* 1565e2bf08d6SAdrian Hunter * Set an arbitrary 100ms data timeout for commands with 1566e2bf08d6SAdrian Hunter * busy signal. 1567e2bf08d6SAdrian Hunter */ 1568e2bf08d6SAdrian Hunter if (req->cmd->flags & MMC_RSP_BUSY) 1569e2bf08d6SAdrian Hunter set_data_timeout(host, 100000000U, 0); 1570a45c6cb8SMadhusudhan Chikkature return 0; 1571a45c6cb8SMadhusudhan Chikkature } 1572a45c6cb8SMadhusudhan Chikkature 1573a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 15749d025334SBalaji T K ret = omap_hsmmc_setup_dma_transfer(host, req); 1575a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 1576b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); 1577a45c6cb8SMadhusudhan Chikkature return ret; 1578a45c6cb8SMadhusudhan Chikkature } 1579a45c6cb8SMadhusudhan Chikkature } 1580a45c6cb8SMadhusudhan Chikkature return 0; 1581a45c6cb8SMadhusudhan Chikkature } 1582a45c6cb8SMadhusudhan Chikkature 15839782aff8SPer Forlin static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 15849782aff8SPer Forlin int err) 15859782aff8SPer Forlin { 15869782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15879782aff8SPer Forlin struct mmc_data *data = mrq->data; 15889782aff8SPer Forlin 158926b88520SRussell King if (host->use_dma && data->host_cookie) { 1590c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1591c5c98927SRussell King 159226b88520SRussell King dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 15939782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 15949782aff8SPer Forlin data->host_cookie = 0; 15959782aff8SPer Forlin } 15969782aff8SPer Forlin } 15979782aff8SPer Forlin 15989782aff8SPer Forlin static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 15999782aff8SPer Forlin bool is_first_req) 16009782aff8SPer Forlin { 16019782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 16029782aff8SPer Forlin 16039782aff8SPer Forlin if (mrq->data->host_cookie) { 16049782aff8SPer Forlin mrq->data->host_cookie = 0; 16059782aff8SPer Forlin return ; 16069782aff8SPer Forlin } 16079782aff8SPer Forlin 1608c5c98927SRussell King if (host->use_dma) { 1609c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1610c5c98927SRussell King 16119782aff8SPer Forlin if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 161226b88520SRussell King &host->next_data, c)) 16139782aff8SPer Forlin mrq->data->host_cookie = 0; 16149782aff8SPer Forlin } 1615c5c98927SRussell King } 16169782aff8SPer Forlin 1617a45c6cb8SMadhusudhan Chikkature /* 1618a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 1619a45c6cb8SMadhusudhan Chikkature */ 162070a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1621a45c6cb8SMadhusudhan Chikkature { 162270a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1623a3f406f8SJarkko Lavinen int err; 1624a45c6cb8SMadhusudhan Chikkature 1625b417577dSAdrian Hunter BUG_ON(host->req_in_progress); 1626b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1627f57ba4caSNeilBrown pm_runtime_get_sync(host->dev); 1628b62f6228SAdrian Hunter if (host->protect_card) { 1629b62f6228SAdrian Hunter if (host->reqs_blocked < 3) { 1630b62f6228SAdrian Hunter /* 1631b62f6228SAdrian Hunter * Ensure the controller is left in a consistent 1632b62f6228SAdrian Hunter * state by resetting the command and data state 1633b62f6228SAdrian Hunter * machines. 1634b62f6228SAdrian Hunter */ 1635b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRD); 1636b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRC); 1637b62f6228SAdrian Hunter host->reqs_blocked += 1; 1638b62f6228SAdrian Hunter } 1639b62f6228SAdrian Hunter req->cmd->error = -EBADF; 1640b62f6228SAdrian Hunter if (req->data) 1641b62f6228SAdrian Hunter req->data->error = -EBADF; 1642b417577dSAdrian Hunter req->cmd->retries = 0; 1643b62f6228SAdrian Hunter mmc_request_done(mmc, req); 1644f57ba4caSNeilBrown pm_runtime_mark_last_busy(host->dev); 1645f57ba4caSNeilBrown pm_runtime_put_autosuspend(host->dev); 1646b62f6228SAdrian Hunter return; 1647b62f6228SAdrian Hunter } else if (host->reqs_blocked) 1648b62f6228SAdrian Hunter host->reqs_blocked = 0; 1649a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 1650a45c6cb8SMadhusudhan Chikkature host->mrq = req; 16516e3076c2SBalaji T K host->clk_rate = clk_get_rate(host->fclk); 165270a3341aSDenis Karpov err = omap_hsmmc_prepare_data(host, req); 1653a3f406f8SJarkko Lavinen if (err) { 1654a3f406f8SJarkko Lavinen req->cmd->error = err; 1655a3f406f8SJarkko Lavinen if (req->data) 1656a3f406f8SJarkko Lavinen req->data->error = err; 1657a3f406f8SJarkko Lavinen host->mrq = NULL; 1658a3f406f8SJarkko Lavinen mmc_request_done(mmc, req); 1659f57ba4caSNeilBrown pm_runtime_mark_last_busy(host->dev); 1660f57ba4caSNeilBrown pm_runtime_put_autosuspend(host->dev); 1661a3f406f8SJarkko Lavinen return; 1662a3f406f8SJarkko Lavinen } 1663a2e77152SBalaji T K if (req->sbc && !(host->flags & AUTO_CMD23)) { 1664bf129e1cSBalaji T K omap_hsmmc_start_command(host, req->sbc, NULL); 1665bf129e1cSBalaji T K return; 1666bf129e1cSBalaji T K } 1667a3f406f8SJarkko Lavinen 16689d025334SBalaji T K omap_hsmmc_start_dma_transfer(host); 166970a3341aSDenis Karpov omap_hsmmc_start_command(host, req->cmd, req->data); 1670a45c6cb8SMadhusudhan Chikkature } 1671a45c6cb8SMadhusudhan Chikkature 1672a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 167370a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1674a45c6cb8SMadhusudhan Chikkature { 167570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1676a3621465SAdrian Hunter int do_send_init_stream = 0; 1677a45c6cb8SMadhusudhan Chikkature 1678fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 16795e2ea617SAdrian Hunter 1680a3621465SAdrian Hunter if (ios->power_mode != host->power_mode) { 1681a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 1682a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 1683f7f0f035SAndreas Fenkart omap_hsmmc_set_power(host->dev, 0, 0); 1684a45c6cb8SMadhusudhan Chikkature break; 1685a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 1686f7f0f035SAndreas Fenkart omap_hsmmc_set_power(host->dev, 1, ios->vdd); 1687a45c6cb8SMadhusudhan Chikkature break; 1688a3621465SAdrian Hunter case MMC_POWER_ON: 1689a3621465SAdrian Hunter do_send_init_stream = 1; 1690a3621465SAdrian Hunter break; 1691a3621465SAdrian Hunter } 1692a3621465SAdrian Hunter host->power_mode = ios->power_mode; 1693a45c6cb8SMadhusudhan Chikkature } 1694a45c6cb8SMadhusudhan Chikkature 1695dd498effSDenis Karpov /* FIXME: set registers based only on changes to ios */ 1696dd498effSDenis Karpov 16973796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 1698a45c6cb8SMadhusudhan Chikkature 16994621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1700eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 1701eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 1702eb250826SDavid Brownell */ 1703a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 17042cf171cbSBalaji T K (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1705a45c6cb8SMadhusudhan Chikkature /* 1706a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 1707a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 1708a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 1709a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 1710a45c6cb8SMadhusudhan Chikkature */ 171170a3341aSDenis Karpov if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1712a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1713a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 1714a45c6cb8SMadhusudhan Chikkature } 1715a45c6cb8SMadhusudhan Chikkature } 1716a45c6cb8SMadhusudhan Chikkature 17175934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 1718a45c6cb8SMadhusudhan Chikkature 1719a3621465SAdrian Hunter if (do_send_init_stream) 1720a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 1721a45c6cb8SMadhusudhan Chikkature 17223796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 17235e2ea617SAdrian Hunter 1724fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1725a45c6cb8SMadhusudhan Chikkature } 1726a45c6cb8SMadhusudhan Chikkature 1727a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1728a45c6cb8SMadhusudhan Chikkature { 172970a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1730a45c6cb8SMadhusudhan Chikkature 1731b5cd43f0SAndreas Fenkart if (!host->card_detect) 1732a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 173380412ca8SAndreas Fenkart return host->card_detect(host->dev); 1734a45c6cb8SMadhusudhan Chikkature } 1735a45c6cb8SMadhusudhan Chikkature 17364816858cSGrazvydas Ignotas static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 17374816858cSGrazvydas Ignotas { 17384816858cSGrazvydas Ignotas struct omap_hsmmc_host *host = mmc_priv(mmc); 17394816858cSGrazvydas Ignotas 1740326119c9SAndreas Fenkart if (mmc_pdata(host)->init_card) 1741326119c9SAndreas Fenkart mmc_pdata(host)->init_card(card); 17424816858cSGrazvydas Ignotas } 17434816858cSGrazvydas Ignotas 17442cd3a2a5SAndreas Fenkart static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 17452cd3a2a5SAndreas Fenkart { 17462cd3a2a5SAndreas Fenkart struct omap_hsmmc_host *host = mmc_priv(mmc); 17475a52b08bSBalaji T K u32 irq_mask, con; 17482cd3a2a5SAndreas Fenkart unsigned long flags; 17492cd3a2a5SAndreas Fenkart 17502cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 17512cd3a2a5SAndreas Fenkart 17525a52b08bSBalaji T K con = OMAP_HSMMC_READ(host->base, CON); 17532cd3a2a5SAndreas Fenkart irq_mask = OMAP_HSMMC_READ(host->base, ISE); 17542cd3a2a5SAndreas Fenkart if (enable) { 17552cd3a2a5SAndreas Fenkart host->flags |= HSMMC_SDIO_IRQ_ENABLED; 17562cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 17575a52b08bSBalaji T K con |= CTPL | CLKEXTFREE; 17582cd3a2a5SAndreas Fenkart } else { 17592cd3a2a5SAndreas Fenkart host->flags &= ~HSMMC_SDIO_IRQ_ENABLED; 17602cd3a2a5SAndreas Fenkart irq_mask &= ~CIRQ_EN; 17615a52b08bSBalaji T K con &= ~(CTPL | CLKEXTFREE); 17622cd3a2a5SAndreas Fenkart } 17635a52b08bSBalaji T K OMAP_HSMMC_WRITE(host->base, CON, con); 17642cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 17652cd3a2a5SAndreas Fenkart 17662cd3a2a5SAndreas Fenkart /* 17672cd3a2a5SAndreas Fenkart * if enable, piggy back detection on current request 17682cd3a2a5SAndreas Fenkart * but always disable immediately 17692cd3a2a5SAndreas Fenkart */ 17702cd3a2a5SAndreas Fenkart if (!host->req_in_progress || !enable) 17712cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 17722cd3a2a5SAndreas Fenkart 17732cd3a2a5SAndreas Fenkart /* flush posted write */ 17742cd3a2a5SAndreas Fenkart OMAP_HSMMC_READ(host->base, IE); 17752cd3a2a5SAndreas Fenkart 17762cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 17772cd3a2a5SAndreas Fenkart } 17782cd3a2a5SAndreas Fenkart 17792cd3a2a5SAndreas Fenkart static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host) 17802cd3a2a5SAndreas Fenkart { 17812cd3a2a5SAndreas Fenkart int ret; 17822cd3a2a5SAndreas Fenkart 17832cd3a2a5SAndreas Fenkart /* 17842cd3a2a5SAndreas Fenkart * For omaps with wake-up path, wakeirq will be irq from pinctrl and 17852cd3a2a5SAndreas Fenkart * for other omaps, wakeirq will be from GPIO (dat line remuxed to 17862cd3a2a5SAndreas Fenkart * gpio). wakeirq is needed to detect sdio irq in runtime suspend state 17872cd3a2a5SAndreas Fenkart * with functional clock disabled. 17882cd3a2a5SAndreas Fenkart */ 17892cd3a2a5SAndreas Fenkart if (!host->dev->of_node || !host->wake_irq) 17902cd3a2a5SAndreas Fenkart return -ENODEV; 17912cd3a2a5SAndreas Fenkart 17925b83b223STony Lindgren ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq); 17932cd3a2a5SAndreas Fenkart if (ret) { 17942cd3a2a5SAndreas Fenkart dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n"); 17952cd3a2a5SAndreas Fenkart goto err; 17962cd3a2a5SAndreas Fenkart } 17972cd3a2a5SAndreas Fenkart 17982cd3a2a5SAndreas Fenkart /* 17992cd3a2a5SAndreas Fenkart * Some omaps don't have wake-up path from deeper idle states 18002cd3a2a5SAndreas Fenkart * and need to remux SDIO DAT1 to GPIO for wake-up from idle. 18012cd3a2a5SAndreas Fenkart */ 18022cd3a2a5SAndreas Fenkart if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) { 1803455e5cd6SAndreas Fenkart struct pinctrl *p = devm_pinctrl_get(host->dev); 1804455e5cd6SAndreas Fenkart if (!p) { 18052cd3a2a5SAndreas Fenkart ret = -ENODEV; 1806455e5cd6SAndreas Fenkart goto err_free_irq; 1807455e5cd6SAndreas Fenkart } 1808455e5cd6SAndreas Fenkart if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) { 1809455e5cd6SAndreas Fenkart dev_info(host->dev, "missing default pinctrl state\n"); 1810455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 1811455e5cd6SAndreas Fenkart ret = -EINVAL; 1812455e5cd6SAndreas Fenkart goto err_free_irq; 1813455e5cd6SAndreas Fenkart } 1814455e5cd6SAndreas Fenkart 1815455e5cd6SAndreas Fenkart if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) { 1816455e5cd6SAndreas Fenkart dev_info(host->dev, "missing idle pinctrl state\n"); 1817455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 1818455e5cd6SAndreas Fenkart ret = -EINVAL; 1819455e5cd6SAndreas Fenkart goto err_free_irq; 1820455e5cd6SAndreas Fenkart } 1821455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 18222cd3a2a5SAndreas Fenkart } 18232cd3a2a5SAndreas Fenkart 18245a52b08bSBalaji T K OMAP_HSMMC_WRITE(host->base, HCTL, 18255a52b08bSBalaji T K OMAP_HSMMC_READ(host->base, HCTL) | IWE); 18262cd3a2a5SAndreas Fenkart return 0; 18272cd3a2a5SAndreas Fenkart 1828455e5cd6SAndreas Fenkart err_free_irq: 18295b83b223STony Lindgren dev_pm_clear_wake_irq(host->dev); 18302cd3a2a5SAndreas Fenkart err: 18312cd3a2a5SAndreas Fenkart dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n"); 18322cd3a2a5SAndreas Fenkart host->wake_irq = 0; 18332cd3a2a5SAndreas Fenkart return ret; 18342cd3a2a5SAndreas Fenkart } 18352cd3a2a5SAndreas Fenkart 183670a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 18371b331e69SKim Kyuwon { 18381b331e69SKim Kyuwon u32 hctl, capa, value; 18391b331e69SKim Kyuwon 18401b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 18414621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 18421b331e69SKim Kyuwon hctl = SDVS30; 18431b331e69SKim Kyuwon capa = VS30 | VS18; 18441b331e69SKim Kyuwon } else { 18451b331e69SKim Kyuwon hctl = SDVS18; 18461b331e69SKim Kyuwon capa = VS18; 18471b331e69SKim Kyuwon } 18481b331e69SKim Kyuwon 18491b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 18501b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 18511b331e69SKim Kyuwon 18521b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 18531b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 18541b331e69SKim Kyuwon 18551b331e69SKim Kyuwon /* Set SD bus power bit */ 1856e13bb300SAdrian Hunter set_sd_bus_power(host); 18571b331e69SKim Kyuwon } 18581b331e69SKim Kyuwon 1859afd8c29dSKuninori Morimoto static int omap_hsmmc_multi_io_quirk(struct mmc_card *card, 1860afd8c29dSKuninori Morimoto unsigned int direction, int blk_size) 1861afd8c29dSKuninori Morimoto { 1862afd8c29dSKuninori Morimoto /* This controller can't do multiblock reads due to hw bugs */ 1863afd8c29dSKuninori Morimoto if (direction == MMC_DATA_READ) 1864afd8c29dSKuninori Morimoto return 1; 1865afd8c29dSKuninori Morimoto 1866afd8c29dSKuninori Morimoto return blk_size; 1867afd8c29dSKuninori Morimoto } 1868afd8c29dSKuninori Morimoto 1869afd8c29dSKuninori Morimoto static struct mmc_host_ops omap_hsmmc_ops = { 18709782aff8SPer Forlin .post_req = omap_hsmmc_post_req, 18719782aff8SPer Forlin .pre_req = omap_hsmmc_pre_req, 187270a3341aSDenis Karpov .request = omap_hsmmc_request, 187370a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1874dd498effSDenis Karpov .get_cd = omap_hsmmc_get_cd, 1875a49d8353SAndreas Fenkart .get_ro = mmc_gpio_get_ro, 18764816858cSGrazvydas Ignotas .init_card = omap_hsmmc_init_card, 18772cd3a2a5SAndreas Fenkart .enable_sdio_irq = omap_hsmmc_enable_sdio_irq, 1878dd498effSDenis Karpov }; 1879dd498effSDenis Karpov 1880d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS 1881d900f712SDenis Karpov 188270a3341aSDenis Karpov static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1883d900f712SDenis Karpov { 1884d900f712SDenis Karpov struct mmc_host *mmc = s->private; 188570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 188611dd62a7SDenis Karpov 1887bb0635f0SAndreas Fenkart seq_printf(s, "mmc%d:\n", mmc->index); 1888bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq mode\t%s\n", 1889bb0635f0SAndreas Fenkart (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling"); 1890bb0635f0SAndreas Fenkart 1891bb0635f0SAndreas Fenkart if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1892bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq \t%s\n", 1893bb0635f0SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled" 1894bb0635f0SAndreas Fenkart : "disabled"); 1895bb0635f0SAndreas Fenkart } 1896bb0635f0SAndreas Fenkart seq_printf(s, "ctx_loss:\t%d\n", host->context_loss); 18975e2ea617SAdrian Hunter 1898fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1899bb0635f0SAndreas Fenkart seq_puts(s, "\nregs:\n"); 1900d900f712SDenis Karpov seq_printf(s, "CON:\t\t0x%08x\n", 1901d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CON)); 1902bb0635f0SAndreas Fenkart seq_printf(s, "PSTATE:\t\t0x%08x\n", 1903bb0635f0SAndreas Fenkart OMAP_HSMMC_READ(host->base, PSTATE)); 1904d900f712SDenis Karpov seq_printf(s, "HCTL:\t\t0x%08x\n", 1905d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL)); 1906d900f712SDenis Karpov seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1907d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL)); 1908d900f712SDenis Karpov seq_printf(s, "IE:\t\t0x%08x\n", 1909d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, IE)); 1910d900f712SDenis Karpov seq_printf(s, "ISE:\t\t0x%08x\n", 1911d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, ISE)); 1912d900f712SDenis Karpov seq_printf(s, "CAPA:\t\t0x%08x\n", 1913d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA)); 19145e2ea617SAdrian Hunter 1915fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1916fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1917dd498effSDenis Karpov 1918d900f712SDenis Karpov return 0; 1919d900f712SDenis Karpov } 1920d900f712SDenis Karpov 192170a3341aSDenis Karpov static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1922d900f712SDenis Karpov { 192370a3341aSDenis Karpov return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1924d900f712SDenis Karpov } 1925d900f712SDenis Karpov 1926d900f712SDenis Karpov static const struct file_operations mmc_regs_fops = { 192770a3341aSDenis Karpov .open = omap_hsmmc_regs_open, 1928d900f712SDenis Karpov .read = seq_read, 1929d900f712SDenis Karpov .llseek = seq_lseek, 1930d900f712SDenis Karpov .release = single_release, 1931d900f712SDenis Karpov }; 1932d900f712SDenis Karpov 193370a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1934d900f712SDenis Karpov { 1935d900f712SDenis Karpov if (mmc->debugfs_root) 1936d900f712SDenis Karpov debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1937d900f712SDenis Karpov mmc, &mmc_regs_fops); 1938d900f712SDenis Karpov } 1939d900f712SDenis Karpov 1940d900f712SDenis Karpov #else 1941d900f712SDenis Karpov 194270a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1943d900f712SDenis Karpov { 1944d900f712SDenis Karpov } 1945d900f712SDenis Karpov 1946d900f712SDenis Karpov #endif 1947d900f712SDenis Karpov 194846856a68SRajendra Nayak #ifdef CONFIG_OF 194959445b10SNishanth Menon static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = { 195059445b10SNishanth Menon /* See 35xx errata 2.1.1.128 in SPRZ278F */ 195159445b10SNishanth Menon .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 195259445b10SNishanth Menon }; 195359445b10SNishanth Menon 195459445b10SNishanth Menon static const struct omap_mmc_of_data omap4_mmc_of_data = { 195559445b10SNishanth Menon .reg_offset = 0x100, 195659445b10SNishanth Menon }; 19572cd3a2a5SAndreas Fenkart static const struct omap_mmc_of_data am33xx_mmc_of_data = { 19582cd3a2a5SAndreas Fenkart .reg_offset = 0x100, 19592cd3a2a5SAndreas Fenkart .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING, 19602cd3a2a5SAndreas Fenkart }; 196146856a68SRajendra Nayak 196246856a68SRajendra Nayak static const struct of_device_id omap_mmc_of_match[] = { 196346856a68SRajendra Nayak { 196446856a68SRajendra Nayak .compatible = "ti,omap2-hsmmc", 196546856a68SRajendra Nayak }, 196646856a68SRajendra Nayak { 196759445b10SNishanth Menon .compatible = "ti,omap3-pre-es3-hsmmc", 196859445b10SNishanth Menon .data = &omap3_pre_es3_mmc_of_data, 196959445b10SNishanth Menon }, 197059445b10SNishanth Menon { 197146856a68SRajendra Nayak .compatible = "ti,omap3-hsmmc", 197246856a68SRajendra Nayak }, 197346856a68SRajendra Nayak { 197446856a68SRajendra Nayak .compatible = "ti,omap4-hsmmc", 197559445b10SNishanth Menon .data = &omap4_mmc_of_data, 197646856a68SRajendra Nayak }, 19772cd3a2a5SAndreas Fenkart { 19782cd3a2a5SAndreas Fenkart .compatible = "ti,am33xx-hsmmc", 19792cd3a2a5SAndreas Fenkart .data = &am33xx_mmc_of_data, 19802cd3a2a5SAndreas Fenkart }, 198146856a68SRajendra Nayak {}, 1982b6d085f6SChris Ball }; 198346856a68SRajendra Nayak MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 198446856a68SRajendra Nayak 198555143438SAndreas Fenkart static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 198646856a68SRajendra Nayak { 198755143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata; 198846856a68SRajendra Nayak struct device_node *np = dev->of_node; 198946856a68SRajendra Nayak 199046856a68SRajendra Nayak pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 199146856a68SRajendra Nayak if (!pdata) 199219df45bcSBalaji T K return ERR_PTR(-ENOMEM); /* out of memory */ 199346856a68SRajendra Nayak 199446856a68SRajendra Nayak if (of_find_property(np, "ti,dual-volt", NULL)) 199546856a68SRajendra Nayak pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 199646856a68SRajendra Nayak 1997b7a5646fSAndreas Fenkart pdata->gpio_cd = -EINVAL; 1998b7a5646fSAndreas Fenkart pdata->gpio_cod = -EINVAL; 1999fdb9de12SNeilBrown pdata->gpio_wp = -EINVAL; 200046856a68SRajendra Nayak 200146856a68SRajendra Nayak if (of_find_property(np, "ti,non-removable", NULL)) { 2002326119c9SAndreas Fenkart pdata->nonremovable = true; 2003326119c9SAndreas Fenkart pdata->no_regulator_off_init = true; 200446856a68SRajendra Nayak } 200546856a68SRajendra Nayak 200646856a68SRajendra Nayak if (of_find_property(np, "ti,needs-special-reset", NULL)) 2007326119c9SAndreas Fenkart pdata->features |= HSMMC_HAS_UPDATED_RESET; 200846856a68SRajendra Nayak 2009cd587096SHebbar, Gururaja if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) 2010326119c9SAndreas Fenkart pdata->features |= HSMMC_HAS_HSPE_SUPPORT; 2011cd587096SHebbar, Gururaja 201246856a68SRajendra Nayak return pdata; 201346856a68SRajendra Nayak } 201446856a68SRajendra Nayak #else 201555143438SAndreas Fenkart static inline struct omap_hsmmc_platform_data 201646856a68SRajendra Nayak *of_get_hsmmc_pdata(struct device *dev) 201746856a68SRajendra Nayak { 201819df45bcSBalaji T K return ERR_PTR(-EINVAL); 201946856a68SRajendra Nayak } 202046856a68SRajendra Nayak #endif 202146856a68SRajendra Nayak 2022c3be1efdSBill Pemberton static int omap_hsmmc_probe(struct platform_device *pdev) 2023a45c6cb8SMadhusudhan Chikkature { 202455143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data; 2025a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 202670a3341aSDenis Karpov struct omap_hsmmc_host *host = NULL; 2027a45c6cb8SMadhusudhan Chikkature struct resource *res; 2028db0fefc5SAdrian Hunter int ret, irq; 202946856a68SRajendra Nayak const struct of_device_id *match; 203026b88520SRussell King dma_cap_mask_t mask; 203126b88520SRussell King unsigned tx_req, rx_req; 203259445b10SNishanth Menon const struct omap_mmc_of_data *data; 203377fae219SBalaji T K void __iomem *base; 203446856a68SRajendra Nayak 203546856a68SRajendra Nayak match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 203646856a68SRajendra Nayak if (match) { 203746856a68SRajendra Nayak pdata = of_get_hsmmc_pdata(&pdev->dev); 2038dc642c28SJan Luebbe 2039dc642c28SJan Luebbe if (IS_ERR(pdata)) 2040dc642c28SJan Luebbe return PTR_ERR(pdata); 2041dc642c28SJan Luebbe 204246856a68SRajendra Nayak if (match->data) { 204359445b10SNishanth Menon data = match->data; 204459445b10SNishanth Menon pdata->reg_offset = data->reg_offset; 204559445b10SNishanth Menon pdata->controller_flags |= data->controller_flags; 204646856a68SRajendra Nayak } 204746856a68SRajendra Nayak } 2048a45c6cb8SMadhusudhan Chikkature 2049a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 2050a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 2051a45c6cb8SMadhusudhan Chikkature return -ENXIO; 2052a45c6cb8SMadhusudhan Chikkature } 2053a45c6cb8SMadhusudhan Chikkature 2054a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2055a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 2056a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 2057a45c6cb8SMadhusudhan Chikkature return -ENXIO; 2058a45c6cb8SMadhusudhan Chikkature 205977fae219SBalaji T K base = devm_ioremap_resource(&pdev->dev, res); 206077fae219SBalaji T K if (IS_ERR(base)) 206177fae219SBalaji T K return PTR_ERR(base); 2062a45c6cb8SMadhusudhan Chikkature 206370a3341aSDenis Karpov mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 2064a45c6cb8SMadhusudhan Chikkature if (!mmc) { 2065a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 20661e363e3bSAndreas Fenkart goto err; 2067a45c6cb8SMadhusudhan Chikkature } 2068a45c6cb8SMadhusudhan Chikkature 2069fdb9de12SNeilBrown ret = mmc_of_parse(mmc); 2070fdb9de12SNeilBrown if (ret) 2071fdb9de12SNeilBrown goto err1; 2072fdb9de12SNeilBrown 2073a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 2074a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 2075a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 2076a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 2077a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 2078a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 2079a45c6cb8SMadhusudhan Chikkature host->irq = irq; 2080fc307df8SBalaji T K host->mapbase = res->start + pdata->reg_offset; 208177fae219SBalaji T K host->base = base + pdata->reg_offset; 20826da20c89SAdrian Hunter host->power_mode = MMC_POWER_OFF; 20839782aff8SPer Forlin host->next_data.cookie = 1; 2084e99448ffSBalaji T K host->pbias_enabled = 0; 20853f77f702SKishon Vijay Abraham I host->vqmmc_enabled = 0; 2086a45c6cb8SMadhusudhan Chikkature 208741afa314SNeilBrown ret = omap_hsmmc_gpio_init(mmc, host, pdata); 20881e363e3bSAndreas Fenkart if (ret) 20891e363e3bSAndreas Fenkart goto err_gpio; 20901e363e3bSAndreas Fenkart 2091a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 2092a45c6cb8SMadhusudhan Chikkature 20932cd3a2a5SAndreas Fenkart if (pdev->dev.of_node) 20942cd3a2a5SAndreas Fenkart host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1); 20952cd3a2a5SAndreas Fenkart 209670a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ops; 2097dd498effSDenis Karpov 20986b206efeSAndy Shevchenko mmc->f_min = OMAP_MMC_MIN_CLOCK; 2099d418ed87SDaniel Mack 2100d418ed87SDaniel Mack if (pdata->max_freq > 0) 2101d418ed87SDaniel Mack mmc->f_max = pdata->max_freq; 2102fdb9de12SNeilBrown else if (mmc->f_max == 0) 21036b206efeSAndy Shevchenko mmc->f_max = OMAP_MMC_MAX_CLOCK; 2104a45c6cb8SMadhusudhan Chikkature 21054dffd7a2SAdrian Hunter spin_lock_init(&host->irq_lock); 2106a45c6cb8SMadhusudhan Chikkature 21079618195eSBalaji T K host->fclk = devm_clk_get(&pdev->dev, "fck"); 2108a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 2109a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 2110a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 2111a45c6cb8SMadhusudhan Chikkature goto err1; 2112a45c6cb8SMadhusudhan Chikkature } 2113a45c6cb8SMadhusudhan Chikkature 21149b68256cSPaul Walmsley if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 21159b68256cSPaul Walmsley dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 2116afd8c29dSKuninori Morimoto omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk; 21179b68256cSPaul Walmsley } 2118dd498effSDenis Karpov 21195b83b223STony Lindgren device_init_wakeup(&pdev->dev, true); 2120fa4aa2d4SBalaji T K pm_runtime_enable(host->dev); 2121fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2122fa4aa2d4SBalaji T K pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 2123fa4aa2d4SBalaji T K pm_runtime_use_autosuspend(host->dev); 2124a45c6cb8SMadhusudhan Chikkature 212592a3aebfSBalaji T K omap_hsmmc_context_save(host); 212692a3aebfSBalaji T K 21279618195eSBalaji T K host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck"); 2128a45c6cb8SMadhusudhan Chikkature /* 2129a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 2130a45c6cb8SMadhusudhan Chikkature */ 2131cd03d9a8SRajendra Nayak if (IS_ERR(host->dbclk)) { 2132cd03d9a8SRajendra Nayak host->dbclk = NULL; 213394c18149SRajendra Nayak } else if (clk_prepare_enable(host->dbclk) != 0) { 2134cd03d9a8SRajendra Nayak dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 2135cd03d9a8SRajendra Nayak host->dbclk = NULL; 21362bec0893SAdrian Hunter } 2137a45c6cb8SMadhusudhan Chikkature 21380ccd76d4SJuha Yrjola /* Since we do only SG emulation, we can have as many segs 21390ccd76d4SJuha Yrjola * as we want. */ 2140a36274e0SMartin K. Petersen mmc->max_segs = 1024; 21410ccd76d4SJuha Yrjola 2142a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 2143a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 2144a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2145a45c6cb8SMadhusudhan Chikkature mmc->max_seg_size = mmc->max_req_size; 2146a45c6cb8SMadhusudhan Chikkature 214713189e78SJarkko Lavinen mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 214893caf8e6SAdrian Hunter MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 2149a45c6cb8SMadhusudhan Chikkature 2150326119c9SAndreas Fenkart mmc->caps |= mmc_pdata(host)->caps; 21513a63833eSSukumar Ghorai if (mmc->caps & MMC_CAP_8_BIT_DATA) 2152a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 2153a45c6cb8SMadhusudhan Chikkature 2154326119c9SAndreas Fenkart if (mmc_pdata(host)->nonremovable) 215523d99bb9SAdrian Hunter mmc->caps |= MMC_CAP_NONREMOVABLE; 215623d99bb9SAdrian Hunter 2157fdb9de12SNeilBrown mmc->pm_caps |= mmc_pdata(host)->pm_caps; 21586fdc75deSEliad Peller 215970a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 2160a45c6cb8SMadhusudhan Chikkature 21614a29b559SSantosh Shilimkar if (!pdev->dev.of_node) { 2162b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 2163b7bf773bSBalaji T K if (!res) { 2164b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n"); 21659c17d08cSKevin Hilman ret = -ENXIO; 2166f3e2f1ddSGrazvydas Ignotas goto err_irq; 2167a45c6cb8SMadhusudhan Chikkature } 216826b88520SRussell King tx_req = res->start; 2169b7bf773bSBalaji T K 2170b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 2171b7bf773bSBalaji T K if (!res) { 2172b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n"); 21739c17d08cSKevin Hilman ret = -ENXIO; 2174b7bf773bSBalaji T K goto err_irq; 2175b7bf773bSBalaji T K } 217626b88520SRussell King rx_req = res->start; 21774a29b559SSantosh Shilimkar } 2178c5c98927SRussell King 2179c5c98927SRussell King dma_cap_zero(mask); 2180c5c98927SRussell King dma_cap_set(DMA_SLAVE, mask); 218126b88520SRussell King 2182d272fbf0SMatt Porter host->rx_chan = 2183d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 2184d272fbf0SMatt Porter &rx_req, &pdev->dev, "rx"); 2185d272fbf0SMatt Porter 2186c5c98927SRussell King if (!host->rx_chan) { 218726b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req); 218804e8c7bcSKevin Hilman ret = -ENXIO; 218926b88520SRussell King goto err_irq; 2190c5c98927SRussell King } 219126b88520SRussell King 2192d272fbf0SMatt Porter host->tx_chan = 2193d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 2194d272fbf0SMatt Porter &tx_req, &pdev->dev, "tx"); 2195d272fbf0SMatt Porter 2196c5c98927SRussell King if (!host->tx_chan) { 219726b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req); 219804e8c7bcSKevin Hilman ret = -ENXIO; 219926b88520SRussell King goto err_irq; 2200c5c98927SRussell King } 2201a45c6cb8SMadhusudhan Chikkature 2202a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 2203e1538ed7SBalaji T K ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0, 2204a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 2205a45c6cb8SMadhusudhan Chikkature if (ret) { 2206b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 2207a45c6cb8SMadhusudhan Chikkature goto err_irq; 2208a45c6cb8SMadhusudhan Chikkature } 2209a45c6cb8SMadhusudhan Chikkature 2210f7f0f035SAndreas Fenkart if (omap_hsmmc_have_reg()) { 2211db0fefc5SAdrian Hunter ret = omap_hsmmc_reg_get(host); 2212db0fefc5SAdrian Hunter if (ret) 2213bb09d151SAndreas Fenkart goto err_irq; 2214db0fefc5SAdrian Hunter } 2215db0fefc5SAdrian Hunter 2216326119c9SAndreas Fenkart mmc->ocr_avail = mmc_pdata(host)->ocr_mask; 2217a45c6cb8SMadhusudhan Chikkature 2218b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 2219a45c6cb8SMadhusudhan Chikkature 22202cd3a2a5SAndreas Fenkart /* 22212cd3a2a5SAndreas Fenkart * For now, only support SDIO interrupt if we have a separate 22222cd3a2a5SAndreas Fenkart * wake-up interrupt configured from device tree. This is because 22232cd3a2a5SAndreas Fenkart * the wake-up interrupt is needed for idle state and some 22242cd3a2a5SAndreas Fenkart * platforms need special quirks. And we don't want to add new 22252cd3a2a5SAndreas Fenkart * legacy mux platform init code callbacks any longer as we 22262cd3a2a5SAndreas Fenkart * are moving to DT based booting anyways. 22272cd3a2a5SAndreas Fenkart */ 22282cd3a2a5SAndreas Fenkart ret = omap_hsmmc_configure_wake_irq(host); 22292cd3a2a5SAndreas Fenkart if (!ret) 22302cd3a2a5SAndreas Fenkart mmc->caps |= MMC_CAP_SDIO_IRQ; 22312cd3a2a5SAndreas Fenkart 2232b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2233b62f6228SAdrian Hunter 2234a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 2235a45c6cb8SMadhusudhan Chikkature 2236326119c9SAndreas Fenkart if (mmc_pdata(host)->name != NULL) { 2237a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2238a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2239a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 2240a45c6cb8SMadhusudhan Chikkature } 2241cde592cbSAndreas Fenkart if (host->get_cover_state) { 2242a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, 2243a45c6cb8SMadhusudhan Chikkature &dev_attr_cover_switch); 2244a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2245db0fefc5SAdrian Hunter goto err_slot_name; 2246a45c6cb8SMadhusudhan Chikkature } 2247a45c6cb8SMadhusudhan Chikkature 224870a3341aSDenis Karpov omap_hsmmc_debugfs(mmc); 2249fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2250fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2251d900f712SDenis Karpov 2252a45c6cb8SMadhusudhan Chikkature return 0; 2253a45c6cb8SMadhusudhan Chikkature 2254a45c6cb8SMadhusudhan Chikkature err_slot_name: 2255a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 2256a45c6cb8SMadhusudhan Chikkature err_irq: 22575b83b223STony Lindgren device_init_wakeup(&pdev->dev, false); 2258c5c98927SRussell King if (host->tx_chan) 2259c5c98927SRussell King dma_release_channel(host->tx_chan); 2260c5c98927SRussell King if (host->rx_chan) 2261c5c98927SRussell King dma_release_channel(host->rx_chan); 2262d59d77edSBalaji T K pm_runtime_put_sync(host->dev); 226337f6190dSTony Lindgren pm_runtime_disable(host->dev); 22649618195eSBalaji T K if (host->dbclk) 226594c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2266a45c6cb8SMadhusudhan Chikkature err1: 22671e363e3bSAndreas Fenkart err_gpio: 2268a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 2269db0fefc5SAdrian Hunter err: 2270a45c6cb8SMadhusudhan Chikkature return ret; 2271a45c6cb8SMadhusudhan Chikkature } 2272a45c6cb8SMadhusudhan Chikkature 22736e0ee714SBill Pemberton static int omap_hsmmc_remove(struct platform_device *pdev) 2274a45c6cb8SMadhusudhan Chikkature { 227570a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2276a45c6cb8SMadhusudhan Chikkature 2277fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2278a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 2279a45c6cb8SMadhusudhan Chikkature 2280c5c98927SRussell King if (host->tx_chan) 2281c5c98927SRussell King dma_release_channel(host->tx_chan); 2282c5c98927SRussell King if (host->rx_chan) 2283c5c98927SRussell King dma_release_channel(host->rx_chan); 2284c5c98927SRussell King 2285fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2286fa4aa2d4SBalaji T K pm_runtime_disable(host->dev); 22875b83b223STony Lindgren device_init_wakeup(&pdev->dev, false); 22889618195eSBalaji T K if (host->dbclk) 228994c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2290a45c6cb8SMadhusudhan Chikkature 22919d1f0286SBalaji T K mmc_free_host(host->mmc); 2292a45c6cb8SMadhusudhan Chikkature 2293a45c6cb8SMadhusudhan Chikkature return 0; 2294a45c6cb8SMadhusudhan Chikkature } 2295a45c6cb8SMadhusudhan Chikkature 22963d3bbfbdSRuss Dill #ifdef CONFIG_PM_SLEEP 2297a791daa1SKevin Hilman static int omap_hsmmc_suspend(struct device *dev) 2298a45c6cb8SMadhusudhan Chikkature { 2299927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2300927ce944SFelipe Balbi 2301927ce944SFelipe Balbi if (!host) 2302927ce944SFelipe Balbi return 0; 2303a45c6cb8SMadhusudhan Chikkature 2304fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 230531f9d463SEliad Peller 230631f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 23072cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 23082cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 23092cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 231031f9d463SEliad Peller OMAP_HSMMC_WRITE(host->base, HCTL, 231131f9d463SEliad Peller OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 231231f9d463SEliad Peller } 2313927ce944SFelipe Balbi 2314cd03d9a8SRajendra Nayak if (host->dbclk) 231594c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 23163932afd5SUlf Hansson 2317fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 23183932afd5SUlf Hansson return 0; 2319a45c6cb8SMadhusudhan Chikkature } 2320a45c6cb8SMadhusudhan Chikkature 2321a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 2322a791daa1SKevin Hilman static int omap_hsmmc_resume(struct device *dev) 2323a45c6cb8SMadhusudhan Chikkature { 2324927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2325927ce944SFelipe Balbi 2326927ce944SFelipe Balbi if (!host) 2327927ce944SFelipe Balbi return 0; 2328a45c6cb8SMadhusudhan Chikkature 2329fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 233011dd62a7SDenis Karpov 2331cd03d9a8SRajendra Nayak if (host->dbclk) 233294c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 23332bec0893SAdrian Hunter 233431f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 233570a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 23361b331e69SKim Kyuwon 2337b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2338fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2339fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 23403932afd5SUlf Hansson return 0; 2341a45c6cb8SMadhusudhan Chikkature } 2342a45c6cb8SMadhusudhan Chikkature #endif 2343a45c6cb8SMadhusudhan Chikkature 2344fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_suspend(struct device *dev) 2345fa4aa2d4SBalaji T K { 2346fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 23472cd3a2a5SAndreas Fenkart unsigned long flags; 2348f945901fSAndreas Fenkart int ret = 0; 2349fa4aa2d4SBalaji T K 2350fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2351fa4aa2d4SBalaji T K omap_hsmmc_context_save(host); 2352927ce944SFelipe Balbi dev_dbg(dev, "disabled\n"); 2353fa4aa2d4SBalaji T K 23542cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 23552cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 23562cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 23572cd3a2a5SAndreas Fenkart /* disable sdio irq handling to prevent race */ 23582cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 23592cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 2360f945901fSAndreas Fenkart 2361f945901fSAndreas Fenkart if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) { 2362f945901fSAndreas Fenkart /* 2363f945901fSAndreas Fenkart * dat1 line low, pending sdio irq 2364f945901fSAndreas Fenkart * race condition: possible irq handler running on 2365f945901fSAndreas Fenkart * multi-core, abort 2366f945901fSAndreas Fenkart */ 2367f945901fSAndreas Fenkart dev_dbg(dev, "pending sdio irq, abort suspend\n"); 23682cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 2369f945901fSAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 2370f945901fSAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 2371f945901fSAndreas Fenkart pm_runtime_mark_last_busy(dev); 2372f945901fSAndreas Fenkart ret = -EBUSY; 2373f945901fSAndreas Fenkart goto abort; 2374f945901fSAndreas Fenkart } 23752cd3a2a5SAndreas Fenkart 237697978a44SAndreas Fenkart pinctrl_pm_select_idle_state(dev); 237797978a44SAndreas Fenkart } else { 237897978a44SAndreas Fenkart pinctrl_pm_select_idle_state(dev); 23792cd3a2a5SAndreas Fenkart } 238097978a44SAndreas Fenkart 2381f945901fSAndreas Fenkart abort: 23822cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2383f945901fSAndreas Fenkart return ret; 2384fa4aa2d4SBalaji T K } 2385fa4aa2d4SBalaji T K 2386fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_resume(struct device *dev) 2387fa4aa2d4SBalaji T K { 2388fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 23892cd3a2a5SAndreas Fenkart unsigned long flags; 2390fa4aa2d4SBalaji T K 2391fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2392fa4aa2d4SBalaji T K omap_hsmmc_context_restore(host); 2393927ce944SFelipe Balbi dev_dbg(dev, "enabled\n"); 2394fa4aa2d4SBalaji T K 23952cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 23962cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 23972cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 23982cd3a2a5SAndreas Fenkart 239997978a44SAndreas Fenkart pinctrl_pm_select_default_state(host->dev); 240097978a44SAndreas Fenkart 240197978a44SAndreas Fenkart /* irq lost, if pinmux incorrect */ 24022cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 24032cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 24042cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 240597978a44SAndreas Fenkart } else { 240697978a44SAndreas Fenkart pinctrl_pm_select_default_state(host->dev); 24072cd3a2a5SAndreas Fenkart } 24082cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2409fa4aa2d4SBalaji T K return 0; 2410fa4aa2d4SBalaji T K } 2411fa4aa2d4SBalaji T K 2412a791daa1SKevin Hilman static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 24133d3bbfbdSRuss Dill SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume) 2414fa4aa2d4SBalaji T K .runtime_suspend = omap_hsmmc_runtime_suspend, 2415fa4aa2d4SBalaji T K .runtime_resume = omap_hsmmc_runtime_resume, 2416a791daa1SKevin Hilman }; 2417a791daa1SKevin Hilman 2418a791daa1SKevin Hilman static struct platform_driver omap_hsmmc_driver = { 2419efa25fd3SFelipe Balbi .probe = omap_hsmmc_probe, 24200433c143SBill Pemberton .remove = omap_hsmmc_remove, 2421a45c6cb8SMadhusudhan Chikkature .driver = { 2422a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 2423a791daa1SKevin Hilman .pm = &omap_hsmmc_dev_pm_ops, 242446856a68SRajendra Nayak .of_match_table = of_match_ptr(omap_mmc_of_match), 2425a45c6cb8SMadhusudhan Chikkature }, 2426a45c6cb8SMadhusudhan Chikkature }; 2427a45c6cb8SMadhusudhan Chikkature 2428b796450bSFelipe Balbi module_platform_driver(omap_hsmmc_driver); 2429a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2430a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 2431a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 2432a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 2433