1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20ac330f44SAndy Shevchenko #include <linux/kernel.h> 21d900f712SDenis Karpov #include <linux/debugfs.h> 22c5c98927SRussell King #include <linux/dmaengine.h> 23d900f712SDenis Karpov #include <linux/seq_file.h> 24031cd037SFelipe Balbi #include <linux/sizes.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 29a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 30a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 3146856a68SRajendra Nayak #include <linux/of.h> 322cd3a2a5SAndreas Fenkart #include <linux/of_irq.h> 3346856a68SRajendra Nayak #include <linux/of_gpio.h> 3446856a68SRajendra Nayak #include <linux/of_device.h> 35ee526d51SBalaji T K #include <linux/omap-dmaengine.h> 36a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 3713189e78SJarkko Lavinen #include <linux/mmc/core.h> 3893caf8e6SAdrian Hunter #include <linux/mmc/mmc.h> 3941afa314SNeilBrown #include <linux/mmc/slot-gpio.h> 40a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 412cd3a2a5SAndreas Fenkart #include <linux/irq.h> 42db0fefc5SAdrian Hunter #include <linux/gpio.h> 43db0fefc5SAdrian Hunter #include <linux/regulator/consumer.h> 4446b76035SDaniel Mack #include <linux/pinctrl/consumer.h> 45fa4aa2d4SBalaji T K #include <linux/pm_runtime.h> 4655143438SAndreas Fenkart #include <linux/platform_data/hsmmc-omap.h> 47a45c6cb8SMadhusudhan Chikkature 48a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 4911dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS 0x0014 50a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 51a2e77152SBalaji T K #define OMAP_HSMMC_SDMASA 0x0100 52a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 57a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 58a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 59a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 60bb0635f0SAndreas Fenkart #define OMAP_HSMMC_PSTATE 0x0124 61a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 62a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 63a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 64a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 65a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 66a2e77152SBalaji T K #define OMAP_HSMMC_AC12 0x013C 67a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 68a45c6cb8SMadhusudhan Chikkature 69a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 70a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 71cd587096SHebbar, Gururaja #define HSS (1 << 21) 72a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 73a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 74eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 751b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 76a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 77a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 78a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 79a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 80a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 81a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 82a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 83a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 84ed164182SBalaji T K #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ 85a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 86a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 87a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 88a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 89a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 90a2e77152SBalaji T K #define ACEN_ACMD23 (2 << 2) 91a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 92a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 93a7e96879SVenkatraman S #define DMAE 0x1 94a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 95a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 96a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 97cd587096SHebbar, Gururaja #define HSPE (1 << 2) 985a52b08bSBalaji T K #define IWE (1 << 24) 9903b5d924SBalaji T K #define DDR (1 << 19) 1005a52b08bSBalaji T K #define CLKEXTFREE (1 << 16) 1015a52b08bSBalaji T K #define CTPL (1 << 11) 10273153010SJarkko Lavinen #define DW8 (1 << 5) 103a45c6cb8SMadhusudhan Chikkature #define OD 0x1 104a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 105a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 106a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 107a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 108a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 10911dd62a7SDenis Karpov #define SOFTRESET (1 << 1) 110a45c6cb8SMadhusudhan Chikkature 111f945901fSAndreas Fenkart /* PSTATE */ 112f945901fSAndreas Fenkart #define DLEV_DAT(x) (1 << (20 + (x))) 113f945901fSAndreas Fenkart 114a7e96879SVenkatraman S /* Interrupt masks for IE and ISE register */ 115a7e96879SVenkatraman S #define CC_EN (1 << 0) 116a7e96879SVenkatraman S #define TC_EN (1 << 1) 117a7e96879SVenkatraman S #define BWR_EN (1 << 4) 118a7e96879SVenkatraman S #define BRR_EN (1 << 5) 1192cd3a2a5SAndreas Fenkart #define CIRQ_EN (1 << 8) 120a7e96879SVenkatraman S #define ERR_EN (1 << 15) 121a7e96879SVenkatraman S #define CTO_EN (1 << 16) 122a7e96879SVenkatraman S #define CCRC_EN (1 << 17) 123a7e96879SVenkatraman S #define CEB_EN (1 << 18) 124a7e96879SVenkatraman S #define CIE_EN (1 << 19) 125a7e96879SVenkatraman S #define DTO_EN (1 << 20) 126a7e96879SVenkatraman S #define DCRC_EN (1 << 21) 127a7e96879SVenkatraman S #define DEB_EN (1 << 22) 128a2e77152SBalaji T K #define ACE_EN (1 << 24) 129a7e96879SVenkatraman S #define CERR_EN (1 << 28) 130a7e96879SVenkatraman S #define BADA_EN (1 << 29) 131a7e96879SVenkatraman S 132a2e77152SBalaji T K #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\ 133a7e96879SVenkatraman S DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ 134a7e96879SVenkatraman S BRR_EN | BWR_EN | TC_EN | CC_EN) 135a7e96879SVenkatraman S 136a2e77152SBalaji T K #define CNI (1 << 7) 137a2e77152SBalaji T K #define ACIE (1 << 4) 138a2e77152SBalaji T K #define ACEB (1 << 3) 139a2e77152SBalaji T K #define ACCE (1 << 2) 140a2e77152SBalaji T K #define ACTO (1 << 1) 141a2e77152SBalaji T K #define ACNE (1 << 0) 142a2e77152SBalaji T K 143fa4aa2d4SBalaji T K #define MMC_AUTOSUSPEND_DELAY 100 1441e881786SJianpeng Ma #define MMC_TIMEOUT_MS 20 /* 20 mSec */ 1451e881786SJianpeng Ma #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ 1466b206efeSAndy Shevchenko #define OMAP_MMC_MIN_CLOCK 400000 1476b206efeSAndy Shevchenko #define OMAP_MMC_MAX_CLOCK 52000000 1480005ae73SKishore Kadiyala #define DRIVER_NAME "omap_hsmmc" 149a45c6cb8SMadhusudhan Chikkature 150e99448ffSBalaji T K #define VDD_1V8 1800000 /* 180000 uV */ 151e99448ffSBalaji T K #define VDD_3V0 3000000 /* 300000 uV */ 152e99448ffSBalaji T K #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1) 153e99448ffSBalaji T K 154a45c6cb8SMadhusudhan Chikkature /* 155a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 156a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 157a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 158a45c6cb8SMadhusudhan Chikkature */ 159326119c9SAndreas Fenkart #define mmc_pdata(host) host->pdata 160a45c6cb8SMadhusudhan Chikkature 161a45c6cb8SMadhusudhan Chikkature /* 162a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 163a45c6cb8SMadhusudhan Chikkature */ 164a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 165a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 166a45c6cb8SMadhusudhan Chikkature 167a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 168a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 169a45c6cb8SMadhusudhan Chikkature 1709782aff8SPer Forlin struct omap_hsmmc_next { 1719782aff8SPer Forlin unsigned int dma_len; 1729782aff8SPer Forlin s32 cookie; 1739782aff8SPer Forlin }; 1749782aff8SPer Forlin 17570a3341aSDenis Karpov struct omap_hsmmc_host { 176a45c6cb8SMadhusudhan Chikkature struct device *dev; 177a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 178a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 179a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 180a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 181a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 182a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 183db0fefc5SAdrian Hunter /* 184db0fefc5SAdrian Hunter * vcc == configured supply 185db0fefc5SAdrian Hunter * vcc_aux == optional 186db0fefc5SAdrian Hunter * - MMC1, supply for DAT4..DAT7 187db0fefc5SAdrian Hunter * - MMC2/MMC2, external level shifter voltage supply, for 188db0fefc5SAdrian Hunter * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) 189db0fefc5SAdrian Hunter */ 190db0fefc5SAdrian Hunter struct regulator *vcc; 191db0fefc5SAdrian Hunter struct regulator *vcc_aux; 192e99448ffSBalaji T K struct regulator *pbias; 193e99448ffSBalaji T K bool pbias_enabled; 194a45c6cb8SMadhusudhan Chikkature void __iomem *base; 195a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 1964dffd7a2SAdrian Hunter spinlock_t irq_lock; /* Prevent races with irq handler */ 197a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 1980ccd76d4SJuha Yrjola unsigned int dma_sg_idx; 199a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 200a3621465SAdrian Hunter unsigned char power_mode; 201a45c6cb8SMadhusudhan Chikkature int suspended; 2020a82e06eSTony Lindgren u32 con; 2030a82e06eSTony Lindgren u32 hctl; 2040a82e06eSTony Lindgren u32 sysctl; 2050a82e06eSTony Lindgren u32 capa; 206a45c6cb8SMadhusudhan Chikkature int irq; 2072cd3a2a5SAndreas Fenkart int wake_irq; 208a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 209c5c98927SRussell King struct dma_chan *tx_chan; 210c5c98927SRussell King struct dma_chan *rx_chan; 2114a694dc9SAdrian Hunter int response_busy; 21211dd62a7SDenis Karpov int context_loss; 213b62f6228SAdrian Hunter int protect_card; 214b62f6228SAdrian Hunter int reqs_blocked; 215db0fefc5SAdrian Hunter int use_reg; 216b417577dSAdrian Hunter int req_in_progress; 2176e3076c2SBalaji T K unsigned long clk_rate; 218a2e77152SBalaji T K unsigned int flags; 2192cd3a2a5SAndreas Fenkart #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */ 2202cd3a2a5SAndreas Fenkart #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */ 2212cd3a2a5SAndreas Fenkart #define HSMMC_WAKE_IRQ_ENABLED (1 << 2) 2229782aff8SPer Forlin struct omap_hsmmc_next next_data; 22355143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata; 224b5cd43f0SAndreas Fenkart 225b5cd43f0SAndreas Fenkart /* return MMC cover switch state, can be NULL if not supported. 226b5cd43f0SAndreas Fenkart * 227b5cd43f0SAndreas Fenkart * possible return values: 228b5cd43f0SAndreas Fenkart * 0 - closed 229b5cd43f0SAndreas Fenkart * 1 - open 230b5cd43f0SAndreas Fenkart */ 23180412ca8SAndreas Fenkart int (*get_cover_state)(struct device *dev); 232b5cd43f0SAndreas Fenkart 23380412ca8SAndreas Fenkart int (*card_detect)(struct device *dev); 234a45c6cb8SMadhusudhan Chikkature }; 235a45c6cb8SMadhusudhan Chikkature 23659445b10SNishanth Menon struct omap_mmc_of_data { 23759445b10SNishanth Menon u32 reg_offset; 23859445b10SNishanth Menon u8 controller_flags; 23959445b10SNishanth Menon }; 24059445b10SNishanth Menon 241bf129e1cSBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host); 242bf129e1cSBalaji T K 24380412ca8SAndreas Fenkart static int omap_hsmmc_card_detect(struct device *dev) 244db0fefc5SAdrian Hunter { 2459ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 246db0fefc5SAdrian Hunter 24741afa314SNeilBrown return mmc_gpio_get_cd(host->mmc); 248db0fefc5SAdrian Hunter } 249db0fefc5SAdrian Hunter 25080412ca8SAndreas Fenkart static int omap_hsmmc_get_cover_state(struct device *dev) 251db0fefc5SAdrian Hunter { 2529ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 253db0fefc5SAdrian Hunter 25441afa314SNeilBrown return mmc_gpio_get_cd(host->mmc); 255db0fefc5SAdrian Hunter } 256db0fefc5SAdrian Hunter 257b702b106SAdrian Hunter #ifdef CONFIG_REGULATOR 258b702b106SAdrian Hunter 25980412ca8SAndreas Fenkart static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd) 260db0fefc5SAdrian Hunter { 261db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 262db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 263db0fefc5SAdrian Hunter int ret = 0; 264db0fefc5SAdrian Hunter 265db0fefc5SAdrian Hunter /* 266db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 267db0fefc5SAdrian Hunter * voltage always-on regulator. 268db0fefc5SAdrian Hunter */ 269db0fefc5SAdrian Hunter if (!host->vcc) 270db0fefc5SAdrian Hunter return 0; 271db0fefc5SAdrian Hunter 272326119c9SAndreas Fenkart if (mmc_pdata(host)->before_set_reg) 27380412ca8SAndreas Fenkart mmc_pdata(host)->before_set_reg(dev, power_on, vdd); 274db0fefc5SAdrian Hunter 275e99448ffSBalaji T K if (host->pbias) { 276e99448ffSBalaji T K if (host->pbias_enabled == 1) { 277e99448ffSBalaji T K ret = regulator_disable(host->pbias); 278e99448ffSBalaji T K if (!ret) 279e99448ffSBalaji T K host->pbias_enabled = 0; 280e99448ffSBalaji T K } 281e99448ffSBalaji T K regulator_set_voltage(host->pbias, VDD_3V0, VDD_3V0); 282e99448ffSBalaji T K } 283e99448ffSBalaji T K 284db0fefc5SAdrian Hunter /* 285db0fefc5SAdrian Hunter * Assume Vcc regulator is used only to power the card ... OMAP 286db0fefc5SAdrian Hunter * VDDS is used to power the pins, optionally with a transceiver to 287db0fefc5SAdrian Hunter * support cards using voltages other than VDDS (1.8V nominal). When a 288db0fefc5SAdrian Hunter * transceiver is used, DAT3..7 are muxed as transceiver control pins. 289db0fefc5SAdrian Hunter * 290db0fefc5SAdrian Hunter * In some cases this regulator won't support enable/disable; 291db0fefc5SAdrian Hunter * e.g. it's a fixed rail for a WLAN chip. 292db0fefc5SAdrian Hunter * 293db0fefc5SAdrian Hunter * In other cases vcc_aux switches interface power. Example, for 294db0fefc5SAdrian Hunter * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 295db0fefc5SAdrian Hunter * chips/cards need an interface voltage rail too. 296db0fefc5SAdrian Hunter */ 297db0fefc5SAdrian Hunter if (power_on) { 298987fd49bSBalaji T K if (host->vcc) 29999fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 300db0fefc5SAdrian Hunter /* Enable interface voltage rail, if needed */ 301db0fefc5SAdrian Hunter if (ret == 0 && host->vcc_aux) { 302db0fefc5SAdrian Hunter ret = regulator_enable(host->vcc_aux); 303987fd49bSBalaji T K if (ret < 0 && host->vcc) 30499fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 30599fc5131SLinus Walleij host->vcc, 0); 306db0fefc5SAdrian Hunter } 307db0fefc5SAdrian Hunter } else { 30899fc5131SLinus Walleij /* Shut down the rail */ 3096da20c89SAdrian Hunter if (host->vcc_aux) 310db0fefc5SAdrian Hunter ret = regulator_disable(host->vcc_aux); 311987fd49bSBalaji T K if (host->vcc) { 31299fc5131SLinus Walleij /* Then proceed to shut down the local regulator */ 31399fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 31499fc5131SLinus Walleij host->vcc, 0); 31599fc5131SLinus Walleij } 316db0fefc5SAdrian Hunter } 317db0fefc5SAdrian Hunter 318e99448ffSBalaji T K if (host->pbias) { 319e99448ffSBalaji T K if (vdd <= VDD_165_195) 320e99448ffSBalaji T K ret = regulator_set_voltage(host->pbias, VDD_1V8, 321e99448ffSBalaji T K VDD_1V8); 322e99448ffSBalaji T K else 323e99448ffSBalaji T K ret = regulator_set_voltage(host->pbias, VDD_3V0, 324e99448ffSBalaji T K VDD_3V0); 325e99448ffSBalaji T K if (ret < 0) 326e99448ffSBalaji T K goto error_set_power; 327e99448ffSBalaji T K 328e99448ffSBalaji T K if (host->pbias_enabled == 0) { 329e99448ffSBalaji T K ret = regulator_enable(host->pbias); 330e99448ffSBalaji T K if (!ret) 331e99448ffSBalaji T K host->pbias_enabled = 1; 332e99448ffSBalaji T K } 333e99448ffSBalaji T K } 334e99448ffSBalaji T K 335326119c9SAndreas Fenkart if (mmc_pdata(host)->after_set_reg) 33680412ca8SAndreas Fenkart mmc_pdata(host)->after_set_reg(dev, power_on, vdd); 337db0fefc5SAdrian Hunter 338e99448ffSBalaji T K error_set_power: 339db0fefc5SAdrian Hunter return ret; 340db0fefc5SAdrian Hunter } 341db0fefc5SAdrian Hunter 342db0fefc5SAdrian Hunter static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 343db0fefc5SAdrian Hunter { 344db0fefc5SAdrian Hunter struct regulator *reg; 34564be9782Skishore kadiyala int ocr_value = 0; 346db0fefc5SAdrian Hunter 347f2ddc1daSBalaji T K reg = devm_regulator_get(host->dev, "vmmc"); 348db0fefc5SAdrian Hunter if (IS_ERR(reg)) { 349987fd49bSBalaji T K dev_err(host->dev, "unable to get vmmc regulator %ld\n", 350987fd49bSBalaji T K PTR_ERR(reg)); 3511fdc90fbSNeilBrown return PTR_ERR(reg); 352db0fefc5SAdrian Hunter } else { 353db0fefc5SAdrian Hunter host->vcc = reg; 35464be9782Skishore kadiyala ocr_value = mmc_regulator_get_ocrmask(reg); 355326119c9SAndreas Fenkart if (!mmc_pdata(host)->ocr_mask) { 356326119c9SAndreas Fenkart mmc_pdata(host)->ocr_mask = ocr_value; 35764be9782Skishore kadiyala } else { 358326119c9SAndreas Fenkart if (!(mmc_pdata(host)->ocr_mask & ocr_value)) { 3592cecdf00SRajendra Nayak dev_err(host->dev, "ocrmask %x is not supported\n", 360326119c9SAndreas Fenkart mmc_pdata(host)->ocr_mask); 361326119c9SAndreas Fenkart mmc_pdata(host)->ocr_mask = 0; 36264be9782Skishore kadiyala return -EINVAL; 36364be9782Skishore kadiyala } 36464be9782Skishore kadiyala } 365987fd49bSBalaji T K } 366326119c9SAndreas Fenkart mmc_pdata(host)->set_power = omap_hsmmc_set_power; 367db0fefc5SAdrian Hunter 368db0fefc5SAdrian Hunter /* Allow an aux regulator */ 369f2ddc1daSBalaji T K reg = devm_regulator_get_optional(host->dev, "vmmc_aux"); 370db0fefc5SAdrian Hunter host->vcc_aux = IS_ERR(reg) ? NULL : reg; 371db0fefc5SAdrian Hunter 372e99448ffSBalaji T K reg = devm_regulator_get_optional(host->dev, "pbias"); 373e99448ffSBalaji T K host->pbias = IS_ERR(reg) ? NULL : reg; 374e99448ffSBalaji T K 375b1c1df7aSBalaji T K /* For eMMC do not power off when not in sleep state */ 376326119c9SAndreas Fenkart if (mmc_pdata(host)->no_regulator_off_init) 377b1c1df7aSBalaji T K return 0; 378db0fefc5SAdrian Hunter /* 379987fd49bSBalaji T K * To disable boot_on regulator, enable regulator 380987fd49bSBalaji T K * to increase usecount and then disable it. 381db0fefc5SAdrian Hunter */ 382987fd49bSBalaji T K if ((host->vcc && regulator_is_enabled(host->vcc) > 0) || 383e840ce13SAdrian Hunter (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) { 384326119c9SAndreas Fenkart int vdd = ffs(mmc_pdata(host)->ocr_mask) - 1; 385e840ce13SAdrian Hunter 38680412ca8SAndreas Fenkart mmc_pdata(host)->set_power(host->dev, 1, vdd); 38780412ca8SAndreas Fenkart mmc_pdata(host)->set_power(host->dev, 0, 0); 388db0fefc5SAdrian Hunter } 389db0fefc5SAdrian Hunter 390db0fefc5SAdrian Hunter return 0; 391db0fefc5SAdrian Hunter } 392db0fefc5SAdrian Hunter 393db0fefc5SAdrian Hunter static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 394db0fefc5SAdrian Hunter { 395326119c9SAndreas Fenkart mmc_pdata(host)->set_power = NULL; 396db0fefc5SAdrian Hunter } 397db0fefc5SAdrian Hunter 398b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 399b702b106SAdrian Hunter { 400b702b106SAdrian Hunter return 1; 401b702b106SAdrian Hunter } 402b702b106SAdrian Hunter 403b702b106SAdrian Hunter #else 404b702b106SAdrian Hunter 405b702b106SAdrian Hunter static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 406b702b106SAdrian Hunter { 407b702b106SAdrian Hunter return -EINVAL; 408b702b106SAdrian Hunter } 409b702b106SAdrian Hunter 410b702b106SAdrian Hunter static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 411b702b106SAdrian Hunter { 412b702b106SAdrian Hunter } 413b702b106SAdrian Hunter 414b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 415b702b106SAdrian Hunter { 416b702b106SAdrian Hunter return 0; 417b702b106SAdrian Hunter } 418b702b106SAdrian Hunter 419b702b106SAdrian Hunter #endif 420b702b106SAdrian Hunter 42141afa314SNeilBrown static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id); 422cde592cbSAndreas Fenkart static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id); 42341afa314SNeilBrown 42441afa314SNeilBrown static int omap_hsmmc_gpio_init(struct mmc_host *mmc, 42541afa314SNeilBrown struct omap_hsmmc_host *host, 4261e363e3bSAndreas Fenkart struct omap_hsmmc_platform_data *pdata) 427b702b106SAdrian Hunter { 428b702b106SAdrian Hunter int ret; 429b702b106SAdrian Hunter 430cde592cbSAndreas Fenkart if (pdata->cover && gpio_is_valid(pdata->switch_pin)) { 43141afa314SNeilBrown ret = mmc_gpio_request_cd(mmc, pdata->switch_pin, 0); 432b702b106SAdrian Hunter if (ret) 433b702b106SAdrian Hunter return ret; 434cde592cbSAndreas Fenkart 435cde592cbSAndreas Fenkart host->get_cover_state = omap_hsmmc_get_cover_state; 436cde592cbSAndreas Fenkart mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq); 437cde592cbSAndreas Fenkart } else if (!pdata->cover && gpio_is_valid(pdata->switch_pin)) { 438cde592cbSAndreas Fenkart ret = mmc_gpio_request_cd(mmc, pdata->switch_pin, 0); 439cde592cbSAndreas Fenkart if (ret) 440cde592cbSAndreas Fenkart return ret; 441cde592cbSAndreas Fenkart 442cde592cbSAndreas Fenkart host->card_detect = omap_hsmmc_card_detect; 443cde592cbSAndreas Fenkart mmc_gpio_set_cd_isr(mmc, omap_hsmmc_detect); 444326119c9SAndreas Fenkart } 445b702b106SAdrian Hunter 446326119c9SAndreas Fenkart if (gpio_is_valid(pdata->gpio_wp)) { 44741afa314SNeilBrown ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp); 448b702b106SAdrian Hunter if (ret) 44941afa314SNeilBrown return ret; 450326119c9SAndreas Fenkart } 451b702b106SAdrian Hunter 452b702b106SAdrian Hunter return 0; 453b702b106SAdrian Hunter } 454b702b106SAdrian Hunter 455a45c6cb8SMadhusudhan Chikkature /* 456e0c7f99bSAndy Shevchenko * Start clock to the card 457e0c7f99bSAndy Shevchenko */ 458e0c7f99bSAndy Shevchenko static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 459e0c7f99bSAndy Shevchenko { 460e0c7f99bSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 461e0c7f99bSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 462e0c7f99bSAndy Shevchenko } 463e0c7f99bSAndy Shevchenko 464e0c7f99bSAndy Shevchenko /* 465a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 466a45c6cb8SMadhusudhan Chikkature */ 46770a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 468a45c6cb8SMadhusudhan Chikkature { 469a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 470a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 471a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 4727122bbb0SMasanari Iida dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); 473a45c6cb8SMadhusudhan Chikkature } 474a45c6cb8SMadhusudhan Chikkature 47593caf8e6SAdrian Hunter static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 47693caf8e6SAdrian Hunter struct mmc_command *cmd) 477b417577dSAdrian Hunter { 4782cd3a2a5SAndreas Fenkart u32 irq_mask = INT_EN_MASK; 4792cd3a2a5SAndreas Fenkart unsigned long flags; 480b417577dSAdrian Hunter 481b417577dSAdrian Hunter if (host->use_dma) 4822cd3a2a5SAndreas Fenkart irq_mask &= ~(BRR_EN | BWR_EN); 483b417577dSAdrian Hunter 48493caf8e6SAdrian Hunter /* Disable timeout for erases */ 48593caf8e6SAdrian Hunter if (cmd->opcode == MMC_ERASE) 486a7e96879SVenkatraman S irq_mask &= ~DTO_EN; 48793caf8e6SAdrian Hunter 4882cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 489b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 490b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 4912cd3a2a5SAndreas Fenkart 4922cd3a2a5SAndreas Fenkart /* latch pending CIRQ, but don't signal MMC core */ 4932cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 4942cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 495b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 4962cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 497b417577dSAdrian Hunter } 498b417577dSAdrian Hunter 499b417577dSAdrian Hunter static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 500b417577dSAdrian Hunter { 5012cd3a2a5SAndreas Fenkart u32 irq_mask = 0; 5022cd3a2a5SAndreas Fenkart unsigned long flags; 5032cd3a2a5SAndreas Fenkart 5042cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 5052cd3a2a5SAndreas Fenkart /* no transfer running but need to keep cirq if enabled */ 5062cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 5072cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 5082cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 5092cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 510b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 5112cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 512b417577dSAdrian Hunter } 513b417577dSAdrian Hunter 514ac330f44SAndy Shevchenko /* Calculate divisor for the given clock frequency */ 515d83b6e03SBalaji TK static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 516ac330f44SAndy Shevchenko { 517ac330f44SAndy Shevchenko u16 dsor = 0; 518ac330f44SAndy Shevchenko 519ac330f44SAndy Shevchenko if (ios->clock) { 520d83b6e03SBalaji TK dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 521ed164182SBalaji T K if (dsor > CLKD_MAX) 522ed164182SBalaji T K dsor = CLKD_MAX; 523ac330f44SAndy Shevchenko } 524ac330f44SAndy Shevchenko 525ac330f44SAndy Shevchenko return dsor; 526ac330f44SAndy Shevchenko } 527ac330f44SAndy Shevchenko 5285934df2fSAndy Shevchenko static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 5295934df2fSAndy Shevchenko { 5305934df2fSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5315934df2fSAndy Shevchenko unsigned long regval; 5325934df2fSAndy Shevchenko unsigned long timeout; 533cd587096SHebbar, Gururaja unsigned long clkdiv; 5345934df2fSAndy Shevchenko 5358986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 5365934df2fSAndy Shevchenko 5375934df2fSAndy Shevchenko omap_hsmmc_stop_clock(host); 5385934df2fSAndy Shevchenko 5395934df2fSAndy Shevchenko regval = OMAP_HSMMC_READ(host->base, SYSCTL); 5405934df2fSAndy Shevchenko regval = regval & ~(CLKD_MASK | DTO_MASK); 541cd587096SHebbar, Gururaja clkdiv = calc_divisor(host, ios); 542cd587096SHebbar, Gururaja regval = regval | (clkdiv << 6) | (DTO << 16); 5435934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 5445934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 5455934df2fSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 5465934df2fSAndy Shevchenko 5475934df2fSAndy Shevchenko /* Wait till the ICS bit is set */ 5485934df2fSAndy Shevchenko timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 5495934df2fSAndy Shevchenko while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 5505934df2fSAndy Shevchenko && time_before(jiffies, timeout)) 5515934df2fSAndy Shevchenko cpu_relax(); 5525934df2fSAndy Shevchenko 553cd587096SHebbar, Gururaja /* 554cd587096SHebbar, Gururaja * Enable High-Speed Support 555cd587096SHebbar, Gururaja * Pre-Requisites 556cd587096SHebbar, Gururaja * - Controller should support High-Speed-Enable Bit 557cd587096SHebbar, Gururaja * - Controller should not be using DDR Mode 558cd587096SHebbar, Gururaja * - Controller should advertise that it supports High Speed 559cd587096SHebbar, Gururaja * in capabilities register 560cd587096SHebbar, Gururaja * - MMC/SD clock coming out of controller > 25MHz 561cd587096SHebbar, Gururaja */ 562326119c9SAndreas Fenkart if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) && 5635438ad95SSeungwon Jeon (ios->timing != MMC_TIMING_MMC_DDR52) && 564903101a8SUlf Hansson (ios->timing != MMC_TIMING_UHS_DDR50) && 565cd587096SHebbar, Gururaja ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 566cd587096SHebbar, Gururaja regval = OMAP_HSMMC_READ(host->base, HCTL); 567cd587096SHebbar, Gururaja if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 568cd587096SHebbar, Gururaja regval |= HSPE; 569cd587096SHebbar, Gururaja else 570cd587096SHebbar, Gururaja regval &= ~HSPE; 571cd587096SHebbar, Gururaja 572cd587096SHebbar, Gururaja OMAP_HSMMC_WRITE(host->base, HCTL, regval); 573cd587096SHebbar, Gururaja } 574cd587096SHebbar, Gururaja 5755934df2fSAndy Shevchenko omap_hsmmc_start_clock(host); 5765934df2fSAndy Shevchenko } 5775934df2fSAndy Shevchenko 5783796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 5793796fb8aSAndy Shevchenko { 5803796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5813796fb8aSAndy Shevchenko u32 con; 5823796fb8aSAndy Shevchenko 5833796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 584903101a8SUlf Hansson if (ios->timing == MMC_TIMING_MMC_DDR52 || 585903101a8SUlf Hansson ios->timing == MMC_TIMING_UHS_DDR50) 58603b5d924SBalaji T K con |= DDR; /* configure in DDR mode */ 58703b5d924SBalaji T K else 58803b5d924SBalaji T K con &= ~DDR; 5893796fb8aSAndy Shevchenko switch (ios->bus_width) { 5903796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_8: 5913796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 5923796fb8aSAndy Shevchenko break; 5933796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_4: 5943796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 5953796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 5963796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 5973796fb8aSAndy Shevchenko break; 5983796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_1: 5993796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 6003796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 6013796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 6023796fb8aSAndy Shevchenko break; 6033796fb8aSAndy Shevchenko } 6043796fb8aSAndy Shevchenko } 6053796fb8aSAndy Shevchenko 6063796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 6073796fb8aSAndy Shevchenko { 6083796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6093796fb8aSAndy Shevchenko u32 con; 6103796fb8aSAndy Shevchenko 6113796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 6123796fb8aSAndy Shevchenko if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 6133796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | OD); 6143796fb8aSAndy Shevchenko else 6153796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 6163796fb8aSAndy Shevchenko } 6173796fb8aSAndy Shevchenko 61811dd62a7SDenis Karpov #ifdef CONFIG_PM 61911dd62a7SDenis Karpov 62011dd62a7SDenis Karpov /* 62111dd62a7SDenis Karpov * Restore the MMC host context, if it was lost as result of a 62211dd62a7SDenis Karpov * power state change. 62311dd62a7SDenis Karpov */ 62470a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 62511dd62a7SDenis Karpov { 62611dd62a7SDenis Karpov struct mmc_ios *ios = &host->mmc->ios; 6273796fb8aSAndy Shevchenko u32 hctl, capa; 62811dd62a7SDenis Karpov unsigned long timeout; 62911dd62a7SDenis Karpov 6300a82e06eSTony Lindgren if (host->con == OMAP_HSMMC_READ(host->base, CON) && 6310a82e06eSTony Lindgren host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && 6320a82e06eSTony Lindgren host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && 6330a82e06eSTony Lindgren host->capa == OMAP_HSMMC_READ(host->base, CAPA)) 6340a82e06eSTony Lindgren return 0; 6350a82e06eSTony Lindgren 6360a82e06eSTony Lindgren host->context_loss++; 6370a82e06eSTony Lindgren 638c2200efbSBalaji T K if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 63911dd62a7SDenis Karpov if (host->power_mode != MMC_POWER_OFF && 64011dd62a7SDenis Karpov (1 << ios->vdd) <= MMC_VDD_23_24) 64111dd62a7SDenis Karpov hctl = SDVS18; 64211dd62a7SDenis Karpov else 64311dd62a7SDenis Karpov hctl = SDVS30; 64411dd62a7SDenis Karpov capa = VS30 | VS18; 64511dd62a7SDenis Karpov } else { 64611dd62a7SDenis Karpov hctl = SDVS18; 64711dd62a7SDenis Karpov capa = VS18; 64811dd62a7SDenis Karpov } 64911dd62a7SDenis Karpov 6505a52b08bSBalaji T K if (host->mmc->caps & MMC_CAP_SDIO_IRQ) 6515a52b08bSBalaji T K hctl |= IWE; 6525a52b08bSBalaji T K 65311dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 65411dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | hctl); 65511dd62a7SDenis Karpov 65611dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CAPA, 65711dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA) | capa); 65811dd62a7SDenis Karpov 65911dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 66011dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 66111dd62a7SDenis Karpov 66211dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 66311dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 66411dd62a7SDenis Karpov && time_before(jiffies, timeout)) 66511dd62a7SDenis Karpov ; 66611dd62a7SDenis Karpov 6672cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 6682cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 6692cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 67011dd62a7SDenis Karpov 67111dd62a7SDenis Karpov /* Do not initialize card-specific things if the power is off */ 67211dd62a7SDenis Karpov if (host->power_mode == MMC_POWER_OFF) 67311dd62a7SDenis Karpov goto out; 67411dd62a7SDenis Karpov 6753796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 67611dd62a7SDenis Karpov 6775934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 67811dd62a7SDenis Karpov 6793796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 6803796fb8aSAndy Shevchenko 68111dd62a7SDenis Karpov out: 6820a82e06eSTony Lindgren dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", 6830a82e06eSTony Lindgren host->context_loss); 68411dd62a7SDenis Karpov return 0; 68511dd62a7SDenis Karpov } 68611dd62a7SDenis Karpov 68711dd62a7SDenis Karpov /* 68811dd62a7SDenis Karpov * Save the MMC host context (store the number of power state changes so far). 68911dd62a7SDenis Karpov */ 69070a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 69111dd62a7SDenis Karpov { 6920a82e06eSTony Lindgren host->con = OMAP_HSMMC_READ(host->base, CON); 6930a82e06eSTony Lindgren host->hctl = OMAP_HSMMC_READ(host->base, HCTL); 6940a82e06eSTony Lindgren host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); 6950a82e06eSTony Lindgren host->capa = OMAP_HSMMC_READ(host->base, CAPA); 69611dd62a7SDenis Karpov } 69711dd62a7SDenis Karpov 69811dd62a7SDenis Karpov #else 69911dd62a7SDenis Karpov 70070a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 70111dd62a7SDenis Karpov { 70211dd62a7SDenis Karpov return 0; 70311dd62a7SDenis Karpov } 70411dd62a7SDenis Karpov 70570a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 70611dd62a7SDenis Karpov { 70711dd62a7SDenis Karpov } 70811dd62a7SDenis Karpov 70911dd62a7SDenis Karpov #endif 71011dd62a7SDenis Karpov 711a45c6cb8SMadhusudhan Chikkature /* 712a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 713a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 714a45c6cb8SMadhusudhan Chikkature */ 71570a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host) 716a45c6cb8SMadhusudhan Chikkature { 717a45c6cb8SMadhusudhan Chikkature int reg = 0; 718a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 719a45c6cb8SMadhusudhan Chikkature 720b62f6228SAdrian Hunter if (host->protect_card) 721b62f6228SAdrian Hunter return; 722b62f6228SAdrian Hunter 723a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 724b417577dSAdrian Hunter 725b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 726a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 727a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 728a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 729a45c6cb8SMadhusudhan Chikkature 730a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 731a7e96879SVenkatraman S while ((reg != CC_EN) && time_before(jiffies, timeout)) 732a7e96879SVenkatraman S reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; 733a45c6cb8SMadhusudhan Chikkature 734a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 735a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 736c653a6d4SAdrian Hunter 737c653a6d4SAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 738c653a6d4SAdrian Hunter OMAP_HSMMC_READ(host->base, STAT); 739c653a6d4SAdrian Hunter 740a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 741a45c6cb8SMadhusudhan Chikkature } 742a45c6cb8SMadhusudhan Chikkature 743a45c6cb8SMadhusudhan Chikkature static inline 74470a3341aSDenis Karpov int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 745a45c6cb8SMadhusudhan Chikkature { 746a45c6cb8SMadhusudhan Chikkature int r = 1; 747a45c6cb8SMadhusudhan Chikkature 748b5cd43f0SAndreas Fenkart if (host->get_cover_state) 74980412ca8SAndreas Fenkart r = host->get_cover_state(host->dev); 750a45c6cb8SMadhusudhan Chikkature return r; 751a45c6cb8SMadhusudhan Chikkature } 752a45c6cb8SMadhusudhan Chikkature 753a45c6cb8SMadhusudhan Chikkature static ssize_t 75470a3341aSDenis Karpov omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 755a45c6cb8SMadhusudhan Chikkature char *buf) 756a45c6cb8SMadhusudhan Chikkature { 757a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 75870a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 759a45c6cb8SMadhusudhan Chikkature 76070a3341aSDenis Karpov return sprintf(buf, "%s\n", 76170a3341aSDenis Karpov omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 762a45c6cb8SMadhusudhan Chikkature } 763a45c6cb8SMadhusudhan Chikkature 76470a3341aSDenis Karpov static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 765a45c6cb8SMadhusudhan Chikkature 766a45c6cb8SMadhusudhan Chikkature static ssize_t 76770a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 768a45c6cb8SMadhusudhan Chikkature char *buf) 769a45c6cb8SMadhusudhan Chikkature { 770a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 77170a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 772a45c6cb8SMadhusudhan Chikkature 773326119c9SAndreas Fenkart return sprintf(buf, "%s\n", mmc_pdata(host)->name); 774a45c6cb8SMadhusudhan Chikkature } 775a45c6cb8SMadhusudhan Chikkature 77670a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 777a45c6cb8SMadhusudhan Chikkature 778a45c6cb8SMadhusudhan Chikkature /* 779a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 780a45c6cb8SMadhusudhan Chikkature */ 781a45c6cb8SMadhusudhan Chikkature static void 78270a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 783a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 784a45c6cb8SMadhusudhan Chikkature { 785a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 786a45c6cb8SMadhusudhan Chikkature 7878986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 788a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 789a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 790a45c6cb8SMadhusudhan Chikkature 79193caf8e6SAdrian Hunter omap_hsmmc_enable_irq(host, cmd); 792a45c6cb8SMadhusudhan Chikkature 7934a694dc9SAdrian Hunter host->response_busy = 0; 794a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 795a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 796a45c6cb8SMadhusudhan Chikkature resptype = 1; 7974a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 7984a694dc9SAdrian Hunter resptype = 3; 7994a694dc9SAdrian Hunter host->response_busy = 1; 8004a694dc9SAdrian Hunter } else 801a45c6cb8SMadhusudhan Chikkature resptype = 2; 802a45c6cb8SMadhusudhan Chikkature } 803a45c6cb8SMadhusudhan Chikkature 804a45c6cb8SMadhusudhan Chikkature /* 805a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 806a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 807a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 808a45c6cb8SMadhusudhan Chikkature */ 809a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 810a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 811a45c6cb8SMadhusudhan Chikkature 812a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 813a45c6cb8SMadhusudhan Chikkature 814a2e77152SBalaji T K if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) && 815a2e77152SBalaji T K host->mrq->sbc) { 816a2e77152SBalaji T K cmdreg |= ACEN_ACMD23; 817a2e77152SBalaji T K OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg); 818a2e77152SBalaji T K } 819a45c6cb8SMadhusudhan Chikkature if (data) { 820a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 821a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 822a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 823a45c6cb8SMadhusudhan Chikkature else 824a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 825a45c6cb8SMadhusudhan Chikkature } 826a45c6cb8SMadhusudhan Chikkature 827a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 828a7e96879SVenkatraman S cmdreg |= DMAE; 829a45c6cb8SMadhusudhan Chikkature 830b417577dSAdrian Hunter host->req_in_progress = 1; 8314dffd7a2SAdrian Hunter 832a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 833a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 834a45c6cb8SMadhusudhan Chikkature } 835a45c6cb8SMadhusudhan Chikkature 8360ccd76d4SJuha Yrjola static int 83770a3341aSDenis Karpov omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 8380ccd76d4SJuha Yrjola { 8390ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) 8400ccd76d4SJuha Yrjola return DMA_TO_DEVICE; 8410ccd76d4SJuha Yrjola else 8420ccd76d4SJuha Yrjola return DMA_FROM_DEVICE; 8430ccd76d4SJuha Yrjola } 8440ccd76d4SJuha Yrjola 845c5c98927SRussell King static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 846c5c98927SRussell King struct mmc_data *data) 847c5c98927SRussell King { 848c5c98927SRussell King return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 849c5c98927SRussell King } 850c5c98927SRussell King 851b417577dSAdrian Hunter static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 852b417577dSAdrian Hunter { 853b417577dSAdrian Hunter int dma_ch; 85431463b14SVenkatraman S unsigned long flags; 855b417577dSAdrian Hunter 85631463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 857b417577dSAdrian Hunter host->req_in_progress = 0; 858b417577dSAdrian Hunter dma_ch = host->dma_ch; 85931463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 860b417577dSAdrian Hunter 861b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 862b417577dSAdrian Hunter /* Do not complete the request if DMA is still in progress */ 863b417577dSAdrian Hunter if (mrq->data && host->use_dma && dma_ch != -1) 864b417577dSAdrian Hunter return; 865b417577dSAdrian Hunter host->mrq = NULL; 866b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 867b417577dSAdrian Hunter } 868b417577dSAdrian Hunter 869a45c6cb8SMadhusudhan Chikkature /* 870a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 871a45c6cb8SMadhusudhan Chikkature */ 872a45c6cb8SMadhusudhan Chikkature static void 87370a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 874a45c6cb8SMadhusudhan Chikkature { 8754a694dc9SAdrian Hunter if (!data) { 8764a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 8774a694dc9SAdrian Hunter 87823050103SAdrian Hunter /* TC before CC from CMD6 - don't know why, but it happens */ 87923050103SAdrian Hunter if (host->cmd && host->cmd->opcode == 6 && 88023050103SAdrian Hunter host->response_busy) { 88123050103SAdrian Hunter host->response_busy = 0; 88223050103SAdrian Hunter return; 88323050103SAdrian Hunter } 88423050103SAdrian Hunter 885b417577dSAdrian Hunter omap_hsmmc_request_done(host, mrq); 8864a694dc9SAdrian Hunter return; 8874a694dc9SAdrian Hunter } 8884a694dc9SAdrian Hunter 889a45c6cb8SMadhusudhan Chikkature host->data = NULL; 890a45c6cb8SMadhusudhan Chikkature 891a45c6cb8SMadhusudhan Chikkature if (!data->error) 892a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 893a45c6cb8SMadhusudhan Chikkature else 894a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 895a45c6cb8SMadhusudhan Chikkature 896bf129e1cSBalaji T K if (data->stop && (data->error || !host->mrq->sbc)) 897fe852273SMing Lei omap_hsmmc_start_command(host, data->stop, NULL); 898bf129e1cSBalaji T K else 899bf129e1cSBalaji T K omap_hsmmc_request_done(host, data->mrq); 900a45c6cb8SMadhusudhan Chikkature } 901a45c6cb8SMadhusudhan Chikkature 902a45c6cb8SMadhusudhan Chikkature /* 903a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 904a45c6cb8SMadhusudhan Chikkature */ 905a45c6cb8SMadhusudhan Chikkature static void 90670a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 907a45c6cb8SMadhusudhan Chikkature { 908bf129e1cSBalaji T K if (host->mrq->sbc && (host->cmd == host->mrq->sbc) && 909a2e77152SBalaji T K !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) { 9102177fa94SBalaji T K host->cmd = NULL; 911bf129e1cSBalaji T K omap_hsmmc_start_dma_transfer(host); 912bf129e1cSBalaji T K omap_hsmmc_start_command(host, host->mrq->cmd, 913bf129e1cSBalaji T K host->mrq->data); 914bf129e1cSBalaji T K return; 915bf129e1cSBalaji T K } 916bf129e1cSBalaji T K 9172177fa94SBalaji T K host->cmd = NULL; 9182177fa94SBalaji T K 919a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 920a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 921a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 922a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 923a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 924a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 925a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 926a45c6cb8SMadhusudhan Chikkature } else { 927a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 928a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 929a45c6cb8SMadhusudhan Chikkature } 930a45c6cb8SMadhusudhan Chikkature } 931b417577dSAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) 932d4b2c375SBalaji T K omap_hsmmc_request_done(host, host->mrq); 933a45c6cb8SMadhusudhan Chikkature } 934a45c6cb8SMadhusudhan Chikkature 935a45c6cb8SMadhusudhan Chikkature /* 936a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 937a45c6cb8SMadhusudhan Chikkature */ 93870a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 939a45c6cb8SMadhusudhan Chikkature { 940b417577dSAdrian Hunter int dma_ch; 94131463b14SVenkatraman S unsigned long flags; 942b417577dSAdrian Hunter 94382788ff5SJarkko Lavinen host->data->error = errno; 944a45c6cb8SMadhusudhan Chikkature 94531463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 946b417577dSAdrian Hunter dma_ch = host->dma_ch; 947b417577dSAdrian Hunter host->dma_ch = -1; 94831463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 949b417577dSAdrian Hunter 950b417577dSAdrian Hunter if (host->use_dma && dma_ch != -1) { 951c5c98927SRussell King struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 952c5c98927SRussell King 953c5c98927SRussell King dmaengine_terminate_all(chan); 954c5c98927SRussell King dma_unmap_sg(chan->device->dev, 955c5c98927SRussell King host->data->sg, host->data->sg_len, 95670a3341aSDenis Karpov omap_hsmmc_get_dma_dir(host, host->data)); 957c5c98927SRussell King 958053bf34fSPer Forlin host->data->host_cookie = 0; 959a45c6cb8SMadhusudhan Chikkature } 960a45c6cb8SMadhusudhan Chikkature host->data = NULL; 961a45c6cb8SMadhusudhan Chikkature } 962a45c6cb8SMadhusudhan Chikkature 963a45c6cb8SMadhusudhan Chikkature /* 964a45c6cb8SMadhusudhan Chikkature * Readable error output 965a45c6cb8SMadhusudhan Chikkature */ 966a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 967699b958bSAdrian Hunter static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 968a45c6cb8SMadhusudhan Chikkature { 969a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 97070a3341aSDenis Karpov static const char *omap_hsmmc_status_bits[] = { 971699b958bSAdrian Hunter "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 972699b958bSAdrian Hunter "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 973699b958bSAdrian Hunter "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 974699b958bSAdrian Hunter "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 975a45c6cb8SMadhusudhan Chikkature }; 976a45c6cb8SMadhusudhan Chikkature char res[256]; 977a45c6cb8SMadhusudhan Chikkature char *buf = res; 978a45c6cb8SMadhusudhan Chikkature int len, i; 979a45c6cb8SMadhusudhan Chikkature 980a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 981a45c6cb8SMadhusudhan Chikkature buf += len; 982a45c6cb8SMadhusudhan Chikkature 98370a3341aSDenis Karpov for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 984a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 98570a3341aSDenis Karpov len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 986a45c6cb8SMadhusudhan Chikkature buf += len; 987a45c6cb8SMadhusudhan Chikkature } 988a45c6cb8SMadhusudhan Chikkature 9898986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 990a45c6cb8SMadhusudhan Chikkature } 991699b958bSAdrian Hunter #else 992699b958bSAdrian Hunter static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 993699b958bSAdrian Hunter u32 status) 994699b958bSAdrian Hunter { 995699b958bSAdrian Hunter } 996a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 997a45c6cb8SMadhusudhan Chikkature 9983ebf74b1SJean Pihet /* 9993ebf74b1SJean Pihet * MMC controller internal state machines reset 10003ebf74b1SJean Pihet * 10013ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 10023ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 10033ebf74b1SJean Pihet * Can be called from interrupt context 10043ebf74b1SJean Pihet */ 100570a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 10063ebf74b1SJean Pihet unsigned long bit) 10073ebf74b1SJean Pihet { 10083ebf74b1SJean Pihet unsigned long i = 0; 10091e881786SJianpeng Ma unsigned long limit = MMC_TIMEOUT_US; 10103ebf74b1SJean Pihet 10113ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 10123ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 10133ebf74b1SJean Pihet 101407ad64b6SMadhusudhan Chikkature /* 101507ad64b6SMadhusudhan Chikkature * OMAP4 ES2 and greater has an updated reset logic. 101607ad64b6SMadhusudhan Chikkature * Monitor a 0->1 transition first 101707ad64b6SMadhusudhan Chikkature */ 1018326119c9SAndreas Fenkart if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) { 1019b432b4b3Skishore kadiyala while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 102007ad64b6SMadhusudhan Chikkature && (i++ < limit)) 10211e881786SJianpeng Ma udelay(1); 102207ad64b6SMadhusudhan Chikkature } 102307ad64b6SMadhusudhan Chikkature i = 0; 102407ad64b6SMadhusudhan Chikkature 10253ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 10263ebf74b1SJean Pihet (i++ < limit)) 10271e881786SJianpeng Ma udelay(1); 10283ebf74b1SJean Pihet 10293ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 10303ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 10313ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 10323ebf74b1SJean Pihet __func__); 10333ebf74b1SJean Pihet } 1034a45c6cb8SMadhusudhan Chikkature 103525e1897bSBalaji T K static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, 103625e1897bSBalaji T K int err, int end_cmd) 1037ae4bf788SVenkatraman S { 103825e1897bSBalaji T K if (end_cmd) { 103994d4f272SBalaji T K omap_hsmmc_reset_controller_fsm(host, SRC); 104025e1897bSBalaji T K if (host->cmd) 1041ae4bf788SVenkatraman S host->cmd->error = err; 104225e1897bSBalaji T K } 1043ae4bf788SVenkatraman S 1044ae4bf788SVenkatraman S if (host->data) { 1045ae4bf788SVenkatraman S omap_hsmmc_reset_controller_fsm(host, SRD); 1046ae4bf788SVenkatraman S omap_hsmmc_dma_cleanup(host, err); 1047dc7745bdSBalaji T K } else if (host->mrq && host->mrq->cmd) 1048dc7745bdSBalaji T K host->mrq->cmd->error = err; 1049ae4bf788SVenkatraman S } 1050ae4bf788SVenkatraman S 1051b417577dSAdrian Hunter static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1052a45c6cb8SMadhusudhan Chikkature { 1053a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 1054b417577dSAdrian Hunter int end_cmd = 0, end_trans = 0; 1055a2e77152SBalaji T K int error = 0; 1056a45c6cb8SMadhusudhan Chikkature 1057a45c6cb8SMadhusudhan Chikkature data = host->data; 10588986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1059a45c6cb8SMadhusudhan Chikkature 1060a7e96879SVenkatraman S if (status & ERR_EN) { 1061699b958bSAdrian Hunter omap_hsmmc_dbg_report_irq(host, status); 10624a694dc9SAdrian Hunter 1063a7e96879SVenkatraman S if (status & (CTO_EN | CCRC_EN)) 1064a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1065a7e96879SVenkatraman S if (status & (CTO_EN | DTO_EN)) 106625e1897bSBalaji T K hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); 1067a7e96879SVenkatraman S else if (status & (CCRC_EN | DCRC_EN)) 106825e1897bSBalaji T K hsmmc_command_incomplete(host, -EILSEQ, end_cmd); 106925e1897bSBalaji T K 1070a2e77152SBalaji T K if (status & ACE_EN) { 1071a2e77152SBalaji T K u32 ac12; 1072a2e77152SBalaji T K ac12 = OMAP_HSMMC_READ(host->base, AC12); 1073a2e77152SBalaji T K if (!(ac12 & ACNE) && host->mrq->sbc) { 1074a2e77152SBalaji T K end_cmd = 1; 1075a2e77152SBalaji T K if (ac12 & ACTO) 1076a2e77152SBalaji T K error = -ETIMEDOUT; 1077a2e77152SBalaji T K else if (ac12 & (ACCE | ACEB | ACIE)) 1078a2e77152SBalaji T K error = -EILSEQ; 1079a2e77152SBalaji T K host->mrq->sbc->error = error; 1080a2e77152SBalaji T K hsmmc_command_incomplete(host, error, end_cmd); 1081a2e77152SBalaji T K } 1082a2e77152SBalaji T K dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12); 1083a2e77152SBalaji T K } 1084ae4bf788SVenkatraman S if (host->data || host->response_busy) { 108525e1897bSBalaji T K end_trans = !end_cmd; 1086ae4bf788SVenkatraman S host->response_busy = 0; 1087a45c6cb8SMadhusudhan Chikkature } 1088a45c6cb8SMadhusudhan Chikkature } 1089a45c6cb8SMadhusudhan Chikkature 10907472bab2SFrancesco Lavra OMAP_HSMMC_WRITE(host->base, STAT, status); 1091a7e96879SVenkatraman S if (end_cmd || ((status & CC_EN) && host->cmd)) 109270a3341aSDenis Karpov omap_hsmmc_cmd_done(host, host->cmd); 1093a7e96879SVenkatraman S if ((end_trans || (status & TC_EN)) && host->mrq) 109470a3341aSDenis Karpov omap_hsmmc_xfer_done(host, data); 1095b417577dSAdrian Hunter } 1096a45c6cb8SMadhusudhan Chikkature 1097b417577dSAdrian Hunter /* 1098b417577dSAdrian Hunter * MMC controller IRQ handler 1099b417577dSAdrian Hunter */ 1100b417577dSAdrian Hunter static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1101b417577dSAdrian Hunter { 1102b417577dSAdrian Hunter struct omap_hsmmc_host *host = dev_id; 1103b417577dSAdrian Hunter int status; 1104b417577dSAdrian Hunter 1105b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 11062cd3a2a5SAndreas Fenkart while (status & (INT_EN_MASK | CIRQ_EN)) { 11072cd3a2a5SAndreas Fenkart if (host->req_in_progress) 1108b417577dSAdrian Hunter omap_hsmmc_do_irq(host, status); 11091f6b9fa4SVenkatraman S 11102cd3a2a5SAndreas Fenkart if (status & CIRQ_EN) 11112cd3a2a5SAndreas Fenkart mmc_signal_sdio_irq(host->mmc); 11122cd3a2a5SAndreas Fenkart 1113b417577dSAdrian Hunter /* Flush posted write */ 1114b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 11151f6b9fa4SVenkatraman S } 11164dffd7a2SAdrian Hunter 1117a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1118a45c6cb8SMadhusudhan Chikkature } 1119a45c6cb8SMadhusudhan Chikkature 11202cd3a2a5SAndreas Fenkart static irqreturn_t omap_hsmmc_wake_irq(int irq, void *dev_id) 11212cd3a2a5SAndreas Fenkart { 11222cd3a2a5SAndreas Fenkart struct omap_hsmmc_host *host = dev_id; 11232cd3a2a5SAndreas Fenkart 11242cd3a2a5SAndreas Fenkart /* cirq is level triggered, disable to avoid infinite loop */ 11252cd3a2a5SAndreas Fenkart spin_lock(&host->irq_lock); 11262cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_WAKE_IRQ_ENABLED) { 11272cd3a2a5SAndreas Fenkart disable_irq_nosync(host->wake_irq); 11282cd3a2a5SAndreas Fenkart host->flags &= ~HSMMC_WAKE_IRQ_ENABLED; 11292cd3a2a5SAndreas Fenkart } 11302cd3a2a5SAndreas Fenkart spin_unlock(&host->irq_lock); 11312cd3a2a5SAndreas Fenkart pm_request_resume(host->dev); /* no use counter */ 11322cd3a2a5SAndreas Fenkart 11332cd3a2a5SAndreas Fenkart return IRQ_HANDLED; 11342cd3a2a5SAndreas Fenkart } 11352cd3a2a5SAndreas Fenkart 113670a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host) 1137e13bb300SAdrian Hunter { 1138e13bb300SAdrian Hunter unsigned long i; 1139e13bb300SAdrian Hunter 1140e13bb300SAdrian Hunter OMAP_HSMMC_WRITE(host->base, HCTL, 1141e13bb300SAdrian Hunter OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1142e13bb300SAdrian Hunter for (i = 0; i < loops_per_jiffy; i++) { 1143e13bb300SAdrian Hunter if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1144e13bb300SAdrian Hunter break; 1145e13bb300SAdrian Hunter cpu_relax(); 1146e13bb300SAdrian Hunter } 1147e13bb300SAdrian Hunter } 1148e13bb300SAdrian Hunter 1149a45c6cb8SMadhusudhan Chikkature /* 1150eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 1151eb250826SDavid Brownell * 1152eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1153eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1154eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 1155a45c6cb8SMadhusudhan Chikkature */ 115670a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1157a45c6cb8SMadhusudhan Chikkature { 1158a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 1159a45c6cb8SMadhusudhan Chikkature int ret; 1160a45c6cb8SMadhusudhan Chikkature 1161a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 1162fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 1163cd03d9a8SRajendra Nayak if (host->dbclk) 116494c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 1165a45c6cb8SMadhusudhan Chikkature 1166a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 116780412ca8SAndreas Fenkart ret = mmc_pdata(host)->set_power(host->dev, 0, 0); 1168a45c6cb8SMadhusudhan Chikkature 1169a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 11702bec0893SAdrian Hunter if (!ret) 117180412ca8SAndreas Fenkart ret = mmc_pdata(host)->set_power(host->dev, 1, vdd); 1172fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1173cd03d9a8SRajendra Nayak if (host->dbclk) 117494c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 11752bec0893SAdrian Hunter 1176a45c6cb8SMadhusudhan Chikkature if (ret != 0) 1177a45c6cb8SMadhusudhan Chikkature goto err; 1178a45c6cb8SMadhusudhan Chikkature 1179a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1180a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1181a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1182eb250826SDavid Brownell 1183a45c6cb8SMadhusudhan Chikkature /* 1184a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 1185a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 118670a3341aSDenis Karpov * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1187a45c6cb8SMadhusudhan Chikkature * 1188eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 1189eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1190eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 1191eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1192eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 1193eb250826SDavid Brownell * 1194eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 1195eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1196eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1197a45c6cb8SMadhusudhan Chikkature */ 1198eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 1199a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 1200eb250826SDavid Brownell else 1201eb250826SDavid Brownell reg_val |= SDVS30; 1202a45c6cb8SMadhusudhan Chikkature 1203a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1204e13bb300SAdrian Hunter set_sd_bus_power(host); 1205a45c6cb8SMadhusudhan Chikkature 1206a45c6cb8SMadhusudhan Chikkature return 0; 1207a45c6cb8SMadhusudhan Chikkature err: 1208b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1209a45c6cb8SMadhusudhan Chikkature return ret; 1210a45c6cb8SMadhusudhan Chikkature } 1211a45c6cb8SMadhusudhan Chikkature 1212b62f6228SAdrian Hunter /* Protect the card while the cover is open */ 1213b62f6228SAdrian Hunter static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1214b62f6228SAdrian Hunter { 1215b5cd43f0SAndreas Fenkart if (!host->get_cover_state) 1216b62f6228SAdrian Hunter return; 1217b62f6228SAdrian Hunter 1218b62f6228SAdrian Hunter host->reqs_blocked = 0; 121980412ca8SAndreas Fenkart if (host->get_cover_state(host->dev)) { 1220b62f6228SAdrian Hunter if (host->protect_card) { 12212cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is closed, " 1222b62f6228SAdrian Hunter "card is now accessible\n", 1223b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1224b62f6228SAdrian Hunter host->protect_card = 0; 1225b62f6228SAdrian Hunter } 1226b62f6228SAdrian Hunter } else { 1227b62f6228SAdrian Hunter if (!host->protect_card) { 12282cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is open, " 1229b62f6228SAdrian Hunter "card is now inaccessible\n", 1230b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1231b62f6228SAdrian Hunter host->protect_card = 1; 1232b62f6228SAdrian Hunter } 1233b62f6228SAdrian Hunter } 1234b62f6228SAdrian Hunter } 1235b62f6228SAdrian Hunter 1236a45c6cb8SMadhusudhan Chikkature /* 1237cde592cbSAndreas Fenkart * irq handler when (cell-phone) cover is mounted/removed 1238cde592cbSAndreas Fenkart */ 1239cde592cbSAndreas Fenkart static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id) 1240cde592cbSAndreas Fenkart { 1241cde592cbSAndreas Fenkart struct omap_hsmmc_host *host = dev_id; 1242cde592cbSAndreas Fenkart int carddetect; 1243cde592cbSAndreas Fenkart 1244cde592cbSAndreas Fenkart sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1245cde592cbSAndreas Fenkart 1246cde592cbSAndreas Fenkart if (host->card_detect) { 1247cde592cbSAndreas Fenkart carddetect = host->card_detect(host->dev); 1248cde592cbSAndreas Fenkart } else { 1249cde592cbSAndreas Fenkart omap_hsmmc_protect_card(host); 1250cde592cbSAndreas Fenkart carddetect = -ENOSYS; 1251cde592cbSAndreas Fenkart } 1252cde592cbSAndreas Fenkart 1253cde592cbSAndreas Fenkart if (carddetect) 1254cde592cbSAndreas Fenkart mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1255cde592cbSAndreas Fenkart else 1256cde592cbSAndreas Fenkart mmc_detect_change(host->mmc, (HZ * 50) / 1000); 1257cde592cbSAndreas Fenkart return IRQ_HANDLED; 1258cde592cbSAndreas Fenkart } 1259cde592cbSAndreas Fenkart 1260cde592cbSAndreas Fenkart /* 12617efab4f3SNeilBrown * irq handler to notify the core about card insertion/removal 1262a45c6cb8SMadhusudhan Chikkature */ 12637efab4f3SNeilBrown static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id) 1264a45c6cb8SMadhusudhan Chikkature { 12657efab4f3SNeilBrown struct omap_hsmmc_host *host = dev_id; 1266a6b2240dSAdrian Hunter int carddetect; 1267249d0fa9SDavid Brownell 1268b5cd43f0SAndreas Fenkart if (host->card_detect) 126980412ca8SAndreas Fenkart carddetect = host->card_detect(host->dev); 1270b62f6228SAdrian Hunter else { 1271b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 1272a6b2240dSAdrian Hunter carddetect = -ENOSYS; 1273b62f6228SAdrian Hunter } 1274a6b2240dSAdrian Hunter 1275cdeebaddSMadhusudhan Chikkature if (carddetect) 1276a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1277cdeebaddSMadhusudhan Chikkature else 1278a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 50) / 1000); 1279a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1280a45c6cb8SMadhusudhan Chikkature } 1281a45c6cb8SMadhusudhan Chikkature 1282c5c98927SRussell King static void omap_hsmmc_dma_callback(void *param) 12830ccd76d4SJuha Yrjola { 1284c5c98927SRussell King struct omap_hsmmc_host *host = param; 1285c5c98927SRussell King struct dma_chan *chan; 1286770d7432SAdrian Hunter struct mmc_data *data; 1287c5c98927SRussell King int req_in_progress; 1288a45c6cb8SMadhusudhan Chikkature 1289c5c98927SRussell King spin_lock_irq(&host->irq_lock); 1290b417577dSAdrian Hunter if (host->dma_ch < 0) { 1291c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1292a45c6cb8SMadhusudhan Chikkature return; 1293b417577dSAdrian Hunter } 1294a45c6cb8SMadhusudhan Chikkature 1295770d7432SAdrian Hunter data = host->mrq->data; 1296c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 12979782aff8SPer Forlin if (!data->host_cookie) 1298c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1299c5c98927SRussell King data->sg, data->sg_len, 1300b417577dSAdrian Hunter omap_hsmmc_get_dma_dir(host, data)); 1301b417577dSAdrian Hunter 1302b417577dSAdrian Hunter req_in_progress = host->req_in_progress; 1303a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1304c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1305b417577dSAdrian Hunter 1306b417577dSAdrian Hunter /* If DMA has finished after TC, complete the request */ 1307b417577dSAdrian Hunter if (!req_in_progress) { 1308b417577dSAdrian Hunter struct mmc_request *mrq = host->mrq; 1309b417577dSAdrian Hunter 1310b417577dSAdrian Hunter host->mrq = NULL; 1311b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 1312b417577dSAdrian Hunter } 1313a45c6cb8SMadhusudhan Chikkature } 1314a45c6cb8SMadhusudhan Chikkature 13159782aff8SPer Forlin static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 13169782aff8SPer Forlin struct mmc_data *data, 1317c5c98927SRussell King struct omap_hsmmc_next *next, 131826b88520SRussell King struct dma_chan *chan) 13199782aff8SPer Forlin { 13209782aff8SPer Forlin int dma_len; 13219782aff8SPer Forlin 13229782aff8SPer Forlin if (!next && data->host_cookie && 13239782aff8SPer Forlin data->host_cookie != host->next_data.cookie) { 13242cecdf00SRajendra Nayak dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 13259782aff8SPer Forlin " host->next_data.cookie %d\n", 13269782aff8SPer Forlin __func__, data->host_cookie, host->next_data.cookie); 13279782aff8SPer Forlin data->host_cookie = 0; 13289782aff8SPer Forlin } 13299782aff8SPer Forlin 13309782aff8SPer Forlin /* Check if next job is already prepared */ 1331b38313d6SDan Carpenter if (next || data->host_cookie != host->next_data.cookie) { 133226b88520SRussell King dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 13339782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 13349782aff8SPer Forlin 13359782aff8SPer Forlin } else { 13369782aff8SPer Forlin dma_len = host->next_data.dma_len; 13379782aff8SPer Forlin host->next_data.dma_len = 0; 13389782aff8SPer Forlin } 13399782aff8SPer Forlin 13409782aff8SPer Forlin 13419782aff8SPer Forlin if (dma_len == 0) 13429782aff8SPer Forlin return -EINVAL; 13439782aff8SPer Forlin 13449782aff8SPer Forlin if (next) { 13459782aff8SPer Forlin next->dma_len = dma_len; 13469782aff8SPer Forlin data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 13479782aff8SPer Forlin } else 13489782aff8SPer Forlin host->dma_len = dma_len; 13499782aff8SPer Forlin 13509782aff8SPer Forlin return 0; 13519782aff8SPer Forlin } 13529782aff8SPer Forlin 1353a45c6cb8SMadhusudhan Chikkature /* 1354a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 1355a45c6cb8SMadhusudhan Chikkature */ 13569d025334SBalaji T K static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host, 135770a3341aSDenis Karpov struct mmc_request *req) 1358a45c6cb8SMadhusudhan Chikkature { 135926b88520SRussell King struct dma_slave_config cfg; 136026b88520SRussell King struct dma_async_tx_descriptor *tx; 136126b88520SRussell King int ret = 0, i; 1362a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 1363c5c98927SRussell King struct dma_chan *chan; 1364a45c6cb8SMadhusudhan Chikkature 13650ccd76d4SJuha Yrjola /* Sanity check: all the SG entries must be aligned by block size. */ 1366a3f406f8SJarkko Lavinen for (i = 0; i < data->sg_len; i++) { 13670ccd76d4SJuha Yrjola struct scatterlist *sgl; 13680ccd76d4SJuha Yrjola 13690ccd76d4SJuha Yrjola sgl = data->sg + i; 13700ccd76d4SJuha Yrjola if (sgl->length % data->blksz) 13710ccd76d4SJuha Yrjola return -EINVAL; 13720ccd76d4SJuha Yrjola } 13730ccd76d4SJuha Yrjola if ((data->blksz % 4) != 0) 13740ccd76d4SJuha Yrjola /* REVISIT: The MMC buffer increments only when MSB is written. 13750ccd76d4SJuha Yrjola * Return error for blksz which is non multiple of four. 13760ccd76d4SJuha Yrjola */ 13770ccd76d4SJuha Yrjola return -EINVAL; 13780ccd76d4SJuha Yrjola 1379b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1380a45c6cb8SMadhusudhan Chikkature 1381c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 1382c5c98927SRussell King 1383c5c98927SRussell King cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA; 1384c5c98927SRussell King cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA; 1385c5c98927SRussell King cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1386c5c98927SRussell King cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1387c5c98927SRussell King cfg.src_maxburst = data->blksz / 4; 1388c5c98927SRussell King cfg.dst_maxburst = data->blksz / 4; 1389c5c98927SRussell King 1390c5c98927SRussell King ret = dmaengine_slave_config(chan, &cfg); 13919782aff8SPer Forlin if (ret) 13929782aff8SPer Forlin return ret; 1393a45c6cb8SMadhusudhan Chikkature 139426b88520SRussell King ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1395c5c98927SRussell King if (ret) 1396c5c98927SRussell King return ret; 1397a45c6cb8SMadhusudhan Chikkature 1398c5c98927SRussell King tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1399c5c98927SRussell King data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1400c5c98927SRussell King DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1401c5c98927SRussell King if (!tx) { 1402c5c98927SRussell King dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1403c5c98927SRussell King /* FIXME: cleanup */ 1404c5c98927SRussell King return -1; 1405c5c98927SRussell King } 1406c5c98927SRussell King 1407c5c98927SRussell King tx->callback = omap_hsmmc_dma_callback; 1408c5c98927SRussell King tx->callback_param = host; 1409c5c98927SRussell King 1410c5c98927SRussell King /* Does not fail */ 1411c5c98927SRussell King dmaengine_submit(tx); 1412c5c98927SRussell King 141326b88520SRussell King host->dma_ch = 1; 1414c5c98927SRussell King 1415a45c6cb8SMadhusudhan Chikkature return 0; 1416a45c6cb8SMadhusudhan Chikkature } 1417a45c6cb8SMadhusudhan Chikkature 141870a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host, 1419e2bf08d6SAdrian Hunter unsigned int timeout_ns, 1420e2bf08d6SAdrian Hunter unsigned int timeout_clks) 1421a45c6cb8SMadhusudhan Chikkature { 1422a45c6cb8SMadhusudhan Chikkature unsigned int timeout, cycle_ns; 1423a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 1424a45c6cb8SMadhusudhan Chikkature 1425a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1426a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1427a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 1428a45c6cb8SMadhusudhan Chikkature clkd = 1; 1429a45c6cb8SMadhusudhan Chikkature 14306e3076c2SBalaji T K cycle_ns = 1000000000 / (host->clk_rate / clkd); 1431e2bf08d6SAdrian Hunter timeout = timeout_ns / cycle_ns; 1432e2bf08d6SAdrian Hunter timeout += timeout_clks; 1433a45c6cb8SMadhusudhan Chikkature if (timeout) { 1434a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 1435a45c6cb8SMadhusudhan Chikkature dto += 1; 1436a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1437a45c6cb8SMadhusudhan Chikkature } 1438a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 1439a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1440a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 1441a45c6cb8SMadhusudhan Chikkature dto += 1; 1442a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 1443a45c6cb8SMadhusudhan Chikkature dto -= 13; 1444a45c6cb8SMadhusudhan Chikkature else 1445a45c6cb8SMadhusudhan Chikkature dto = 0; 1446a45c6cb8SMadhusudhan Chikkature if (dto > 14) 1447a45c6cb8SMadhusudhan Chikkature dto = 14; 1448a45c6cb8SMadhusudhan Chikkature } 1449a45c6cb8SMadhusudhan Chikkature 1450a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 1451a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 1452a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1453a45c6cb8SMadhusudhan Chikkature } 1454a45c6cb8SMadhusudhan Chikkature 14559d025334SBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host) 14569d025334SBalaji T K { 14579d025334SBalaji T K struct mmc_request *req = host->mrq; 14589d025334SBalaji T K struct dma_chan *chan; 14599d025334SBalaji T K 14609d025334SBalaji T K if (!req->data) 14619d025334SBalaji T K return; 14629d025334SBalaji T K OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 14639d025334SBalaji T K | (req->data->blocks << 16)); 14649d025334SBalaji T K set_data_timeout(host, req->data->timeout_ns, 14659d025334SBalaji T K req->data->timeout_clks); 14669d025334SBalaji T K chan = omap_hsmmc_get_dma_chan(host, req->data); 14679d025334SBalaji T K dma_async_issue_pending(chan); 14689d025334SBalaji T K } 14699d025334SBalaji T K 1470a45c6cb8SMadhusudhan Chikkature /* 1471a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 1472a45c6cb8SMadhusudhan Chikkature */ 1473a45c6cb8SMadhusudhan Chikkature static int 147470a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1475a45c6cb8SMadhusudhan Chikkature { 1476a45c6cb8SMadhusudhan Chikkature int ret; 1477a45c6cb8SMadhusudhan Chikkature host->data = req->data; 1478a45c6cb8SMadhusudhan Chikkature 1479a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 1480a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 1481e2bf08d6SAdrian Hunter /* 1482e2bf08d6SAdrian Hunter * Set an arbitrary 100ms data timeout for commands with 1483e2bf08d6SAdrian Hunter * busy signal. 1484e2bf08d6SAdrian Hunter */ 1485e2bf08d6SAdrian Hunter if (req->cmd->flags & MMC_RSP_BUSY) 1486e2bf08d6SAdrian Hunter set_data_timeout(host, 100000000U, 0); 1487a45c6cb8SMadhusudhan Chikkature return 0; 1488a45c6cb8SMadhusudhan Chikkature } 1489a45c6cb8SMadhusudhan Chikkature 1490a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 14919d025334SBalaji T K ret = omap_hsmmc_setup_dma_transfer(host, req); 1492a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 1493b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); 1494a45c6cb8SMadhusudhan Chikkature return ret; 1495a45c6cb8SMadhusudhan Chikkature } 1496a45c6cb8SMadhusudhan Chikkature } 1497a45c6cb8SMadhusudhan Chikkature return 0; 1498a45c6cb8SMadhusudhan Chikkature } 1499a45c6cb8SMadhusudhan Chikkature 15009782aff8SPer Forlin static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 15019782aff8SPer Forlin int err) 15029782aff8SPer Forlin { 15039782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15049782aff8SPer Forlin struct mmc_data *data = mrq->data; 15059782aff8SPer Forlin 150626b88520SRussell King if (host->use_dma && data->host_cookie) { 1507c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1508c5c98927SRussell King 150926b88520SRussell King dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 15109782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 15119782aff8SPer Forlin data->host_cookie = 0; 15129782aff8SPer Forlin } 15139782aff8SPer Forlin } 15149782aff8SPer Forlin 15159782aff8SPer Forlin static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 15169782aff8SPer Forlin bool is_first_req) 15179782aff8SPer Forlin { 15189782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15199782aff8SPer Forlin 15209782aff8SPer Forlin if (mrq->data->host_cookie) { 15219782aff8SPer Forlin mrq->data->host_cookie = 0; 15229782aff8SPer Forlin return ; 15239782aff8SPer Forlin } 15249782aff8SPer Forlin 1525c5c98927SRussell King if (host->use_dma) { 1526c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1527c5c98927SRussell King 15289782aff8SPer Forlin if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 152926b88520SRussell King &host->next_data, c)) 15309782aff8SPer Forlin mrq->data->host_cookie = 0; 15319782aff8SPer Forlin } 1532c5c98927SRussell King } 15339782aff8SPer Forlin 1534a45c6cb8SMadhusudhan Chikkature /* 1535a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 1536a45c6cb8SMadhusudhan Chikkature */ 153770a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1538a45c6cb8SMadhusudhan Chikkature { 153970a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1540a3f406f8SJarkko Lavinen int err; 1541a45c6cb8SMadhusudhan Chikkature 1542b417577dSAdrian Hunter BUG_ON(host->req_in_progress); 1543b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1544b62f6228SAdrian Hunter if (host->protect_card) { 1545b62f6228SAdrian Hunter if (host->reqs_blocked < 3) { 1546b62f6228SAdrian Hunter /* 1547b62f6228SAdrian Hunter * Ensure the controller is left in a consistent 1548b62f6228SAdrian Hunter * state by resetting the command and data state 1549b62f6228SAdrian Hunter * machines. 1550b62f6228SAdrian Hunter */ 1551b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRD); 1552b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRC); 1553b62f6228SAdrian Hunter host->reqs_blocked += 1; 1554b62f6228SAdrian Hunter } 1555b62f6228SAdrian Hunter req->cmd->error = -EBADF; 1556b62f6228SAdrian Hunter if (req->data) 1557b62f6228SAdrian Hunter req->data->error = -EBADF; 1558b417577dSAdrian Hunter req->cmd->retries = 0; 1559b62f6228SAdrian Hunter mmc_request_done(mmc, req); 1560b62f6228SAdrian Hunter return; 1561b62f6228SAdrian Hunter } else if (host->reqs_blocked) 1562b62f6228SAdrian Hunter host->reqs_blocked = 0; 1563a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 1564a45c6cb8SMadhusudhan Chikkature host->mrq = req; 15656e3076c2SBalaji T K host->clk_rate = clk_get_rate(host->fclk); 156670a3341aSDenis Karpov err = omap_hsmmc_prepare_data(host, req); 1567a3f406f8SJarkko Lavinen if (err) { 1568a3f406f8SJarkko Lavinen req->cmd->error = err; 1569a3f406f8SJarkko Lavinen if (req->data) 1570a3f406f8SJarkko Lavinen req->data->error = err; 1571a3f406f8SJarkko Lavinen host->mrq = NULL; 1572a3f406f8SJarkko Lavinen mmc_request_done(mmc, req); 1573a3f406f8SJarkko Lavinen return; 1574a3f406f8SJarkko Lavinen } 1575a2e77152SBalaji T K if (req->sbc && !(host->flags & AUTO_CMD23)) { 1576bf129e1cSBalaji T K omap_hsmmc_start_command(host, req->sbc, NULL); 1577bf129e1cSBalaji T K return; 1578bf129e1cSBalaji T K } 1579a3f406f8SJarkko Lavinen 15809d025334SBalaji T K omap_hsmmc_start_dma_transfer(host); 158170a3341aSDenis Karpov omap_hsmmc_start_command(host, req->cmd, req->data); 1582a45c6cb8SMadhusudhan Chikkature } 1583a45c6cb8SMadhusudhan Chikkature 1584a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 158570a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1586a45c6cb8SMadhusudhan Chikkature { 158770a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1588a3621465SAdrian Hunter int do_send_init_stream = 0; 1589a45c6cb8SMadhusudhan Chikkature 1590fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 15915e2ea617SAdrian Hunter 1592a3621465SAdrian Hunter if (ios->power_mode != host->power_mode) { 1593a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 1594a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 159580412ca8SAndreas Fenkart mmc_pdata(host)->set_power(host->dev, 0, 0); 1596a45c6cb8SMadhusudhan Chikkature break; 1597a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 159880412ca8SAndreas Fenkart mmc_pdata(host)->set_power(host->dev, 1, ios->vdd); 1599a45c6cb8SMadhusudhan Chikkature break; 1600a3621465SAdrian Hunter case MMC_POWER_ON: 1601a3621465SAdrian Hunter do_send_init_stream = 1; 1602a3621465SAdrian Hunter break; 1603a3621465SAdrian Hunter } 1604a3621465SAdrian Hunter host->power_mode = ios->power_mode; 1605a45c6cb8SMadhusudhan Chikkature } 1606a45c6cb8SMadhusudhan Chikkature 1607dd498effSDenis Karpov /* FIXME: set registers based only on changes to ios */ 1608dd498effSDenis Karpov 16093796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 1610a45c6cb8SMadhusudhan Chikkature 16114621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1612eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 1613eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 1614eb250826SDavid Brownell */ 1615a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 16162cf171cbSBalaji T K (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1617a45c6cb8SMadhusudhan Chikkature /* 1618a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 1619a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 1620a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 1621a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 1622a45c6cb8SMadhusudhan Chikkature */ 162370a3341aSDenis Karpov if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1624a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1625a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 1626a45c6cb8SMadhusudhan Chikkature } 1627a45c6cb8SMadhusudhan Chikkature } 1628a45c6cb8SMadhusudhan Chikkature 16295934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 1630a45c6cb8SMadhusudhan Chikkature 1631a3621465SAdrian Hunter if (do_send_init_stream) 1632a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 1633a45c6cb8SMadhusudhan Chikkature 16343796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 16355e2ea617SAdrian Hunter 1636fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1637a45c6cb8SMadhusudhan Chikkature } 1638a45c6cb8SMadhusudhan Chikkature 1639a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1640a45c6cb8SMadhusudhan Chikkature { 164170a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1642a45c6cb8SMadhusudhan Chikkature 1643b5cd43f0SAndreas Fenkart if (!host->card_detect) 1644a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 164580412ca8SAndreas Fenkart return host->card_detect(host->dev); 1646a45c6cb8SMadhusudhan Chikkature } 1647a45c6cb8SMadhusudhan Chikkature 16484816858cSGrazvydas Ignotas static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 16494816858cSGrazvydas Ignotas { 16504816858cSGrazvydas Ignotas struct omap_hsmmc_host *host = mmc_priv(mmc); 16514816858cSGrazvydas Ignotas 1652326119c9SAndreas Fenkart if (mmc_pdata(host)->init_card) 1653326119c9SAndreas Fenkart mmc_pdata(host)->init_card(card); 16544816858cSGrazvydas Ignotas } 16554816858cSGrazvydas Ignotas 16562cd3a2a5SAndreas Fenkart static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 16572cd3a2a5SAndreas Fenkart { 16582cd3a2a5SAndreas Fenkart struct omap_hsmmc_host *host = mmc_priv(mmc); 16595a52b08bSBalaji T K u32 irq_mask, con; 16602cd3a2a5SAndreas Fenkart unsigned long flags; 16612cd3a2a5SAndreas Fenkart 16622cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 16632cd3a2a5SAndreas Fenkart 16645a52b08bSBalaji T K con = OMAP_HSMMC_READ(host->base, CON); 16652cd3a2a5SAndreas Fenkart irq_mask = OMAP_HSMMC_READ(host->base, ISE); 16662cd3a2a5SAndreas Fenkart if (enable) { 16672cd3a2a5SAndreas Fenkart host->flags |= HSMMC_SDIO_IRQ_ENABLED; 16682cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 16695a52b08bSBalaji T K con |= CTPL | CLKEXTFREE; 16702cd3a2a5SAndreas Fenkart } else { 16712cd3a2a5SAndreas Fenkart host->flags &= ~HSMMC_SDIO_IRQ_ENABLED; 16722cd3a2a5SAndreas Fenkart irq_mask &= ~CIRQ_EN; 16735a52b08bSBalaji T K con &= ~(CTPL | CLKEXTFREE); 16742cd3a2a5SAndreas Fenkart } 16755a52b08bSBalaji T K OMAP_HSMMC_WRITE(host->base, CON, con); 16762cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 16772cd3a2a5SAndreas Fenkart 16782cd3a2a5SAndreas Fenkart /* 16792cd3a2a5SAndreas Fenkart * if enable, piggy back detection on current request 16802cd3a2a5SAndreas Fenkart * but always disable immediately 16812cd3a2a5SAndreas Fenkart */ 16822cd3a2a5SAndreas Fenkart if (!host->req_in_progress || !enable) 16832cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 16842cd3a2a5SAndreas Fenkart 16852cd3a2a5SAndreas Fenkart /* flush posted write */ 16862cd3a2a5SAndreas Fenkart OMAP_HSMMC_READ(host->base, IE); 16872cd3a2a5SAndreas Fenkart 16882cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 16892cd3a2a5SAndreas Fenkart } 16902cd3a2a5SAndreas Fenkart 16912cd3a2a5SAndreas Fenkart static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host) 16922cd3a2a5SAndreas Fenkart { 16932cd3a2a5SAndreas Fenkart struct mmc_host *mmc = host->mmc; 16942cd3a2a5SAndreas Fenkart int ret; 16952cd3a2a5SAndreas Fenkart 16962cd3a2a5SAndreas Fenkart /* 16972cd3a2a5SAndreas Fenkart * For omaps with wake-up path, wakeirq will be irq from pinctrl and 16982cd3a2a5SAndreas Fenkart * for other omaps, wakeirq will be from GPIO (dat line remuxed to 16992cd3a2a5SAndreas Fenkart * gpio). wakeirq is needed to detect sdio irq in runtime suspend state 17002cd3a2a5SAndreas Fenkart * with functional clock disabled. 17012cd3a2a5SAndreas Fenkart */ 17022cd3a2a5SAndreas Fenkart if (!host->dev->of_node || !host->wake_irq) 17032cd3a2a5SAndreas Fenkart return -ENODEV; 17042cd3a2a5SAndreas Fenkart 17052cd3a2a5SAndreas Fenkart /* Prevent auto-enabling of IRQ */ 17062cd3a2a5SAndreas Fenkart irq_set_status_flags(host->wake_irq, IRQ_NOAUTOEN); 17072cd3a2a5SAndreas Fenkart ret = devm_request_irq(host->dev, host->wake_irq, omap_hsmmc_wake_irq, 17082cd3a2a5SAndreas Fenkart IRQF_TRIGGER_LOW | IRQF_ONESHOT, 17092cd3a2a5SAndreas Fenkart mmc_hostname(mmc), host); 17102cd3a2a5SAndreas Fenkart if (ret) { 17112cd3a2a5SAndreas Fenkart dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n"); 17122cd3a2a5SAndreas Fenkart goto err; 17132cd3a2a5SAndreas Fenkart } 17142cd3a2a5SAndreas Fenkart 17152cd3a2a5SAndreas Fenkart /* 17162cd3a2a5SAndreas Fenkart * Some omaps don't have wake-up path from deeper idle states 17172cd3a2a5SAndreas Fenkart * and need to remux SDIO DAT1 to GPIO for wake-up from idle. 17182cd3a2a5SAndreas Fenkart */ 17192cd3a2a5SAndreas Fenkart if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) { 1720455e5cd6SAndreas Fenkart struct pinctrl *p = devm_pinctrl_get(host->dev); 1721455e5cd6SAndreas Fenkart if (!p) { 17222cd3a2a5SAndreas Fenkart ret = -ENODEV; 1723455e5cd6SAndreas Fenkart goto err_free_irq; 1724455e5cd6SAndreas Fenkart } 1725455e5cd6SAndreas Fenkart if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) { 1726455e5cd6SAndreas Fenkart dev_info(host->dev, "missing default pinctrl state\n"); 1727455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 1728455e5cd6SAndreas Fenkart ret = -EINVAL; 1729455e5cd6SAndreas Fenkart goto err_free_irq; 1730455e5cd6SAndreas Fenkart } 1731455e5cd6SAndreas Fenkart 1732455e5cd6SAndreas Fenkart if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) { 1733455e5cd6SAndreas Fenkart dev_info(host->dev, "missing idle pinctrl state\n"); 1734455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 1735455e5cd6SAndreas Fenkart ret = -EINVAL; 1736455e5cd6SAndreas Fenkart goto err_free_irq; 1737455e5cd6SAndreas Fenkart } 1738455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 17392cd3a2a5SAndreas Fenkart } 17402cd3a2a5SAndreas Fenkart 17415a52b08bSBalaji T K OMAP_HSMMC_WRITE(host->base, HCTL, 17425a52b08bSBalaji T K OMAP_HSMMC_READ(host->base, HCTL) | IWE); 17432cd3a2a5SAndreas Fenkart return 0; 17442cd3a2a5SAndreas Fenkart 1745455e5cd6SAndreas Fenkart err_free_irq: 1746455e5cd6SAndreas Fenkart devm_free_irq(host->dev, host->wake_irq, host); 17472cd3a2a5SAndreas Fenkart err: 17482cd3a2a5SAndreas Fenkart dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n"); 17492cd3a2a5SAndreas Fenkart host->wake_irq = 0; 17502cd3a2a5SAndreas Fenkart return ret; 17512cd3a2a5SAndreas Fenkart } 17522cd3a2a5SAndreas Fenkart 175370a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 17541b331e69SKim Kyuwon { 17551b331e69SKim Kyuwon u32 hctl, capa, value; 17561b331e69SKim Kyuwon 17571b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 17584621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 17591b331e69SKim Kyuwon hctl = SDVS30; 17601b331e69SKim Kyuwon capa = VS30 | VS18; 17611b331e69SKim Kyuwon } else { 17621b331e69SKim Kyuwon hctl = SDVS18; 17631b331e69SKim Kyuwon capa = VS18; 17641b331e69SKim Kyuwon } 17651b331e69SKim Kyuwon 17661b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 17671b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 17681b331e69SKim Kyuwon 17691b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 17701b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 17711b331e69SKim Kyuwon 17721b331e69SKim Kyuwon /* Set SD bus power bit */ 1773e13bb300SAdrian Hunter set_sd_bus_power(host); 17741b331e69SKim Kyuwon } 17751b331e69SKim Kyuwon 177670a3341aSDenis Karpov static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) 1777dd498effSDenis Karpov { 177870a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1779dd498effSDenis Karpov 1780fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1781fa4aa2d4SBalaji T K 1782dd498effSDenis Karpov return 0; 1783dd498effSDenis Karpov } 1784dd498effSDenis Karpov 1785907d2e7cSAdrian Hunter static int omap_hsmmc_disable_fclk(struct mmc_host *mmc) 1786dd498effSDenis Karpov { 178770a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1788dd498effSDenis Karpov 1789fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1790fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1791fa4aa2d4SBalaji T K 1792dd498effSDenis Karpov return 0; 1793dd498effSDenis Karpov } 1794dd498effSDenis Karpov 1795afd8c29dSKuninori Morimoto static int omap_hsmmc_multi_io_quirk(struct mmc_card *card, 1796afd8c29dSKuninori Morimoto unsigned int direction, int blk_size) 1797afd8c29dSKuninori Morimoto { 1798afd8c29dSKuninori Morimoto /* This controller can't do multiblock reads due to hw bugs */ 1799afd8c29dSKuninori Morimoto if (direction == MMC_DATA_READ) 1800afd8c29dSKuninori Morimoto return 1; 1801afd8c29dSKuninori Morimoto 1802afd8c29dSKuninori Morimoto return blk_size; 1803afd8c29dSKuninori Morimoto } 1804afd8c29dSKuninori Morimoto 1805afd8c29dSKuninori Morimoto static struct mmc_host_ops omap_hsmmc_ops = { 180670a3341aSDenis Karpov .enable = omap_hsmmc_enable_fclk, 180770a3341aSDenis Karpov .disable = omap_hsmmc_disable_fclk, 18089782aff8SPer Forlin .post_req = omap_hsmmc_post_req, 18099782aff8SPer Forlin .pre_req = omap_hsmmc_pre_req, 181070a3341aSDenis Karpov .request = omap_hsmmc_request, 181170a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1812dd498effSDenis Karpov .get_cd = omap_hsmmc_get_cd, 1813a49d8353SAndreas Fenkart .get_ro = mmc_gpio_get_ro, 18144816858cSGrazvydas Ignotas .init_card = omap_hsmmc_init_card, 18152cd3a2a5SAndreas Fenkart .enable_sdio_irq = omap_hsmmc_enable_sdio_irq, 1816dd498effSDenis Karpov }; 1817dd498effSDenis Karpov 1818d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS 1819d900f712SDenis Karpov 182070a3341aSDenis Karpov static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1821d900f712SDenis Karpov { 1822d900f712SDenis Karpov struct mmc_host *mmc = s->private; 182370a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 182411dd62a7SDenis Karpov 1825bb0635f0SAndreas Fenkart seq_printf(s, "mmc%d:\n", mmc->index); 1826bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq mode\t%s\n", 1827bb0635f0SAndreas Fenkart (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling"); 1828bb0635f0SAndreas Fenkart 1829bb0635f0SAndreas Fenkart if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1830bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq \t%s\n", 1831bb0635f0SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled" 1832bb0635f0SAndreas Fenkart : "disabled"); 1833bb0635f0SAndreas Fenkart } 1834bb0635f0SAndreas Fenkart seq_printf(s, "ctx_loss:\t%d\n", host->context_loss); 18355e2ea617SAdrian Hunter 1836fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1837bb0635f0SAndreas Fenkart seq_puts(s, "\nregs:\n"); 1838d900f712SDenis Karpov seq_printf(s, "CON:\t\t0x%08x\n", 1839d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CON)); 1840bb0635f0SAndreas Fenkart seq_printf(s, "PSTATE:\t\t0x%08x\n", 1841bb0635f0SAndreas Fenkart OMAP_HSMMC_READ(host->base, PSTATE)); 1842d900f712SDenis Karpov seq_printf(s, "HCTL:\t\t0x%08x\n", 1843d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL)); 1844d900f712SDenis Karpov seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1845d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL)); 1846d900f712SDenis Karpov seq_printf(s, "IE:\t\t0x%08x\n", 1847d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, IE)); 1848d900f712SDenis Karpov seq_printf(s, "ISE:\t\t0x%08x\n", 1849d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, ISE)); 1850d900f712SDenis Karpov seq_printf(s, "CAPA:\t\t0x%08x\n", 1851d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA)); 18525e2ea617SAdrian Hunter 1853fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1854fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1855dd498effSDenis Karpov 1856d900f712SDenis Karpov return 0; 1857d900f712SDenis Karpov } 1858d900f712SDenis Karpov 185970a3341aSDenis Karpov static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1860d900f712SDenis Karpov { 186170a3341aSDenis Karpov return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1862d900f712SDenis Karpov } 1863d900f712SDenis Karpov 1864d900f712SDenis Karpov static const struct file_operations mmc_regs_fops = { 186570a3341aSDenis Karpov .open = omap_hsmmc_regs_open, 1866d900f712SDenis Karpov .read = seq_read, 1867d900f712SDenis Karpov .llseek = seq_lseek, 1868d900f712SDenis Karpov .release = single_release, 1869d900f712SDenis Karpov }; 1870d900f712SDenis Karpov 187170a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1872d900f712SDenis Karpov { 1873d900f712SDenis Karpov if (mmc->debugfs_root) 1874d900f712SDenis Karpov debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1875d900f712SDenis Karpov mmc, &mmc_regs_fops); 1876d900f712SDenis Karpov } 1877d900f712SDenis Karpov 1878d900f712SDenis Karpov #else 1879d900f712SDenis Karpov 188070a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1881d900f712SDenis Karpov { 1882d900f712SDenis Karpov } 1883d900f712SDenis Karpov 1884d900f712SDenis Karpov #endif 1885d900f712SDenis Karpov 188646856a68SRajendra Nayak #ifdef CONFIG_OF 188759445b10SNishanth Menon static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = { 188859445b10SNishanth Menon /* See 35xx errata 2.1.1.128 in SPRZ278F */ 188959445b10SNishanth Menon .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 189059445b10SNishanth Menon }; 189159445b10SNishanth Menon 189259445b10SNishanth Menon static const struct omap_mmc_of_data omap4_mmc_of_data = { 189359445b10SNishanth Menon .reg_offset = 0x100, 189459445b10SNishanth Menon }; 18952cd3a2a5SAndreas Fenkart static const struct omap_mmc_of_data am33xx_mmc_of_data = { 18962cd3a2a5SAndreas Fenkart .reg_offset = 0x100, 18972cd3a2a5SAndreas Fenkart .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING, 18982cd3a2a5SAndreas Fenkart }; 189946856a68SRajendra Nayak 190046856a68SRajendra Nayak static const struct of_device_id omap_mmc_of_match[] = { 190146856a68SRajendra Nayak { 190246856a68SRajendra Nayak .compatible = "ti,omap2-hsmmc", 190346856a68SRajendra Nayak }, 190446856a68SRajendra Nayak { 190559445b10SNishanth Menon .compatible = "ti,omap3-pre-es3-hsmmc", 190659445b10SNishanth Menon .data = &omap3_pre_es3_mmc_of_data, 190759445b10SNishanth Menon }, 190859445b10SNishanth Menon { 190946856a68SRajendra Nayak .compatible = "ti,omap3-hsmmc", 191046856a68SRajendra Nayak }, 191146856a68SRajendra Nayak { 191246856a68SRajendra Nayak .compatible = "ti,omap4-hsmmc", 191359445b10SNishanth Menon .data = &omap4_mmc_of_data, 191446856a68SRajendra Nayak }, 19152cd3a2a5SAndreas Fenkart { 19162cd3a2a5SAndreas Fenkart .compatible = "ti,am33xx-hsmmc", 19172cd3a2a5SAndreas Fenkart .data = &am33xx_mmc_of_data, 19182cd3a2a5SAndreas Fenkart }, 191946856a68SRajendra Nayak {}, 1920b6d085f6SChris Ball }; 192146856a68SRajendra Nayak MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 192246856a68SRajendra Nayak 192355143438SAndreas Fenkart static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 192446856a68SRajendra Nayak { 192555143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata; 192646856a68SRajendra Nayak struct device_node *np = dev->of_node; 192746856a68SRajendra Nayak 192846856a68SRajendra Nayak pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 192946856a68SRajendra Nayak if (!pdata) 193019df45bcSBalaji T K return ERR_PTR(-ENOMEM); /* out of memory */ 193146856a68SRajendra Nayak 193246856a68SRajendra Nayak if (of_find_property(np, "ti,dual-volt", NULL)) 193346856a68SRajendra Nayak pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 193446856a68SRajendra Nayak 1935fdb9de12SNeilBrown pdata->switch_pin = -EINVAL; 1936fdb9de12SNeilBrown pdata->gpio_wp = -EINVAL; 193746856a68SRajendra Nayak 193846856a68SRajendra Nayak if (of_find_property(np, "ti,non-removable", NULL)) { 1939326119c9SAndreas Fenkart pdata->nonremovable = true; 1940326119c9SAndreas Fenkart pdata->no_regulator_off_init = true; 194146856a68SRajendra Nayak } 194246856a68SRajendra Nayak 194346856a68SRajendra Nayak if (of_find_property(np, "ti,needs-special-reset", NULL)) 1944326119c9SAndreas Fenkart pdata->features |= HSMMC_HAS_UPDATED_RESET; 194546856a68SRajendra Nayak 1946cd587096SHebbar, Gururaja if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) 1947326119c9SAndreas Fenkart pdata->features |= HSMMC_HAS_HSPE_SUPPORT; 1948cd587096SHebbar, Gururaja 194946856a68SRajendra Nayak return pdata; 195046856a68SRajendra Nayak } 195146856a68SRajendra Nayak #else 195255143438SAndreas Fenkart static inline struct omap_hsmmc_platform_data 195346856a68SRajendra Nayak *of_get_hsmmc_pdata(struct device *dev) 195446856a68SRajendra Nayak { 195519df45bcSBalaji T K return ERR_PTR(-EINVAL); 195646856a68SRajendra Nayak } 195746856a68SRajendra Nayak #endif 195846856a68SRajendra Nayak 1959c3be1efdSBill Pemberton static int omap_hsmmc_probe(struct platform_device *pdev) 1960a45c6cb8SMadhusudhan Chikkature { 196155143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data; 1962a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 196370a3341aSDenis Karpov struct omap_hsmmc_host *host = NULL; 1964a45c6cb8SMadhusudhan Chikkature struct resource *res; 1965db0fefc5SAdrian Hunter int ret, irq; 196646856a68SRajendra Nayak const struct of_device_id *match; 196726b88520SRussell King dma_cap_mask_t mask; 196826b88520SRussell King unsigned tx_req, rx_req; 196959445b10SNishanth Menon const struct omap_mmc_of_data *data; 197077fae219SBalaji T K void __iomem *base; 197146856a68SRajendra Nayak 197246856a68SRajendra Nayak match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 197346856a68SRajendra Nayak if (match) { 197446856a68SRajendra Nayak pdata = of_get_hsmmc_pdata(&pdev->dev); 1975dc642c28SJan Luebbe 1976dc642c28SJan Luebbe if (IS_ERR(pdata)) 1977dc642c28SJan Luebbe return PTR_ERR(pdata); 1978dc642c28SJan Luebbe 197946856a68SRajendra Nayak if (match->data) { 198059445b10SNishanth Menon data = match->data; 198159445b10SNishanth Menon pdata->reg_offset = data->reg_offset; 198259445b10SNishanth Menon pdata->controller_flags |= data->controller_flags; 198346856a68SRajendra Nayak } 198446856a68SRajendra Nayak } 1985a45c6cb8SMadhusudhan Chikkature 1986a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 1987a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 1988a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1989a45c6cb8SMadhusudhan Chikkature } 1990a45c6cb8SMadhusudhan Chikkature 1991a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1992a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 1993a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 1994a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1995a45c6cb8SMadhusudhan Chikkature 199677fae219SBalaji T K base = devm_ioremap_resource(&pdev->dev, res); 199777fae219SBalaji T K if (IS_ERR(base)) 199877fae219SBalaji T K return PTR_ERR(base); 1999a45c6cb8SMadhusudhan Chikkature 200070a3341aSDenis Karpov mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 2001a45c6cb8SMadhusudhan Chikkature if (!mmc) { 2002a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 20031e363e3bSAndreas Fenkart goto err; 2004a45c6cb8SMadhusudhan Chikkature } 2005a45c6cb8SMadhusudhan Chikkature 2006fdb9de12SNeilBrown ret = mmc_of_parse(mmc); 2007fdb9de12SNeilBrown if (ret) 2008fdb9de12SNeilBrown goto err1; 2009fdb9de12SNeilBrown 2010a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 2011a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 2012a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 2013a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 2014a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 2015a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 2016a45c6cb8SMadhusudhan Chikkature host->irq = irq; 2017fc307df8SBalaji T K host->mapbase = res->start + pdata->reg_offset; 201877fae219SBalaji T K host->base = base + pdata->reg_offset; 20196da20c89SAdrian Hunter host->power_mode = MMC_POWER_OFF; 20209782aff8SPer Forlin host->next_data.cookie = 1; 2021e99448ffSBalaji T K host->pbias_enabled = 0; 2022a45c6cb8SMadhusudhan Chikkature 202341afa314SNeilBrown ret = omap_hsmmc_gpio_init(mmc, host, pdata); 20241e363e3bSAndreas Fenkart if (ret) 20251e363e3bSAndreas Fenkart goto err_gpio; 20261e363e3bSAndreas Fenkart 2027a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 2028a45c6cb8SMadhusudhan Chikkature 20292cd3a2a5SAndreas Fenkart if (pdev->dev.of_node) 20302cd3a2a5SAndreas Fenkart host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1); 20312cd3a2a5SAndreas Fenkart 203270a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ops; 2033dd498effSDenis Karpov 20346b206efeSAndy Shevchenko mmc->f_min = OMAP_MMC_MIN_CLOCK; 2035d418ed87SDaniel Mack 2036d418ed87SDaniel Mack if (pdata->max_freq > 0) 2037d418ed87SDaniel Mack mmc->f_max = pdata->max_freq; 2038fdb9de12SNeilBrown else if (mmc->f_max == 0) 20396b206efeSAndy Shevchenko mmc->f_max = OMAP_MMC_MAX_CLOCK; 2040a45c6cb8SMadhusudhan Chikkature 20414dffd7a2SAdrian Hunter spin_lock_init(&host->irq_lock); 2042a45c6cb8SMadhusudhan Chikkature 20439618195eSBalaji T K host->fclk = devm_clk_get(&pdev->dev, "fck"); 2044a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 2045a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 2046a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 2047a45c6cb8SMadhusudhan Chikkature goto err1; 2048a45c6cb8SMadhusudhan Chikkature } 2049a45c6cb8SMadhusudhan Chikkature 20509b68256cSPaul Walmsley if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 20519b68256cSPaul Walmsley dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 2052afd8c29dSKuninori Morimoto omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk; 20539b68256cSPaul Walmsley } 2054dd498effSDenis Karpov 2055fa4aa2d4SBalaji T K pm_runtime_enable(host->dev); 2056fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2057fa4aa2d4SBalaji T K pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 2058fa4aa2d4SBalaji T K pm_runtime_use_autosuspend(host->dev); 2059a45c6cb8SMadhusudhan Chikkature 206092a3aebfSBalaji T K omap_hsmmc_context_save(host); 206192a3aebfSBalaji T K 20629618195eSBalaji T K host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck"); 2063a45c6cb8SMadhusudhan Chikkature /* 2064a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 2065a45c6cb8SMadhusudhan Chikkature */ 2066cd03d9a8SRajendra Nayak if (IS_ERR(host->dbclk)) { 2067cd03d9a8SRajendra Nayak host->dbclk = NULL; 206894c18149SRajendra Nayak } else if (clk_prepare_enable(host->dbclk) != 0) { 2069cd03d9a8SRajendra Nayak dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 2070cd03d9a8SRajendra Nayak host->dbclk = NULL; 20712bec0893SAdrian Hunter } 2072a45c6cb8SMadhusudhan Chikkature 20730ccd76d4SJuha Yrjola /* Since we do only SG emulation, we can have as many segs 20740ccd76d4SJuha Yrjola * as we want. */ 2075a36274e0SMartin K. Petersen mmc->max_segs = 1024; 20760ccd76d4SJuha Yrjola 2077a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 2078a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 2079a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2080a45c6cb8SMadhusudhan Chikkature mmc->max_seg_size = mmc->max_req_size; 2081a45c6cb8SMadhusudhan Chikkature 208213189e78SJarkko Lavinen mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 208393caf8e6SAdrian Hunter MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 2084a45c6cb8SMadhusudhan Chikkature 2085326119c9SAndreas Fenkart mmc->caps |= mmc_pdata(host)->caps; 20863a63833eSSukumar Ghorai if (mmc->caps & MMC_CAP_8_BIT_DATA) 2087a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 2088a45c6cb8SMadhusudhan Chikkature 2089326119c9SAndreas Fenkart if (mmc_pdata(host)->nonremovable) 209023d99bb9SAdrian Hunter mmc->caps |= MMC_CAP_NONREMOVABLE; 209123d99bb9SAdrian Hunter 2092fdb9de12SNeilBrown mmc->pm_caps |= mmc_pdata(host)->pm_caps; 20936fdc75deSEliad Peller 209470a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 2095a45c6cb8SMadhusudhan Chikkature 20964a29b559SSantosh Shilimkar if (!pdev->dev.of_node) { 2097b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 2098b7bf773bSBalaji T K if (!res) { 2099b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n"); 21009c17d08cSKevin Hilman ret = -ENXIO; 2101f3e2f1ddSGrazvydas Ignotas goto err_irq; 2102a45c6cb8SMadhusudhan Chikkature } 210326b88520SRussell King tx_req = res->start; 2104b7bf773bSBalaji T K 2105b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 2106b7bf773bSBalaji T K if (!res) { 2107b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n"); 21089c17d08cSKevin Hilman ret = -ENXIO; 2109b7bf773bSBalaji T K goto err_irq; 2110b7bf773bSBalaji T K } 211126b88520SRussell King rx_req = res->start; 21124a29b559SSantosh Shilimkar } 2113c5c98927SRussell King 2114c5c98927SRussell King dma_cap_zero(mask); 2115c5c98927SRussell King dma_cap_set(DMA_SLAVE, mask); 211626b88520SRussell King 2117d272fbf0SMatt Porter host->rx_chan = 2118d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 2119d272fbf0SMatt Porter &rx_req, &pdev->dev, "rx"); 2120d272fbf0SMatt Porter 2121c5c98927SRussell King if (!host->rx_chan) { 212226b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req); 212304e8c7bcSKevin Hilman ret = -ENXIO; 212426b88520SRussell King goto err_irq; 2125c5c98927SRussell King } 212626b88520SRussell King 2127d272fbf0SMatt Porter host->tx_chan = 2128d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 2129d272fbf0SMatt Porter &tx_req, &pdev->dev, "tx"); 2130d272fbf0SMatt Porter 2131c5c98927SRussell King if (!host->tx_chan) { 213226b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req); 213304e8c7bcSKevin Hilman ret = -ENXIO; 213426b88520SRussell King goto err_irq; 2135c5c98927SRussell King } 2136a45c6cb8SMadhusudhan Chikkature 2137a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 2138e1538ed7SBalaji T K ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0, 2139a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 2140a45c6cb8SMadhusudhan Chikkature if (ret) { 2141b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 2142a45c6cb8SMadhusudhan Chikkature goto err_irq; 2143a45c6cb8SMadhusudhan Chikkature } 2144a45c6cb8SMadhusudhan Chikkature 2145326119c9SAndreas Fenkart if (omap_hsmmc_have_reg() && !mmc_pdata(host)->set_power) { 2146db0fefc5SAdrian Hunter ret = omap_hsmmc_reg_get(host); 2147db0fefc5SAdrian Hunter if (ret) 2148bb09d151SAndreas Fenkart goto err_irq; 2149db0fefc5SAdrian Hunter host->use_reg = 1; 2150db0fefc5SAdrian Hunter } 2151db0fefc5SAdrian Hunter 2152326119c9SAndreas Fenkart mmc->ocr_avail = mmc_pdata(host)->ocr_mask; 2153a45c6cb8SMadhusudhan Chikkature 2154b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 2155a45c6cb8SMadhusudhan Chikkature 21562cd3a2a5SAndreas Fenkart /* 21572cd3a2a5SAndreas Fenkart * For now, only support SDIO interrupt if we have a separate 21582cd3a2a5SAndreas Fenkart * wake-up interrupt configured from device tree. This is because 21592cd3a2a5SAndreas Fenkart * the wake-up interrupt is needed for idle state and some 21602cd3a2a5SAndreas Fenkart * platforms need special quirks. And we don't want to add new 21612cd3a2a5SAndreas Fenkart * legacy mux platform init code callbacks any longer as we 21622cd3a2a5SAndreas Fenkart * are moving to DT based booting anyways. 21632cd3a2a5SAndreas Fenkart */ 21642cd3a2a5SAndreas Fenkart ret = omap_hsmmc_configure_wake_irq(host); 21652cd3a2a5SAndreas Fenkart if (!ret) 21662cd3a2a5SAndreas Fenkart mmc->caps |= MMC_CAP_SDIO_IRQ; 21672cd3a2a5SAndreas Fenkart 2168b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2169b62f6228SAdrian Hunter 2170a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 2171a45c6cb8SMadhusudhan Chikkature 2172326119c9SAndreas Fenkart if (mmc_pdata(host)->name != NULL) { 2173a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2174a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2175a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 2176a45c6cb8SMadhusudhan Chikkature } 2177cde592cbSAndreas Fenkart if (host->get_cover_state) { 2178a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, 2179a45c6cb8SMadhusudhan Chikkature &dev_attr_cover_switch); 2180a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2181db0fefc5SAdrian Hunter goto err_slot_name; 2182a45c6cb8SMadhusudhan Chikkature } 2183a45c6cb8SMadhusudhan Chikkature 218470a3341aSDenis Karpov omap_hsmmc_debugfs(mmc); 2185fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2186fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2187d900f712SDenis Karpov 2188a45c6cb8SMadhusudhan Chikkature return 0; 2189a45c6cb8SMadhusudhan Chikkature 2190a45c6cb8SMadhusudhan Chikkature err_slot_name: 2191a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 2192db0fefc5SAdrian Hunter if (host->use_reg) 2193db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2194a45c6cb8SMadhusudhan Chikkature err_irq: 2195c5c98927SRussell King if (host->tx_chan) 2196c5c98927SRussell King dma_release_channel(host->tx_chan); 2197c5c98927SRussell King if (host->rx_chan) 2198c5c98927SRussell King dma_release_channel(host->rx_chan); 2199d59d77edSBalaji T K pm_runtime_put_sync(host->dev); 220037f6190dSTony Lindgren pm_runtime_disable(host->dev); 22019618195eSBalaji T K if (host->dbclk) 220294c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2203a45c6cb8SMadhusudhan Chikkature err1: 22041e363e3bSAndreas Fenkart err_gpio: 2205a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 2206db0fefc5SAdrian Hunter err: 2207a45c6cb8SMadhusudhan Chikkature return ret; 2208a45c6cb8SMadhusudhan Chikkature } 2209a45c6cb8SMadhusudhan Chikkature 22106e0ee714SBill Pemberton static int omap_hsmmc_remove(struct platform_device *pdev) 2211a45c6cb8SMadhusudhan Chikkature { 221270a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2213a45c6cb8SMadhusudhan Chikkature 2214fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2215a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 2216db0fefc5SAdrian Hunter if (host->use_reg) 2217db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2218a45c6cb8SMadhusudhan Chikkature 2219c5c98927SRussell King if (host->tx_chan) 2220c5c98927SRussell King dma_release_channel(host->tx_chan); 2221c5c98927SRussell King if (host->rx_chan) 2222c5c98927SRussell King dma_release_channel(host->rx_chan); 2223c5c98927SRussell King 2224fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2225fa4aa2d4SBalaji T K pm_runtime_disable(host->dev); 22269618195eSBalaji T K if (host->dbclk) 222794c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2228a45c6cb8SMadhusudhan Chikkature 22299d1f0286SBalaji T K mmc_free_host(host->mmc); 2230a45c6cb8SMadhusudhan Chikkature 2231a45c6cb8SMadhusudhan Chikkature return 0; 2232a45c6cb8SMadhusudhan Chikkature } 2233a45c6cb8SMadhusudhan Chikkature 22343d3bbfbdSRuss Dill #ifdef CONFIG_PM_SLEEP 2235a791daa1SKevin Hilman static int omap_hsmmc_suspend(struct device *dev) 2236a45c6cb8SMadhusudhan Chikkature { 2237927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2238927ce944SFelipe Balbi 2239927ce944SFelipe Balbi if (!host) 2240927ce944SFelipe Balbi return 0; 2241a45c6cb8SMadhusudhan Chikkature 2242fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 224331f9d463SEliad Peller 224431f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 22452cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 22462cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 22472cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 224831f9d463SEliad Peller OMAP_HSMMC_WRITE(host->base, HCTL, 224931f9d463SEliad Peller OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 225031f9d463SEliad Peller } 2251927ce944SFelipe Balbi 22522cd3a2a5SAndreas Fenkart /* do not wake up due to sdio irq */ 22532cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 22542cd3a2a5SAndreas Fenkart !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 22552cd3a2a5SAndreas Fenkart disable_irq(host->wake_irq); 22562cd3a2a5SAndreas Fenkart 2257cd03d9a8SRajendra Nayak if (host->dbclk) 225894c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 22593932afd5SUlf Hansson 2260fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 22613932afd5SUlf Hansson return 0; 2262a45c6cb8SMadhusudhan Chikkature } 2263a45c6cb8SMadhusudhan Chikkature 2264a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 2265a791daa1SKevin Hilman static int omap_hsmmc_resume(struct device *dev) 2266a45c6cb8SMadhusudhan Chikkature { 2267927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2268927ce944SFelipe Balbi 2269927ce944SFelipe Balbi if (!host) 2270927ce944SFelipe Balbi return 0; 2271a45c6cb8SMadhusudhan Chikkature 2272fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 227311dd62a7SDenis Karpov 2274cd03d9a8SRajendra Nayak if (host->dbclk) 227594c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 22762bec0893SAdrian Hunter 227731f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 227870a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 22791b331e69SKim Kyuwon 2280b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2281b62f6228SAdrian Hunter 22822cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 22832cd3a2a5SAndreas Fenkart !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 22842cd3a2a5SAndreas Fenkart enable_irq(host->wake_irq); 22852cd3a2a5SAndreas Fenkart 2286fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2287fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 22883932afd5SUlf Hansson return 0; 2289a45c6cb8SMadhusudhan Chikkature } 2290a45c6cb8SMadhusudhan Chikkature #endif 2291a45c6cb8SMadhusudhan Chikkature 2292fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_suspend(struct device *dev) 2293fa4aa2d4SBalaji T K { 2294fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 22952cd3a2a5SAndreas Fenkart unsigned long flags; 2296f945901fSAndreas Fenkart int ret = 0; 2297fa4aa2d4SBalaji T K 2298fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2299fa4aa2d4SBalaji T K omap_hsmmc_context_save(host); 2300927ce944SFelipe Balbi dev_dbg(dev, "disabled\n"); 2301fa4aa2d4SBalaji T K 23022cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 23032cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 23042cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 23052cd3a2a5SAndreas Fenkart /* disable sdio irq handling to prevent race */ 23062cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 23072cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 2308f945901fSAndreas Fenkart 2309f945901fSAndreas Fenkart if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) { 2310f945901fSAndreas Fenkart /* 2311f945901fSAndreas Fenkart * dat1 line low, pending sdio irq 2312f945901fSAndreas Fenkart * race condition: possible irq handler running on 2313f945901fSAndreas Fenkart * multi-core, abort 2314f945901fSAndreas Fenkart */ 2315f945901fSAndreas Fenkart dev_dbg(dev, "pending sdio irq, abort suspend\n"); 23162cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 2317f945901fSAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 2318f945901fSAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 2319f945901fSAndreas Fenkart pm_runtime_mark_last_busy(dev); 2320f945901fSAndreas Fenkart ret = -EBUSY; 2321f945901fSAndreas Fenkart goto abort; 2322f945901fSAndreas Fenkart } 23232cd3a2a5SAndreas Fenkart 232497978a44SAndreas Fenkart pinctrl_pm_select_idle_state(dev); 232597978a44SAndreas Fenkart 23262cd3a2a5SAndreas Fenkart WARN_ON(host->flags & HSMMC_WAKE_IRQ_ENABLED); 23272cd3a2a5SAndreas Fenkart enable_irq(host->wake_irq); 23282cd3a2a5SAndreas Fenkart host->flags |= HSMMC_WAKE_IRQ_ENABLED; 232997978a44SAndreas Fenkart } else { 233097978a44SAndreas Fenkart pinctrl_pm_select_idle_state(dev); 23312cd3a2a5SAndreas Fenkart } 233297978a44SAndreas Fenkart 2333f945901fSAndreas Fenkart abort: 23342cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2335f945901fSAndreas Fenkart return ret; 2336fa4aa2d4SBalaji T K } 2337fa4aa2d4SBalaji T K 2338fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_resume(struct device *dev) 2339fa4aa2d4SBalaji T K { 2340fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 23412cd3a2a5SAndreas Fenkart unsigned long flags; 2342fa4aa2d4SBalaji T K 2343fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2344fa4aa2d4SBalaji T K omap_hsmmc_context_restore(host); 2345927ce944SFelipe Balbi dev_dbg(dev, "enabled\n"); 2346fa4aa2d4SBalaji T K 23472cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 23482cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 23492cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 23502cd3a2a5SAndreas Fenkart /* sdio irq flag can't change while in runtime suspend */ 23512cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_WAKE_IRQ_ENABLED) { 23522cd3a2a5SAndreas Fenkart disable_irq_nosync(host->wake_irq); 23532cd3a2a5SAndreas Fenkart host->flags &= ~HSMMC_WAKE_IRQ_ENABLED; 23542cd3a2a5SAndreas Fenkart } 23552cd3a2a5SAndreas Fenkart 235697978a44SAndreas Fenkart pinctrl_pm_select_default_state(host->dev); 235797978a44SAndreas Fenkart 235897978a44SAndreas Fenkart /* irq lost, if pinmux incorrect */ 23592cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 23602cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 23612cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 236297978a44SAndreas Fenkart } else { 236397978a44SAndreas Fenkart pinctrl_pm_select_default_state(host->dev); 23642cd3a2a5SAndreas Fenkart } 23652cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2366fa4aa2d4SBalaji T K return 0; 2367fa4aa2d4SBalaji T K } 2368fa4aa2d4SBalaji T K 2369a791daa1SKevin Hilman static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 23703d3bbfbdSRuss Dill SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume) 2371fa4aa2d4SBalaji T K .runtime_suspend = omap_hsmmc_runtime_suspend, 2372fa4aa2d4SBalaji T K .runtime_resume = omap_hsmmc_runtime_resume, 2373a791daa1SKevin Hilman }; 2374a791daa1SKevin Hilman 2375a791daa1SKevin Hilman static struct platform_driver omap_hsmmc_driver = { 2376efa25fd3SFelipe Balbi .probe = omap_hsmmc_probe, 23770433c143SBill Pemberton .remove = omap_hsmmc_remove, 2378a45c6cb8SMadhusudhan Chikkature .driver = { 2379a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 2380a791daa1SKevin Hilman .pm = &omap_hsmmc_dev_pm_ops, 238146856a68SRajendra Nayak .of_match_table = of_match_ptr(omap_mmc_of_match), 2382a45c6cb8SMadhusudhan Chikkature }, 2383a45c6cb8SMadhusudhan Chikkature }; 2384a45c6cb8SMadhusudhan Chikkature 2385b796450bSFelipe Balbi module_platform_driver(omap_hsmmc_driver); 2386a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2387a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 2388a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 2389a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 2390