1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20ac330f44SAndy Shevchenko #include <linux/kernel.h> 21d900f712SDenis Karpov #include <linux/debugfs.h> 22c5c98927SRussell King #include <linux/dmaengine.h> 23d900f712SDenis Karpov #include <linux/seq_file.h> 24031cd037SFelipe Balbi #include <linux/sizes.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 29a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 30a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 3146856a68SRajendra Nayak #include <linux/of.h> 322cd3a2a5SAndreas Fenkart #include <linux/of_irq.h> 3346856a68SRajendra Nayak #include <linux/of_gpio.h> 3446856a68SRajendra Nayak #include <linux/of_device.h> 35ee526d51SBalaji T K #include <linux/omap-dmaengine.h> 36a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 3713189e78SJarkko Lavinen #include <linux/mmc/core.h> 3893caf8e6SAdrian Hunter #include <linux/mmc/mmc.h> 3941afa314SNeilBrown #include <linux/mmc/slot-gpio.h> 40a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 412cd3a2a5SAndreas Fenkart #include <linux/irq.h> 42db0fefc5SAdrian Hunter #include <linux/gpio.h> 43db0fefc5SAdrian Hunter #include <linux/regulator/consumer.h> 4446b76035SDaniel Mack #include <linux/pinctrl/consumer.h> 45fa4aa2d4SBalaji T K #include <linux/pm_runtime.h> 465b83b223STony Lindgren #include <linux/pm_wakeirq.h> 4755143438SAndreas Fenkart #include <linux/platform_data/hsmmc-omap.h> 48a45c6cb8SMadhusudhan Chikkature 49a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 5011dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS 0x0014 51a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 52a2e77152SBalaji T K #define OMAP_HSMMC_SDMASA 0x0100 53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 57a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 58a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 59a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 60a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 61bb0635f0SAndreas Fenkart #define OMAP_HSMMC_PSTATE 0x0124 62a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 63a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 64a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 65a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 66a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 67a2e77152SBalaji T K #define OMAP_HSMMC_AC12 0x013C 68a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 69a45c6cb8SMadhusudhan Chikkature 70a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 71a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 72cd587096SHebbar, Gururaja #define HSS (1 << 21) 73a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 74a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 75eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 761b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 77a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 78a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 79a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 80a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 81a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 82a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 83a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 84a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 85ed164182SBalaji T K #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ 86a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 87a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 88a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 89a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 90a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 91a2e77152SBalaji T K #define ACEN_ACMD23 (2 << 2) 92a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 93a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 94a7e96879SVenkatraman S #define DMAE 0x1 95a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 96a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 97a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 98cd587096SHebbar, Gururaja #define HSPE (1 << 2) 995a52b08bSBalaji T K #define IWE (1 << 24) 10003b5d924SBalaji T K #define DDR (1 << 19) 1015a52b08bSBalaji T K #define CLKEXTFREE (1 << 16) 1025a52b08bSBalaji T K #define CTPL (1 << 11) 10373153010SJarkko Lavinen #define DW8 (1 << 5) 104a45c6cb8SMadhusudhan Chikkature #define OD 0x1 105a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 106a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 107a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 108a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 109a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 11011dd62a7SDenis Karpov #define SOFTRESET (1 << 1) 111a45c6cb8SMadhusudhan Chikkature 112f945901fSAndreas Fenkart /* PSTATE */ 113f945901fSAndreas Fenkart #define DLEV_DAT(x) (1 << (20 + (x))) 114f945901fSAndreas Fenkart 115a7e96879SVenkatraman S /* Interrupt masks for IE and ISE register */ 116a7e96879SVenkatraman S #define CC_EN (1 << 0) 117a7e96879SVenkatraman S #define TC_EN (1 << 1) 118a7e96879SVenkatraman S #define BWR_EN (1 << 4) 119a7e96879SVenkatraman S #define BRR_EN (1 << 5) 1202cd3a2a5SAndreas Fenkart #define CIRQ_EN (1 << 8) 121a7e96879SVenkatraman S #define ERR_EN (1 << 15) 122a7e96879SVenkatraman S #define CTO_EN (1 << 16) 123a7e96879SVenkatraman S #define CCRC_EN (1 << 17) 124a7e96879SVenkatraman S #define CEB_EN (1 << 18) 125a7e96879SVenkatraman S #define CIE_EN (1 << 19) 126a7e96879SVenkatraman S #define DTO_EN (1 << 20) 127a7e96879SVenkatraman S #define DCRC_EN (1 << 21) 128a7e96879SVenkatraman S #define DEB_EN (1 << 22) 129a2e77152SBalaji T K #define ACE_EN (1 << 24) 130a7e96879SVenkatraman S #define CERR_EN (1 << 28) 131a7e96879SVenkatraman S #define BADA_EN (1 << 29) 132a7e96879SVenkatraman S 133a2e77152SBalaji T K #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\ 134a7e96879SVenkatraman S DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ 135a7e96879SVenkatraman S BRR_EN | BWR_EN | TC_EN | CC_EN) 136a7e96879SVenkatraman S 137a2e77152SBalaji T K #define CNI (1 << 7) 138a2e77152SBalaji T K #define ACIE (1 << 4) 139a2e77152SBalaji T K #define ACEB (1 << 3) 140a2e77152SBalaji T K #define ACCE (1 << 2) 141a2e77152SBalaji T K #define ACTO (1 << 1) 142a2e77152SBalaji T K #define ACNE (1 << 0) 143a2e77152SBalaji T K 144fa4aa2d4SBalaji T K #define MMC_AUTOSUSPEND_DELAY 100 1451e881786SJianpeng Ma #define MMC_TIMEOUT_MS 20 /* 20 mSec */ 1461e881786SJianpeng Ma #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ 1476b206efeSAndy Shevchenko #define OMAP_MMC_MIN_CLOCK 400000 1486b206efeSAndy Shevchenko #define OMAP_MMC_MAX_CLOCK 52000000 1490005ae73SKishore Kadiyala #define DRIVER_NAME "omap_hsmmc" 150a45c6cb8SMadhusudhan Chikkature 151e99448ffSBalaji T K #define VDD_1V8 1800000 /* 180000 uV */ 152e99448ffSBalaji T K #define VDD_3V0 3000000 /* 300000 uV */ 153e99448ffSBalaji T K #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1) 154e99448ffSBalaji T K 155a45c6cb8SMadhusudhan Chikkature /* 156a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 157a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 158a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 159a45c6cb8SMadhusudhan Chikkature */ 160326119c9SAndreas Fenkart #define mmc_pdata(host) host->pdata 161a45c6cb8SMadhusudhan Chikkature 162a45c6cb8SMadhusudhan Chikkature /* 163a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 164a45c6cb8SMadhusudhan Chikkature */ 165a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 166a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 167a45c6cb8SMadhusudhan Chikkature 168a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 169a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 170a45c6cb8SMadhusudhan Chikkature 1719782aff8SPer Forlin struct omap_hsmmc_next { 1729782aff8SPer Forlin unsigned int dma_len; 1739782aff8SPer Forlin s32 cookie; 1749782aff8SPer Forlin }; 1759782aff8SPer Forlin 17670a3341aSDenis Karpov struct omap_hsmmc_host { 177a45c6cb8SMadhusudhan Chikkature struct device *dev; 178a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 179a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 180a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 181a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 182a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 183a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 184e99448ffSBalaji T K struct regulator *pbias; 185e99448ffSBalaji T K bool pbias_enabled; 186a45c6cb8SMadhusudhan Chikkature void __iomem *base; 187a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 1884dffd7a2SAdrian Hunter spinlock_t irq_lock; /* Prevent races with irq handler */ 189a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 1900ccd76d4SJuha Yrjola unsigned int dma_sg_idx; 191a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 192a3621465SAdrian Hunter unsigned char power_mode; 193a45c6cb8SMadhusudhan Chikkature int suspended; 1940a82e06eSTony Lindgren u32 con; 1950a82e06eSTony Lindgren u32 hctl; 1960a82e06eSTony Lindgren u32 sysctl; 1970a82e06eSTony Lindgren u32 capa; 198a45c6cb8SMadhusudhan Chikkature int irq; 1992cd3a2a5SAndreas Fenkart int wake_irq; 200a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 201c5c98927SRussell King struct dma_chan *tx_chan; 202c5c98927SRussell King struct dma_chan *rx_chan; 2034a694dc9SAdrian Hunter int response_busy; 20411dd62a7SDenis Karpov int context_loss; 205b62f6228SAdrian Hunter int protect_card; 206b62f6228SAdrian Hunter int reqs_blocked; 207b417577dSAdrian Hunter int req_in_progress; 2086e3076c2SBalaji T K unsigned long clk_rate; 209a2e77152SBalaji T K unsigned int flags; 2102cd3a2a5SAndreas Fenkart #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */ 2112cd3a2a5SAndreas Fenkart #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */ 2129782aff8SPer Forlin struct omap_hsmmc_next next_data; 21355143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata; 214b5cd43f0SAndreas Fenkart 215b5cd43f0SAndreas Fenkart /* return MMC cover switch state, can be NULL if not supported. 216b5cd43f0SAndreas Fenkart * 217b5cd43f0SAndreas Fenkart * possible return values: 218b5cd43f0SAndreas Fenkart * 0 - closed 219b5cd43f0SAndreas Fenkart * 1 - open 220b5cd43f0SAndreas Fenkart */ 22180412ca8SAndreas Fenkart int (*get_cover_state)(struct device *dev); 222b5cd43f0SAndreas Fenkart 22380412ca8SAndreas Fenkart int (*card_detect)(struct device *dev); 224a45c6cb8SMadhusudhan Chikkature }; 225a45c6cb8SMadhusudhan Chikkature 22659445b10SNishanth Menon struct omap_mmc_of_data { 22759445b10SNishanth Menon u32 reg_offset; 22859445b10SNishanth Menon u8 controller_flags; 22959445b10SNishanth Menon }; 23059445b10SNishanth Menon 231bf129e1cSBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host); 232bf129e1cSBalaji T K 23380412ca8SAndreas Fenkart static int omap_hsmmc_card_detect(struct device *dev) 234db0fefc5SAdrian Hunter { 2359ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 236db0fefc5SAdrian Hunter 23741afa314SNeilBrown return mmc_gpio_get_cd(host->mmc); 238db0fefc5SAdrian Hunter } 239db0fefc5SAdrian Hunter 24080412ca8SAndreas Fenkart static int omap_hsmmc_get_cover_state(struct device *dev) 241db0fefc5SAdrian Hunter { 2429ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 243db0fefc5SAdrian Hunter 24441afa314SNeilBrown return mmc_gpio_get_cd(host->mmc); 245db0fefc5SAdrian Hunter } 246db0fefc5SAdrian Hunter 247b702b106SAdrian Hunter #ifdef CONFIG_REGULATOR 248b702b106SAdrian Hunter 24980412ca8SAndreas Fenkart static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd) 250db0fefc5SAdrian Hunter { 251db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 252db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 253aa9a6801SKishon Vijay Abraham I struct mmc_host *mmc = host->mmc; 254db0fefc5SAdrian Hunter int ret = 0; 255db0fefc5SAdrian Hunter 256f7f0f035SAndreas Fenkart if (mmc_pdata(host)->set_power) 257f7f0f035SAndreas Fenkart return mmc_pdata(host)->set_power(dev, power_on, vdd); 258f7f0f035SAndreas Fenkart 259db0fefc5SAdrian Hunter /* 260db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 261db0fefc5SAdrian Hunter * voltage always-on regulator. 262db0fefc5SAdrian Hunter */ 263aa9a6801SKishon Vijay Abraham I if (!mmc->supply.vmmc) 264db0fefc5SAdrian Hunter return 0; 265db0fefc5SAdrian Hunter 266326119c9SAndreas Fenkart if (mmc_pdata(host)->before_set_reg) 26780412ca8SAndreas Fenkart mmc_pdata(host)->before_set_reg(dev, power_on, vdd); 268db0fefc5SAdrian Hunter 269e99448ffSBalaji T K if (host->pbias) { 270e99448ffSBalaji T K if (host->pbias_enabled == 1) { 271e99448ffSBalaji T K ret = regulator_disable(host->pbias); 272229f3292SKishon Vijay Abraham I if (ret) { 273229f3292SKishon Vijay Abraham I dev_err(dev, "pbias reg disable failed\n"); 274229f3292SKishon Vijay Abraham I return ret; 275229f3292SKishon Vijay Abraham I } 276e99448ffSBalaji T K host->pbias_enabled = 0; 277e99448ffSBalaji T K } 278e99448ffSBalaji T K } 279e99448ffSBalaji T K 280db0fefc5SAdrian Hunter /* 281db0fefc5SAdrian Hunter * Assume Vcc regulator is used only to power the card ... OMAP 282db0fefc5SAdrian Hunter * VDDS is used to power the pins, optionally with a transceiver to 283db0fefc5SAdrian Hunter * support cards using voltages other than VDDS (1.8V nominal). When a 284db0fefc5SAdrian Hunter * transceiver is used, DAT3..7 are muxed as transceiver control pins. 285db0fefc5SAdrian Hunter * 286db0fefc5SAdrian Hunter * In some cases this regulator won't support enable/disable; 287db0fefc5SAdrian Hunter * e.g. it's a fixed rail for a WLAN chip. 288db0fefc5SAdrian Hunter * 289db0fefc5SAdrian Hunter * In other cases vcc_aux switches interface power. Example, for 290db0fefc5SAdrian Hunter * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 291db0fefc5SAdrian Hunter * chips/cards need an interface voltage rail too. 292db0fefc5SAdrian Hunter */ 293db0fefc5SAdrian Hunter if (power_on) { 294229f3292SKishon Vijay Abraham I if (mmc->supply.vmmc) { 295aa9a6801SKishon Vijay Abraham I ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 296229f3292SKishon Vijay Abraham I if (ret) 297229f3292SKishon Vijay Abraham I return ret; 298229f3292SKishon Vijay Abraham I } 299229f3292SKishon Vijay Abraham I 300db0fefc5SAdrian Hunter /* Enable interface voltage rail, if needed */ 301229f3292SKishon Vijay Abraham I if (mmc->supply.vqmmc) { 302aa9a6801SKishon Vijay Abraham I ret = regulator_enable(mmc->supply.vqmmc); 303229f3292SKishon Vijay Abraham I if (ret) { 304229f3292SKishon Vijay Abraham I dev_err(dev, "vmmc_aux reg enable failed\n"); 305229f3292SKishon Vijay Abraham I goto err_set_vqmmc; 306229f3292SKishon Vijay Abraham I } 307db0fefc5SAdrian Hunter } 308db0fefc5SAdrian Hunter } else { 30999fc5131SLinus Walleij /* Shut down the rail */ 310229f3292SKishon Vijay Abraham I if (mmc->supply.vqmmc) { 311aa9a6801SKishon Vijay Abraham I ret = regulator_disable(mmc->supply.vqmmc); 312229f3292SKishon Vijay Abraham I if (ret) { 313229f3292SKishon Vijay Abraham I dev_err(dev, "vmmc_aux reg disable failed\n"); 314229f3292SKishon Vijay Abraham I return ret; 315229f3292SKishon Vijay Abraham I } 316229f3292SKishon Vijay Abraham I } 317229f3292SKishon Vijay Abraham I 318aa9a6801SKishon Vijay Abraham I if (mmc->supply.vmmc) { 31999fc5131SLinus Walleij /* Then proceed to shut down the local regulator */ 320aa9a6801SKishon Vijay Abraham I ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 321229f3292SKishon Vijay Abraham I if (ret) 322229f3292SKishon Vijay Abraham I return ret; 32399fc5131SLinus Walleij } 324db0fefc5SAdrian Hunter } 325db0fefc5SAdrian Hunter 326e99448ffSBalaji T K if (host->pbias) { 327e99448ffSBalaji T K if (vdd <= VDD_165_195) 328e99448ffSBalaji T K ret = regulator_set_voltage(host->pbias, VDD_1V8, 329e99448ffSBalaji T K VDD_1V8); 330e99448ffSBalaji T K else 331e99448ffSBalaji T K ret = regulator_set_voltage(host->pbias, VDD_3V0, 332e99448ffSBalaji T K VDD_3V0); 333e99448ffSBalaji T K if (ret < 0) 334229f3292SKishon Vijay Abraham I goto err_set_voltage; 335e99448ffSBalaji T K 336e99448ffSBalaji T K if (host->pbias_enabled == 0) { 337e99448ffSBalaji T K ret = regulator_enable(host->pbias); 338229f3292SKishon Vijay Abraham I if (ret) { 339229f3292SKishon Vijay Abraham I dev_err(dev, "pbias reg enable failed\n"); 340229f3292SKishon Vijay Abraham I goto err_set_voltage; 341229f3292SKishon Vijay Abraham I } else { 342e99448ffSBalaji T K host->pbias_enabled = 1; 343e99448ffSBalaji T K } 344e99448ffSBalaji T K } 345229f3292SKishon Vijay Abraham I } 346e99448ffSBalaji T K 347326119c9SAndreas Fenkart if (mmc_pdata(host)->after_set_reg) 34880412ca8SAndreas Fenkart mmc_pdata(host)->after_set_reg(dev, power_on, vdd); 349db0fefc5SAdrian Hunter 350229f3292SKishon Vijay Abraham I return 0; 351229f3292SKishon Vijay Abraham I 352229f3292SKishon Vijay Abraham I err_set_voltage: 353229f3292SKishon Vijay Abraham I if (mmc->supply.vqmmc) 354229f3292SKishon Vijay Abraham I regulator_disable(mmc->supply.vqmmc); 355229f3292SKishon Vijay Abraham I 356229f3292SKishon Vijay Abraham I err_set_vqmmc: 357229f3292SKishon Vijay Abraham I if (mmc->supply.vmmc) 358229f3292SKishon Vijay Abraham I mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 359229f3292SKishon Vijay Abraham I 360db0fefc5SAdrian Hunter return ret; 361db0fefc5SAdrian Hunter } 362db0fefc5SAdrian Hunter 363db0fefc5SAdrian Hunter static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 364db0fefc5SAdrian Hunter { 36564be9782Skishore kadiyala int ocr_value = 0; 3667d607f91SKishon Vijay Abraham I int ret; 367aa9a6801SKishon Vijay Abraham I struct mmc_host *mmc = host->mmc; 368db0fefc5SAdrian Hunter 369f7f0f035SAndreas Fenkart if (mmc_pdata(host)->set_power) 370f7f0f035SAndreas Fenkart return 0; 371f7f0f035SAndreas Fenkart 372aa9a6801SKishon Vijay Abraham I mmc->supply.vmmc = devm_regulator_get_optional(host->dev, "vmmc"); 373aa9a6801SKishon Vijay Abraham I if (IS_ERR(mmc->supply.vmmc)) { 374aa9a6801SKishon Vijay Abraham I ret = PTR_ERR(mmc->supply.vmmc); 3757d607f91SKishon Vijay Abraham I if (ret != -ENODEV) 3767d607f91SKishon Vijay Abraham I return ret; 3777d607f91SKishon Vijay Abraham I dev_dbg(host->dev, "unable to get vmmc regulator %ld\n", 378aa9a6801SKishon Vijay Abraham I PTR_ERR(mmc->supply.vmmc)); 379aa9a6801SKishon Vijay Abraham I mmc->supply.vmmc = NULL; 380db0fefc5SAdrian Hunter } else { 381aa9a6801SKishon Vijay Abraham I ocr_value = mmc_regulator_get_ocrmask(mmc->supply.vmmc); 382b49069fcSKishon Vijay Abraham I if (ocr_value > 0) 383326119c9SAndreas Fenkart mmc_pdata(host)->ocr_mask = ocr_value; 384987fd49bSBalaji T K } 385db0fefc5SAdrian Hunter 386db0fefc5SAdrian Hunter /* Allow an aux regulator */ 387aa9a6801SKishon Vijay Abraham I mmc->supply.vqmmc = devm_regulator_get_optional(host->dev, "vmmc_aux"); 388aa9a6801SKishon Vijay Abraham I if (IS_ERR(mmc->supply.vqmmc)) { 389aa9a6801SKishon Vijay Abraham I ret = PTR_ERR(mmc->supply.vqmmc); 3906a9b2ff0SKishon Vijay Abraham I if (ret != -ENODEV) 3916a9b2ff0SKishon Vijay Abraham I return ret; 3926a9b2ff0SKishon Vijay Abraham I dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n", 393aa9a6801SKishon Vijay Abraham I PTR_ERR(mmc->supply.vqmmc)); 394aa9a6801SKishon Vijay Abraham I mmc->supply.vqmmc = NULL; 3956a9b2ff0SKishon Vijay Abraham I } 396db0fefc5SAdrian Hunter 397c299dc39SKishon Vijay Abraham I host->pbias = devm_regulator_get_optional(host->dev, "pbias"); 398c299dc39SKishon Vijay Abraham I if (IS_ERR(host->pbias)) { 399c299dc39SKishon Vijay Abraham I ret = PTR_ERR(host->pbias); 4006a9b2ff0SKishon Vijay Abraham I if (ret != -ENODEV) 4016a9b2ff0SKishon Vijay Abraham I return ret; 4026a9b2ff0SKishon Vijay Abraham I dev_dbg(host->dev, "unable to get pbias regulator %ld\n", 403c299dc39SKishon Vijay Abraham I PTR_ERR(host->pbias)); 404c299dc39SKishon Vijay Abraham I host->pbias = NULL; 4056a9b2ff0SKishon Vijay Abraham I } 406e99448ffSBalaji T K 407b1c1df7aSBalaji T K /* For eMMC do not power off when not in sleep state */ 408326119c9SAndreas Fenkart if (mmc_pdata(host)->no_regulator_off_init) 409b1c1df7aSBalaji T K return 0; 410db0fefc5SAdrian Hunter /* 411987fd49bSBalaji T K * To disable boot_on regulator, enable regulator 412987fd49bSBalaji T K * to increase usecount and then disable it. 413db0fefc5SAdrian Hunter */ 414aa9a6801SKishon Vijay Abraham I if ((mmc->supply.vmmc && regulator_is_enabled(mmc->supply.vmmc) > 0) || 415aa9a6801SKishon Vijay Abraham I (mmc->supply.vqmmc && regulator_is_enabled(mmc->supply.vqmmc))) { 416326119c9SAndreas Fenkart int vdd = ffs(mmc_pdata(host)->ocr_mask) - 1; 417e840ce13SAdrian Hunter 418f7f0f035SAndreas Fenkart omap_hsmmc_set_power(host->dev, 1, vdd); 419f7f0f035SAndreas Fenkart omap_hsmmc_set_power(host->dev, 0, 0); 420db0fefc5SAdrian Hunter } 421db0fefc5SAdrian Hunter 422db0fefc5SAdrian Hunter return 0; 423db0fefc5SAdrian Hunter } 424db0fefc5SAdrian Hunter 425b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 426b702b106SAdrian Hunter { 427b702b106SAdrian Hunter return 1; 428b702b106SAdrian Hunter } 429b702b106SAdrian Hunter 430b702b106SAdrian Hunter #else 431b702b106SAdrian Hunter 432f7f0f035SAndreas Fenkart static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd) 433f7f0f035SAndreas Fenkart { 434f7f0f035SAndreas Fenkart return 0; 435f7f0f035SAndreas Fenkart } 436f7f0f035SAndreas Fenkart 437b702b106SAdrian Hunter static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 438b702b106SAdrian Hunter { 439b702b106SAdrian Hunter return -EINVAL; 440b702b106SAdrian Hunter } 441b702b106SAdrian Hunter 442b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 443b702b106SAdrian Hunter { 444b702b106SAdrian Hunter return 0; 445b702b106SAdrian Hunter } 446b702b106SAdrian Hunter 447b702b106SAdrian Hunter #endif 448b702b106SAdrian Hunter 449cde592cbSAndreas Fenkart static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id); 45041afa314SNeilBrown 45141afa314SNeilBrown static int omap_hsmmc_gpio_init(struct mmc_host *mmc, 45241afa314SNeilBrown struct omap_hsmmc_host *host, 4531e363e3bSAndreas Fenkart struct omap_hsmmc_platform_data *pdata) 454b702b106SAdrian Hunter { 455b702b106SAdrian Hunter int ret; 456b702b106SAdrian Hunter 457b7a5646fSAndreas Fenkart if (gpio_is_valid(pdata->gpio_cod)) { 458b7a5646fSAndreas Fenkart ret = mmc_gpio_request_cd(mmc, pdata->gpio_cod, 0); 459b702b106SAdrian Hunter if (ret) 460b702b106SAdrian Hunter return ret; 461cde592cbSAndreas Fenkart 462cde592cbSAndreas Fenkart host->get_cover_state = omap_hsmmc_get_cover_state; 463cde592cbSAndreas Fenkart mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq); 464b7a5646fSAndreas Fenkart } else if (gpio_is_valid(pdata->gpio_cd)) { 465b7a5646fSAndreas Fenkart ret = mmc_gpio_request_cd(mmc, pdata->gpio_cd, 0); 466cde592cbSAndreas Fenkart if (ret) 467cde592cbSAndreas Fenkart return ret; 468cde592cbSAndreas Fenkart 469cde592cbSAndreas Fenkart host->card_detect = omap_hsmmc_card_detect; 470326119c9SAndreas Fenkart } 471b702b106SAdrian Hunter 472326119c9SAndreas Fenkart if (gpio_is_valid(pdata->gpio_wp)) { 47341afa314SNeilBrown ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp); 474b702b106SAdrian Hunter if (ret) 47541afa314SNeilBrown return ret; 476326119c9SAndreas Fenkart } 477b702b106SAdrian Hunter 478b702b106SAdrian Hunter return 0; 479b702b106SAdrian Hunter } 480b702b106SAdrian Hunter 481a45c6cb8SMadhusudhan Chikkature /* 482e0c7f99bSAndy Shevchenko * Start clock to the card 483e0c7f99bSAndy Shevchenko */ 484e0c7f99bSAndy Shevchenko static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 485e0c7f99bSAndy Shevchenko { 486e0c7f99bSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 487e0c7f99bSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 488e0c7f99bSAndy Shevchenko } 489e0c7f99bSAndy Shevchenko 490e0c7f99bSAndy Shevchenko /* 491a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 492a45c6cb8SMadhusudhan Chikkature */ 49370a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 494a45c6cb8SMadhusudhan Chikkature { 495a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 496a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 497a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 4987122bbb0SMasanari Iida dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); 499a45c6cb8SMadhusudhan Chikkature } 500a45c6cb8SMadhusudhan Chikkature 50193caf8e6SAdrian Hunter static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 50293caf8e6SAdrian Hunter struct mmc_command *cmd) 503b417577dSAdrian Hunter { 5042cd3a2a5SAndreas Fenkart u32 irq_mask = INT_EN_MASK; 5052cd3a2a5SAndreas Fenkart unsigned long flags; 506b417577dSAdrian Hunter 507b417577dSAdrian Hunter if (host->use_dma) 5082cd3a2a5SAndreas Fenkart irq_mask &= ~(BRR_EN | BWR_EN); 509b417577dSAdrian Hunter 51093caf8e6SAdrian Hunter /* Disable timeout for erases */ 51193caf8e6SAdrian Hunter if (cmd->opcode == MMC_ERASE) 512a7e96879SVenkatraman S irq_mask &= ~DTO_EN; 51393caf8e6SAdrian Hunter 5142cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 515b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 516b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 5172cd3a2a5SAndreas Fenkart 5182cd3a2a5SAndreas Fenkart /* latch pending CIRQ, but don't signal MMC core */ 5192cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 5202cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 521b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 5222cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 523b417577dSAdrian Hunter } 524b417577dSAdrian Hunter 525b417577dSAdrian Hunter static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 526b417577dSAdrian Hunter { 5272cd3a2a5SAndreas Fenkart u32 irq_mask = 0; 5282cd3a2a5SAndreas Fenkart unsigned long flags; 5292cd3a2a5SAndreas Fenkart 5302cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 5312cd3a2a5SAndreas Fenkart /* no transfer running but need to keep cirq if enabled */ 5322cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 5332cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 5342cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 5352cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 536b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 5372cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 538b417577dSAdrian Hunter } 539b417577dSAdrian Hunter 540ac330f44SAndy Shevchenko /* Calculate divisor for the given clock frequency */ 541d83b6e03SBalaji TK static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 542ac330f44SAndy Shevchenko { 543ac330f44SAndy Shevchenko u16 dsor = 0; 544ac330f44SAndy Shevchenko 545ac330f44SAndy Shevchenko if (ios->clock) { 546d83b6e03SBalaji TK dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 547ed164182SBalaji T K if (dsor > CLKD_MAX) 548ed164182SBalaji T K dsor = CLKD_MAX; 549ac330f44SAndy Shevchenko } 550ac330f44SAndy Shevchenko 551ac330f44SAndy Shevchenko return dsor; 552ac330f44SAndy Shevchenko } 553ac330f44SAndy Shevchenko 5545934df2fSAndy Shevchenko static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 5555934df2fSAndy Shevchenko { 5565934df2fSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5575934df2fSAndy Shevchenko unsigned long regval; 5585934df2fSAndy Shevchenko unsigned long timeout; 559cd587096SHebbar, Gururaja unsigned long clkdiv; 5605934df2fSAndy Shevchenko 5618986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 5625934df2fSAndy Shevchenko 5635934df2fSAndy Shevchenko omap_hsmmc_stop_clock(host); 5645934df2fSAndy Shevchenko 5655934df2fSAndy Shevchenko regval = OMAP_HSMMC_READ(host->base, SYSCTL); 5665934df2fSAndy Shevchenko regval = regval & ~(CLKD_MASK | DTO_MASK); 567cd587096SHebbar, Gururaja clkdiv = calc_divisor(host, ios); 568cd587096SHebbar, Gururaja regval = regval | (clkdiv << 6) | (DTO << 16); 5695934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 5705934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 5715934df2fSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 5725934df2fSAndy Shevchenko 5735934df2fSAndy Shevchenko /* Wait till the ICS bit is set */ 5745934df2fSAndy Shevchenko timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 5755934df2fSAndy Shevchenko while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 5765934df2fSAndy Shevchenko && time_before(jiffies, timeout)) 5775934df2fSAndy Shevchenko cpu_relax(); 5785934df2fSAndy Shevchenko 579cd587096SHebbar, Gururaja /* 580cd587096SHebbar, Gururaja * Enable High-Speed Support 581cd587096SHebbar, Gururaja * Pre-Requisites 582cd587096SHebbar, Gururaja * - Controller should support High-Speed-Enable Bit 583cd587096SHebbar, Gururaja * - Controller should not be using DDR Mode 584cd587096SHebbar, Gururaja * - Controller should advertise that it supports High Speed 585cd587096SHebbar, Gururaja * in capabilities register 586cd587096SHebbar, Gururaja * - MMC/SD clock coming out of controller > 25MHz 587cd587096SHebbar, Gururaja */ 588326119c9SAndreas Fenkart if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) && 5895438ad95SSeungwon Jeon (ios->timing != MMC_TIMING_MMC_DDR52) && 590903101a8SUlf Hansson (ios->timing != MMC_TIMING_UHS_DDR50) && 591cd587096SHebbar, Gururaja ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 592cd587096SHebbar, Gururaja regval = OMAP_HSMMC_READ(host->base, HCTL); 593cd587096SHebbar, Gururaja if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 594cd587096SHebbar, Gururaja regval |= HSPE; 595cd587096SHebbar, Gururaja else 596cd587096SHebbar, Gururaja regval &= ~HSPE; 597cd587096SHebbar, Gururaja 598cd587096SHebbar, Gururaja OMAP_HSMMC_WRITE(host->base, HCTL, regval); 599cd587096SHebbar, Gururaja } 600cd587096SHebbar, Gururaja 6015934df2fSAndy Shevchenko omap_hsmmc_start_clock(host); 6025934df2fSAndy Shevchenko } 6035934df2fSAndy Shevchenko 6043796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 6053796fb8aSAndy Shevchenko { 6063796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6073796fb8aSAndy Shevchenko u32 con; 6083796fb8aSAndy Shevchenko 6093796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 610903101a8SUlf Hansson if (ios->timing == MMC_TIMING_MMC_DDR52 || 611903101a8SUlf Hansson ios->timing == MMC_TIMING_UHS_DDR50) 61203b5d924SBalaji T K con |= DDR; /* configure in DDR mode */ 61303b5d924SBalaji T K else 61403b5d924SBalaji T K con &= ~DDR; 6153796fb8aSAndy Shevchenko switch (ios->bus_width) { 6163796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_8: 6173796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 6183796fb8aSAndy Shevchenko break; 6193796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_4: 6203796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 6213796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 6223796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 6233796fb8aSAndy Shevchenko break; 6243796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_1: 6253796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 6263796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 6273796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 6283796fb8aSAndy Shevchenko break; 6293796fb8aSAndy Shevchenko } 6303796fb8aSAndy Shevchenko } 6313796fb8aSAndy Shevchenko 6323796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 6333796fb8aSAndy Shevchenko { 6343796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6353796fb8aSAndy Shevchenko u32 con; 6363796fb8aSAndy Shevchenko 6373796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 6383796fb8aSAndy Shevchenko if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 6393796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | OD); 6403796fb8aSAndy Shevchenko else 6413796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 6423796fb8aSAndy Shevchenko } 6433796fb8aSAndy Shevchenko 64411dd62a7SDenis Karpov #ifdef CONFIG_PM 64511dd62a7SDenis Karpov 64611dd62a7SDenis Karpov /* 64711dd62a7SDenis Karpov * Restore the MMC host context, if it was lost as result of a 64811dd62a7SDenis Karpov * power state change. 64911dd62a7SDenis Karpov */ 65070a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 65111dd62a7SDenis Karpov { 65211dd62a7SDenis Karpov struct mmc_ios *ios = &host->mmc->ios; 6533796fb8aSAndy Shevchenko u32 hctl, capa; 65411dd62a7SDenis Karpov unsigned long timeout; 65511dd62a7SDenis Karpov 6560a82e06eSTony Lindgren if (host->con == OMAP_HSMMC_READ(host->base, CON) && 6570a82e06eSTony Lindgren host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && 6580a82e06eSTony Lindgren host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && 6590a82e06eSTony Lindgren host->capa == OMAP_HSMMC_READ(host->base, CAPA)) 6600a82e06eSTony Lindgren return 0; 6610a82e06eSTony Lindgren 6620a82e06eSTony Lindgren host->context_loss++; 6630a82e06eSTony Lindgren 664c2200efbSBalaji T K if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 66511dd62a7SDenis Karpov if (host->power_mode != MMC_POWER_OFF && 66611dd62a7SDenis Karpov (1 << ios->vdd) <= MMC_VDD_23_24) 66711dd62a7SDenis Karpov hctl = SDVS18; 66811dd62a7SDenis Karpov else 66911dd62a7SDenis Karpov hctl = SDVS30; 67011dd62a7SDenis Karpov capa = VS30 | VS18; 67111dd62a7SDenis Karpov } else { 67211dd62a7SDenis Karpov hctl = SDVS18; 67311dd62a7SDenis Karpov capa = VS18; 67411dd62a7SDenis Karpov } 67511dd62a7SDenis Karpov 6765a52b08bSBalaji T K if (host->mmc->caps & MMC_CAP_SDIO_IRQ) 6775a52b08bSBalaji T K hctl |= IWE; 6785a52b08bSBalaji T K 67911dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 68011dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | hctl); 68111dd62a7SDenis Karpov 68211dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CAPA, 68311dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA) | capa); 68411dd62a7SDenis Karpov 68511dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 68611dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 68711dd62a7SDenis Karpov 68811dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 68911dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 69011dd62a7SDenis Karpov && time_before(jiffies, timeout)) 69111dd62a7SDenis Karpov ; 69211dd62a7SDenis Karpov 6932cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 6942cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 6952cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 69611dd62a7SDenis Karpov 69711dd62a7SDenis Karpov /* Do not initialize card-specific things if the power is off */ 69811dd62a7SDenis Karpov if (host->power_mode == MMC_POWER_OFF) 69911dd62a7SDenis Karpov goto out; 70011dd62a7SDenis Karpov 7013796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 70211dd62a7SDenis Karpov 7035934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 70411dd62a7SDenis Karpov 7053796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 7063796fb8aSAndy Shevchenko 70711dd62a7SDenis Karpov out: 7080a82e06eSTony Lindgren dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", 7090a82e06eSTony Lindgren host->context_loss); 71011dd62a7SDenis Karpov return 0; 71111dd62a7SDenis Karpov } 71211dd62a7SDenis Karpov 71311dd62a7SDenis Karpov /* 71411dd62a7SDenis Karpov * Save the MMC host context (store the number of power state changes so far). 71511dd62a7SDenis Karpov */ 71670a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 71711dd62a7SDenis Karpov { 7180a82e06eSTony Lindgren host->con = OMAP_HSMMC_READ(host->base, CON); 7190a82e06eSTony Lindgren host->hctl = OMAP_HSMMC_READ(host->base, HCTL); 7200a82e06eSTony Lindgren host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); 7210a82e06eSTony Lindgren host->capa = OMAP_HSMMC_READ(host->base, CAPA); 72211dd62a7SDenis Karpov } 72311dd62a7SDenis Karpov 72411dd62a7SDenis Karpov #else 72511dd62a7SDenis Karpov 72670a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 72711dd62a7SDenis Karpov { 72811dd62a7SDenis Karpov return 0; 72911dd62a7SDenis Karpov } 73011dd62a7SDenis Karpov 73170a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 73211dd62a7SDenis Karpov { 73311dd62a7SDenis Karpov } 73411dd62a7SDenis Karpov 73511dd62a7SDenis Karpov #endif 73611dd62a7SDenis Karpov 737a45c6cb8SMadhusudhan Chikkature /* 738a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 739a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 740a45c6cb8SMadhusudhan Chikkature */ 74170a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host) 742a45c6cb8SMadhusudhan Chikkature { 743a45c6cb8SMadhusudhan Chikkature int reg = 0; 744a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 745a45c6cb8SMadhusudhan Chikkature 746b62f6228SAdrian Hunter if (host->protect_card) 747b62f6228SAdrian Hunter return; 748b62f6228SAdrian Hunter 749a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 750b417577dSAdrian Hunter 751b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 752a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 753a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 754a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 755a45c6cb8SMadhusudhan Chikkature 756a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 757a7e96879SVenkatraman S while ((reg != CC_EN) && time_before(jiffies, timeout)) 758a7e96879SVenkatraman S reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; 759a45c6cb8SMadhusudhan Chikkature 760a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 761a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 762c653a6d4SAdrian Hunter 763c653a6d4SAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 764c653a6d4SAdrian Hunter OMAP_HSMMC_READ(host->base, STAT); 765c653a6d4SAdrian Hunter 766a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 767a45c6cb8SMadhusudhan Chikkature } 768a45c6cb8SMadhusudhan Chikkature 769a45c6cb8SMadhusudhan Chikkature static inline 77070a3341aSDenis Karpov int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 771a45c6cb8SMadhusudhan Chikkature { 772a45c6cb8SMadhusudhan Chikkature int r = 1; 773a45c6cb8SMadhusudhan Chikkature 774b5cd43f0SAndreas Fenkart if (host->get_cover_state) 77580412ca8SAndreas Fenkart r = host->get_cover_state(host->dev); 776a45c6cb8SMadhusudhan Chikkature return r; 777a45c6cb8SMadhusudhan Chikkature } 778a45c6cb8SMadhusudhan Chikkature 779a45c6cb8SMadhusudhan Chikkature static ssize_t 78070a3341aSDenis Karpov omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 781a45c6cb8SMadhusudhan Chikkature char *buf) 782a45c6cb8SMadhusudhan Chikkature { 783a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 78470a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 785a45c6cb8SMadhusudhan Chikkature 78670a3341aSDenis Karpov return sprintf(buf, "%s\n", 78770a3341aSDenis Karpov omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 788a45c6cb8SMadhusudhan Chikkature } 789a45c6cb8SMadhusudhan Chikkature 79070a3341aSDenis Karpov static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 791a45c6cb8SMadhusudhan Chikkature 792a45c6cb8SMadhusudhan Chikkature static ssize_t 79370a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 794a45c6cb8SMadhusudhan Chikkature char *buf) 795a45c6cb8SMadhusudhan Chikkature { 796a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 79770a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 798a45c6cb8SMadhusudhan Chikkature 799326119c9SAndreas Fenkart return sprintf(buf, "%s\n", mmc_pdata(host)->name); 800a45c6cb8SMadhusudhan Chikkature } 801a45c6cb8SMadhusudhan Chikkature 80270a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 803a45c6cb8SMadhusudhan Chikkature 804a45c6cb8SMadhusudhan Chikkature /* 805a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 806a45c6cb8SMadhusudhan Chikkature */ 807a45c6cb8SMadhusudhan Chikkature static void 80870a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 809a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 810a45c6cb8SMadhusudhan Chikkature { 811a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 812a45c6cb8SMadhusudhan Chikkature 8138986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 814a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 815a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 816a45c6cb8SMadhusudhan Chikkature 81793caf8e6SAdrian Hunter omap_hsmmc_enable_irq(host, cmd); 818a45c6cb8SMadhusudhan Chikkature 8194a694dc9SAdrian Hunter host->response_busy = 0; 820a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 821a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 822a45c6cb8SMadhusudhan Chikkature resptype = 1; 8234a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 8244a694dc9SAdrian Hunter resptype = 3; 8254a694dc9SAdrian Hunter host->response_busy = 1; 8264a694dc9SAdrian Hunter } else 827a45c6cb8SMadhusudhan Chikkature resptype = 2; 828a45c6cb8SMadhusudhan Chikkature } 829a45c6cb8SMadhusudhan Chikkature 830a45c6cb8SMadhusudhan Chikkature /* 831a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 832a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 833a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 834a45c6cb8SMadhusudhan Chikkature */ 835a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 836a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 837a45c6cb8SMadhusudhan Chikkature 838a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 839a45c6cb8SMadhusudhan Chikkature 840a2e77152SBalaji T K if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) && 841a2e77152SBalaji T K host->mrq->sbc) { 842a2e77152SBalaji T K cmdreg |= ACEN_ACMD23; 843a2e77152SBalaji T K OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg); 844a2e77152SBalaji T K } 845a45c6cb8SMadhusudhan Chikkature if (data) { 846a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 847a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 848a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 849a45c6cb8SMadhusudhan Chikkature else 850a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 851a45c6cb8SMadhusudhan Chikkature } 852a45c6cb8SMadhusudhan Chikkature 853a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 854a7e96879SVenkatraman S cmdreg |= DMAE; 855a45c6cb8SMadhusudhan Chikkature 856b417577dSAdrian Hunter host->req_in_progress = 1; 8574dffd7a2SAdrian Hunter 858a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 859a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 860a45c6cb8SMadhusudhan Chikkature } 861a45c6cb8SMadhusudhan Chikkature 8620ccd76d4SJuha Yrjola static int 86370a3341aSDenis Karpov omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 8640ccd76d4SJuha Yrjola { 8650ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) 8660ccd76d4SJuha Yrjola return DMA_TO_DEVICE; 8670ccd76d4SJuha Yrjola else 8680ccd76d4SJuha Yrjola return DMA_FROM_DEVICE; 8690ccd76d4SJuha Yrjola } 8700ccd76d4SJuha Yrjola 871c5c98927SRussell King static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 872c5c98927SRussell King struct mmc_data *data) 873c5c98927SRussell King { 874c5c98927SRussell King return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 875c5c98927SRussell King } 876c5c98927SRussell King 877b417577dSAdrian Hunter static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 878b417577dSAdrian Hunter { 879b417577dSAdrian Hunter int dma_ch; 88031463b14SVenkatraman S unsigned long flags; 881b417577dSAdrian Hunter 88231463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 883b417577dSAdrian Hunter host->req_in_progress = 0; 884b417577dSAdrian Hunter dma_ch = host->dma_ch; 88531463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 886b417577dSAdrian Hunter 887b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 888b417577dSAdrian Hunter /* Do not complete the request if DMA is still in progress */ 889b417577dSAdrian Hunter if (mrq->data && host->use_dma && dma_ch != -1) 890b417577dSAdrian Hunter return; 891b417577dSAdrian Hunter host->mrq = NULL; 892b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 893f57ba4caSNeilBrown pm_runtime_mark_last_busy(host->dev); 894f57ba4caSNeilBrown pm_runtime_put_autosuspend(host->dev); 895b417577dSAdrian Hunter } 896b417577dSAdrian Hunter 897a45c6cb8SMadhusudhan Chikkature /* 898a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 899a45c6cb8SMadhusudhan Chikkature */ 900a45c6cb8SMadhusudhan Chikkature static void 90170a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 902a45c6cb8SMadhusudhan Chikkature { 9034a694dc9SAdrian Hunter if (!data) { 9044a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 9054a694dc9SAdrian Hunter 90623050103SAdrian Hunter /* TC before CC from CMD6 - don't know why, but it happens */ 90723050103SAdrian Hunter if (host->cmd && host->cmd->opcode == 6 && 90823050103SAdrian Hunter host->response_busy) { 90923050103SAdrian Hunter host->response_busy = 0; 91023050103SAdrian Hunter return; 91123050103SAdrian Hunter } 91223050103SAdrian Hunter 913b417577dSAdrian Hunter omap_hsmmc_request_done(host, mrq); 9144a694dc9SAdrian Hunter return; 9154a694dc9SAdrian Hunter } 9164a694dc9SAdrian Hunter 917a45c6cb8SMadhusudhan Chikkature host->data = NULL; 918a45c6cb8SMadhusudhan Chikkature 919a45c6cb8SMadhusudhan Chikkature if (!data->error) 920a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 921a45c6cb8SMadhusudhan Chikkature else 922a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 923a45c6cb8SMadhusudhan Chikkature 924bf129e1cSBalaji T K if (data->stop && (data->error || !host->mrq->sbc)) 925fe852273SMing Lei omap_hsmmc_start_command(host, data->stop, NULL); 926bf129e1cSBalaji T K else 927bf129e1cSBalaji T K omap_hsmmc_request_done(host, data->mrq); 928a45c6cb8SMadhusudhan Chikkature } 929a45c6cb8SMadhusudhan Chikkature 930a45c6cb8SMadhusudhan Chikkature /* 931a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 932a45c6cb8SMadhusudhan Chikkature */ 933a45c6cb8SMadhusudhan Chikkature static void 93470a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 935a45c6cb8SMadhusudhan Chikkature { 936bf129e1cSBalaji T K if (host->mrq->sbc && (host->cmd == host->mrq->sbc) && 937a2e77152SBalaji T K !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) { 9382177fa94SBalaji T K host->cmd = NULL; 939bf129e1cSBalaji T K omap_hsmmc_start_dma_transfer(host); 940bf129e1cSBalaji T K omap_hsmmc_start_command(host, host->mrq->cmd, 941bf129e1cSBalaji T K host->mrq->data); 942bf129e1cSBalaji T K return; 943bf129e1cSBalaji T K } 944bf129e1cSBalaji T K 9452177fa94SBalaji T K host->cmd = NULL; 9462177fa94SBalaji T K 947a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 948a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 949a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 950a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 951a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 952a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 953a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 954a45c6cb8SMadhusudhan Chikkature } else { 955a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 956a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 957a45c6cb8SMadhusudhan Chikkature } 958a45c6cb8SMadhusudhan Chikkature } 959b417577dSAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) 960d4b2c375SBalaji T K omap_hsmmc_request_done(host, host->mrq); 961a45c6cb8SMadhusudhan Chikkature } 962a45c6cb8SMadhusudhan Chikkature 963a45c6cb8SMadhusudhan Chikkature /* 964a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 965a45c6cb8SMadhusudhan Chikkature */ 96670a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 967a45c6cb8SMadhusudhan Chikkature { 968b417577dSAdrian Hunter int dma_ch; 96931463b14SVenkatraman S unsigned long flags; 970b417577dSAdrian Hunter 97182788ff5SJarkko Lavinen host->data->error = errno; 972a45c6cb8SMadhusudhan Chikkature 97331463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 974b417577dSAdrian Hunter dma_ch = host->dma_ch; 975b417577dSAdrian Hunter host->dma_ch = -1; 97631463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 977b417577dSAdrian Hunter 978b417577dSAdrian Hunter if (host->use_dma && dma_ch != -1) { 979c5c98927SRussell King struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 980c5c98927SRussell King 981c5c98927SRussell King dmaengine_terminate_all(chan); 982c5c98927SRussell King dma_unmap_sg(chan->device->dev, 983c5c98927SRussell King host->data->sg, host->data->sg_len, 98470a3341aSDenis Karpov omap_hsmmc_get_dma_dir(host, host->data)); 985c5c98927SRussell King 986053bf34fSPer Forlin host->data->host_cookie = 0; 987a45c6cb8SMadhusudhan Chikkature } 988a45c6cb8SMadhusudhan Chikkature host->data = NULL; 989a45c6cb8SMadhusudhan Chikkature } 990a45c6cb8SMadhusudhan Chikkature 991a45c6cb8SMadhusudhan Chikkature /* 992a45c6cb8SMadhusudhan Chikkature * Readable error output 993a45c6cb8SMadhusudhan Chikkature */ 994a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 995699b958bSAdrian Hunter static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 996a45c6cb8SMadhusudhan Chikkature { 997a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 99870a3341aSDenis Karpov static const char *omap_hsmmc_status_bits[] = { 999699b958bSAdrian Hunter "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 1000699b958bSAdrian Hunter "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 1001699b958bSAdrian Hunter "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 1002699b958bSAdrian Hunter "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 1003a45c6cb8SMadhusudhan Chikkature }; 1004a45c6cb8SMadhusudhan Chikkature char res[256]; 1005a45c6cb8SMadhusudhan Chikkature char *buf = res; 1006a45c6cb8SMadhusudhan Chikkature int len, i; 1007a45c6cb8SMadhusudhan Chikkature 1008a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 1009a45c6cb8SMadhusudhan Chikkature buf += len; 1010a45c6cb8SMadhusudhan Chikkature 101170a3341aSDenis Karpov for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 1012a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 101370a3341aSDenis Karpov len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 1014a45c6cb8SMadhusudhan Chikkature buf += len; 1015a45c6cb8SMadhusudhan Chikkature } 1016a45c6cb8SMadhusudhan Chikkature 10178986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 1018a45c6cb8SMadhusudhan Chikkature } 1019699b958bSAdrian Hunter #else 1020699b958bSAdrian Hunter static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 1021699b958bSAdrian Hunter u32 status) 1022699b958bSAdrian Hunter { 1023699b958bSAdrian Hunter } 1024a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 1025a45c6cb8SMadhusudhan Chikkature 10263ebf74b1SJean Pihet /* 10273ebf74b1SJean Pihet * MMC controller internal state machines reset 10283ebf74b1SJean Pihet * 10293ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 10303ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 10313ebf74b1SJean Pihet * Can be called from interrupt context 10323ebf74b1SJean Pihet */ 103370a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 10343ebf74b1SJean Pihet unsigned long bit) 10353ebf74b1SJean Pihet { 10363ebf74b1SJean Pihet unsigned long i = 0; 10371e881786SJianpeng Ma unsigned long limit = MMC_TIMEOUT_US; 10383ebf74b1SJean Pihet 10393ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 10403ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 10413ebf74b1SJean Pihet 104207ad64b6SMadhusudhan Chikkature /* 104307ad64b6SMadhusudhan Chikkature * OMAP4 ES2 and greater has an updated reset logic. 104407ad64b6SMadhusudhan Chikkature * Monitor a 0->1 transition first 104507ad64b6SMadhusudhan Chikkature */ 1046326119c9SAndreas Fenkart if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) { 1047b432b4b3Skishore kadiyala while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 104807ad64b6SMadhusudhan Chikkature && (i++ < limit)) 10491e881786SJianpeng Ma udelay(1); 105007ad64b6SMadhusudhan Chikkature } 105107ad64b6SMadhusudhan Chikkature i = 0; 105207ad64b6SMadhusudhan Chikkature 10533ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 10543ebf74b1SJean Pihet (i++ < limit)) 10551e881786SJianpeng Ma udelay(1); 10563ebf74b1SJean Pihet 10573ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 10583ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 10593ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 10603ebf74b1SJean Pihet __func__); 10613ebf74b1SJean Pihet } 1062a45c6cb8SMadhusudhan Chikkature 106325e1897bSBalaji T K static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, 106425e1897bSBalaji T K int err, int end_cmd) 1065ae4bf788SVenkatraman S { 106625e1897bSBalaji T K if (end_cmd) { 106794d4f272SBalaji T K omap_hsmmc_reset_controller_fsm(host, SRC); 106825e1897bSBalaji T K if (host->cmd) 1069ae4bf788SVenkatraman S host->cmd->error = err; 107025e1897bSBalaji T K } 1071ae4bf788SVenkatraman S 1072ae4bf788SVenkatraman S if (host->data) { 1073ae4bf788SVenkatraman S omap_hsmmc_reset_controller_fsm(host, SRD); 1074ae4bf788SVenkatraman S omap_hsmmc_dma_cleanup(host, err); 1075dc7745bdSBalaji T K } else if (host->mrq && host->mrq->cmd) 1076dc7745bdSBalaji T K host->mrq->cmd->error = err; 1077ae4bf788SVenkatraman S } 1078ae4bf788SVenkatraman S 1079b417577dSAdrian Hunter static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1080a45c6cb8SMadhusudhan Chikkature { 1081a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 1082b417577dSAdrian Hunter int end_cmd = 0, end_trans = 0; 1083a2e77152SBalaji T K int error = 0; 1084a45c6cb8SMadhusudhan Chikkature 1085a45c6cb8SMadhusudhan Chikkature data = host->data; 10868986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1087a45c6cb8SMadhusudhan Chikkature 1088a7e96879SVenkatraman S if (status & ERR_EN) { 1089699b958bSAdrian Hunter omap_hsmmc_dbg_report_irq(host, status); 10904a694dc9SAdrian Hunter 1091a7e96879SVenkatraman S if (status & (CTO_EN | CCRC_EN)) 1092a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1093408806f7SKishon Vijay Abraham I if (host->data || host->response_busy) { 1094408806f7SKishon Vijay Abraham I end_trans = !end_cmd; 1095408806f7SKishon Vijay Abraham I host->response_busy = 0; 1096408806f7SKishon Vijay Abraham I } 1097a7e96879SVenkatraman S if (status & (CTO_EN | DTO_EN)) 109825e1897bSBalaji T K hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); 10995027cd1eSVignesh R else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN | 11005027cd1eSVignesh R BADA_EN)) 110125e1897bSBalaji T K hsmmc_command_incomplete(host, -EILSEQ, end_cmd); 110225e1897bSBalaji T K 1103a2e77152SBalaji T K if (status & ACE_EN) { 1104a2e77152SBalaji T K u32 ac12; 1105a2e77152SBalaji T K ac12 = OMAP_HSMMC_READ(host->base, AC12); 1106a2e77152SBalaji T K if (!(ac12 & ACNE) && host->mrq->sbc) { 1107a2e77152SBalaji T K end_cmd = 1; 1108a2e77152SBalaji T K if (ac12 & ACTO) 1109a2e77152SBalaji T K error = -ETIMEDOUT; 1110a2e77152SBalaji T K else if (ac12 & (ACCE | ACEB | ACIE)) 1111a2e77152SBalaji T K error = -EILSEQ; 1112a2e77152SBalaji T K host->mrq->sbc->error = error; 1113a2e77152SBalaji T K hsmmc_command_incomplete(host, error, end_cmd); 1114a2e77152SBalaji T K } 1115a2e77152SBalaji T K dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12); 1116a2e77152SBalaji T K } 1117a45c6cb8SMadhusudhan Chikkature } 1118a45c6cb8SMadhusudhan Chikkature 11197472bab2SFrancesco Lavra OMAP_HSMMC_WRITE(host->base, STAT, status); 1120a7e96879SVenkatraman S if (end_cmd || ((status & CC_EN) && host->cmd)) 112170a3341aSDenis Karpov omap_hsmmc_cmd_done(host, host->cmd); 1122a7e96879SVenkatraman S if ((end_trans || (status & TC_EN)) && host->mrq) 112370a3341aSDenis Karpov omap_hsmmc_xfer_done(host, data); 1124b417577dSAdrian Hunter } 1125a45c6cb8SMadhusudhan Chikkature 1126b417577dSAdrian Hunter /* 1127b417577dSAdrian Hunter * MMC controller IRQ handler 1128b417577dSAdrian Hunter */ 1129b417577dSAdrian Hunter static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1130b417577dSAdrian Hunter { 1131b417577dSAdrian Hunter struct omap_hsmmc_host *host = dev_id; 1132b417577dSAdrian Hunter int status; 1133b417577dSAdrian Hunter 1134b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 11352cd3a2a5SAndreas Fenkart while (status & (INT_EN_MASK | CIRQ_EN)) { 11362cd3a2a5SAndreas Fenkart if (host->req_in_progress) 1137b417577dSAdrian Hunter omap_hsmmc_do_irq(host, status); 11381f6b9fa4SVenkatraman S 11392cd3a2a5SAndreas Fenkart if (status & CIRQ_EN) 11402cd3a2a5SAndreas Fenkart mmc_signal_sdio_irq(host->mmc); 11412cd3a2a5SAndreas Fenkart 1142b417577dSAdrian Hunter /* Flush posted write */ 1143b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 11441f6b9fa4SVenkatraman S } 11454dffd7a2SAdrian Hunter 1146a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1147a45c6cb8SMadhusudhan Chikkature } 1148a45c6cb8SMadhusudhan Chikkature 114970a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host) 1150e13bb300SAdrian Hunter { 1151e13bb300SAdrian Hunter unsigned long i; 1152e13bb300SAdrian Hunter 1153e13bb300SAdrian Hunter OMAP_HSMMC_WRITE(host->base, HCTL, 1154e13bb300SAdrian Hunter OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1155e13bb300SAdrian Hunter for (i = 0; i < loops_per_jiffy; i++) { 1156e13bb300SAdrian Hunter if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1157e13bb300SAdrian Hunter break; 1158e13bb300SAdrian Hunter cpu_relax(); 1159e13bb300SAdrian Hunter } 1160e13bb300SAdrian Hunter } 1161e13bb300SAdrian Hunter 1162a45c6cb8SMadhusudhan Chikkature /* 1163eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 1164eb250826SDavid Brownell * 1165eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1166eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1167eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 1168a45c6cb8SMadhusudhan Chikkature */ 116970a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1170a45c6cb8SMadhusudhan Chikkature { 1171a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 1172a45c6cb8SMadhusudhan Chikkature int ret; 1173a45c6cb8SMadhusudhan Chikkature 1174a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 1175fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 1176cd03d9a8SRajendra Nayak if (host->dbclk) 117794c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 1178a45c6cb8SMadhusudhan Chikkature 1179a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 1180f7f0f035SAndreas Fenkart ret = omap_hsmmc_set_power(host->dev, 0, 0); 1181a45c6cb8SMadhusudhan Chikkature 1182a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 11832bec0893SAdrian Hunter if (!ret) 1184f7f0f035SAndreas Fenkart ret = omap_hsmmc_set_power(host->dev, 1, vdd); 1185fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1186cd03d9a8SRajendra Nayak if (host->dbclk) 118794c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 11882bec0893SAdrian Hunter 1189a45c6cb8SMadhusudhan Chikkature if (ret != 0) 1190a45c6cb8SMadhusudhan Chikkature goto err; 1191a45c6cb8SMadhusudhan Chikkature 1192a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1193a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1194a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1195eb250826SDavid Brownell 1196a45c6cb8SMadhusudhan Chikkature /* 1197a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 1198a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 119970a3341aSDenis Karpov * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1200a45c6cb8SMadhusudhan Chikkature * 1201eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 1202eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1203eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 1204eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1205eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 1206eb250826SDavid Brownell * 1207eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 1208eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1209eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1210a45c6cb8SMadhusudhan Chikkature */ 1211eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 1212a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 1213eb250826SDavid Brownell else 1214eb250826SDavid Brownell reg_val |= SDVS30; 1215a45c6cb8SMadhusudhan Chikkature 1216a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1217e13bb300SAdrian Hunter set_sd_bus_power(host); 1218a45c6cb8SMadhusudhan Chikkature 1219a45c6cb8SMadhusudhan Chikkature return 0; 1220a45c6cb8SMadhusudhan Chikkature err: 1221b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1222a45c6cb8SMadhusudhan Chikkature return ret; 1223a45c6cb8SMadhusudhan Chikkature } 1224a45c6cb8SMadhusudhan Chikkature 1225b62f6228SAdrian Hunter /* Protect the card while the cover is open */ 1226b62f6228SAdrian Hunter static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1227b62f6228SAdrian Hunter { 1228b5cd43f0SAndreas Fenkart if (!host->get_cover_state) 1229b62f6228SAdrian Hunter return; 1230b62f6228SAdrian Hunter 1231b62f6228SAdrian Hunter host->reqs_blocked = 0; 123280412ca8SAndreas Fenkart if (host->get_cover_state(host->dev)) { 1233b62f6228SAdrian Hunter if (host->protect_card) { 12342cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is closed, " 1235b62f6228SAdrian Hunter "card is now accessible\n", 1236b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1237b62f6228SAdrian Hunter host->protect_card = 0; 1238b62f6228SAdrian Hunter } 1239b62f6228SAdrian Hunter } else { 1240b62f6228SAdrian Hunter if (!host->protect_card) { 12412cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is open, " 1242b62f6228SAdrian Hunter "card is now inaccessible\n", 1243b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1244b62f6228SAdrian Hunter host->protect_card = 1; 1245b62f6228SAdrian Hunter } 1246b62f6228SAdrian Hunter } 1247b62f6228SAdrian Hunter } 1248b62f6228SAdrian Hunter 1249a45c6cb8SMadhusudhan Chikkature /* 1250cde592cbSAndreas Fenkart * irq handler when (cell-phone) cover is mounted/removed 1251cde592cbSAndreas Fenkart */ 1252cde592cbSAndreas Fenkart static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id) 1253cde592cbSAndreas Fenkart { 1254cde592cbSAndreas Fenkart struct omap_hsmmc_host *host = dev_id; 1255cde592cbSAndreas Fenkart 1256cde592cbSAndreas Fenkart sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1257cde592cbSAndreas Fenkart 1258cde592cbSAndreas Fenkart omap_hsmmc_protect_card(host); 1259cde592cbSAndreas Fenkart mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1260cde592cbSAndreas Fenkart return IRQ_HANDLED; 1261cde592cbSAndreas Fenkart } 1262cde592cbSAndreas Fenkart 1263c5c98927SRussell King static void omap_hsmmc_dma_callback(void *param) 12640ccd76d4SJuha Yrjola { 1265c5c98927SRussell King struct omap_hsmmc_host *host = param; 1266c5c98927SRussell King struct dma_chan *chan; 1267770d7432SAdrian Hunter struct mmc_data *data; 1268c5c98927SRussell King int req_in_progress; 1269a45c6cb8SMadhusudhan Chikkature 1270c5c98927SRussell King spin_lock_irq(&host->irq_lock); 1271b417577dSAdrian Hunter if (host->dma_ch < 0) { 1272c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1273a45c6cb8SMadhusudhan Chikkature return; 1274b417577dSAdrian Hunter } 1275a45c6cb8SMadhusudhan Chikkature 1276770d7432SAdrian Hunter data = host->mrq->data; 1277c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 12789782aff8SPer Forlin if (!data->host_cookie) 1279c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1280c5c98927SRussell King data->sg, data->sg_len, 1281b417577dSAdrian Hunter omap_hsmmc_get_dma_dir(host, data)); 1282b417577dSAdrian Hunter 1283b417577dSAdrian Hunter req_in_progress = host->req_in_progress; 1284a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1285c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1286b417577dSAdrian Hunter 1287b417577dSAdrian Hunter /* If DMA has finished after TC, complete the request */ 1288b417577dSAdrian Hunter if (!req_in_progress) { 1289b417577dSAdrian Hunter struct mmc_request *mrq = host->mrq; 1290b417577dSAdrian Hunter 1291b417577dSAdrian Hunter host->mrq = NULL; 1292b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 1293f57ba4caSNeilBrown pm_runtime_mark_last_busy(host->dev); 1294f57ba4caSNeilBrown pm_runtime_put_autosuspend(host->dev); 1295b417577dSAdrian Hunter } 1296a45c6cb8SMadhusudhan Chikkature } 1297a45c6cb8SMadhusudhan Chikkature 12989782aff8SPer Forlin static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 12999782aff8SPer Forlin struct mmc_data *data, 1300c5c98927SRussell King struct omap_hsmmc_next *next, 130126b88520SRussell King struct dma_chan *chan) 13029782aff8SPer Forlin { 13039782aff8SPer Forlin int dma_len; 13049782aff8SPer Forlin 13059782aff8SPer Forlin if (!next && data->host_cookie && 13069782aff8SPer Forlin data->host_cookie != host->next_data.cookie) { 13072cecdf00SRajendra Nayak dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 13089782aff8SPer Forlin " host->next_data.cookie %d\n", 13099782aff8SPer Forlin __func__, data->host_cookie, host->next_data.cookie); 13109782aff8SPer Forlin data->host_cookie = 0; 13119782aff8SPer Forlin } 13129782aff8SPer Forlin 13139782aff8SPer Forlin /* Check if next job is already prepared */ 1314b38313d6SDan Carpenter if (next || data->host_cookie != host->next_data.cookie) { 131526b88520SRussell King dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 13169782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 13179782aff8SPer Forlin 13189782aff8SPer Forlin } else { 13199782aff8SPer Forlin dma_len = host->next_data.dma_len; 13209782aff8SPer Forlin host->next_data.dma_len = 0; 13219782aff8SPer Forlin } 13229782aff8SPer Forlin 13239782aff8SPer Forlin 13249782aff8SPer Forlin if (dma_len == 0) 13259782aff8SPer Forlin return -EINVAL; 13269782aff8SPer Forlin 13279782aff8SPer Forlin if (next) { 13289782aff8SPer Forlin next->dma_len = dma_len; 13299782aff8SPer Forlin data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 13309782aff8SPer Forlin } else 13319782aff8SPer Forlin host->dma_len = dma_len; 13329782aff8SPer Forlin 13339782aff8SPer Forlin return 0; 13349782aff8SPer Forlin } 13359782aff8SPer Forlin 1336a45c6cb8SMadhusudhan Chikkature /* 1337a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 1338a45c6cb8SMadhusudhan Chikkature */ 13399d025334SBalaji T K static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host, 134070a3341aSDenis Karpov struct mmc_request *req) 1341a45c6cb8SMadhusudhan Chikkature { 134226b88520SRussell King struct dma_slave_config cfg; 134326b88520SRussell King struct dma_async_tx_descriptor *tx; 134426b88520SRussell King int ret = 0, i; 1345a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 1346c5c98927SRussell King struct dma_chan *chan; 1347a45c6cb8SMadhusudhan Chikkature 13480ccd76d4SJuha Yrjola /* Sanity check: all the SG entries must be aligned by block size. */ 1349a3f406f8SJarkko Lavinen for (i = 0; i < data->sg_len; i++) { 13500ccd76d4SJuha Yrjola struct scatterlist *sgl; 13510ccd76d4SJuha Yrjola 13520ccd76d4SJuha Yrjola sgl = data->sg + i; 13530ccd76d4SJuha Yrjola if (sgl->length % data->blksz) 13540ccd76d4SJuha Yrjola return -EINVAL; 13550ccd76d4SJuha Yrjola } 13560ccd76d4SJuha Yrjola if ((data->blksz % 4) != 0) 13570ccd76d4SJuha Yrjola /* REVISIT: The MMC buffer increments only when MSB is written. 13580ccd76d4SJuha Yrjola * Return error for blksz which is non multiple of four. 13590ccd76d4SJuha Yrjola */ 13600ccd76d4SJuha Yrjola return -EINVAL; 13610ccd76d4SJuha Yrjola 1362b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1363a45c6cb8SMadhusudhan Chikkature 1364c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 1365c5c98927SRussell King 1366c5c98927SRussell King cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA; 1367c5c98927SRussell King cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA; 1368c5c98927SRussell King cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1369c5c98927SRussell King cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1370c5c98927SRussell King cfg.src_maxburst = data->blksz / 4; 1371c5c98927SRussell King cfg.dst_maxburst = data->blksz / 4; 1372c5c98927SRussell King 1373c5c98927SRussell King ret = dmaengine_slave_config(chan, &cfg); 13749782aff8SPer Forlin if (ret) 13759782aff8SPer Forlin return ret; 1376a45c6cb8SMadhusudhan Chikkature 137726b88520SRussell King ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1378c5c98927SRussell King if (ret) 1379c5c98927SRussell King return ret; 1380a45c6cb8SMadhusudhan Chikkature 1381c5c98927SRussell King tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1382c5c98927SRussell King data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1383c5c98927SRussell King DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1384c5c98927SRussell King if (!tx) { 1385c5c98927SRussell King dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1386c5c98927SRussell King /* FIXME: cleanup */ 1387c5c98927SRussell King return -1; 1388c5c98927SRussell King } 1389c5c98927SRussell King 1390c5c98927SRussell King tx->callback = omap_hsmmc_dma_callback; 1391c5c98927SRussell King tx->callback_param = host; 1392c5c98927SRussell King 1393c5c98927SRussell King /* Does not fail */ 1394c5c98927SRussell King dmaengine_submit(tx); 1395c5c98927SRussell King 139626b88520SRussell King host->dma_ch = 1; 1397c5c98927SRussell King 1398a45c6cb8SMadhusudhan Chikkature return 0; 1399a45c6cb8SMadhusudhan Chikkature } 1400a45c6cb8SMadhusudhan Chikkature 140170a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host, 1402e2bf08d6SAdrian Hunter unsigned int timeout_ns, 1403e2bf08d6SAdrian Hunter unsigned int timeout_clks) 1404a45c6cb8SMadhusudhan Chikkature { 1405a45c6cb8SMadhusudhan Chikkature unsigned int timeout, cycle_ns; 1406a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 1407a45c6cb8SMadhusudhan Chikkature 1408a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1409a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1410a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 1411a45c6cb8SMadhusudhan Chikkature clkd = 1; 1412a45c6cb8SMadhusudhan Chikkature 14136e3076c2SBalaji T K cycle_ns = 1000000000 / (host->clk_rate / clkd); 1414e2bf08d6SAdrian Hunter timeout = timeout_ns / cycle_ns; 1415e2bf08d6SAdrian Hunter timeout += timeout_clks; 1416a45c6cb8SMadhusudhan Chikkature if (timeout) { 1417a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 1418a45c6cb8SMadhusudhan Chikkature dto += 1; 1419a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1420a45c6cb8SMadhusudhan Chikkature } 1421a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 1422a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1423a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 1424a45c6cb8SMadhusudhan Chikkature dto += 1; 1425a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 1426a45c6cb8SMadhusudhan Chikkature dto -= 13; 1427a45c6cb8SMadhusudhan Chikkature else 1428a45c6cb8SMadhusudhan Chikkature dto = 0; 1429a45c6cb8SMadhusudhan Chikkature if (dto > 14) 1430a45c6cb8SMadhusudhan Chikkature dto = 14; 1431a45c6cb8SMadhusudhan Chikkature } 1432a45c6cb8SMadhusudhan Chikkature 1433a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 1434a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 1435a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1436a45c6cb8SMadhusudhan Chikkature } 1437a45c6cb8SMadhusudhan Chikkature 14389d025334SBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host) 14399d025334SBalaji T K { 14409d025334SBalaji T K struct mmc_request *req = host->mrq; 14419d025334SBalaji T K struct dma_chan *chan; 14429d025334SBalaji T K 14439d025334SBalaji T K if (!req->data) 14449d025334SBalaji T K return; 14459d025334SBalaji T K OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 14469d025334SBalaji T K | (req->data->blocks << 16)); 14479d025334SBalaji T K set_data_timeout(host, req->data->timeout_ns, 14489d025334SBalaji T K req->data->timeout_clks); 14499d025334SBalaji T K chan = omap_hsmmc_get_dma_chan(host, req->data); 14509d025334SBalaji T K dma_async_issue_pending(chan); 14519d025334SBalaji T K } 14529d025334SBalaji T K 1453a45c6cb8SMadhusudhan Chikkature /* 1454a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 1455a45c6cb8SMadhusudhan Chikkature */ 1456a45c6cb8SMadhusudhan Chikkature static int 145770a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1458a45c6cb8SMadhusudhan Chikkature { 1459a45c6cb8SMadhusudhan Chikkature int ret; 1460a45c6cb8SMadhusudhan Chikkature host->data = req->data; 1461a45c6cb8SMadhusudhan Chikkature 1462a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 1463a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 1464e2bf08d6SAdrian Hunter /* 1465e2bf08d6SAdrian Hunter * Set an arbitrary 100ms data timeout for commands with 1466e2bf08d6SAdrian Hunter * busy signal. 1467e2bf08d6SAdrian Hunter */ 1468e2bf08d6SAdrian Hunter if (req->cmd->flags & MMC_RSP_BUSY) 1469e2bf08d6SAdrian Hunter set_data_timeout(host, 100000000U, 0); 1470a45c6cb8SMadhusudhan Chikkature return 0; 1471a45c6cb8SMadhusudhan Chikkature } 1472a45c6cb8SMadhusudhan Chikkature 1473a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 14749d025334SBalaji T K ret = omap_hsmmc_setup_dma_transfer(host, req); 1475a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 1476b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); 1477a45c6cb8SMadhusudhan Chikkature return ret; 1478a45c6cb8SMadhusudhan Chikkature } 1479a45c6cb8SMadhusudhan Chikkature } 1480a45c6cb8SMadhusudhan Chikkature return 0; 1481a45c6cb8SMadhusudhan Chikkature } 1482a45c6cb8SMadhusudhan Chikkature 14839782aff8SPer Forlin static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 14849782aff8SPer Forlin int err) 14859782aff8SPer Forlin { 14869782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 14879782aff8SPer Forlin struct mmc_data *data = mrq->data; 14889782aff8SPer Forlin 148926b88520SRussell King if (host->use_dma && data->host_cookie) { 1490c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1491c5c98927SRussell King 149226b88520SRussell King dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 14939782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 14949782aff8SPer Forlin data->host_cookie = 0; 14959782aff8SPer Forlin } 14969782aff8SPer Forlin } 14979782aff8SPer Forlin 14989782aff8SPer Forlin static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 14999782aff8SPer Forlin bool is_first_req) 15009782aff8SPer Forlin { 15019782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15029782aff8SPer Forlin 15039782aff8SPer Forlin if (mrq->data->host_cookie) { 15049782aff8SPer Forlin mrq->data->host_cookie = 0; 15059782aff8SPer Forlin return ; 15069782aff8SPer Forlin } 15079782aff8SPer Forlin 1508c5c98927SRussell King if (host->use_dma) { 1509c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1510c5c98927SRussell King 15119782aff8SPer Forlin if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 151226b88520SRussell King &host->next_data, c)) 15139782aff8SPer Forlin mrq->data->host_cookie = 0; 15149782aff8SPer Forlin } 1515c5c98927SRussell King } 15169782aff8SPer Forlin 1517a45c6cb8SMadhusudhan Chikkature /* 1518a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 1519a45c6cb8SMadhusudhan Chikkature */ 152070a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1521a45c6cb8SMadhusudhan Chikkature { 152270a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1523a3f406f8SJarkko Lavinen int err; 1524a45c6cb8SMadhusudhan Chikkature 1525b417577dSAdrian Hunter BUG_ON(host->req_in_progress); 1526b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1527f57ba4caSNeilBrown pm_runtime_get_sync(host->dev); 1528b62f6228SAdrian Hunter if (host->protect_card) { 1529b62f6228SAdrian Hunter if (host->reqs_blocked < 3) { 1530b62f6228SAdrian Hunter /* 1531b62f6228SAdrian Hunter * Ensure the controller is left in a consistent 1532b62f6228SAdrian Hunter * state by resetting the command and data state 1533b62f6228SAdrian Hunter * machines. 1534b62f6228SAdrian Hunter */ 1535b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRD); 1536b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRC); 1537b62f6228SAdrian Hunter host->reqs_blocked += 1; 1538b62f6228SAdrian Hunter } 1539b62f6228SAdrian Hunter req->cmd->error = -EBADF; 1540b62f6228SAdrian Hunter if (req->data) 1541b62f6228SAdrian Hunter req->data->error = -EBADF; 1542b417577dSAdrian Hunter req->cmd->retries = 0; 1543b62f6228SAdrian Hunter mmc_request_done(mmc, req); 1544f57ba4caSNeilBrown pm_runtime_mark_last_busy(host->dev); 1545f57ba4caSNeilBrown pm_runtime_put_autosuspend(host->dev); 1546b62f6228SAdrian Hunter return; 1547b62f6228SAdrian Hunter } else if (host->reqs_blocked) 1548b62f6228SAdrian Hunter host->reqs_blocked = 0; 1549a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 1550a45c6cb8SMadhusudhan Chikkature host->mrq = req; 15516e3076c2SBalaji T K host->clk_rate = clk_get_rate(host->fclk); 155270a3341aSDenis Karpov err = omap_hsmmc_prepare_data(host, req); 1553a3f406f8SJarkko Lavinen if (err) { 1554a3f406f8SJarkko Lavinen req->cmd->error = err; 1555a3f406f8SJarkko Lavinen if (req->data) 1556a3f406f8SJarkko Lavinen req->data->error = err; 1557a3f406f8SJarkko Lavinen host->mrq = NULL; 1558a3f406f8SJarkko Lavinen mmc_request_done(mmc, req); 1559f57ba4caSNeilBrown pm_runtime_mark_last_busy(host->dev); 1560f57ba4caSNeilBrown pm_runtime_put_autosuspend(host->dev); 1561a3f406f8SJarkko Lavinen return; 1562a3f406f8SJarkko Lavinen } 1563a2e77152SBalaji T K if (req->sbc && !(host->flags & AUTO_CMD23)) { 1564bf129e1cSBalaji T K omap_hsmmc_start_command(host, req->sbc, NULL); 1565bf129e1cSBalaji T K return; 1566bf129e1cSBalaji T K } 1567a3f406f8SJarkko Lavinen 15689d025334SBalaji T K omap_hsmmc_start_dma_transfer(host); 156970a3341aSDenis Karpov omap_hsmmc_start_command(host, req->cmd, req->data); 1570a45c6cb8SMadhusudhan Chikkature } 1571a45c6cb8SMadhusudhan Chikkature 1572a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 157370a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1574a45c6cb8SMadhusudhan Chikkature { 157570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1576a3621465SAdrian Hunter int do_send_init_stream = 0; 1577a45c6cb8SMadhusudhan Chikkature 1578fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 15795e2ea617SAdrian Hunter 1580a3621465SAdrian Hunter if (ios->power_mode != host->power_mode) { 1581a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 1582a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 1583f7f0f035SAndreas Fenkart omap_hsmmc_set_power(host->dev, 0, 0); 1584a45c6cb8SMadhusudhan Chikkature break; 1585a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 1586f7f0f035SAndreas Fenkart omap_hsmmc_set_power(host->dev, 1, ios->vdd); 1587a45c6cb8SMadhusudhan Chikkature break; 1588a3621465SAdrian Hunter case MMC_POWER_ON: 1589a3621465SAdrian Hunter do_send_init_stream = 1; 1590a3621465SAdrian Hunter break; 1591a3621465SAdrian Hunter } 1592a3621465SAdrian Hunter host->power_mode = ios->power_mode; 1593a45c6cb8SMadhusudhan Chikkature } 1594a45c6cb8SMadhusudhan Chikkature 1595dd498effSDenis Karpov /* FIXME: set registers based only on changes to ios */ 1596dd498effSDenis Karpov 15973796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 1598a45c6cb8SMadhusudhan Chikkature 15994621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1600eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 1601eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 1602eb250826SDavid Brownell */ 1603a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 16042cf171cbSBalaji T K (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1605a45c6cb8SMadhusudhan Chikkature /* 1606a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 1607a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 1608a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 1609a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 1610a45c6cb8SMadhusudhan Chikkature */ 161170a3341aSDenis Karpov if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1612a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1613a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 1614a45c6cb8SMadhusudhan Chikkature } 1615a45c6cb8SMadhusudhan Chikkature } 1616a45c6cb8SMadhusudhan Chikkature 16175934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 1618a45c6cb8SMadhusudhan Chikkature 1619a3621465SAdrian Hunter if (do_send_init_stream) 1620a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 1621a45c6cb8SMadhusudhan Chikkature 16223796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 16235e2ea617SAdrian Hunter 1624fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1625a45c6cb8SMadhusudhan Chikkature } 1626a45c6cb8SMadhusudhan Chikkature 1627a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1628a45c6cb8SMadhusudhan Chikkature { 162970a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1630a45c6cb8SMadhusudhan Chikkature 1631b5cd43f0SAndreas Fenkart if (!host->card_detect) 1632a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 163380412ca8SAndreas Fenkart return host->card_detect(host->dev); 1634a45c6cb8SMadhusudhan Chikkature } 1635a45c6cb8SMadhusudhan Chikkature 16364816858cSGrazvydas Ignotas static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 16374816858cSGrazvydas Ignotas { 16384816858cSGrazvydas Ignotas struct omap_hsmmc_host *host = mmc_priv(mmc); 16394816858cSGrazvydas Ignotas 1640326119c9SAndreas Fenkart if (mmc_pdata(host)->init_card) 1641326119c9SAndreas Fenkart mmc_pdata(host)->init_card(card); 16424816858cSGrazvydas Ignotas } 16434816858cSGrazvydas Ignotas 16442cd3a2a5SAndreas Fenkart static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 16452cd3a2a5SAndreas Fenkart { 16462cd3a2a5SAndreas Fenkart struct omap_hsmmc_host *host = mmc_priv(mmc); 16475a52b08bSBalaji T K u32 irq_mask, con; 16482cd3a2a5SAndreas Fenkart unsigned long flags; 16492cd3a2a5SAndreas Fenkart 16502cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 16512cd3a2a5SAndreas Fenkart 16525a52b08bSBalaji T K con = OMAP_HSMMC_READ(host->base, CON); 16532cd3a2a5SAndreas Fenkart irq_mask = OMAP_HSMMC_READ(host->base, ISE); 16542cd3a2a5SAndreas Fenkart if (enable) { 16552cd3a2a5SAndreas Fenkart host->flags |= HSMMC_SDIO_IRQ_ENABLED; 16562cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 16575a52b08bSBalaji T K con |= CTPL | CLKEXTFREE; 16582cd3a2a5SAndreas Fenkart } else { 16592cd3a2a5SAndreas Fenkart host->flags &= ~HSMMC_SDIO_IRQ_ENABLED; 16602cd3a2a5SAndreas Fenkart irq_mask &= ~CIRQ_EN; 16615a52b08bSBalaji T K con &= ~(CTPL | CLKEXTFREE); 16622cd3a2a5SAndreas Fenkart } 16635a52b08bSBalaji T K OMAP_HSMMC_WRITE(host->base, CON, con); 16642cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 16652cd3a2a5SAndreas Fenkart 16662cd3a2a5SAndreas Fenkart /* 16672cd3a2a5SAndreas Fenkart * if enable, piggy back detection on current request 16682cd3a2a5SAndreas Fenkart * but always disable immediately 16692cd3a2a5SAndreas Fenkart */ 16702cd3a2a5SAndreas Fenkart if (!host->req_in_progress || !enable) 16712cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 16722cd3a2a5SAndreas Fenkart 16732cd3a2a5SAndreas Fenkart /* flush posted write */ 16742cd3a2a5SAndreas Fenkart OMAP_HSMMC_READ(host->base, IE); 16752cd3a2a5SAndreas Fenkart 16762cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 16772cd3a2a5SAndreas Fenkart } 16782cd3a2a5SAndreas Fenkart 16792cd3a2a5SAndreas Fenkart static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host) 16802cd3a2a5SAndreas Fenkart { 16812cd3a2a5SAndreas Fenkart int ret; 16822cd3a2a5SAndreas Fenkart 16832cd3a2a5SAndreas Fenkart /* 16842cd3a2a5SAndreas Fenkart * For omaps with wake-up path, wakeirq will be irq from pinctrl and 16852cd3a2a5SAndreas Fenkart * for other omaps, wakeirq will be from GPIO (dat line remuxed to 16862cd3a2a5SAndreas Fenkart * gpio). wakeirq is needed to detect sdio irq in runtime suspend state 16872cd3a2a5SAndreas Fenkart * with functional clock disabled. 16882cd3a2a5SAndreas Fenkart */ 16892cd3a2a5SAndreas Fenkart if (!host->dev->of_node || !host->wake_irq) 16902cd3a2a5SAndreas Fenkart return -ENODEV; 16912cd3a2a5SAndreas Fenkart 16925b83b223STony Lindgren ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq); 16932cd3a2a5SAndreas Fenkart if (ret) { 16942cd3a2a5SAndreas Fenkart dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n"); 16952cd3a2a5SAndreas Fenkart goto err; 16962cd3a2a5SAndreas Fenkart } 16972cd3a2a5SAndreas Fenkart 16982cd3a2a5SAndreas Fenkart /* 16992cd3a2a5SAndreas Fenkart * Some omaps don't have wake-up path from deeper idle states 17002cd3a2a5SAndreas Fenkart * and need to remux SDIO DAT1 to GPIO for wake-up from idle. 17012cd3a2a5SAndreas Fenkart */ 17022cd3a2a5SAndreas Fenkart if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) { 1703455e5cd6SAndreas Fenkart struct pinctrl *p = devm_pinctrl_get(host->dev); 1704455e5cd6SAndreas Fenkart if (!p) { 17052cd3a2a5SAndreas Fenkart ret = -ENODEV; 1706455e5cd6SAndreas Fenkart goto err_free_irq; 1707455e5cd6SAndreas Fenkart } 1708455e5cd6SAndreas Fenkart if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) { 1709455e5cd6SAndreas Fenkart dev_info(host->dev, "missing default pinctrl state\n"); 1710455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 1711455e5cd6SAndreas Fenkart ret = -EINVAL; 1712455e5cd6SAndreas Fenkart goto err_free_irq; 1713455e5cd6SAndreas Fenkart } 1714455e5cd6SAndreas Fenkart 1715455e5cd6SAndreas Fenkart if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) { 1716455e5cd6SAndreas Fenkart dev_info(host->dev, "missing idle pinctrl state\n"); 1717455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 1718455e5cd6SAndreas Fenkart ret = -EINVAL; 1719455e5cd6SAndreas Fenkart goto err_free_irq; 1720455e5cd6SAndreas Fenkart } 1721455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 17222cd3a2a5SAndreas Fenkart } 17232cd3a2a5SAndreas Fenkart 17245a52b08bSBalaji T K OMAP_HSMMC_WRITE(host->base, HCTL, 17255a52b08bSBalaji T K OMAP_HSMMC_READ(host->base, HCTL) | IWE); 17262cd3a2a5SAndreas Fenkart return 0; 17272cd3a2a5SAndreas Fenkart 1728455e5cd6SAndreas Fenkart err_free_irq: 17295b83b223STony Lindgren dev_pm_clear_wake_irq(host->dev); 17302cd3a2a5SAndreas Fenkart err: 17312cd3a2a5SAndreas Fenkart dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n"); 17322cd3a2a5SAndreas Fenkart host->wake_irq = 0; 17332cd3a2a5SAndreas Fenkart return ret; 17342cd3a2a5SAndreas Fenkart } 17352cd3a2a5SAndreas Fenkart 173670a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 17371b331e69SKim Kyuwon { 17381b331e69SKim Kyuwon u32 hctl, capa, value; 17391b331e69SKim Kyuwon 17401b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 17414621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 17421b331e69SKim Kyuwon hctl = SDVS30; 17431b331e69SKim Kyuwon capa = VS30 | VS18; 17441b331e69SKim Kyuwon } else { 17451b331e69SKim Kyuwon hctl = SDVS18; 17461b331e69SKim Kyuwon capa = VS18; 17471b331e69SKim Kyuwon } 17481b331e69SKim Kyuwon 17491b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 17501b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 17511b331e69SKim Kyuwon 17521b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 17531b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 17541b331e69SKim Kyuwon 17551b331e69SKim Kyuwon /* Set SD bus power bit */ 1756e13bb300SAdrian Hunter set_sd_bus_power(host); 17571b331e69SKim Kyuwon } 17581b331e69SKim Kyuwon 1759afd8c29dSKuninori Morimoto static int omap_hsmmc_multi_io_quirk(struct mmc_card *card, 1760afd8c29dSKuninori Morimoto unsigned int direction, int blk_size) 1761afd8c29dSKuninori Morimoto { 1762afd8c29dSKuninori Morimoto /* This controller can't do multiblock reads due to hw bugs */ 1763afd8c29dSKuninori Morimoto if (direction == MMC_DATA_READ) 1764afd8c29dSKuninori Morimoto return 1; 1765afd8c29dSKuninori Morimoto 1766afd8c29dSKuninori Morimoto return blk_size; 1767afd8c29dSKuninori Morimoto } 1768afd8c29dSKuninori Morimoto 1769afd8c29dSKuninori Morimoto static struct mmc_host_ops omap_hsmmc_ops = { 17709782aff8SPer Forlin .post_req = omap_hsmmc_post_req, 17719782aff8SPer Forlin .pre_req = omap_hsmmc_pre_req, 177270a3341aSDenis Karpov .request = omap_hsmmc_request, 177370a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1774dd498effSDenis Karpov .get_cd = omap_hsmmc_get_cd, 1775a49d8353SAndreas Fenkart .get_ro = mmc_gpio_get_ro, 17764816858cSGrazvydas Ignotas .init_card = omap_hsmmc_init_card, 17772cd3a2a5SAndreas Fenkart .enable_sdio_irq = omap_hsmmc_enable_sdio_irq, 1778dd498effSDenis Karpov }; 1779dd498effSDenis Karpov 1780d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS 1781d900f712SDenis Karpov 178270a3341aSDenis Karpov static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1783d900f712SDenis Karpov { 1784d900f712SDenis Karpov struct mmc_host *mmc = s->private; 178570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 178611dd62a7SDenis Karpov 1787bb0635f0SAndreas Fenkart seq_printf(s, "mmc%d:\n", mmc->index); 1788bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq mode\t%s\n", 1789bb0635f0SAndreas Fenkart (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling"); 1790bb0635f0SAndreas Fenkart 1791bb0635f0SAndreas Fenkart if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1792bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq \t%s\n", 1793bb0635f0SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled" 1794bb0635f0SAndreas Fenkart : "disabled"); 1795bb0635f0SAndreas Fenkart } 1796bb0635f0SAndreas Fenkart seq_printf(s, "ctx_loss:\t%d\n", host->context_loss); 17975e2ea617SAdrian Hunter 1798fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1799bb0635f0SAndreas Fenkart seq_puts(s, "\nregs:\n"); 1800d900f712SDenis Karpov seq_printf(s, "CON:\t\t0x%08x\n", 1801d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CON)); 1802bb0635f0SAndreas Fenkart seq_printf(s, "PSTATE:\t\t0x%08x\n", 1803bb0635f0SAndreas Fenkart OMAP_HSMMC_READ(host->base, PSTATE)); 1804d900f712SDenis Karpov seq_printf(s, "HCTL:\t\t0x%08x\n", 1805d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL)); 1806d900f712SDenis Karpov seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1807d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL)); 1808d900f712SDenis Karpov seq_printf(s, "IE:\t\t0x%08x\n", 1809d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, IE)); 1810d900f712SDenis Karpov seq_printf(s, "ISE:\t\t0x%08x\n", 1811d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, ISE)); 1812d900f712SDenis Karpov seq_printf(s, "CAPA:\t\t0x%08x\n", 1813d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA)); 18145e2ea617SAdrian Hunter 1815fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1816fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1817dd498effSDenis Karpov 1818d900f712SDenis Karpov return 0; 1819d900f712SDenis Karpov } 1820d900f712SDenis Karpov 182170a3341aSDenis Karpov static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1822d900f712SDenis Karpov { 182370a3341aSDenis Karpov return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1824d900f712SDenis Karpov } 1825d900f712SDenis Karpov 1826d900f712SDenis Karpov static const struct file_operations mmc_regs_fops = { 182770a3341aSDenis Karpov .open = omap_hsmmc_regs_open, 1828d900f712SDenis Karpov .read = seq_read, 1829d900f712SDenis Karpov .llseek = seq_lseek, 1830d900f712SDenis Karpov .release = single_release, 1831d900f712SDenis Karpov }; 1832d900f712SDenis Karpov 183370a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1834d900f712SDenis Karpov { 1835d900f712SDenis Karpov if (mmc->debugfs_root) 1836d900f712SDenis Karpov debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1837d900f712SDenis Karpov mmc, &mmc_regs_fops); 1838d900f712SDenis Karpov } 1839d900f712SDenis Karpov 1840d900f712SDenis Karpov #else 1841d900f712SDenis Karpov 184270a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1843d900f712SDenis Karpov { 1844d900f712SDenis Karpov } 1845d900f712SDenis Karpov 1846d900f712SDenis Karpov #endif 1847d900f712SDenis Karpov 184846856a68SRajendra Nayak #ifdef CONFIG_OF 184959445b10SNishanth Menon static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = { 185059445b10SNishanth Menon /* See 35xx errata 2.1.1.128 in SPRZ278F */ 185159445b10SNishanth Menon .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 185259445b10SNishanth Menon }; 185359445b10SNishanth Menon 185459445b10SNishanth Menon static const struct omap_mmc_of_data omap4_mmc_of_data = { 185559445b10SNishanth Menon .reg_offset = 0x100, 185659445b10SNishanth Menon }; 18572cd3a2a5SAndreas Fenkart static const struct omap_mmc_of_data am33xx_mmc_of_data = { 18582cd3a2a5SAndreas Fenkart .reg_offset = 0x100, 18592cd3a2a5SAndreas Fenkart .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING, 18602cd3a2a5SAndreas Fenkart }; 186146856a68SRajendra Nayak 186246856a68SRajendra Nayak static const struct of_device_id omap_mmc_of_match[] = { 186346856a68SRajendra Nayak { 186446856a68SRajendra Nayak .compatible = "ti,omap2-hsmmc", 186546856a68SRajendra Nayak }, 186646856a68SRajendra Nayak { 186759445b10SNishanth Menon .compatible = "ti,omap3-pre-es3-hsmmc", 186859445b10SNishanth Menon .data = &omap3_pre_es3_mmc_of_data, 186959445b10SNishanth Menon }, 187059445b10SNishanth Menon { 187146856a68SRajendra Nayak .compatible = "ti,omap3-hsmmc", 187246856a68SRajendra Nayak }, 187346856a68SRajendra Nayak { 187446856a68SRajendra Nayak .compatible = "ti,omap4-hsmmc", 187559445b10SNishanth Menon .data = &omap4_mmc_of_data, 187646856a68SRajendra Nayak }, 18772cd3a2a5SAndreas Fenkart { 18782cd3a2a5SAndreas Fenkart .compatible = "ti,am33xx-hsmmc", 18792cd3a2a5SAndreas Fenkart .data = &am33xx_mmc_of_data, 18802cd3a2a5SAndreas Fenkart }, 188146856a68SRajendra Nayak {}, 1882b6d085f6SChris Ball }; 188346856a68SRajendra Nayak MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 188446856a68SRajendra Nayak 188555143438SAndreas Fenkart static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 188646856a68SRajendra Nayak { 188755143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata; 188846856a68SRajendra Nayak struct device_node *np = dev->of_node; 188946856a68SRajendra Nayak 189046856a68SRajendra Nayak pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 189146856a68SRajendra Nayak if (!pdata) 189219df45bcSBalaji T K return ERR_PTR(-ENOMEM); /* out of memory */ 189346856a68SRajendra Nayak 189446856a68SRajendra Nayak if (of_find_property(np, "ti,dual-volt", NULL)) 189546856a68SRajendra Nayak pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 189646856a68SRajendra Nayak 1897b7a5646fSAndreas Fenkart pdata->gpio_cd = -EINVAL; 1898b7a5646fSAndreas Fenkart pdata->gpio_cod = -EINVAL; 1899fdb9de12SNeilBrown pdata->gpio_wp = -EINVAL; 190046856a68SRajendra Nayak 190146856a68SRajendra Nayak if (of_find_property(np, "ti,non-removable", NULL)) { 1902326119c9SAndreas Fenkart pdata->nonremovable = true; 1903326119c9SAndreas Fenkart pdata->no_regulator_off_init = true; 190446856a68SRajendra Nayak } 190546856a68SRajendra Nayak 190646856a68SRajendra Nayak if (of_find_property(np, "ti,needs-special-reset", NULL)) 1907326119c9SAndreas Fenkart pdata->features |= HSMMC_HAS_UPDATED_RESET; 190846856a68SRajendra Nayak 1909cd587096SHebbar, Gururaja if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) 1910326119c9SAndreas Fenkart pdata->features |= HSMMC_HAS_HSPE_SUPPORT; 1911cd587096SHebbar, Gururaja 191246856a68SRajendra Nayak return pdata; 191346856a68SRajendra Nayak } 191446856a68SRajendra Nayak #else 191555143438SAndreas Fenkart static inline struct omap_hsmmc_platform_data 191646856a68SRajendra Nayak *of_get_hsmmc_pdata(struct device *dev) 191746856a68SRajendra Nayak { 191819df45bcSBalaji T K return ERR_PTR(-EINVAL); 191946856a68SRajendra Nayak } 192046856a68SRajendra Nayak #endif 192146856a68SRajendra Nayak 1922c3be1efdSBill Pemberton static int omap_hsmmc_probe(struct platform_device *pdev) 1923a45c6cb8SMadhusudhan Chikkature { 192455143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data; 1925a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 192670a3341aSDenis Karpov struct omap_hsmmc_host *host = NULL; 1927a45c6cb8SMadhusudhan Chikkature struct resource *res; 1928db0fefc5SAdrian Hunter int ret, irq; 192946856a68SRajendra Nayak const struct of_device_id *match; 193026b88520SRussell King dma_cap_mask_t mask; 193126b88520SRussell King unsigned tx_req, rx_req; 193259445b10SNishanth Menon const struct omap_mmc_of_data *data; 193377fae219SBalaji T K void __iomem *base; 193446856a68SRajendra Nayak 193546856a68SRajendra Nayak match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 193646856a68SRajendra Nayak if (match) { 193746856a68SRajendra Nayak pdata = of_get_hsmmc_pdata(&pdev->dev); 1938dc642c28SJan Luebbe 1939dc642c28SJan Luebbe if (IS_ERR(pdata)) 1940dc642c28SJan Luebbe return PTR_ERR(pdata); 1941dc642c28SJan Luebbe 194246856a68SRajendra Nayak if (match->data) { 194359445b10SNishanth Menon data = match->data; 194459445b10SNishanth Menon pdata->reg_offset = data->reg_offset; 194559445b10SNishanth Menon pdata->controller_flags |= data->controller_flags; 194646856a68SRajendra Nayak } 194746856a68SRajendra Nayak } 1948a45c6cb8SMadhusudhan Chikkature 1949a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 1950a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 1951a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1952a45c6cb8SMadhusudhan Chikkature } 1953a45c6cb8SMadhusudhan Chikkature 1954a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1955a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 1956a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 1957a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1958a45c6cb8SMadhusudhan Chikkature 195977fae219SBalaji T K base = devm_ioremap_resource(&pdev->dev, res); 196077fae219SBalaji T K if (IS_ERR(base)) 196177fae219SBalaji T K return PTR_ERR(base); 1962a45c6cb8SMadhusudhan Chikkature 196370a3341aSDenis Karpov mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 1964a45c6cb8SMadhusudhan Chikkature if (!mmc) { 1965a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 19661e363e3bSAndreas Fenkart goto err; 1967a45c6cb8SMadhusudhan Chikkature } 1968a45c6cb8SMadhusudhan Chikkature 1969fdb9de12SNeilBrown ret = mmc_of_parse(mmc); 1970fdb9de12SNeilBrown if (ret) 1971fdb9de12SNeilBrown goto err1; 1972fdb9de12SNeilBrown 1973a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 1974a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 1975a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 1976a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 1977a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 1978a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1979a45c6cb8SMadhusudhan Chikkature host->irq = irq; 1980fc307df8SBalaji T K host->mapbase = res->start + pdata->reg_offset; 198177fae219SBalaji T K host->base = base + pdata->reg_offset; 19826da20c89SAdrian Hunter host->power_mode = MMC_POWER_OFF; 19839782aff8SPer Forlin host->next_data.cookie = 1; 1984e99448ffSBalaji T K host->pbias_enabled = 0; 1985a45c6cb8SMadhusudhan Chikkature 198641afa314SNeilBrown ret = omap_hsmmc_gpio_init(mmc, host, pdata); 19871e363e3bSAndreas Fenkart if (ret) 19881e363e3bSAndreas Fenkart goto err_gpio; 19891e363e3bSAndreas Fenkart 1990a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 1991a45c6cb8SMadhusudhan Chikkature 19922cd3a2a5SAndreas Fenkart if (pdev->dev.of_node) 19932cd3a2a5SAndreas Fenkart host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1); 19942cd3a2a5SAndreas Fenkart 199570a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ops; 1996dd498effSDenis Karpov 19976b206efeSAndy Shevchenko mmc->f_min = OMAP_MMC_MIN_CLOCK; 1998d418ed87SDaniel Mack 1999d418ed87SDaniel Mack if (pdata->max_freq > 0) 2000d418ed87SDaniel Mack mmc->f_max = pdata->max_freq; 2001fdb9de12SNeilBrown else if (mmc->f_max == 0) 20026b206efeSAndy Shevchenko mmc->f_max = OMAP_MMC_MAX_CLOCK; 2003a45c6cb8SMadhusudhan Chikkature 20044dffd7a2SAdrian Hunter spin_lock_init(&host->irq_lock); 2005a45c6cb8SMadhusudhan Chikkature 20069618195eSBalaji T K host->fclk = devm_clk_get(&pdev->dev, "fck"); 2007a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 2008a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 2009a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 2010a45c6cb8SMadhusudhan Chikkature goto err1; 2011a45c6cb8SMadhusudhan Chikkature } 2012a45c6cb8SMadhusudhan Chikkature 20139b68256cSPaul Walmsley if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 20149b68256cSPaul Walmsley dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 2015afd8c29dSKuninori Morimoto omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk; 20169b68256cSPaul Walmsley } 2017dd498effSDenis Karpov 20185b83b223STony Lindgren device_init_wakeup(&pdev->dev, true); 2019fa4aa2d4SBalaji T K pm_runtime_enable(host->dev); 2020fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2021fa4aa2d4SBalaji T K pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 2022fa4aa2d4SBalaji T K pm_runtime_use_autosuspend(host->dev); 2023a45c6cb8SMadhusudhan Chikkature 202492a3aebfSBalaji T K omap_hsmmc_context_save(host); 202592a3aebfSBalaji T K 20269618195eSBalaji T K host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck"); 2027a45c6cb8SMadhusudhan Chikkature /* 2028a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 2029a45c6cb8SMadhusudhan Chikkature */ 2030cd03d9a8SRajendra Nayak if (IS_ERR(host->dbclk)) { 2031cd03d9a8SRajendra Nayak host->dbclk = NULL; 203294c18149SRajendra Nayak } else if (clk_prepare_enable(host->dbclk) != 0) { 2033cd03d9a8SRajendra Nayak dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 2034cd03d9a8SRajendra Nayak host->dbclk = NULL; 20352bec0893SAdrian Hunter } 2036a45c6cb8SMadhusudhan Chikkature 20370ccd76d4SJuha Yrjola /* Since we do only SG emulation, we can have as many segs 20380ccd76d4SJuha Yrjola * as we want. */ 2039a36274e0SMartin K. Petersen mmc->max_segs = 1024; 20400ccd76d4SJuha Yrjola 2041a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 2042a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 2043a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2044a45c6cb8SMadhusudhan Chikkature mmc->max_seg_size = mmc->max_req_size; 2045a45c6cb8SMadhusudhan Chikkature 204613189e78SJarkko Lavinen mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 204793caf8e6SAdrian Hunter MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 2048a45c6cb8SMadhusudhan Chikkature 2049326119c9SAndreas Fenkart mmc->caps |= mmc_pdata(host)->caps; 20503a63833eSSukumar Ghorai if (mmc->caps & MMC_CAP_8_BIT_DATA) 2051a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 2052a45c6cb8SMadhusudhan Chikkature 2053326119c9SAndreas Fenkart if (mmc_pdata(host)->nonremovable) 205423d99bb9SAdrian Hunter mmc->caps |= MMC_CAP_NONREMOVABLE; 205523d99bb9SAdrian Hunter 2056fdb9de12SNeilBrown mmc->pm_caps |= mmc_pdata(host)->pm_caps; 20576fdc75deSEliad Peller 205870a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 2059a45c6cb8SMadhusudhan Chikkature 20604a29b559SSantosh Shilimkar if (!pdev->dev.of_node) { 2061b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 2062b7bf773bSBalaji T K if (!res) { 2063b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n"); 20649c17d08cSKevin Hilman ret = -ENXIO; 2065f3e2f1ddSGrazvydas Ignotas goto err_irq; 2066a45c6cb8SMadhusudhan Chikkature } 206726b88520SRussell King tx_req = res->start; 2068b7bf773bSBalaji T K 2069b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 2070b7bf773bSBalaji T K if (!res) { 2071b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n"); 20729c17d08cSKevin Hilman ret = -ENXIO; 2073b7bf773bSBalaji T K goto err_irq; 2074b7bf773bSBalaji T K } 207526b88520SRussell King rx_req = res->start; 20764a29b559SSantosh Shilimkar } 2077c5c98927SRussell King 2078c5c98927SRussell King dma_cap_zero(mask); 2079c5c98927SRussell King dma_cap_set(DMA_SLAVE, mask); 208026b88520SRussell King 2081d272fbf0SMatt Porter host->rx_chan = 2082d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 2083d272fbf0SMatt Porter &rx_req, &pdev->dev, "rx"); 2084d272fbf0SMatt Porter 2085c5c98927SRussell King if (!host->rx_chan) { 208626b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req); 208704e8c7bcSKevin Hilman ret = -ENXIO; 208826b88520SRussell King goto err_irq; 2089c5c98927SRussell King } 209026b88520SRussell King 2091d272fbf0SMatt Porter host->tx_chan = 2092d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 2093d272fbf0SMatt Porter &tx_req, &pdev->dev, "tx"); 2094d272fbf0SMatt Porter 2095c5c98927SRussell King if (!host->tx_chan) { 209626b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req); 209704e8c7bcSKevin Hilman ret = -ENXIO; 209826b88520SRussell King goto err_irq; 2099c5c98927SRussell King } 2100a45c6cb8SMadhusudhan Chikkature 2101a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 2102e1538ed7SBalaji T K ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0, 2103a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 2104a45c6cb8SMadhusudhan Chikkature if (ret) { 2105b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 2106a45c6cb8SMadhusudhan Chikkature goto err_irq; 2107a45c6cb8SMadhusudhan Chikkature } 2108a45c6cb8SMadhusudhan Chikkature 2109f7f0f035SAndreas Fenkart if (omap_hsmmc_have_reg()) { 2110db0fefc5SAdrian Hunter ret = omap_hsmmc_reg_get(host); 2111db0fefc5SAdrian Hunter if (ret) 2112bb09d151SAndreas Fenkart goto err_irq; 2113db0fefc5SAdrian Hunter } 2114db0fefc5SAdrian Hunter 2115326119c9SAndreas Fenkart mmc->ocr_avail = mmc_pdata(host)->ocr_mask; 2116a45c6cb8SMadhusudhan Chikkature 2117b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 2118a45c6cb8SMadhusudhan Chikkature 21192cd3a2a5SAndreas Fenkart /* 21202cd3a2a5SAndreas Fenkart * For now, only support SDIO interrupt if we have a separate 21212cd3a2a5SAndreas Fenkart * wake-up interrupt configured from device tree. This is because 21222cd3a2a5SAndreas Fenkart * the wake-up interrupt is needed for idle state and some 21232cd3a2a5SAndreas Fenkart * platforms need special quirks. And we don't want to add new 21242cd3a2a5SAndreas Fenkart * legacy mux platform init code callbacks any longer as we 21252cd3a2a5SAndreas Fenkart * are moving to DT based booting anyways. 21262cd3a2a5SAndreas Fenkart */ 21272cd3a2a5SAndreas Fenkart ret = omap_hsmmc_configure_wake_irq(host); 21282cd3a2a5SAndreas Fenkart if (!ret) 21292cd3a2a5SAndreas Fenkart mmc->caps |= MMC_CAP_SDIO_IRQ; 21302cd3a2a5SAndreas Fenkart 2131b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2132b62f6228SAdrian Hunter 2133a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 2134a45c6cb8SMadhusudhan Chikkature 2135326119c9SAndreas Fenkart if (mmc_pdata(host)->name != NULL) { 2136a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2137a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2138a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 2139a45c6cb8SMadhusudhan Chikkature } 2140cde592cbSAndreas Fenkart if (host->get_cover_state) { 2141a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, 2142a45c6cb8SMadhusudhan Chikkature &dev_attr_cover_switch); 2143a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2144db0fefc5SAdrian Hunter goto err_slot_name; 2145a45c6cb8SMadhusudhan Chikkature } 2146a45c6cb8SMadhusudhan Chikkature 214770a3341aSDenis Karpov omap_hsmmc_debugfs(mmc); 2148fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2149fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2150d900f712SDenis Karpov 2151a45c6cb8SMadhusudhan Chikkature return 0; 2152a45c6cb8SMadhusudhan Chikkature 2153a45c6cb8SMadhusudhan Chikkature err_slot_name: 2154a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 2155a45c6cb8SMadhusudhan Chikkature err_irq: 21565b83b223STony Lindgren device_init_wakeup(&pdev->dev, false); 2157c5c98927SRussell King if (host->tx_chan) 2158c5c98927SRussell King dma_release_channel(host->tx_chan); 2159c5c98927SRussell King if (host->rx_chan) 2160c5c98927SRussell King dma_release_channel(host->rx_chan); 2161d59d77edSBalaji T K pm_runtime_put_sync(host->dev); 216237f6190dSTony Lindgren pm_runtime_disable(host->dev); 21639618195eSBalaji T K if (host->dbclk) 216494c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2165a45c6cb8SMadhusudhan Chikkature err1: 21661e363e3bSAndreas Fenkart err_gpio: 2167a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 2168db0fefc5SAdrian Hunter err: 2169a45c6cb8SMadhusudhan Chikkature return ret; 2170a45c6cb8SMadhusudhan Chikkature } 2171a45c6cb8SMadhusudhan Chikkature 21726e0ee714SBill Pemberton static int omap_hsmmc_remove(struct platform_device *pdev) 2173a45c6cb8SMadhusudhan Chikkature { 217470a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2175a45c6cb8SMadhusudhan Chikkature 2176fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2177a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 2178a45c6cb8SMadhusudhan Chikkature 2179c5c98927SRussell King if (host->tx_chan) 2180c5c98927SRussell King dma_release_channel(host->tx_chan); 2181c5c98927SRussell King if (host->rx_chan) 2182c5c98927SRussell King dma_release_channel(host->rx_chan); 2183c5c98927SRussell King 2184fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2185fa4aa2d4SBalaji T K pm_runtime_disable(host->dev); 21865b83b223STony Lindgren device_init_wakeup(&pdev->dev, false); 21879618195eSBalaji T K if (host->dbclk) 218894c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2189a45c6cb8SMadhusudhan Chikkature 21909d1f0286SBalaji T K mmc_free_host(host->mmc); 2191a45c6cb8SMadhusudhan Chikkature 2192a45c6cb8SMadhusudhan Chikkature return 0; 2193a45c6cb8SMadhusudhan Chikkature } 2194a45c6cb8SMadhusudhan Chikkature 21953d3bbfbdSRuss Dill #ifdef CONFIG_PM_SLEEP 2196a791daa1SKevin Hilman static int omap_hsmmc_suspend(struct device *dev) 2197a45c6cb8SMadhusudhan Chikkature { 2198927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2199927ce944SFelipe Balbi 2200927ce944SFelipe Balbi if (!host) 2201927ce944SFelipe Balbi return 0; 2202a45c6cb8SMadhusudhan Chikkature 2203fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 220431f9d463SEliad Peller 220531f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 22062cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 22072cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 22082cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 220931f9d463SEliad Peller OMAP_HSMMC_WRITE(host->base, HCTL, 221031f9d463SEliad Peller OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 221131f9d463SEliad Peller } 2212927ce944SFelipe Balbi 2213cd03d9a8SRajendra Nayak if (host->dbclk) 221494c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 22153932afd5SUlf Hansson 2216fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 22173932afd5SUlf Hansson return 0; 2218a45c6cb8SMadhusudhan Chikkature } 2219a45c6cb8SMadhusudhan Chikkature 2220a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 2221a791daa1SKevin Hilman static int omap_hsmmc_resume(struct device *dev) 2222a45c6cb8SMadhusudhan Chikkature { 2223927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2224927ce944SFelipe Balbi 2225927ce944SFelipe Balbi if (!host) 2226927ce944SFelipe Balbi return 0; 2227a45c6cb8SMadhusudhan Chikkature 2228fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 222911dd62a7SDenis Karpov 2230cd03d9a8SRajendra Nayak if (host->dbclk) 223194c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 22322bec0893SAdrian Hunter 223331f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 223470a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 22351b331e69SKim Kyuwon 2236b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2237fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2238fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 22393932afd5SUlf Hansson return 0; 2240a45c6cb8SMadhusudhan Chikkature } 2241a45c6cb8SMadhusudhan Chikkature #endif 2242a45c6cb8SMadhusudhan Chikkature 2243fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_suspend(struct device *dev) 2244fa4aa2d4SBalaji T K { 2245fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 22462cd3a2a5SAndreas Fenkart unsigned long flags; 2247f945901fSAndreas Fenkart int ret = 0; 2248fa4aa2d4SBalaji T K 2249fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2250fa4aa2d4SBalaji T K omap_hsmmc_context_save(host); 2251927ce944SFelipe Balbi dev_dbg(dev, "disabled\n"); 2252fa4aa2d4SBalaji T K 22532cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 22542cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 22552cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 22562cd3a2a5SAndreas Fenkart /* disable sdio irq handling to prevent race */ 22572cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 22582cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 2259f945901fSAndreas Fenkart 2260f945901fSAndreas Fenkart if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) { 2261f945901fSAndreas Fenkart /* 2262f945901fSAndreas Fenkart * dat1 line low, pending sdio irq 2263f945901fSAndreas Fenkart * race condition: possible irq handler running on 2264f945901fSAndreas Fenkart * multi-core, abort 2265f945901fSAndreas Fenkart */ 2266f945901fSAndreas Fenkart dev_dbg(dev, "pending sdio irq, abort suspend\n"); 22672cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 2268f945901fSAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 2269f945901fSAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 2270f945901fSAndreas Fenkart pm_runtime_mark_last_busy(dev); 2271f945901fSAndreas Fenkart ret = -EBUSY; 2272f945901fSAndreas Fenkart goto abort; 2273f945901fSAndreas Fenkart } 22742cd3a2a5SAndreas Fenkart 227597978a44SAndreas Fenkart pinctrl_pm_select_idle_state(dev); 227697978a44SAndreas Fenkart } else { 227797978a44SAndreas Fenkart pinctrl_pm_select_idle_state(dev); 22782cd3a2a5SAndreas Fenkart } 227997978a44SAndreas Fenkart 2280f945901fSAndreas Fenkart abort: 22812cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2282f945901fSAndreas Fenkart return ret; 2283fa4aa2d4SBalaji T K } 2284fa4aa2d4SBalaji T K 2285fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_resume(struct device *dev) 2286fa4aa2d4SBalaji T K { 2287fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 22882cd3a2a5SAndreas Fenkart unsigned long flags; 2289fa4aa2d4SBalaji T K 2290fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2291fa4aa2d4SBalaji T K omap_hsmmc_context_restore(host); 2292927ce944SFelipe Balbi dev_dbg(dev, "enabled\n"); 2293fa4aa2d4SBalaji T K 22942cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 22952cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 22962cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 22972cd3a2a5SAndreas Fenkart 229897978a44SAndreas Fenkart pinctrl_pm_select_default_state(host->dev); 229997978a44SAndreas Fenkart 230097978a44SAndreas Fenkart /* irq lost, if pinmux incorrect */ 23012cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 23022cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 23032cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 230497978a44SAndreas Fenkart } else { 230597978a44SAndreas Fenkart pinctrl_pm_select_default_state(host->dev); 23062cd3a2a5SAndreas Fenkart } 23072cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2308fa4aa2d4SBalaji T K return 0; 2309fa4aa2d4SBalaji T K } 2310fa4aa2d4SBalaji T K 2311a791daa1SKevin Hilman static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 23123d3bbfbdSRuss Dill SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume) 2313fa4aa2d4SBalaji T K .runtime_suspend = omap_hsmmc_runtime_suspend, 2314fa4aa2d4SBalaji T K .runtime_resume = omap_hsmmc_runtime_resume, 2315a791daa1SKevin Hilman }; 2316a791daa1SKevin Hilman 2317a791daa1SKevin Hilman static struct platform_driver omap_hsmmc_driver = { 2318efa25fd3SFelipe Balbi .probe = omap_hsmmc_probe, 23190433c143SBill Pemberton .remove = omap_hsmmc_remove, 2320a45c6cb8SMadhusudhan Chikkature .driver = { 2321a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 2322a791daa1SKevin Hilman .pm = &omap_hsmmc_dev_pm_ops, 232346856a68SRajendra Nayak .of_match_table = of_match_ptr(omap_mmc_of_match), 2324a45c6cb8SMadhusudhan Chikkature }, 2325a45c6cb8SMadhusudhan Chikkature }; 2326a45c6cb8SMadhusudhan Chikkature 2327b796450bSFelipe Balbi module_platform_driver(omap_hsmmc_driver); 2328a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2329a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 2330a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 2331a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 2332