1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20ac330f44SAndy Shevchenko #include <linux/kernel.h> 21d900f712SDenis Karpov #include <linux/debugfs.h> 22c5c98927SRussell King #include <linux/dmaengine.h> 23d900f712SDenis Karpov #include <linux/seq_file.h> 24031cd037SFelipe Balbi #include <linux/sizes.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 29a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 30a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 3146856a68SRajendra Nayak #include <linux/of.h> 322cd3a2a5SAndreas Fenkart #include <linux/of_irq.h> 3346856a68SRajendra Nayak #include <linux/of_device.h> 34a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 3513189e78SJarkko Lavinen #include <linux/mmc/core.h> 3693caf8e6SAdrian Hunter #include <linux/mmc/mmc.h> 3741afa314SNeilBrown #include <linux/mmc/slot-gpio.h> 38a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 392cd3a2a5SAndreas Fenkart #include <linux/irq.h> 40db0fefc5SAdrian Hunter #include <linux/regulator/consumer.h> 4146b76035SDaniel Mack #include <linux/pinctrl/consumer.h> 42fa4aa2d4SBalaji T K #include <linux/pm_runtime.h> 435b83b223STony Lindgren #include <linux/pm_wakeirq.h> 4455143438SAndreas Fenkart #include <linux/platform_data/hsmmc-omap.h> 45a45c6cb8SMadhusudhan Chikkature 46a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 4711dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS 0x0014 48a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 49a2e77152SBalaji T K #define OMAP_HSMMC_SDMASA 0x0100 50a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 51a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 52a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 57a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 58bb0635f0SAndreas Fenkart #define OMAP_HSMMC_PSTATE 0x0124 59a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 60a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 61a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 62a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 63a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 64a2e77152SBalaji T K #define OMAP_HSMMC_AC12 0x013C 65a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 66a45c6cb8SMadhusudhan Chikkature 67a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 68a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 69cd587096SHebbar, Gururaja #define HSS (1 << 21) 70a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 71a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 72eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 731b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 74a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 75a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 76a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 77a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 78a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 79a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 80a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 81a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 82ed164182SBalaji T K #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ 83a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 84a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 85a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 86a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 87a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 88a2e77152SBalaji T K #define ACEN_ACMD23 (2 << 2) 89a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 90a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 91a7e96879SVenkatraman S #define DMAE 0x1 92a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 93a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 94a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 95cd587096SHebbar, Gururaja #define HSPE (1 << 2) 965a52b08bSBalaji T K #define IWE (1 << 24) 9703b5d924SBalaji T K #define DDR (1 << 19) 985a52b08bSBalaji T K #define CLKEXTFREE (1 << 16) 995a52b08bSBalaji T K #define CTPL (1 << 11) 10073153010SJarkko Lavinen #define DW8 (1 << 5) 101a45c6cb8SMadhusudhan Chikkature #define OD 0x1 102a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 103a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 104a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 105a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 106a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 10711dd62a7SDenis Karpov #define SOFTRESET (1 << 1) 108a45c6cb8SMadhusudhan Chikkature 109f945901fSAndreas Fenkart /* PSTATE */ 110f945901fSAndreas Fenkart #define DLEV_DAT(x) (1 << (20 + (x))) 111f945901fSAndreas Fenkart 112a7e96879SVenkatraman S /* Interrupt masks for IE and ISE register */ 113a7e96879SVenkatraman S #define CC_EN (1 << 0) 114a7e96879SVenkatraman S #define TC_EN (1 << 1) 115a7e96879SVenkatraman S #define BWR_EN (1 << 4) 116a7e96879SVenkatraman S #define BRR_EN (1 << 5) 1172cd3a2a5SAndreas Fenkart #define CIRQ_EN (1 << 8) 118a7e96879SVenkatraman S #define ERR_EN (1 << 15) 119a7e96879SVenkatraman S #define CTO_EN (1 << 16) 120a7e96879SVenkatraman S #define CCRC_EN (1 << 17) 121a7e96879SVenkatraman S #define CEB_EN (1 << 18) 122a7e96879SVenkatraman S #define CIE_EN (1 << 19) 123a7e96879SVenkatraman S #define DTO_EN (1 << 20) 124a7e96879SVenkatraman S #define DCRC_EN (1 << 21) 125a7e96879SVenkatraman S #define DEB_EN (1 << 22) 126a2e77152SBalaji T K #define ACE_EN (1 << 24) 127a7e96879SVenkatraman S #define CERR_EN (1 << 28) 128a7e96879SVenkatraman S #define BADA_EN (1 << 29) 129a7e96879SVenkatraman S 130a2e77152SBalaji T K #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\ 131a7e96879SVenkatraman S DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ 132a7e96879SVenkatraman S BRR_EN | BWR_EN | TC_EN | CC_EN) 133a7e96879SVenkatraman S 134a2e77152SBalaji T K #define CNI (1 << 7) 135a2e77152SBalaji T K #define ACIE (1 << 4) 136a2e77152SBalaji T K #define ACEB (1 << 3) 137a2e77152SBalaji T K #define ACCE (1 << 2) 138a2e77152SBalaji T K #define ACTO (1 << 1) 139a2e77152SBalaji T K #define ACNE (1 << 0) 140a2e77152SBalaji T K 141fa4aa2d4SBalaji T K #define MMC_AUTOSUSPEND_DELAY 100 1421e881786SJianpeng Ma #define MMC_TIMEOUT_MS 20 /* 20 mSec */ 1431e881786SJianpeng Ma #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ 1446b206efeSAndy Shevchenko #define OMAP_MMC_MIN_CLOCK 400000 1456b206efeSAndy Shevchenko #define OMAP_MMC_MAX_CLOCK 52000000 1460005ae73SKishore Kadiyala #define DRIVER_NAME "omap_hsmmc" 147a45c6cb8SMadhusudhan Chikkature 148a45c6cb8SMadhusudhan Chikkature /* 149a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 150a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 151a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 152a45c6cb8SMadhusudhan Chikkature */ 153326119c9SAndreas Fenkart #define mmc_pdata(host) host->pdata 154a45c6cb8SMadhusudhan Chikkature 155a45c6cb8SMadhusudhan Chikkature /* 156a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 157a45c6cb8SMadhusudhan Chikkature */ 158a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 159a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 160a45c6cb8SMadhusudhan Chikkature 161a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 162a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 163a45c6cb8SMadhusudhan Chikkature 1649782aff8SPer Forlin struct omap_hsmmc_next { 1659782aff8SPer Forlin unsigned int dma_len; 1669782aff8SPer Forlin s32 cookie; 1679782aff8SPer Forlin }; 1689782aff8SPer Forlin 16970a3341aSDenis Karpov struct omap_hsmmc_host { 170a45c6cb8SMadhusudhan Chikkature struct device *dev; 171a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 172a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 173a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 174a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 175a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 176a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 177e99448ffSBalaji T K struct regulator *pbias; 178bb2726b5STony Lindgren bool pbias_enabled; 179a45c6cb8SMadhusudhan Chikkature void __iomem *base; 1803f77f702SKishon Vijay Abraham I int vqmmc_enabled; 181a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 1824dffd7a2SAdrian Hunter spinlock_t irq_lock; /* Prevent races with irq handler */ 183a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 1840ccd76d4SJuha Yrjola unsigned int dma_sg_idx; 185a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 186a3621465SAdrian Hunter unsigned char power_mode; 187a45c6cb8SMadhusudhan Chikkature int suspended; 1880a82e06eSTony Lindgren u32 con; 1890a82e06eSTony Lindgren u32 hctl; 1900a82e06eSTony Lindgren u32 sysctl; 1910a82e06eSTony Lindgren u32 capa; 192a45c6cb8SMadhusudhan Chikkature int irq; 1932cd3a2a5SAndreas Fenkart int wake_irq; 194a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 195c5c98927SRussell King struct dma_chan *tx_chan; 196c5c98927SRussell King struct dma_chan *rx_chan; 1974a694dc9SAdrian Hunter int response_busy; 19811dd62a7SDenis Karpov int context_loss; 199b62f6228SAdrian Hunter int reqs_blocked; 200b417577dSAdrian Hunter int req_in_progress; 2016e3076c2SBalaji T K unsigned long clk_rate; 202a2e77152SBalaji T K unsigned int flags; 2032cd3a2a5SAndreas Fenkart #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */ 2042cd3a2a5SAndreas Fenkart #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */ 2059782aff8SPer Forlin struct omap_hsmmc_next next_data; 20655143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata; 207a45c6cb8SMadhusudhan Chikkature }; 208a45c6cb8SMadhusudhan Chikkature 20959445b10SNishanth Menon struct omap_mmc_of_data { 21059445b10SNishanth Menon u32 reg_offset; 21159445b10SNishanth Menon u8 controller_flags; 21259445b10SNishanth Menon }; 21359445b10SNishanth Menon 214bf129e1cSBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host); 215bf129e1cSBalaji T K 2161d17f30bSKishon Vijay Abraham I static int omap_hsmmc_enable_supply(struct mmc_host *mmc) 2172a17f844SKishon Vijay Abraham I { 2182a17f844SKishon Vijay Abraham I int ret; 2193f77f702SKishon Vijay Abraham I struct omap_hsmmc_host *host = mmc_priv(mmc); 2201d17f30bSKishon Vijay Abraham I struct mmc_ios *ios = &mmc->ios; 2212a17f844SKishon Vijay Abraham I 22286d79da0SKishon Vijay Abraham I if (!IS_ERR(mmc->supply.vmmc)) { 2231d17f30bSKishon Vijay Abraham I ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 2242a17f844SKishon Vijay Abraham I if (ret) 2252a17f844SKishon Vijay Abraham I return ret; 2262a17f844SKishon Vijay Abraham I } 2272a17f844SKishon Vijay Abraham I 2282a17f844SKishon Vijay Abraham I /* Enable interface voltage rail, if needed */ 22986d79da0SKishon Vijay Abraham I if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 2302a17f844SKishon Vijay Abraham I ret = regulator_enable(mmc->supply.vqmmc); 2312a17f844SKishon Vijay Abraham I if (ret) { 2322a17f844SKishon Vijay Abraham I dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n"); 2332a17f844SKishon Vijay Abraham I goto err_vqmmc; 2342a17f844SKishon Vijay Abraham I } 2353f77f702SKishon Vijay Abraham I host->vqmmc_enabled = 1; 2362a17f844SKishon Vijay Abraham I } 2372a17f844SKishon Vijay Abraham I 2382a17f844SKishon Vijay Abraham I return 0; 2392a17f844SKishon Vijay Abraham I 2402a17f844SKishon Vijay Abraham I err_vqmmc: 24186d79da0SKishon Vijay Abraham I if (!IS_ERR(mmc->supply.vmmc)) 2422a17f844SKishon Vijay Abraham I mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 2432a17f844SKishon Vijay Abraham I 2442a17f844SKishon Vijay Abraham I return ret; 2452a17f844SKishon Vijay Abraham I } 2462a17f844SKishon Vijay Abraham I 2472a17f844SKishon Vijay Abraham I static int omap_hsmmc_disable_supply(struct mmc_host *mmc) 2482a17f844SKishon Vijay Abraham I { 2492a17f844SKishon Vijay Abraham I int ret; 2502a17f844SKishon Vijay Abraham I int status; 2513f77f702SKishon Vijay Abraham I struct omap_hsmmc_host *host = mmc_priv(mmc); 2522a17f844SKishon Vijay Abraham I 25386d79da0SKishon Vijay Abraham I if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 2542a17f844SKishon Vijay Abraham I ret = regulator_disable(mmc->supply.vqmmc); 2552a17f844SKishon Vijay Abraham I if (ret) { 2562a17f844SKishon Vijay Abraham I dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n"); 2572a17f844SKishon Vijay Abraham I return ret; 2582a17f844SKishon Vijay Abraham I } 2593f77f702SKishon Vijay Abraham I host->vqmmc_enabled = 0; 2602a17f844SKishon Vijay Abraham I } 2612a17f844SKishon Vijay Abraham I 26286d79da0SKishon Vijay Abraham I if (!IS_ERR(mmc->supply.vmmc)) { 2632a17f844SKishon Vijay Abraham I ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 2642a17f844SKishon Vijay Abraham I if (ret) 2652a17f844SKishon Vijay Abraham I goto err_set_ocr; 2662a17f844SKishon Vijay Abraham I } 2672a17f844SKishon Vijay Abraham I 2682a17f844SKishon Vijay Abraham I return 0; 2692a17f844SKishon Vijay Abraham I 2702a17f844SKishon Vijay Abraham I err_set_ocr: 27186d79da0SKishon Vijay Abraham I if (!IS_ERR(mmc->supply.vqmmc)) { 2722a17f844SKishon Vijay Abraham I status = regulator_enable(mmc->supply.vqmmc); 2732a17f844SKishon Vijay Abraham I if (status) 2742a17f844SKishon Vijay Abraham I dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n"); 2752a17f844SKishon Vijay Abraham I } 2762a17f844SKishon Vijay Abraham I 2772a17f844SKishon Vijay Abraham I return ret; 2782a17f844SKishon Vijay Abraham I } 2792a17f844SKishon Vijay Abraham I 28066162becSKishon Vijay Abraham I static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on) 281ec85c95eSKishon Vijay Abraham I { 282ec85c95eSKishon Vijay Abraham I int ret; 283ec85c95eSKishon Vijay Abraham I 28486d79da0SKishon Vijay Abraham I if (IS_ERR(host->pbias)) 285ec85c95eSKishon Vijay Abraham I return 0; 286ec85c95eSKishon Vijay Abraham I 287ec85c95eSKishon Vijay Abraham I if (power_on) { 288bb2726b5STony Lindgren if (host->pbias_enabled == 0) { 289ec85c95eSKishon Vijay Abraham I ret = regulator_enable(host->pbias); 290ec85c95eSKishon Vijay Abraham I if (ret) { 291ec85c95eSKishon Vijay Abraham I dev_err(host->dev, "pbias reg enable fail\n"); 292ec85c95eSKishon Vijay Abraham I return ret; 293ec85c95eSKishon Vijay Abraham I } 294bb2726b5STony Lindgren host->pbias_enabled = 1; 295ec85c95eSKishon Vijay Abraham I } 296ec85c95eSKishon Vijay Abraham I } else { 297bb2726b5STony Lindgren if (host->pbias_enabled == 1) { 298ec85c95eSKishon Vijay Abraham I ret = regulator_disable(host->pbias); 299ec85c95eSKishon Vijay Abraham I if (ret) { 300ec85c95eSKishon Vijay Abraham I dev_err(host->dev, "pbias reg disable fail\n"); 301ec85c95eSKishon Vijay Abraham I return ret; 302ec85c95eSKishon Vijay Abraham I } 303bb2726b5STony Lindgren host->pbias_enabled = 0; 304ec85c95eSKishon Vijay Abraham I } 305ec85c95eSKishon Vijay Abraham I } 306ec85c95eSKishon Vijay Abraham I 307ec85c95eSKishon Vijay Abraham I return 0; 308ec85c95eSKishon Vijay Abraham I } 309ec85c95eSKishon Vijay Abraham I 31066162becSKishon Vijay Abraham I static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on) 311db0fefc5SAdrian Hunter { 312aa9a6801SKishon Vijay Abraham I struct mmc_host *mmc = host->mmc; 313db0fefc5SAdrian Hunter int ret = 0; 314db0fefc5SAdrian Hunter 315db0fefc5SAdrian Hunter /* 316db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 317db0fefc5SAdrian Hunter * voltage always-on regulator. 318db0fefc5SAdrian Hunter */ 31986d79da0SKishon Vijay Abraham I if (IS_ERR(mmc->supply.vmmc)) 320db0fefc5SAdrian Hunter return 0; 321db0fefc5SAdrian Hunter 32266162becSKishon Vijay Abraham I ret = omap_hsmmc_set_pbias(host, false); 323ec85c95eSKishon Vijay Abraham I if (ret) 324229f3292SKishon Vijay Abraham I return ret; 325e99448ffSBalaji T K 326db0fefc5SAdrian Hunter /* 327db0fefc5SAdrian Hunter * Assume Vcc regulator is used only to power the card ... OMAP 328db0fefc5SAdrian Hunter * VDDS is used to power the pins, optionally with a transceiver to 329db0fefc5SAdrian Hunter * support cards using voltages other than VDDS (1.8V nominal). When a 330db0fefc5SAdrian Hunter * transceiver is used, DAT3..7 are muxed as transceiver control pins. 331db0fefc5SAdrian Hunter * 332db0fefc5SAdrian Hunter * In some cases this regulator won't support enable/disable; 333db0fefc5SAdrian Hunter * e.g. it's a fixed rail for a WLAN chip. 334db0fefc5SAdrian Hunter * 335db0fefc5SAdrian Hunter * In other cases vcc_aux switches interface power. Example, for 336db0fefc5SAdrian Hunter * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 337db0fefc5SAdrian Hunter * chips/cards need an interface voltage rail too. 338db0fefc5SAdrian Hunter */ 339db0fefc5SAdrian Hunter if (power_on) { 3401d17f30bSKishon Vijay Abraham I ret = omap_hsmmc_enable_supply(mmc); 341229f3292SKishon Vijay Abraham I if (ret) 342229f3292SKishon Vijay Abraham I return ret; 34397fe7e5aSKishon Vijay Abraham I 34466162becSKishon Vijay Abraham I ret = omap_hsmmc_set_pbias(host, true); 34597fe7e5aSKishon Vijay Abraham I if (ret) 34697fe7e5aSKishon Vijay Abraham I goto err_set_voltage; 347db0fefc5SAdrian Hunter } else { 3482a17f844SKishon Vijay Abraham I ret = omap_hsmmc_disable_supply(mmc); 349229f3292SKishon Vijay Abraham I if (ret) 350229f3292SKishon Vijay Abraham I return ret; 35199fc5131SLinus Walleij } 352db0fefc5SAdrian Hunter 353229f3292SKishon Vijay Abraham I return 0; 354229f3292SKishon Vijay Abraham I 355229f3292SKishon Vijay Abraham I err_set_voltage: 3562a17f844SKishon Vijay Abraham I omap_hsmmc_disable_supply(mmc); 357229f3292SKishon Vijay Abraham I 358db0fefc5SAdrian Hunter return ret; 359db0fefc5SAdrian Hunter } 360db0fefc5SAdrian Hunter 361c8518efaSKishon Vijay Abraham I static int omap_hsmmc_disable_boot_regulator(struct regulator *reg) 362c8518efaSKishon Vijay Abraham I { 363c8518efaSKishon Vijay Abraham I int ret; 364c8518efaSKishon Vijay Abraham I 36586d79da0SKishon Vijay Abraham I if (IS_ERR(reg)) 366c8518efaSKishon Vijay Abraham I return 0; 367c8518efaSKishon Vijay Abraham I 368c8518efaSKishon Vijay Abraham I if (regulator_is_enabled(reg)) { 369c8518efaSKishon Vijay Abraham I ret = regulator_enable(reg); 370c8518efaSKishon Vijay Abraham I if (ret) 371c8518efaSKishon Vijay Abraham I return ret; 372c8518efaSKishon Vijay Abraham I 373c8518efaSKishon Vijay Abraham I ret = regulator_disable(reg); 374c8518efaSKishon Vijay Abraham I if (ret) 375c8518efaSKishon Vijay Abraham I return ret; 376c8518efaSKishon Vijay Abraham I } 377c8518efaSKishon Vijay Abraham I 378c8518efaSKishon Vijay Abraham I return 0; 379c8518efaSKishon Vijay Abraham I } 380c8518efaSKishon Vijay Abraham I 381c8518efaSKishon Vijay Abraham I static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host) 382c8518efaSKishon Vijay Abraham I { 383c8518efaSKishon Vijay Abraham I struct mmc_host *mmc = host->mmc; 384c8518efaSKishon Vijay Abraham I int ret; 385c8518efaSKishon Vijay Abraham I 386c8518efaSKishon Vijay Abraham I /* 387c8518efaSKishon Vijay Abraham I * disable regulators enabled during boot and get the usecount 388c8518efaSKishon Vijay Abraham I * right so that regulators can be enabled/disabled by checking 389c8518efaSKishon Vijay Abraham I * the return value of regulator_is_enabled 390c8518efaSKishon Vijay Abraham I */ 391c8518efaSKishon Vijay Abraham I ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc); 392c8518efaSKishon Vijay Abraham I if (ret) { 393c8518efaSKishon Vijay Abraham I dev_err(host->dev, "fail to disable boot enabled vmmc reg\n"); 394c8518efaSKishon Vijay Abraham I return ret; 395c8518efaSKishon Vijay Abraham I } 396c8518efaSKishon Vijay Abraham I 397c8518efaSKishon Vijay Abraham I ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc); 398c8518efaSKishon Vijay Abraham I if (ret) { 399c8518efaSKishon Vijay Abraham I dev_err(host->dev, 400c8518efaSKishon Vijay Abraham I "fail to disable boot enabled vmmc_aux reg\n"); 401c8518efaSKishon Vijay Abraham I return ret; 402c8518efaSKishon Vijay Abraham I } 403c8518efaSKishon Vijay Abraham I 404c8518efaSKishon Vijay Abraham I ret = omap_hsmmc_disable_boot_regulator(host->pbias); 405c8518efaSKishon Vijay Abraham I if (ret) { 406c8518efaSKishon Vijay Abraham I dev_err(host->dev, 407c8518efaSKishon Vijay Abraham I "failed to disable boot enabled pbias reg\n"); 408c8518efaSKishon Vijay Abraham I return ret; 409c8518efaSKishon Vijay Abraham I } 410c8518efaSKishon Vijay Abraham I 411c8518efaSKishon Vijay Abraham I return 0; 412c8518efaSKishon Vijay Abraham I } 413c8518efaSKishon Vijay Abraham I 414db0fefc5SAdrian Hunter static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 415db0fefc5SAdrian Hunter { 4167d607f91SKishon Vijay Abraham I int ret; 417aa9a6801SKishon Vijay Abraham I struct mmc_host *mmc = host->mmc; 418db0fefc5SAdrian Hunter 419f7f0f035SAndreas Fenkart 42013ab2a66SKishon Vijay Abraham I ret = mmc_regulator_get_supply(mmc); 4213b649a73SWolfram Sang if (ret) 4227d607f91SKishon Vijay Abraham I return ret; 423db0fefc5SAdrian Hunter 424db0fefc5SAdrian Hunter /* Allow an aux regulator */ 42513ab2a66SKishon Vijay Abraham I if (IS_ERR(mmc->supply.vqmmc)) { 42613ab2a66SKishon Vijay Abraham I mmc->supply.vqmmc = devm_regulator_get_optional(host->dev, 42713ab2a66SKishon Vijay Abraham I "vmmc_aux"); 428aa9a6801SKishon Vijay Abraham I if (IS_ERR(mmc->supply.vqmmc)) { 429aa9a6801SKishon Vijay Abraham I ret = PTR_ERR(mmc->supply.vqmmc); 430123e20b1STony Lindgren if ((ret != -ENODEV) && host->dev->of_node) 4316a9b2ff0SKishon Vijay Abraham I return ret; 4326a9b2ff0SKishon Vijay Abraham I dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n", 433aa9a6801SKishon Vijay Abraham I PTR_ERR(mmc->supply.vqmmc)); 4346a9b2ff0SKishon Vijay Abraham I } 43513ab2a66SKishon Vijay Abraham I } 436db0fefc5SAdrian Hunter 437c299dc39SKishon Vijay Abraham I host->pbias = devm_regulator_get_optional(host->dev, "pbias"); 438c299dc39SKishon Vijay Abraham I if (IS_ERR(host->pbias)) { 439c299dc39SKishon Vijay Abraham I ret = PTR_ERR(host->pbias); 4409143757bSKishon Vijay Abraham I if ((ret != -ENODEV) && host->dev->of_node) { 4419143757bSKishon Vijay Abraham I dev_err(host->dev, 4429143757bSKishon Vijay Abraham I "SD card detect fail? enable CONFIG_REGULATOR_PBIAS\n"); 4436a9b2ff0SKishon Vijay Abraham I return ret; 4449143757bSKishon Vijay Abraham I } 4456a9b2ff0SKishon Vijay Abraham I dev_dbg(host->dev, "unable to get pbias regulator %ld\n", 446c299dc39SKishon Vijay Abraham I PTR_ERR(host->pbias)); 4476a9b2ff0SKishon Vijay Abraham I } 448e99448ffSBalaji T K 449b1c1df7aSBalaji T K /* For eMMC do not power off when not in sleep state */ 450326119c9SAndreas Fenkart if (mmc_pdata(host)->no_regulator_off_init) 451b1c1df7aSBalaji T K return 0; 452e840ce13SAdrian Hunter 453c8518efaSKishon Vijay Abraham I ret = omap_hsmmc_disable_boot_regulators(host); 454c8518efaSKishon Vijay Abraham I if (ret) 455c8518efaSKishon Vijay Abraham I return ret; 456db0fefc5SAdrian Hunter 457db0fefc5SAdrian Hunter return 0; 458db0fefc5SAdrian Hunter } 459db0fefc5SAdrian Hunter 460a45c6cb8SMadhusudhan Chikkature /* 461e0c7f99bSAndy Shevchenko * Start clock to the card 462e0c7f99bSAndy Shevchenko */ 463e0c7f99bSAndy Shevchenko static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 464e0c7f99bSAndy Shevchenko { 465e0c7f99bSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 466e0c7f99bSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 467e0c7f99bSAndy Shevchenko } 468e0c7f99bSAndy Shevchenko 469e0c7f99bSAndy Shevchenko /* 470a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 471a45c6cb8SMadhusudhan Chikkature */ 47270a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 473a45c6cb8SMadhusudhan Chikkature { 474a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 475a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 476a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 4777122bbb0SMasanari Iida dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); 478a45c6cb8SMadhusudhan Chikkature } 479a45c6cb8SMadhusudhan Chikkature 48093caf8e6SAdrian Hunter static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 48193caf8e6SAdrian Hunter struct mmc_command *cmd) 482b417577dSAdrian Hunter { 4832cd3a2a5SAndreas Fenkart u32 irq_mask = INT_EN_MASK; 4842cd3a2a5SAndreas Fenkart unsigned long flags; 485b417577dSAdrian Hunter 486b417577dSAdrian Hunter if (host->use_dma) 4872cd3a2a5SAndreas Fenkart irq_mask &= ~(BRR_EN | BWR_EN); 488b417577dSAdrian Hunter 48993caf8e6SAdrian Hunter /* Disable timeout for erases */ 49093caf8e6SAdrian Hunter if (cmd->opcode == MMC_ERASE) 491a7e96879SVenkatraman S irq_mask &= ~DTO_EN; 49293caf8e6SAdrian Hunter 4932cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 494b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 495b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 4962cd3a2a5SAndreas Fenkart 4972cd3a2a5SAndreas Fenkart /* latch pending CIRQ, but don't signal MMC core */ 4982cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 4992cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 500b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 5012cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 502b417577dSAdrian Hunter } 503b417577dSAdrian Hunter 504b417577dSAdrian Hunter static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 505b417577dSAdrian Hunter { 5062cd3a2a5SAndreas Fenkart u32 irq_mask = 0; 5072cd3a2a5SAndreas Fenkart unsigned long flags; 5082cd3a2a5SAndreas Fenkart 5092cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 5102cd3a2a5SAndreas Fenkart /* no transfer running but need to keep cirq if enabled */ 5112cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 5122cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 5132cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 5142cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 515b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 5162cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 517b417577dSAdrian Hunter } 518b417577dSAdrian Hunter 519ac330f44SAndy Shevchenko /* Calculate divisor for the given clock frequency */ 520d83b6e03SBalaji TK static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 521ac330f44SAndy Shevchenko { 522ac330f44SAndy Shevchenko u16 dsor = 0; 523ac330f44SAndy Shevchenko 524ac330f44SAndy Shevchenko if (ios->clock) { 525d83b6e03SBalaji TK dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 526ed164182SBalaji T K if (dsor > CLKD_MAX) 527ed164182SBalaji T K dsor = CLKD_MAX; 528ac330f44SAndy Shevchenko } 529ac330f44SAndy Shevchenko 530ac330f44SAndy Shevchenko return dsor; 531ac330f44SAndy Shevchenko } 532ac330f44SAndy Shevchenko 5335934df2fSAndy Shevchenko static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 5345934df2fSAndy Shevchenko { 5355934df2fSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5365934df2fSAndy Shevchenko unsigned long regval; 5375934df2fSAndy Shevchenko unsigned long timeout; 538cd587096SHebbar, Gururaja unsigned long clkdiv; 5395934df2fSAndy Shevchenko 5408986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 5415934df2fSAndy Shevchenko 5425934df2fSAndy Shevchenko omap_hsmmc_stop_clock(host); 5435934df2fSAndy Shevchenko 5445934df2fSAndy Shevchenko regval = OMAP_HSMMC_READ(host->base, SYSCTL); 5455934df2fSAndy Shevchenko regval = regval & ~(CLKD_MASK | DTO_MASK); 546cd587096SHebbar, Gururaja clkdiv = calc_divisor(host, ios); 547cd587096SHebbar, Gururaja regval = regval | (clkdiv << 6) | (DTO << 16); 5485934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 5495934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 5505934df2fSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 5515934df2fSAndy Shevchenko 5525934df2fSAndy Shevchenko /* Wait till the ICS bit is set */ 5535934df2fSAndy Shevchenko timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 5545934df2fSAndy Shevchenko while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 5555934df2fSAndy Shevchenko && time_before(jiffies, timeout)) 5565934df2fSAndy Shevchenko cpu_relax(); 5575934df2fSAndy Shevchenko 558cd587096SHebbar, Gururaja /* 559cd587096SHebbar, Gururaja * Enable High-Speed Support 560cd587096SHebbar, Gururaja * Pre-Requisites 561cd587096SHebbar, Gururaja * - Controller should support High-Speed-Enable Bit 562cd587096SHebbar, Gururaja * - Controller should not be using DDR Mode 563cd587096SHebbar, Gururaja * - Controller should advertise that it supports High Speed 564cd587096SHebbar, Gururaja * in capabilities register 565cd587096SHebbar, Gururaja * - MMC/SD clock coming out of controller > 25MHz 566cd587096SHebbar, Gururaja */ 567326119c9SAndreas Fenkart if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) && 5685438ad95SSeungwon Jeon (ios->timing != MMC_TIMING_MMC_DDR52) && 569903101a8SUlf Hansson (ios->timing != MMC_TIMING_UHS_DDR50) && 570cd587096SHebbar, Gururaja ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 571cd587096SHebbar, Gururaja regval = OMAP_HSMMC_READ(host->base, HCTL); 572cd587096SHebbar, Gururaja if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 573cd587096SHebbar, Gururaja regval |= HSPE; 574cd587096SHebbar, Gururaja else 575cd587096SHebbar, Gururaja regval &= ~HSPE; 576cd587096SHebbar, Gururaja 577cd587096SHebbar, Gururaja OMAP_HSMMC_WRITE(host->base, HCTL, regval); 578cd587096SHebbar, Gururaja } 579cd587096SHebbar, Gururaja 5805934df2fSAndy Shevchenko omap_hsmmc_start_clock(host); 5815934df2fSAndy Shevchenko } 5825934df2fSAndy Shevchenko 5833796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 5843796fb8aSAndy Shevchenko { 5853796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5863796fb8aSAndy Shevchenko u32 con; 5873796fb8aSAndy Shevchenko 5883796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 589903101a8SUlf Hansson if (ios->timing == MMC_TIMING_MMC_DDR52 || 590903101a8SUlf Hansson ios->timing == MMC_TIMING_UHS_DDR50) 59103b5d924SBalaji T K con |= DDR; /* configure in DDR mode */ 59203b5d924SBalaji T K else 59303b5d924SBalaji T K con &= ~DDR; 5943796fb8aSAndy Shevchenko switch (ios->bus_width) { 5953796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_8: 5963796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 5973796fb8aSAndy Shevchenko break; 5983796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_4: 5993796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 6003796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 6013796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 6023796fb8aSAndy Shevchenko break; 6033796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_1: 6043796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 6053796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 6063796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 6073796fb8aSAndy Shevchenko break; 6083796fb8aSAndy Shevchenko } 6093796fb8aSAndy Shevchenko } 6103796fb8aSAndy Shevchenko 6113796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 6123796fb8aSAndy Shevchenko { 6133796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6143796fb8aSAndy Shevchenko u32 con; 6153796fb8aSAndy Shevchenko 6163796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 6173796fb8aSAndy Shevchenko if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 6183796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | OD); 6193796fb8aSAndy Shevchenko else 6203796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 6213796fb8aSAndy Shevchenko } 6223796fb8aSAndy Shevchenko 62311dd62a7SDenis Karpov #ifdef CONFIG_PM 62411dd62a7SDenis Karpov 62511dd62a7SDenis Karpov /* 62611dd62a7SDenis Karpov * Restore the MMC host context, if it was lost as result of a 62711dd62a7SDenis Karpov * power state change. 62811dd62a7SDenis Karpov */ 62970a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 63011dd62a7SDenis Karpov { 63111dd62a7SDenis Karpov struct mmc_ios *ios = &host->mmc->ios; 6323796fb8aSAndy Shevchenko u32 hctl, capa; 63311dd62a7SDenis Karpov unsigned long timeout; 63411dd62a7SDenis Karpov 6350a82e06eSTony Lindgren if (host->con == OMAP_HSMMC_READ(host->base, CON) && 6360a82e06eSTony Lindgren host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && 6370a82e06eSTony Lindgren host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && 6380a82e06eSTony Lindgren host->capa == OMAP_HSMMC_READ(host->base, CAPA)) 6390a82e06eSTony Lindgren return 0; 6400a82e06eSTony Lindgren 6410a82e06eSTony Lindgren host->context_loss++; 6420a82e06eSTony Lindgren 643c2200efbSBalaji T K if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 64411dd62a7SDenis Karpov if (host->power_mode != MMC_POWER_OFF && 64511dd62a7SDenis Karpov (1 << ios->vdd) <= MMC_VDD_23_24) 64611dd62a7SDenis Karpov hctl = SDVS18; 64711dd62a7SDenis Karpov else 64811dd62a7SDenis Karpov hctl = SDVS30; 64911dd62a7SDenis Karpov capa = VS30 | VS18; 65011dd62a7SDenis Karpov } else { 65111dd62a7SDenis Karpov hctl = SDVS18; 65211dd62a7SDenis Karpov capa = VS18; 65311dd62a7SDenis Karpov } 65411dd62a7SDenis Karpov 6555a52b08bSBalaji T K if (host->mmc->caps & MMC_CAP_SDIO_IRQ) 6565a52b08bSBalaji T K hctl |= IWE; 6575a52b08bSBalaji T K 65811dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 65911dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | hctl); 66011dd62a7SDenis Karpov 66111dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CAPA, 66211dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA) | capa); 66311dd62a7SDenis Karpov 66411dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 66511dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 66611dd62a7SDenis Karpov 66711dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 66811dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 66911dd62a7SDenis Karpov && time_before(jiffies, timeout)) 67011dd62a7SDenis Karpov ; 67111dd62a7SDenis Karpov 6722cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 6732cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 6742cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 67511dd62a7SDenis Karpov 67611dd62a7SDenis Karpov /* Do not initialize card-specific things if the power is off */ 67711dd62a7SDenis Karpov if (host->power_mode == MMC_POWER_OFF) 67811dd62a7SDenis Karpov goto out; 67911dd62a7SDenis Karpov 6803796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 68111dd62a7SDenis Karpov 6825934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 68311dd62a7SDenis Karpov 6843796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 6853796fb8aSAndy Shevchenko 68611dd62a7SDenis Karpov out: 6870a82e06eSTony Lindgren dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", 6880a82e06eSTony Lindgren host->context_loss); 68911dd62a7SDenis Karpov return 0; 69011dd62a7SDenis Karpov } 69111dd62a7SDenis Karpov 69211dd62a7SDenis Karpov /* 69311dd62a7SDenis Karpov * Save the MMC host context (store the number of power state changes so far). 69411dd62a7SDenis Karpov */ 69570a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 69611dd62a7SDenis Karpov { 6970a82e06eSTony Lindgren host->con = OMAP_HSMMC_READ(host->base, CON); 6980a82e06eSTony Lindgren host->hctl = OMAP_HSMMC_READ(host->base, HCTL); 6990a82e06eSTony Lindgren host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); 7000a82e06eSTony Lindgren host->capa = OMAP_HSMMC_READ(host->base, CAPA); 70111dd62a7SDenis Karpov } 70211dd62a7SDenis Karpov 70311dd62a7SDenis Karpov #else 70411dd62a7SDenis Karpov 70570a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 70611dd62a7SDenis Karpov { 70711dd62a7SDenis Karpov return 0; 70811dd62a7SDenis Karpov } 70911dd62a7SDenis Karpov 71070a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 71111dd62a7SDenis Karpov { 71211dd62a7SDenis Karpov } 71311dd62a7SDenis Karpov 71411dd62a7SDenis Karpov #endif 71511dd62a7SDenis Karpov 716a45c6cb8SMadhusudhan Chikkature /* 717a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 718a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 719a45c6cb8SMadhusudhan Chikkature */ 72070a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host) 721a45c6cb8SMadhusudhan Chikkature { 722a45c6cb8SMadhusudhan Chikkature int reg = 0; 723a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 724a45c6cb8SMadhusudhan Chikkature 725a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 726b417577dSAdrian Hunter 727b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 728a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 729a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 730a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 731a45c6cb8SMadhusudhan Chikkature 732a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 733a7e96879SVenkatraman S while ((reg != CC_EN) && time_before(jiffies, timeout)) 734a7e96879SVenkatraman S reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; 735a45c6cb8SMadhusudhan Chikkature 736a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 737a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 738c653a6d4SAdrian Hunter 739c653a6d4SAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 740c653a6d4SAdrian Hunter OMAP_HSMMC_READ(host->base, STAT); 741c653a6d4SAdrian Hunter 742a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 743a45c6cb8SMadhusudhan Chikkature } 744a45c6cb8SMadhusudhan Chikkature 745a45c6cb8SMadhusudhan Chikkature static ssize_t 74670a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 747a45c6cb8SMadhusudhan Chikkature char *buf) 748a45c6cb8SMadhusudhan Chikkature { 749a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 75070a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 751a45c6cb8SMadhusudhan Chikkature 752326119c9SAndreas Fenkart return sprintf(buf, "%s\n", mmc_pdata(host)->name); 753a45c6cb8SMadhusudhan Chikkature } 754a45c6cb8SMadhusudhan Chikkature 75570a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 756a45c6cb8SMadhusudhan Chikkature 757a45c6cb8SMadhusudhan Chikkature /* 758a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 759a45c6cb8SMadhusudhan Chikkature */ 760a45c6cb8SMadhusudhan Chikkature static void 76170a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 762a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 763a45c6cb8SMadhusudhan Chikkature { 764a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 765a45c6cb8SMadhusudhan Chikkature 7668986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 767a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 768a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 769a45c6cb8SMadhusudhan Chikkature 77093caf8e6SAdrian Hunter omap_hsmmc_enable_irq(host, cmd); 771a45c6cb8SMadhusudhan Chikkature 7724a694dc9SAdrian Hunter host->response_busy = 0; 773a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 774a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 775a45c6cb8SMadhusudhan Chikkature resptype = 1; 7764a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 7774a694dc9SAdrian Hunter resptype = 3; 7784a694dc9SAdrian Hunter host->response_busy = 1; 7794a694dc9SAdrian Hunter } else 780a45c6cb8SMadhusudhan Chikkature resptype = 2; 781a45c6cb8SMadhusudhan Chikkature } 782a45c6cb8SMadhusudhan Chikkature 783a45c6cb8SMadhusudhan Chikkature /* 784a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 785a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 786a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 787a45c6cb8SMadhusudhan Chikkature */ 788a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 789a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 790a45c6cb8SMadhusudhan Chikkature 791a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 792a45c6cb8SMadhusudhan Chikkature 793a2e77152SBalaji T K if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) && 794a2e77152SBalaji T K host->mrq->sbc) { 795a2e77152SBalaji T K cmdreg |= ACEN_ACMD23; 796a2e77152SBalaji T K OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg); 797a2e77152SBalaji T K } 798a45c6cb8SMadhusudhan Chikkature if (data) { 799a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 800a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 801a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 802a45c6cb8SMadhusudhan Chikkature else 803a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 804a45c6cb8SMadhusudhan Chikkature } 805a45c6cb8SMadhusudhan Chikkature 806a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 807a7e96879SVenkatraman S cmdreg |= DMAE; 808a45c6cb8SMadhusudhan Chikkature 809b417577dSAdrian Hunter host->req_in_progress = 1; 8104dffd7a2SAdrian Hunter 811a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 812a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 813a45c6cb8SMadhusudhan Chikkature } 814a45c6cb8SMadhusudhan Chikkature 815c5c98927SRussell King static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 816c5c98927SRussell King struct mmc_data *data) 817c5c98927SRussell King { 818c5c98927SRussell King return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 819c5c98927SRussell King } 820c5c98927SRussell King 821b417577dSAdrian Hunter static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 822b417577dSAdrian Hunter { 823b417577dSAdrian Hunter int dma_ch; 82431463b14SVenkatraman S unsigned long flags; 825b417577dSAdrian Hunter 82631463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 827b417577dSAdrian Hunter host->req_in_progress = 0; 828b417577dSAdrian Hunter dma_ch = host->dma_ch; 82931463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 830b417577dSAdrian Hunter 831b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 832b417577dSAdrian Hunter /* Do not complete the request if DMA is still in progress */ 833b417577dSAdrian Hunter if (mrq->data && host->use_dma && dma_ch != -1) 834b417577dSAdrian Hunter return; 835b417577dSAdrian Hunter host->mrq = NULL; 836b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 837b417577dSAdrian Hunter } 838b417577dSAdrian Hunter 839a45c6cb8SMadhusudhan Chikkature /* 840a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 841a45c6cb8SMadhusudhan Chikkature */ 842a45c6cb8SMadhusudhan Chikkature static void 84370a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 844a45c6cb8SMadhusudhan Chikkature { 8454a694dc9SAdrian Hunter if (!data) { 8464a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 8474a694dc9SAdrian Hunter 84823050103SAdrian Hunter /* TC before CC from CMD6 - don't know why, but it happens */ 84923050103SAdrian Hunter if (host->cmd && host->cmd->opcode == 6 && 85023050103SAdrian Hunter host->response_busy) { 85123050103SAdrian Hunter host->response_busy = 0; 85223050103SAdrian Hunter return; 85323050103SAdrian Hunter } 85423050103SAdrian Hunter 855b417577dSAdrian Hunter omap_hsmmc_request_done(host, mrq); 8564a694dc9SAdrian Hunter return; 8574a694dc9SAdrian Hunter } 8584a694dc9SAdrian Hunter 859a45c6cb8SMadhusudhan Chikkature host->data = NULL; 860a45c6cb8SMadhusudhan Chikkature 861a45c6cb8SMadhusudhan Chikkature if (!data->error) 862a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 863a45c6cb8SMadhusudhan Chikkature else 864a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 865a45c6cb8SMadhusudhan Chikkature 866bf129e1cSBalaji T K if (data->stop && (data->error || !host->mrq->sbc)) 867fe852273SMing Lei omap_hsmmc_start_command(host, data->stop, NULL); 868bf129e1cSBalaji T K else 869bf129e1cSBalaji T K omap_hsmmc_request_done(host, data->mrq); 870a45c6cb8SMadhusudhan Chikkature } 871a45c6cb8SMadhusudhan Chikkature 872a45c6cb8SMadhusudhan Chikkature /* 873a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 874a45c6cb8SMadhusudhan Chikkature */ 875a45c6cb8SMadhusudhan Chikkature static void 87670a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 877a45c6cb8SMadhusudhan Chikkature { 878bf129e1cSBalaji T K if (host->mrq->sbc && (host->cmd == host->mrq->sbc) && 879a2e77152SBalaji T K !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) { 8802177fa94SBalaji T K host->cmd = NULL; 881bf129e1cSBalaji T K omap_hsmmc_start_dma_transfer(host); 882bf129e1cSBalaji T K omap_hsmmc_start_command(host, host->mrq->cmd, 883bf129e1cSBalaji T K host->mrq->data); 884bf129e1cSBalaji T K return; 885bf129e1cSBalaji T K } 886bf129e1cSBalaji T K 8872177fa94SBalaji T K host->cmd = NULL; 8882177fa94SBalaji T K 889a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 890a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 891a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 892a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 893a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 894a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 895a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 896a45c6cb8SMadhusudhan Chikkature } else { 897a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 898a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 899a45c6cb8SMadhusudhan Chikkature } 900a45c6cb8SMadhusudhan Chikkature } 901b417577dSAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) 902d4b2c375SBalaji T K omap_hsmmc_request_done(host, host->mrq); 903a45c6cb8SMadhusudhan Chikkature } 904a45c6cb8SMadhusudhan Chikkature 905a45c6cb8SMadhusudhan Chikkature /* 906a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 907a45c6cb8SMadhusudhan Chikkature */ 90870a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 909a45c6cb8SMadhusudhan Chikkature { 910b417577dSAdrian Hunter int dma_ch; 91131463b14SVenkatraman S unsigned long flags; 912b417577dSAdrian Hunter 91382788ff5SJarkko Lavinen host->data->error = errno; 914a45c6cb8SMadhusudhan Chikkature 91531463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 916b417577dSAdrian Hunter dma_ch = host->dma_ch; 917b417577dSAdrian Hunter host->dma_ch = -1; 91831463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 919b417577dSAdrian Hunter 920b417577dSAdrian Hunter if (host->use_dma && dma_ch != -1) { 921c5c98927SRussell King struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 922c5c98927SRussell King 923c5c98927SRussell King dmaengine_terminate_all(chan); 924c5c98927SRussell King dma_unmap_sg(chan->device->dev, 925c5c98927SRussell King host->data->sg, host->data->sg_len, 926feeef096SHeiner Kallweit mmc_get_dma_dir(host->data)); 927c5c98927SRussell King 928053bf34fSPer Forlin host->data->host_cookie = 0; 929a45c6cb8SMadhusudhan Chikkature } 930a45c6cb8SMadhusudhan Chikkature host->data = NULL; 931a45c6cb8SMadhusudhan Chikkature } 932a45c6cb8SMadhusudhan Chikkature 933a45c6cb8SMadhusudhan Chikkature /* 934a45c6cb8SMadhusudhan Chikkature * Readable error output 935a45c6cb8SMadhusudhan Chikkature */ 936a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 937699b958bSAdrian Hunter static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 938a45c6cb8SMadhusudhan Chikkature { 939a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 94070a3341aSDenis Karpov static const char *omap_hsmmc_status_bits[] = { 941699b958bSAdrian Hunter "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 942699b958bSAdrian Hunter "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 943699b958bSAdrian Hunter "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 944699b958bSAdrian Hunter "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 945a45c6cb8SMadhusudhan Chikkature }; 946a45c6cb8SMadhusudhan Chikkature char res[256]; 947a45c6cb8SMadhusudhan Chikkature char *buf = res; 948a45c6cb8SMadhusudhan Chikkature int len, i; 949a45c6cb8SMadhusudhan Chikkature 950a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 951a45c6cb8SMadhusudhan Chikkature buf += len; 952a45c6cb8SMadhusudhan Chikkature 95370a3341aSDenis Karpov for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 954a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 95570a3341aSDenis Karpov len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 956a45c6cb8SMadhusudhan Chikkature buf += len; 957a45c6cb8SMadhusudhan Chikkature } 958a45c6cb8SMadhusudhan Chikkature 9598986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 960a45c6cb8SMadhusudhan Chikkature } 961699b958bSAdrian Hunter #else 962699b958bSAdrian Hunter static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 963699b958bSAdrian Hunter u32 status) 964699b958bSAdrian Hunter { 965699b958bSAdrian Hunter } 966a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 967a45c6cb8SMadhusudhan Chikkature 9683ebf74b1SJean Pihet /* 9693ebf74b1SJean Pihet * MMC controller internal state machines reset 9703ebf74b1SJean Pihet * 9713ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 9723ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 9733ebf74b1SJean Pihet * Can be called from interrupt context 9743ebf74b1SJean Pihet */ 97570a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 9763ebf74b1SJean Pihet unsigned long bit) 9773ebf74b1SJean Pihet { 9783ebf74b1SJean Pihet unsigned long i = 0; 9791e881786SJianpeng Ma unsigned long limit = MMC_TIMEOUT_US; 9803ebf74b1SJean Pihet 9813ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 9823ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 9833ebf74b1SJean Pihet 98407ad64b6SMadhusudhan Chikkature /* 98507ad64b6SMadhusudhan Chikkature * OMAP4 ES2 and greater has an updated reset logic. 98607ad64b6SMadhusudhan Chikkature * Monitor a 0->1 transition first 98707ad64b6SMadhusudhan Chikkature */ 988326119c9SAndreas Fenkart if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) { 989b432b4b3Skishore kadiyala while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 99007ad64b6SMadhusudhan Chikkature && (i++ < limit)) 9911e881786SJianpeng Ma udelay(1); 99207ad64b6SMadhusudhan Chikkature } 99307ad64b6SMadhusudhan Chikkature i = 0; 99407ad64b6SMadhusudhan Chikkature 9953ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 9963ebf74b1SJean Pihet (i++ < limit)) 9971e881786SJianpeng Ma udelay(1); 9983ebf74b1SJean Pihet 9993ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 10003ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 10013ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 10023ebf74b1SJean Pihet __func__); 10033ebf74b1SJean Pihet } 1004a45c6cb8SMadhusudhan Chikkature 100525e1897bSBalaji T K static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, 100625e1897bSBalaji T K int err, int end_cmd) 1007ae4bf788SVenkatraman S { 100825e1897bSBalaji T K if (end_cmd) { 100994d4f272SBalaji T K omap_hsmmc_reset_controller_fsm(host, SRC); 101025e1897bSBalaji T K if (host->cmd) 1011ae4bf788SVenkatraman S host->cmd->error = err; 101225e1897bSBalaji T K } 1013ae4bf788SVenkatraman S 1014ae4bf788SVenkatraman S if (host->data) { 1015ae4bf788SVenkatraman S omap_hsmmc_reset_controller_fsm(host, SRD); 1016ae4bf788SVenkatraman S omap_hsmmc_dma_cleanup(host, err); 1017dc7745bdSBalaji T K } else if (host->mrq && host->mrq->cmd) 1018dc7745bdSBalaji T K host->mrq->cmd->error = err; 1019ae4bf788SVenkatraman S } 1020ae4bf788SVenkatraman S 1021b417577dSAdrian Hunter static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1022a45c6cb8SMadhusudhan Chikkature { 1023a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 1024b417577dSAdrian Hunter int end_cmd = 0, end_trans = 0; 1025a2e77152SBalaji T K int error = 0; 1026a45c6cb8SMadhusudhan Chikkature 1027a45c6cb8SMadhusudhan Chikkature data = host->data; 10288986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1029a45c6cb8SMadhusudhan Chikkature 1030a7e96879SVenkatraman S if (status & ERR_EN) { 1031699b958bSAdrian Hunter omap_hsmmc_dbg_report_irq(host, status); 10324a694dc9SAdrian Hunter 103324380dd4SRavikumar Kattekola if (status & (CTO_EN | CCRC_EN | CEB_EN)) 1034a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1035408806f7SKishon Vijay Abraham I if (host->data || host->response_busy) { 1036408806f7SKishon Vijay Abraham I end_trans = !end_cmd; 1037408806f7SKishon Vijay Abraham I host->response_busy = 0; 1038408806f7SKishon Vijay Abraham I } 1039a7e96879SVenkatraman S if (status & (CTO_EN | DTO_EN)) 104025e1897bSBalaji T K hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); 10415027cd1eSVignesh R else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN | 10425027cd1eSVignesh R BADA_EN)) 104325e1897bSBalaji T K hsmmc_command_incomplete(host, -EILSEQ, end_cmd); 104425e1897bSBalaji T K 1045a2e77152SBalaji T K if (status & ACE_EN) { 1046a2e77152SBalaji T K u32 ac12; 1047a2e77152SBalaji T K ac12 = OMAP_HSMMC_READ(host->base, AC12); 1048a2e77152SBalaji T K if (!(ac12 & ACNE) && host->mrq->sbc) { 1049a2e77152SBalaji T K end_cmd = 1; 1050a2e77152SBalaji T K if (ac12 & ACTO) 1051a2e77152SBalaji T K error = -ETIMEDOUT; 1052a2e77152SBalaji T K else if (ac12 & (ACCE | ACEB | ACIE)) 1053a2e77152SBalaji T K error = -EILSEQ; 1054a2e77152SBalaji T K host->mrq->sbc->error = error; 1055a2e77152SBalaji T K hsmmc_command_incomplete(host, error, end_cmd); 1056a2e77152SBalaji T K } 1057a2e77152SBalaji T K dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12); 1058a2e77152SBalaji T K } 1059a45c6cb8SMadhusudhan Chikkature } 1060a45c6cb8SMadhusudhan Chikkature 10617472bab2SFrancesco Lavra OMAP_HSMMC_WRITE(host->base, STAT, status); 1062a7e96879SVenkatraman S if (end_cmd || ((status & CC_EN) && host->cmd)) 106370a3341aSDenis Karpov omap_hsmmc_cmd_done(host, host->cmd); 1064a7e96879SVenkatraman S if ((end_trans || (status & TC_EN)) && host->mrq) 106570a3341aSDenis Karpov omap_hsmmc_xfer_done(host, data); 1066b417577dSAdrian Hunter } 1067a45c6cb8SMadhusudhan Chikkature 1068b417577dSAdrian Hunter /* 1069b417577dSAdrian Hunter * MMC controller IRQ handler 1070b417577dSAdrian Hunter */ 1071b417577dSAdrian Hunter static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1072b417577dSAdrian Hunter { 1073b417577dSAdrian Hunter struct omap_hsmmc_host *host = dev_id; 1074b417577dSAdrian Hunter int status; 1075b417577dSAdrian Hunter 1076b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 10772cd3a2a5SAndreas Fenkart while (status & (INT_EN_MASK | CIRQ_EN)) { 10782cd3a2a5SAndreas Fenkart if (host->req_in_progress) 1079b417577dSAdrian Hunter omap_hsmmc_do_irq(host, status); 10801f6b9fa4SVenkatraman S 10812cd3a2a5SAndreas Fenkart if (status & CIRQ_EN) 10822cd3a2a5SAndreas Fenkart mmc_signal_sdio_irq(host->mmc); 10832cd3a2a5SAndreas Fenkart 1084b417577dSAdrian Hunter /* Flush posted write */ 1085b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 10861f6b9fa4SVenkatraman S } 10874dffd7a2SAdrian Hunter 1088a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1089a45c6cb8SMadhusudhan Chikkature } 1090a45c6cb8SMadhusudhan Chikkature 109170a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host) 1092e13bb300SAdrian Hunter { 1093e13bb300SAdrian Hunter unsigned long i; 1094e13bb300SAdrian Hunter 1095e13bb300SAdrian Hunter OMAP_HSMMC_WRITE(host->base, HCTL, 1096e13bb300SAdrian Hunter OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1097e13bb300SAdrian Hunter for (i = 0; i < loops_per_jiffy; i++) { 1098e13bb300SAdrian Hunter if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1099e13bb300SAdrian Hunter break; 1100e13bb300SAdrian Hunter cpu_relax(); 1101e13bb300SAdrian Hunter } 1102e13bb300SAdrian Hunter } 1103e13bb300SAdrian Hunter 1104a45c6cb8SMadhusudhan Chikkature /* 1105eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 1106eb250826SDavid Brownell * 1107eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1108eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1109eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 1110a45c6cb8SMadhusudhan Chikkature */ 111170a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1112a45c6cb8SMadhusudhan Chikkature { 1113a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 1114a45c6cb8SMadhusudhan Chikkature int ret; 1115a45c6cb8SMadhusudhan Chikkature 1116a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 111794c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 1118a45c6cb8SMadhusudhan Chikkature 1119a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 112066162becSKishon Vijay Abraham I ret = omap_hsmmc_set_power(host, 0); 1121a45c6cb8SMadhusudhan Chikkature 1122a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 11232bec0893SAdrian Hunter if (!ret) 112466162becSKishon Vijay Abraham I ret = omap_hsmmc_set_power(host, 1); 112594c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 11262bec0893SAdrian Hunter 1127a45c6cb8SMadhusudhan Chikkature if (ret != 0) 1128a45c6cb8SMadhusudhan Chikkature goto err; 1129a45c6cb8SMadhusudhan Chikkature 1130a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1131a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1132a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1133eb250826SDavid Brownell 1134a45c6cb8SMadhusudhan Chikkature /* 1135a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 1136a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 113770a3341aSDenis Karpov * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1138a45c6cb8SMadhusudhan Chikkature * 1139eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 1140eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1141eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 1142eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1143eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 1144eb250826SDavid Brownell * 1145eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 1146eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1147eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1148a45c6cb8SMadhusudhan Chikkature */ 1149eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 1150a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 1151eb250826SDavid Brownell else 1152eb250826SDavid Brownell reg_val |= SDVS30; 1153a45c6cb8SMadhusudhan Chikkature 1154a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1155e13bb300SAdrian Hunter set_sd_bus_power(host); 1156a45c6cb8SMadhusudhan Chikkature 1157a45c6cb8SMadhusudhan Chikkature return 0; 1158a45c6cb8SMadhusudhan Chikkature err: 1159b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1160a45c6cb8SMadhusudhan Chikkature return ret; 1161a45c6cb8SMadhusudhan Chikkature } 1162a45c6cb8SMadhusudhan Chikkature 1163c5c98927SRussell King static void omap_hsmmc_dma_callback(void *param) 11640ccd76d4SJuha Yrjola { 1165c5c98927SRussell King struct omap_hsmmc_host *host = param; 1166c5c98927SRussell King struct dma_chan *chan; 1167770d7432SAdrian Hunter struct mmc_data *data; 1168c5c98927SRussell King int req_in_progress; 1169a45c6cb8SMadhusudhan Chikkature 1170c5c98927SRussell King spin_lock_irq(&host->irq_lock); 1171b417577dSAdrian Hunter if (host->dma_ch < 0) { 1172c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1173a45c6cb8SMadhusudhan Chikkature return; 1174b417577dSAdrian Hunter } 1175a45c6cb8SMadhusudhan Chikkature 1176770d7432SAdrian Hunter data = host->mrq->data; 1177c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 11789782aff8SPer Forlin if (!data->host_cookie) 1179c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1180c5c98927SRussell King data->sg, data->sg_len, 1181feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 1182b417577dSAdrian Hunter 1183b417577dSAdrian Hunter req_in_progress = host->req_in_progress; 1184a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1185c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1186b417577dSAdrian Hunter 1187b417577dSAdrian Hunter /* If DMA has finished after TC, complete the request */ 1188b417577dSAdrian Hunter if (!req_in_progress) { 1189b417577dSAdrian Hunter struct mmc_request *mrq = host->mrq; 1190b417577dSAdrian Hunter 1191b417577dSAdrian Hunter host->mrq = NULL; 1192b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 1193b417577dSAdrian Hunter } 1194a45c6cb8SMadhusudhan Chikkature } 1195a45c6cb8SMadhusudhan Chikkature 11969782aff8SPer Forlin static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 11979782aff8SPer Forlin struct mmc_data *data, 1198c5c98927SRussell King struct omap_hsmmc_next *next, 119926b88520SRussell King struct dma_chan *chan) 12009782aff8SPer Forlin { 12019782aff8SPer Forlin int dma_len; 12029782aff8SPer Forlin 12039782aff8SPer Forlin if (!next && data->host_cookie && 12049782aff8SPer Forlin data->host_cookie != host->next_data.cookie) { 12052cecdf00SRajendra Nayak dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 12069782aff8SPer Forlin " host->next_data.cookie %d\n", 12079782aff8SPer Forlin __func__, data->host_cookie, host->next_data.cookie); 12089782aff8SPer Forlin data->host_cookie = 0; 12099782aff8SPer Forlin } 12109782aff8SPer Forlin 12119782aff8SPer Forlin /* Check if next job is already prepared */ 1212b38313d6SDan Carpenter if (next || data->host_cookie != host->next_data.cookie) { 121326b88520SRussell King dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 1214feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 12159782aff8SPer Forlin 12169782aff8SPer Forlin } else { 12179782aff8SPer Forlin dma_len = host->next_data.dma_len; 12189782aff8SPer Forlin host->next_data.dma_len = 0; 12199782aff8SPer Forlin } 12209782aff8SPer Forlin 12219782aff8SPer Forlin 12229782aff8SPer Forlin if (dma_len == 0) 12239782aff8SPer Forlin return -EINVAL; 12249782aff8SPer Forlin 12259782aff8SPer Forlin if (next) { 12269782aff8SPer Forlin next->dma_len = dma_len; 12279782aff8SPer Forlin data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 12289782aff8SPer Forlin } else 12299782aff8SPer Forlin host->dma_len = dma_len; 12309782aff8SPer Forlin 12319782aff8SPer Forlin return 0; 12329782aff8SPer Forlin } 12339782aff8SPer Forlin 1234a45c6cb8SMadhusudhan Chikkature /* 1235a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 1236a45c6cb8SMadhusudhan Chikkature */ 12379d025334SBalaji T K static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host, 123870a3341aSDenis Karpov struct mmc_request *req) 1239a45c6cb8SMadhusudhan Chikkature { 124026b88520SRussell King struct dma_async_tx_descriptor *tx; 124126b88520SRussell King int ret = 0, i; 1242a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 1243c5c98927SRussell King struct dma_chan *chan; 1244e5789608SPeter Ujfalusi struct dma_slave_config cfg = { 1245e5789608SPeter Ujfalusi .src_addr = host->mapbase + OMAP_HSMMC_DATA, 1246e5789608SPeter Ujfalusi .dst_addr = host->mapbase + OMAP_HSMMC_DATA, 1247e5789608SPeter Ujfalusi .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 1248e5789608SPeter Ujfalusi .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 1249e5789608SPeter Ujfalusi .src_maxburst = data->blksz / 4, 1250e5789608SPeter Ujfalusi .dst_maxburst = data->blksz / 4, 1251e5789608SPeter Ujfalusi }; 1252a45c6cb8SMadhusudhan Chikkature 12530ccd76d4SJuha Yrjola /* Sanity check: all the SG entries must be aligned by block size. */ 1254a3f406f8SJarkko Lavinen for (i = 0; i < data->sg_len; i++) { 12550ccd76d4SJuha Yrjola struct scatterlist *sgl; 12560ccd76d4SJuha Yrjola 12570ccd76d4SJuha Yrjola sgl = data->sg + i; 12580ccd76d4SJuha Yrjola if (sgl->length % data->blksz) 12590ccd76d4SJuha Yrjola return -EINVAL; 12600ccd76d4SJuha Yrjola } 12610ccd76d4SJuha Yrjola if ((data->blksz % 4) != 0) 12620ccd76d4SJuha Yrjola /* REVISIT: The MMC buffer increments only when MSB is written. 12630ccd76d4SJuha Yrjola * Return error for blksz which is non multiple of four. 12640ccd76d4SJuha Yrjola */ 12650ccd76d4SJuha Yrjola return -EINVAL; 12660ccd76d4SJuha Yrjola 1267b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1268a45c6cb8SMadhusudhan Chikkature 1269c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 1270c5c98927SRussell King 1271c5c98927SRussell King ret = dmaengine_slave_config(chan, &cfg); 12729782aff8SPer Forlin if (ret) 12739782aff8SPer Forlin return ret; 1274a45c6cb8SMadhusudhan Chikkature 127526b88520SRussell King ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1276c5c98927SRussell King if (ret) 1277c5c98927SRussell King return ret; 1278a45c6cb8SMadhusudhan Chikkature 1279c5c98927SRussell King tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1280c5c98927SRussell King data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1281c5c98927SRussell King DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1282c5c98927SRussell King if (!tx) { 1283c5c98927SRussell King dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1284c5c98927SRussell King /* FIXME: cleanup */ 1285c5c98927SRussell King return -1; 1286c5c98927SRussell King } 1287c5c98927SRussell King 1288c5c98927SRussell King tx->callback = omap_hsmmc_dma_callback; 1289c5c98927SRussell King tx->callback_param = host; 1290c5c98927SRussell King 1291c5c98927SRussell King /* Does not fail */ 1292c5c98927SRussell King dmaengine_submit(tx); 1293c5c98927SRussell King 129426b88520SRussell King host->dma_ch = 1; 1295c5c98927SRussell King 1296a45c6cb8SMadhusudhan Chikkature return 0; 1297a45c6cb8SMadhusudhan Chikkature } 1298a45c6cb8SMadhusudhan Chikkature 129970a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host, 1300a53210f5SRavikumar Kattekola unsigned long long timeout_ns, 1301e2bf08d6SAdrian Hunter unsigned int timeout_clks) 1302a45c6cb8SMadhusudhan Chikkature { 1303a53210f5SRavikumar Kattekola unsigned long long timeout = timeout_ns; 1304a53210f5SRavikumar Kattekola unsigned int cycle_ns; 1305a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 1306a45c6cb8SMadhusudhan Chikkature 1307a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1308a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1309a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 1310a45c6cb8SMadhusudhan Chikkature clkd = 1; 1311a45c6cb8SMadhusudhan Chikkature 13126e3076c2SBalaji T K cycle_ns = 1000000000 / (host->clk_rate / clkd); 1313a53210f5SRavikumar Kattekola do_div(timeout, cycle_ns); 1314e2bf08d6SAdrian Hunter timeout += timeout_clks; 1315a45c6cb8SMadhusudhan Chikkature if (timeout) { 1316a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 1317a45c6cb8SMadhusudhan Chikkature dto += 1; 1318a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1319a45c6cb8SMadhusudhan Chikkature } 1320a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 1321a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1322a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 1323a45c6cb8SMadhusudhan Chikkature dto += 1; 1324a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 1325a45c6cb8SMadhusudhan Chikkature dto -= 13; 1326a45c6cb8SMadhusudhan Chikkature else 1327a45c6cb8SMadhusudhan Chikkature dto = 0; 1328a45c6cb8SMadhusudhan Chikkature if (dto > 14) 1329a45c6cb8SMadhusudhan Chikkature dto = 14; 1330a45c6cb8SMadhusudhan Chikkature } 1331a45c6cb8SMadhusudhan Chikkature 1332a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 1333a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 1334a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1335a45c6cb8SMadhusudhan Chikkature } 1336a45c6cb8SMadhusudhan Chikkature 13379d025334SBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host) 13389d025334SBalaji T K { 13399d025334SBalaji T K struct mmc_request *req = host->mrq; 13409d025334SBalaji T K struct dma_chan *chan; 13419d025334SBalaji T K 13429d025334SBalaji T K if (!req->data) 13439d025334SBalaji T K return; 13449d025334SBalaji T K OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 13459d025334SBalaji T K | (req->data->blocks << 16)); 13469d025334SBalaji T K set_data_timeout(host, req->data->timeout_ns, 13479d025334SBalaji T K req->data->timeout_clks); 13489d025334SBalaji T K chan = omap_hsmmc_get_dma_chan(host, req->data); 13499d025334SBalaji T K dma_async_issue_pending(chan); 13509d025334SBalaji T K } 13519d025334SBalaji T K 1352a45c6cb8SMadhusudhan Chikkature /* 1353a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 1354a45c6cb8SMadhusudhan Chikkature */ 1355a45c6cb8SMadhusudhan Chikkature static int 135670a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1357a45c6cb8SMadhusudhan Chikkature { 1358a45c6cb8SMadhusudhan Chikkature int ret; 1359a53210f5SRavikumar Kattekola unsigned long long timeout; 13608cc9a3e7SKishon Vijay Abraham I 1361a45c6cb8SMadhusudhan Chikkature host->data = req->data; 1362a45c6cb8SMadhusudhan Chikkature 1363a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 1364a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 13658cc9a3e7SKishon Vijay Abraham I if (req->cmd->flags & MMC_RSP_BUSY) { 13668cc9a3e7SKishon Vijay Abraham I timeout = req->cmd->busy_timeout * NSEC_PER_MSEC; 13678cc9a3e7SKishon Vijay Abraham I 1368e2bf08d6SAdrian Hunter /* 1369e2bf08d6SAdrian Hunter * Set an arbitrary 100ms data timeout for commands with 13708cc9a3e7SKishon Vijay Abraham I * busy signal and no indication of busy_timeout. 1371e2bf08d6SAdrian Hunter */ 13728cc9a3e7SKishon Vijay Abraham I if (!timeout) 13738cc9a3e7SKishon Vijay Abraham I timeout = 100000000U; 13748cc9a3e7SKishon Vijay Abraham I 13758cc9a3e7SKishon Vijay Abraham I set_data_timeout(host, timeout, 0); 13768cc9a3e7SKishon Vijay Abraham I } 1377a45c6cb8SMadhusudhan Chikkature return 0; 1378a45c6cb8SMadhusudhan Chikkature } 1379a45c6cb8SMadhusudhan Chikkature 1380a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 13819d025334SBalaji T K ret = omap_hsmmc_setup_dma_transfer(host, req); 1382a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 1383b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); 1384a45c6cb8SMadhusudhan Chikkature return ret; 1385a45c6cb8SMadhusudhan Chikkature } 1386a45c6cb8SMadhusudhan Chikkature } 1387a45c6cb8SMadhusudhan Chikkature return 0; 1388a45c6cb8SMadhusudhan Chikkature } 1389a45c6cb8SMadhusudhan Chikkature 13909782aff8SPer Forlin static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 13919782aff8SPer Forlin int err) 13929782aff8SPer Forlin { 13939782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 13949782aff8SPer Forlin struct mmc_data *data = mrq->data; 13959782aff8SPer Forlin 139626b88520SRussell King if (host->use_dma && data->host_cookie) { 1397c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1398c5c98927SRussell King 139926b88520SRussell King dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 1400feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 14019782aff8SPer Forlin data->host_cookie = 0; 14029782aff8SPer Forlin } 14039782aff8SPer Forlin } 14049782aff8SPer Forlin 1405d3c6aac3SLinus Walleij static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 14069782aff8SPer Forlin { 14079782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 14089782aff8SPer Forlin 14099782aff8SPer Forlin if (mrq->data->host_cookie) { 14109782aff8SPer Forlin mrq->data->host_cookie = 0; 14119782aff8SPer Forlin return ; 14129782aff8SPer Forlin } 14139782aff8SPer Forlin 1414c5c98927SRussell King if (host->use_dma) { 1415c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1416c5c98927SRussell King 14179782aff8SPer Forlin if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 141826b88520SRussell King &host->next_data, c)) 14199782aff8SPer Forlin mrq->data->host_cookie = 0; 14209782aff8SPer Forlin } 1421c5c98927SRussell King } 14229782aff8SPer Forlin 1423a45c6cb8SMadhusudhan Chikkature /* 1424a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 1425a45c6cb8SMadhusudhan Chikkature */ 142670a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1427a45c6cb8SMadhusudhan Chikkature { 142870a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1429a3f406f8SJarkko Lavinen int err; 1430a45c6cb8SMadhusudhan Chikkature 1431b417577dSAdrian Hunter BUG_ON(host->req_in_progress); 1432b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 14337838a8ddSLinus Walleij if (host->reqs_blocked) 1434b62f6228SAdrian Hunter host->reqs_blocked = 0; 1435a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 1436a45c6cb8SMadhusudhan Chikkature host->mrq = req; 14376e3076c2SBalaji T K host->clk_rate = clk_get_rate(host->fclk); 143870a3341aSDenis Karpov err = omap_hsmmc_prepare_data(host, req); 1439a3f406f8SJarkko Lavinen if (err) { 1440a3f406f8SJarkko Lavinen req->cmd->error = err; 1441a3f406f8SJarkko Lavinen if (req->data) 1442a3f406f8SJarkko Lavinen req->data->error = err; 1443a3f406f8SJarkko Lavinen host->mrq = NULL; 1444a3f406f8SJarkko Lavinen mmc_request_done(mmc, req); 1445a3f406f8SJarkko Lavinen return; 1446a3f406f8SJarkko Lavinen } 1447a2e77152SBalaji T K if (req->sbc && !(host->flags & AUTO_CMD23)) { 1448bf129e1cSBalaji T K omap_hsmmc_start_command(host, req->sbc, NULL); 1449bf129e1cSBalaji T K return; 1450bf129e1cSBalaji T K } 1451a3f406f8SJarkko Lavinen 14529d025334SBalaji T K omap_hsmmc_start_dma_transfer(host); 145370a3341aSDenis Karpov omap_hsmmc_start_command(host, req->cmd, req->data); 1454a45c6cb8SMadhusudhan Chikkature } 1455a45c6cb8SMadhusudhan Chikkature 1456a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 145770a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1458a45c6cb8SMadhusudhan Chikkature { 145970a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1460a3621465SAdrian Hunter int do_send_init_stream = 0; 1461a45c6cb8SMadhusudhan Chikkature 1462a3621465SAdrian Hunter if (ios->power_mode != host->power_mode) { 1463a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 1464a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 146566162becSKishon Vijay Abraham I omap_hsmmc_set_power(host, 0); 1466a45c6cb8SMadhusudhan Chikkature break; 1467a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 146866162becSKishon Vijay Abraham I omap_hsmmc_set_power(host, 1); 1469a45c6cb8SMadhusudhan Chikkature break; 1470a3621465SAdrian Hunter case MMC_POWER_ON: 1471a3621465SAdrian Hunter do_send_init_stream = 1; 1472a3621465SAdrian Hunter break; 1473a3621465SAdrian Hunter } 1474a3621465SAdrian Hunter host->power_mode = ios->power_mode; 1475a45c6cb8SMadhusudhan Chikkature } 1476a45c6cb8SMadhusudhan Chikkature 1477dd498effSDenis Karpov /* FIXME: set registers based only on changes to ios */ 1478dd498effSDenis Karpov 14793796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 1480a45c6cb8SMadhusudhan Chikkature 14814621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1482eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 1483eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 1484eb250826SDavid Brownell */ 1485a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 14862cf171cbSBalaji T K (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1487a45c6cb8SMadhusudhan Chikkature /* 1488a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 1489a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 1490a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 1491a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 1492a45c6cb8SMadhusudhan Chikkature */ 149370a3341aSDenis Karpov if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1494a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1495a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 1496a45c6cb8SMadhusudhan Chikkature } 1497a45c6cb8SMadhusudhan Chikkature } 1498a45c6cb8SMadhusudhan Chikkature 14995934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 1500a45c6cb8SMadhusudhan Chikkature 1501a3621465SAdrian Hunter if (do_send_init_stream) 1502a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 1503a45c6cb8SMadhusudhan Chikkature 15043796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 1505a45c6cb8SMadhusudhan Chikkature } 1506a45c6cb8SMadhusudhan Chikkature 15074816858cSGrazvydas Ignotas static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 15084816858cSGrazvydas Ignotas { 15094816858cSGrazvydas Ignotas struct omap_hsmmc_host *host = mmc_priv(mmc); 15104816858cSGrazvydas Ignotas 15114d219f4cSH. Nikolaus Schaller if (card->type == MMC_TYPE_SDIO || card->type == MMC_TYPE_SD_COMBO) { 1512f6498b92SH. Nikolaus Schaller struct device_node *np = mmc_dev(mmc)->of_node; 1513f6498b92SH. Nikolaus Schaller 1514f6498b92SH. Nikolaus Schaller /* 1515f6498b92SH. Nikolaus Schaller * REVISIT: should be moved to sdio core and made more 1516f6498b92SH. Nikolaus Schaller * general e.g. by expanding the DT bindings of child nodes 1517f6498b92SH. Nikolaus Schaller * to provide a mechanism to provide this information: 1518f6498b92SH. Nikolaus Schaller * Documentation/devicetree/bindings/mmc/mmc-card.txt 1519f6498b92SH. Nikolaus Schaller */ 1520f6498b92SH. Nikolaus Schaller 1521f6498b92SH. Nikolaus Schaller np = of_get_compatible_child(np, "ti,wl1251"); 1522f6498b92SH. Nikolaus Schaller if (np) { 1523f6498b92SH. Nikolaus Schaller /* 1524f6498b92SH. Nikolaus Schaller * We have TI wl1251 attached to MMC3. Pass this 1525f6498b92SH. Nikolaus Schaller * information to the SDIO core because it can't be 1526f6498b92SH. Nikolaus Schaller * probed by normal methods. 1527f6498b92SH. Nikolaus Schaller */ 1528f6498b92SH. Nikolaus Schaller 1529f6498b92SH. Nikolaus Schaller dev_info(host->dev, "found wl1251\n"); 1530f6498b92SH. Nikolaus Schaller card->quirks |= MMC_QUIRK_NONSTD_SDIO; 1531f6498b92SH. Nikolaus Schaller card->cccr.wide_bus = 1; 1532f6498b92SH. Nikolaus Schaller card->cis.vendor = 0x104c; 1533f6498b92SH. Nikolaus Schaller card->cis.device = 0x9066; 1534f6498b92SH. Nikolaus Schaller card->cis.blksize = 512; 1535f6498b92SH. Nikolaus Schaller card->cis.max_dtr = 24000000; 1536f6498b92SH. Nikolaus Schaller card->ocr = 0x80; 1537f6498b92SH. Nikolaus Schaller of_node_put(np); 1538f6498b92SH. Nikolaus Schaller } 1539f6498b92SH. Nikolaus Schaller } 15404816858cSGrazvydas Ignotas } 15414816858cSGrazvydas Ignotas 15422cd3a2a5SAndreas Fenkart static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 15432cd3a2a5SAndreas Fenkart { 15442cd3a2a5SAndreas Fenkart struct omap_hsmmc_host *host = mmc_priv(mmc); 15455a52b08bSBalaji T K u32 irq_mask, con; 15462cd3a2a5SAndreas Fenkart unsigned long flags; 15472cd3a2a5SAndreas Fenkart 15482cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 15492cd3a2a5SAndreas Fenkart 15505a52b08bSBalaji T K con = OMAP_HSMMC_READ(host->base, CON); 15512cd3a2a5SAndreas Fenkart irq_mask = OMAP_HSMMC_READ(host->base, ISE); 15522cd3a2a5SAndreas Fenkart if (enable) { 15532cd3a2a5SAndreas Fenkart host->flags |= HSMMC_SDIO_IRQ_ENABLED; 15542cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 15555a52b08bSBalaji T K con |= CTPL | CLKEXTFREE; 15562cd3a2a5SAndreas Fenkart } else { 15572cd3a2a5SAndreas Fenkart host->flags &= ~HSMMC_SDIO_IRQ_ENABLED; 15582cd3a2a5SAndreas Fenkart irq_mask &= ~CIRQ_EN; 15595a52b08bSBalaji T K con &= ~(CTPL | CLKEXTFREE); 15602cd3a2a5SAndreas Fenkart } 15615a52b08bSBalaji T K OMAP_HSMMC_WRITE(host->base, CON, con); 15622cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 15632cd3a2a5SAndreas Fenkart 15642cd3a2a5SAndreas Fenkart /* 15652cd3a2a5SAndreas Fenkart * if enable, piggy back detection on current request 15662cd3a2a5SAndreas Fenkart * but always disable immediately 15672cd3a2a5SAndreas Fenkart */ 15682cd3a2a5SAndreas Fenkart if (!host->req_in_progress || !enable) 15692cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 15702cd3a2a5SAndreas Fenkart 15712cd3a2a5SAndreas Fenkart /* flush posted write */ 15722cd3a2a5SAndreas Fenkart OMAP_HSMMC_READ(host->base, IE); 15732cd3a2a5SAndreas Fenkart 15742cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 15752cd3a2a5SAndreas Fenkart } 15762cd3a2a5SAndreas Fenkart 15772cd3a2a5SAndreas Fenkart static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host) 15782cd3a2a5SAndreas Fenkart { 15792cd3a2a5SAndreas Fenkart int ret; 15802cd3a2a5SAndreas Fenkart 15812cd3a2a5SAndreas Fenkart /* 15822cd3a2a5SAndreas Fenkart * For omaps with wake-up path, wakeirq will be irq from pinctrl and 15832cd3a2a5SAndreas Fenkart * for other omaps, wakeirq will be from GPIO (dat line remuxed to 15842cd3a2a5SAndreas Fenkart * gpio). wakeirq is needed to detect sdio irq in runtime suspend state 15852cd3a2a5SAndreas Fenkart * with functional clock disabled. 15862cd3a2a5SAndreas Fenkart */ 15872cd3a2a5SAndreas Fenkart if (!host->dev->of_node || !host->wake_irq) 15882cd3a2a5SAndreas Fenkart return -ENODEV; 15892cd3a2a5SAndreas Fenkart 15905b83b223STony Lindgren ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq); 15912cd3a2a5SAndreas Fenkart if (ret) { 15922cd3a2a5SAndreas Fenkart dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n"); 15932cd3a2a5SAndreas Fenkart goto err; 15942cd3a2a5SAndreas Fenkart } 15952cd3a2a5SAndreas Fenkart 15962cd3a2a5SAndreas Fenkart /* 15972cd3a2a5SAndreas Fenkart * Some omaps don't have wake-up path from deeper idle states 15982cd3a2a5SAndreas Fenkart * and need to remux SDIO DAT1 to GPIO for wake-up from idle. 15992cd3a2a5SAndreas Fenkart */ 16002cd3a2a5SAndreas Fenkart if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) { 1601455e5cd6SAndreas Fenkart struct pinctrl *p = devm_pinctrl_get(host->dev); 1602ec5ab893SDan Carpenter if (IS_ERR(p)) { 1603ec5ab893SDan Carpenter ret = PTR_ERR(p); 1604455e5cd6SAndreas Fenkart goto err_free_irq; 1605455e5cd6SAndreas Fenkart } 1606455e5cd6SAndreas Fenkart 1607455e5cd6SAndreas Fenkart if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) { 1608455e5cd6SAndreas Fenkart dev_info(host->dev, "missing idle pinctrl state\n"); 1609455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 1610455e5cd6SAndreas Fenkart ret = -EINVAL; 1611455e5cd6SAndreas Fenkart goto err_free_irq; 1612455e5cd6SAndreas Fenkart } 1613455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 16142cd3a2a5SAndreas Fenkart } 16152cd3a2a5SAndreas Fenkart 16165a52b08bSBalaji T K OMAP_HSMMC_WRITE(host->base, HCTL, 16175a52b08bSBalaji T K OMAP_HSMMC_READ(host->base, HCTL) | IWE); 16182cd3a2a5SAndreas Fenkart return 0; 16192cd3a2a5SAndreas Fenkart 1620455e5cd6SAndreas Fenkart err_free_irq: 16215b83b223STony Lindgren dev_pm_clear_wake_irq(host->dev); 16222cd3a2a5SAndreas Fenkart err: 16232cd3a2a5SAndreas Fenkart dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n"); 16242cd3a2a5SAndreas Fenkart host->wake_irq = 0; 16252cd3a2a5SAndreas Fenkart return ret; 16262cd3a2a5SAndreas Fenkart } 16272cd3a2a5SAndreas Fenkart 162870a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 16291b331e69SKim Kyuwon { 16301b331e69SKim Kyuwon u32 hctl, capa, value; 16311b331e69SKim Kyuwon 16321b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 16334621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 16341b331e69SKim Kyuwon hctl = SDVS30; 16351b331e69SKim Kyuwon capa = VS30 | VS18; 16361b331e69SKim Kyuwon } else { 16371b331e69SKim Kyuwon hctl = SDVS18; 16381b331e69SKim Kyuwon capa = VS18; 16391b331e69SKim Kyuwon } 16401b331e69SKim Kyuwon 16411b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 16421b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 16431b331e69SKim Kyuwon 16441b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 16451b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 16461b331e69SKim Kyuwon 16471b331e69SKim Kyuwon /* Set SD bus power bit */ 1648e13bb300SAdrian Hunter set_sd_bus_power(host); 16491b331e69SKim Kyuwon } 16501b331e69SKim Kyuwon 1651afd8c29dSKuninori Morimoto static int omap_hsmmc_multi_io_quirk(struct mmc_card *card, 1652afd8c29dSKuninori Morimoto unsigned int direction, int blk_size) 1653afd8c29dSKuninori Morimoto { 1654afd8c29dSKuninori Morimoto /* This controller can't do multiblock reads due to hw bugs */ 1655afd8c29dSKuninori Morimoto if (direction == MMC_DATA_READ) 1656afd8c29dSKuninori Morimoto return 1; 1657afd8c29dSKuninori Morimoto 1658afd8c29dSKuninori Morimoto return blk_size; 1659afd8c29dSKuninori Morimoto } 1660afd8c29dSKuninori Morimoto 1661afd8c29dSKuninori Morimoto static struct mmc_host_ops omap_hsmmc_ops = { 16629782aff8SPer Forlin .post_req = omap_hsmmc_post_req, 16639782aff8SPer Forlin .pre_req = omap_hsmmc_pre_req, 166470a3341aSDenis Karpov .request = omap_hsmmc_request, 166570a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1666e63201f1SLinus Walleij .get_cd = mmc_gpio_get_cd, 1667a49d8353SAndreas Fenkart .get_ro = mmc_gpio_get_ro, 16684816858cSGrazvydas Ignotas .init_card = omap_hsmmc_init_card, 16692cd3a2a5SAndreas Fenkart .enable_sdio_irq = omap_hsmmc_enable_sdio_irq, 1670dd498effSDenis Karpov }; 1671dd498effSDenis Karpov 1672d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS 1673d900f712SDenis Karpov 16748ceb2943SYangtao Li static int mmc_regs_show(struct seq_file *s, void *data) 1675d900f712SDenis Karpov { 1676d900f712SDenis Karpov struct mmc_host *mmc = s->private; 167770a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 167811dd62a7SDenis Karpov 1679bb0635f0SAndreas Fenkart seq_printf(s, "mmc%d:\n", mmc->index); 1680bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq mode\t%s\n", 1681bb0635f0SAndreas Fenkart (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling"); 1682bb0635f0SAndreas Fenkart 1683bb0635f0SAndreas Fenkart if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1684bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq \t%s\n", 1685bb0635f0SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled" 1686bb0635f0SAndreas Fenkart : "disabled"); 1687bb0635f0SAndreas Fenkart } 1688bb0635f0SAndreas Fenkart seq_printf(s, "ctx_loss:\t%d\n", host->context_loss); 16895e2ea617SAdrian Hunter 1690fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1691bb0635f0SAndreas Fenkart seq_puts(s, "\nregs:\n"); 1692d900f712SDenis Karpov seq_printf(s, "CON:\t\t0x%08x\n", 1693d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CON)); 1694bb0635f0SAndreas Fenkart seq_printf(s, "PSTATE:\t\t0x%08x\n", 1695bb0635f0SAndreas Fenkart OMAP_HSMMC_READ(host->base, PSTATE)); 1696d900f712SDenis Karpov seq_printf(s, "HCTL:\t\t0x%08x\n", 1697d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL)); 1698d900f712SDenis Karpov seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1699d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL)); 1700d900f712SDenis Karpov seq_printf(s, "IE:\t\t0x%08x\n", 1701d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, IE)); 1702d900f712SDenis Karpov seq_printf(s, "ISE:\t\t0x%08x\n", 1703d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, ISE)); 1704d900f712SDenis Karpov seq_printf(s, "CAPA:\t\t0x%08x\n", 1705d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA)); 17065e2ea617SAdrian Hunter 1707fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1708fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1709dd498effSDenis Karpov 1710d900f712SDenis Karpov return 0; 1711d900f712SDenis Karpov } 1712d900f712SDenis Karpov 17138ceb2943SYangtao Li DEFINE_SHOW_ATTRIBUTE(mmc_regs); 1714d900f712SDenis Karpov 171570a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1716d900f712SDenis Karpov { 1717d900f712SDenis Karpov if (mmc->debugfs_root) 1718d900f712SDenis Karpov debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1719d900f712SDenis Karpov mmc, &mmc_regs_fops); 1720d900f712SDenis Karpov } 1721d900f712SDenis Karpov 1722d900f712SDenis Karpov #else 1723d900f712SDenis Karpov 172470a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1725d900f712SDenis Karpov { 1726d900f712SDenis Karpov } 1727d900f712SDenis Karpov 1728d900f712SDenis Karpov #endif 1729d900f712SDenis Karpov 173046856a68SRajendra Nayak #ifdef CONFIG_OF 173159445b10SNishanth Menon static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = { 173259445b10SNishanth Menon /* See 35xx errata 2.1.1.128 in SPRZ278F */ 173359445b10SNishanth Menon .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 173459445b10SNishanth Menon }; 173559445b10SNishanth Menon 173659445b10SNishanth Menon static const struct omap_mmc_of_data omap4_mmc_of_data = { 173759445b10SNishanth Menon .reg_offset = 0x100, 173859445b10SNishanth Menon }; 17392cd3a2a5SAndreas Fenkart static const struct omap_mmc_of_data am33xx_mmc_of_data = { 17402cd3a2a5SAndreas Fenkart .reg_offset = 0x100, 17412cd3a2a5SAndreas Fenkart .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING, 17422cd3a2a5SAndreas Fenkart }; 174346856a68SRajendra Nayak 174446856a68SRajendra Nayak static const struct of_device_id omap_mmc_of_match[] = { 174546856a68SRajendra Nayak { 174646856a68SRajendra Nayak .compatible = "ti,omap2-hsmmc", 174746856a68SRajendra Nayak }, 174846856a68SRajendra Nayak { 174959445b10SNishanth Menon .compatible = "ti,omap3-pre-es3-hsmmc", 175059445b10SNishanth Menon .data = &omap3_pre_es3_mmc_of_data, 175159445b10SNishanth Menon }, 175259445b10SNishanth Menon { 175346856a68SRajendra Nayak .compatible = "ti,omap3-hsmmc", 175446856a68SRajendra Nayak }, 175546856a68SRajendra Nayak { 175646856a68SRajendra Nayak .compatible = "ti,omap4-hsmmc", 175759445b10SNishanth Menon .data = &omap4_mmc_of_data, 175846856a68SRajendra Nayak }, 17592cd3a2a5SAndreas Fenkart { 17602cd3a2a5SAndreas Fenkart .compatible = "ti,am33xx-hsmmc", 17612cd3a2a5SAndreas Fenkart .data = &am33xx_mmc_of_data, 17622cd3a2a5SAndreas Fenkart }, 176346856a68SRajendra Nayak {}, 1764b6d085f6SChris Ball }; 176546856a68SRajendra Nayak MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 176646856a68SRajendra Nayak 176755143438SAndreas Fenkart static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 176846856a68SRajendra Nayak { 1769db863d89STony Lindgren struct omap_hsmmc_platform_data *pdata, *legacy; 177046856a68SRajendra Nayak struct device_node *np = dev->of_node; 177146856a68SRajendra Nayak 177246856a68SRajendra Nayak pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 177346856a68SRajendra Nayak if (!pdata) 177419df45bcSBalaji T K return ERR_PTR(-ENOMEM); /* out of memory */ 177546856a68SRajendra Nayak 1776db863d89STony Lindgren legacy = dev_get_platdata(dev); 1777db863d89STony Lindgren if (legacy && legacy->name) 1778db863d89STony Lindgren pdata->name = legacy->name; 1779db863d89STony Lindgren 178046856a68SRajendra Nayak if (of_find_property(np, "ti,dual-volt", NULL)) 178146856a68SRajendra Nayak pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 178246856a68SRajendra Nayak 178346856a68SRajendra Nayak if (of_find_property(np, "ti,non-removable", NULL)) { 1784326119c9SAndreas Fenkart pdata->nonremovable = true; 1785326119c9SAndreas Fenkart pdata->no_regulator_off_init = true; 178646856a68SRajendra Nayak } 178746856a68SRajendra Nayak 178846856a68SRajendra Nayak if (of_find_property(np, "ti,needs-special-reset", NULL)) 1789326119c9SAndreas Fenkart pdata->features |= HSMMC_HAS_UPDATED_RESET; 179046856a68SRajendra Nayak 1791cd587096SHebbar, Gururaja if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) 1792326119c9SAndreas Fenkart pdata->features |= HSMMC_HAS_HSPE_SUPPORT; 1793cd587096SHebbar, Gururaja 179446856a68SRajendra Nayak return pdata; 179546856a68SRajendra Nayak } 179646856a68SRajendra Nayak #else 179755143438SAndreas Fenkart static inline struct omap_hsmmc_platform_data 179846856a68SRajendra Nayak *of_get_hsmmc_pdata(struct device *dev) 179946856a68SRajendra Nayak { 180019df45bcSBalaji T K return ERR_PTR(-EINVAL); 180146856a68SRajendra Nayak } 180246856a68SRajendra Nayak #endif 180346856a68SRajendra Nayak 1804c3be1efdSBill Pemberton static int omap_hsmmc_probe(struct platform_device *pdev) 1805a45c6cb8SMadhusudhan Chikkature { 180655143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data; 1807a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 180870a3341aSDenis Karpov struct omap_hsmmc_host *host = NULL; 1809a45c6cb8SMadhusudhan Chikkature struct resource *res; 1810db0fefc5SAdrian Hunter int ret, irq; 181146856a68SRajendra Nayak const struct of_device_id *match; 181259445b10SNishanth Menon const struct omap_mmc_of_data *data; 181377fae219SBalaji T K void __iomem *base; 181446856a68SRajendra Nayak 181546856a68SRajendra Nayak match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 181646856a68SRajendra Nayak if (match) { 181746856a68SRajendra Nayak pdata = of_get_hsmmc_pdata(&pdev->dev); 1818dc642c28SJan Luebbe 1819dc642c28SJan Luebbe if (IS_ERR(pdata)) 1820dc642c28SJan Luebbe return PTR_ERR(pdata); 1821dc642c28SJan Luebbe 182246856a68SRajendra Nayak if (match->data) { 182359445b10SNishanth Menon data = match->data; 182459445b10SNishanth Menon pdata->reg_offset = data->reg_offset; 182559445b10SNishanth Menon pdata->controller_flags |= data->controller_flags; 182646856a68SRajendra Nayak } 182746856a68SRajendra Nayak } 1828a45c6cb8SMadhusudhan Chikkature 1829a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 1830a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 1831a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1832a45c6cb8SMadhusudhan Chikkature } 1833a45c6cb8SMadhusudhan Chikkature 1834a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1835a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 1836a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 1837a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1838a45c6cb8SMadhusudhan Chikkature 183977fae219SBalaji T K base = devm_ioremap_resource(&pdev->dev, res); 184077fae219SBalaji T K if (IS_ERR(base)) 184177fae219SBalaji T K return PTR_ERR(base); 1842a45c6cb8SMadhusudhan Chikkature 184370a3341aSDenis Karpov mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 1844a45c6cb8SMadhusudhan Chikkature if (!mmc) { 1845a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 18461e363e3bSAndreas Fenkart goto err; 1847a45c6cb8SMadhusudhan Chikkature } 1848a45c6cb8SMadhusudhan Chikkature 1849fdb9de12SNeilBrown ret = mmc_of_parse(mmc); 1850fdb9de12SNeilBrown if (ret) 1851fdb9de12SNeilBrown goto err1; 1852fdb9de12SNeilBrown 1853a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 1854a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 1855a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 1856a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 1857a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 1858a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1859a45c6cb8SMadhusudhan Chikkature host->irq = irq; 1860fc307df8SBalaji T K host->mapbase = res->start + pdata->reg_offset; 186177fae219SBalaji T K host->base = base + pdata->reg_offset; 18626da20c89SAdrian Hunter host->power_mode = MMC_POWER_OFF; 18639782aff8SPer Forlin host->next_data.cookie = 1; 1864bb2726b5STony Lindgren host->pbias_enabled = 0; 18653f77f702SKishon Vijay Abraham I host->vqmmc_enabled = 0; 1866a45c6cb8SMadhusudhan Chikkature 1867a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 1868a45c6cb8SMadhusudhan Chikkature 18692cd3a2a5SAndreas Fenkart if (pdev->dev.of_node) 18702cd3a2a5SAndreas Fenkart host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1); 18712cd3a2a5SAndreas Fenkart 187270a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ops; 1873dd498effSDenis Karpov 18746b206efeSAndy Shevchenko mmc->f_min = OMAP_MMC_MIN_CLOCK; 1875d418ed87SDaniel Mack 1876d418ed87SDaniel Mack if (pdata->max_freq > 0) 1877d418ed87SDaniel Mack mmc->f_max = pdata->max_freq; 1878fdb9de12SNeilBrown else if (mmc->f_max == 0) 18796b206efeSAndy Shevchenko mmc->f_max = OMAP_MMC_MAX_CLOCK; 1880a45c6cb8SMadhusudhan Chikkature 18814dffd7a2SAdrian Hunter spin_lock_init(&host->irq_lock); 1882a45c6cb8SMadhusudhan Chikkature 18839618195eSBalaji T K host->fclk = devm_clk_get(&pdev->dev, "fck"); 1884a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 1885a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 1886a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 1887a45c6cb8SMadhusudhan Chikkature goto err1; 1888a45c6cb8SMadhusudhan Chikkature } 1889a45c6cb8SMadhusudhan Chikkature 18909b68256cSPaul Walmsley if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 18919b68256cSPaul Walmsley dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 1892afd8c29dSKuninori Morimoto omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk; 18939b68256cSPaul Walmsley } 1894dd498effSDenis Karpov 18955b83b223STony Lindgren device_init_wakeup(&pdev->dev, true); 1896fa4aa2d4SBalaji T K pm_runtime_enable(host->dev); 1897fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1898fa4aa2d4SBalaji T K pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 1899fa4aa2d4SBalaji T K pm_runtime_use_autosuspend(host->dev); 1900a45c6cb8SMadhusudhan Chikkature 190192a3aebfSBalaji T K omap_hsmmc_context_save(host); 190292a3aebfSBalaji T K 19039618195eSBalaji T K host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck"); 1904a45c6cb8SMadhusudhan Chikkature /* 1905a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 1906a45c6cb8SMadhusudhan Chikkature */ 1907cd03d9a8SRajendra Nayak if (IS_ERR(host->dbclk)) { 1908cd03d9a8SRajendra Nayak host->dbclk = NULL; 190994c18149SRajendra Nayak } else if (clk_prepare_enable(host->dbclk) != 0) { 1910cd03d9a8SRajendra Nayak dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 1911cd03d9a8SRajendra Nayak host->dbclk = NULL; 19122bec0893SAdrian Hunter } 1913a45c6cb8SMadhusudhan Chikkature 191494424004SWill Newton /* Set this to a value that allows allocating an entire descriptor 191594424004SWill Newton * list within a page (zero order allocation). */ 191694424004SWill Newton mmc->max_segs = 64; 19170ccd76d4SJuha Yrjola 1918a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 1919a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 1920a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1921a45c6cb8SMadhusudhan Chikkature 192213189e78SJarkko Lavinen mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 19231be64c79SUlf Hansson MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_CMD23; 1924a45c6cb8SMadhusudhan Chikkature 1925326119c9SAndreas Fenkart mmc->caps |= mmc_pdata(host)->caps; 19263a63833eSSukumar Ghorai if (mmc->caps & MMC_CAP_8_BIT_DATA) 1927a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 1928a45c6cb8SMadhusudhan Chikkature 1929326119c9SAndreas Fenkart if (mmc_pdata(host)->nonremovable) 193023d99bb9SAdrian Hunter mmc->caps |= MMC_CAP_NONREMOVABLE; 193123d99bb9SAdrian Hunter 1932fdb9de12SNeilBrown mmc->pm_caps |= mmc_pdata(host)->pm_caps; 19336fdc75deSEliad Peller 193470a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 1935a45c6cb8SMadhusudhan Chikkature 193681eef6caSPeter Ujfalusi host->rx_chan = dma_request_chan(&pdev->dev, "rx"); 193781eef6caSPeter Ujfalusi if (IS_ERR(host->rx_chan)) { 193881eef6caSPeter Ujfalusi dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n"); 193981eef6caSPeter Ujfalusi ret = PTR_ERR(host->rx_chan); 194026b88520SRussell King goto err_irq; 1941c5c98927SRussell King } 194226b88520SRussell King 194381eef6caSPeter Ujfalusi host->tx_chan = dma_request_chan(&pdev->dev, "tx"); 194481eef6caSPeter Ujfalusi if (IS_ERR(host->tx_chan)) { 194581eef6caSPeter Ujfalusi dev_err(mmc_dev(host->mmc), "TX DMA channel request failed\n"); 194681eef6caSPeter Ujfalusi ret = PTR_ERR(host->tx_chan); 194726b88520SRussell King goto err_irq; 1948c5c98927SRussell King } 1949a45c6cb8SMadhusudhan Chikkature 19500b479790SRussell King /* 19510b479790SRussell King * Limit the maximum segment size to the lower of the request size 19520b479790SRussell King * and the DMA engine device segment size limits. In reality, with 19530b479790SRussell King * 32-bit transfers, the DMA engine can do longer segments than this 19540b479790SRussell King * but there is no way to represent that in the DMA model - if we 19550b479790SRussell King * increase this figure here, we get warnings from the DMA API debug. 19560b479790SRussell King */ 19570b479790SRussell King mmc->max_seg_size = min3(mmc->max_req_size, 19580b479790SRussell King dma_get_max_seg_size(host->rx_chan->device->dev), 19590b479790SRussell King dma_get_max_seg_size(host->tx_chan->device->dev)); 19600b479790SRussell King 1961a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 1962e1538ed7SBalaji T K ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0, 1963a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 1964a45c6cb8SMadhusudhan Chikkature if (ret) { 1965b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 1966a45c6cb8SMadhusudhan Chikkature goto err_irq; 1967a45c6cb8SMadhusudhan Chikkature } 1968a45c6cb8SMadhusudhan Chikkature 1969db0fefc5SAdrian Hunter ret = omap_hsmmc_reg_get(host); 1970db0fefc5SAdrian Hunter if (ret) 1971bb09d151SAndreas Fenkart goto err_irq; 1972db0fefc5SAdrian Hunter 197313ab2a66SKishon Vijay Abraham I if (!mmc->ocr_avail) 1974326119c9SAndreas Fenkart mmc->ocr_avail = mmc_pdata(host)->ocr_mask; 1975a45c6cb8SMadhusudhan Chikkature 1976b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 1977a45c6cb8SMadhusudhan Chikkature 19782cd3a2a5SAndreas Fenkart /* 19792cd3a2a5SAndreas Fenkart * For now, only support SDIO interrupt if we have a separate 19802cd3a2a5SAndreas Fenkart * wake-up interrupt configured from device tree. This is because 19812cd3a2a5SAndreas Fenkart * the wake-up interrupt is needed for idle state and some 19822cd3a2a5SAndreas Fenkart * platforms need special quirks. And we don't want to add new 19832cd3a2a5SAndreas Fenkart * legacy mux platform init code callbacks any longer as we 19842cd3a2a5SAndreas Fenkart * are moving to DT based booting anyways. 19852cd3a2a5SAndreas Fenkart */ 19862cd3a2a5SAndreas Fenkart ret = omap_hsmmc_configure_wake_irq(host); 19872cd3a2a5SAndreas Fenkart if (!ret) 19882cd3a2a5SAndreas Fenkart mmc->caps |= MMC_CAP_SDIO_IRQ; 19892cd3a2a5SAndreas Fenkart 1990a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 1991a45c6cb8SMadhusudhan Chikkature 1992326119c9SAndreas Fenkart if (mmc_pdata(host)->name != NULL) { 1993a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 1994a45c6cb8SMadhusudhan Chikkature if (ret < 0) 1995a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 1996a45c6cb8SMadhusudhan Chikkature } 1997a45c6cb8SMadhusudhan Chikkature 199870a3341aSDenis Karpov omap_hsmmc_debugfs(mmc); 1999fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2000fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2001d900f712SDenis Karpov 2002a45c6cb8SMadhusudhan Chikkature return 0; 2003a45c6cb8SMadhusudhan Chikkature 2004a45c6cb8SMadhusudhan Chikkature err_slot_name: 2005a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 2006a45c6cb8SMadhusudhan Chikkature err_irq: 20075b83b223STony Lindgren device_init_wakeup(&pdev->dev, false); 200881eef6caSPeter Ujfalusi if (!IS_ERR_OR_NULL(host->tx_chan)) 2009c5c98927SRussell King dma_release_channel(host->tx_chan); 201081eef6caSPeter Ujfalusi if (!IS_ERR_OR_NULL(host->rx_chan)) 2011c5c98927SRussell King dma_release_channel(host->rx_chan); 2012814a3c0cSTony Lindgren pm_runtime_dont_use_autosuspend(host->dev); 2013d59d77edSBalaji T K pm_runtime_put_sync(host->dev); 201437f6190dSTony Lindgren pm_runtime_disable(host->dev); 201594c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2016a45c6cb8SMadhusudhan Chikkature err1: 2017a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 2018db0fefc5SAdrian Hunter err: 2019a45c6cb8SMadhusudhan Chikkature return ret; 2020a45c6cb8SMadhusudhan Chikkature } 2021a45c6cb8SMadhusudhan Chikkature 20226e0ee714SBill Pemberton static int omap_hsmmc_remove(struct platform_device *pdev) 2023a45c6cb8SMadhusudhan Chikkature { 202470a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2025a45c6cb8SMadhusudhan Chikkature 2026fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2027a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 2028a45c6cb8SMadhusudhan Chikkature 2029c5c98927SRussell King dma_release_channel(host->tx_chan); 2030c5c98927SRussell King dma_release_channel(host->rx_chan); 2031c5c98927SRussell King 20323c398f3cSAndreas Kemnade dev_pm_clear_wake_irq(host->dev); 2033814a3c0cSTony Lindgren pm_runtime_dont_use_autosuspend(host->dev); 2034fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2035fa4aa2d4SBalaji T K pm_runtime_disable(host->dev); 20365b83b223STony Lindgren device_init_wakeup(&pdev->dev, false); 203794c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2038a45c6cb8SMadhusudhan Chikkature 20399d1f0286SBalaji T K mmc_free_host(host->mmc); 2040a45c6cb8SMadhusudhan Chikkature 2041a45c6cb8SMadhusudhan Chikkature return 0; 2042a45c6cb8SMadhusudhan Chikkature } 2043a45c6cb8SMadhusudhan Chikkature 20443d3bbfbdSRuss Dill #ifdef CONFIG_PM_SLEEP 2045a791daa1SKevin Hilman static int omap_hsmmc_suspend(struct device *dev) 2046a45c6cb8SMadhusudhan Chikkature { 2047927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2048927ce944SFelipe Balbi 2049927ce944SFelipe Balbi if (!host) 2050927ce944SFelipe Balbi return 0; 2051a45c6cb8SMadhusudhan Chikkature 2052fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 205331f9d463SEliad Peller 205431f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 20552cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 20562cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 20572cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 205831f9d463SEliad Peller OMAP_HSMMC_WRITE(host->base, HCTL, 205931f9d463SEliad Peller OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 206031f9d463SEliad Peller } 2061927ce944SFelipe Balbi 206294c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 20633932afd5SUlf Hansson 2064fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 20653932afd5SUlf Hansson return 0; 2066a45c6cb8SMadhusudhan Chikkature } 2067a45c6cb8SMadhusudhan Chikkature 2068a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 2069a791daa1SKevin Hilman static int omap_hsmmc_resume(struct device *dev) 2070a45c6cb8SMadhusudhan Chikkature { 2071927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2072927ce944SFelipe Balbi 2073927ce944SFelipe Balbi if (!host) 2074927ce944SFelipe Balbi return 0; 2075a45c6cb8SMadhusudhan Chikkature 2076fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 207711dd62a7SDenis Karpov 207894c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 20792bec0893SAdrian Hunter 208031f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 208170a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 20821b331e69SKim Kyuwon 2083fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2084fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 20853932afd5SUlf Hansson return 0; 2086a45c6cb8SMadhusudhan Chikkature } 2087a45c6cb8SMadhusudhan Chikkature #endif 2088a45c6cb8SMadhusudhan Chikkature 2089fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_suspend(struct device *dev) 2090fa4aa2d4SBalaji T K { 2091fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 20922cd3a2a5SAndreas Fenkart unsigned long flags; 2093f945901fSAndreas Fenkart int ret = 0; 2094fa4aa2d4SBalaji T K 20957fc13b87SKefeng Wang host = dev_get_drvdata(dev); 2096fa4aa2d4SBalaji T K omap_hsmmc_context_save(host); 2097927ce944SFelipe Balbi dev_dbg(dev, "disabled\n"); 2098fa4aa2d4SBalaji T K 20992cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 21002cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 21012cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 21022cd3a2a5SAndreas Fenkart /* disable sdio irq handling to prevent race */ 21032cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 21042cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 2105f945901fSAndreas Fenkart 2106f945901fSAndreas Fenkart if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) { 2107f945901fSAndreas Fenkart /* 2108f945901fSAndreas Fenkart * dat1 line low, pending sdio irq 2109f945901fSAndreas Fenkart * race condition: possible irq handler running on 2110f945901fSAndreas Fenkart * multi-core, abort 2111f945901fSAndreas Fenkart */ 2112f945901fSAndreas Fenkart dev_dbg(dev, "pending sdio irq, abort suspend\n"); 21132cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 2114f945901fSAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 2115f945901fSAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 2116f945901fSAndreas Fenkart pm_runtime_mark_last_busy(dev); 2117f945901fSAndreas Fenkart ret = -EBUSY; 2118f945901fSAndreas Fenkart goto abort; 2119f945901fSAndreas Fenkart } 21202cd3a2a5SAndreas Fenkart 212197978a44SAndreas Fenkart pinctrl_pm_select_idle_state(dev); 212297978a44SAndreas Fenkart } else { 212397978a44SAndreas Fenkart pinctrl_pm_select_idle_state(dev); 21242cd3a2a5SAndreas Fenkart } 212597978a44SAndreas Fenkart 2126f945901fSAndreas Fenkart abort: 21272cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2128f945901fSAndreas Fenkart return ret; 2129fa4aa2d4SBalaji T K } 2130fa4aa2d4SBalaji T K 2131fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_resume(struct device *dev) 2132fa4aa2d4SBalaji T K { 2133fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 21342cd3a2a5SAndreas Fenkart unsigned long flags; 2135fa4aa2d4SBalaji T K 21367fc13b87SKefeng Wang host = dev_get_drvdata(dev); 2137fa4aa2d4SBalaji T K omap_hsmmc_context_restore(host); 2138927ce944SFelipe Balbi dev_dbg(dev, "enabled\n"); 2139fa4aa2d4SBalaji T K 21402cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 21412cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 21422cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 21432cd3a2a5SAndreas Fenkart 21449f888b55SUlf Hansson pinctrl_select_default_state(host->dev); 214597978a44SAndreas Fenkart 214697978a44SAndreas Fenkart /* irq lost, if pinmux incorrect */ 21472cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 21482cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 21492cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 215097978a44SAndreas Fenkart } else { 21519f888b55SUlf Hansson pinctrl_select_default_state(host->dev); 21522cd3a2a5SAndreas Fenkart } 21532cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2154fa4aa2d4SBalaji T K return 0; 2155fa4aa2d4SBalaji T K } 2156fa4aa2d4SBalaji T K 21576bba4064SArvind Yadav static const struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 21583d3bbfbdSRuss Dill SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume) 2159fa4aa2d4SBalaji T K .runtime_suspend = omap_hsmmc_runtime_suspend, 2160fa4aa2d4SBalaji T K .runtime_resume = omap_hsmmc_runtime_resume, 2161a791daa1SKevin Hilman }; 2162a791daa1SKevin Hilman 2163a791daa1SKevin Hilman static struct platform_driver omap_hsmmc_driver = { 2164efa25fd3SFelipe Balbi .probe = omap_hsmmc_probe, 21650433c143SBill Pemberton .remove = omap_hsmmc_remove, 2166a45c6cb8SMadhusudhan Chikkature .driver = { 2167a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 216821b2cec6SDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 2169a791daa1SKevin Hilman .pm = &omap_hsmmc_dev_pm_ops, 217046856a68SRajendra Nayak .of_match_table = of_match_ptr(omap_mmc_of_match), 2171a45c6cb8SMadhusudhan Chikkature }, 2172a45c6cb8SMadhusudhan Chikkature }; 2173a45c6cb8SMadhusudhan Chikkature 2174b796450bSFelipe Balbi module_platform_driver(omap_hsmmc_driver); 2175a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2176a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 2177a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 2178a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 2179