1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20ac330f44SAndy Shevchenko #include <linux/kernel.h> 21d900f712SDenis Karpov #include <linux/debugfs.h> 22c5c98927SRussell King #include <linux/dmaengine.h> 23d900f712SDenis Karpov #include <linux/seq_file.h> 24a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 29a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 3046856a68SRajendra Nayak #include <linux/of.h> 3146856a68SRajendra Nayak #include <linux/of_gpio.h> 3246856a68SRajendra Nayak #include <linux/of_device.h> 333451c067SRussell King #include <linux/omap-dma.h> 34a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 3513189e78SJarkko Lavinen #include <linux/mmc/core.h> 3693caf8e6SAdrian Hunter #include <linux/mmc/mmc.h> 37a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 38db0fefc5SAdrian Hunter #include <linux/gpio.h> 39db0fefc5SAdrian Hunter #include <linux/regulator/consumer.h> 40fa4aa2d4SBalaji T K #include <linux/pm_runtime.h> 41a45c6cb8SMadhusudhan Chikkature #include <mach/hardware.h> 42ce491cf8STony Lindgren #include <plat/board.h> 43ce491cf8STony Lindgren #include <plat/mmc.h> 44ce491cf8STony Lindgren #include <plat/cpu.h> 45a45c6cb8SMadhusudhan Chikkature 46a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 4711dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS 0x0014 48a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 49a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 50a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 51a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 52a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 57a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 58a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 59a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 60a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 61a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 62a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 63a45c6cb8SMadhusudhan Chikkature 64a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 65a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 66a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 67a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 68eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 691b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 70a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 71a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 72a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 73a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 74a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 75a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 76a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 77a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 78a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 79a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 80a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 81a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 82a45c6cb8SMadhusudhan Chikkature #define INT_EN_MASK 0x307F0033 83ccdfe3a6SAnand Gadiyar #define BWR_ENABLE (1 << 4) 84ccdfe3a6SAnand Gadiyar #define BRR_ENABLE (1 << 5) 8593caf8e6SAdrian Hunter #define DTO_ENABLE (1 << 20) 86a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 87a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 88a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 89a45c6cb8SMadhusudhan Chikkature #define DMA_EN 0x1 90a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 91a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 92a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 9303b5d924SBalaji T K #define DDR (1 << 19) 9473153010SJarkko Lavinen #define DW8 (1 << 5) 95a45c6cb8SMadhusudhan Chikkature #define CC 0x1 96a45c6cb8SMadhusudhan Chikkature #define TC 0x02 97a45c6cb8SMadhusudhan Chikkature #define OD 0x1 98a45c6cb8SMadhusudhan Chikkature #define ERR (1 << 15) 99a45c6cb8SMadhusudhan Chikkature #define CMD_TIMEOUT (1 << 16) 100a45c6cb8SMadhusudhan Chikkature #define DATA_TIMEOUT (1 << 20) 101a45c6cb8SMadhusudhan Chikkature #define CMD_CRC (1 << 17) 102a45c6cb8SMadhusudhan Chikkature #define DATA_CRC (1 << 21) 103a45c6cb8SMadhusudhan Chikkature #define CARD_ERR (1 << 28) 104a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 105a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 106a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 107a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 108a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 10911dd62a7SDenis Karpov #define SOFTRESET (1 << 1) 11011dd62a7SDenis Karpov #define RESETDONE (1 << 0) 111a45c6cb8SMadhusudhan Chikkature 112fa4aa2d4SBalaji T K #define MMC_AUTOSUSPEND_DELAY 100 113a45c6cb8SMadhusudhan Chikkature #define MMC_TIMEOUT_MS 20 1146b206efeSAndy Shevchenko #define OMAP_MMC_MIN_CLOCK 400000 1156b206efeSAndy Shevchenko #define OMAP_MMC_MAX_CLOCK 52000000 1160005ae73SKishore Kadiyala #define DRIVER_NAME "omap_hsmmc" 117a45c6cb8SMadhusudhan Chikkature 118a45c6cb8SMadhusudhan Chikkature /* 119a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 120a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 121a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 122a45c6cb8SMadhusudhan Chikkature */ 123a45c6cb8SMadhusudhan Chikkature #define mmc_slot(host) (host->pdata->slots[host->slot_id]) 124a45c6cb8SMadhusudhan Chikkature 125a45c6cb8SMadhusudhan Chikkature /* 126a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 127a45c6cb8SMadhusudhan Chikkature */ 128a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 129a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 130a45c6cb8SMadhusudhan Chikkature 131a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 132a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 133a45c6cb8SMadhusudhan Chikkature 1349782aff8SPer Forlin struct omap_hsmmc_next { 1359782aff8SPer Forlin unsigned int dma_len; 1369782aff8SPer Forlin s32 cookie; 1379782aff8SPer Forlin }; 1389782aff8SPer Forlin 13970a3341aSDenis Karpov struct omap_hsmmc_host { 140a45c6cb8SMadhusudhan Chikkature struct device *dev; 141a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 142a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 143a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 144a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 145a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 146a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 147db0fefc5SAdrian Hunter /* 148db0fefc5SAdrian Hunter * vcc == configured supply 149db0fefc5SAdrian Hunter * vcc_aux == optional 150db0fefc5SAdrian Hunter * - MMC1, supply for DAT4..DAT7 151db0fefc5SAdrian Hunter * - MMC2/MMC2, external level shifter voltage supply, for 152db0fefc5SAdrian Hunter * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) 153db0fefc5SAdrian Hunter */ 154db0fefc5SAdrian Hunter struct regulator *vcc; 155db0fefc5SAdrian Hunter struct regulator *vcc_aux; 156a45c6cb8SMadhusudhan Chikkature void __iomem *base; 157a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 1584dffd7a2SAdrian Hunter spinlock_t irq_lock; /* Prevent races with irq handler */ 159a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 1600ccd76d4SJuha Yrjola unsigned int dma_sg_idx; 161a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 162a3621465SAdrian Hunter unsigned char power_mode; 163a45c6cb8SMadhusudhan Chikkature int suspended; 164a45c6cb8SMadhusudhan Chikkature int irq; 165a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 166c5c98927SRussell King struct dma_chan *tx_chan; 167c5c98927SRussell King struct dma_chan *rx_chan; 168a45c6cb8SMadhusudhan Chikkature int slot_id; 1694a694dc9SAdrian Hunter int response_busy; 17011dd62a7SDenis Karpov int context_loss; 171b62f6228SAdrian Hunter int protect_card; 172b62f6228SAdrian Hunter int reqs_blocked; 173db0fefc5SAdrian Hunter int use_reg; 174b417577dSAdrian Hunter int req_in_progress; 1759782aff8SPer Forlin struct omap_hsmmc_next next_data; 17611dd62a7SDenis Karpov 177a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata; 178a45c6cb8SMadhusudhan Chikkature }; 179a45c6cb8SMadhusudhan Chikkature 180db0fefc5SAdrian Hunter static int omap_hsmmc_card_detect(struct device *dev, int slot) 181db0fefc5SAdrian Hunter { 182db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 183db0fefc5SAdrian Hunter 184db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 185db0fefc5SAdrian Hunter return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 186db0fefc5SAdrian Hunter } 187db0fefc5SAdrian Hunter 188db0fefc5SAdrian Hunter static int omap_hsmmc_get_wp(struct device *dev, int slot) 189db0fefc5SAdrian Hunter { 190db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 191db0fefc5SAdrian Hunter 192db0fefc5SAdrian Hunter /* NOTE: assumes write protect signal is active-high */ 193db0fefc5SAdrian Hunter return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); 194db0fefc5SAdrian Hunter } 195db0fefc5SAdrian Hunter 196db0fefc5SAdrian Hunter static int omap_hsmmc_get_cover_state(struct device *dev, int slot) 197db0fefc5SAdrian Hunter { 198db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 199db0fefc5SAdrian Hunter 200db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 201db0fefc5SAdrian Hunter return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 202db0fefc5SAdrian Hunter } 203db0fefc5SAdrian Hunter 204db0fefc5SAdrian Hunter #ifdef CONFIG_PM 205db0fefc5SAdrian Hunter 206db0fefc5SAdrian Hunter static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) 207db0fefc5SAdrian Hunter { 208db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 209db0fefc5SAdrian Hunter 210db0fefc5SAdrian Hunter disable_irq(mmc->slots[0].card_detect_irq); 211db0fefc5SAdrian Hunter return 0; 212db0fefc5SAdrian Hunter } 213db0fefc5SAdrian Hunter 214db0fefc5SAdrian Hunter static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) 215db0fefc5SAdrian Hunter { 216db0fefc5SAdrian Hunter struct omap_mmc_platform_data *mmc = dev->platform_data; 217db0fefc5SAdrian Hunter 218db0fefc5SAdrian Hunter enable_irq(mmc->slots[0].card_detect_irq); 219db0fefc5SAdrian Hunter return 0; 220db0fefc5SAdrian Hunter } 221db0fefc5SAdrian Hunter 222db0fefc5SAdrian Hunter #else 223db0fefc5SAdrian Hunter 224db0fefc5SAdrian Hunter #define omap_hsmmc_suspend_cdirq NULL 225db0fefc5SAdrian Hunter #define omap_hsmmc_resume_cdirq NULL 226db0fefc5SAdrian Hunter 227db0fefc5SAdrian Hunter #endif 228db0fefc5SAdrian Hunter 229b702b106SAdrian Hunter #ifdef CONFIG_REGULATOR 230b702b106SAdrian Hunter 23169b07eceSRajendra Nayak static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on, 232db0fefc5SAdrian Hunter int vdd) 233db0fefc5SAdrian Hunter { 234db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 235db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 236db0fefc5SAdrian Hunter int ret = 0; 237db0fefc5SAdrian Hunter 238db0fefc5SAdrian Hunter /* 239db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 240db0fefc5SAdrian Hunter * voltage always-on regulator. 241db0fefc5SAdrian Hunter */ 242db0fefc5SAdrian Hunter if (!host->vcc) 243db0fefc5SAdrian Hunter return 0; 2441f84b71bSRajendra Nayak /* 2451f84b71bSRajendra Nayak * With DT, never turn OFF the regulator. This is because 2461f84b71bSRajendra Nayak * the pbias cell programming support is still missing when 2471f84b71bSRajendra Nayak * booting with Device tree 2481f84b71bSRajendra Nayak */ 2494d048f91SRajendra Nayak if (dev->of_node && !vdd) 2501f84b71bSRajendra Nayak return 0; 251db0fefc5SAdrian Hunter 252db0fefc5SAdrian Hunter if (mmc_slot(host).before_set_reg) 253db0fefc5SAdrian Hunter mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 254db0fefc5SAdrian Hunter 255db0fefc5SAdrian Hunter /* 256db0fefc5SAdrian Hunter * Assume Vcc regulator is used only to power the card ... OMAP 257db0fefc5SAdrian Hunter * VDDS is used to power the pins, optionally with a transceiver to 258db0fefc5SAdrian Hunter * support cards using voltages other than VDDS (1.8V nominal). When a 259db0fefc5SAdrian Hunter * transceiver is used, DAT3..7 are muxed as transceiver control pins. 260db0fefc5SAdrian Hunter * 261db0fefc5SAdrian Hunter * In some cases this regulator won't support enable/disable; 262db0fefc5SAdrian Hunter * e.g. it's a fixed rail for a WLAN chip. 263db0fefc5SAdrian Hunter * 264db0fefc5SAdrian Hunter * In other cases vcc_aux switches interface power. Example, for 265db0fefc5SAdrian Hunter * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 266db0fefc5SAdrian Hunter * chips/cards need an interface voltage rail too. 267db0fefc5SAdrian Hunter */ 268db0fefc5SAdrian Hunter if (power_on) { 26999fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 270db0fefc5SAdrian Hunter /* Enable interface voltage rail, if needed */ 271db0fefc5SAdrian Hunter if (ret == 0 && host->vcc_aux) { 272db0fefc5SAdrian Hunter ret = regulator_enable(host->vcc_aux); 273db0fefc5SAdrian Hunter if (ret < 0) 27499fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 27599fc5131SLinus Walleij host->vcc, 0); 276db0fefc5SAdrian Hunter } 277db0fefc5SAdrian Hunter } else { 27899fc5131SLinus Walleij /* Shut down the rail */ 2796da20c89SAdrian Hunter if (host->vcc_aux) 280db0fefc5SAdrian Hunter ret = regulator_disable(host->vcc_aux); 28199fc5131SLinus Walleij if (!ret) { 28299fc5131SLinus Walleij /* Then proceed to shut down the local regulator */ 28399fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 28499fc5131SLinus Walleij host->vcc, 0); 28599fc5131SLinus Walleij } 286db0fefc5SAdrian Hunter } 287db0fefc5SAdrian Hunter 288db0fefc5SAdrian Hunter if (mmc_slot(host).after_set_reg) 289db0fefc5SAdrian Hunter mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 290db0fefc5SAdrian Hunter 291db0fefc5SAdrian Hunter return ret; 292db0fefc5SAdrian Hunter } 293db0fefc5SAdrian Hunter 294db0fefc5SAdrian Hunter static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 295db0fefc5SAdrian Hunter { 296db0fefc5SAdrian Hunter struct regulator *reg; 29764be9782Skishore kadiyala int ocr_value = 0; 298db0fefc5SAdrian Hunter 299db0fefc5SAdrian Hunter reg = regulator_get(host->dev, "vmmc"); 300db0fefc5SAdrian Hunter if (IS_ERR(reg)) { 301db0fefc5SAdrian Hunter dev_dbg(host->dev, "vmmc regulator missing\n"); 3021fdc90fbSNeilBrown return PTR_ERR(reg); 303db0fefc5SAdrian Hunter } else { 3041fdc90fbSNeilBrown mmc_slot(host).set_power = omap_hsmmc_set_power; 305db0fefc5SAdrian Hunter host->vcc = reg; 30664be9782Skishore kadiyala ocr_value = mmc_regulator_get_ocrmask(reg); 30764be9782Skishore kadiyala if (!mmc_slot(host).ocr_mask) { 30864be9782Skishore kadiyala mmc_slot(host).ocr_mask = ocr_value; 30964be9782Skishore kadiyala } else { 31064be9782Skishore kadiyala if (!(mmc_slot(host).ocr_mask & ocr_value)) { 3112cecdf00SRajendra Nayak dev_err(host->dev, "ocrmask %x is not supported\n", 312e3f1adb6SRajendra Nayak mmc_slot(host).ocr_mask); 31364be9782Skishore kadiyala mmc_slot(host).ocr_mask = 0; 31464be9782Skishore kadiyala return -EINVAL; 31564be9782Skishore kadiyala } 31664be9782Skishore kadiyala } 317db0fefc5SAdrian Hunter 318db0fefc5SAdrian Hunter /* Allow an aux regulator */ 319db0fefc5SAdrian Hunter reg = regulator_get(host->dev, "vmmc_aux"); 320db0fefc5SAdrian Hunter host->vcc_aux = IS_ERR(reg) ? NULL : reg; 321db0fefc5SAdrian Hunter 322b1c1df7aSBalaji T K /* For eMMC do not power off when not in sleep state */ 323b1c1df7aSBalaji T K if (mmc_slot(host).no_regulator_off_init) 324b1c1df7aSBalaji T K return 0; 325db0fefc5SAdrian Hunter /* 326db0fefc5SAdrian Hunter * UGLY HACK: workaround regulator framework bugs. 327db0fefc5SAdrian Hunter * When the bootloader leaves a supply active, it's 328db0fefc5SAdrian Hunter * initialized with zero usecount ... and we can't 329db0fefc5SAdrian Hunter * disable it without first enabling it. Until the 330db0fefc5SAdrian Hunter * framework is fixed, we need a workaround like this 331db0fefc5SAdrian Hunter * (which is safe for MMC, but not in general). 332db0fefc5SAdrian Hunter */ 333e840ce13SAdrian Hunter if (regulator_is_enabled(host->vcc) > 0 || 334e840ce13SAdrian Hunter (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) { 335e840ce13SAdrian Hunter int vdd = ffs(mmc_slot(host).ocr_mask) - 1; 336e840ce13SAdrian Hunter 337e840ce13SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 338e840ce13SAdrian Hunter 1, vdd); 339e840ce13SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 340e840ce13SAdrian Hunter 0, 0); 341db0fefc5SAdrian Hunter } 342db0fefc5SAdrian Hunter } 343db0fefc5SAdrian Hunter 344db0fefc5SAdrian Hunter return 0; 345db0fefc5SAdrian Hunter } 346db0fefc5SAdrian Hunter 347db0fefc5SAdrian Hunter static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 348db0fefc5SAdrian Hunter { 349db0fefc5SAdrian Hunter regulator_put(host->vcc); 350db0fefc5SAdrian Hunter regulator_put(host->vcc_aux); 351db0fefc5SAdrian Hunter mmc_slot(host).set_power = NULL; 352db0fefc5SAdrian Hunter } 353db0fefc5SAdrian Hunter 354b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 355b702b106SAdrian Hunter { 356b702b106SAdrian Hunter return 1; 357b702b106SAdrian Hunter } 358b702b106SAdrian Hunter 359b702b106SAdrian Hunter #else 360b702b106SAdrian Hunter 361b702b106SAdrian Hunter static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 362b702b106SAdrian Hunter { 363b702b106SAdrian Hunter return -EINVAL; 364b702b106SAdrian Hunter } 365b702b106SAdrian Hunter 366b702b106SAdrian Hunter static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 367b702b106SAdrian Hunter { 368b702b106SAdrian Hunter } 369b702b106SAdrian Hunter 370b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 371b702b106SAdrian Hunter { 372b702b106SAdrian Hunter return 0; 373b702b106SAdrian Hunter } 374b702b106SAdrian Hunter 375b702b106SAdrian Hunter #endif 376b702b106SAdrian Hunter 377b702b106SAdrian Hunter static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) 378b702b106SAdrian Hunter { 379b702b106SAdrian Hunter int ret; 380b702b106SAdrian Hunter 381b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) { 382b702b106SAdrian Hunter if (pdata->slots[0].cover) 383b702b106SAdrian Hunter pdata->slots[0].get_cover_state = 384b702b106SAdrian Hunter omap_hsmmc_get_cover_state; 385b702b106SAdrian Hunter else 386b702b106SAdrian Hunter pdata->slots[0].card_detect = omap_hsmmc_card_detect; 387b702b106SAdrian Hunter pdata->slots[0].card_detect_irq = 388b702b106SAdrian Hunter gpio_to_irq(pdata->slots[0].switch_pin); 389b702b106SAdrian Hunter ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd"); 390b702b106SAdrian Hunter if (ret) 391b702b106SAdrian Hunter return ret; 392b702b106SAdrian Hunter ret = gpio_direction_input(pdata->slots[0].switch_pin); 393b702b106SAdrian Hunter if (ret) 394b702b106SAdrian Hunter goto err_free_sp; 395b702b106SAdrian Hunter } else 396b702b106SAdrian Hunter pdata->slots[0].switch_pin = -EINVAL; 397b702b106SAdrian Hunter 398b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].gpio_wp)) { 399b702b106SAdrian Hunter pdata->slots[0].get_ro = omap_hsmmc_get_wp; 400b702b106SAdrian Hunter ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp"); 401b702b106SAdrian Hunter if (ret) 402b702b106SAdrian Hunter goto err_free_cd; 403b702b106SAdrian Hunter ret = gpio_direction_input(pdata->slots[0].gpio_wp); 404b702b106SAdrian Hunter if (ret) 405b702b106SAdrian Hunter goto err_free_wp; 406b702b106SAdrian Hunter } else 407b702b106SAdrian Hunter pdata->slots[0].gpio_wp = -EINVAL; 408b702b106SAdrian Hunter 409b702b106SAdrian Hunter return 0; 410b702b106SAdrian Hunter 411b702b106SAdrian Hunter err_free_wp: 412b702b106SAdrian Hunter gpio_free(pdata->slots[0].gpio_wp); 413b702b106SAdrian Hunter err_free_cd: 414b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) 415b702b106SAdrian Hunter err_free_sp: 416b702b106SAdrian Hunter gpio_free(pdata->slots[0].switch_pin); 417b702b106SAdrian Hunter return ret; 418b702b106SAdrian Hunter } 419b702b106SAdrian Hunter 420b702b106SAdrian Hunter static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) 421b702b106SAdrian Hunter { 422b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].gpio_wp)) 423b702b106SAdrian Hunter gpio_free(pdata->slots[0].gpio_wp); 424b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) 425b702b106SAdrian Hunter gpio_free(pdata->slots[0].switch_pin); 426b702b106SAdrian Hunter } 427b702b106SAdrian Hunter 428a45c6cb8SMadhusudhan Chikkature /* 429e0c7f99bSAndy Shevchenko * Start clock to the card 430e0c7f99bSAndy Shevchenko */ 431e0c7f99bSAndy Shevchenko static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 432e0c7f99bSAndy Shevchenko { 433e0c7f99bSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 434e0c7f99bSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 435e0c7f99bSAndy Shevchenko } 436e0c7f99bSAndy Shevchenko 437e0c7f99bSAndy Shevchenko /* 438a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 439a45c6cb8SMadhusudhan Chikkature */ 44070a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 441a45c6cb8SMadhusudhan Chikkature { 442a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 443a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 444a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 445a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n"); 446a45c6cb8SMadhusudhan Chikkature } 447a45c6cb8SMadhusudhan Chikkature 44893caf8e6SAdrian Hunter static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 44993caf8e6SAdrian Hunter struct mmc_command *cmd) 450b417577dSAdrian Hunter { 451b417577dSAdrian Hunter unsigned int irq_mask; 452b417577dSAdrian Hunter 453b417577dSAdrian Hunter if (host->use_dma) 454b417577dSAdrian Hunter irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE); 455b417577dSAdrian Hunter else 456b417577dSAdrian Hunter irq_mask = INT_EN_MASK; 457b417577dSAdrian Hunter 45893caf8e6SAdrian Hunter /* Disable timeout for erases */ 45993caf8e6SAdrian Hunter if (cmd->opcode == MMC_ERASE) 46093caf8e6SAdrian Hunter irq_mask &= ~DTO_ENABLE; 46193caf8e6SAdrian Hunter 462b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 463b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 464b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 465b417577dSAdrian Hunter } 466b417577dSAdrian Hunter 467b417577dSAdrian Hunter static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 468b417577dSAdrian Hunter { 469b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, 0); 470b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, 0); 471b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 472b417577dSAdrian Hunter } 473b417577dSAdrian Hunter 474ac330f44SAndy Shevchenko /* Calculate divisor for the given clock frequency */ 475d83b6e03SBalaji TK static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 476ac330f44SAndy Shevchenko { 477ac330f44SAndy Shevchenko u16 dsor = 0; 478ac330f44SAndy Shevchenko 479ac330f44SAndy Shevchenko if (ios->clock) { 480d83b6e03SBalaji TK dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 481ac330f44SAndy Shevchenko if (dsor > 250) 482ac330f44SAndy Shevchenko dsor = 250; 483ac330f44SAndy Shevchenko } 484ac330f44SAndy Shevchenko 485ac330f44SAndy Shevchenko return dsor; 486ac330f44SAndy Shevchenko } 487ac330f44SAndy Shevchenko 4885934df2fSAndy Shevchenko static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 4895934df2fSAndy Shevchenko { 4905934df2fSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 4915934df2fSAndy Shevchenko unsigned long regval; 4925934df2fSAndy Shevchenko unsigned long timeout; 4935934df2fSAndy Shevchenko 4948986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 4955934df2fSAndy Shevchenko 4965934df2fSAndy Shevchenko omap_hsmmc_stop_clock(host); 4975934df2fSAndy Shevchenko 4985934df2fSAndy Shevchenko regval = OMAP_HSMMC_READ(host->base, SYSCTL); 4995934df2fSAndy Shevchenko regval = regval & ~(CLKD_MASK | DTO_MASK); 500d83b6e03SBalaji TK regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16); 5015934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 5025934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 5035934df2fSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 5045934df2fSAndy Shevchenko 5055934df2fSAndy Shevchenko /* Wait till the ICS bit is set */ 5065934df2fSAndy Shevchenko timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 5075934df2fSAndy Shevchenko while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 5085934df2fSAndy Shevchenko && time_before(jiffies, timeout)) 5095934df2fSAndy Shevchenko cpu_relax(); 5105934df2fSAndy Shevchenko 5115934df2fSAndy Shevchenko omap_hsmmc_start_clock(host); 5125934df2fSAndy Shevchenko } 5135934df2fSAndy Shevchenko 5143796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 5153796fb8aSAndy Shevchenko { 5163796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5173796fb8aSAndy Shevchenko u32 con; 5183796fb8aSAndy Shevchenko 5193796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 52003b5d924SBalaji T K if (ios->timing == MMC_TIMING_UHS_DDR50) 52103b5d924SBalaji T K con |= DDR; /* configure in DDR mode */ 52203b5d924SBalaji T K else 52303b5d924SBalaji T K con &= ~DDR; 5243796fb8aSAndy Shevchenko switch (ios->bus_width) { 5253796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_8: 5263796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 5273796fb8aSAndy Shevchenko break; 5283796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_4: 5293796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 5303796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 5313796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 5323796fb8aSAndy Shevchenko break; 5333796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_1: 5343796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 5353796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 5363796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 5373796fb8aSAndy Shevchenko break; 5383796fb8aSAndy Shevchenko } 5393796fb8aSAndy Shevchenko } 5403796fb8aSAndy Shevchenko 5413796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 5423796fb8aSAndy Shevchenko { 5433796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5443796fb8aSAndy Shevchenko u32 con; 5453796fb8aSAndy Shevchenko 5463796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 5473796fb8aSAndy Shevchenko if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 5483796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | OD); 5493796fb8aSAndy Shevchenko else 5503796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 5513796fb8aSAndy Shevchenko } 5523796fb8aSAndy Shevchenko 55311dd62a7SDenis Karpov #ifdef CONFIG_PM 55411dd62a7SDenis Karpov 55511dd62a7SDenis Karpov /* 55611dd62a7SDenis Karpov * Restore the MMC host context, if it was lost as result of a 55711dd62a7SDenis Karpov * power state change. 55811dd62a7SDenis Karpov */ 55970a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 56011dd62a7SDenis Karpov { 56111dd62a7SDenis Karpov struct mmc_ios *ios = &host->mmc->ios; 56211dd62a7SDenis Karpov struct omap_mmc_platform_data *pdata = host->pdata; 56311dd62a7SDenis Karpov int context_loss = 0; 5643796fb8aSAndy Shevchenko u32 hctl, capa; 56511dd62a7SDenis Karpov unsigned long timeout; 56611dd62a7SDenis Karpov 56711dd62a7SDenis Karpov if (pdata->get_context_loss_count) { 56811dd62a7SDenis Karpov context_loss = pdata->get_context_loss_count(host->dev); 56911dd62a7SDenis Karpov if (context_loss < 0) 57011dd62a7SDenis Karpov return 1; 57111dd62a7SDenis Karpov } 57211dd62a7SDenis Karpov 57311dd62a7SDenis Karpov dev_dbg(mmc_dev(host->mmc), "context was %slost\n", 57411dd62a7SDenis Karpov context_loss == host->context_loss ? "not " : ""); 57511dd62a7SDenis Karpov if (host->context_loss == context_loss) 57611dd62a7SDenis Karpov return 1; 57711dd62a7SDenis Karpov 5786c31b215SVenkatraman S if (!OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) 5796c31b215SVenkatraman S return 1; 58011dd62a7SDenis Karpov 581c2200efbSBalaji T K if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 58211dd62a7SDenis Karpov if (host->power_mode != MMC_POWER_OFF && 58311dd62a7SDenis Karpov (1 << ios->vdd) <= MMC_VDD_23_24) 58411dd62a7SDenis Karpov hctl = SDVS18; 58511dd62a7SDenis Karpov else 58611dd62a7SDenis Karpov hctl = SDVS30; 58711dd62a7SDenis Karpov capa = VS30 | VS18; 58811dd62a7SDenis Karpov } else { 58911dd62a7SDenis Karpov hctl = SDVS18; 59011dd62a7SDenis Karpov capa = VS18; 59111dd62a7SDenis Karpov } 59211dd62a7SDenis Karpov 59311dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 59411dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | hctl); 59511dd62a7SDenis Karpov 59611dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CAPA, 59711dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA) | capa); 59811dd62a7SDenis Karpov 59911dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 60011dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 60111dd62a7SDenis Karpov 60211dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 60311dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 60411dd62a7SDenis Karpov && time_before(jiffies, timeout)) 60511dd62a7SDenis Karpov ; 60611dd62a7SDenis Karpov 607b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 60811dd62a7SDenis Karpov 60911dd62a7SDenis Karpov /* Do not initialize card-specific things if the power is off */ 61011dd62a7SDenis Karpov if (host->power_mode == MMC_POWER_OFF) 61111dd62a7SDenis Karpov goto out; 61211dd62a7SDenis Karpov 6133796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 61411dd62a7SDenis Karpov 6155934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 61611dd62a7SDenis Karpov 6173796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 6183796fb8aSAndy Shevchenko 61911dd62a7SDenis Karpov out: 62011dd62a7SDenis Karpov host->context_loss = context_loss; 62111dd62a7SDenis Karpov 62211dd62a7SDenis Karpov dev_dbg(mmc_dev(host->mmc), "context is restored\n"); 62311dd62a7SDenis Karpov return 0; 62411dd62a7SDenis Karpov } 62511dd62a7SDenis Karpov 62611dd62a7SDenis Karpov /* 62711dd62a7SDenis Karpov * Save the MMC host context (store the number of power state changes so far). 62811dd62a7SDenis Karpov */ 62970a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 63011dd62a7SDenis Karpov { 63111dd62a7SDenis Karpov struct omap_mmc_platform_data *pdata = host->pdata; 63211dd62a7SDenis Karpov int context_loss; 63311dd62a7SDenis Karpov 63411dd62a7SDenis Karpov if (pdata->get_context_loss_count) { 63511dd62a7SDenis Karpov context_loss = pdata->get_context_loss_count(host->dev); 63611dd62a7SDenis Karpov if (context_loss < 0) 63711dd62a7SDenis Karpov return; 63811dd62a7SDenis Karpov host->context_loss = context_loss; 63911dd62a7SDenis Karpov } 64011dd62a7SDenis Karpov } 64111dd62a7SDenis Karpov 64211dd62a7SDenis Karpov #else 64311dd62a7SDenis Karpov 64470a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 64511dd62a7SDenis Karpov { 64611dd62a7SDenis Karpov return 0; 64711dd62a7SDenis Karpov } 64811dd62a7SDenis Karpov 64970a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 65011dd62a7SDenis Karpov { 65111dd62a7SDenis Karpov } 65211dd62a7SDenis Karpov 65311dd62a7SDenis Karpov #endif 65411dd62a7SDenis Karpov 655a45c6cb8SMadhusudhan Chikkature /* 656a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 657a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 658a45c6cb8SMadhusudhan Chikkature */ 65970a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host) 660a45c6cb8SMadhusudhan Chikkature { 661a45c6cb8SMadhusudhan Chikkature int reg = 0; 662a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 663a45c6cb8SMadhusudhan Chikkature 664b62f6228SAdrian Hunter if (host->protect_card) 665b62f6228SAdrian Hunter return; 666b62f6228SAdrian Hunter 667a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 668b417577dSAdrian Hunter 669b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 670a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 671a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 672a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 673a45c6cb8SMadhusudhan Chikkature 674a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 675a45c6cb8SMadhusudhan Chikkature while ((reg != CC) && time_before(jiffies, timeout)) 676a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, STAT) & CC; 677a45c6cb8SMadhusudhan Chikkature 678a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 679a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 680c653a6d4SAdrian Hunter 681c653a6d4SAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 682c653a6d4SAdrian Hunter OMAP_HSMMC_READ(host->base, STAT); 683c653a6d4SAdrian Hunter 684a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 685a45c6cb8SMadhusudhan Chikkature } 686a45c6cb8SMadhusudhan Chikkature 687a45c6cb8SMadhusudhan Chikkature static inline 68870a3341aSDenis Karpov int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 689a45c6cb8SMadhusudhan Chikkature { 690a45c6cb8SMadhusudhan Chikkature int r = 1; 691a45c6cb8SMadhusudhan Chikkature 692191d1f1dSDenis Karpov if (mmc_slot(host).get_cover_state) 693191d1f1dSDenis Karpov r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); 694a45c6cb8SMadhusudhan Chikkature return r; 695a45c6cb8SMadhusudhan Chikkature } 696a45c6cb8SMadhusudhan Chikkature 697a45c6cb8SMadhusudhan Chikkature static ssize_t 69870a3341aSDenis Karpov omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 699a45c6cb8SMadhusudhan Chikkature char *buf) 700a45c6cb8SMadhusudhan Chikkature { 701a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 70270a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 703a45c6cb8SMadhusudhan Chikkature 70470a3341aSDenis Karpov return sprintf(buf, "%s\n", 70570a3341aSDenis Karpov omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 706a45c6cb8SMadhusudhan Chikkature } 707a45c6cb8SMadhusudhan Chikkature 70870a3341aSDenis Karpov static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 709a45c6cb8SMadhusudhan Chikkature 710a45c6cb8SMadhusudhan Chikkature static ssize_t 71170a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 712a45c6cb8SMadhusudhan Chikkature char *buf) 713a45c6cb8SMadhusudhan Chikkature { 714a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 71570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 716a45c6cb8SMadhusudhan Chikkature 717191d1f1dSDenis Karpov return sprintf(buf, "%s\n", mmc_slot(host).name); 718a45c6cb8SMadhusudhan Chikkature } 719a45c6cb8SMadhusudhan Chikkature 72070a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 721a45c6cb8SMadhusudhan Chikkature 722a45c6cb8SMadhusudhan Chikkature /* 723a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 724a45c6cb8SMadhusudhan Chikkature */ 725a45c6cb8SMadhusudhan Chikkature static void 72670a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 727a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 728a45c6cb8SMadhusudhan Chikkature { 729a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 730a45c6cb8SMadhusudhan Chikkature 7318986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 732a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 733a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 734a45c6cb8SMadhusudhan Chikkature 73593caf8e6SAdrian Hunter omap_hsmmc_enable_irq(host, cmd); 736a45c6cb8SMadhusudhan Chikkature 7374a694dc9SAdrian Hunter host->response_busy = 0; 738a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 739a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 740a45c6cb8SMadhusudhan Chikkature resptype = 1; 7414a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 7424a694dc9SAdrian Hunter resptype = 3; 7434a694dc9SAdrian Hunter host->response_busy = 1; 7444a694dc9SAdrian Hunter } else 745a45c6cb8SMadhusudhan Chikkature resptype = 2; 746a45c6cb8SMadhusudhan Chikkature } 747a45c6cb8SMadhusudhan Chikkature 748a45c6cb8SMadhusudhan Chikkature /* 749a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 750a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 751a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 752a45c6cb8SMadhusudhan Chikkature */ 753a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 754a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 755a45c6cb8SMadhusudhan Chikkature 756a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 757a45c6cb8SMadhusudhan Chikkature 758a45c6cb8SMadhusudhan Chikkature if (data) { 759a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 760a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 761a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 762a45c6cb8SMadhusudhan Chikkature else 763a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 764a45c6cb8SMadhusudhan Chikkature } 765a45c6cb8SMadhusudhan Chikkature 766a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 767a45c6cb8SMadhusudhan Chikkature cmdreg |= DMA_EN; 768a45c6cb8SMadhusudhan Chikkature 769b417577dSAdrian Hunter host->req_in_progress = 1; 7704dffd7a2SAdrian Hunter 771a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 772a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 773a45c6cb8SMadhusudhan Chikkature } 774a45c6cb8SMadhusudhan Chikkature 7750ccd76d4SJuha Yrjola static int 77670a3341aSDenis Karpov omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 7770ccd76d4SJuha Yrjola { 7780ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) 7790ccd76d4SJuha Yrjola return DMA_TO_DEVICE; 7800ccd76d4SJuha Yrjola else 7810ccd76d4SJuha Yrjola return DMA_FROM_DEVICE; 7820ccd76d4SJuha Yrjola } 7830ccd76d4SJuha Yrjola 784c5c98927SRussell King static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 785c5c98927SRussell King struct mmc_data *data) 786c5c98927SRussell King { 787c5c98927SRussell King return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 788c5c98927SRussell King } 789c5c98927SRussell King 790b417577dSAdrian Hunter static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 791b417577dSAdrian Hunter { 792b417577dSAdrian Hunter int dma_ch; 79331463b14SVenkatraman S unsigned long flags; 794b417577dSAdrian Hunter 79531463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 796b417577dSAdrian Hunter host->req_in_progress = 0; 797b417577dSAdrian Hunter dma_ch = host->dma_ch; 79831463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 799b417577dSAdrian Hunter 800b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 801b417577dSAdrian Hunter /* Do not complete the request if DMA is still in progress */ 802b417577dSAdrian Hunter if (mrq->data && host->use_dma && dma_ch != -1) 803b417577dSAdrian Hunter return; 804b417577dSAdrian Hunter host->mrq = NULL; 805b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 806b417577dSAdrian Hunter } 807b417577dSAdrian Hunter 808a45c6cb8SMadhusudhan Chikkature /* 809a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 810a45c6cb8SMadhusudhan Chikkature */ 811a45c6cb8SMadhusudhan Chikkature static void 81270a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 813a45c6cb8SMadhusudhan Chikkature { 8144a694dc9SAdrian Hunter if (!data) { 8154a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 8164a694dc9SAdrian Hunter 81723050103SAdrian Hunter /* TC before CC from CMD6 - don't know why, but it happens */ 81823050103SAdrian Hunter if (host->cmd && host->cmd->opcode == 6 && 81923050103SAdrian Hunter host->response_busy) { 82023050103SAdrian Hunter host->response_busy = 0; 82123050103SAdrian Hunter return; 82223050103SAdrian Hunter } 82323050103SAdrian Hunter 824b417577dSAdrian Hunter omap_hsmmc_request_done(host, mrq); 8254a694dc9SAdrian Hunter return; 8264a694dc9SAdrian Hunter } 8274a694dc9SAdrian Hunter 828a45c6cb8SMadhusudhan Chikkature host->data = NULL; 829a45c6cb8SMadhusudhan Chikkature 830a45c6cb8SMadhusudhan Chikkature if (!data->error) 831a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 832a45c6cb8SMadhusudhan Chikkature else 833a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 834a45c6cb8SMadhusudhan Chikkature 835fe852273SMing Lei if (!data->stop) { 836dba3c29eSBalaji T K omap_hsmmc_request_done(host, data->mrq); 837fe852273SMing Lei return; 838dba3c29eSBalaji T K } 839fe852273SMing Lei omap_hsmmc_start_command(host, data->stop, NULL); 840a45c6cb8SMadhusudhan Chikkature } 841a45c6cb8SMadhusudhan Chikkature 842a45c6cb8SMadhusudhan Chikkature /* 843a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 844a45c6cb8SMadhusudhan Chikkature */ 845a45c6cb8SMadhusudhan Chikkature static void 84670a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 847a45c6cb8SMadhusudhan Chikkature { 848a45c6cb8SMadhusudhan Chikkature host->cmd = NULL; 849a45c6cb8SMadhusudhan Chikkature 850a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 851a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 852a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 853a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 854a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 855a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 856a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 857a45c6cb8SMadhusudhan Chikkature } else { 858a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 859a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 860a45c6cb8SMadhusudhan Chikkature } 861a45c6cb8SMadhusudhan Chikkature } 862b417577dSAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) 863b417577dSAdrian Hunter omap_hsmmc_request_done(host, cmd->mrq); 864a45c6cb8SMadhusudhan Chikkature } 865a45c6cb8SMadhusudhan Chikkature 866a45c6cb8SMadhusudhan Chikkature /* 867a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 868a45c6cb8SMadhusudhan Chikkature */ 86970a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 870a45c6cb8SMadhusudhan Chikkature { 871b417577dSAdrian Hunter int dma_ch; 87231463b14SVenkatraman S unsigned long flags; 873b417577dSAdrian Hunter 87482788ff5SJarkko Lavinen host->data->error = errno; 875a45c6cb8SMadhusudhan Chikkature 87631463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 877b417577dSAdrian Hunter dma_ch = host->dma_ch; 878b417577dSAdrian Hunter host->dma_ch = -1; 87931463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 880b417577dSAdrian Hunter 881b417577dSAdrian Hunter if (host->use_dma && dma_ch != -1) { 882c5c98927SRussell King struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 883c5c98927SRussell King 884c5c98927SRussell King dmaengine_terminate_all(chan); 885c5c98927SRussell King dma_unmap_sg(chan->device->dev, 886c5c98927SRussell King host->data->sg, host->data->sg_len, 88770a3341aSDenis Karpov omap_hsmmc_get_dma_dir(host, host->data)); 888c5c98927SRussell King 889053bf34fSPer Forlin host->data->host_cookie = 0; 890a45c6cb8SMadhusudhan Chikkature } 891a45c6cb8SMadhusudhan Chikkature host->data = NULL; 892a45c6cb8SMadhusudhan Chikkature } 893a45c6cb8SMadhusudhan Chikkature 894a45c6cb8SMadhusudhan Chikkature /* 895a45c6cb8SMadhusudhan Chikkature * Readable error output 896a45c6cb8SMadhusudhan Chikkature */ 897a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 898699b958bSAdrian Hunter static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 899a45c6cb8SMadhusudhan Chikkature { 900a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 90170a3341aSDenis Karpov static const char *omap_hsmmc_status_bits[] = { 902699b958bSAdrian Hunter "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 903699b958bSAdrian Hunter "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 904699b958bSAdrian Hunter "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 905699b958bSAdrian Hunter "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 906a45c6cb8SMadhusudhan Chikkature }; 907a45c6cb8SMadhusudhan Chikkature char res[256]; 908a45c6cb8SMadhusudhan Chikkature char *buf = res; 909a45c6cb8SMadhusudhan Chikkature int len, i; 910a45c6cb8SMadhusudhan Chikkature 911a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 912a45c6cb8SMadhusudhan Chikkature buf += len; 913a45c6cb8SMadhusudhan Chikkature 91470a3341aSDenis Karpov for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 915a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 91670a3341aSDenis Karpov len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 917a45c6cb8SMadhusudhan Chikkature buf += len; 918a45c6cb8SMadhusudhan Chikkature } 919a45c6cb8SMadhusudhan Chikkature 9208986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 921a45c6cb8SMadhusudhan Chikkature } 922699b958bSAdrian Hunter #else 923699b958bSAdrian Hunter static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 924699b958bSAdrian Hunter u32 status) 925699b958bSAdrian Hunter { 926699b958bSAdrian Hunter } 927a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 928a45c6cb8SMadhusudhan Chikkature 9293ebf74b1SJean Pihet /* 9303ebf74b1SJean Pihet * MMC controller internal state machines reset 9313ebf74b1SJean Pihet * 9323ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 9333ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 9343ebf74b1SJean Pihet * Can be called from interrupt context 9353ebf74b1SJean Pihet */ 93670a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 9373ebf74b1SJean Pihet unsigned long bit) 9383ebf74b1SJean Pihet { 9393ebf74b1SJean Pihet unsigned long i = 0; 9403ebf74b1SJean Pihet unsigned long limit = (loops_per_jiffy * 9413ebf74b1SJean Pihet msecs_to_jiffies(MMC_TIMEOUT_MS)); 9423ebf74b1SJean Pihet 9433ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 9443ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 9453ebf74b1SJean Pihet 94607ad64b6SMadhusudhan Chikkature /* 94707ad64b6SMadhusudhan Chikkature * OMAP4 ES2 and greater has an updated reset logic. 94807ad64b6SMadhusudhan Chikkature * Monitor a 0->1 transition first 94907ad64b6SMadhusudhan Chikkature */ 95007ad64b6SMadhusudhan Chikkature if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) { 951b432b4b3Skishore kadiyala while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 95207ad64b6SMadhusudhan Chikkature && (i++ < limit)) 95307ad64b6SMadhusudhan Chikkature cpu_relax(); 95407ad64b6SMadhusudhan Chikkature } 95507ad64b6SMadhusudhan Chikkature i = 0; 95607ad64b6SMadhusudhan Chikkature 9573ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 9583ebf74b1SJean Pihet (i++ < limit)) 9593ebf74b1SJean Pihet cpu_relax(); 9603ebf74b1SJean Pihet 9613ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 9623ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 9633ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 9643ebf74b1SJean Pihet __func__); 9653ebf74b1SJean Pihet } 966a45c6cb8SMadhusudhan Chikkature 967b417577dSAdrian Hunter static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 968a45c6cb8SMadhusudhan Chikkature { 969a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 970b417577dSAdrian Hunter int end_cmd = 0, end_trans = 0; 971a45c6cb8SMadhusudhan Chikkature 972a45c6cb8SMadhusudhan Chikkature data = host->data; 9738986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 974a45c6cb8SMadhusudhan Chikkature 975a45c6cb8SMadhusudhan Chikkature if (status & ERR) { 976699b958bSAdrian Hunter omap_hsmmc_dbg_report_irq(host, status); 977a45c6cb8SMadhusudhan Chikkature if ((status & CMD_TIMEOUT) || 978a45c6cb8SMadhusudhan Chikkature (status & CMD_CRC)) { 979a45c6cb8SMadhusudhan Chikkature if (host->cmd) { 980a45c6cb8SMadhusudhan Chikkature if (status & CMD_TIMEOUT) { 98170a3341aSDenis Karpov omap_hsmmc_reset_controller_fsm(host, 982191d1f1dSDenis Karpov SRC); 983a45c6cb8SMadhusudhan Chikkature host->cmd->error = -ETIMEDOUT; 984a45c6cb8SMadhusudhan Chikkature } else { 985a45c6cb8SMadhusudhan Chikkature host->cmd->error = -EILSEQ; 986a45c6cb8SMadhusudhan Chikkature } 987a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 988a45c6cb8SMadhusudhan Chikkature } 9894a694dc9SAdrian Hunter if (host->data || host->response_busy) { 9904a694dc9SAdrian Hunter if (host->data) 99170a3341aSDenis Karpov omap_hsmmc_dma_cleanup(host, 99270a3341aSDenis Karpov -ETIMEDOUT); 9934a694dc9SAdrian Hunter host->response_busy = 0; 99470a3341aSDenis Karpov omap_hsmmc_reset_controller_fsm(host, SRD); 995c232f457SJean Pihet } 996a45c6cb8SMadhusudhan Chikkature } 997a45c6cb8SMadhusudhan Chikkature if ((status & DATA_TIMEOUT) || 998a45c6cb8SMadhusudhan Chikkature (status & DATA_CRC)) { 9994a694dc9SAdrian Hunter if (host->data || host->response_busy) { 10004a694dc9SAdrian Hunter int err = (status & DATA_TIMEOUT) ? 10014a694dc9SAdrian Hunter -ETIMEDOUT : -EILSEQ; 10024a694dc9SAdrian Hunter 10034a694dc9SAdrian Hunter if (host->data) 100470a3341aSDenis Karpov omap_hsmmc_dma_cleanup(host, err); 1005a45c6cb8SMadhusudhan Chikkature else 10064a694dc9SAdrian Hunter host->mrq->cmd->error = err; 10074a694dc9SAdrian Hunter host->response_busy = 0; 100870a3341aSDenis Karpov omap_hsmmc_reset_controller_fsm(host, SRD); 1009a45c6cb8SMadhusudhan Chikkature end_trans = 1; 1010a45c6cb8SMadhusudhan Chikkature } 1011a45c6cb8SMadhusudhan Chikkature } 1012a45c6cb8SMadhusudhan Chikkature if (status & CARD_ERR) { 1013a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1014a45c6cb8SMadhusudhan Chikkature "Ignoring card err CMD%d\n", host->cmd->opcode); 1015a45c6cb8SMadhusudhan Chikkature if (host->cmd) 1016a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1017a45c6cb8SMadhusudhan Chikkature if (host->data) 1018a45c6cb8SMadhusudhan Chikkature end_trans = 1; 1019a45c6cb8SMadhusudhan Chikkature } 1020a45c6cb8SMadhusudhan Chikkature } 1021a45c6cb8SMadhusudhan Chikkature 1022a8fe29d8SJarkko Lavinen if (end_cmd || ((status & CC) && host->cmd)) 102370a3341aSDenis Karpov omap_hsmmc_cmd_done(host, host->cmd); 10240a40e647SJarkko Lavinen if ((end_trans || (status & TC)) && host->mrq) 102570a3341aSDenis Karpov omap_hsmmc_xfer_done(host, data); 1026b417577dSAdrian Hunter } 1027a45c6cb8SMadhusudhan Chikkature 1028b417577dSAdrian Hunter /* 1029b417577dSAdrian Hunter * MMC controller IRQ handler 1030b417577dSAdrian Hunter */ 1031b417577dSAdrian Hunter static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1032b417577dSAdrian Hunter { 1033b417577dSAdrian Hunter struct omap_hsmmc_host *host = dev_id; 1034b417577dSAdrian Hunter int status; 1035b417577dSAdrian Hunter 1036b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 10371f6b9fa4SVenkatraman S while (status & INT_EN_MASK && host->req_in_progress) { 1038b417577dSAdrian Hunter omap_hsmmc_do_irq(host, status); 10391f6b9fa4SVenkatraman S 1040b417577dSAdrian Hunter /* Flush posted write */ 10411f6b9fa4SVenkatraman S OMAP_HSMMC_WRITE(host->base, STAT, status); 1042b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 10431f6b9fa4SVenkatraman S } 10444dffd7a2SAdrian Hunter 1045a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1046a45c6cb8SMadhusudhan Chikkature } 1047a45c6cb8SMadhusudhan Chikkature 104870a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host) 1049e13bb300SAdrian Hunter { 1050e13bb300SAdrian Hunter unsigned long i; 1051e13bb300SAdrian Hunter 1052e13bb300SAdrian Hunter OMAP_HSMMC_WRITE(host->base, HCTL, 1053e13bb300SAdrian Hunter OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1054e13bb300SAdrian Hunter for (i = 0; i < loops_per_jiffy; i++) { 1055e13bb300SAdrian Hunter if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1056e13bb300SAdrian Hunter break; 1057e13bb300SAdrian Hunter cpu_relax(); 1058e13bb300SAdrian Hunter } 1059e13bb300SAdrian Hunter } 1060e13bb300SAdrian Hunter 1061a45c6cb8SMadhusudhan Chikkature /* 1062eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 1063eb250826SDavid Brownell * 1064eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1065eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1066eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 1067a45c6cb8SMadhusudhan Chikkature */ 106870a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1069a45c6cb8SMadhusudhan Chikkature { 1070a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 1071a45c6cb8SMadhusudhan Chikkature int ret; 1072a45c6cb8SMadhusudhan Chikkature 1073a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 1074fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 1075cd03d9a8SRajendra Nayak if (host->dbclk) 107694c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 1077a45c6cb8SMadhusudhan Chikkature 1078a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 1079a45c6cb8SMadhusudhan Chikkature ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 1080a45c6cb8SMadhusudhan Chikkature 1081a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 10822bec0893SAdrian Hunter if (!ret) 10832bec0893SAdrian Hunter ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, 10842bec0893SAdrian Hunter vdd); 1085fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1086cd03d9a8SRajendra Nayak if (host->dbclk) 108794c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 10882bec0893SAdrian Hunter 1089a45c6cb8SMadhusudhan Chikkature if (ret != 0) 1090a45c6cb8SMadhusudhan Chikkature goto err; 1091a45c6cb8SMadhusudhan Chikkature 1092a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1093a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1094a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1095eb250826SDavid Brownell 1096a45c6cb8SMadhusudhan Chikkature /* 1097a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 1098a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 109970a3341aSDenis Karpov * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1100a45c6cb8SMadhusudhan Chikkature * 1101eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 1102eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1103eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 1104eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1105eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 1106eb250826SDavid Brownell * 1107eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 1108eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1109eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1110a45c6cb8SMadhusudhan Chikkature */ 1111eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 1112a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 1113eb250826SDavid Brownell else 1114eb250826SDavid Brownell reg_val |= SDVS30; 1115a45c6cb8SMadhusudhan Chikkature 1116a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1117e13bb300SAdrian Hunter set_sd_bus_power(host); 1118a45c6cb8SMadhusudhan Chikkature 1119a45c6cb8SMadhusudhan Chikkature return 0; 1120a45c6cb8SMadhusudhan Chikkature err: 1121a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1122a45c6cb8SMadhusudhan Chikkature return ret; 1123a45c6cb8SMadhusudhan Chikkature } 1124a45c6cb8SMadhusudhan Chikkature 1125b62f6228SAdrian Hunter /* Protect the card while the cover is open */ 1126b62f6228SAdrian Hunter static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1127b62f6228SAdrian Hunter { 1128b62f6228SAdrian Hunter if (!mmc_slot(host).get_cover_state) 1129b62f6228SAdrian Hunter return; 1130b62f6228SAdrian Hunter 1131b62f6228SAdrian Hunter host->reqs_blocked = 0; 1132b62f6228SAdrian Hunter if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) { 1133b62f6228SAdrian Hunter if (host->protect_card) { 11342cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is closed, " 1135b62f6228SAdrian Hunter "card is now accessible\n", 1136b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1137b62f6228SAdrian Hunter host->protect_card = 0; 1138b62f6228SAdrian Hunter } 1139b62f6228SAdrian Hunter } else { 1140b62f6228SAdrian Hunter if (!host->protect_card) { 11412cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is open, " 1142b62f6228SAdrian Hunter "card is now inaccessible\n", 1143b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1144b62f6228SAdrian Hunter host->protect_card = 1; 1145b62f6228SAdrian Hunter } 1146b62f6228SAdrian Hunter } 1147b62f6228SAdrian Hunter } 1148b62f6228SAdrian Hunter 1149a45c6cb8SMadhusudhan Chikkature /* 11507efab4f3SNeilBrown * irq handler to notify the core about card insertion/removal 1151a45c6cb8SMadhusudhan Chikkature */ 11527efab4f3SNeilBrown static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id) 1153a45c6cb8SMadhusudhan Chikkature { 11547efab4f3SNeilBrown struct omap_hsmmc_host *host = dev_id; 1155249d0fa9SDavid Brownell struct omap_mmc_slot_data *slot = &mmc_slot(host); 1156a6b2240dSAdrian Hunter int carddetect; 1157249d0fa9SDavid Brownell 1158a6b2240dSAdrian Hunter if (host->suspended) 11597efab4f3SNeilBrown return IRQ_HANDLED; 1160a45c6cb8SMadhusudhan Chikkature 1161a45c6cb8SMadhusudhan Chikkature sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1162a6b2240dSAdrian Hunter 1163191d1f1dSDenis Karpov if (slot->card_detect) 1164db0fefc5SAdrian Hunter carddetect = slot->card_detect(host->dev, host->slot_id); 1165b62f6228SAdrian Hunter else { 1166b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 1167a6b2240dSAdrian Hunter carddetect = -ENOSYS; 1168b62f6228SAdrian Hunter } 1169a6b2240dSAdrian Hunter 1170cdeebaddSMadhusudhan Chikkature if (carddetect) 1171a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1172cdeebaddSMadhusudhan Chikkature else 1173a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 50) / 1000); 1174a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1175a45c6cb8SMadhusudhan Chikkature } 1176a45c6cb8SMadhusudhan Chikkature 1177c5c98927SRussell King static void omap_hsmmc_dma_callback(void *param) 11780ccd76d4SJuha Yrjola { 1179c5c98927SRussell King struct omap_hsmmc_host *host = param; 1180c5c98927SRussell King struct dma_chan *chan; 1181770d7432SAdrian Hunter struct mmc_data *data; 1182c5c98927SRussell King int req_in_progress; 1183a45c6cb8SMadhusudhan Chikkature 1184c5c98927SRussell King spin_lock_irq(&host->irq_lock); 1185b417577dSAdrian Hunter if (host->dma_ch < 0) { 1186c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1187a45c6cb8SMadhusudhan Chikkature return; 1188b417577dSAdrian Hunter } 1189a45c6cb8SMadhusudhan Chikkature 1190770d7432SAdrian Hunter data = host->mrq->data; 1191c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 11929782aff8SPer Forlin if (!data->host_cookie) 1193c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1194c5c98927SRussell King data->sg, data->sg_len, 1195b417577dSAdrian Hunter omap_hsmmc_get_dma_dir(host, data)); 1196b417577dSAdrian Hunter 1197b417577dSAdrian Hunter req_in_progress = host->req_in_progress; 1198a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1199c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1200b417577dSAdrian Hunter 1201b417577dSAdrian Hunter /* If DMA has finished after TC, complete the request */ 1202b417577dSAdrian Hunter if (!req_in_progress) { 1203b417577dSAdrian Hunter struct mmc_request *mrq = host->mrq; 1204b417577dSAdrian Hunter 1205b417577dSAdrian Hunter host->mrq = NULL; 1206b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 1207b417577dSAdrian Hunter } 1208a45c6cb8SMadhusudhan Chikkature } 1209a45c6cb8SMadhusudhan Chikkature 12109782aff8SPer Forlin static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 12119782aff8SPer Forlin struct mmc_data *data, 1212c5c98927SRussell King struct omap_hsmmc_next *next, 121326b88520SRussell King struct dma_chan *chan) 12149782aff8SPer Forlin { 12159782aff8SPer Forlin int dma_len; 12169782aff8SPer Forlin 12179782aff8SPer Forlin if (!next && data->host_cookie && 12189782aff8SPer Forlin data->host_cookie != host->next_data.cookie) { 12192cecdf00SRajendra Nayak dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 12209782aff8SPer Forlin " host->next_data.cookie %d\n", 12219782aff8SPer Forlin __func__, data->host_cookie, host->next_data.cookie); 12229782aff8SPer Forlin data->host_cookie = 0; 12239782aff8SPer Forlin } 12249782aff8SPer Forlin 12259782aff8SPer Forlin /* Check if next job is already prepared */ 12269782aff8SPer Forlin if (next || 12279782aff8SPer Forlin (!next && data->host_cookie != host->next_data.cookie)) { 122826b88520SRussell King dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 12299782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 12309782aff8SPer Forlin 12319782aff8SPer Forlin } else { 12329782aff8SPer Forlin dma_len = host->next_data.dma_len; 12339782aff8SPer Forlin host->next_data.dma_len = 0; 12349782aff8SPer Forlin } 12359782aff8SPer Forlin 12369782aff8SPer Forlin 12379782aff8SPer Forlin if (dma_len == 0) 12389782aff8SPer Forlin return -EINVAL; 12399782aff8SPer Forlin 12409782aff8SPer Forlin if (next) { 12419782aff8SPer Forlin next->dma_len = dma_len; 12429782aff8SPer Forlin data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 12439782aff8SPer Forlin } else 12449782aff8SPer Forlin host->dma_len = dma_len; 12459782aff8SPer Forlin 12469782aff8SPer Forlin return 0; 12479782aff8SPer Forlin } 12489782aff8SPer Forlin 1249a45c6cb8SMadhusudhan Chikkature /* 1250a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 1251a45c6cb8SMadhusudhan Chikkature */ 125270a3341aSDenis Karpov static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host, 125370a3341aSDenis Karpov struct mmc_request *req) 1254a45c6cb8SMadhusudhan Chikkature { 125526b88520SRussell King struct dma_slave_config cfg; 125626b88520SRussell King struct dma_async_tx_descriptor *tx; 125726b88520SRussell King int ret = 0, i; 1258a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 1259c5c98927SRussell King struct dma_chan *chan; 1260a45c6cb8SMadhusudhan Chikkature 12610ccd76d4SJuha Yrjola /* Sanity check: all the SG entries must be aligned by block size. */ 1262a3f406f8SJarkko Lavinen for (i = 0; i < data->sg_len; i++) { 12630ccd76d4SJuha Yrjola struct scatterlist *sgl; 12640ccd76d4SJuha Yrjola 12650ccd76d4SJuha Yrjola sgl = data->sg + i; 12660ccd76d4SJuha Yrjola if (sgl->length % data->blksz) 12670ccd76d4SJuha Yrjola return -EINVAL; 12680ccd76d4SJuha Yrjola } 12690ccd76d4SJuha Yrjola if ((data->blksz % 4) != 0) 12700ccd76d4SJuha Yrjola /* REVISIT: The MMC buffer increments only when MSB is written. 12710ccd76d4SJuha Yrjola * Return error for blksz which is non multiple of four. 12720ccd76d4SJuha Yrjola */ 12730ccd76d4SJuha Yrjola return -EINVAL; 12740ccd76d4SJuha Yrjola 1275b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1276a45c6cb8SMadhusudhan Chikkature 1277c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 1278c5c98927SRussell King 1279c5c98927SRussell King cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA; 1280c5c98927SRussell King cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA; 1281c5c98927SRussell King cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1282c5c98927SRussell King cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1283c5c98927SRussell King cfg.src_maxburst = data->blksz / 4; 1284c5c98927SRussell King cfg.dst_maxburst = data->blksz / 4; 1285c5c98927SRussell King 1286c5c98927SRussell King ret = dmaengine_slave_config(chan, &cfg); 12879782aff8SPer Forlin if (ret) 12889782aff8SPer Forlin return ret; 1289a45c6cb8SMadhusudhan Chikkature 129026b88520SRussell King ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1291c5c98927SRussell King if (ret) 1292c5c98927SRussell King return ret; 1293a45c6cb8SMadhusudhan Chikkature 1294c5c98927SRussell King tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1295c5c98927SRussell King data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1296c5c98927SRussell King DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1297c5c98927SRussell King if (!tx) { 1298c5c98927SRussell King dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1299c5c98927SRussell King /* FIXME: cleanup */ 1300c5c98927SRussell King return -1; 1301c5c98927SRussell King } 1302c5c98927SRussell King 1303c5c98927SRussell King tx->callback = omap_hsmmc_dma_callback; 1304c5c98927SRussell King tx->callback_param = host; 1305c5c98927SRussell King 1306c5c98927SRussell King /* Does not fail */ 1307c5c98927SRussell King dmaengine_submit(tx); 1308c5c98927SRussell King 130926b88520SRussell King host->dma_ch = 1; 1310c5c98927SRussell King 1311c5c98927SRussell King dma_async_issue_pending(chan); 1312a45c6cb8SMadhusudhan Chikkature 1313a45c6cb8SMadhusudhan Chikkature return 0; 1314a45c6cb8SMadhusudhan Chikkature } 1315a45c6cb8SMadhusudhan Chikkature 131670a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host, 1317e2bf08d6SAdrian Hunter unsigned int timeout_ns, 1318e2bf08d6SAdrian Hunter unsigned int timeout_clks) 1319a45c6cb8SMadhusudhan Chikkature { 1320a45c6cb8SMadhusudhan Chikkature unsigned int timeout, cycle_ns; 1321a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 1322a45c6cb8SMadhusudhan Chikkature 1323a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1324a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1325a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 1326a45c6cb8SMadhusudhan Chikkature clkd = 1; 1327a45c6cb8SMadhusudhan Chikkature 1328a45c6cb8SMadhusudhan Chikkature cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); 1329e2bf08d6SAdrian Hunter timeout = timeout_ns / cycle_ns; 1330e2bf08d6SAdrian Hunter timeout += timeout_clks; 1331a45c6cb8SMadhusudhan Chikkature if (timeout) { 1332a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 1333a45c6cb8SMadhusudhan Chikkature dto += 1; 1334a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1335a45c6cb8SMadhusudhan Chikkature } 1336a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 1337a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1338a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 1339a45c6cb8SMadhusudhan Chikkature dto += 1; 1340a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 1341a45c6cb8SMadhusudhan Chikkature dto -= 13; 1342a45c6cb8SMadhusudhan Chikkature else 1343a45c6cb8SMadhusudhan Chikkature dto = 0; 1344a45c6cb8SMadhusudhan Chikkature if (dto > 14) 1345a45c6cb8SMadhusudhan Chikkature dto = 14; 1346a45c6cb8SMadhusudhan Chikkature } 1347a45c6cb8SMadhusudhan Chikkature 1348a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 1349a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 1350a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1351a45c6cb8SMadhusudhan Chikkature } 1352a45c6cb8SMadhusudhan Chikkature 1353a45c6cb8SMadhusudhan Chikkature /* 1354a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 1355a45c6cb8SMadhusudhan Chikkature */ 1356a45c6cb8SMadhusudhan Chikkature static int 135770a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1358a45c6cb8SMadhusudhan Chikkature { 1359a45c6cb8SMadhusudhan Chikkature int ret; 1360a45c6cb8SMadhusudhan Chikkature host->data = req->data; 1361a45c6cb8SMadhusudhan Chikkature 1362a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 1363a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 1364e2bf08d6SAdrian Hunter /* 1365e2bf08d6SAdrian Hunter * Set an arbitrary 100ms data timeout for commands with 1366e2bf08d6SAdrian Hunter * busy signal. 1367e2bf08d6SAdrian Hunter */ 1368e2bf08d6SAdrian Hunter if (req->cmd->flags & MMC_RSP_BUSY) 1369e2bf08d6SAdrian Hunter set_data_timeout(host, 100000000U, 0); 1370a45c6cb8SMadhusudhan Chikkature return 0; 1371a45c6cb8SMadhusudhan Chikkature } 1372a45c6cb8SMadhusudhan Chikkature 1373a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 1374a45c6cb8SMadhusudhan Chikkature | (req->data->blocks << 16)); 1375e2bf08d6SAdrian Hunter set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks); 1376a45c6cb8SMadhusudhan Chikkature 1377a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 137870a3341aSDenis Karpov ret = omap_hsmmc_start_dma_transfer(host, req); 1379a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 1380a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n"); 1381a45c6cb8SMadhusudhan Chikkature return ret; 1382a45c6cb8SMadhusudhan Chikkature } 1383a45c6cb8SMadhusudhan Chikkature } 1384a45c6cb8SMadhusudhan Chikkature return 0; 1385a45c6cb8SMadhusudhan Chikkature } 1386a45c6cb8SMadhusudhan Chikkature 13879782aff8SPer Forlin static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 13889782aff8SPer Forlin int err) 13899782aff8SPer Forlin { 13909782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 13919782aff8SPer Forlin struct mmc_data *data = mrq->data; 13929782aff8SPer Forlin 139326b88520SRussell King if (host->use_dma && data->host_cookie) { 1394c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1395c5c98927SRussell King 139626b88520SRussell King dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 13979782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 13989782aff8SPer Forlin data->host_cookie = 0; 13999782aff8SPer Forlin } 14009782aff8SPer Forlin } 14019782aff8SPer Forlin 14029782aff8SPer Forlin static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 14039782aff8SPer Forlin bool is_first_req) 14049782aff8SPer Forlin { 14059782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 14069782aff8SPer Forlin 14079782aff8SPer Forlin if (mrq->data->host_cookie) { 14089782aff8SPer Forlin mrq->data->host_cookie = 0; 14099782aff8SPer Forlin return ; 14109782aff8SPer Forlin } 14119782aff8SPer Forlin 1412c5c98927SRussell King if (host->use_dma) { 1413c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1414c5c98927SRussell King 14159782aff8SPer Forlin if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 141626b88520SRussell King &host->next_data, c)) 14179782aff8SPer Forlin mrq->data->host_cookie = 0; 14189782aff8SPer Forlin } 1419c5c98927SRussell King } 14209782aff8SPer Forlin 1421a45c6cb8SMadhusudhan Chikkature /* 1422a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 1423a45c6cb8SMadhusudhan Chikkature */ 142470a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1425a45c6cb8SMadhusudhan Chikkature { 142670a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1427a3f406f8SJarkko Lavinen int err; 1428a45c6cb8SMadhusudhan Chikkature 1429b417577dSAdrian Hunter BUG_ON(host->req_in_progress); 1430b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1431b62f6228SAdrian Hunter if (host->protect_card) { 1432b62f6228SAdrian Hunter if (host->reqs_blocked < 3) { 1433b62f6228SAdrian Hunter /* 1434b62f6228SAdrian Hunter * Ensure the controller is left in a consistent 1435b62f6228SAdrian Hunter * state by resetting the command and data state 1436b62f6228SAdrian Hunter * machines. 1437b62f6228SAdrian Hunter */ 1438b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRD); 1439b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRC); 1440b62f6228SAdrian Hunter host->reqs_blocked += 1; 1441b62f6228SAdrian Hunter } 1442b62f6228SAdrian Hunter req->cmd->error = -EBADF; 1443b62f6228SAdrian Hunter if (req->data) 1444b62f6228SAdrian Hunter req->data->error = -EBADF; 1445b417577dSAdrian Hunter req->cmd->retries = 0; 1446b62f6228SAdrian Hunter mmc_request_done(mmc, req); 1447b62f6228SAdrian Hunter return; 1448b62f6228SAdrian Hunter } else if (host->reqs_blocked) 1449b62f6228SAdrian Hunter host->reqs_blocked = 0; 1450a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 1451a45c6cb8SMadhusudhan Chikkature host->mrq = req; 145270a3341aSDenis Karpov err = omap_hsmmc_prepare_data(host, req); 1453a3f406f8SJarkko Lavinen if (err) { 1454a3f406f8SJarkko Lavinen req->cmd->error = err; 1455a3f406f8SJarkko Lavinen if (req->data) 1456a3f406f8SJarkko Lavinen req->data->error = err; 1457a3f406f8SJarkko Lavinen host->mrq = NULL; 1458a3f406f8SJarkko Lavinen mmc_request_done(mmc, req); 1459a3f406f8SJarkko Lavinen return; 1460a3f406f8SJarkko Lavinen } 1461a3f406f8SJarkko Lavinen 146270a3341aSDenis Karpov omap_hsmmc_start_command(host, req->cmd, req->data); 1463a45c6cb8SMadhusudhan Chikkature } 1464a45c6cb8SMadhusudhan Chikkature 1465a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 146670a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1467a45c6cb8SMadhusudhan Chikkature { 146870a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1469a3621465SAdrian Hunter int do_send_init_stream = 0; 1470a45c6cb8SMadhusudhan Chikkature 1471fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 14725e2ea617SAdrian Hunter 1473a3621465SAdrian Hunter if (ios->power_mode != host->power_mode) { 1474a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 1475a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 1476a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1477a3621465SAdrian Hunter 0, 0); 1478a45c6cb8SMadhusudhan Chikkature break; 1479a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 1480a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1481a3621465SAdrian Hunter 1, ios->vdd); 1482a45c6cb8SMadhusudhan Chikkature break; 1483a3621465SAdrian Hunter case MMC_POWER_ON: 1484a3621465SAdrian Hunter do_send_init_stream = 1; 1485a3621465SAdrian Hunter break; 1486a3621465SAdrian Hunter } 1487a3621465SAdrian Hunter host->power_mode = ios->power_mode; 1488a45c6cb8SMadhusudhan Chikkature } 1489a45c6cb8SMadhusudhan Chikkature 1490dd498effSDenis Karpov /* FIXME: set registers based only on changes to ios */ 1491dd498effSDenis Karpov 14923796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 1493a45c6cb8SMadhusudhan Chikkature 14944621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1495eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 1496eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 1497eb250826SDavid Brownell */ 1498a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 14991f84b71bSRajendra Nayak (ios->vdd == DUAL_VOLT_OCR_BIT) && 15001f84b71bSRajendra Nayak /* 15011f84b71bSRajendra Nayak * With pbias cell programming missing, this 15021f84b71bSRajendra Nayak * can't be allowed when booting with device 15031f84b71bSRajendra Nayak * tree. 15041f84b71bSRajendra Nayak */ 15054d048f91SRajendra Nayak !host->dev->of_node) { 1506a45c6cb8SMadhusudhan Chikkature /* 1507a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 1508a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 1509a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 1510a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 1511a45c6cb8SMadhusudhan Chikkature */ 151270a3341aSDenis Karpov if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1513a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1514a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 1515a45c6cb8SMadhusudhan Chikkature } 1516a45c6cb8SMadhusudhan Chikkature } 1517a45c6cb8SMadhusudhan Chikkature 15185934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 1519a45c6cb8SMadhusudhan Chikkature 1520a3621465SAdrian Hunter if (do_send_init_stream) 1521a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 1522a45c6cb8SMadhusudhan Chikkature 15233796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 15245e2ea617SAdrian Hunter 1525fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1526a45c6cb8SMadhusudhan Chikkature } 1527a45c6cb8SMadhusudhan Chikkature 1528a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1529a45c6cb8SMadhusudhan Chikkature { 153070a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1531a45c6cb8SMadhusudhan Chikkature 1532191d1f1dSDenis Karpov if (!mmc_slot(host).card_detect) 1533a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1534db0fefc5SAdrian Hunter return mmc_slot(host).card_detect(host->dev, host->slot_id); 1535a45c6cb8SMadhusudhan Chikkature } 1536a45c6cb8SMadhusudhan Chikkature 1537a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_ro(struct mmc_host *mmc) 1538a45c6cb8SMadhusudhan Chikkature { 153970a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1540a45c6cb8SMadhusudhan Chikkature 1541191d1f1dSDenis Karpov if (!mmc_slot(host).get_ro) 1542a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1543191d1f1dSDenis Karpov return mmc_slot(host).get_ro(host->dev, 0); 1544a45c6cb8SMadhusudhan Chikkature } 1545a45c6cb8SMadhusudhan Chikkature 15464816858cSGrazvydas Ignotas static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 15474816858cSGrazvydas Ignotas { 15484816858cSGrazvydas Ignotas struct omap_hsmmc_host *host = mmc_priv(mmc); 15494816858cSGrazvydas Ignotas 15504816858cSGrazvydas Ignotas if (mmc_slot(host).init_card) 15514816858cSGrazvydas Ignotas mmc_slot(host).init_card(card); 15524816858cSGrazvydas Ignotas } 15534816858cSGrazvydas Ignotas 155470a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 15551b331e69SKim Kyuwon { 15561b331e69SKim Kyuwon u32 hctl, capa, value; 15571b331e69SKim Kyuwon 15581b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 15594621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 15601b331e69SKim Kyuwon hctl = SDVS30; 15611b331e69SKim Kyuwon capa = VS30 | VS18; 15621b331e69SKim Kyuwon } else { 15631b331e69SKim Kyuwon hctl = SDVS18; 15641b331e69SKim Kyuwon capa = VS18; 15651b331e69SKim Kyuwon } 15661b331e69SKim Kyuwon 15671b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 15681b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 15691b331e69SKim Kyuwon 15701b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 15711b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 15721b331e69SKim Kyuwon 15731b331e69SKim Kyuwon /* Set SD bus power bit */ 1574e13bb300SAdrian Hunter set_sd_bus_power(host); 15751b331e69SKim Kyuwon } 15761b331e69SKim Kyuwon 157770a3341aSDenis Karpov static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) 1578dd498effSDenis Karpov { 157970a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1580dd498effSDenis Karpov 1581fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1582fa4aa2d4SBalaji T K 1583dd498effSDenis Karpov return 0; 1584dd498effSDenis Karpov } 1585dd498effSDenis Karpov 1586907d2e7cSAdrian Hunter static int omap_hsmmc_disable_fclk(struct mmc_host *mmc) 1587dd498effSDenis Karpov { 158870a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1589dd498effSDenis Karpov 1590fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1591fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1592fa4aa2d4SBalaji T K 1593dd498effSDenis Karpov return 0; 1594dd498effSDenis Karpov } 1595dd498effSDenis Karpov 159670a3341aSDenis Karpov static const struct mmc_host_ops omap_hsmmc_ops = { 159770a3341aSDenis Karpov .enable = omap_hsmmc_enable_fclk, 159870a3341aSDenis Karpov .disable = omap_hsmmc_disable_fclk, 15999782aff8SPer Forlin .post_req = omap_hsmmc_post_req, 16009782aff8SPer Forlin .pre_req = omap_hsmmc_pre_req, 160170a3341aSDenis Karpov .request = omap_hsmmc_request, 160270a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1603dd498effSDenis Karpov .get_cd = omap_hsmmc_get_cd, 1604dd498effSDenis Karpov .get_ro = omap_hsmmc_get_ro, 16054816858cSGrazvydas Ignotas .init_card = omap_hsmmc_init_card, 1606dd498effSDenis Karpov /* NYET -- enable_sdio_irq */ 1607dd498effSDenis Karpov }; 1608dd498effSDenis Karpov 1609d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS 1610d900f712SDenis Karpov 161170a3341aSDenis Karpov static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1612d900f712SDenis Karpov { 1613d900f712SDenis Karpov struct mmc_host *mmc = s->private; 161470a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 161511dd62a7SDenis Karpov int context_loss = 0; 161611dd62a7SDenis Karpov 161770a3341aSDenis Karpov if (host->pdata->get_context_loss_count) 161870a3341aSDenis Karpov context_loss = host->pdata->get_context_loss_count(host->dev); 1619d900f712SDenis Karpov 1620907d2e7cSAdrian Hunter seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n", 1621907d2e7cSAdrian Hunter mmc->index, host->context_loss, context_loss); 16225e2ea617SAdrian Hunter 16237a8c2cefSBalaji T K if (host->suspended) { 1624dd498effSDenis Karpov seq_printf(s, "host suspended, can't read registers\n"); 1625dd498effSDenis Karpov return 0; 1626dd498effSDenis Karpov } 1627dd498effSDenis Karpov 1628fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1629d900f712SDenis Karpov 1630d900f712SDenis Karpov seq_printf(s, "CON:\t\t0x%08x\n", 1631d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CON)); 1632d900f712SDenis Karpov seq_printf(s, "HCTL:\t\t0x%08x\n", 1633d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL)); 1634d900f712SDenis Karpov seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1635d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL)); 1636d900f712SDenis Karpov seq_printf(s, "IE:\t\t0x%08x\n", 1637d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, IE)); 1638d900f712SDenis Karpov seq_printf(s, "ISE:\t\t0x%08x\n", 1639d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, ISE)); 1640d900f712SDenis Karpov seq_printf(s, "CAPA:\t\t0x%08x\n", 1641d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA)); 16425e2ea617SAdrian Hunter 1643fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1644fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1645dd498effSDenis Karpov 1646d900f712SDenis Karpov return 0; 1647d900f712SDenis Karpov } 1648d900f712SDenis Karpov 164970a3341aSDenis Karpov static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1650d900f712SDenis Karpov { 165170a3341aSDenis Karpov return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1652d900f712SDenis Karpov } 1653d900f712SDenis Karpov 1654d900f712SDenis Karpov static const struct file_operations mmc_regs_fops = { 165570a3341aSDenis Karpov .open = omap_hsmmc_regs_open, 1656d900f712SDenis Karpov .read = seq_read, 1657d900f712SDenis Karpov .llseek = seq_lseek, 1658d900f712SDenis Karpov .release = single_release, 1659d900f712SDenis Karpov }; 1660d900f712SDenis Karpov 166170a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1662d900f712SDenis Karpov { 1663d900f712SDenis Karpov if (mmc->debugfs_root) 1664d900f712SDenis Karpov debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1665d900f712SDenis Karpov mmc, &mmc_regs_fops); 1666d900f712SDenis Karpov } 1667d900f712SDenis Karpov 1668d900f712SDenis Karpov #else 1669d900f712SDenis Karpov 167070a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1671d900f712SDenis Karpov { 1672d900f712SDenis Karpov } 1673d900f712SDenis Karpov 1674d900f712SDenis Karpov #endif 1675d900f712SDenis Karpov 167646856a68SRajendra Nayak #ifdef CONFIG_OF 167746856a68SRajendra Nayak static u16 omap4_reg_offset = 0x100; 167846856a68SRajendra Nayak 167946856a68SRajendra Nayak static const struct of_device_id omap_mmc_of_match[] = { 168046856a68SRajendra Nayak { 168146856a68SRajendra Nayak .compatible = "ti,omap2-hsmmc", 168246856a68SRajendra Nayak }, 168346856a68SRajendra Nayak { 168446856a68SRajendra Nayak .compatible = "ti,omap3-hsmmc", 168546856a68SRajendra Nayak }, 168646856a68SRajendra Nayak { 168746856a68SRajendra Nayak .compatible = "ti,omap4-hsmmc", 168846856a68SRajendra Nayak .data = &omap4_reg_offset, 168946856a68SRajendra Nayak }, 169046856a68SRajendra Nayak {}, 1691b6d085f6SChris Ball }; 169246856a68SRajendra Nayak MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 169346856a68SRajendra Nayak 169446856a68SRajendra Nayak static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 169546856a68SRajendra Nayak { 169646856a68SRajendra Nayak struct omap_mmc_platform_data *pdata; 169746856a68SRajendra Nayak struct device_node *np = dev->of_node; 169846856a68SRajendra Nayak u32 bus_width; 169946856a68SRajendra Nayak 170046856a68SRajendra Nayak pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 170146856a68SRajendra Nayak if (!pdata) 170246856a68SRajendra Nayak return NULL; /* out of memory */ 170346856a68SRajendra Nayak 170446856a68SRajendra Nayak if (of_find_property(np, "ti,dual-volt", NULL)) 170546856a68SRajendra Nayak pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 170646856a68SRajendra Nayak 170746856a68SRajendra Nayak /* This driver only supports 1 slot */ 170846856a68SRajendra Nayak pdata->nr_slots = 1; 170946856a68SRajendra Nayak pdata->slots[0].switch_pin = of_get_named_gpio(np, "cd-gpios", 0); 171046856a68SRajendra Nayak pdata->slots[0].gpio_wp = of_get_named_gpio(np, "wp-gpios", 0); 171146856a68SRajendra Nayak 171246856a68SRajendra Nayak if (of_find_property(np, "ti,non-removable", NULL)) { 171346856a68SRajendra Nayak pdata->slots[0].nonremovable = true; 171446856a68SRajendra Nayak pdata->slots[0].no_regulator_off_init = true; 171546856a68SRajendra Nayak } 17167f217794SArnd Bergmann of_property_read_u32(np, "bus-width", &bus_width); 171746856a68SRajendra Nayak if (bus_width == 4) 171846856a68SRajendra Nayak pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA; 171946856a68SRajendra Nayak else if (bus_width == 8) 172046856a68SRajendra Nayak pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA; 172146856a68SRajendra Nayak 172246856a68SRajendra Nayak if (of_find_property(np, "ti,needs-special-reset", NULL)) 172346856a68SRajendra Nayak pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET; 172446856a68SRajendra Nayak 172546856a68SRajendra Nayak return pdata; 172646856a68SRajendra Nayak } 172746856a68SRajendra Nayak #else 172846856a68SRajendra Nayak static inline struct omap_mmc_platform_data 172946856a68SRajendra Nayak *of_get_hsmmc_pdata(struct device *dev) 173046856a68SRajendra Nayak { 173146856a68SRajendra Nayak return NULL; 173246856a68SRajendra Nayak } 173346856a68SRajendra Nayak #endif 173446856a68SRajendra Nayak 1735efa25fd3SFelipe Balbi static int __devinit omap_hsmmc_probe(struct platform_device *pdev) 1736a45c6cb8SMadhusudhan Chikkature { 1737a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 1738a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 173970a3341aSDenis Karpov struct omap_hsmmc_host *host = NULL; 1740a45c6cb8SMadhusudhan Chikkature struct resource *res; 1741db0fefc5SAdrian Hunter int ret, irq; 174246856a68SRajendra Nayak const struct of_device_id *match; 174326b88520SRussell King dma_cap_mask_t mask; 174426b88520SRussell King unsigned tx_req, rx_req; 174546856a68SRajendra Nayak 174646856a68SRajendra Nayak match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 174746856a68SRajendra Nayak if (match) { 174846856a68SRajendra Nayak pdata = of_get_hsmmc_pdata(&pdev->dev); 174946856a68SRajendra Nayak if (match->data) { 175046856a68SRajendra Nayak u16 *offsetp = match->data; 175146856a68SRajendra Nayak pdata->reg_offset = *offsetp; 175246856a68SRajendra Nayak } 175346856a68SRajendra Nayak } 1754a45c6cb8SMadhusudhan Chikkature 1755a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 1756a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 1757a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1758a45c6cb8SMadhusudhan Chikkature } 1759a45c6cb8SMadhusudhan Chikkature 1760a45c6cb8SMadhusudhan Chikkature if (pdata->nr_slots == 0) { 1761a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "No Slots\n"); 1762a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1763a45c6cb8SMadhusudhan Chikkature } 1764a45c6cb8SMadhusudhan Chikkature 1765a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1766a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 1767a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 1768a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1769a45c6cb8SMadhusudhan Chikkature 1770984b203aSChris Ball res = request_mem_region(res->start, resource_size(res), pdev->name); 1771a45c6cb8SMadhusudhan Chikkature if (res == NULL) 1772a45c6cb8SMadhusudhan Chikkature return -EBUSY; 1773a45c6cb8SMadhusudhan Chikkature 1774db0fefc5SAdrian Hunter ret = omap_hsmmc_gpio_init(pdata); 1775db0fefc5SAdrian Hunter if (ret) 1776db0fefc5SAdrian Hunter goto err; 1777db0fefc5SAdrian Hunter 177870a3341aSDenis Karpov mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 1779a45c6cb8SMadhusudhan Chikkature if (!mmc) { 1780a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 1781db0fefc5SAdrian Hunter goto err_alloc; 1782a45c6cb8SMadhusudhan Chikkature } 1783a45c6cb8SMadhusudhan Chikkature 1784a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 1785a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 1786a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 1787a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 1788a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 1789a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1790a45c6cb8SMadhusudhan Chikkature host->irq = irq; 1791a45c6cb8SMadhusudhan Chikkature host->slot_id = 0; 1792fc307df8SBalaji T K host->mapbase = res->start + pdata->reg_offset; 1793a45c6cb8SMadhusudhan Chikkature host->base = ioremap(host->mapbase, SZ_4K); 17946da20c89SAdrian Hunter host->power_mode = MMC_POWER_OFF; 17959782aff8SPer Forlin host->next_data.cookie = 1; 1796a45c6cb8SMadhusudhan Chikkature 1797a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 1798a45c6cb8SMadhusudhan Chikkature 179970a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ops; 1800dd498effSDenis Karpov 1801e0eb2424SAdrian Hunter /* 1802e0eb2424SAdrian Hunter * If regulator_disable can only put vcc_aux to sleep then there is 1803e0eb2424SAdrian Hunter * no off state. 1804e0eb2424SAdrian Hunter */ 1805e0eb2424SAdrian Hunter if (mmc_slot(host).vcc_aux_disable_is_sleep) 1806e0eb2424SAdrian Hunter mmc_slot(host).no_off = 1; 1807e0eb2424SAdrian Hunter 18086b206efeSAndy Shevchenko mmc->f_min = OMAP_MMC_MIN_CLOCK; 1809d418ed87SDaniel Mack 1810d418ed87SDaniel Mack if (pdata->max_freq > 0) 1811d418ed87SDaniel Mack mmc->f_max = pdata->max_freq; 1812d418ed87SDaniel Mack else 18136b206efeSAndy Shevchenko mmc->f_max = OMAP_MMC_MAX_CLOCK; 1814a45c6cb8SMadhusudhan Chikkature 18154dffd7a2SAdrian Hunter spin_lock_init(&host->irq_lock); 1816a45c6cb8SMadhusudhan Chikkature 18176f7607ccSRussell King host->fclk = clk_get(&pdev->dev, "fck"); 1818a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 1819a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 1820a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 1821a45c6cb8SMadhusudhan Chikkature goto err1; 1822a45c6cb8SMadhusudhan Chikkature } 1823a45c6cb8SMadhusudhan Chikkature 18249b68256cSPaul Walmsley if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 18259b68256cSPaul Walmsley dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 18269b68256cSPaul Walmsley mmc->caps2 |= MMC_CAP2_NO_MULTI_READ; 18279b68256cSPaul Walmsley } 1828dd498effSDenis Karpov 1829fa4aa2d4SBalaji T K pm_runtime_enable(host->dev); 1830fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1831fa4aa2d4SBalaji T K pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 1832fa4aa2d4SBalaji T K pm_runtime_use_autosuspend(host->dev); 1833a45c6cb8SMadhusudhan Chikkature 183492a3aebfSBalaji T K omap_hsmmc_context_save(host); 183592a3aebfSBalaji T K 1836a45c6cb8SMadhusudhan Chikkature host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); 1837a45c6cb8SMadhusudhan Chikkature /* 1838a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 1839a45c6cb8SMadhusudhan Chikkature */ 1840cd03d9a8SRajendra Nayak if (IS_ERR(host->dbclk)) { 1841cd03d9a8SRajendra Nayak dev_warn(mmc_dev(host->mmc), "Failed to get debounce clk\n"); 1842cd03d9a8SRajendra Nayak host->dbclk = NULL; 184394c18149SRajendra Nayak } else if (clk_prepare_enable(host->dbclk) != 0) { 1844cd03d9a8SRajendra Nayak dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 1845cd03d9a8SRajendra Nayak clk_put(host->dbclk); 1846cd03d9a8SRajendra Nayak host->dbclk = NULL; 18472bec0893SAdrian Hunter } 1848a45c6cb8SMadhusudhan Chikkature 18490ccd76d4SJuha Yrjola /* Since we do only SG emulation, we can have as many segs 18500ccd76d4SJuha Yrjola * as we want. */ 1851a36274e0SMartin K. Petersen mmc->max_segs = 1024; 18520ccd76d4SJuha Yrjola 1853a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 1854a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 1855a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1856a45c6cb8SMadhusudhan Chikkature mmc->max_seg_size = mmc->max_req_size; 1857a45c6cb8SMadhusudhan Chikkature 185813189e78SJarkko Lavinen mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 185993caf8e6SAdrian Hunter MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 1860a45c6cb8SMadhusudhan Chikkature 18613a63833eSSukumar Ghorai mmc->caps |= mmc_slot(host).caps; 18623a63833eSSukumar Ghorai if (mmc->caps & MMC_CAP_8_BIT_DATA) 1863a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 1864a45c6cb8SMadhusudhan Chikkature 1865191d1f1dSDenis Karpov if (mmc_slot(host).nonremovable) 186623d99bb9SAdrian Hunter mmc->caps |= MMC_CAP_NONREMOVABLE; 186723d99bb9SAdrian Hunter 18686fdc75deSEliad Peller mmc->pm_caps = mmc_slot(host).pm_caps; 18696fdc75deSEliad Peller 187070a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 1871a45c6cb8SMadhusudhan Chikkature 1872b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 1873b7bf773bSBalaji T K if (!res) { 1874b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n"); 18759c17d08cSKevin Hilman ret = -ENXIO; 1876f3e2f1ddSGrazvydas Ignotas goto err_irq; 1877a45c6cb8SMadhusudhan Chikkature } 187826b88520SRussell King tx_req = res->start; 1879b7bf773bSBalaji T K 1880b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 1881b7bf773bSBalaji T K if (!res) { 1882b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n"); 18839c17d08cSKevin Hilman ret = -ENXIO; 1884b7bf773bSBalaji T K goto err_irq; 1885b7bf773bSBalaji T K } 188626b88520SRussell King rx_req = res->start; 1887c5c98927SRussell King 1888c5c98927SRussell King dma_cap_zero(mask); 1889c5c98927SRussell King dma_cap_set(DMA_SLAVE, mask); 189026b88520SRussell King 189126b88520SRussell King host->rx_chan = dma_request_channel(mask, omap_dma_filter_fn, &rx_req); 1892c5c98927SRussell King if (!host->rx_chan) { 189326b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req); 189404e8c7bcSKevin Hilman ret = -ENXIO; 189526b88520SRussell King goto err_irq; 1896c5c98927SRussell King } 189726b88520SRussell King 189826b88520SRussell King host->tx_chan = dma_request_channel(mask, omap_dma_filter_fn, &tx_req); 1899c5c98927SRussell King if (!host->tx_chan) { 190026b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req); 190104e8c7bcSKevin Hilman ret = -ENXIO; 190226b88520SRussell King goto err_irq; 1903c5c98927SRussell King } 1904a45c6cb8SMadhusudhan Chikkature 1905a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 1906d9618e9fSYong Zhang ret = request_irq(host->irq, omap_hsmmc_irq, 0, 1907a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 1908a45c6cb8SMadhusudhan Chikkature if (ret) { 1909a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 1910a45c6cb8SMadhusudhan Chikkature goto err_irq; 1911a45c6cb8SMadhusudhan Chikkature } 1912a45c6cb8SMadhusudhan Chikkature 1913a45c6cb8SMadhusudhan Chikkature if (pdata->init != NULL) { 1914a45c6cb8SMadhusudhan Chikkature if (pdata->init(&pdev->dev) != 0) { 191570a3341aSDenis Karpov dev_dbg(mmc_dev(host->mmc), 191670a3341aSDenis Karpov "Unable to configure MMC IRQs\n"); 1917a45c6cb8SMadhusudhan Chikkature goto err_irq_cd_init; 1918a45c6cb8SMadhusudhan Chikkature } 1919a45c6cb8SMadhusudhan Chikkature } 1920db0fefc5SAdrian Hunter 1921b702b106SAdrian Hunter if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) { 1922db0fefc5SAdrian Hunter ret = omap_hsmmc_reg_get(host); 1923db0fefc5SAdrian Hunter if (ret) 1924db0fefc5SAdrian Hunter goto err_reg; 1925db0fefc5SAdrian Hunter host->use_reg = 1; 1926db0fefc5SAdrian Hunter } 1927db0fefc5SAdrian Hunter 1928b583f26dSDavid Brownell mmc->ocr_avail = mmc_slot(host).ocr_mask; 1929a45c6cb8SMadhusudhan Chikkature 1930a45c6cb8SMadhusudhan Chikkature /* Request IRQ for card detect */ 1931e1a55f5eSAdrian Hunter if ((mmc_slot(host).card_detect_irq)) { 19327efab4f3SNeilBrown ret = request_threaded_irq(mmc_slot(host).card_detect_irq, 19337efab4f3SNeilBrown NULL, 19347efab4f3SNeilBrown omap_hsmmc_detect, 1935db35f83eSMing Lei IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1936a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 1937a45c6cb8SMadhusudhan Chikkature if (ret) { 1938a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1939a45c6cb8SMadhusudhan Chikkature "Unable to grab MMC CD IRQ\n"); 1940a45c6cb8SMadhusudhan Chikkature goto err_irq_cd; 1941a45c6cb8SMadhusudhan Chikkature } 194272f2e2c7Skishore kadiyala pdata->suspend = omap_hsmmc_suspend_cdirq; 194372f2e2c7Skishore kadiyala pdata->resume = omap_hsmmc_resume_cdirq; 1944a45c6cb8SMadhusudhan Chikkature } 1945a45c6cb8SMadhusudhan Chikkature 1946b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 1947a45c6cb8SMadhusudhan Chikkature 1948b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 1949b62f6228SAdrian Hunter 1950a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 1951a45c6cb8SMadhusudhan Chikkature 1952191d1f1dSDenis Karpov if (mmc_slot(host).name != NULL) { 1953a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 1954a45c6cb8SMadhusudhan Chikkature if (ret < 0) 1955a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 1956a45c6cb8SMadhusudhan Chikkature } 1957191d1f1dSDenis Karpov if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { 1958a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, 1959a45c6cb8SMadhusudhan Chikkature &dev_attr_cover_switch); 1960a45c6cb8SMadhusudhan Chikkature if (ret < 0) 1961db0fefc5SAdrian Hunter goto err_slot_name; 1962a45c6cb8SMadhusudhan Chikkature } 1963a45c6cb8SMadhusudhan Chikkature 196470a3341aSDenis Karpov omap_hsmmc_debugfs(mmc); 1965fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1966fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1967d900f712SDenis Karpov 1968a45c6cb8SMadhusudhan Chikkature return 0; 1969a45c6cb8SMadhusudhan Chikkature 1970a45c6cb8SMadhusudhan Chikkature err_slot_name: 1971a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 1972a45c6cb8SMadhusudhan Chikkature free_irq(mmc_slot(host).card_detect_irq, host); 1973db0fefc5SAdrian Hunter err_irq_cd: 1974db0fefc5SAdrian Hunter if (host->use_reg) 1975db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 1976db0fefc5SAdrian Hunter err_reg: 1977db0fefc5SAdrian Hunter if (host->pdata->cleanup) 1978db0fefc5SAdrian Hunter host->pdata->cleanup(&pdev->dev); 1979a45c6cb8SMadhusudhan Chikkature err_irq_cd_init: 1980a45c6cb8SMadhusudhan Chikkature free_irq(host->irq, host); 1981a45c6cb8SMadhusudhan Chikkature err_irq: 1982c5c98927SRussell King if (host->tx_chan) 1983c5c98927SRussell King dma_release_channel(host->tx_chan); 1984c5c98927SRussell King if (host->rx_chan) 1985c5c98927SRussell King dma_release_channel(host->rx_chan); 1986d59d77edSBalaji T K pm_runtime_put_sync(host->dev); 198737f6190dSTony Lindgren pm_runtime_disable(host->dev); 1988a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 1989cd03d9a8SRajendra Nayak if (host->dbclk) { 199094c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 1991a45c6cb8SMadhusudhan Chikkature clk_put(host->dbclk); 1992a45c6cb8SMadhusudhan Chikkature } 1993a45c6cb8SMadhusudhan Chikkature err1: 1994a45c6cb8SMadhusudhan Chikkature iounmap(host->base); 1995db0fefc5SAdrian Hunter platform_set_drvdata(pdev, NULL); 1996a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 1997db0fefc5SAdrian Hunter err_alloc: 1998db0fefc5SAdrian Hunter omap_hsmmc_gpio_free(pdata); 1999db0fefc5SAdrian Hunter err: 200048b332f9SRussell King res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 200148b332f9SRussell King if (res) 2002984b203aSChris Ball release_mem_region(res->start, resource_size(res)); 2003a45c6cb8SMadhusudhan Chikkature return ret; 2004a45c6cb8SMadhusudhan Chikkature } 2005a45c6cb8SMadhusudhan Chikkature 2006efa25fd3SFelipe Balbi static int __devexit omap_hsmmc_remove(struct platform_device *pdev) 2007a45c6cb8SMadhusudhan Chikkature { 200870a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2009a45c6cb8SMadhusudhan Chikkature struct resource *res; 2010a45c6cb8SMadhusudhan Chikkature 2011fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2012a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 2013db0fefc5SAdrian Hunter if (host->use_reg) 2014db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2015a45c6cb8SMadhusudhan Chikkature if (host->pdata->cleanup) 2016a45c6cb8SMadhusudhan Chikkature host->pdata->cleanup(&pdev->dev); 2017a45c6cb8SMadhusudhan Chikkature free_irq(host->irq, host); 2018a45c6cb8SMadhusudhan Chikkature if (mmc_slot(host).card_detect_irq) 2019a45c6cb8SMadhusudhan Chikkature free_irq(mmc_slot(host).card_detect_irq, host); 2020a45c6cb8SMadhusudhan Chikkature 2021c5c98927SRussell King if (host->tx_chan) 2022c5c98927SRussell King dma_release_channel(host->tx_chan); 2023c5c98927SRussell King if (host->rx_chan) 2024c5c98927SRussell King dma_release_channel(host->rx_chan); 2025c5c98927SRussell King 2026fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2027fa4aa2d4SBalaji T K pm_runtime_disable(host->dev); 2028a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 2029cd03d9a8SRajendra Nayak if (host->dbclk) { 203094c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2031a45c6cb8SMadhusudhan Chikkature clk_put(host->dbclk); 2032a45c6cb8SMadhusudhan Chikkature } 2033a45c6cb8SMadhusudhan Chikkature 2034a45c6cb8SMadhusudhan Chikkature mmc_free_host(host->mmc); 2035a45c6cb8SMadhusudhan Chikkature iounmap(host->base); 2036db0fefc5SAdrian Hunter omap_hsmmc_gpio_free(pdev->dev.platform_data); 2037a45c6cb8SMadhusudhan Chikkature 2038a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2039a45c6cb8SMadhusudhan Chikkature if (res) 2040984b203aSChris Ball release_mem_region(res->start, resource_size(res)); 2041a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, NULL); 2042a45c6cb8SMadhusudhan Chikkature 2043a45c6cb8SMadhusudhan Chikkature return 0; 2044a45c6cb8SMadhusudhan Chikkature } 2045a45c6cb8SMadhusudhan Chikkature 2046a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_PM 2047a791daa1SKevin Hilman static int omap_hsmmc_suspend(struct device *dev) 2048a45c6cb8SMadhusudhan Chikkature { 2049a45c6cb8SMadhusudhan Chikkature int ret = 0; 2050927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2051927ce944SFelipe Balbi 2052927ce944SFelipe Balbi if (!host) 2053927ce944SFelipe Balbi return 0; 2054a45c6cb8SMadhusudhan Chikkature 2055a45c6cb8SMadhusudhan Chikkature if (host && host->suspended) 2056a45c6cb8SMadhusudhan Chikkature return 0; 2057a45c6cb8SMadhusudhan Chikkature 2058fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2059a45c6cb8SMadhusudhan Chikkature host->suspended = 1; 2060a45c6cb8SMadhusudhan Chikkature if (host->pdata->suspend) { 2061927ce944SFelipe Balbi ret = host->pdata->suspend(dev, host->slot_id); 2062a6b2240dSAdrian Hunter if (ret) { 2063927ce944SFelipe Balbi dev_dbg(dev, "Unable to handle MMC board" 2064a45c6cb8SMadhusudhan Chikkature " level suspend\n"); 2065a6b2240dSAdrian Hunter host->suspended = 0; 2066a6b2240dSAdrian Hunter return ret; 2067a45c6cb8SMadhusudhan Chikkature } 2068a6b2240dSAdrian Hunter } 20691a13f8faSMatt Fleming ret = mmc_suspend_host(host->mmc); 2070fa4aa2d4SBalaji T K 207131f9d463SEliad Peller if (ret) { 2072a6b2240dSAdrian Hunter host->suspended = 0; 2073a6b2240dSAdrian Hunter if (host->pdata->resume) { 2074927ce944SFelipe Balbi ret = host->pdata->resume(dev, host->slot_id); 2075a6b2240dSAdrian Hunter if (ret) 2076927ce944SFelipe Balbi dev_dbg(dev, "Unmask interrupt failed\n"); 2077a6b2240dSAdrian Hunter } 207831f9d463SEliad Peller goto err; 2079a6b2240dSAdrian Hunter } 208031f9d463SEliad Peller 208131f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 208231f9d463SEliad Peller omap_hsmmc_disable_irq(host); 208331f9d463SEliad Peller OMAP_HSMMC_WRITE(host->base, HCTL, 208431f9d463SEliad Peller OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 208531f9d463SEliad Peller } 2086927ce944SFelipe Balbi 2087cd03d9a8SRajendra Nayak if (host->dbclk) 208894c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 208931f9d463SEliad Peller err: 2090fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2091a45c6cb8SMadhusudhan Chikkature return ret; 2092a45c6cb8SMadhusudhan Chikkature } 2093a45c6cb8SMadhusudhan Chikkature 2094a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 2095a791daa1SKevin Hilman static int omap_hsmmc_resume(struct device *dev) 2096a45c6cb8SMadhusudhan Chikkature { 2097a45c6cb8SMadhusudhan Chikkature int ret = 0; 2098927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2099927ce944SFelipe Balbi 2100927ce944SFelipe Balbi if (!host) 2101927ce944SFelipe Balbi return 0; 2102a45c6cb8SMadhusudhan Chikkature 2103a45c6cb8SMadhusudhan Chikkature if (host && !host->suspended) 2104a45c6cb8SMadhusudhan Chikkature return 0; 2105a45c6cb8SMadhusudhan Chikkature 2106fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 210711dd62a7SDenis Karpov 2108cd03d9a8SRajendra Nayak if (host->dbclk) 210994c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 21102bec0893SAdrian Hunter 211131f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 211270a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 21131b331e69SKim Kyuwon 2114a45c6cb8SMadhusudhan Chikkature if (host->pdata->resume) { 2115927ce944SFelipe Balbi ret = host->pdata->resume(dev, host->slot_id); 2116a45c6cb8SMadhusudhan Chikkature if (ret) 2117927ce944SFelipe Balbi dev_dbg(dev, "Unmask interrupt failed\n"); 2118a45c6cb8SMadhusudhan Chikkature } 2119a45c6cb8SMadhusudhan Chikkature 2120b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2121b62f6228SAdrian Hunter 2122a45c6cb8SMadhusudhan Chikkature /* Notify the core to resume the host */ 2123a45c6cb8SMadhusudhan Chikkature ret = mmc_resume_host(host->mmc); 2124a45c6cb8SMadhusudhan Chikkature if (ret == 0) 2125a45c6cb8SMadhusudhan Chikkature host->suspended = 0; 2126fa4aa2d4SBalaji T K 2127fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2128fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2129a45c6cb8SMadhusudhan Chikkature 2130a45c6cb8SMadhusudhan Chikkature return ret; 2131a45c6cb8SMadhusudhan Chikkature 2132a45c6cb8SMadhusudhan Chikkature } 2133a45c6cb8SMadhusudhan Chikkature 2134a45c6cb8SMadhusudhan Chikkature #else 213570a3341aSDenis Karpov #define omap_hsmmc_suspend NULL 213670a3341aSDenis Karpov #define omap_hsmmc_resume NULL 2137a45c6cb8SMadhusudhan Chikkature #endif 2138a45c6cb8SMadhusudhan Chikkature 2139fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_suspend(struct device *dev) 2140fa4aa2d4SBalaji T K { 2141fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 2142fa4aa2d4SBalaji T K 2143fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2144fa4aa2d4SBalaji T K omap_hsmmc_context_save(host); 2145927ce944SFelipe Balbi dev_dbg(dev, "disabled\n"); 2146fa4aa2d4SBalaji T K 2147fa4aa2d4SBalaji T K return 0; 2148fa4aa2d4SBalaji T K } 2149fa4aa2d4SBalaji T K 2150fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_resume(struct device *dev) 2151fa4aa2d4SBalaji T K { 2152fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 2153fa4aa2d4SBalaji T K 2154fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2155fa4aa2d4SBalaji T K omap_hsmmc_context_restore(host); 2156927ce944SFelipe Balbi dev_dbg(dev, "enabled\n"); 2157fa4aa2d4SBalaji T K 2158fa4aa2d4SBalaji T K return 0; 2159fa4aa2d4SBalaji T K } 2160fa4aa2d4SBalaji T K 2161a791daa1SKevin Hilman static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 216270a3341aSDenis Karpov .suspend = omap_hsmmc_suspend, 216370a3341aSDenis Karpov .resume = omap_hsmmc_resume, 2164fa4aa2d4SBalaji T K .runtime_suspend = omap_hsmmc_runtime_suspend, 2165fa4aa2d4SBalaji T K .runtime_resume = omap_hsmmc_runtime_resume, 2166a791daa1SKevin Hilman }; 2167a791daa1SKevin Hilman 2168a791daa1SKevin Hilman static struct platform_driver omap_hsmmc_driver = { 2169efa25fd3SFelipe Balbi .probe = omap_hsmmc_probe, 2170efa25fd3SFelipe Balbi .remove = __devexit_p(omap_hsmmc_remove), 2171a45c6cb8SMadhusudhan Chikkature .driver = { 2172a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 2173a45c6cb8SMadhusudhan Chikkature .owner = THIS_MODULE, 2174a791daa1SKevin Hilman .pm = &omap_hsmmc_dev_pm_ops, 217546856a68SRajendra Nayak .of_match_table = of_match_ptr(omap_mmc_of_match), 2176a45c6cb8SMadhusudhan Chikkature }, 2177a45c6cb8SMadhusudhan Chikkature }; 2178a45c6cb8SMadhusudhan Chikkature 2179b796450bSFelipe Balbi module_platform_driver(omap_hsmmc_driver); 2180a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2181a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 2182a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 2183a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 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