xref: /openbmc/linux/drivers/mmc/host/omap_hsmmc.c (revision 13ab2a66)
1a45c6cb8SMadhusudhan Chikkature /*
2a45c6cb8SMadhusudhan Chikkature  * drivers/mmc/host/omap_hsmmc.c
3a45c6cb8SMadhusudhan Chikkature  *
4a45c6cb8SMadhusudhan Chikkature  * Driver for OMAP2430/3430 MMC controller.
5a45c6cb8SMadhusudhan Chikkature  *
6a45c6cb8SMadhusudhan Chikkature  * Copyright (C) 2007 Texas Instruments.
7a45c6cb8SMadhusudhan Chikkature  *
8a45c6cb8SMadhusudhan Chikkature  * Authors:
9a45c6cb8SMadhusudhan Chikkature  *	Syed Mohammed Khasim	<x0khasim@ti.com>
10a45c6cb8SMadhusudhan Chikkature  *	Madhusudhan		<madhu.cr@ti.com>
11a45c6cb8SMadhusudhan Chikkature  *	Mohit Jalori		<mjalori@ti.com>
12a45c6cb8SMadhusudhan Chikkature  *
13a45c6cb8SMadhusudhan Chikkature  * This file is licensed under the terms of the GNU General Public License
14a45c6cb8SMadhusudhan Chikkature  * version 2. This program is licensed "as is" without any warranty of any
15a45c6cb8SMadhusudhan Chikkature  * kind, whether express or implied.
16a45c6cb8SMadhusudhan Chikkature  */
17a45c6cb8SMadhusudhan Chikkature 
18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h>
19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h>
20ac330f44SAndy Shevchenko #include <linux/kernel.h>
21d900f712SDenis Karpov #include <linux/debugfs.h>
22c5c98927SRussell King #include <linux/dmaengine.h>
23d900f712SDenis Karpov #include <linux/seq_file.h>
24031cd037SFelipe Balbi #include <linux/sizes.h>
25a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h>
26a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h>
27a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h>
28a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h>
29a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h>
30a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h>
3146856a68SRajendra Nayak #include <linux/of.h>
322cd3a2a5SAndreas Fenkart #include <linux/of_irq.h>
3346856a68SRajendra Nayak #include <linux/of_gpio.h>
3446856a68SRajendra Nayak #include <linux/of_device.h>
35a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h>
3613189e78SJarkko Lavinen #include <linux/mmc/core.h>
3793caf8e6SAdrian Hunter #include <linux/mmc/mmc.h>
3841afa314SNeilBrown #include <linux/mmc/slot-gpio.h>
39a45c6cb8SMadhusudhan Chikkature #include <linux/io.h>
402cd3a2a5SAndreas Fenkart #include <linux/irq.h>
41db0fefc5SAdrian Hunter #include <linux/gpio.h>
42db0fefc5SAdrian Hunter #include <linux/regulator/consumer.h>
4346b76035SDaniel Mack #include <linux/pinctrl/consumer.h>
44fa4aa2d4SBalaji T K #include <linux/pm_runtime.h>
455b83b223STony Lindgren #include <linux/pm_wakeirq.h>
4655143438SAndreas Fenkart #include <linux/platform_data/hsmmc-omap.h>
47a45c6cb8SMadhusudhan Chikkature 
48a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */
4911dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS	0x0014
50a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON		0x002C
51a2e77152SBalaji T K #define OMAP_HSMMC_SDMASA	0x0100
52a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK		0x0104
53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG		0x0108
54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD		0x010C
55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10	0x0110
56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32	0x0114
57a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54	0x0118
58a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76	0x011C
59a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA		0x0120
60bb0635f0SAndreas Fenkart #define OMAP_HSMMC_PSTATE	0x0124
61a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL		0x0128
62a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL	0x012C
63a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT		0x0130
64a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE		0x0134
65a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE		0x0138
66a2e77152SBalaji T K #define OMAP_HSMMC_AC12		0x013C
67a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA		0x0140
68a45c6cb8SMadhusudhan Chikkature 
69a45c6cb8SMadhusudhan Chikkature #define VS18			(1 << 26)
70a45c6cb8SMadhusudhan Chikkature #define VS30			(1 << 25)
71cd587096SHebbar, Gururaja #define HSS			(1 << 21)
72a45c6cb8SMadhusudhan Chikkature #define SDVS18			(0x5 << 9)
73a45c6cb8SMadhusudhan Chikkature #define SDVS30			(0x6 << 9)
74eb250826SDavid Brownell #define SDVS33			(0x7 << 9)
751b331e69SKim Kyuwon #define SDVS_MASK		0x00000E00
76a45c6cb8SMadhusudhan Chikkature #define SDVSCLR			0xFFFFF1FF
77a45c6cb8SMadhusudhan Chikkature #define SDVSDET			0x00000400
78a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE		0x1
79a45c6cb8SMadhusudhan Chikkature #define SDBP			(1 << 8)
80a45c6cb8SMadhusudhan Chikkature #define DTO			0xe
81a45c6cb8SMadhusudhan Chikkature #define ICE			0x1
82a45c6cb8SMadhusudhan Chikkature #define ICS			0x2
83a45c6cb8SMadhusudhan Chikkature #define CEN			(1 << 2)
84ed164182SBalaji T K #define CLKD_MAX		0x3FF		/* max clock divisor: 1023 */
85a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK		0x0000FFC0
86a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT		6
87a45c6cb8SMadhusudhan Chikkature #define DTO_MASK		0x000F0000
88a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT		16
89a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM		(1 << 1)
90a2e77152SBalaji T K #define ACEN_ACMD23		(2 << 2)
91a45c6cb8SMadhusudhan Chikkature #define DP_SELECT		(1 << 21)
92a45c6cb8SMadhusudhan Chikkature #define DDIR			(1 << 4)
93a7e96879SVenkatraman S #define DMAE			0x1
94a45c6cb8SMadhusudhan Chikkature #define MSBS			(1 << 5)
95a45c6cb8SMadhusudhan Chikkature #define BCE			(1 << 1)
96a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT		(1 << 1)
97cd587096SHebbar, Gururaja #define HSPE			(1 << 2)
985a52b08bSBalaji T K #define IWE			(1 << 24)
9903b5d924SBalaji T K #define DDR			(1 << 19)
1005a52b08bSBalaji T K #define CLKEXTFREE		(1 << 16)
1015a52b08bSBalaji T K #define CTPL			(1 << 11)
10273153010SJarkko Lavinen #define DW8			(1 << 5)
103a45c6cb8SMadhusudhan Chikkature #define OD			0x1
104a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR		0xFFFFFFFF
105a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD		0x00000000
106a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT	7
107a45c6cb8SMadhusudhan Chikkature #define SRC			(1 << 25)
108a45c6cb8SMadhusudhan Chikkature #define SRD			(1 << 26)
10911dd62a7SDenis Karpov #define SOFTRESET		(1 << 1)
110a45c6cb8SMadhusudhan Chikkature 
111f945901fSAndreas Fenkart /* PSTATE */
112f945901fSAndreas Fenkart #define DLEV_DAT(x)		(1 << (20 + (x)))
113f945901fSAndreas Fenkart 
114a7e96879SVenkatraman S /* Interrupt masks for IE and ISE register */
115a7e96879SVenkatraman S #define CC_EN			(1 << 0)
116a7e96879SVenkatraman S #define TC_EN			(1 << 1)
117a7e96879SVenkatraman S #define BWR_EN			(1 << 4)
118a7e96879SVenkatraman S #define BRR_EN			(1 << 5)
1192cd3a2a5SAndreas Fenkart #define CIRQ_EN			(1 << 8)
120a7e96879SVenkatraman S #define ERR_EN			(1 << 15)
121a7e96879SVenkatraman S #define CTO_EN			(1 << 16)
122a7e96879SVenkatraman S #define CCRC_EN			(1 << 17)
123a7e96879SVenkatraman S #define CEB_EN			(1 << 18)
124a7e96879SVenkatraman S #define CIE_EN			(1 << 19)
125a7e96879SVenkatraman S #define DTO_EN			(1 << 20)
126a7e96879SVenkatraman S #define DCRC_EN			(1 << 21)
127a7e96879SVenkatraman S #define DEB_EN			(1 << 22)
128a2e77152SBalaji T K #define ACE_EN			(1 << 24)
129a7e96879SVenkatraman S #define CERR_EN			(1 << 28)
130a7e96879SVenkatraman S #define BADA_EN			(1 << 29)
131a7e96879SVenkatraman S 
132a2e77152SBalaji T K #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
133a7e96879SVenkatraman S 		DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
134a7e96879SVenkatraman S 		BRR_EN | BWR_EN | TC_EN | CC_EN)
135a7e96879SVenkatraman S 
136a2e77152SBalaji T K #define CNI	(1 << 7)
137a2e77152SBalaji T K #define ACIE	(1 << 4)
138a2e77152SBalaji T K #define ACEB	(1 << 3)
139a2e77152SBalaji T K #define ACCE	(1 << 2)
140a2e77152SBalaji T K #define ACTO	(1 << 1)
141a2e77152SBalaji T K #define ACNE	(1 << 0)
142a2e77152SBalaji T K 
143fa4aa2d4SBalaji T K #define MMC_AUTOSUSPEND_DELAY	100
1441e881786SJianpeng Ma #define MMC_TIMEOUT_MS		20		/* 20 mSec */
1451e881786SJianpeng Ma #define MMC_TIMEOUT_US		20000		/* 20000 micro Sec */
1466b206efeSAndy Shevchenko #define OMAP_MMC_MIN_CLOCK	400000
1476b206efeSAndy Shevchenko #define OMAP_MMC_MAX_CLOCK	52000000
1480005ae73SKishore Kadiyala #define DRIVER_NAME		"omap_hsmmc"
149a45c6cb8SMadhusudhan Chikkature 
150e99448ffSBalaji T K #define VDD_1V8			1800000		/* 180000 uV */
151e99448ffSBalaji T K #define VDD_3V0			3000000		/* 300000 uV */
152e99448ffSBalaji T K #define VDD_165_195		(ffs(MMC_VDD_165_195) - 1)
153e99448ffSBalaji T K 
154a45c6cb8SMadhusudhan Chikkature /*
155a45c6cb8SMadhusudhan Chikkature  * One controller can have multiple slots, like on some omap boards using
156a45c6cb8SMadhusudhan Chikkature  * omap.c controller driver. Luckily this is not currently done on any known
157a45c6cb8SMadhusudhan Chikkature  * omap_hsmmc.c device.
158a45c6cb8SMadhusudhan Chikkature  */
159326119c9SAndreas Fenkart #define mmc_pdata(host)		host->pdata
160a45c6cb8SMadhusudhan Chikkature 
161a45c6cb8SMadhusudhan Chikkature /*
162a45c6cb8SMadhusudhan Chikkature  * MMC Host controller read/write API's
163a45c6cb8SMadhusudhan Chikkature  */
164a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg)	\
165a45c6cb8SMadhusudhan Chikkature 	__raw_readl((base) + OMAP_HSMMC_##reg)
166a45c6cb8SMadhusudhan Chikkature 
167a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \
168a45c6cb8SMadhusudhan Chikkature 	__raw_writel((val), (base) + OMAP_HSMMC_##reg)
169a45c6cb8SMadhusudhan Chikkature 
1709782aff8SPer Forlin struct omap_hsmmc_next {
1719782aff8SPer Forlin 	unsigned int	dma_len;
1729782aff8SPer Forlin 	s32		cookie;
1739782aff8SPer Forlin };
1749782aff8SPer Forlin 
17570a3341aSDenis Karpov struct omap_hsmmc_host {
176a45c6cb8SMadhusudhan Chikkature 	struct	device		*dev;
177a45c6cb8SMadhusudhan Chikkature 	struct	mmc_host	*mmc;
178a45c6cb8SMadhusudhan Chikkature 	struct	mmc_request	*mrq;
179a45c6cb8SMadhusudhan Chikkature 	struct	mmc_command	*cmd;
180a45c6cb8SMadhusudhan Chikkature 	struct	mmc_data	*data;
181a45c6cb8SMadhusudhan Chikkature 	struct	clk		*fclk;
182a45c6cb8SMadhusudhan Chikkature 	struct	clk		*dbclk;
183e99448ffSBalaji T K 	struct	regulator	*pbias;
184bb2726b5STony Lindgren 	bool			pbias_enabled;
185a45c6cb8SMadhusudhan Chikkature 	void	__iomem		*base;
1863f77f702SKishon Vijay Abraham I 	int			vqmmc_enabled;
187a45c6cb8SMadhusudhan Chikkature 	resource_size_t		mapbase;
1884dffd7a2SAdrian Hunter 	spinlock_t		irq_lock; /* Prevent races with irq handler */
189a45c6cb8SMadhusudhan Chikkature 	unsigned int		dma_len;
1900ccd76d4SJuha Yrjola 	unsigned int		dma_sg_idx;
191a45c6cb8SMadhusudhan Chikkature 	unsigned char		bus_mode;
192a3621465SAdrian Hunter 	unsigned char		power_mode;
193a45c6cb8SMadhusudhan Chikkature 	int			suspended;
1940a82e06eSTony Lindgren 	u32			con;
1950a82e06eSTony Lindgren 	u32			hctl;
1960a82e06eSTony Lindgren 	u32			sysctl;
1970a82e06eSTony Lindgren 	u32			capa;
198a45c6cb8SMadhusudhan Chikkature 	int			irq;
1992cd3a2a5SAndreas Fenkart 	int			wake_irq;
200a45c6cb8SMadhusudhan Chikkature 	int			use_dma, dma_ch;
201c5c98927SRussell King 	struct dma_chan		*tx_chan;
202c5c98927SRussell King 	struct dma_chan		*rx_chan;
2034a694dc9SAdrian Hunter 	int			response_busy;
20411dd62a7SDenis Karpov 	int			context_loss;
205b62f6228SAdrian Hunter 	int			protect_card;
206b62f6228SAdrian Hunter 	int			reqs_blocked;
207b417577dSAdrian Hunter 	int			req_in_progress;
2086e3076c2SBalaji T K 	unsigned long		clk_rate;
209a2e77152SBalaji T K 	unsigned int		flags;
2102cd3a2a5SAndreas Fenkart #define AUTO_CMD23		(1 << 0)        /* Auto CMD23 support */
2112cd3a2a5SAndreas Fenkart #define HSMMC_SDIO_IRQ_ENABLED	(1 << 1)        /* SDIO irq enabled */
2129782aff8SPer Forlin 	struct omap_hsmmc_next	next_data;
21355143438SAndreas Fenkart 	struct	omap_hsmmc_platform_data	*pdata;
214b5cd43f0SAndreas Fenkart 
215b5cd43f0SAndreas Fenkart 	/* return MMC cover switch state, can be NULL if not supported.
216b5cd43f0SAndreas Fenkart 	 *
217b5cd43f0SAndreas Fenkart 	 * possible return values:
218b5cd43f0SAndreas Fenkart 	 *   0 - closed
219b5cd43f0SAndreas Fenkart 	 *   1 - open
220b5cd43f0SAndreas Fenkart 	 */
22180412ca8SAndreas Fenkart 	int (*get_cover_state)(struct device *dev);
222b5cd43f0SAndreas Fenkart 
22380412ca8SAndreas Fenkart 	int (*card_detect)(struct device *dev);
224a45c6cb8SMadhusudhan Chikkature };
225a45c6cb8SMadhusudhan Chikkature 
22659445b10SNishanth Menon struct omap_mmc_of_data {
22759445b10SNishanth Menon 	u32 reg_offset;
22859445b10SNishanth Menon 	u8 controller_flags;
22959445b10SNishanth Menon };
23059445b10SNishanth Menon 
231bf129e1cSBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
232bf129e1cSBalaji T K 
23380412ca8SAndreas Fenkart static int omap_hsmmc_card_detect(struct device *dev)
234db0fefc5SAdrian Hunter {
2359ea28ecbSBalaji T K 	struct omap_hsmmc_host *host = dev_get_drvdata(dev);
236db0fefc5SAdrian Hunter 
23741afa314SNeilBrown 	return mmc_gpio_get_cd(host->mmc);
238db0fefc5SAdrian Hunter }
239db0fefc5SAdrian Hunter 
24080412ca8SAndreas Fenkart static int omap_hsmmc_get_cover_state(struct device *dev)
241db0fefc5SAdrian Hunter {
2429ea28ecbSBalaji T K 	struct omap_hsmmc_host *host = dev_get_drvdata(dev);
243db0fefc5SAdrian Hunter 
24441afa314SNeilBrown 	return mmc_gpio_get_cd(host->mmc);
245db0fefc5SAdrian Hunter }
246db0fefc5SAdrian Hunter 
2471d17f30bSKishon Vijay Abraham I static int omap_hsmmc_enable_supply(struct mmc_host *mmc)
2482a17f844SKishon Vijay Abraham I {
2492a17f844SKishon Vijay Abraham I 	int ret;
2503f77f702SKishon Vijay Abraham I 	struct omap_hsmmc_host *host = mmc_priv(mmc);
2511d17f30bSKishon Vijay Abraham I 	struct mmc_ios *ios = &mmc->ios;
2522a17f844SKishon Vijay Abraham I 
25386d79da0SKishon Vijay Abraham I 	if (!IS_ERR(mmc->supply.vmmc)) {
2541d17f30bSKishon Vijay Abraham I 		ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
2552a17f844SKishon Vijay Abraham I 		if (ret)
2562a17f844SKishon Vijay Abraham I 			return ret;
2572a17f844SKishon Vijay Abraham I 	}
2582a17f844SKishon Vijay Abraham I 
2592a17f844SKishon Vijay Abraham I 	/* Enable interface voltage rail, if needed */
26086d79da0SKishon Vijay Abraham I 	if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
2612a17f844SKishon Vijay Abraham I 		ret = regulator_enable(mmc->supply.vqmmc);
2622a17f844SKishon Vijay Abraham I 		if (ret) {
2632a17f844SKishon Vijay Abraham I 			dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n");
2642a17f844SKishon Vijay Abraham I 			goto err_vqmmc;
2652a17f844SKishon Vijay Abraham I 		}
2663f77f702SKishon Vijay Abraham I 		host->vqmmc_enabled = 1;
2672a17f844SKishon Vijay Abraham I 	}
2682a17f844SKishon Vijay Abraham I 
2692a17f844SKishon Vijay Abraham I 	return 0;
2702a17f844SKishon Vijay Abraham I 
2712a17f844SKishon Vijay Abraham I err_vqmmc:
27286d79da0SKishon Vijay Abraham I 	if (!IS_ERR(mmc->supply.vmmc))
2732a17f844SKishon Vijay Abraham I 		mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
2742a17f844SKishon Vijay Abraham I 
2752a17f844SKishon Vijay Abraham I 	return ret;
2762a17f844SKishon Vijay Abraham I }
2772a17f844SKishon Vijay Abraham I 
2782a17f844SKishon Vijay Abraham I static int omap_hsmmc_disable_supply(struct mmc_host *mmc)
2792a17f844SKishon Vijay Abraham I {
2802a17f844SKishon Vijay Abraham I 	int ret;
2812a17f844SKishon Vijay Abraham I 	int status;
2823f77f702SKishon Vijay Abraham I 	struct omap_hsmmc_host *host = mmc_priv(mmc);
2832a17f844SKishon Vijay Abraham I 
28486d79da0SKishon Vijay Abraham I 	if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
2852a17f844SKishon Vijay Abraham I 		ret = regulator_disable(mmc->supply.vqmmc);
2862a17f844SKishon Vijay Abraham I 		if (ret) {
2872a17f844SKishon Vijay Abraham I 			dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n");
2882a17f844SKishon Vijay Abraham I 			return ret;
2892a17f844SKishon Vijay Abraham I 		}
2903f77f702SKishon Vijay Abraham I 		host->vqmmc_enabled = 0;
2912a17f844SKishon Vijay Abraham I 	}
2922a17f844SKishon Vijay Abraham I 
29386d79da0SKishon Vijay Abraham I 	if (!IS_ERR(mmc->supply.vmmc)) {
2942a17f844SKishon Vijay Abraham I 		ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
2952a17f844SKishon Vijay Abraham I 		if (ret)
2962a17f844SKishon Vijay Abraham I 			goto err_set_ocr;
2972a17f844SKishon Vijay Abraham I 	}
2982a17f844SKishon Vijay Abraham I 
2992a17f844SKishon Vijay Abraham I 	return 0;
3002a17f844SKishon Vijay Abraham I 
3012a17f844SKishon Vijay Abraham I err_set_ocr:
30286d79da0SKishon Vijay Abraham I 	if (!IS_ERR(mmc->supply.vqmmc)) {
3032a17f844SKishon Vijay Abraham I 		status = regulator_enable(mmc->supply.vqmmc);
3042a17f844SKishon Vijay Abraham I 		if (status)
3052a17f844SKishon Vijay Abraham I 			dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n");
3062a17f844SKishon Vijay Abraham I 	}
3072a17f844SKishon Vijay Abraham I 
3082a17f844SKishon Vijay Abraham I 	return ret;
3092a17f844SKishon Vijay Abraham I }
3102a17f844SKishon Vijay Abraham I 
311ec85c95eSKishon Vijay Abraham I static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on,
312ec85c95eSKishon Vijay Abraham I 				int vdd)
313ec85c95eSKishon Vijay Abraham I {
314ec85c95eSKishon Vijay Abraham I 	int ret;
315ec85c95eSKishon Vijay Abraham I 
31686d79da0SKishon Vijay Abraham I 	if (IS_ERR(host->pbias))
317ec85c95eSKishon Vijay Abraham I 		return 0;
318ec85c95eSKishon Vijay Abraham I 
319ec85c95eSKishon Vijay Abraham I 	if (power_on) {
320ec85c95eSKishon Vijay Abraham I 		if (vdd <= VDD_165_195)
321ec85c95eSKishon Vijay Abraham I 			ret = regulator_set_voltage(host->pbias, VDD_1V8,
322ec85c95eSKishon Vijay Abraham I 						    VDD_1V8);
323ec85c95eSKishon Vijay Abraham I 		else
324ec85c95eSKishon Vijay Abraham I 			ret = regulator_set_voltage(host->pbias, VDD_3V0,
325ec85c95eSKishon Vijay Abraham I 						    VDD_3V0);
326ec85c95eSKishon Vijay Abraham I 		if (ret < 0) {
327ec85c95eSKishon Vijay Abraham I 			dev_err(host->dev, "pbias set voltage fail\n");
328ec85c95eSKishon Vijay Abraham I 			return ret;
329ec85c95eSKishon Vijay Abraham I 		}
330ec85c95eSKishon Vijay Abraham I 
331bb2726b5STony Lindgren 		if (host->pbias_enabled == 0) {
332ec85c95eSKishon Vijay Abraham I 			ret = regulator_enable(host->pbias);
333ec85c95eSKishon Vijay Abraham I 			if (ret) {
334ec85c95eSKishon Vijay Abraham I 				dev_err(host->dev, "pbias reg enable fail\n");
335ec85c95eSKishon Vijay Abraham I 				return ret;
336ec85c95eSKishon Vijay Abraham I 			}
337bb2726b5STony Lindgren 			host->pbias_enabled = 1;
338ec85c95eSKishon Vijay Abraham I 		}
339ec85c95eSKishon Vijay Abraham I 	} else {
340bb2726b5STony Lindgren 		if (host->pbias_enabled == 1) {
341ec85c95eSKishon Vijay Abraham I 			ret = regulator_disable(host->pbias);
342ec85c95eSKishon Vijay Abraham I 			if (ret) {
343ec85c95eSKishon Vijay Abraham I 				dev_err(host->dev, "pbias reg disable fail\n");
344ec85c95eSKishon Vijay Abraham I 				return ret;
345ec85c95eSKishon Vijay Abraham I 			}
346bb2726b5STony Lindgren 			host->pbias_enabled = 0;
347ec85c95eSKishon Vijay Abraham I 		}
348ec85c95eSKishon Vijay Abraham I 	}
349ec85c95eSKishon Vijay Abraham I 
350ec85c95eSKishon Vijay Abraham I 	return 0;
351ec85c95eSKishon Vijay Abraham I }
352ec85c95eSKishon Vijay Abraham I 
3531ca4d359SAndreas Fenkart static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on,
3541ca4d359SAndreas Fenkart 				int vdd)
355db0fefc5SAdrian Hunter {
356aa9a6801SKishon Vijay Abraham I 	struct mmc_host *mmc = host->mmc;
357db0fefc5SAdrian Hunter 	int ret = 0;
358db0fefc5SAdrian Hunter 
359f7f0f035SAndreas Fenkart 	if (mmc_pdata(host)->set_power)
3601ca4d359SAndreas Fenkart 		return mmc_pdata(host)->set_power(host->dev, power_on, vdd);
361f7f0f035SAndreas Fenkart 
362db0fefc5SAdrian Hunter 	/*
363db0fefc5SAdrian Hunter 	 * If we don't see a Vcc regulator, assume it's a fixed
364db0fefc5SAdrian Hunter 	 * voltage always-on regulator.
365db0fefc5SAdrian Hunter 	 */
36686d79da0SKishon Vijay Abraham I 	if (IS_ERR(mmc->supply.vmmc))
367db0fefc5SAdrian Hunter 		return 0;
368db0fefc5SAdrian Hunter 
369326119c9SAndreas Fenkart 	if (mmc_pdata(host)->before_set_reg)
3701ca4d359SAndreas Fenkart 		mmc_pdata(host)->before_set_reg(host->dev, power_on, vdd);
371db0fefc5SAdrian Hunter 
372ec85c95eSKishon Vijay Abraham I 	ret = omap_hsmmc_set_pbias(host, false, 0);
373ec85c95eSKishon Vijay Abraham I 	if (ret)
374229f3292SKishon Vijay Abraham I 		return ret;
375e99448ffSBalaji T K 
376db0fefc5SAdrian Hunter 	/*
377db0fefc5SAdrian Hunter 	 * Assume Vcc regulator is used only to power the card ... OMAP
378db0fefc5SAdrian Hunter 	 * VDDS is used to power the pins, optionally with a transceiver to
379db0fefc5SAdrian Hunter 	 * support cards using voltages other than VDDS (1.8V nominal).  When a
380db0fefc5SAdrian Hunter 	 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
381db0fefc5SAdrian Hunter 	 *
382db0fefc5SAdrian Hunter 	 * In some cases this regulator won't support enable/disable;
383db0fefc5SAdrian Hunter 	 * e.g. it's a fixed rail for a WLAN chip.
384db0fefc5SAdrian Hunter 	 *
385db0fefc5SAdrian Hunter 	 * In other cases vcc_aux switches interface power.  Example, for
386db0fefc5SAdrian Hunter 	 * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
387db0fefc5SAdrian Hunter 	 * chips/cards need an interface voltage rail too.
388db0fefc5SAdrian Hunter 	 */
389db0fefc5SAdrian Hunter 	if (power_on) {
3901d17f30bSKishon Vijay Abraham I 		ret = omap_hsmmc_enable_supply(mmc);
391229f3292SKishon Vijay Abraham I 		if (ret)
392229f3292SKishon Vijay Abraham I 			return ret;
39397fe7e5aSKishon Vijay Abraham I 
39497fe7e5aSKishon Vijay Abraham I 		ret = omap_hsmmc_set_pbias(host, true, vdd);
39597fe7e5aSKishon Vijay Abraham I 		if (ret)
39697fe7e5aSKishon Vijay Abraham I 			goto err_set_voltage;
397db0fefc5SAdrian Hunter 	} else {
3982a17f844SKishon Vijay Abraham I 		ret = omap_hsmmc_disable_supply(mmc);
399229f3292SKishon Vijay Abraham I 		if (ret)
400229f3292SKishon Vijay Abraham I 			return ret;
40199fc5131SLinus Walleij 	}
402db0fefc5SAdrian Hunter 
403326119c9SAndreas Fenkart 	if (mmc_pdata(host)->after_set_reg)
4041ca4d359SAndreas Fenkart 		mmc_pdata(host)->after_set_reg(host->dev, power_on, vdd);
405db0fefc5SAdrian Hunter 
406229f3292SKishon Vijay Abraham I 	return 0;
407229f3292SKishon Vijay Abraham I 
408229f3292SKishon Vijay Abraham I err_set_voltage:
4092a17f844SKishon Vijay Abraham I 	omap_hsmmc_disable_supply(mmc);
410229f3292SKishon Vijay Abraham I 
411db0fefc5SAdrian Hunter 	return ret;
412db0fefc5SAdrian Hunter }
413db0fefc5SAdrian Hunter 
414c8518efaSKishon Vijay Abraham I static int omap_hsmmc_disable_boot_regulator(struct regulator *reg)
415c8518efaSKishon Vijay Abraham I {
416c8518efaSKishon Vijay Abraham I 	int ret;
417c8518efaSKishon Vijay Abraham I 
41886d79da0SKishon Vijay Abraham I 	if (IS_ERR(reg))
419c8518efaSKishon Vijay Abraham I 		return 0;
420c8518efaSKishon Vijay Abraham I 
421c8518efaSKishon Vijay Abraham I 	if (regulator_is_enabled(reg)) {
422c8518efaSKishon Vijay Abraham I 		ret = regulator_enable(reg);
423c8518efaSKishon Vijay Abraham I 		if (ret)
424c8518efaSKishon Vijay Abraham I 			return ret;
425c8518efaSKishon Vijay Abraham I 
426c8518efaSKishon Vijay Abraham I 		ret = regulator_disable(reg);
427c8518efaSKishon Vijay Abraham I 		if (ret)
428c8518efaSKishon Vijay Abraham I 			return ret;
429c8518efaSKishon Vijay Abraham I 	}
430c8518efaSKishon Vijay Abraham I 
431c8518efaSKishon Vijay Abraham I 	return 0;
432c8518efaSKishon Vijay Abraham I }
433c8518efaSKishon Vijay Abraham I 
434c8518efaSKishon Vijay Abraham I static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host)
435c8518efaSKishon Vijay Abraham I {
436c8518efaSKishon Vijay Abraham I 	struct mmc_host *mmc = host->mmc;
437c8518efaSKishon Vijay Abraham I 	int ret;
438c8518efaSKishon Vijay Abraham I 
439c8518efaSKishon Vijay Abraham I 	/*
440c8518efaSKishon Vijay Abraham I 	 * disable regulators enabled during boot and get the usecount
441c8518efaSKishon Vijay Abraham I 	 * right so that regulators can be enabled/disabled by checking
442c8518efaSKishon Vijay Abraham I 	 * the return value of regulator_is_enabled
443c8518efaSKishon Vijay Abraham I 	 */
444c8518efaSKishon Vijay Abraham I 	ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc);
445c8518efaSKishon Vijay Abraham I 	if (ret) {
446c8518efaSKishon Vijay Abraham I 		dev_err(host->dev, "fail to disable boot enabled vmmc reg\n");
447c8518efaSKishon Vijay Abraham I 		return ret;
448c8518efaSKishon Vijay Abraham I 	}
449c8518efaSKishon Vijay Abraham I 
450c8518efaSKishon Vijay Abraham I 	ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc);
451c8518efaSKishon Vijay Abraham I 	if (ret) {
452c8518efaSKishon Vijay Abraham I 		dev_err(host->dev,
453c8518efaSKishon Vijay Abraham I 			"fail to disable boot enabled vmmc_aux reg\n");
454c8518efaSKishon Vijay Abraham I 		return ret;
455c8518efaSKishon Vijay Abraham I 	}
456c8518efaSKishon Vijay Abraham I 
457c8518efaSKishon Vijay Abraham I 	ret = omap_hsmmc_disable_boot_regulator(host->pbias);
458c8518efaSKishon Vijay Abraham I 	if (ret) {
459c8518efaSKishon Vijay Abraham I 		dev_err(host->dev,
460c8518efaSKishon Vijay Abraham I 			"failed to disable boot enabled pbias reg\n");
461c8518efaSKishon Vijay Abraham I 		return ret;
462c8518efaSKishon Vijay Abraham I 	}
463c8518efaSKishon Vijay Abraham I 
464c8518efaSKishon Vijay Abraham I 	return 0;
465c8518efaSKishon Vijay Abraham I }
466c8518efaSKishon Vijay Abraham I 
467db0fefc5SAdrian Hunter static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
468db0fefc5SAdrian Hunter {
4697d607f91SKishon Vijay Abraham I 	int ret;
470aa9a6801SKishon Vijay Abraham I 	struct mmc_host *mmc = host->mmc;
471db0fefc5SAdrian Hunter 
472f7f0f035SAndreas Fenkart 	if (mmc_pdata(host)->set_power)
473f7f0f035SAndreas Fenkart 		return 0;
474f7f0f035SAndreas Fenkart 
47513ab2a66SKishon Vijay Abraham I 	ret = mmc_regulator_get_supply(mmc);
47613ab2a66SKishon Vijay Abraham I 	if (ret == -EPROBE_DEFER)
4777d607f91SKishon Vijay Abraham I 		return ret;
478db0fefc5SAdrian Hunter 
479db0fefc5SAdrian Hunter 	/* Allow an aux regulator */
48013ab2a66SKishon Vijay Abraham I 	if (IS_ERR(mmc->supply.vqmmc)) {
48113ab2a66SKishon Vijay Abraham I 		mmc->supply.vqmmc = devm_regulator_get_optional(host->dev,
48213ab2a66SKishon Vijay Abraham I 								"vmmc_aux");
483aa9a6801SKishon Vijay Abraham I 		if (IS_ERR(mmc->supply.vqmmc)) {
484aa9a6801SKishon Vijay Abraham I 			ret = PTR_ERR(mmc->supply.vqmmc);
485123e20b1STony Lindgren 			if ((ret != -ENODEV) && host->dev->of_node)
4866a9b2ff0SKishon Vijay Abraham I 				return ret;
4876a9b2ff0SKishon Vijay Abraham I 			dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n",
488aa9a6801SKishon Vijay Abraham I 				PTR_ERR(mmc->supply.vqmmc));
4896a9b2ff0SKishon Vijay Abraham I 		}
49013ab2a66SKishon Vijay Abraham I 	}
491db0fefc5SAdrian Hunter 
492c299dc39SKishon Vijay Abraham I 	host->pbias = devm_regulator_get_optional(host->dev, "pbias");
493c299dc39SKishon Vijay Abraham I 	if (IS_ERR(host->pbias)) {
494c299dc39SKishon Vijay Abraham I 		ret = PTR_ERR(host->pbias);
4959143757bSKishon Vijay Abraham I 		if ((ret != -ENODEV) && host->dev->of_node) {
4969143757bSKishon Vijay Abraham I 			dev_err(host->dev,
4979143757bSKishon Vijay Abraham I 			"SD card detect fail? enable CONFIG_REGULATOR_PBIAS\n");
4986a9b2ff0SKishon Vijay Abraham I 			return ret;
4999143757bSKishon Vijay Abraham I 		}
5006a9b2ff0SKishon Vijay Abraham I 		dev_dbg(host->dev, "unable to get pbias regulator %ld\n",
501c299dc39SKishon Vijay Abraham I 			PTR_ERR(host->pbias));
5026a9b2ff0SKishon Vijay Abraham I 	}
503e99448ffSBalaji T K 
504b1c1df7aSBalaji T K 	/* For eMMC do not power off when not in sleep state */
505326119c9SAndreas Fenkart 	if (mmc_pdata(host)->no_regulator_off_init)
506b1c1df7aSBalaji T K 		return 0;
507e840ce13SAdrian Hunter 
508c8518efaSKishon Vijay Abraham I 	ret = omap_hsmmc_disable_boot_regulators(host);
509c8518efaSKishon Vijay Abraham I 	if (ret)
510c8518efaSKishon Vijay Abraham I 		return ret;
511db0fefc5SAdrian Hunter 
512db0fefc5SAdrian Hunter 	return 0;
513db0fefc5SAdrian Hunter }
514db0fefc5SAdrian Hunter 
515cde592cbSAndreas Fenkart static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id);
51641afa314SNeilBrown 
51741afa314SNeilBrown static int omap_hsmmc_gpio_init(struct mmc_host *mmc,
51841afa314SNeilBrown 				struct omap_hsmmc_host *host,
5191e363e3bSAndreas Fenkart 				struct omap_hsmmc_platform_data *pdata)
520b702b106SAdrian Hunter {
521b702b106SAdrian Hunter 	int ret;
522b702b106SAdrian Hunter 
523b7a5646fSAndreas Fenkart 	if (gpio_is_valid(pdata->gpio_cod)) {
524b7a5646fSAndreas Fenkart 		ret = mmc_gpio_request_cd(mmc, pdata->gpio_cod, 0);
525b702b106SAdrian Hunter 		if (ret)
526b702b106SAdrian Hunter 			return ret;
527cde592cbSAndreas Fenkart 
528cde592cbSAndreas Fenkart 		host->get_cover_state = omap_hsmmc_get_cover_state;
529cde592cbSAndreas Fenkart 		mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq);
530b7a5646fSAndreas Fenkart 	} else if (gpio_is_valid(pdata->gpio_cd)) {
531b7a5646fSAndreas Fenkart 		ret = mmc_gpio_request_cd(mmc, pdata->gpio_cd, 0);
532cde592cbSAndreas Fenkart 		if (ret)
533cde592cbSAndreas Fenkart 			return ret;
534cde592cbSAndreas Fenkart 
535cde592cbSAndreas Fenkart 		host->card_detect = omap_hsmmc_card_detect;
536326119c9SAndreas Fenkart 	}
537b702b106SAdrian Hunter 
538326119c9SAndreas Fenkart 	if (gpio_is_valid(pdata->gpio_wp)) {
53941afa314SNeilBrown 		ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp);
540b702b106SAdrian Hunter 		if (ret)
54141afa314SNeilBrown 			return ret;
542326119c9SAndreas Fenkart 	}
543b702b106SAdrian Hunter 
544b702b106SAdrian Hunter 	return 0;
545b702b106SAdrian Hunter }
546b702b106SAdrian Hunter 
547a45c6cb8SMadhusudhan Chikkature /*
548e0c7f99bSAndy Shevchenko  * Start clock to the card
549e0c7f99bSAndy Shevchenko  */
550e0c7f99bSAndy Shevchenko static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
551e0c7f99bSAndy Shevchenko {
552e0c7f99bSAndy Shevchenko 	OMAP_HSMMC_WRITE(host->base, SYSCTL,
553e0c7f99bSAndy Shevchenko 		OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
554e0c7f99bSAndy Shevchenko }
555e0c7f99bSAndy Shevchenko 
556e0c7f99bSAndy Shevchenko /*
557a45c6cb8SMadhusudhan Chikkature  * Stop clock to the card
558a45c6cb8SMadhusudhan Chikkature  */
55970a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
560a45c6cb8SMadhusudhan Chikkature {
561a45c6cb8SMadhusudhan Chikkature 	OMAP_HSMMC_WRITE(host->base, SYSCTL,
562a45c6cb8SMadhusudhan Chikkature 		OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
563a45c6cb8SMadhusudhan Chikkature 	if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
5647122bbb0SMasanari Iida 		dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
565a45c6cb8SMadhusudhan Chikkature }
566a45c6cb8SMadhusudhan Chikkature 
56793caf8e6SAdrian Hunter static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
56893caf8e6SAdrian Hunter 				  struct mmc_command *cmd)
569b417577dSAdrian Hunter {
5702cd3a2a5SAndreas Fenkart 	u32 irq_mask = INT_EN_MASK;
5712cd3a2a5SAndreas Fenkart 	unsigned long flags;
572b417577dSAdrian Hunter 
573b417577dSAdrian Hunter 	if (host->use_dma)
5742cd3a2a5SAndreas Fenkart 		irq_mask &= ~(BRR_EN | BWR_EN);
575b417577dSAdrian Hunter 
57693caf8e6SAdrian Hunter 	/* Disable timeout for erases */
57793caf8e6SAdrian Hunter 	if (cmd->opcode == MMC_ERASE)
578a7e96879SVenkatraman S 		irq_mask &= ~DTO_EN;
57993caf8e6SAdrian Hunter 
5802cd3a2a5SAndreas Fenkart 	spin_lock_irqsave(&host->irq_lock, flags);
581b417577dSAdrian Hunter 	OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
582b417577dSAdrian Hunter 	OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
5832cd3a2a5SAndreas Fenkart 
5842cd3a2a5SAndreas Fenkart 	/* latch pending CIRQ, but don't signal MMC core */
5852cd3a2a5SAndreas Fenkart 	if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
5862cd3a2a5SAndreas Fenkart 		irq_mask |= CIRQ_EN;
587b417577dSAdrian Hunter 	OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
5882cd3a2a5SAndreas Fenkart 	spin_unlock_irqrestore(&host->irq_lock, flags);
589b417577dSAdrian Hunter }
590b417577dSAdrian Hunter 
591b417577dSAdrian Hunter static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
592b417577dSAdrian Hunter {
5932cd3a2a5SAndreas Fenkart 	u32 irq_mask = 0;
5942cd3a2a5SAndreas Fenkart 	unsigned long flags;
5952cd3a2a5SAndreas Fenkart 
5962cd3a2a5SAndreas Fenkart 	spin_lock_irqsave(&host->irq_lock, flags);
5972cd3a2a5SAndreas Fenkart 	/* no transfer running but need to keep cirq if enabled */
5982cd3a2a5SAndreas Fenkart 	if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
5992cd3a2a5SAndreas Fenkart 		irq_mask |= CIRQ_EN;
6002cd3a2a5SAndreas Fenkart 	OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
6012cd3a2a5SAndreas Fenkart 	OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
602b417577dSAdrian Hunter 	OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
6032cd3a2a5SAndreas Fenkart 	spin_unlock_irqrestore(&host->irq_lock, flags);
604b417577dSAdrian Hunter }
605b417577dSAdrian Hunter 
606ac330f44SAndy Shevchenko /* Calculate divisor for the given clock frequency */
607d83b6e03SBalaji TK static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
608ac330f44SAndy Shevchenko {
609ac330f44SAndy Shevchenko 	u16 dsor = 0;
610ac330f44SAndy Shevchenko 
611ac330f44SAndy Shevchenko 	if (ios->clock) {
612d83b6e03SBalaji TK 		dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
613ed164182SBalaji T K 		if (dsor > CLKD_MAX)
614ed164182SBalaji T K 			dsor = CLKD_MAX;
615ac330f44SAndy Shevchenko 	}
616ac330f44SAndy Shevchenko 
617ac330f44SAndy Shevchenko 	return dsor;
618ac330f44SAndy Shevchenko }
619ac330f44SAndy Shevchenko 
6205934df2fSAndy Shevchenko static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
6215934df2fSAndy Shevchenko {
6225934df2fSAndy Shevchenko 	struct mmc_ios *ios = &host->mmc->ios;
6235934df2fSAndy Shevchenko 	unsigned long regval;
6245934df2fSAndy Shevchenko 	unsigned long timeout;
625cd587096SHebbar, Gururaja 	unsigned long clkdiv;
6265934df2fSAndy Shevchenko 
6278986d31bSVenkatraman S 	dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
6285934df2fSAndy Shevchenko 
6295934df2fSAndy Shevchenko 	omap_hsmmc_stop_clock(host);
6305934df2fSAndy Shevchenko 
6315934df2fSAndy Shevchenko 	regval = OMAP_HSMMC_READ(host->base, SYSCTL);
6325934df2fSAndy Shevchenko 	regval = regval & ~(CLKD_MASK | DTO_MASK);
633cd587096SHebbar, Gururaja 	clkdiv = calc_divisor(host, ios);
634cd587096SHebbar, Gururaja 	regval = regval | (clkdiv << 6) | (DTO << 16);
6355934df2fSAndy Shevchenko 	OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
6365934df2fSAndy Shevchenko 	OMAP_HSMMC_WRITE(host->base, SYSCTL,
6375934df2fSAndy Shevchenko 		OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
6385934df2fSAndy Shevchenko 
6395934df2fSAndy Shevchenko 	/* Wait till the ICS bit is set */
6405934df2fSAndy Shevchenko 	timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
6415934df2fSAndy Shevchenko 	while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
6425934df2fSAndy Shevchenko 		&& time_before(jiffies, timeout))
6435934df2fSAndy Shevchenko 		cpu_relax();
6445934df2fSAndy Shevchenko 
645cd587096SHebbar, Gururaja 	/*
646cd587096SHebbar, Gururaja 	 * Enable High-Speed Support
647cd587096SHebbar, Gururaja 	 * Pre-Requisites
648cd587096SHebbar, Gururaja 	 *	- Controller should support High-Speed-Enable Bit
649cd587096SHebbar, Gururaja 	 *	- Controller should not be using DDR Mode
650cd587096SHebbar, Gururaja 	 *	- Controller should advertise that it supports High Speed
651cd587096SHebbar, Gururaja 	 *	  in capabilities register
652cd587096SHebbar, Gururaja 	 *	- MMC/SD clock coming out of controller > 25MHz
653cd587096SHebbar, Gururaja 	 */
654326119c9SAndreas Fenkart 	if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
6555438ad95SSeungwon Jeon 	    (ios->timing != MMC_TIMING_MMC_DDR52) &&
656903101a8SUlf Hansson 	    (ios->timing != MMC_TIMING_UHS_DDR50) &&
657cd587096SHebbar, Gururaja 	    ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
658cd587096SHebbar, Gururaja 		regval = OMAP_HSMMC_READ(host->base, HCTL);
659cd587096SHebbar, Gururaja 		if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
660cd587096SHebbar, Gururaja 			regval |= HSPE;
661cd587096SHebbar, Gururaja 		else
662cd587096SHebbar, Gururaja 			regval &= ~HSPE;
663cd587096SHebbar, Gururaja 
664cd587096SHebbar, Gururaja 		OMAP_HSMMC_WRITE(host->base, HCTL, regval);
665cd587096SHebbar, Gururaja 	}
666cd587096SHebbar, Gururaja 
6675934df2fSAndy Shevchenko 	omap_hsmmc_start_clock(host);
6685934df2fSAndy Shevchenko }
6695934df2fSAndy Shevchenko 
6703796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
6713796fb8aSAndy Shevchenko {
6723796fb8aSAndy Shevchenko 	struct mmc_ios *ios = &host->mmc->ios;
6733796fb8aSAndy Shevchenko 	u32 con;
6743796fb8aSAndy Shevchenko 
6753796fb8aSAndy Shevchenko 	con = OMAP_HSMMC_READ(host->base, CON);
676903101a8SUlf Hansson 	if (ios->timing == MMC_TIMING_MMC_DDR52 ||
677903101a8SUlf Hansson 	    ios->timing == MMC_TIMING_UHS_DDR50)
67803b5d924SBalaji T K 		con |= DDR;	/* configure in DDR mode */
67903b5d924SBalaji T K 	else
68003b5d924SBalaji T K 		con &= ~DDR;
6813796fb8aSAndy Shevchenko 	switch (ios->bus_width) {
6823796fb8aSAndy Shevchenko 	case MMC_BUS_WIDTH_8:
6833796fb8aSAndy Shevchenko 		OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
6843796fb8aSAndy Shevchenko 		break;
6853796fb8aSAndy Shevchenko 	case MMC_BUS_WIDTH_4:
6863796fb8aSAndy Shevchenko 		OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
6873796fb8aSAndy Shevchenko 		OMAP_HSMMC_WRITE(host->base, HCTL,
6883796fb8aSAndy Shevchenko 			OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
6893796fb8aSAndy Shevchenko 		break;
6903796fb8aSAndy Shevchenko 	case MMC_BUS_WIDTH_1:
6913796fb8aSAndy Shevchenko 		OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
6923796fb8aSAndy Shevchenko 		OMAP_HSMMC_WRITE(host->base, HCTL,
6933796fb8aSAndy Shevchenko 			OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
6943796fb8aSAndy Shevchenko 		break;
6953796fb8aSAndy Shevchenko 	}
6963796fb8aSAndy Shevchenko }
6973796fb8aSAndy Shevchenko 
6983796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
6993796fb8aSAndy Shevchenko {
7003796fb8aSAndy Shevchenko 	struct mmc_ios *ios = &host->mmc->ios;
7013796fb8aSAndy Shevchenko 	u32 con;
7023796fb8aSAndy Shevchenko 
7033796fb8aSAndy Shevchenko 	con = OMAP_HSMMC_READ(host->base, CON);
7043796fb8aSAndy Shevchenko 	if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
7053796fb8aSAndy Shevchenko 		OMAP_HSMMC_WRITE(host->base, CON, con | OD);
7063796fb8aSAndy Shevchenko 	else
7073796fb8aSAndy Shevchenko 		OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
7083796fb8aSAndy Shevchenko }
7093796fb8aSAndy Shevchenko 
71011dd62a7SDenis Karpov #ifdef CONFIG_PM
71111dd62a7SDenis Karpov 
71211dd62a7SDenis Karpov /*
71311dd62a7SDenis Karpov  * Restore the MMC host context, if it was lost as result of a
71411dd62a7SDenis Karpov  * power state change.
71511dd62a7SDenis Karpov  */
71670a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
71711dd62a7SDenis Karpov {
71811dd62a7SDenis Karpov 	struct mmc_ios *ios = &host->mmc->ios;
7193796fb8aSAndy Shevchenko 	u32 hctl, capa;
72011dd62a7SDenis Karpov 	unsigned long timeout;
72111dd62a7SDenis Karpov 
7220a82e06eSTony Lindgren 	if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
7230a82e06eSTony Lindgren 	    host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
7240a82e06eSTony Lindgren 	    host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
7250a82e06eSTony Lindgren 	    host->capa == OMAP_HSMMC_READ(host->base, CAPA))
7260a82e06eSTony Lindgren 		return 0;
7270a82e06eSTony Lindgren 
7280a82e06eSTony Lindgren 	host->context_loss++;
7290a82e06eSTony Lindgren 
730c2200efbSBalaji T K 	if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
73111dd62a7SDenis Karpov 		if (host->power_mode != MMC_POWER_OFF &&
73211dd62a7SDenis Karpov 		    (1 << ios->vdd) <= MMC_VDD_23_24)
73311dd62a7SDenis Karpov 			hctl = SDVS18;
73411dd62a7SDenis Karpov 		else
73511dd62a7SDenis Karpov 			hctl = SDVS30;
73611dd62a7SDenis Karpov 		capa = VS30 | VS18;
73711dd62a7SDenis Karpov 	} else {
73811dd62a7SDenis Karpov 		hctl = SDVS18;
73911dd62a7SDenis Karpov 		capa = VS18;
74011dd62a7SDenis Karpov 	}
74111dd62a7SDenis Karpov 
7425a52b08bSBalaji T K 	if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
7435a52b08bSBalaji T K 		hctl |= IWE;
7445a52b08bSBalaji T K 
74511dd62a7SDenis Karpov 	OMAP_HSMMC_WRITE(host->base, HCTL,
74611dd62a7SDenis Karpov 			OMAP_HSMMC_READ(host->base, HCTL) | hctl);
74711dd62a7SDenis Karpov 
74811dd62a7SDenis Karpov 	OMAP_HSMMC_WRITE(host->base, CAPA,
74911dd62a7SDenis Karpov 			OMAP_HSMMC_READ(host->base, CAPA) | capa);
75011dd62a7SDenis Karpov 
75111dd62a7SDenis Karpov 	OMAP_HSMMC_WRITE(host->base, HCTL,
75211dd62a7SDenis Karpov 			OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
75311dd62a7SDenis Karpov 
75411dd62a7SDenis Karpov 	timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
75511dd62a7SDenis Karpov 	while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
75611dd62a7SDenis Karpov 		&& time_before(jiffies, timeout))
75711dd62a7SDenis Karpov 		;
75811dd62a7SDenis Karpov 
7592cd3a2a5SAndreas Fenkart 	OMAP_HSMMC_WRITE(host->base, ISE, 0);
7602cd3a2a5SAndreas Fenkart 	OMAP_HSMMC_WRITE(host->base, IE, 0);
7612cd3a2a5SAndreas Fenkart 	OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
76211dd62a7SDenis Karpov 
76311dd62a7SDenis Karpov 	/* Do not initialize card-specific things if the power is off */
76411dd62a7SDenis Karpov 	if (host->power_mode == MMC_POWER_OFF)
76511dd62a7SDenis Karpov 		goto out;
76611dd62a7SDenis Karpov 
7673796fb8aSAndy Shevchenko 	omap_hsmmc_set_bus_width(host);
76811dd62a7SDenis Karpov 
7695934df2fSAndy Shevchenko 	omap_hsmmc_set_clock(host);
77011dd62a7SDenis Karpov 
7713796fb8aSAndy Shevchenko 	omap_hsmmc_set_bus_mode(host);
7723796fb8aSAndy Shevchenko 
77311dd62a7SDenis Karpov out:
7740a82e06eSTony Lindgren 	dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
7750a82e06eSTony Lindgren 		host->context_loss);
77611dd62a7SDenis Karpov 	return 0;
77711dd62a7SDenis Karpov }
77811dd62a7SDenis Karpov 
77911dd62a7SDenis Karpov /*
78011dd62a7SDenis Karpov  * Save the MMC host context (store the number of power state changes so far).
78111dd62a7SDenis Karpov  */
78270a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
78311dd62a7SDenis Karpov {
7840a82e06eSTony Lindgren 	host->con =  OMAP_HSMMC_READ(host->base, CON);
7850a82e06eSTony Lindgren 	host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
7860a82e06eSTony Lindgren 	host->sysctl =  OMAP_HSMMC_READ(host->base, SYSCTL);
7870a82e06eSTony Lindgren 	host->capa = OMAP_HSMMC_READ(host->base, CAPA);
78811dd62a7SDenis Karpov }
78911dd62a7SDenis Karpov 
79011dd62a7SDenis Karpov #else
79111dd62a7SDenis Karpov 
79270a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
79311dd62a7SDenis Karpov {
79411dd62a7SDenis Karpov 	return 0;
79511dd62a7SDenis Karpov }
79611dd62a7SDenis Karpov 
79770a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
79811dd62a7SDenis Karpov {
79911dd62a7SDenis Karpov }
80011dd62a7SDenis Karpov 
80111dd62a7SDenis Karpov #endif
80211dd62a7SDenis Karpov 
803a45c6cb8SMadhusudhan Chikkature /*
804a45c6cb8SMadhusudhan Chikkature  * Send init stream sequence to card
805a45c6cb8SMadhusudhan Chikkature  * before sending IDLE command
806a45c6cb8SMadhusudhan Chikkature  */
80770a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host)
808a45c6cb8SMadhusudhan Chikkature {
809a45c6cb8SMadhusudhan Chikkature 	int reg = 0;
810a45c6cb8SMadhusudhan Chikkature 	unsigned long timeout;
811a45c6cb8SMadhusudhan Chikkature 
812b62f6228SAdrian Hunter 	if (host->protect_card)
813b62f6228SAdrian Hunter 		return;
814b62f6228SAdrian Hunter 
815a45c6cb8SMadhusudhan Chikkature 	disable_irq(host->irq);
816b417577dSAdrian Hunter 
817b417577dSAdrian Hunter 	OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
818a45c6cb8SMadhusudhan Chikkature 	OMAP_HSMMC_WRITE(host->base, CON,
819a45c6cb8SMadhusudhan Chikkature 		OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
820a45c6cb8SMadhusudhan Chikkature 	OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
821a45c6cb8SMadhusudhan Chikkature 
822a45c6cb8SMadhusudhan Chikkature 	timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
823a7e96879SVenkatraman S 	while ((reg != CC_EN) && time_before(jiffies, timeout))
824a7e96879SVenkatraman S 		reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
825a45c6cb8SMadhusudhan Chikkature 
826a45c6cb8SMadhusudhan Chikkature 	OMAP_HSMMC_WRITE(host->base, CON,
827a45c6cb8SMadhusudhan Chikkature 		OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
828c653a6d4SAdrian Hunter 
829c653a6d4SAdrian Hunter 	OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
830c653a6d4SAdrian Hunter 	OMAP_HSMMC_READ(host->base, STAT);
831c653a6d4SAdrian Hunter 
832a45c6cb8SMadhusudhan Chikkature 	enable_irq(host->irq);
833a45c6cb8SMadhusudhan Chikkature }
834a45c6cb8SMadhusudhan Chikkature 
835a45c6cb8SMadhusudhan Chikkature static inline
83670a3341aSDenis Karpov int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
837a45c6cb8SMadhusudhan Chikkature {
838a45c6cb8SMadhusudhan Chikkature 	int r = 1;
839a45c6cb8SMadhusudhan Chikkature 
840b5cd43f0SAndreas Fenkart 	if (host->get_cover_state)
84180412ca8SAndreas Fenkart 		r = host->get_cover_state(host->dev);
842a45c6cb8SMadhusudhan Chikkature 	return r;
843a45c6cb8SMadhusudhan Chikkature }
844a45c6cb8SMadhusudhan Chikkature 
845a45c6cb8SMadhusudhan Chikkature static ssize_t
84670a3341aSDenis Karpov omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
847a45c6cb8SMadhusudhan Chikkature 			   char *buf)
848a45c6cb8SMadhusudhan Chikkature {
849a45c6cb8SMadhusudhan Chikkature 	struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
85070a3341aSDenis Karpov 	struct omap_hsmmc_host *host = mmc_priv(mmc);
851a45c6cb8SMadhusudhan Chikkature 
85270a3341aSDenis Karpov 	return sprintf(buf, "%s\n",
85370a3341aSDenis Karpov 			omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
854a45c6cb8SMadhusudhan Chikkature }
855a45c6cb8SMadhusudhan Chikkature 
85670a3341aSDenis Karpov static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
857a45c6cb8SMadhusudhan Chikkature 
858a45c6cb8SMadhusudhan Chikkature static ssize_t
85970a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
860a45c6cb8SMadhusudhan Chikkature 			char *buf)
861a45c6cb8SMadhusudhan Chikkature {
862a45c6cb8SMadhusudhan Chikkature 	struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
86370a3341aSDenis Karpov 	struct omap_hsmmc_host *host = mmc_priv(mmc);
864a45c6cb8SMadhusudhan Chikkature 
865326119c9SAndreas Fenkart 	return sprintf(buf, "%s\n", mmc_pdata(host)->name);
866a45c6cb8SMadhusudhan Chikkature }
867a45c6cb8SMadhusudhan Chikkature 
86870a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
869a45c6cb8SMadhusudhan Chikkature 
870a45c6cb8SMadhusudhan Chikkature /*
871a45c6cb8SMadhusudhan Chikkature  * Configure the response type and send the cmd.
872a45c6cb8SMadhusudhan Chikkature  */
873a45c6cb8SMadhusudhan Chikkature static void
87470a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
875a45c6cb8SMadhusudhan Chikkature 	struct mmc_data *data)
876a45c6cb8SMadhusudhan Chikkature {
877a45c6cb8SMadhusudhan Chikkature 	int cmdreg = 0, resptype = 0, cmdtype = 0;
878a45c6cb8SMadhusudhan Chikkature 
8798986d31bSVenkatraman S 	dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
880a45c6cb8SMadhusudhan Chikkature 		mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
881a45c6cb8SMadhusudhan Chikkature 	host->cmd = cmd;
882a45c6cb8SMadhusudhan Chikkature 
88393caf8e6SAdrian Hunter 	omap_hsmmc_enable_irq(host, cmd);
884a45c6cb8SMadhusudhan Chikkature 
8854a694dc9SAdrian Hunter 	host->response_busy = 0;
886a45c6cb8SMadhusudhan Chikkature 	if (cmd->flags & MMC_RSP_PRESENT) {
887a45c6cb8SMadhusudhan Chikkature 		if (cmd->flags & MMC_RSP_136)
888a45c6cb8SMadhusudhan Chikkature 			resptype = 1;
8894a694dc9SAdrian Hunter 		else if (cmd->flags & MMC_RSP_BUSY) {
8904a694dc9SAdrian Hunter 			resptype = 3;
8914a694dc9SAdrian Hunter 			host->response_busy = 1;
8924a694dc9SAdrian Hunter 		} else
893a45c6cb8SMadhusudhan Chikkature 			resptype = 2;
894a45c6cb8SMadhusudhan Chikkature 	}
895a45c6cb8SMadhusudhan Chikkature 
896a45c6cb8SMadhusudhan Chikkature 	/*
897a45c6cb8SMadhusudhan Chikkature 	 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
898a45c6cb8SMadhusudhan Chikkature 	 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
899a45c6cb8SMadhusudhan Chikkature 	 * a val of 0x3, rest 0x0.
900a45c6cb8SMadhusudhan Chikkature 	 */
901a45c6cb8SMadhusudhan Chikkature 	if (cmd == host->mrq->stop)
902a45c6cb8SMadhusudhan Chikkature 		cmdtype = 0x3;
903a45c6cb8SMadhusudhan Chikkature 
904a45c6cb8SMadhusudhan Chikkature 	cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
905a45c6cb8SMadhusudhan Chikkature 
906a2e77152SBalaji T K 	if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
907a2e77152SBalaji T K 	    host->mrq->sbc) {
908a2e77152SBalaji T K 		cmdreg |= ACEN_ACMD23;
909a2e77152SBalaji T K 		OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
910a2e77152SBalaji T K 	}
911a45c6cb8SMadhusudhan Chikkature 	if (data) {
912a45c6cb8SMadhusudhan Chikkature 		cmdreg |= DP_SELECT | MSBS | BCE;
913a45c6cb8SMadhusudhan Chikkature 		if (data->flags & MMC_DATA_READ)
914a45c6cb8SMadhusudhan Chikkature 			cmdreg |= DDIR;
915a45c6cb8SMadhusudhan Chikkature 		else
916a45c6cb8SMadhusudhan Chikkature 			cmdreg &= ~(DDIR);
917a45c6cb8SMadhusudhan Chikkature 	}
918a45c6cb8SMadhusudhan Chikkature 
919a45c6cb8SMadhusudhan Chikkature 	if (host->use_dma)
920a7e96879SVenkatraman S 		cmdreg |= DMAE;
921a45c6cb8SMadhusudhan Chikkature 
922b417577dSAdrian Hunter 	host->req_in_progress = 1;
9234dffd7a2SAdrian Hunter 
924a45c6cb8SMadhusudhan Chikkature 	OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
925a45c6cb8SMadhusudhan Chikkature 	OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
926a45c6cb8SMadhusudhan Chikkature }
927a45c6cb8SMadhusudhan Chikkature 
928c5c98927SRussell King static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
929c5c98927SRussell King 	struct mmc_data *data)
930c5c98927SRussell King {
931c5c98927SRussell King 	return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
932c5c98927SRussell King }
933c5c98927SRussell King 
934b417577dSAdrian Hunter static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
935b417577dSAdrian Hunter {
936b417577dSAdrian Hunter 	int dma_ch;
93731463b14SVenkatraman S 	unsigned long flags;
938b417577dSAdrian Hunter 
93931463b14SVenkatraman S 	spin_lock_irqsave(&host->irq_lock, flags);
940b417577dSAdrian Hunter 	host->req_in_progress = 0;
941b417577dSAdrian Hunter 	dma_ch = host->dma_ch;
94231463b14SVenkatraman S 	spin_unlock_irqrestore(&host->irq_lock, flags);
943b417577dSAdrian Hunter 
944b417577dSAdrian Hunter 	omap_hsmmc_disable_irq(host);
945b417577dSAdrian Hunter 	/* Do not complete the request if DMA is still in progress */
946b417577dSAdrian Hunter 	if (mrq->data && host->use_dma && dma_ch != -1)
947b417577dSAdrian Hunter 		return;
948b417577dSAdrian Hunter 	host->mrq = NULL;
949b417577dSAdrian Hunter 	mmc_request_done(host->mmc, mrq);
950b417577dSAdrian Hunter }
951b417577dSAdrian Hunter 
952a45c6cb8SMadhusudhan Chikkature /*
953a45c6cb8SMadhusudhan Chikkature  * Notify the transfer complete to MMC core
954a45c6cb8SMadhusudhan Chikkature  */
955a45c6cb8SMadhusudhan Chikkature static void
95670a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
957a45c6cb8SMadhusudhan Chikkature {
9584a694dc9SAdrian Hunter 	if (!data) {
9594a694dc9SAdrian Hunter 		struct mmc_request *mrq = host->mrq;
9604a694dc9SAdrian Hunter 
96123050103SAdrian Hunter 		/* TC before CC from CMD6 - don't know why, but it happens */
96223050103SAdrian Hunter 		if (host->cmd && host->cmd->opcode == 6 &&
96323050103SAdrian Hunter 		    host->response_busy) {
96423050103SAdrian Hunter 			host->response_busy = 0;
96523050103SAdrian Hunter 			return;
96623050103SAdrian Hunter 		}
96723050103SAdrian Hunter 
968b417577dSAdrian Hunter 		omap_hsmmc_request_done(host, mrq);
9694a694dc9SAdrian Hunter 		return;
9704a694dc9SAdrian Hunter 	}
9714a694dc9SAdrian Hunter 
972a45c6cb8SMadhusudhan Chikkature 	host->data = NULL;
973a45c6cb8SMadhusudhan Chikkature 
974a45c6cb8SMadhusudhan Chikkature 	if (!data->error)
975a45c6cb8SMadhusudhan Chikkature 		data->bytes_xfered += data->blocks * (data->blksz);
976a45c6cb8SMadhusudhan Chikkature 	else
977a45c6cb8SMadhusudhan Chikkature 		data->bytes_xfered = 0;
978a45c6cb8SMadhusudhan Chikkature 
979bf129e1cSBalaji T K 	if (data->stop && (data->error || !host->mrq->sbc))
980fe852273SMing Lei 		omap_hsmmc_start_command(host, data->stop, NULL);
981bf129e1cSBalaji T K 	else
982bf129e1cSBalaji T K 		omap_hsmmc_request_done(host, data->mrq);
983a45c6cb8SMadhusudhan Chikkature }
984a45c6cb8SMadhusudhan Chikkature 
985a45c6cb8SMadhusudhan Chikkature /*
986a45c6cb8SMadhusudhan Chikkature  * Notify the core about command completion
987a45c6cb8SMadhusudhan Chikkature  */
988a45c6cb8SMadhusudhan Chikkature static void
98970a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
990a45c6cb8SMadhusudhan Chikkature {
991bf129e1cSBalaji T K 	if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
992a2e77152SBalaji T K 	    !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
9932177fa94SBalaji T K 		host->cmd = NULL;
994bf129e1cSBalaji T K 		omap_hsmmc_start_dma_transfer(host);
995bf129e1cSBalaji T K 		omap_hsmmc_start_command(host, host->mrq->cmd,
996bf129e1cSBalaji T K 						host->mrq->data);
997bf129e1cSBalaji T K 		return;
998bf129e1cSBalaji T K 	}
999bf129e1cSBalaji T K 
10002177fa94SBalaji T K 	host->cmd = NULL;
10012177fa94SBalaji T K 
1002a45c6cb8SMadhusudhan Chikkature 	if (cmd->flags & MMC_RSP_PRESENT) {
1003a45c6cb8SMadhusudhan Chikkature 		if (cmd->flags & MMC_RSP_136) {
1004a45c6cb8SMadhusudhan Chikkature 			/* response type 2 */
1005a45c6cb8SMadhusudhan Chikkature 			cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
1006a45c6cb8SMadhusudhan Chikkature 			cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
1007a45c6cb8SMadhusudhan Chikkature 			cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
1008a45c6cb8SMadhusudhan Chikkature 			cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
1009a45c6cb8SMadhusudhan Chikkature 		} else {
1010a45c6cb8SMadhusudhan Chikkature 			/* response types 1, 1b, 3, 4, 5, 6 */
1011a45c6cb8SMadhusudhan Chikkature 			cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
1012a45c6cb8SMadhusudhan Chikkature 		}
1013a45c6cb8SMadhusudhan Chikkature 	}
1014b417577dSAdrian Hunter 	if ((host->data == NULL && !host->response_busy) || cmd->error)
1015d4b2c375SBalaji T K 		omap_hsmmc_request_done(host, host->mrq);
1016a45c6cb8SMadhusudhan Chikkature }
1017a45c6cb8SMadhusudhan Chikkature 
1018a45c6cb8SMadhusudhan Chikkature /*
1019a45c6cb8SMadhusudhan Chikkature  * DMA clean up for command errors
1020a45c6cb8SMadhusudhan Chikkature  */
102170a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
1022a45c6cb8SMadhusudhan Chikkature {
1023b417577dSAdrian Hunter 	int dma_ch;
102431463b14SVenkatraman S 	unsigned long flags;
1025b417577dSAdrian Hunter 
102682788ff5SJarkko Lavinen 	host->data->error = errno;
1027a45c6cb8SMadhusudhan Chikkature 
102831463b14SVenkatraman S 	spin_lock_irqsave(&host->irq_lock, flags);
1029b417577dSAdrian Hunter 	dma_ch = host->dma_ch;
1030b417577dSAdrian Hunter 	host->dma_ch = -1;
103131463b14SVenkatraman S 	spin_unlock_irqrestore(&host->irq_lock, flags);
1032b417577dSAdrian Hunter 
1033b417577dSAdrian Hunter 	if (host->use_dma && dma_ch != -1) {
1034c5c98927SRussell King 		struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
1035c5c98927SRussell King 
1036c5c98927SRussell King 		dmaengine_terminate_all(chan);
1037c5c98927SRussell King 		dma_unmap_sg(chan->device->dev,
1038c5c98927SRussell King 			host->data->sg, host->data->sg_len,
1039feeef096SHeiner Kallweit 			mmc_get_dma_dir(host->data));
1040c5c98927SRussell King 
1041053bf34fSPer Forlin 		host->data->host_cookie = 0;
1042a45c6cb8SMadhusudhan Chikkature 	}
1043a45c6cb8SMadhusudhan Chikkature 	host->data = NULL;
1044a45c6cb8SMadhusudhan Chikkature }
1045a45c6cb8SMadhusudhan Chikkature 
1046a45c6cb8SMadhusudhan Chikkature /*
1047a45c6cb8SMadhusudhan Chikkature  * Readable error output
1048a45c6cb8SMadhusudhan Chikkature  */
1049a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG
1050699b958bSAdrian Hunter static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
1051a45c6cb8SMadhusudhan Chikkature {
1052a45c6cb8SMadhusudhan Chikkature 	/* --- means reserved bit without definition at documentation */
105370a3341aSDenis Karpov 	static const char *omap_hsmmc_status_bits[] = {
1054699b958bSAdrian Hunter 		"CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
1055699b958bSAdrian Hunter 		"CIRQ",	"OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
1056699b958bSAdrian Hunter 		"CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
1057699b958bSAdrian Hunter 		"ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
1058a45c6cb8SMadhusudhan Chikkature 	};
1059a45c6cb8SMadhusudhan Chikkature 	char res[256];
1060a45c6cb8SMadhusudhan Chikkature 	char *buf = res;
1061a45c6cb8SMadhusudhan Chikkature 	int len, i;
1062a45c6cb8SMadhusudhan Chikkature 
1063a45c6cb8SMadhusudhan Chikkature 	len = sprintf(buf, "MMC IRQ 0x%x :", status);
1064a45c6cb8SMadhusudhan Chikkature 	buf += len;
1065a45c6cb8SMadhusudhan Chikkature 
106670a3341aSDenis Karpov 	for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
1067a45c6cb8SMadhusudhan Chikkature 		if (status & (1 << i)) {
106870a3341aSDenis Karpov 			len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1069a45c6cb8SMadhusudhan Chikkature 			buf += len;
1070a45c6cb8SMadhusudhan Chikkature 		}
1071a45c6cb8SMadhusudhan Chikkature 
10728986d31bSVenkatraman S 	dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
1073a45c6cb8SMadhusudhan Chikkature }
1074699b958bSAdrian Hunter #else
1075699b958bSAdrian Hunter static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1076699b958bSAdrian Hunter 					     u32 status)
1077699b958bSAdrian Hunter {
1078699b958bSAdrian Hunter }
1079a45c6cb8SMadhusudhan Chikkature #endif  /* CONFIG_MMC_DEBUG */
1080a45c6cb8SMadhusudhan Chikkature 
10813ebf74b1SJean Pihet /*
10823ebf74b1SJean Pihet  * MMC controller internal state machines reset
10833ebf74b1SJean Pihet  *
10843ebf74b1SJean Pihet  * Used to reset command or data internal state machines, using respectively
10853ebf74b1SJean Pihet  *  SRC or SRD bit of SYSCTL register
10863ebf74b1SJean Pihet  * Can be called from interrupt context
10873ebf74b1SJean Pihet  */
108870a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
10893ebf74b1SJean Pihet 						   unsigned long bit)
10903ebf74b1SJean Pihet {
10913ebf74b1SJean Pihet 	unsigned long i = 0;
10921e881786SJianpeng Ma 	unsigned long limit = MMC_TIMEOUT_US;
10933ebf74b1SJean Pihet 
10943ebf74b1SJean Pihet 	OMAP_HSMMC_WRITE(host->base, SYSCTL,
10953ebf74b1SJean Pihet 			 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
10963ebf74b1SJean Pihet 
109707ad64b6SMadhusudhan Chikkature 	/*
109807ad64b6SMadhusudhan Chikkature 	 * OMAP4 ES2 and greater has an updated reset logic.
109907ad64b6SMadhusudhan Chikkature 	 * Monitor a 0->1 transition first
110007ad64b6SMadhusudhan Chikkature 	 */
1101326119c9SAndreas Fenkart 	if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
1102b432b4b3Skishore kadiyala 		while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
110307ad64b6SMadhusudhan Chikkature 					&& (i++ < limit))
11041e881786SJianpeng Ma 			udelay(1);
110507ad64b6SMadhusudhan Chikkature 	}
110607ad64b6SMadhusudhan Chikkature 	i = 0;
110707ad64b6SMadhusudhan Chikkature 
11083ebf74b1SJean Pihet 	while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
11093ebf74b1SJean Pihet 		(i++ < limit))
11101e881786SJianpeng Ma 		udelay(1);
11113ebf74b1SJean Pihet 
11123ebf74b1SJean Pihet 	if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
11133ebf74b1SJean Pihet 		dev_err(mmc_dev(host->mmc),
11143ebf74b1SJean Pihet 			"Timeout waiting on controller reset in %s\n",
11153ebf74b1SJean Pihet 			__func__);
11163ebf74b1SJean Pihet }
1117a45c6cb8SMadhusudhan Chikkature 
111825e1897bSBalaji T K static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
111925e1897bSBalaji T K 					int err, int end_cmd)
1120ae4bf788SVenkatraman S {
112125e1897bSBalaji T K 	if (end_cmd) {
112294d4f272SBalaji T K 		omap_hsmmc_reset_controller_fsm(host, SRC);
112325e1897bSBalaji T K 		if (host->cmd)
1124ae4bf788SVenkatraman S 			host->cmd->error = err;
112525e1897bSBalaji T K 	}
1126ae4bf788SVenkatraman S 
1127ae4bf788SVenkatraman S 	if (host->data) {
1128ae4bf788SVenkatraman S 		omap_hsmmc_reset_controller_fsm(host, SRD);
1129ae4bf788SVenkatraman S 		omap_hsmmc_dma_cleanup(host, err);
1130dc7745bdSBalaji T K 	} else if (host->mrq && host->mrq->cmd)
1131dc7745bdSBalaji T K 		host->mrq->cmd->error = err;
1132ae4bf788SVenkatraman S }
1133ae4bf788SVenkatraman S 
1134b417577dSAdrian Hunter static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1135a45c6cb8SMadhusudhan Chikkature {
1136a45c6cb8SMadhusudhan Chikkature 	struct mmc_data *data;
1137b417577dSAdrian Hunter 	int end_cmd = 0, end_trans = 0;
1138a2e77152SBalaji T K 	int error = 0;
1139a45c6cb8SMadhusudhan Chikkature 
1140a45c6cb8SMadhusudhan Chikkature 	data = host->data;
11418986d31bSVenkatraman S 	dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1142a45c6cb8SMadhusudhan Chikkature 
1143a7e96879SVenkatraman S 	if (status & ERR_EN) {
1144699b958bSAdrian Hunter 		omap_hsmmc_dbg_report_irq(host, status);
11454a694dc9SAdrian Hunter 
114624380dd4SRavikumar Kattekola 		if (status & (CTO_EN | CCRC_EN | CEB_EN))
1147a45c6cb8SMadhusudhan Chikkature 			end_cmd = 1;
1148408806f7SKishon Vijay Abraham I 		if (host->data || host->response_busy) {
1149408806f7SKishon Vijay Abraham I 			end_trans = !end_cmd;
1150408806f7SKishon Vijay Abraham I 			host->response_busy = 0;
1151408806f7SKishon Vijay Abraham I 		}
1152a7e96879SVenkatraman S 		if (status & (CTO_EN | DTO_EN))
115325e1897bSBalaji T K 			hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
11545027cd1eSVignesh R 		else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN |
11555027cd1eSVignesh R 				   BADA_EN))
115625e1897bSBalaji T K 			hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
115725e1897bSBalaji T K 
1158a2e77152SBalaji T K 		if (status & ACE_EN) {
1159a2e77152SBalaji T K 			u32 ac12;
1160a2e77152SBalaji T K 			ac12 = OMAP_HSMMC_READ(host->base, AC12);
1161a2e77152SBalaji T K 			if (!(ac12 & ACNE) && host->mrq->sbc) {
1162a2e77152SBalaji T K 				end_cmd = 1;
1163a2e77152SBalaji T K 				if (ac12 & ACTO)
1164a2e77152SBalaji T K 					error =  -ETIMEDOUT;
1165a2e77152SBalaji T K 				else if (ac12 & (ACCE | ACEB | ACIE))
1166a2e77152SBalaji T K 					error = -EILSEQ;
1167a2e77152SBalaji T K 				host->mrq->sbc->error = error;
1168a2e77152SBalaji T K 				hsmmc_command_incomplete(host, error, end_cmd);
1169a2e77152SBalaji T K 			}
1170a2e77152SBalaji T K 			dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
1171a2e77152SBalaji T K 		}
1172a45c6cb8SMadhusudhan Chikkature 	}
1173a45c6cb8SMadhusudhan Chikkature 
11747472bab2SFrancesco Lavra 	OMAP_HSMMC_WRITE(host->base, STAT, status);
1175a7e96879SVenkatraman S 	if (end_cmd || ((status & CC_EN) && host->cmd))
117670a3341aSDenis Karpov 		omap_hsmmc_cmd_done(host, host->cmd);
1177a7e96879SVenkatraman S 	if ((end_trans || (status & TC_EN)) && host->mrq)
117870a3341aSDenis Karpov 		omap_hsmmc_xfer_done(host, data);
1179b417577dSAdrian Hunter }
1180a45c6cb8SMadhusudhan Chikkature 
1181b417577dSAdrian Hunter /*
1182b417577dSAdrian Hunter  * MMC controller IRQ handler
1183b417577dSAdrian Hunter  */
1184b417577dSAdrian Hunter static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1185b417577dSAdrian Hunter {
1186b417577dSAdrian Hunter 	struct omap_hsmmc_host *host = dev_id;
1187b417577dSAdrian Hunter 	int status;
1188b417577dSAdrian Hunter 
1189b417577dSAdrian Hunter 	status = OMAP_HSMMC_READ(host->base, STAT);
11902cd3a2a5SAndreas Fenkart 	while (status & (INT_EN_MASK | CIRQ_EN)) {
11912cd3a2a5SAndreas Fenkart 		if (host->req_in_progress)
1192b417577dSAdrian Hunter 			omap_hsmmc_do_irq(host, status);
11931f6b9fa4SVenkatraman S 
11942cd3a2a5SAndreas Fenkart 		if (status & CIRQ_EN)
11952cd3a2a5SAndreas Fenkart 			mmc_signal_sdio_irq(host->mmc);
11962cd3a2a5SAndreas Fenkart 
1197b417577dSAdrian Hunter 		/* Flush posted write */
1198b417577dSAdrian Hunter 		status = OMAP_HSMMC_READ(host->base, STAT);
11991f6b9fa4SVenkatraman S 	}
12004dffd7a2SAdrian Hunter 
1201a45c6cb8SMadhusudhan Chikkature 	return IRQ_HANDLED;
1202a45c6cb8SMadhusudhan Chikkature }
1203a45c6cb8SMadhusudhan Chikkature 
120470a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host)
1205e13bb300SAdrian Hunter {
1206e13bb300SAdrian Hunter 	unsigned long i;
1207e13bb300SAdrian Hunter 
1208e13bb300SAdrian Hunter 	OMAP_HSMMC_WRITE(host->base, HCTL,
1209e13bb300SAdrian Hunter 			 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1210e13bb300SAdrian Hunter 	for (i = 0; i < loops_per_jiffy; i++) {
1211e13bb300SAdrian Hunter 		if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1212e13bb300SAdrian Hunter 			break;
1213e13bb300SAdrian Hunter 		cpu_relax();
1214e13bb300SAdrian Hunter 	}
1215e13bb300SAdrian Hunter }
1216e13bb300SAdrian Hunter 
1217a45c6cb8SMadhusudhan Chikkature /*
1218eb250826SDavid Brownell  * Switch MMC interface voltage ... only relevant for MMC1.
1219eb250826SDavid Brownell  *
1220eb250826SDavid Brownell  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1221eb250826SDavid Brownell  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1222eb250826SDavid Brownell  * Some chips, like eMMC ones, use internal transceivers.
1223a45c6cb8SMadhusudhan Chikkature  */
122470a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1225a45c6cb8SMadhusudhan Chikkature {
1226a45c6cb8SMadhusudhan Chikkature 	u32 reg_val = 0;
1227a45c6cb8SMadhusudhan Chikkature 	int ret;
1228a45c6cb8SMadhusudhan Chikkature 
1229a45c6cb8SMadhusudhan Chikkature 	/* Disable the clocks */
1230cd03d9a8SRajendra Nayak 	if (host->dbclk)
123194c18149SRajendra Nayak 		clk_disable_unprepare(host->dbclk);
1232a45c6cb8SMadhusudhan Chikkature 
1233a45c6cb8SMadhusudhan Chikkature 	/* Turn the power off */
12341ca4d359SAndreas Fenkart 	ret = omap_hsmmc_set_power(host, 0, 0);
1235a45c6cb8SMadhusudhan Chikkature 
1236a45c6cb8SMadhusudhan Chikkature 	/* Turn the power ON with given VDD 1.8 or 3.0v */
12372bec0893SAdrian Hunter 	if (!ret)
12381ca4d359SAndreas Fenkart 		ret = omap_hsmmc_set_power(host, 1, vdd);
1239cd03d9a8SRajendra Nayak 	if (host->dbclk)
124094c18149SRajendra Nayak 		clk_prepare_enable(host->dbclk);
12412bec0893SAdrian Hunter 
1242a45c6cb8SMadhusudhan Chikkature 	if (ret != 0)
1243a45c6cb8SMadhusudhan Chikkature 		goto err;
1244a45c6cb8SMadhusudhan Chikkature 
1245a45c6cb8SMadhusudhan Chikkature 	OMAP_HSMMC_WRITE(host->base, HCTL,
1246a45c6cb8SMadhusudhan Chikkature 		OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1247a45c6cb8SMadhusudhan Chikkature 	reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1248eb250826SDavid Brownell 
1249a45c6cb8SMadhusudhan Chikkature 	/*
1250a45c6cb8SMadhusudhan Chikkature 	 * If a MMC dual voltage card is detected, the set_ios fn calls
1251a45c6cb8SMadhusudhan Chikkature 	 * this fn with VDD bit set for 1.8V. Upon card removal from the
125270a3341aSDenis Karpov 	 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1253a45c6cb8SMadhusudhan Chikkature 	 *
1254eb250826SDavid Brownell 	 * Cope with a bit of slop in the range ... per data sheets:
1255eb250826SDavid Brownell 	 *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1256eb250826SDavid Brownell 	 *    but recommended values are 1.71V to 1.89V
1257eb250826SDavid Brownell 	 *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1258eb250826SDavid Brownell 	 *    but recommended values are 2.7V to 3.3V
1259eb250826SDavid Brownell 	 *
1260eb250826SDavid Brownell 	 * Board setup code shouldn't permit anything very out-of-range.
1261eb250826SDavid Brownell 	 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1262eb250826SDavid Brownell 	 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1263a45c6cb8SMadhusudhan Chikkature 	 */
1264eb250826SDavid Brownell 	if ((1 << vdd) <= MMC_VDD_23_24)
1265a45c6cb8SMadhusudhan Chikkature 		reg_val |= SDVS18;
1266eb250826SDavid Brownell 	else
1267eb250826SDavid Brownell 		reg_val |= SDVS30;
1268a45c6cb8SMadhusudhan Chikkature 
1269a45c6cb8SMadhusudhan Chikkature 	OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1270e13bb300SAdrian Hunter 	set_sd_bus_power(host);
1271a45c6cb8SMadhusudhan Chikkature 
1272a45c6cb8SMadhusudhan Chikkature 	return 0;
1273a45c6cb8SMadhusudhan Chikkature err:
1274b1e056aeSVenkatraman S 	dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1275a45c6cb8SMadhusudhan Chikkature 	return ret;
1276a45c6cb8SMadhusudhan Chikkature }
1277a45c6cb8SMadhusudhan Chikkature 
1278b62f6228SAdrian Hunter /* Protect the card while the cover is open */
1279b62f6228SAdrian Hunter static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1280b62f6228SAdrian Hunter {
1281b5cd43f0SAndreas Fenkart 	if (!host->get_cover_state)
1282b62f6228SAdrian Hunter 		return;
1283b62f6228SAdrian Hunter 
1284b62f6228SAdrian Hunter 	host->reqs_blocked = 0;
128580412ca8SAndreas Fenkart 	if (host->get_cover_state(host->dev)) {
1286b62f6228SAdrian Hunter 		if (host->protect_card) {
12872cecdf00SRajendra Nayak 			dev_info(host->dev, "%s: cover is closed, "
1288b62f6228SAdrian Hunter 					 "card is now accessible\n",
1289b62f6228SAdrian Hunter 					 mmc_hostname(host->mmc));
1290b62f6228SAdrian Hunter 			host->protect_card = 0;
1291b62f6228SAdrian Hunter 		}
1292b62f6228SAdrian Hunter 	} else {
1293b62f6228SAdrian Hunter 		if (!host->protect_card) {
12942cecdf00SRajendra Nayak 			dev_info(host->dev, "%s: cover is open, "
1295b62f6228SAdrian Hunter 					 "card is now inaccessible\n",
1296b62f6228SAdrian Hunter 					 mmc_hostname(host->mmc));
1297b62f6228SAdrian Hunter 			host->protect_card = 1;
1298b62f6228SAdrian Hunter 		}
1299b62f6228SAdrian Hunter 	}
1300b62f6228SAdrian Hunter }
1301b62f6228SAdrian Hunter 
1302a45c6cb8SMadhusudhan Chikkature /*
1303cde592cbSAndreas Fenkart  * irq handler when (cell-phone) cover is mounted/removed
1304cde592cbSAndreas Fenkart  */
1305cde592cbSAndreas Fenkart static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id)
1306cde592cbSAndreas Fenkart {
1307cde592cbSAndreas Fenkart 	struct omap_hsmmc_host *host = dev_id;
1308cde592cbSAndreas Fenkart 
1309cde592cbSAndreas Fenkart 	sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1310cde592cbSAndreas Fenkart 
1311cde592cbSAndreas Fenkart 	omap_hsmmc_protect_card(host);
1312cde592cbSAndreas Fenkart 	mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1313cde592cbSAndreas Fenkart 	return IRQ_HANDLED;
1314cde592cbSAndreas Fenkart }
1315cde592cbSAndreas Fenkart 
1316c5c98927SRussell King static void omap_hsmmc_dma_callback(void *param)
13170ccd76d4SJuha Yrjola {
1318c5c98927SRussell King 	struct omap_hsmmc_host *host = param;
1319c5c98927SRussell King 	struct dma_chan *chan;
1320770d7432SAdrian Hunter 	struct mmc_data *data;
1321c5c98927SRussell King 	int req_in_progress;
1322a45c6cb8SMadhusudhan Chikkature 
1323c5c98927SRussell King 	spin_lock_irq(&host->irq_lock);
1324b417577dSAdrian Hunter 	if (host->dma_ch < 0) {
1325c5c98927SRussell King 		spin_unlock_irq(&host->irq_lock);
1326a45c6cb8SMadhusudhan Chikkature 		return;
1327b417577dSAdrian Hunter 	}
1328a45c6cb8SMadhusudhan Chikkature 
1329770d7432SAdrian Hunter 	data = host->mrq->data;
1330c5c98927SRussell King 	chan = omap_hsmmc_get_dma_chan(host, data);
13319782aff8SPer Forlin 	if (!data->host_cookie)
1332c5c98927SRussell King 		dma_unmap_sg(chan->device->dev,
1333c5c98927SRussell King 			     data->sg, data->sg_len,
1334feeef096SHeiner Kallweit 			     mmc_get_dma_dir(data));
1335b417577dSAdrian Hunter 
1336b417577dSAdrian Hunter 	req_in_progress = host->req_in_progress;
1337a45c6cb8SMadhusudhan Chikkature 	host->dma_ch = -1;
1338c5c98927SRussell King 	spin_unlock_irq(&host->irq_lock);
1339b417577dSAdrian Hunter 
1340b417577dSAdrian Hunter 	/* If DMA has finished after TC, complete the request */
1341b417577dSAdrian Hunter 	if (!req_in_progress) {
1342b417577dSAdrian Hunter 		struct mmc_request *mrq = host->mrq;
1343b417577dSAdrian Hunter 
1344b417577dSAdrian Hunter 		host->mrq = NULL;
1345b417577dSAdrian Hunter 		mmc_request_done(host->mmc, mrq);
1346b417577dSAdrian Hunter 	}
1347a45c6cb8SMadhusudhan Chikkature }
1348a45c6cb8SMadhusudhan Chikkature 
13499782aff8SPer Forlin static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
13509782aff8SPer Forlin 				       struct mmc_data *data,
1351c5c98927SRussell King 				       struct omap_hsmmc_next *next,
135226b88520SRussell King 				       struct dma_chan *chan)
13539782aff8SPer Forlin {
13549782aff8SPer Forlin 	int dma_len;
13559782aff8SPer Forlin 
13569782aff8SPer Forlin 	if (!next && data->host_cookie &&
13579782aff8SPer Forlin 	    data->host_cookie != host->next_data.cookie) {
13582cecdf00SRajendra Nayak 		dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
13599782aff8SPer Forlin 		       " host->next_data.cookie %d\n",
13609782aff8SPer Forlin 		       __func__, data->host_cookie, host->next_data.cookie);
13619782aff8SPer Forlin 		data->host_cookie = 0;
13629782aff8SPer Forlin 	}
13639782aff8SPer Forlin 
13649782aff8SPer Forlin 	/* Check if next job is already prepared */
1365b38313d6SDan Carpenter 	if (next || data->host_cookie != host->next_data.cookie) {
136626b88520SRussell King 		dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1367feeef096SHeiner Kallweit 				     mmc_get_dma_dir(data));
13689782aff8SPer Forlin 
13699782aff8SPer Forlin 	} else {
13709782aff8SPer Forlin 		dma_len = host->next_data.dma_len;
13719782aff8SPer Forlin 		host->next_data.dma_len = 0;
13729782aff8SPer Forlin 	}
13739782aff8SPer Forlin 
13749782aff8SPer Forlin 
13759782aff8SPer Forlin 	if (dma_len == 0)
13769782aff8SPer Forlin 		return -EINVAL;
13779782aff8SPer Forlin 
13789782aff8SPer Forlin 	if (next) {
13799782aff8SPer Forlin 		next->dma_len = dma_len;
13809782aff8SPer Forlin 		data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
13819782aff8SPer Forlin 	} else
13829782aff8SPer Forlin 		host->dma_len = dma_len;
13839782aff8SPer Forlin 
13849782aff8SPer Forlin 	return 0;
13859782aff8SPer Forlin }
13869782aff8SPer Forlin 
1387a45c6cb8SMadhusudhan Chikkature /*
1388a45c6cb8SMadhusudhan Chikkature  * Routine to configure and start DMA for the MMC card
1389a45c6cb8SMadhusudhan Chikkature  */
13909d025334SBalaji T K static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
139170a3341aSDenis Karpov 					struct mmc_request *req)
1392a45c6cb8SMadhusudhan Chikkature {
139326b88520SRussell King 	struct dma_async_tx_descriptor *tx;
139426b88520SRussell King 	int ret = 0, i;
1395a45c6cb8SMadhusudhan Chikkature 	struct mmc_data *data = req->data;
1396c5c98927SRussell King 	struct dma_chan *chan;
1397e5789608SPeter Ujfalusi 	struct dma_slave_config cfg = {
1398e5789608SPeter Ujfalusi 		.src_addr = host->mapbase + OMAP_HSMMC_DATA,
1399e5789608SPeter Ujfalusi 		.dst_addr = host->mapbase + OMAP_HSMMC_DATA,
1400e5789608SPeter Ujfalusi 		.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1401e5789608SPeter Ujfalusi 		.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1402e5789608SPeter Ujfalusi 		.src_maxburst = data->blksz / 4,
1403e5789608SPeter Ujfalusi 		.dst_maxburst = data->blksz / 4,
1404e5789608SPeter Ujfalusi 	};
1405a45c6cb8SMadhusudhan Chikkature 
14060ccd76d4SJuha Yrjola 	/* Sanity check: all the SG entries must be aligned by block size. */
1407a3f406f8SJarkko Lavinen 	for (i = 0; i < data->sg_len; i++) {
14080ccd76d4SJuha Yrjola 		struct scatterlist *sgl;
14090ccd76d4SJuha Yrjola 
14100ccd76d4SJuha Yrjola 		sgl = data->sg + i;
14110ccd76d4SJuha Yrjola 		if (sgl->length % data->blksz)
14120ccd76d4SJuha Yrjola 			return -EINVAL;
14130ccd76d4SJuha Yrjola 	}
14140ccd76d4SJuha Yrjola 	if ((data->blksz % 4) != 0)
14150ccd76d4SJuha Yrjola 		/* REVISIT: The MMC buffer increments only when MSB is written.
14160ccd76d4SJuha Yrjola 		 * Return error for blksz which is non multiple of four.
14170ccd76d4SJuha Yrjola 		 */
14180ccd76d4SJuha Yrjola 		return -EINVAL;
14190ccd76d4SJuha Yrjola 
1420b417577dSAdrian Hunter 	BUG_ON(host->dma_ch != -1);
1421a45c6cb8SMadhusudhan Chikkature 
1422c5c98927SRussell King 	chan = omap_hsmmc_get_dma_chan(host, data);
1423c5c98927SRussell King 
1424c5c98927SRussell King 	ret = dmaengine_slave_config(chan, &cfg);
14259782aff8SPer Forlin 	if (ret)
14269782aff8SPer Forlin 		return ret;
1427a45c6cb8SMadhusudhan Chikkature 
142826b88520SRussell King 	ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1429c5c98927SRussell King 	if (ret)
1430c5c98927SRussell King 		return ret;
1431a45c6cb8SMadhusudhan Chikkature 
1432c5c98927SRussell King 	tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1433c5c98927SRussell King 		data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1434c5c98927SRussell King 		DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1435c5c98927SRussell King 	if (!tx) {
1436c5c98927SRussell King 		dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1437c5c98927SRussell King 		/* FIXME: cleanup */
1438c5c98927SRussell King 		return -1;
1439c5c98927SRussell King 	}
1440c5c98927SRussell King 
1441c5c98927SRussell King 	tx->callback = omap_hsmmc_dma_callback;
1442c5c98927SRussell King 	tx->callback_param = host;
1443c5c98927SRussell King 
1444c5c98927SRussell King 	/* Does not fail */
1445c5c98927SRussell King 	dmaengine_submit(tx);
1446c5c98927SRussell King 
144726b88520SRussell King 	host->dma_ch = 1;
1448c5c98927SRussell King 
1449a45c6cb8SMadhusudhan Chikkature 	return 0;
1450a45c6cb8SMadhusudhan Chikkature }
1451a45c6cb8SMadhusudhan Chikkature 
145270a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host,
1453a53210f5SRavikumar Kattekola 			     unsigned long long timeout_ns,
1454e2bf08d6SAdrian Hunter 			     unsigned int timeout_clks)
1455a45c6cb8SMadhusudhan Chikkature {
1456a53210f5SRavikumar Kattekola 	unsigned long long timeout = timeout_ns;
1457a53210f5SRavikumar Kattekola 	unsigned int cycle_ns;
1458a45c6cb8SMadhusudhan Chikkature 	uint32_t reg, clkd, dto = 0;
1459a45c6cb8SMadhusudhan Chikkature 
1460a45c6cb8SMadhusudhan Chikkature 	reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1461a45c6cb8SMadhusudhan Chikkature 	clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1462a45c6cb8SMadhusudhan Chikkature 	if (clkd == 0)
1463a45c6cb8SMadhusudhan Chikkature 		clkd = 1;
1464a45c6cb8SMadhusudhan Chikkature 
14656e3076c2SBalaji T K 	cycle_ns = 1000000000 / (host->clk_rate / clkd);
1466a53210f5SRavikumar Kattekola 	do_div(timeout, cycle_ns);
1467e2bf08d6SAdrian Hunter 	timeout += timeout_clks;
1468a45c6cb8SMadhusudhan Chikkature 	if (timeout) {
1469a45c6cb8SMadhusudhan Chikkature 		while ((timeout & 0x80000000) == 0) {
1470a45c6cb8SMadhusudhan Chikkature 			dto += 1;
1471a45c6cb8SMadhusudhan Chikkature 			timeout <<= 1;
1472a45c6cb8SMadhusudhan Chikkature 		}
1473a45c6cb8SMadhusudhan Chikkature 		dto = 31 - dto;
1474a45c6cb8SMadhusudhan Chikkature 		timeout <<= 1;
1475a45c6cb8SMadhusudhan Chikkature 		if (timeout && dto)
1476a45c6cb8SMadhusudhan Chikkature 			dto += 1;
1477a45c6cb8SMadhusudhan Chikkature 		if (dto >= 13)
1478a45c6cb8SMadhusudhan Chikkature 			dto -= 13;
1479a45c6cb8SMadhusudhan Chikkature 		else
1480a45c6cb8SMadhusudhan Chikkature 			dto = 0;
1481a45c6cb8SMadhusudhan Chikkature 		if (dto > 14)
1482a45c6cb8SMadhusudhan Chikkature 			dto = 14;
1483a45c6cb8SMadhusudhan Chikkature 	}
1484a45c6cb8SMadhusudhan Chikkature 
1485a45c6cb8SMadhusudhan Chikkature 	reg &= ~DTO_MASK;
1486a45c6cb8SMadhusudhan Chikkature 	reg |= dto << DTO_SHIFT;
1487a45c6cb8SMadhusudhan Chikkature 	OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1488a45c6cb8SMadhusudhan Chikkature }
1489a45c6cb8SMadhusudhan Chikkature 
14909d025334SBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
14919d025334SBalaji T K {
14929d025334SBalaji T K 	struct mmc_request *req = host->mrq;
14939d025334SBalaji T K 	struct dma_chan *chan;
14949d025334SBalaji T K 
14959d025334SBalaji T K 	if (!req->data)
14969d025334SBalaji T K 		return;
14979d025334SBalaji T K 	OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
14989d025334SBalaji T K 				| (req->data->blocks << 16));
14999d025334SBalaji T K 	set_data_timeout(host, req->data->timeout_ns,
15009d025334SBalaji T K 				req->data->timeout_clks);
15019d025334SBalaji T K 	chan = omap_hsmmc_get_dma_chan(host, req->data);
15029d025334SBalaji T K 	dma_async_issue_pending(chan);
15039d025334SBalaji T K }
15049d025334SBalaji T K 
1505a45c6cb8SMadhusudhan Chikkature /*
1506a45c6cb8SMadhusudhan Chikkature  * Configure block length for MMC/SD cards and initiate the transfer.
1507a45c6cb8SMadhusudhan Chikkature  */
1508a45c6cb8SMadhusudhan Chikkature static int
150970a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1510a45c6cb8SMadhusudhan Chikkature {
1511a45c6cb8SMadhusudhan Chikkature 	int ret;
1512a53210f5SRavikumar Kattekola 	unsigned long long timeout;
15138cc9a3e7SKishon Vijay Abraham I 
1514a45c6cb8SMadhusudhan Chikkature 	host->data = req->data;
1515a45c6cb8SMadhusudhan Chikkature 
1516a45c6cb8SMadhusudhan Chikkature 	if (req->data == NULL) {
1517a45c6cb8SMadhusudhan Chikkature 		OMAP_HSMMC_WRITE(host->base, BLK, 0);
15188cc9a3e7SKishon Vijay Abraham I 		if (req->cmd->flags & MMC_RSP_BUSY) {
15198cc9a3e7SKishon Vijay Abraham I 			timeout = req->cmd->busy_timeout * NSEC_PER_MSEC;
15208cc9a3e7SKishon Vijay Abraham I 
1521e2bf08d6SAdrian Hunter 			/*
1522e2bf08d6SAdrian Hunter 			 * Set an arbitrary 100ms data timeout for commands with
15238cc9a3e7SKishon Vijay Abraham I 			 * busy signal and no indication of busy_timeout.
1524e2bf08d6SAdrian Hunter 			 */
15258cc9a3e7SKishon Vijay Abraham I 			if (!timeout)
15268cc9a3e7SKishon Vijay Abraham I 				timeout = 100000000U;
15278cc9a3e7SKishon Vijay Abraham I 
15288cc9a3e7SKishon Vijay Abraham I 			set_data_timeout(host, timeout, 0);
15298cc9a3e7SKishon Vijay Abraham I 		}
1530a45c6cb8SMadhusudhan Chikkature 		return 0;
1531a45c6cb8SMadhusudhan Chikkature 	}
1532a45c6cb8SMadhusudhan Chikkature 
1533a45c6cb8SMadhusudhan Chikkature 	if (host->use_dma) {
15349d025334SBalaji T K 		ret = omap_hsmmc_setup_dma_transfer(host, req);
1535a45c6cb8SMadhusudhan Chikkature 		if (ret != 0) {
1536b1e056aeSVenkatraman S 			dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1537a45c6cb8SMadhusudhan Chikkature 			return ret;
1538a45c6cb8SMadhusudhan Chikkature 		}
1539a45c6cb8SMadhusudhan Chikkature 	}
1540a45c6cb8SMadhusudhan Chikkature 	return 0;
1541a45c6cb8SMadhusudhan Chikkature }
1542a45c6cb8SMadhusudhan Chikkature 
15439782aff8SPer Forlin static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
15449782aff8SPer Forlin 				int err)
15459782aff8SPer Forlin {
15469782aff8SPer Forlin 	struct omap_hsmmc_host *host = mmc_priv(mmc);
15479782aff8SPer Forlin 	struct mmc_data *data = mrq->data;
15489782aff8SPer Forlin 
154926b88520SRussell King 	if (host->use_dma && data->host_cookie) {
1550c5c98927SRussell King 		struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1551c5c98927SRussell King 
155226b88520SRussell King 		dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1553feeef096SHeiner Kallweit 			     mmc_get_dma_dir(data));
15549782aff8SPer Forlin 		data->host_cookie = 0;
15559782aff8SPer Forlin 	}
15569782aff8SPer Forlin }
15579782aff8SPer Forlin 
1558d3c6aac3SLinus Walleij static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
15599782aff8SPer Forlin {
15609782aff8SPer Forlin 	struct omap_hsmmc_host *host = mmc_priv(mmc);
15619782aff8SPer Forlin 
15629782aff8SPer Forlin 	if (mrq->data->host_cookie) {
15639782aff8SPer Forlin 		mrq->data->host_cookie = 0;
15649782aff8SPer Forlin 		return ;
15659782aff8SPer Forlin 	}
15669782aff8SPer Forlin 
1567c5c98927SRussell King 	if (host->use_dma) {
1568c5c98927SRussell King 		struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1569c5c98927SRussell King 
15709782aff8SPer Forlin 		if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
157126b88520SRussell King 						&host->next_data, c))
15729782aff8SPer Forlin 			mrq->data->host_cookie = 0;
15739782aff8SPer Forlin 	}
1574c5c98927SRussell King }
15759782aff8SPer Forlin 
1576a45c6cb8SMadhusudhan Chikkature /*
1577a45c6cb8SMadhusudhan Chikkature  * Request function. for read/write operation
1578a45c6cb8SMadhusudhan Chikkature  */
157970a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1580a45c6cb8SMadhusudhan Chikkature {
158170a3341aSDenis Karpov 	struct omap_hsmmc_host *host = mmc_priv(mmc);
1582a3f406f8SJarkko Lavinen 	int err;
1583a45c6cb8SMadhusudhan Chikkature 
1584b417577dSAdrian Hunter 	BUG_ON(host->req_in_progress);
1585b417577dSAdrian Hunter 	BUG_ON(host->dma_ch != -1);
1586b62f6228SAdrian Hunter 	if (host->protect_card) {
1587b62f6228SAdrian Hunter 		if (host->reqs_blocked < 3) {
1588b62f6228SAdrian Hunter 			/*
1589b62f6228SAdrian Hunter 			 * Ensure the controller is left in a consistent
1590b62f6228SAdrian Hunter 			 * state by resetting the command and data state
1591b62f6228SAdrian Hunter 			 * machines.
1592b62f6228SAdrian Hunter 			 */
1593b62f6228SAdrian Hunter 			omap_hsmmc_reset_controller_fsm(host, SRD);
1594b62f6228SAdrian Hunter 			omap_hsmmc_reset_controller_fsm(host, SRC);
1595b62f6228SAdrian Hunter 			host->reqs_blocked += 1;
1596b62f6228SAdrian Hunter 		}
1597b62f6228SAdrian Hunter 		req->cmd->error = -EBADF;
1598b62f6228SAdrian Hunter 		if (req->data)
1599b62f6228SAdrian Hunter 			req->data->error = -EBADF;
1600b417577dSAdrian Hunter 		req->cmd->retries = 0;
1601b62f6228SAdrian Hunter 		mmc_request_done(mmc, req);
1602b62f6228SAdrian Hunter 		return;
1603b62f6228SAdrian Hunter 	} else if (host->reqs_blocked)
1604b62f6228SAdrian Hunter 		host->reqs_blocked = 0;
1605a45c6cb8SMadhusudhan Chikkature 	WARN_ON(host->mrq != NULL);
1606a45c6cb8SMadhusudhan Chikkature 	host->mrq = req;
16076e3076c2SBalaji T K 	host->clk_rate = clk_get_rate(host->fclk);
160870a3341aSDenis Karpov 	err = omap_hsmmc_prepare_data(host, req);
1609a3f406f8SJarkko Lavinen 	if (err) {
1610a3f406f8SJarkko Lavinen 		req->cmd->error = err;
1611a3f406f8SJarkko Lavinen 		if (req->data)
1612a3f406f8SJarkko Lavinen 			req->data->error = err;
1613a3f406f8SJarkko Lavinen 		host->mrq = NULL;
1614a3f406f8SJarkko Lavinen 		mmc_request_done(mmc, req);
1615a3f406f8SJarkko Lavinen 		return;
1616a3f406f8SJarkko Lavinen 	}
1617a2e77152SBalaji T K 	if (req->sbc && !(host->flags & AUTO_CMD23)) {
1618bf129e1cSBalaji T K 		omap_hsmmc_start_command(host, req->sbc, NULL);
1619bf129e1cSBalaji T K 		return;
1620bf129e1cSBalaji T K 	}
1621a3f406f8SJarkko Lavinen 
16229d025334SBalaji T K 	omap_hsmmc_start_dma_transfer(host);
162370a3341aSDenis Karpov 	omap_hsmmc_start_command(host, req->cmd, req->data);
1624a45c6cb8SMadhusudhan Chikkature }
1625a45c6cb8SMadhusudhan Chikkature 
1626a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */
162770a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1628a45c6cb8SMadhusudhan Chikkature {
162970a3341aSDenis Karpov 	struct omap_hsmmc_host *host = mmc_priv(mmc);
1630a3621465SAdrian Hunter 	int do_send_init_stream = 0;
1631a45c6cb8SMadhusudhan Chikkature 
1632a3621465SAdrian Hunter 	if (ios->power_mode != host->power_mode) {
1633a45c6cb8SMadhusudhan Chikkature 		switch (ios->power_mode) {
1634a45c6cb8SMadhusudhan Chikkature 		case MMC_POWER_OFF:
16351ca4d359SAndreas Fenkart 			omap_hsmmc_set_power(host, 0, 0);
1636a45c6cb8SMadhusudhan Chikkature 			break;
1637a45c6cb8SMadhusudhan Chikkature 		case MMC_POWER_UP:
16381ca4d359SAndreas Fenkart 			omap_hsmmc_set_power(host, 1, ios->vdd);
1639a45c6cb8SMadhusudhan Chikkature 			break;
1640a3621465SAdrian Hunter 		case MMC_POWER_ON:
1641a3621465SAdrian Hunter 			do_send_init_stream = 1;
1642a3621465SAdrian Hunter 			break;
1643a3621465SAdrian Hunter 		}
1644a3621465SAdrian Hunter 		host->power_mode = ios->power_mode;
1645a45c6cb8SMadhusudhan Chikkature 	}
1646a45c6cb8SMadhusudhan Chikkature 
1647dd498effSDenis Karpov 	/* FIXME: set registers based only on changes to ios */
1648dd498effSDenis Karpov 
16493796fb8aSAndy Shevchenko 	omap_hsmmc_set_bus_width(host);
1650a45c6cb8SMadhusudhan Chikkature 
16514621d5f8SKishore Kadiyala 	if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1652eb250826SDavid Brownell 		/* Only MMC1 can interface at 3V without some flavor
1653eb250826SDavid Brownell 		 * of external transceiver; but they all handle 1.8V.
1654eb250826SDavid Brownell 		 */
1655a45c6cb8SMadhusudhan Chikkature 		if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
16562cf171cbSBalaji T K 			(ios->vdd == DUAL_VOLT_OCR_BIT)) {
1657a45c6cb8SMadhusudhan Chikkature 				/*
1658a45c6cb8SMadhusudhan Chikkature 				 * The mmc_select_voltage fn of the core does
1659a45c6cb8SMadhusudhan Chikkature 				 * not seem to set the power_mode to
1660a45c6cb8SMadhusudhan Chikkature 				 * MMC_POWER_UP upon recalculating the voltage.
1661a45c6cb8SMadhusudhan Chikkature 				 * vdd 1.8v.
1662a45c6cb8SMadhusudhan Chikkature 				 */
166370a3341aSDenis Karpov 			if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1664a45c6cb8SMadhusudhan Chikkature 				dev_dbg(mmc_dev(host->mmc),
1665a45c6cb8SMadhusudhan Chikkature 						"Switch operation failed\n");
1666a45c6cb8SMadhusudhan Chikkature 		}
1667a45c6cb8SMadhusudhan Chikkature 	}
1668a45c6cb8SMadhusudhan Chikkature 
16695934df2fSAndy Shevchenko 	omap_hsmmc_set_clock(host);
1670a45c6cb8SMadhusudhan Chikkature 
1671a3621465SAdrian Hunter 	if (do_send_init_stream)
1672a45c6cb8SMadhusudhan Chikkature 		send_init_stream(host);
1673a45c6cb8SMadhusudhan Chikkature 
16743796fb8aSAndy Shevchenko 	omap_hsmmc_set_bus_mode(host);
1675a45c6cb8SMadhusudhan Chikkature }
1676a45c6cb8SMadhusudhan Chikkature 
1677a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1678a45c6cb8SMadhusudhan Chikkature {
167970a3341aSDenis Karpov 	struct omap_hsmmc_host *host = mmc_priv(mmc);
1680a45c6cb8SMadhusudhan Chikkature 
1681b5cd43f0SAndreas Fenkart 	if (!host->card_detect)
1682a45c6cb8SMadhusudhan Chikkature 		return -ENOSYS;
168380412ca8SAndreas Fenkart 	return host->card_detect(host->dev);
1684a45c6cb8SMadhusudhan Chikkature }
1685a45c6cb8SMadhusudhan Chikkature 
16864816858cSGrazvydas Ignotas static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
16874816858cSGrazvydas Ignotas {
16884816858cSGrazvydas Ignotas 	struct omap_hsmmc_host *host = mmc_priv(mmc);
16894816858cSGrazvydas Ignotas 
1690326119c9SAndreas Fenkart 	if (mmc_pdata(host)->init_card)
1691326119c9SAndreas Fenkart 		mmc_pdata(host)->init_card(card);
16924816858cSGrazvydas Ignotas }
16934816858cSGrazvydas Ignotas 
16942cd3a2a5SAndreas Fenkart static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
16952cd3a2a5SAndreas Fenkart {
16962cd3a2a5SAndreas Fenkart 	struct omap_hsmmc_host *host = mmc_priv(mmc);
16975a52b08bSBalaji T K 	u32 irq_mask, con;
16982cd3a2a5SAndreas Fenkart 	unsigned long flags;
16992cd3a2a5SAndreas Fenkart 
17002cd3a2a5SAndreas Fenkart 	spin_lock_irqsave(&host->irq_lock, flags);
17012cd3a2a5SAndreas Fenkart 
17025a52b08bSBalaji T K 	con = OMAP_HSMMC_READ(host->base, CON);
17032cd3a2a5SAndreas Fenkart 	irq_mask = OMAP_HSMMC_READ(host->base, ISE);
17042cd3a2a5SAndreas Fenkart 	if (enable) {
17052cd3a2a5SAndreas Fenkart 		host->flags |= HSMMC_SDIO_IRQ_ENABLED;
17062cd3a2a5SAndreas Fenkart 		irq_mask |= CIRQ_EN;
17075a52b08bSBalaji T K 		con |= CTPL | CLKEXTFREE;
17082cd3a2a5SAndreas Fenkart 	} else {
17092cd3a2a5SAndreas Fenkart 		host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
17102cd3a2a5SAndreas Fenkart 		irq_mask &= ~CIRQ_EN;
17115a52b08bSBalaji T K 		con &= ~(CTPL | CLKEXTFREE);
17122cd3a2a5SAndreas Fenkart 	}
17135a52b08bSBalaji T K 	OMAP_HSMMC_WRITE(host->base, CON, con);
17142cd3a2a5SAndreas Fenkart 	OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
17152cd3a2a5SAndreas Fenkart 
17162cd3a2a5SAndreas Fenkart 	/*
17172cd3a2a5SAndreas Fenkart 	 * if enable, piggy back detection on current request
17182cd3a2a5SAndreas Fenkart 	 * but always disable immediately
17192cd3a2a5SAndreas Fenkart 	 */
17202cd3a2a5SAndreas Fenkart 	if (!host->req_in_progress || !enable)
17212cd3a2a5SAndreas Fenkart 		OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
17222cd3a2a5SAndreas Fenkart 
17232cd3a2a5SAndreas Fenkart 	/* flush posted write */
17242cd3a2a5SAndreas Fenkart 	OMAP_HSMMC_READ(host->base, IE);
17252cd3a2a5SAndreas Fenkart 
17262cd3a2a5SAndreas Fenkart 	spin_unlock_irqrestore(&host->irq_lock, flags);
17272cd3a2a5SAndreas Fenkart }
17282cd3a2a5SAndreas Fenkart 
17292cd3a2a5SAndreas Fenkart static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
17302cd3a2a5SAndreas Fenkart {
17312cd3a2a5SAndreas Fenkart 	int ret;
17322cd3a2a5SAndreas Fenkart 
17332cd3a2a5SAndreas Fenkart 	/*
17342cd3a2a5SAndreas Fenkart 	 * For omaps with wake-up path, wakeirq will be irq from pinctrl and
17352cd3a2a5SAndreas Fenkart 	 * for other omaps, wakeirq will be from GPIO (dat line remuxed to
17362cd3a2a5SAndreas Fenkart 	 * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
17372cd3a2a5SAndreas Fenkart 	 * with functional clock disabled.
17382cd3a2a5SAndreas Fenkart 	 */
17392cd3a2a5SAndreas Fenkart 	if (!host->dev->of_node || !host->wake_irq)
17402cd3a2a5SAndreas Fenkart 		return -ENODEV;
17412cd3a2a5SAndreas Fenkart 
17425b83b223STony Lindgren 	ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq);
17432cd3a2a5SAndreas Fenkart 	if (ret) {
17442cd3a2a5SAndreas Fenkart 		dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
17452cd3a2a5SAndreas Fenkart 		goto err;
17462cd3a2a5SAndreas Fenkart 	}
17472cd3a2a5SAndreas Fenkart 
17482cd3a2a5SAndreas Fenkart 	/*
17492cd3a2a5SAndreas Fenkart 	 * Some omaps don't have wake-up path from deeper idle states
17502cd3a2a5SAndreas Fenkart 	 * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
17512cd3a2a5SAndreas Fenkart 	 */
17522cd3a2a5SAndreas Fenkart 	if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
1753455e5cd6SAndreas Fenkart 		struct pinctrl *p = devm_pinctrl_get(host->dev);
1754ec5ab893SDan Carpenter 		if (IS_ERR(p)) {
1755ec5ab893SDan Carpenter 			ret = PTR_ERR(p);
1756455e5cd6SAndreas Fenkart 			goto err_free_irq;
1757455e5cd6SAndreas Fenkart 		}
1758455e5cd6SAndreas Fenkart 		if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) {
1759455e5cd6SAndreas Fenkart 			dev_info(host->dev, "missing default pinctrl state\n");
1760455e5cd6SAndreas Fenkart 			devm_pinctrl_put(p);
1761455e5cd6SAndreas Fenkart 			ret = -EINVAL;
1762455e5cd6SAndreas Fenkart 			goto err_free_irq;
1763455e5cd6SAndreas Fenkart 		}
1764455e5cd6SAndreas Fenkart 
1765455e5cd6SAndreas Fenkart 		if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
1766455e5cd6SAndreas Fenkart 			dev_info(host->dev, "missing idle pinctrl state\n");
1767455e5cd6SAndreas Fenkart 			devm_pinctrl_put(p);
1768455e5cd6SAndreas Fenkart 			ret = -EINVAL;
1769455e5cd6SAndreas Fenkart 			goto err_free_irq;
1770455e5cd6SAndreas Fenkart 		}
1771455e5cd6SAndreas Fenkart 		devm_pinctrl_put(p);
17722cd3a2a5SAndreas Fenkart 	}
17732cd3a2a5SAndreas Fenkart 
17745a52b08bSBalaji T K 	OMAP_HSMMC_WRITE(host->base, HCTL,
17755a52b08bSBalaji T K 			 OMAP_HSMMC_READ(host->base, HCTL) | IWE);
17762cd3a2a5SAndreas Fenkart 	return 0;
17772cd3a2a5SAndreas Fenkart 
1778455e5cd6SAndreas Fenkart err_free_irq:
17795b83b223STony Lindgren 	dev_pm_clear_wake_irq(host->dev);
17802cd3a2a5SAndreas Fenkart err:
17812cd3a2a5SAndreas Fenkart 	dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
17822cd3a2a5SAndreas Fenkart 	host->wake_irq = 0;
17832cd3a2a5SAndreas Fenkart 	return ret;
17842cd3a2a5SAndreas Fenkart }
17852cd3a2a5SAndreas Fenkart 
178670a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
17871b331e69SKim Kyuwon {
17881b331e69SKim Kyuwon 	u32 hctl, capa, value;
17891b331e69SKim Kyuwon 
17901b331e69SKim Kyuwon 	/* Only MMC1 supports 3.0V */
17914621d5f8SKishore Kadiyala 	if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
17921b331e69SKim Kyuwon 		hctl = SDVS30;
17931b331e69SKim Kyuwon 		capa = VS30 | VS18;
17941b331e69SKim Kyuwon 	} else {
17951b331e69SKim Kyuwon 		hctl = SDVS18;
17961b331e69SKim Kyuwon 		capa = VS18;
17971b331e69SKim Kyuwon 	}
17981b331e69SKim Kyuwon 
17991b331e69SKim Kyuwon 	value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
18001b331e69SKim Kyuwon 	OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
18011b331e69SKim Kyuwon 
18021b331e69SKim Kyuwon 	value = OMAP_HSMMC_READ(host->base, CAPA);
18031b331e69SKim Kyuwon 	OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
18041b331e69SKim Kyuwon 
18051b331e69SKim Kyuwon 	/* Set SD bus power bit */
1806e13bb300SAdrian Hunter 	set_sd_bus_power(host);
18071b331e69SKim Kyuwon }
18081b331e69SKim Kyuwon 
1809afd8c29dSKuninori Morimoto static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
1810afd8c29dSKuninori Morimoto 				     unsigned int direction, int blk_size)
1811afd8c29dSKuninori Morimoto {
1812afd8c29dSKuninori Morimoto 	/* This controller can't do multiblock reads due to hw bugs */
1813afd8c29dSKuninori Morimoto 	if (direction == MMC_DATA_READ)
1814afd8c29dSKuninori Morimoto 		return 1;
1815afd8c29dSKuninori Morimoto 
1816afd8c29dSKuninori Morimoto 	return blk_size;
1817afd8c29dSKuninori Morimoto }
1818afd8c29dSKuninori Morimoto 
1819afd8c29dSKuninori Morimoto static struct mmc_host_ops omap_hsmmc_ops = {
18209782aff8SPer Forlin 	.post_req = omap_hsmmc_post_req,
18219782aff8SPer Forlin 	.pre_req = omap_hsmmc_pre_req,
182270a3341aSDenis Karpov 	.request = omap_hsmmc_request,
182370a3341aSDenis Karpov 	.set_ios = omap_hsmmc_set_ios,
1824dd498effSDenis Karpov 	.get_cd = omap_hsmmc_get_cd,
1825a49d8353SAndreas Fenkart 	.get_ro = mmc_gpio_get_ro,
18264816858cSGrazvydas Ignotas 	.init_card = omap_hsmmc_init_card,
18272cd3a2a5SAndreas Fenkart 	.enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
1828dd498effSDenis Karpov };
1829dd498effSDenis Karpov 
1830d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS
1831d900f712SDenis Karpov 
183270a3341aSDenis Karpov static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1833d900f712SDenis Karpov {
1834d900f712SDenis Karpov 	struct mmc_host *mmc = s->private;
183570a3341aSDenis Karpov 	struct omap_hsmmc_host *host = mmc_priv(mmc);
183611dd62a7SDenis Karpov 
1837bb0635f0SAndreas Fenkart 	seq_printf(s, "mmc%d:\n", mmc->index);
1838bb0635f0SAndreas Fenkart 	seq_printf(s, "sdio irq mode\t%s\n",
1839bb0635f0SAndreas Fenkart 		   (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
1840bb0635f0SAndreas Fenkart 
1841bb0635f0SAndreas Fenkart 	if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1842bb0635f0SAndreas Fenkart 		seq_printf(s, "sdio irq \t%s\n",
1843bb0635f0SAndreas Fenkart 			   (host->flags & HSMMC_SDIO_IRQ_ENABLED) ?  "enabled"
1844bb0635f0SAndreas Fenkart 			   : "disabled");
1845bb0635f0SAndreas Fenkart 	}
1846bb0635f0SAndreas Fenkart 	seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
18475e2ea617SAdrian Hunter 
1848fa4aa2d4SBalaji T K 	pm_runtime_get_sync(host->dev);
1849bb0635f0SAndreas Fenkart 	seq_puts(s, "\nregs:\n");
1850d900f712SDenis Karpov 	seq_printf(s, "CON:\t\t0x%08x\n",
1851d900f712SDenis Karpov 			OMAP_HSMMC_READ(host->base, CON));
1852bb0635f0SAndreas Fenkart 	seq_printf(s, "PSTATE:\t\t0x%08x\n",
1853bb0635f0SAndreas Fenkart 		   OMAP_HSMMC_READ(host->base, PSTATE));
1854d900f712SDenis Karpov 	seq_printf(s, "HCTL:\t\t0x%08x\n",
1855d900f712SDenis Karpov 			OMAP_HSMMC_READ(host->base, HCTL));
1856d900f712SDenis Karpov 	seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1857d900f712SDenis Karpov 			OMAP_HSMMC_READ(host->base, SYSCTL));
1858d900f712SDenis Karpov 	seq_printf(s, "IE:\t\t0x%08x\n",
1859d900f712SDenis Karpov 			OMAP_HSMMC_READ(host->base, IE));
1860d900f712SDenis Karpov 	seq_printf(s, "ISE:\t\t0x%08x\n",
1861d900f712SDenis Karpov 			OMAP_HSMMC_READ(host->base, ISE));
1862d900f712SDenis Karpov 	seq_printf(s, "CAPA:\t\t0x%08x\n",
1863d900f712SDenis Karpov 			OMAP_HSMMC_READ(host->base, CAPA));
18645e2ea617SAdrian Hunter 
1865fa4aa2d4SBalaji T K 	pm_runtime_mark_last_busy(host->dev);
1866fa4aa2d4SBalaji T K 	pm_runtime_put_autosuspend(host->dev);
1867dd498effSDenis Karpov 
1868d900f712SDenis Karpov 	return 0;
1869d900f712SDenis Karpov }
1870d900f712SDenis Karpov 
187170a3341aSDenis Karpov static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1872d900f712SDenis Karpov {
187370a3341aSDenis Karpov 	return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1874d900f712SDenis Karpov }
1875d900f712SDenis Karpov 
1876d900f712SDenis Karpov static const struct file_operations mmc_regs_fops = {
187770a3341aSDenis Karpov 	.open           = omap_hsmmc_regs_open,
1878d900f712SDenis Karpov 	.read           = seq_read,
1879d900f712SDenis Karpov 	.llseek         = seq_lseek,
1880d900f712SDenis Karpov 	.release        = single_release,
1881d900f712SDenis Karpov };
1882d900f712SDenis Karpov 
188370a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1884d900f712SDenis Karpov {
1885d900f712SDenis Karpov 	if (mmc->debugfs_root)
1886d900f712SDenis Karpov 		debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1887d900f712SDenis Karpov 			mmc, &mmc_regs_fops);
1888d900f712SDenis Karpov }
1889d900f712SDenis Karpov 
1890d900f712SDenis Karpov #else
1891d900f712SDenis Karpov 
189270a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1893d900f712SDenis Karpov {
1894d900f712SDenis Karpov }
1895d900f712SDenis Karpov 
1896d900f712SDenis Karpov #endif
1897d900f712SDenis Karpov 
189846856a68SRajendra Nayak #ifdef CONFIG_OF
189959445b10SNishanth Menon static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
190059445b10SNishanth Menon 	/* See 35xx errata 2.1.1.128 in SPRZ278F */
190159445b10SNishanth Menon 	.controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
190259445b10SNishanth Menon };
190359445b10SNishanth Menon 
190459445b10SNishanth Menon static const struct omap_mmc_of_data omap4_mmc_of_data = {
190559445b10SNishanth Menon 	.reg_offset = 0x100,
190659445b10SNishanth Menon };
19072cd3a2a5SAndreas Fenkart static const struct omap_mmc_of_data am33xx_mmc_of_data = {
19082cd3a2a5SAndreas Fenkart 	.reg_offset = 0x100,
19092cd3a2a5SAndreas Fenkart 	.controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
19102cd3a2a5SAndreas Fenkart };
191146856a68SRajendra Nayak 
191246856a68SRajendra Nayak static const struct of_device_id omap_mmc_of_match[] = {
191346856a68SRajendra Nayak 	{
191446856a68SRajendra Nayak 		.compatible = "ti,omap2-hsmmc",
191546856a68SRajendra Nayak 	},
191646856a68SRajendra Nayak 	{
191759445b10SNishanth Menon 		.compatible = "ti,omap3-pre-es3-hsmmc",
191859445b10SNishanth Menon 		.data = &omap3_pre_es3_mmc_of_data,
191959445b10SNishanth Menon 	},
192059445b10SNishanth Menon 	{
192146856a68SRajendra Nayak 		.compatible = "ti,omap3-hsmmc",
192246856a68SRajendra Nayak 	},
192346856a68SRajendra Nayak 	{
192446856a68SRajendra Nayak 		.compatible = "ti,omap4-hsmmc",
192559445b10SNishanth Menon 		.data = &omap4_mmc_of_data,
192646856a68SRajendra Nayak 	},
19272cd3a2a5SAndreas Fenkart 	{
19282cd3a2a5SAndreas Fenkart 		.compatible = "ti,am33xx-hsmmc",
19292cd3a2a5SAndreas Fenkart 		.data = &am33xx_mmc_of_data,
19302cd3a2a5SAndreas Fenkart 	},
193146856a68SRajendra Nayak 	{},
1932b6d085f6SChris Ball };
193346856a68SRajendra Nayak MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
193446856a68SRajendra Nayak 
193555143438SAndreas Fenkart static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
193646856a68SRajendra Nayak {
1937db863d89STony Lindgren 	struct omap_hsmmc_platform_data *pdata, *legacy;
193846856a68SRajendra Nayak 	struct device_node *np = dev->of_node;
193946856a68SRajendra Nayak 
194046856a68SRajendra Nayak 	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
194146856a68SRajendra Nayak 	if (!pdata)
194219df45bcSBalaji T K 		return ERR_PTR(-ENOMEM); /* out of memory */
194346856a68SRajendra Nayak 
1944db863d89STony Lindgren 	legacy = dev_get_platdata(dev);
1945db863d89STony Lindgren 	if (legacy && legacy->name)
1946db863d89STony Lindgren 		pdata->name = legacy->name;
1947db863d89STony Lindgren 
194846856a68SRajendra Nayak 	if (of_find_property(np, "ti,dual-volt", NULL))
194946856a68SRajendra Nayak 		pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
195046856a68SRajendra Nayak 
1951b7a5646fSAndreas Fenkart 	pdata->gpio_cd = -EINVAL;
1952b7a5646fSAndreas Fenkart 	pdata->gpio_cod = -EINVAL;
1953fdb9de12SNeilBrown 	pdata->gpio_wp = -EINVAL;
195446856a68SRajendra Nayak 
195546856a68SRajendra Nayak 	if (of_find_property(np, "ti,non-removable", NULL)) {
1956326119c9SAndreas Fenkart 		pdata->nonremovable = true;
1957326119c9SAndreas Fenkart 		pdata->no_regulator_off_init = true;
195846856a68SRajendra Nayak 	}
195946856a68SRajendra Nayak 
196046856a68SRajendra Nayak 	if (of_find_property(np, "ti,needs-special-reset", NULL))
1961326119c9SAndreas Fenkart 		pdata->features |= HSMMC_HAS_UPDATED_RESET;
196246856a68SRajendra Nayak 
1963cd587096SHebbar, Gururaja 	if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
1964326119c9SAndreas Fenkart 		pdata->features |= HSMMC_HAS_HSPE_SUPPORT;
1965cd587096SHebbar, Gururaja 
196646856a68SRajendra Nayak 	return pdata;
196746856a68SRajendra Nayak }
196846856a68SRajendra Nayak #else
196955143438SAndreas Fenkart static inline struct omap_hsmmc_platform_data
197046856a68SRajendra Nayak 			*of_get_hsmmc_pdata(struct device *dev)
197146856a68SRajendra Nayak {
197219df45bcSBalaji T K 	return ERR_PTR(-EINVAL);
197346856a68SRajendra Nayak }
197446856a68SRajendra Nayak #endif
197546856a68SRajendra Nayak 
1976c3be1efdSBill Pemberton static int omap_hsmmc_probe(struct platform_device *pdev)
1977a45c6cb8SMadhusudhan Chikkature {
197855143438SAndreas Fenkart 	struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
1979a45c6cb8SMadhusudhan Chikkature 	struct mmc_host *mmc;
198070a3341aSDenis Karpov 	struct omap_hsmmc_host *host = NULL;
1981a45c6cb8SMadhusudhan Chikkature 	struct resource *res;
1982db0fefc5SAdrian Hunter 	int ret, irq;
198346856a68SRajendra Nayak 	const struct of_device_id *match;
198459445b10SNishanth Menon 	const struct omap_mmc_of_data *data;
198577fae219SBalaji T K 	void __iomem *base;
198646856a68SRajendra Nayak 
198746856a68SRajendra Nayak 	match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
198846856a68SRajendra Nayak 	if (match) {
198946856a68SRajendra Nayak 		pdata = of_get_hsmmc_pdata(&pdev->dev);
1990dc642c28SJan Luebbe 
1991dc642c28SJan Luebbe 		if (IS_ERR(pdata))
1992dc642c28SJan Luebbe 			return PTR_ERR(pdata);
1993dc642c28SJan Luebbe 
199446856a68SRajendra Nayak 		if (match->data) {
199559445b10SNishanth Menon 			data = match->data;
199659445b10SNishanth Menon 			pdata->reg_offset = data->reg_offset;
199759445b10SNishanth Menon 			pdata->controller_flags |= data->controller_flags;
199846856a68SRajendra Nayak 		}
199946856a68SRajendra Nayak 	}
2000a45c6cb8SMadhusudhan Chikkature 
2001a45c6cb8SMadhusudhan Chikkature 	if (pdata == NULL) {
2002a45c6cb8SMadhusudhan Chikkature 		dev_err(&pdev->dev, "Platform Data is missing\n");
2003a45c6cb8SMadhusudhan Chikkature 		return -ENXIO;
2004a45c6cb8SMadhusudhan Chikkature 	}
2005a45c6cb8SMadhusudhan Chikkature 
2006a45c6cb8SMadhusudhan Chikkature 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2007a45c6cb8SMadhusudhan Chikkature 	irq = platform_get_irq(pdev, 0);
2008a45c6cb8SMadhusudhan Chikkature 	if (res == NULL || irq < 0)
2009a45c6cb8SMadhusudhan Chikkature 		return -ENXIO;
2010a45c6cb8SMadhusudhan Chikkature 
201177fae219SBalaji T K 	base = devm_ioremap_resource(&pdev->dev, res);
201277fae219SBalaji T K 	if (IS_ERR(base))
201377fae219SBalaji T K 		return PTR_ERR(base);
2014a45c6cb8SMadhusudhan Chikkature 
201570a3341aSDenis Karpov 	mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
2016a45c6cb8SMadhusudhan Chikkature 	if (!mmc) {
2017a45c6cb8SMadhusudhan Chikkature 		ret = -ENOMEM;
20181e363e3bSAndreas Fenkart 		goto err;
2019a45c6cb8SMadhusudhan Chikkature 	}
2020a45c6cb8SMadhusudhan Chikkature 
2021fdb9de12SNeilBrown 	ret = mmc_of_parse(mmc);
2022fdb9de12SNeilBrown 	if (ret)
2023fdb9de12SNeilBrown 		goto err1;
2024fdb9de12SNeilBrown 
2025a45c6cb8SMadhusudhan Chikkature 	host		= mmc_priv(mmc);
2026a45c6cb8SMadhusudhan Chikkature 	host->mmc	= mmc;
2027a45c6cb8SMadhusudhan Chikkature 	host->pdata	= pdata;
2028a45c6cb8SMadhusudhan Chikkature 	host->dev	= &pdev->dev;
2029a45c6cb8SMadhusudhan Chikkature 	host->use_dma	= 1;
2030a45c6cb8SMadhusudhan Chikkature 	host->dma_ch	= -1;
2031a45c6cb8SMadhusudhan Chikkature 	host->irq	= irq;
2032fc307df8SBalaji T K 	host->mapbase	= res->start + pdata->reg_offset;
203377fae219SBalaji T K 	host->base	= base + pdata->reg_offset;
20346da20c89SAdrian Hunter 	host->power_mode = MMC_POWER_OFF;
20359782aff8SPer Forlin 	host->next_data.cookie = 1;
2036bb2726b5STony Lindgren 	host->pbias_enabled = 0;
20373f77f702SKishon Vijay Abraham I 	host->vqmmc_enabled = 0;
2038a45c6cb8SMadhusudhan Chikkature 
203941afa314SNeilBrown 	ret = omap_hsmmc_gpio_init(mmc, host, pdata);
20401e363e3bSAndreas Fenkart 	if (ret)
20411e363e3bSAndreas Fenkart 		goto err_gpio;
20421e363e3bSAndreas Fenkart 
2043a45c6cb8SMadhusudhan Chikkature 	platform_set_drvdata(pdev, host);
2044a45c6cb8SMadhusudhan Chikkature 
20452cd3a2a5SAndreas Fenkart 	if (pdev->dev.of_node)
20462cd3a2a5SAndreas Fenkart 		host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
20472cd3a2a5SAndreas Fenkart 
204870a3341aSDenis Karpov 	mmc->ops	= &omap_hsmmc_ops;
2049dd498effSDenis Karpov 
20506b206efeSAndy Shevchenko 	mmc->f_min = OMAP_MMC_MIN_CLOCK;
2051d418ed87SDaniel Mack 
2052d418ed87SDaniel Mack 	if (pdata->max_freq > 0)
2053d418ed87SDaniel Mack 		mmc->f_max = pdata->max_freq;
2054fdb9de12SNeilBrown 	else if (mmc->f_max == 0)
20556b206efeSAndy Shevchenko 		mmc->f_max = OMAP_MMC_MAX_CLOCK;
2056a45c6cb8SMadhusudhan Chikkature 
20574dffd7a2SAdrian Hunter 	spin_lock_init(&host->irq_lock);
2058a45c6cb8SMadhusudhan Chikkature 
20599618195eSBalaji T K 	host->fclk = devm_clk_get(&pdev->dev, "fck");
2060a45c6cb8SMadhusudhan Chikkature 	if (IS_ERR(host->fclk)) {
2061a45c6cb8SMadhusudhan Chikkature 		ret = PTR_ERR(host->fclk);
2062a45c6cb8SMadhusudhan Chikkature 		host->fclk = NULL;
2063a45c6cb8SMadhusudhan Chikkature 		goto err1;
2064a45c6cb8SMadhusudhan Chikkature 	}
2065a45c6cb8SMadhusudhan Chikkature 
20669b68256cSPaul Walmsley 	if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
20679b68256cSPaul Walmsley 		dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
2068afd8c29dSKuninori Morimoto 		omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
20699b68256cSPaul Walmsley 	}
2070dd498effSDenis Karpov 
20715b83b223STony Lindgren 	device_init_wakeup(&pdev->dev, true);
2072fa4aa2d4SBalaji T K 	pm_runtime_enable(host->dev);
2073fa4aa2d4SBalaji T K 	pm_runtime_get_sync(host->dev);
2074fa4aa2d4SBalaji T K 	pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
2075fa4aa2d4SBalaji T K 	pm_runtime_use_autosuspend(host->dev);
2076a45c6cb8SMadhusudhan Chikkature 
207792a3aebfSBalaji T K 	omap_hsmmc_context_save(host);
207892a3aebfSBalaji T K 
20799618195eSBalaji T K 	host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
2080a45c6cb8SMadhusudhan Chikkature 	/*
2081a45c6cb8SMadhusudhan Chikkature 	 * MMC can still work without debounce clock.
2082a45c6cb8SMadhusudhan Chikkature 	 */
2083cd03d9a8SRajendra Nayak 	if (IS_ERR(host->dbclk)) {
2084cd03d9a8SRajendra Nayak 		host->dbclk = NULL;
208594c18149SRajendra Nayak 	} else if (clk_prepare_enable(host->dbclk) != 0) {
2086cd03d9a8SRajendra Nayak 		dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
2087cd03d9a8SRajendra Nayak 		host->dbclk = NULL;
20882bec0893SAdrian Hunter 	}
2089a45c6cb8SMadhusudhan Chikkature 
20900ccd76d4SJuha Yrjola 	/* Since we do only SG emulation, we can have as many segs
20910ccd76d4SJuha Yrjola 	 * as we want. */
2092a36274e0SMartin K. Petersen 	mmc->max_segs = 1024;
20930ccd76d4SJuha Yrjola 
2094a45c6cb8SMadhusudhan Chikkature 	mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
2095a45c6cb8SMadhusudhan Chikkature 	mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
2096a45c6cb8SMadhusudhan Chikkature 	mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2097a45c6cb8SMadhusudhan Chikkature 	mmc->max_seg_size = mmc->max_req_size;
2098a45c6cb8SMadhusudhan Chikkature 
209913189e78SJarkko Lavinen 	mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
210093caf8e6SAdrian Hunter 		     MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
2101a45c6cb8SMadhusudhan Chikkature 
2102326119c9SAndreas Fenkart 	mmc->caps |= mmc_pdata(host)->caps;
21033a63833eSSukumar Ghorai 	if (mmc->caps & MMC_CAP_8_BIT_DATA)
2104a45c6cb8SMadhusudhan Chikkature 		mmc->caps |= MMC_CAP_4_BIT_DATA;
2105a45c6cb8SMadhusudhan Chikkature 
2106326119c9SAndreas Fenkart 	if (mmc_pdata(host)->nonremovable)
210723d99bb9SAdrian Hunter 		mmc->caps |= MMC_CAP_NONREMOVABLE;
210823d99bb9SAdrian Hunter 
2109fdb9de12SNeilBrown 	mmc->pm_caps |= mmc_pdata(host)->pm_caps;
21106fdc75deSEliad Peller 
211170a3341aSDenis Karpov 	omap_hsmmc_conf_bus_power(host);
2112a45c6cb8SMadhusudhan Chikkature 
211381eef6caSPeter Ujfalusi 	host->rx_chan = dma_request_chan(&pdev->dev, "rx");
211481eef6caSPeter Ujfalusi 	if (IS_ERR(host->rx_chan)) {
211581eef6caSPeter Ujfalusi 		dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n");
211681eef6caSPeter Ujfalusi 		ret = PTR_ERR(host->rx_chan);
211726b88520SRussell King 		goto err_irq;
2118c5c98927SRussell King 	}
211926b88520SRussell King 
212081eef6caSPeter Ujfalusi 	host->tx_chan = dma_request_chan(&pdev->dev, "tx");
212181eef6caSPeter Ujfalusi 	if (IS_ERR(host->tx_chan)) {
212281eef6caSPeter Ujfalusi 		dev_err(mmc_dev(host->mmc), "TX DMA channel request failed\n");
212381eef6caSPeter Ujfalusi 		ret = PTR_ERR(host->tx_chan);
212426b88520SRussell King 		goto err_irq;
2125c5c98927SRussell King 	}
2126a45c6cb8SMadhusudhan Chikkature 
2127a45c6cb8SMadhusudhan Chikkature 	/* Request IRQ for MMC operations */
2128e1538ed7SBalaji T K 	ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
2129a45c6cb8SMadhusudhan Chikkature 			mmc_hostname(mmc), host);
2130a45c6cb8SMadhusudhan Chikkature 	if (ret) {
2131b1e056aeSVenkatraman S 		dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2132a45c6cb8SMadhusudhan Chikkature 		goto err_irq;
2133a45c6cb8SMadhusudhan Chikkature 	}
2134a45c6cb8SMadhusudhan Chikkature 
2135db0fefc5SAdrian Hunter 	ret = omap_hsmmc_reg_get(host);
2136db0fefc5SAdrian Hunter 	if (ret)
2137bb09d151SAndreas Fenkart 		goto err_irq;
2138db0fefc5SAdrian Hunter 
213913ab2a66SKishon Vijay Abraham I 	if (!mmc->ocr_avail)
2140326119c9SAndreas Fenkart 		mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
2141a45c6cb8SMadhusudhan Chikkature 
2142b417577dSAdrian Hunter 	omap_hsmmc_disable_irq(host);
2143a45c6cb8SMadhusudhan Chikkature 
21442cd3a2a5SAndreas Fenkart 	/*
21452cd3a2a5SAndreas Fenkart 	 * For now, only support SDIO interrupt if we have a separate
21462cd3a2a5SAndreas Fenkart 	 * wake-up interrupt configured from device tree. This is because
21472cd3a2a5SAndreas Fenkart 	 * the wake-up interrupt is needed for idle state and some
21482cd3a2a5SAndreas Fenkart 	 * platforms need special quirks. And we don't want to add new
21492cd3a2a5SAndreas Fenkart 	 * legacy mux platform init code callbacks any longer as we
21502cd3a2a5SAndreas Fenkart 	 * are moving to DT based booting anyways.
21512cd3a2a5SAndreas Fenkart 	 */
21522cd3a2a5SAndreas Fenkart 	ret = omap_hsmmc_configure_wake_irq(host);
21532cd3a2a5SAndreas Fenkart 	if (!ret)
21542cd3a2a5SAndreas Fenkart 		mmc->caps |= MMC_CAP_SDIO_IRQ;
21552cd3a2a5SAndreas Fenkart 
2156b62f6228SAdrian Hunter 	omap_hsmmc_protect_card(host);
2157b62f6228SAdrian Hunter 
2158a45c6cb8SMadhusudhan Chikkature 	mmc_add_host(mmc);
2159a45c6cb8SMadhusudhan Chikkature 
2160326119c9SAndreas Fenkart 	if (mmc_pdata(host)->name != NULL) {
2161a45c6cb8SMadhusudhan Chikkature 		ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2162a45c6cb8SMadhusudhan Chikkature 		if (ret < 0)
2163a45c6cb8SMadhusudhan Chikkature 			goto err_slot_name;
2164a45c6cb8SMadhusudhan Chikkature 	}
2165cde592cbSAndreas Fenkart 	if (host->get_cover_state) {
2166a45c6cb8SMadhusudhan Chikkature 		ret = device_create_file(&mmc->class_dev,
2167a45c6cb8SMadhusudhan Chikkature 					 &dev_attr_cover_switch);
2168a45c6cb8SMadhusudhan Chikkature 		if (ret < 0)
2169db0fefc5SAdrian Hunter 			goto err_slot_name;
2170a45c6cb8SMadhusudhan Chikkature 	}
2171a45c6cb8SMadhusudhan Chikkature 
217270a3341aSDenis Karpov 	omap_hsmmc_debugfs(mmc);
2173fa4aa2d4SBalaji T K 	pm_runtime_mark_last_busy(host->dev);
2174fa4aa2d4SBalaji T K 	pm_runtime_put_autosuspend(host->dev);
2175d900f712SDenis Karpov 
2176a45c6cb8SMadhusudhan Chikkature 	return 0;
2177a45c6cb8SMadhusudhan Chikkature 
2178a45c6cb8SMadhusudhan Chikkature err_slot_name:
2179a45c6cb8SMadhusudhan Chikkature 	mmc_remove_host(mmc);
2180a45c6cb8SMadhusudhan Chikkature err_irq:
21815b83b223STony Lindgren 	device_init_wakeup(&pdev->dev, false);
218281eef6caSPeter Ujfalusi 	if (!IS_ERR_OR_NULL(host->tx_chan))
2183c5c98927SRussell King 		dma_release_channel(host->tx_chan);
218481eef6caSPeter Ujfalusi 	if (!IS_ERR_OR_NULL(host->rx_chan))
2185c5c98927SRussell King 		dma_release_channel(host->rx_chan);
2186814a3c0cSTony Lindgren 	pm_runtime_dont_use_autosuspend(host->dev);
2187d59d77edSBalaji T K 	pm_runtime_put_sync(host->dev);
218837f6190dSTony Lindgren 	pm_runtime_disable(host->dev);
21899618195eSBalaji T K 	if (host->dbclk)
219094c18149SRajendra Nayak 		clk_disable_unprepare(host->dbclk);
2191a45c6cb8SMadhusudhan Chikkature err1:
21921e363e3bSAndreas Fenkart err_gpio:
2193a45c6cb8SMadhusudhan Chikkature 	mmc_free_host(mmc);
2194db0fefc5SAdrian Hunter err:
2195a45c6cb8SMadhusudhan Chikkature 	return ret;
2196a45c6cb8SMadhusudhan Chikkature }
2197a45c6cb8SMadhusudhan Chikkature 
21986e0ee714SBill Pemberton static int omap_hsmmc_remove(struct platform_device *pdev)
2199a45c6cb8SMadhusudhan Chikkature {
220070a3341aSDenis Karpov 	struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2201a45c6cb8SMadhusudhan Chikkature 
2202fa4aa2d4SBalaji T K 	pm_runtime_get_sync(host->dev);
2203a45c6cb8SMadhusudhan Chikkature 	mmc_remove_host(host->mmc);
2204a45c6cb8SMadhusudhan Chikkature 
2205c5c98927SRussell King 	dma_release_channel(host->tx_chan);
2206c5c98927SRussell King 	dma_release_channel(host->rx_chan);
2207c5c98927SRussell King 
2208814a3c0cSTony Lindgren 	pm_runtime_dont_use_autosuspend(host->dev);
2209fa4aa2d4SBalaji T K 	pm_runtime_put_sync(host->dev);
2210fa4aa2d4SBalaji T K 	pm_runtime_disable(host->dev);
22115b83b223STony Lindgren 	device_init_wakeup(&pdev->dev, false);
22129618195eSBalaji T K 	if (host->dbclk)
221394c18149SRajendra Nayak 		clk_disable_unprepare(host->dbclk);
2214a45c6cb8SMadhusudhan Chikkature 
22159d1f0286SBalaji T K 	mmc_free_host(host->mmc);
2216a45c6cb8SMadhusudhan Chikkature 
2217a45c6cb8SMadhusudhan Chikkature 	return 0;
2218a45c6cb8SMadhusudhan Chikkature }
2219a45c6cb8SMadhusudhan Chikkature 
22203d3bbfbdSRuss Dill #ifdef CONFIG_PM_SLEEP
2221a791daa1SKevin Hilman static int omap_hsmmc_suspend(struct device *dev)
2222a45c6cb8SMadhusudhan Chikkature {
2223927ce944SFelipe Balbi 	struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2224927ce944SFelipe Balbi 
2225927ce944SFelipe Balbi 	if (!host)
2226927ce944SFelipe Balbi 		return 0;
2227a45c6cb8SMadhusudhan Chikkature 
2228fa4aa2d4SBalaji T K 	pm_runtime_get_sync(host->dev);
222931f9d463SEliad Peller 
223031f9d463SEliad Peller 	if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
22312cd3a2a5SAndreas Fenkart 		OMAP_HSMMC_WRITE(host->base, ISE, 0);
22322cd3a2a5SAndreas Fenkart 		OMAP_HSMMC_WRITE(host->base, IE, 0);
22332cd3a2a5SAndreas Fenkart 		OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
223431f9d463SEliad Peller 		OMAP_HSMMC_WRITE(host->base, HCTL,
223531f9d463SEliad Peller 				OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
223631f9d463SEliad Peller 	}
2237927ce944SFelipe Balbi 
2238cd03d9a8SRajendra Nayak 	if (host->dbclk)
223994c18149SRajendra Nayak 		clk_disable_unprepare(host->dbclk);
22403932afd5SUlf Hansson 
2241fa4aa2d4SBalaji T K 	pm_runtime_put_sync(host->dev);
22423932afd5SUlf Hansson 	return 0;
2243a45c6cb8SMadhusudhan Chikkature }
2244a45c6cb8SMadhusudhan Chikkature 
2245a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */
2246a791daa1SKevin Hilman static int omap_hsmmc_resume(struct device *dev)
2247a45c6cb8SMadhusudhan Chikkature {
2248927ce944SFelipe Balbi 	struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2249927ce944SFelipe Balbi 
2250927ce944SFelipe Balbi 	if (!host)
2251927ce944SFelipe Balbi 		return 0;
2252a45c6cb8SMadhusudhan Chikkature 
2253fa4aa2d4SBalaji T K 	pm_runtime_get_sync(host->dev);
225411dd62a7SDenis Karpov 
2255cd03d9a8SRajendra Nayak 	if (host->dbclk)
225694c18149SRajendra Nayak 		clk_prepare_enable(host->dbclk);
22572bec0893SAdrian Hunter 
225831f9d463SEliad Peller 	if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
225970a3341aSDenis Karpov 		omap_hsmmc_conf_bus_power(host);
22601b331e69SKim Kyuwon 
2261b62f6228SAdrian Hunter 	omap_hsmmc_protect_card(host);
2262fa4aa2d4SBalaji T K 	pm_runtime_mark_last_busy(host->dev);
2263fa4aa2d4SBalaji T K 	pm_runtime_put_autosuspend(host->dev);
22643932afd5SUlf Hansson 	return 0;
2265a45c6cb8SMadhusudhan Chikkature }
2266a45c6cb8SMadhusudhan Chikkature #endif
2267a45c6cb8SMadhusudhan Chikkature 
2268fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_suspend(struct device *dev)
2269fa4aa2d4SBalaji T K {
2270fa4aa2d4SBalaji T K 	struct omap_hsmmc_host *host;
22712cd3a2a5SAndreas Fenkart 	unsigned long flags;
2272f945901fSAndreas Fenkart 	int ret = 0;
2273fa4aa2d4SBalaji T K 
2274fa4aa2d4SBalaji T K 	host = platform_get_drvdata(to_platform_device(dev));
2275fa4aa2d4SBalaji T K 	omap_hsmmc_context_save(host);
2276927ce944SFelipe Balbi 	dev_dbg(dev, "disabled\n");
2277fa4aa2d4SBalaji T K 
22782cd3a2a5SAndreas Fenkart 	spin_lock_irqsave(&host->irq_lock, flags);
22792cd3a2a5SAndreas Fenkart 	if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
22802cd3a2a5SAndreas Fenkart 	    (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
22812cd3a2a5SAndreas Fenkart 		/* disable sdio irq handling to prevent race */
22822cd3a2a5SAndreas Fenkart 		OMAP_HSMMC_WRITE(host->base, ISE, 0);
22832cd3a2a5SAndreas Fenkart 		OMAP_HSMMC_WRITE(host->base, IE, 0);
2284f945901fSAndreas Fenkart 
2285f945901fSAndreas Fenkart 		if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
2286f945901fSAndreas Fenkart 			/*
2287f945901fSAndreas Fenkart 			 * dat1 line low, pending sdio irq
2288f945901fSAndreas Fenkart 			 * race condition: possible irq handler running on
2289f945901fSAndreas Fenkart 			 * multi-core, abort
2290f945901fSAndreas Fenkart 			 */
2291f945901fSAndreas Fenkart 			dev_dbg(dev, "pending sdio irq, abort suspend\n");
22922cd3a2a5SAndreas Fenkart 			OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2293f945901fSAndreas Fenkart 			OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2294f945901fSAndreas Fenkart 			OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2295f945901fSAndreas Fenkart 			pm_runtime_mark_last_busy(dev);
2296f945901fSAndreas Fenkart 			ret = -EBUSY;
2297f945901fSAndreas Fenkart 			goto abort;
2298f945901fSAndreas Fenkart 		}
22992cd3a2a5SAndreas Fenkart 
230097978a44SAndreas Fenkart 		pinctrl_pm_select_idle_state(dev);
230197978a44SAndreas Fenkart 	} else {
230297978a44SAndreas Fenkart 		pinctrl_pm_select_idle_state(dev);
23032cd3a2a5SAndreas Fenkart 	}
230497978a44SAndreas Fenkart 
2305f945901fSAndreas Fenkart abort:
23062cd3a2a5SAndreas Fenkart 	spin_unlock_irqrestore(&host->irq_lock, flags);
2307f945901fSAndreas Fenkart 	return ret;
2308fa4aa2d4SBalaji T K }
2309fa4aa2d4SBalaji T K 
2310fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_resume(struct device *dev)
2311fa4aa2d4SBalaji T K {
2312fa4aa2d4SBalaji T K 	struct omap_hsmmc_host *host;
23132cd3a2a5SAndreas Fenkart 	unsigned long flags;
2314fa4aa2d4SBalaji T K 
2315fa4aa2d4SBalaji T K 	host = platform_get_drvdata(to_platform_device(dev));
2316fa4aa2d4SBalaji T K 	omap_hsmmc_context_restore(host);
2317927ce944SFelipe Balbi 	dev_dbg(dev, "enabled\n");
2318fa4aa2d4SBalaji T K 
23192cd3a2a5SAndreas Fenkart 	spin_lock_irqsave(&host->irq_lock, flags);
23202cd3a2a5SAndreas Fenkart 	if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
23212cd3a2a5SAndreas Fenkart 	    (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
23222cd3a2a5SAndreas Fenkart 
232397978a44SAndreas Fenkart 		pinctrl_pm_select_default_state(host->dev);
232497978a44SAndreas Fenkart 
232597978a44SAndreas Fenkart 		/* irq lost, if pinmux incorrect */
23262cd3a2a5SAndreas Fenkart 		OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
23272cd3a2a5SAndreas Fenkart 		OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
23282cd3a2a5SAndreas Fenkart 		OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
232997978a44SAndreas Fenkart 	} else {
233097978a44SAndreas Fenkart 		pinctrl_pm_select_default_state(host->dev);
23312cd3a2a5SAndreas Fenkart 	}
23322cd3a2a5SAndreas Fenkart 	spin_unlock_irqrestore(&host->irq_lock, flags);
2333fa4aa2d4SBalaji T K 	return 0;
2334fa4aa2d4SBalaji T K }
2335fa4aa2d4SBalaji T K 
2336a791daa1SKevin Hilman static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
23373d3bbfbdSRuss Dill 	SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume)
2338fa4aa2d4SBalaji T K 	.runtime_suspend = omap_hsmmc_runtime_suspend,
2339fa4aa2d4SBalaji T K 	.runtime_resume = omap_hsmmc_runtime_resume,
2340a791daa1SKevin Hilman };
2341a791daa1SKevin Hilman 
2342a791daa1SKevin Hilman static struct platform_driver omap_hsmmc_driver = {
2343efa25fd3SFelipe Balbi 	.probe		= omap_hsmmc_probe,
23440433c143SBill Pemberton 	.remove		= omap_hsmmc_remove,
2345a45c6cb8SMadhusudhan Chikkature 	.driver		= {
2346a45c6cb8SMadhusudhan Chikkature 		.name = DRIVER_NAME,
2347a791daa1SKevin Hilman 		.pm = &omap_hsmmc_dev_pm_ops,
234846856a68SRajendra Nayak 		.of_match_table = of_match_ptr(omap_mmc_of_match),
2349a45c6cb8SMadhusudhan Chikkature 	},
2350a45c6cb8SMadhusudhan Chikkature };
2351a45c6cb8SMadhusudhan Chikkature 
2352b796450bSFelipe Balbi module_platform_driver(omap_hsmmc_driver);
2353a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2354a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL");
2355a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME);
2356a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc");
2357