1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20ac330f44SAndy Shevchenko #include <linux/kernel.h> 21d900f712SDenis Karpov #include <linux/debugfs.h> 22c5c98927SRussell King #include <linux/dmaengine.h> 23d900f712SDenis Karpov #include <linux/seq_file.h> 24031cd037SFelipe Balbi #include <linux/sizes.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 29a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 30a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 3146856a68SRajendra Nayak #include <linux/of.h> 322cd3a2a5SAndreas Fenkart #include <linux/of_irq.h> 3346856a68SRajendra Nayak #include <linux/of_gpio.h> 3446856a68SRajendra Nayak #include <linux/of_device.h> 35ee526d51SBalaji T K #include <linux/omap-dmaengine.h> 36a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 3713189e78SJarkko Lavinen #include <linux/mmc/core.h> 3893caf8e6SAdrian Hunter #include <linux/mmc/mmc.h> 3941afa314SNeilBrown #include <linux/mmc/slot-gpio.h> 40a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 412cd3a2a5SAndreas Fenkart #include <linux/irq.h> 42db0fefc5SAdrian Hunter #include <linux/gpio.h> 43db0fefc5SAdrian Hunter #include <linux/regulator/consumer.h> 4446b76035SDaniel Mack #include <linux/pinctrl/consumer.h> 45fa4aa2d4SBalaji T K #include <linux/pm_runtime.h> 465b83b223STony Lindgren #include <linux/pm_wakeirq.h> 4755143438SAndreas Fenkart #include <linux/platform_data/hsmmc-omap.h> 48a45c6cb8SMadhusudhan Chikkature 49a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 5011dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS 0x0014 51a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 52a2e77152SBalaji T K #define OMAP_HSMMC_SDMASA 0x0100 53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 57a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 58a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 59a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 60a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 61bb0635f0SAndreas Fenkart #define OMAP_HSMMC_PSTATE 0x0124 62a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 63a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 64a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 65a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 66a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 67a2e77152SBalaji T K #define OMAP_HSMMC_AC12 0x013C 68a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 69a45c6cb8SMadhusudhan Chikkature 70a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 71a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 72cd587096SHebbar, Gururaja #define HSS (1 << 21) 73a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 74a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 75eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 761b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 77a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 78a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 79a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 80a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 81a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 82a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 83a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 84a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 85ed164182SBalaji T K #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ 86a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 87a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 88a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 89a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 90a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 91a2e77152SBalaji T K #define ACEN_ACMD23 (2 << 2) 92a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 93a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 94a7e96879SVenkatraman S #define DMAE 0x1 95a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 96a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 97a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 98cd587096SHebbar, Gururaja #define HSPE (1 << 2) 995a52b08bSBalaji T K #define IWE (1 << 24) 10003b5d924SBalaji T K #define DDR (1 << 19) 1015a52b08bSBalaji T K #define CLKEXTFREE (1 << 16) 1025a52b08bSBalaji T K #define CTPL (1 << 11) 10373153010SJarkko Lavinen #define DW8 (1 << 5) 104a45c6cb8SMadhusudhan Chikkature #define OD 0x1 105a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 106a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 107a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 108a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 109a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 11011dd62a7SDenis Karpov #define SOFTRESET (1 << 1) 111a45c6cb8SMadhusudhan Chikkature 112f945901fSAndreas Fenkart /* PSTATE */ 113f945901fSAndreas Fenkart #define DLEV_DAT(x) (1 << (20 + (x))) 114f945901fSAndreas Fenkart 115a7e96879SVenkatraman S /* Interrupt masks for IE and ISE register */ 116a7e96879SVenkatraman S #define CC_EN (1 << 0) 117a7e96879SVenkatraman S #define TC_EN (1 << 1) 118a7e96879SVenkatraman S #define BWR_EN (1 << 4) 119a7e96879SVenkatraman S #define BRR_EN (1 << 5) 1202cd3a2a5SAndreas Fenkart #define CIRQ_EN (1 << 8) 121a7e96879SVenkatraman S #define ERR_EN (1 << 15) 122a7e96879SVenkatraman S #define CTO_EN (1 << 16) 123a7e96879SVenkatraman S #define CCRC_EN (1 << 17) 124a7e96879SVenkatraman S #define CEB_EN (1 << 18) 125a7e96879SVenkatraman S #define CIE_EN (1 << 19) 126a7e96879SVenkatraman S #define DTO_EN (1 << 20) 127a7e96879SVenkatraman S #define DCRC_EN (1 << 21) 128a7e96879SVenkatraman S #define DEB_EN (1 << 22) 129a2e77152SBalaji T K #define ACE_EN (1 << 24) 130a7e96879SVenkatraman S #define CERR_EN (1 << 28) 131a7e96879SVenkatraman S #define BADA_EN (1 << 29) 132a7e96879SVenkatraman S 133a2e77152SBalaji T K #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\ 134a7e96879SVenkatraman S DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ 135a7e96879SVenkatraman S BRR_EN | BWR_EN | TC_EN | CC_EN) 136a7e96879SVenkatraman S 137a2e77152SBalaji T K #define CNI (1 << 7) 138a2e77152SBalaji T K #define ACIE (1 << 4) 139a2e77152SBalaji T K #define ACEB (1 << 3) 140a2e77152SBalaji T K #define ACCE (1 << 2) 141a2e77152SBalaji T K #define ACTO (1 << 1) 142a2e77152SBalaji T K #define ACNE (1 << 0) 143a2e77152SBalaji T K 144fa4aa2d4SBalaji T K #define MMC_AUTOSUSPEND_DELAY 100 1451e881786SJianpeng Ma #define MMC_TIMEOUT_MS 20 /* 20 mSec */ 1461e881786SJianpeng Ma #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ 1476b206efeSAndy Shevchenko #define OMAP_MMC_MIN_CLOCK 400000 1486b206efeSAndy Shevchenko #define OMAP_MMC_MAX_CLOCK 52000000 1490005ae73SKishore Kadiyala #define DRIVER_NAME "omap_hsmmc" 150a45c6cb8SMadhusudhan Chikkature 151e99448ffSBalaji T K #define VDD_1V8 1800000 /* 180000 uV */ 152e99448ffSBalaji T K #define VDD_3V0 3000000 /* 300000 uV */ 153e99448ffSBalaji T K #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1) 154e99448ffSBalaji T K 155a45c6cb8SMadhusudhan Chikkature /* 156a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 157a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 158a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 159a45c6cb8SMadhusudhan Chikkature */ 160326119c9SAndreas Fenkart #define mmc_pdata(host) host->pdata 161a45c6cb8SMadhusudhan Chikkature 162a45c6cb8SMadhusudhan Chikkature /* 163a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 164a45c6cb8SMadhusudhan Chikkature */ 165a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 166a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 167a45c6cb8SMadhusudhan Chikkature 168a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 169a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 170a45c6cb8SMadhusudhan Chikkature 1719782aff8SPer Forlin struct omap_hsmmc_next { 1729782aff8SPer Forlin unsigned int dma_len; 1739782aff8SPer Forlin s32 cookie; 1749782aff8SPer Forlin }; 1759782aff8SPer Forlin 17670a3341aSDenis Karpov struct omap_hsmmc_host { 177a45c6cb8SMadhusudhan Chikkature struct device *dev; 178a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 179a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 180a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 181a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 182a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 183a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 184e99448ffSBalaji T K struct regulator *pbias; 185bb2726b5STony Lindgren bool pbias_enabled; 186a45c6cb8SMadhusudhan Chikkature void __iomem *base; 1873f77f702SKishon Vijay Abraham I int vqmmc_enabled; 188a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 1894dffd7a2SAdrian Hunter spinlock_t irq_lock; /* Prevent races with irq handler */ 190a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 1910ccd76d4SJuha Yrjola unsigned int dma_sg_idx; 192a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 193a3621465SAdrian Hunter unsigned char power_mode; 194a45c6cb8SMadhusudhan Chikkature int suspended; 1950a82e06eSTony Lindgren u32 con; 1960a82e06eSTony Lindgren u32 hctl; 1970a82e06eSTony Lindgren u32 sysctl; 1980a82e06eSTony Lindgren u32 capa; 199a45c6cb8SMadhusudhan Chikkature int irq; 2002cd3a2a5SAndreas Fenkart int wake_irq; 201a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 202c5c98927SRussell King struct dma_chan *tx_chan; 203c5c98927SRussell King struct dma_chan *rx_chan; 2044a694dc9SAdrian Hunter int response_busy; 20511dd62a7SDenis Karpov int context_loss; 206b62f6228SAdrian Hunter int protect_card; 207b62f6228SAdrian Hunter int reqs_blocked; 208b417577dSAdrian Hunter int req_in_progress; 2096e3076c2SBalaji T K unsigned long clk_rate; 210a2e77152SBalaji T K unsigned int flags; 2112cd3a2a5SAndreas Fenkart #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */ 2122cd3a2a5SAndreas Fenkart #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */ 2139782aff8SPer Forlin struct omap_hsmmc_next next_data; 21455143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata; 215b5cd43f0SAndreas Fenkart 216b5cd43f0SAndreas Fenkart /* return MMC cover switch state, can be NULL if not supported. 217b5cd43f0SAndreas Fenkart * 218b5cd43f0SAndreas Fenkart * possible return values: 219b5cd43f0SAndreas Fenkart * 0 - closed 220b5cd43f0SAndreas Fenkart * 1 - open 221b5cd43f0SAndreas Fenkart */ 22280412ca8SAndreas Fenkart int (*get_cover_state)(struct device *dev); 223b5cd43f0SAndreas Fenkart 22480412ca8SAndreas Fenkart int (*card_detect)(struct device *dev); 225a45c6cb8SMadhusudhan Chikkature }; 226a45c6cb8SMadhusudhan Chikkature 22759445b10SNishanth Menon struct omap_mmc_of_data { 22859445b10SNishanth Menon u32 reg_offset; 22959445b10SNishanth Menon u8 controller_flags; 23059445b10SNishanth Menon }; 23159445b10SNishanth Menon 232bf129e1cSBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host); 233bf129e1cSBalaji T K 23480412ca8SAndreas Fenkart static int omap_hsmmc_card_detect(struct device *dev) 235db0fefc5SAdrian Hunter { 2369ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 237db0fefc5SAdrian Hunter 23841afa314SNeilBrown return mmc_gpio_get_cd(host->mmc); 239db0fefc5SAdrian Hunter } 240db0fefc5SAdrian Hunter 24180412ca8SAndreas Fenkart static int omap_hsmmc_get_cover_state(struct device *dev) 242db0fefc5SAdrian Hunter { 2439ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 244db0fefc5SAdrian Hunter 24541afa314SNeilBrown return mmc_gpio_get_cd(host->mmc); 246db0fefc5SAdrian Hunter } 247db0fefc5SAdrian Hunter 2481d17f30bSKishon Vijay Abraham I static int omap_hsmmc_enable_supply(struct mmc_host *mmc) 2492a17f844SKishon Vijay Abraham I { 2502a17f844SKishon Vijay Abraham I int ret; 2513f77f702SKishon Vijay Abraham I struct omap_hsmmc_host *host = mmc_priv(mmc); 2521d17f30bSKishon Vijay Abraham I struct mmc_ios *ios = &mmc->ios; 2532a17f844SKishon Vijay Abraham I 2542a17f844SKishon Vijay Abraham I if (mmc->supply.vmmc) { 2551d17f30bSKishon Vijay Abraham I ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 2562a17f844SKishon Vijay Abraham I if (ret) 2572a17f844SKishon Vijay Abraham I return ret; 2582a17f844SKishon Vijay Abraham I } 2592a17f844SKishon Vijay Abraham I 2602a17f844SKishon Vijay Abraham I /* Enable interface voltage rail, if needed */ 2613f77f702SKishon Vijay Abraham I if (mmc->supply.vqmmc && !host->vqmmc_enabled) { 2622a17f844SKishon Vijay Abraham I ret = regulator_enable(mmc->supply.vqmmc); 2632a17f844SKishon Vijay Abraham I if (ret) { 2642a17f844SKishon Vijay Abraham I dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n"); 2652a17f844SKishon Vijay Abraham I goto err_vqmmc; 2662a17f844SKishon Vijay Abraham I } 2673f77f702SKishon Vijay Abraham I host->vqmmc_enabled = 1; 2682a17f844SKishon Vijay Abraham I } 2692a17f844SKishon Vijay Abraham I 2702a17f844SKishon Vijay Abraham I return 0; 2712a17f844SKishon Vijay Abraham I 2722a17f844SKishon Vijay Abraham I err_vqmmc: 2732a17f844SKishon Vijay Abraham I if (mmc->supply.vmmc) 2742a17f844SKishon Vijay Abraham I mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 2752a17f844SKishon Vijay Abraham I 2762a17f844SKishon Vijay Abraham I return ret; 2772a17f844SKishon Vijay Abraham I } 2782a17f844SKishon Vijay Abraham I 2792a17f844SKishon Vijay Abraham I static int omap_hsmmc_disable_supply(struct mmc_host *mmc) 2802a17f844SKishon Vijay Abraham I { 2812a17f844SKishon Vijay Abraham I int ret; 2822a17f844SKishon Vijay Abraham I int status; 2833f77f702SKishon Vijay Abraham I struct omap_hsmmc_host *host = mmc_priv(mmc); 2842a17f844SKishon Vijay Abraham I 2853f77f702SKishon Vijay Abraham I if (mmc->supply.vqmmc && host->vqmmc_enabled) { 2862a17f844SKishon Vijay Abraham I ret = regulator_disable(mmc->supply.vqmmc); 2872a17f844SKishon Vijay Abraham I if (ret) { 2882a17f844SKishon Vijay Abraham I dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n"); 2892a17f844SKishon Vijay Abraham I return ret; 2902a17f844SKishon Vijay Abraham I } 2913f77f702SKishon Vijay Abraham I host->vqmmc_enabled = 0; 2922a17f844SKishon Vijay Abraham I } 2932a17f844SKishon Vijay Abraham I 2942a17f844SKishon Vijay Abraham I if (mmc->supply.vmmc) { 2952a17f844SKishon Vijay Abraham I ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 2962a17f844SKishon Vijay Abraham I if (ret) 2972a17f844SKishon Vijay Abraham I goto err_set_ocr; 2982a17f844SKishon Vijay Abraham I } 2992a17f844SKishon Vijay Abraham I 3002a17f844SKishon Vijay Abraham I return 0; 3012a17f844SKishon Vijay Abraham I 3022a17f844SKishon Vijay Abraham I err_set_ocr: 3032a17f844SKishon Vijay Abraham I if (mmc->supply.vqmmc) { 3042a17f844SKishon Vijay Abraham I status = regulator_enable(mmc->supply.vqmmc); 3052a17f844SKishon Vijay Abraham I if (status) 3062a17f844SKishon Vijay Abraham I dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n"); 3072a17f844SKishon Vijay Abraham I } 3082a17f844SKishon Vijay Abraham I 3092a17f844SKishon Vijay Abraham I return ret; 3102a17f844SKishon Vijay Abraham I } 3112a17f844SKishon Vijay Abraham I 312ec85c95eSKishon Vijay Abraham I static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on, 313ec85c95eSKishon Vijay Abraham I int vdd) 314ec85c95eSKishon Vijay Abraham I { 315ec85c95eSKishon Vijay Abraham I int ret; 316ec85c95eSKishon Vijay Abraham I 317ec85c95eSKishon Vijay Abraham I if (!host->pbias) 318ec85c95eSKishon Vijay Abraham I return 0; 319ec85c95eSKishon Vijay Abraham I 320ec85c95eSKishon Vijay Abraham I if (power_on) { 321ec85c95eSKishon Vijay Abraham I if (vdd <= VDD_165_195) 322ec85c95eSKishon Vijay Abraham I ret = regulator_set_voltage(host->pbias, VDD_1V8, 323ec85c95eSKishon Vijay Abraham I VDD_1V8); 324ec85c95eSKishon Vijay Abraham I else 325ec85c95eSKishon Vijay Abraham I ret = regulator_set_voltage(host->pbias, VDD_3V0, 326ec85c95eSKishon Vijay Abraham I VDD_3V0); 327ec85c95eSKishon Vijay Abraham I if (ret < 0) { 328ec85c95eSKishon Vijay Abraham I dev_err(host->dev, "pbias set voltage fail\n"); 329ec85c95eSKishon Vijay Abraham I return ret; 330ec85c95eSKishon Vijay Abraham I } 331ec85c95eSKishon Vijay Abraham I 332bb2726b5STony Lindgren if (host->pbias_enabled == 0) { 333ec85c95eSKishon Vijay Abraham I ret = regulator_enable(host->pbias); 334ec85c95eSKishon Vijay Abraham I if (ret) { 335ec85c95eSKishon Vijay Abraham I dev_err(host->dev, "pbias reg enable fail\n"); 336ec85c95eSKishon Vijay Abraham I return ret; 337ec85c95eSKishon Vijay Abraham I } 338bb2726b5STony Lindgren host->pbias_enabled = 1; 339ec85c95eSKishon Vijay Abraham I } 340ec85c95eSKishon Vijay Abraham I } else { 341bb2726b5STony Lindgren if (host->pbias_enabled == 1) { 342ec85c95eSKishon Vijay Abraham I ret = regulator_disable(host->pbias); 343ec85c95eSKishon Vijay Abraham I if (ret) { 344ec85c95eSKishon Vijay Abraham I dev_err(host->dev, "pbias reg disable fail\n"); 345ec85c95eSKishon Vijay Abraham I return ret; 346ec85c95eSKishon Vijay Abraham I } 347bb2726b5STony Lindgren host->pbias_enabled = 0; 348ec85c95eSKishon Vijay Abraham I } 349ec85c95eSKishon Vijay Abraham I } 350ec85c95eSKishon Vijay Abraham I 351ec85c95eSKishon Vijay Abraham I return 0; 352ec85c95eSKishon Vijay Abraham I } 353ec85c95eSKishon Vijay Abraham I 35480412ca8SAndreas Fenkart static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd) 355db0fefc5SAdrian Hunter { 356db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 357db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 358aa9a6801SKishon Vijay Abraham I struct mmc_host *mmc = host->mmc; 359db0fefc5SAdrian Hunter int ret = 0; 360db0fefc5SAdrian Hunter 361f7f0f035SAndreas Fenkart if (mmc_pdata(host)->set_power) 362f7f0f035SAndreas Fenkart return mmc_pdata(host)->set_power(dev, power_on, vdd); 363f7f0f035SAndreas Fenkart 364db0fefc5SAdrian Hunter /* 365db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 366db0fefc5SAdrian Hunter * voltage always-on regulator. 367db0fefc5SAdrian Hunter */ 368aa9a6801SKishon Vijay Abraham I if (!mmc->supply.vmmc) 369db0fefc5SAdrian Hunter return 0; 370db0fefc5SAdrian Hunter 371326119c9SAndreas Fenkart if (mmc_pdata(host)->before_set_reg) 37280412ca8SAndreas Fenkart mmc_pdata(host)->before_set_reg(dev, power_on, vdd); 373db0fefc5SAdrian Hunter 374ec85c95eSKishon Vijay Abraham I ret = omap_hsmmc_set_pbias(host, false, 0); 375ec85c95eSKishon Vijay Abraham I if (ret) 376229f3292SKishon Vijay Abraham I return ret; 377e99448ffSBalaji T K 378db0fefc5SAdrian Hunter /* 379db0fefc5SAdrian Hunter * Assume Vcc regulator is used only to power the card ... OMAP 380db0fefc5SAdrian Hunter * VDDS is used to power the pins, optionally with a transceiver to 381db0fefc5SAdrian Hunter * support cards using voltages other than VDDS (1.8V nominal). When a 382db0fefc5SAdrian Hunter * transceiver is used, DAT3..7 are muxed as transceiver control pins. 383db0fefc5SAdrian Hunter * 384db0fefc5SAdrian Hunter * In some cases this regulator won't support enable/disable; 385db0fefc5SAdrian Hunter * e.g. it's a fixed rail for a WLAN chip. 386db0fefc5SAdrian Hunter * 387db0fefc5SAdrian Hunter * In other cases vcc_aux switches interface power. Example, for 388db0fefc5SAdrian Hunter * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 389db0fefc5SAdrian Hunter * chips/cards need an interface voltage rail too. 390db0fefc5SAdrian Hunter */ 391db0fefc5SAdrian Hunter if (power_on) { 3921d17f30bSKishon Vijay Abraham I ret = omap_hsmmc_enable_supply(mmc); 393229f3292SKishon Vijay Abraham I if (ret) 394229f3292SKishon Vijay Abraham I return ret; 39597fe7e5aSKishon Vijay Abraham I 39697fe7e5aSKishon Vijay Abraham I ret = omap_hsmmc_set_pbias(host, true, vdd); 39797fe7e5aSKishon Vijay Abraham I if (ret) 39897fe7e5aSKishon Vijay Abraham I goto err_set_voltage; 399db0fefc5SAdrian Hunter } else { 4002a17f844SKishon Vijay Abraham I ret = omap_hsmmc_disable_supply(mmc); 401229f3292SKishon Vijay Abraham I if (ret) 402229f3292SKishon Vijay Abraham I return ret; 40399fc5131SLinus Walleij } 404db0fefc5SAdrian Hunter 405326119c9SAndreas Fenkart if (mmc_pdata(host)->after_set_reg) 40680412ca8SAndreas Fenkart mmc_pdata(host)->after_set_reg(dev, power_on, vdd); 407db0fefc5SAdrian Hunter 408229f3292SKishon Vijay Abraham I return 0; 409229f3292SKishon Vijay Abraham I 410229f3292SKishon Vijay Abraham I err_set_voltage: 4112a17f844SKishon Vijay Abraham I omap_hsmmc_disable_supply(mmc); 412229f3292SKishon Vijay Abraham I 413db0fefc5SAdrian Hunter return ret; 414db0fefc5SAdrian Hunter } 415db0fefc5SAdrian Hunter 416c8518efaSKishon Vijay Abraham I static int omap_hsmmc_disable_boot_regulator(struct regulator *reg) 417c8518efaSKishon Vijay Abraham I { 418c8518efaSKishon Vijay Abraham I int ret; 419c8518efaSKishon Vijay Abraham I 420c8518efaSKishon Vijay Abraham I if (!reg) 421c8518efaSKishon Vijay Abraham I return 0; 422c8518efaSKishon Vijay Abraham I 423c8518efaSKishon Vijay Abraham I if (regulator_is_enabled(reg)) { 424c8518efaSKishon Vijay Abraham I ret = regulator_enable(reg); 425c8518efaSKishon Vijay Abraham I if (ret) 426c8518efaSKishon Vijay Abraham I return ret; 427c8518efaSKishon Vijay Abraham I 428c8518efaSKishon Vijay Abraham I ret = regulator_disable(reg); 429c8518efaSKishon Vijay Abraham I if (ret) 430c8518efaSKishon Vijay Abraham I return ret; 431c8518efaSKishon Vijay Abraham I } 432c8518efaSKishon Vijay Abraham I 433c8518efaSKishon Vijay Abraham I return 0; 434c8518efaSKishon Vijay Abraham I } 435c8518efaSKishon Vijay Abraham I 436c8518efaSKishon Vijay Abraham I static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host) 437c8518efaSKishon Vijay Abraham I { 438c8518efaSKishon Vijay Abraham I struct mmc_host *mmc = host->mmc; 439c8518efaSKishon Vijay Abraham I int ret; 440c8518efaSKishon Vijay Abraham I 441c8518efaSKishon Vijay Abraham I /* 442c8518efaSKishon Vijay Abraham I * disable regulators enabled during boot and get the usecount 443c8518efaSKishon Vijay Abraham I * right so that regulators can be enabled/disabled by checking 444c8518efaSKishon Vijay Abraham I * the return value of regulator_is_enabled 445c8518efaSKishon Vijay Abraham I */ 446c8518efaSKishon Vijay Abraham I ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc); 447c8518efaSKishon Vijay Abraham I if (ret) { 448c8518efaSKishon Vijay Abraham I dev_err(host->dev, "fail to disable boot enabled vmmc reg\n"); 449c8518efaSKishon Vijay Abraham I return ret; 450c8518efaSKishon Vijay Abraham I } 451c8518efaSKishon Vijay Abraham I 452c8518efaSKishon Vijay Abraham I ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc); 453c8518efaSKishon Vijay Abraham I if (ret) { 454c8518efaSKishon Vijay Abraham I dev_err(host->dev, 455c8518efaSKishon Vijay Abraham I "fail to disable boot enabled vmmc_aux reg\n"); 456c8518efaSKishon Vijay Abraham I return ret; 457c8518efaSKishon Vijay Abraham I } 458c8518efaSKishon Vijay Abraham I 459c8518efaSKishon Vijay Abraham I ret = omap_hsmmc_disable_boot_regulator(host->pbias); 460c8518efaSKishon Vijay Abraham I if (ret) { 461c8518efaSKishon Vijay Abraham I dev_err(host->dev, 462c8518efaSKishon Vijay Abraham I "failed to disable boot enabled pbias reg\n"); 463c8518efaSKishon Vijay Abraham I return ret; 464c8518efaSKishon Vijay Abraham I } 465c8518efaSKishon Vijay Abraham I 466c8518efaSKishon Vijay Abraham I return 0; 467c8518efaSKishon Vijay Abraham I } 468c8518efaSKishon Vijay Abraham I 469db0fefc5SAdrian Hunter static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 470db0fefc5SAdrian Hunter { 47164be9782Skishore kadiyala int ocr_value = 0; 4727d607f91SKishon Vijay Abraham I int ret; 473aa9a6801SKishon Vijay Abraham I struct mmc_host *mmc = host->mmc; 474db0fefc5SAdrian Hunter 475f7f0f035SAndreas Fenkart if (mmc_pdata(host)->set_power) 476f7f0f035SAndreas Fenkart return 0; 477f7f0f035SAndreas Fenkart 478aa9a6801SKishon Vijay Abraham I mmc->supply.vmmc = devm_regulator_get_optional(host->dev, "vmmc"); 479aa9a6801SKishon Vijay Abraham I if (IS_ERR(mmc->supply.vmmc)) { 480aa9a6801SKishon Vijay Abraham I ret = PTR_ERR(mmc->supply.vmmc); 481123e20b1STony Lindgren if ((ret != -ENODEV) && host->dev->of_node) 4827d607f91SKishon Vijay Abraham I return ret; 4837d607f91SKishon Vijay Abraham I dev_dbg(host->dev, "unable to get vmmc regulator %ld\n", 484aa9a6801SKishon Vijay Abraham I PTR_ERR(mmc->supply.vmmc)); 485aa9a6801SKishon Vijay Abraham I mmc->supply.vmmc = NULL; 486db0fefc5SAdrian Hunter } else { 487aa9a6801SKishon Vijay Abraham I ocr_value = mmc_regulator_get_ocrmask(mmc->supply.vmmc); 488b49069fcSKishon Vijay Abraham I if (ocr_value > 0) 489326119c9SAndreas Fenkart mmc_pdata(host)->ocr_mask = ocr_value; 490987fd49bSBalaji T K } 491db0fefc5SAdrian Hunter 492db0fefc5SAdrian Hunter /* Allow an aux regulator */ 493aa9a6801SKishon Vijay Abraham I mmc->supply.vqmmc = devm_regulator_get_optional(host->dev, "vmmc_aux"); 494aa9a6801SKishon Vijay Abraham I if (IS_ERR(mmc->supply.vqmmc)) { 495aa9a6801SKishon Vijay Abraham I ret = PTR_ERR(mmc->supply.vqmmc); 496123e20b1STony Lindgren if ((ret != -ENODEV) && host->dev->of_node) 4976a9b2ff0SKishon Vijay Abraham I return ret; 4986a9b2ff0SKishon Vijay Abraham I dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n", 499aa9a6801SKishon Vijay Abraham I PTR_ERR(mmc->supply.vqmmc)); 500aa9a6801SKishon Vijay Abraham I mmc->supply.vqmmc = NULL; 5016a9b2ff0SKishon Vijay Abraham I } 502db0fefc5SAdrian Hunter 503c299dc39SKishon Vijay Abraham I host->pbias = devm_regulator_get_optional(host->dev, "pbias"); 504c299dc39SKishon Vijay Abraham I if (IS_ERR(host->pbias)) { 505c299dc39SKishon Vijay Abraham I ret = PTR_ERR(host->pbias); 506123e20b1STony Lindgren if ((ret != -ENODEV) && host->dev->of_node) 5076a9b2ff0SKishon Vijay Abraham I return ret; 5086a9b2ff0SKishon Vijay Abraham I dev_dbg(host->dev, "unable to get pbias regulator %ld\n", 509c299dc39SKishon Vijay Abraham I PTR_ERR(host->pbias)); 510c299dc39SKishon Vijay Abraham I host->pbias = NULL; 5116a9b2ff0SKishon Vijay Abraham I } 512e99448ffSBalaji T K 513b1c1df7aSBalaji T K /* For eMMC do not power off when not in sleep state */ 514326119c9SAndreas Fenkart if (mmc_pdata(host)->no_regulator_off_init) 515b1c1df7aSBalaji T K return 0; 516e840ce13SAdrian Hunter 517c8518efaSKishon Vijay Abraham I ret = omap_hsmmc_disable_boot_regulators(host); 518c8518efaSKishon Vijay Abraham I if (ret) 519c8518efaSKishon Vijay Abraham I return ret; 520db0fefc5SAdrian Hunter 521db0fefc5SAdrian Hunter return 0; 522db0fefc5SAdrian Hunter } 523db0fefc5SAdrian Hunter 524cde592cbSAndreas Fenkart static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id); 52541afa314SNeilBrown 52641afa314SNeilBrown static int omap_hsmmc_gpio_init(struct mmc_host *mmc, 52741afa314SNeilBrown struct omap_hsmmc_host *host, 5281e363e3bSAndreas Fenkart struct omap_hsmmc_platform_data *pdata) 529b702b106SAdrian Hunter { 530b702b106SAdrian Hunter int ret; 531b702b106SAdrian Hunter 532b7a5646fSAndreas Fenkart if (gpio_is_valid(pdata->gpio_cod)) { 533b7a5646fSAndreas Fenkart ret = mmc_gpio_request_cd(mmc, pdata->gpio_cod, 0); 534b702b106SAdrian Hunter if (ret) 535b702b106SAdrian Hunter return ret; 536cde592cbSAndreas Fenkart 537cde592cbSAndreas Fenkart host->get_cover_state = omap_hsmmc_get_cover_state; 538cde592cbSAndreas Fenkart mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq); 539b7a5646fSAndreas Fenkart } else if (gpio_is_valid(pdata->gpio_cd)) { 540b7a5646fSAndreas Fenkart ret = mmc_gpio_request_cd(mmc, pdata->gpio_cd, 0); 541cde592cbSAndreas Fenkart if (ret) 542cde592cbSAndreas Fenkart return ret; 543cde592cbSAndreas Fenkart 544cde592cbSAndreas Fenkart host->card_detect = omap_hsmmc_card_detect; 545326119c9SAndreas Fenkart } 546b702b106SAdrian Hunter 547326119c9SAndreas Fenkart if (gpio_is_valid(pdata->gpio_wp)) { 54841afa314SNeilBrown ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp); 549b702b106SAdrian Hunter if (ret) 55041afa314SNeilBrown return ret; 551326119c9SAndreas Fenkart } 552b702b106SAdrian Hunter 553b702b106SAdrian Hunter return 0; 554b702b106SAdrian Hunter } 555b702b106SAdrian Hunter 556a45c6cb8SMadhusudhan Chikkature /* 557e0c7f99bSAndy Shevchenko * Start clock to the card 558e0c7f99bSAndy Shevchenko */ 559e0c7f99bSAndy Shevchenko static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 560e0c7f99bSAndy Shevchenko { 561e0c7f99bSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 562e0c7f99bSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 563e0c7f99bSAndy Shevchenko } 564e0c7f99bSAndy Shevchenko 565e0c7f99bSAndy Shevchenko /* 566a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 567a45c6cb8SMadhusudhan Chikkature */ 56870a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 569a45c6cb8SMadhusudhan Chikkature { 570a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 571a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 572a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 5737122bbb0SMasanari Iida dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); 574a45c6cb8SMadhusudhan Chikkature } 575a45c6cb8SMadhusudhan Chikkature 57693caf8e6SAdrian Hunter static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 57793caf8e6SAdrian Hunter struct mmc_command *cmd) 578b417577dSAdrian Hunter { 5792cd3a2a5SAndreas Fenkart u32 irq_mask = INT_EN_MASK; 5802cd3a2a5SAndreas Fenkart unsigned long flags; 581b417577dSAdrian Hunter 582b417577dSAdrian Hunter if (host->use_dma) 5832cd3a2a5SAndreas Fenkart irq_mask &= ~(BRR_EN | BWR_EN); 584b417577dSAdrian Hunter 58593caf8e6SAdrian Hunter /* Disable timeout for erases */ 58693caf8e6SAdrian Hunter if (cmd->opcode == MMC_ERASE) 587a7e96879SVenkatraman S irq_mask &= ~DTO_EN; 58893caf8e6SAdrian Hunter 5892cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 590b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 591b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 5922cd3a2a5SAndreas Fenkart 5932cd3a2a5SAndreas Fenkart /* latch pending CIRQ, but don't signal MMC core */ 5942cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 5952cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 596b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 5972cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 598b417577dSAdrian Hunter } 599b417577dSAdrian Hunter 600b417577dSAdrian Hunter static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 601b417577dSAdrian Hunter { 6022cd3a2a5SAndreas Fenkart u32 irq_mask = 0; 6032cd3a2a5SAndreas Fenkart unsigned long flags; 6042cd3a2a5SAndreas Fenkart 6052cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 6062cd3a2a5SAndreas Fenkart /* no transfer running but need to keep cirq if enabled */ 6072cd3a2a5SAndreas Fenkart if (host->flags & HSMMC_SDIO_IRQ_ENABLED) 6082cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 6092cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 6102cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 611b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 6122cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 613b417577dSAdrian Hunter } 614b417577dSAdrian Hunter 615ac330f44SAndy Shevchenko /* Calculate divisor for the given clock frequency */ 616d83b6e03SBalaji TK static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 617ac330f44SAndy Shevchenko { 618ac330f44SAndy Shevchenko u16 dsor = 0; 619ac330f44SAndy Shevchenko 620ac330f44SAndy Shevchenko if (ios->clock) { 621d83b6e03SBalaji TK dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 622ed164182SBalaji T K if (dsor > CLKD_MAX) 623ed164182SBalaji T K dsor = CLKD_MAX; 624ac330f44SAndy Shevchenko } 625ac330f44SAndy Shevchenko 626ac330f44SAndy Shevchenko return dsor; 627ac330f44SAndy Shevchenko } 628ac330f44SAndy Shevchenko 6295934df2fSAndy Shevchenko static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 6305934df2fSAndy Shevchenko { 6315934df2fSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6325934df2fSAndy Shevchenko unsigned long regval; 6335934df2fSAndy Shevchenko unsigned long timeout; 634cd587096SHebbar, Gururaja unsigned long clkdiv; 6355934df2fSAndy Shevchenko 6368986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 6375934df2fSAndy Shevchenko 6385934df2fSAndy Shevchenko omap_hsmmc_stop_clock(host); 6395934df2fSAndy Shevchenko 6405934df2fSAndy Shevchenko regval = OMAP_HSMMC_READ(host->base, SYSCTL); 6415934df2fSAndy Shevchenko regval = regval & ~(CLKD_MASK | DTO_MASK); 642cd587096SHebbar, Gururaja clkdiv = calc_divisor(host, ios); 643cd587096SHebbar, Gururaja regval = regval | (clkdiv << 6) | (DTO << 16); 6445934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 6455934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 6465934df2fSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 6475934df2fSAndy Shevchenko 6485934df2fSAndy Shevchenko /* Wait till the ICS bit is set */ 6495934df2fSAndy Shevchenko timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 6505934df2fSAndy Shevchenko while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 6515934df2fSAndy Shevchenko && time_before(jiffies, timeout)) 6525934df2fSAndy Shevchenko cpu_relax(); 6535934df2fSAndy Shevchenko 654cd587096SHebbar, Gururaja /* 655cd587096SHebbar, Gururaja * Enable High-Speed Support 656cd587096SHebbar, Gururaja * Pre-Requisites 657cd587096SHebbar, Gururaja * - Controller should support High-Speed-Enable Bit 658cd587096SHebbar, Gururaja * - Controller should not be using DDR Mode 659cd587096SHebbar, Gururaja * - Controller should advertise that it supports High Speed 660cd587096SHebbar, Gururaja * in capabilities register 661cd587096SHebbar, Gururaja * - MMC/SD clock coming out of controller > 25MHz 662cd587096SHebbar, Gururaja */ 663326119c9SAndreas Fenkart if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) && 6645438ad95SSeungwon Jeon (ios->timing != MMC_TIMING_MMC_DDR52) && 665903101a8SUlf Hansson (ios->timing != MMC_TIMING_UHS_DDR50) && 666cd587096SHebbar, Gururaja ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 667cd587096SHebbar, Gururaja regval = OMAP_HSMMC_READ(host->base, HCTL); 668cd587096SHebbar, Gururaja if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 669cd587096SHebbar, Gururaja regval |= HSPE; 670cd587096SHebbar, Gururaja else 671cd587096SHebbar, Gururaja regval &= ~HSPE; 672cd587096SHebbar, Gururaja 673cd587096SHebbar, Gururaja OMAP_HSMMC_WRITE(host->base, HCTL, regval); 674cd587096SHebbar, Gururaja } 675cd587096SHebbar, Gururaja 6765934df2fSAndy Shevchenko omap_hsmmc_start_clock(host); 6775934df2fSAndy Shevchenko } 6785934df2fSAndy Shevchenko 6793796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 6803796fb8aSAndy Shevchenko { 6813796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 6823796fb8aSAndy Shevchenko u32 con; 6833796fb8aSAndy Shevchenko 6843796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 685903101a8SUlf Hansson if (ios->timing == MMC_TIMING_MMC_DDR52 || 686903101a8SUlf Hansson ios->timing == MMC_TIMING_UHS_DDR50) 68703b5d924SBalaji T K con |= DDR; /* configure in DDR mode */ 68803b5d924SBalaji T K else 68903b5d924SBalaji T K con &= ~DDR; 6903796fb8aSAndy Shevchenko switch (ios->bus_width) { 6913796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_8: 6923796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 6933796fb8aSAndy Shevchenko break; 6943796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_4: 6953796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 6963796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 6973796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 6983796fb8aSAndy Shevchenko break; 6993796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_1: 7003796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 7013796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 7023796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 7033796fb8aSAndy Shevchenko break; 7043796fb8aSAndy Shevchenko } 7053796fb8aSAndy Shevchenko } 7063796fb8aSAndy Shevchenko 7073796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 7083796fb8aSAndy Shevchenko { 7093796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 7103796fb8aSAndy Shevchenko u32 con; 7113796fb8aSAndy Shevchenko 7123796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 7133796fb8aSAndy Shevchenko if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 7143796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | OD); 7153796fb8aSAndy Shevchenko else 7163796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 7173796fb8aSAndy Shevchenko } 7183796fb8aSAndy Shevchenko 71911dd62a7SDenis Karpov #ifdef CONFIG_PM 72011dd62a7SDenis Karpov 72111dd62a7SDenis Karpov /* 72211dd62a7SDenis Karpov * Restore the MMC host context, if it was lost as result of a 72311dd62a7SDenis Karpov * power state change. 72411dd62a7SDenis Karpov */ 72570a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 72611dd62a7SDenis Karpov { 72711dd62a7SDenis Karpov struct mmc_ios *ios = &host->mmc->ios; 7283796fb8aSAndy Shevchenko u32 hctl, capa; 72911dd62a7SDenis Karpov unsigned long timeout; 73011dd62a7SDenis Karpov 7310a82e06eSTony Lindgren if (host->con == OMAP_HSMMC_READ(host->base, CON) && 7320a82e06eSTony Lindgren host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && 7330a82e06eSTony Lindgren host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && 7340a82e06eSTony Lindgren host->capa == OMAP_HSMMC_READ(host->base, CAPA)) 7350a82e06eSTony Lindgren return 0; 7360a82e06eSTony Lindgren 7370a82e06eSTony Lindgren host->context_loss++; 7380a82e06eSTony Lindgren 739c2200efbSBalaji T K if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 74011dd62a7SDenis Karpov if (host->power_mode != MMC_POWER_OFF && 74111dd62a7SDenis Karpov (1 << ios->vdd) <= MMC_VDD_23_24) 74211dd62a7SDenis Karpov hctl = SDVS18; 74311dd62a7SDenis Karpov else 74411dd62a7SDenis Karpov hctl = SDVS30; 74511dd62a7SDenis Karpov capa = VS30 | VS18; 74611dd62a7SDenis Karpov } else { 74711dd62a7SDenis Karpov hctl = SDVS18; 74811dd62a7SDenis Karpov capa = VS18; 74911dd62a7SDenis Karpov } 75011dd62a7SDenis Karpov 7515a52b08bSBalaji T K if (host->mmc->caps & MMC_CAP_SDIO_IRQ) 7525a52b08bSBalaji T K hctl |= IWE; 7535a52b08bSBalaji T K 75411dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 75511dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | hctl); 75611dd62a7SDenis Karpov 75711dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CAPA, 75811dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA) | capa); 75911dd62a7SDenis Karpov 76011dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 76111dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 76211dd62a7SDenis Karpov 76311dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 76411dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 76511dd62a7SDenis Karpov && time_before(jiffies, timeout)) 76611dd62a7SDenis Karpov ; 76711dd62a7SDenis Karpov 7682cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 7692cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 7702cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 77111dd62a7SDenis Karpov 77211dd62a7SDenis Karpov /* Do not initialize card-specific things if the power is off */ 77311dd62a7SDenis Karpov if (host->power_mode == MMC_POWER_OFF) 77411dd62a7SDenis Karpov goto out; 77511dd62a7SDenis Karpov 7763796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 77711dd62a7SDenis Karpov 7785934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 77911dd62a7SDenis Karpov 7803796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 7813796fb8aSAndy Shevchenko 78211dd62a7SDenis Karpov out: 7830a82e06eSTony Lindgren dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", 7840a82e06eSTony Lindgren host->context_loss); 78511dd62a7SDenis Karpov return 0; 78611dd62a7SDenis Karpov } 78711dd62a7SDenis Karpov 78811dd62a7SDenis Karpov /* 78911dd62a7SDenis Karpov * Save the MMC host context (store the number of power state changes so far). 79011dd62a7SDenis Karpov */ 79170a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 79211dd62a7SDenis Karpov { 7930a82e06eSTony Lindgren host->con = OMAP_HSMMC_READ(host->base, CON); 7940a82e06eSTony Lindgren host->hctl = OMAP_HSMMC_READ(host->base, HCTL); 7950a82e06eSTony Lindgren host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); 7960a82e06eSTony Lindgren host->capa = OMAP_HSMMC_READ(host->base, CAPA); 79711dd62a7SDenis Karpov } 79811dd62a7SDenis Karpov 79911dd62a7SDenis Karpov #else 80011dd62a7SDenis Karpov 80170a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 80211dd62a7SDenis Karpov { 80311dd62a7SDenis Karpov return 0; 80411dd62a7SDenis Karpov } 80511dd62a7SDenis Karpov 80670a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 80711dd62a7SDenis Karpov { 80811dd62a7SDenis Karpov } 80911dd62a7SDenis Karpov 81011dd62a7SDenis Karpov #endif 81111dd62a7SDenis Karpov 812a45c6cb8SMadhusudhan Chikkature /* 813a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 814a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 815a45c6cb8SMadhusudhan Chikkature */ 81670a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host) 817a45c6cb8SMadhusudhan Chikkature { 818a45c6cb8SMadhusudhan Chikkature int reg = 0; 819a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 820a45c6cb8SMadhusudhan Chikkature 821b62f6228SAdrian Hunter if (host->protect_card) 822b62f6228SAdrian Hunter return; 823b62f6228SAdrian Hunter 824a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 825b417577dSAdrian Hunter 826b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 827a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 828a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 829a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 830a45c6cb8SMadhusudhan Chikkature 831a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 832a7e96879SVenkatraman S while ((reg != CC_EN) && time_before(jiffies, timeout)) 833a7e96879SVenkatraman S reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; 834a45c6cb8SMadhusudhan Chikkature 835a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 836a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 837c653a6d4SAdrian Hunter 838c653a6d4SAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 839c653a6d4SAdrian Hunter OMAP_HSMMC_READ(host->base, STAT); 840c653a6d4SAdrian Hunter 841a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 842a45c6cb8SMadhusudhan Chikkature } 843a45c6cb8SMadhusudhan Chikkature 844a45c6cb8SMadhusudhan Chikkature static inline 84570a3341aSDenis Karpov int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 846a45c6cb8SMadhusudhan Chikkature { 847a45c6cb8SMadhusudhan Chikkature int r = 1; 848a45c6cb8SMadhusudhan Chikkature 849b5cd43f0SAndreas Fenkart if (host->get_cover_state) 85080412ca8SAndreas Fenkart r = host->get_cover_state(host->dev); 851a45c6cb8SMadhusudhan Chikkature return r; 852a45c6cb8SMadhusudhan Chikkature } 853a45c6cb8SMadhusudhan Chikkature 854a45c6cb8SMadhusudhan Chikkature static ssize_t 85570a3341aSDenis Karpov omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 856a45c6cb8SMadhusudhan Chikkature char *buf) 857a45c6cb8SMadhusudhan Chikkature { 858a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 85970a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 860a45c6cb8SMadhusudhan Chikkature 86170a3341aSDenis Karpov return sprintf(buf, "%s\n", 86270a3341aSDenis Karpov omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 863a45c6cb8SMadhusudhan Chikkature } 864a45c6cb8SMadhusudhan Chikkature 86570a3341aSDenis Karpov static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 866a45c6cb8SMadhusudhan Chikkature 867a45c6cb8SMadhusudhan Chikkature static ssize_t 86870a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 869a45c6cb8SMadhusudhan Chikkature char *buf) 870a45c6cb8SMadhusudhan Chikkature { 871a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 87270a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 873a45c6cb8SMadhusudhan Chikkature 874326119c9SAndreas Fenkart return sprintf(buf, "%s\n", mmc_pdata(host)->name); 875a45c6cb8SMadhusudhan Chikkature } 876a45c6cb8SMadhusudhan Chikkature 87770a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 878a45c6cb8SMadhusudhan Chikkature 879a45c6cb8SMadhusudhan Chikkature /* 880a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 881a45c6cb8SMadhusudhan Chikkature */ 882a45c6cb8SMadhusudhan Chikkature static void 88370a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 884a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 885a45c6cb8SMadhusudhan Chikkature { 886a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 887a45c6cb8SMadhusudhan Chikkature 8888986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 889a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 890a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 891a45c6cb8SMadhusudhan Chikkature 89293caf8e6SAdrian Hunter omap_hsmmc_enable_irq(host, cmd); 893a45c6cb8SMadhusudhan Chikkature 8944a694dc9SAdrian Hunter host->response_busy = 0; 895a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 896a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 897a45c6cb8SMadhusudhan Chikkature resptype = 1; 8984a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 8994a694dc9SAdrian Hunter resptype = 3; 9004a694dc9SAdrian Hunter host->response_busy = 1; 9014a694dc9SAdrian Hunter } else 902a45c6cb8SMadhusudhan Chikkature resptype = 2; 903a45c6cb8SMadhusudhan Chikkature } 904a45c6cb8SMadhusudhan Chikkature 905a45c6cb8SMadhusudhan Chikkature /* 906a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 907a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 908a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 909a45c6cb8SMadhusudhan Chikkature */ 910a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 911a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 912a45c6cb8SMadhusudhan Chikkature 913a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 914a45c6cb8SMadhusudhan Chikkature 915a2e77152SBalaji T K if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) && 916a2e77152SBalaji T K host->mrq->sbc) { 917a2e77152SBalaji T K cmdreg |= ACEN_ACMD23; 918a2e77152SBalaji T K OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg); 919a2e77152SBalaji T K } 920a45c6cb8SMadhusudhan Chikkature if (data) { 921a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 922a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 923a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 924a45c6cb8SMadhusudhan Chikkature else 925a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 926a45c6cb8SMadhusudhan Chikkature } 927a45c6cb8SMadhusudhan Chikkature 928a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 929a7e96879SVenkatraman S cmdreg |= DMAE; 930a45c6cb8SMadhusudhan Chikkature 931b417577dSAdrian Hunter host->req_in_progress = 1; 9324dffd7a2SAdrian Hunter 933a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 934a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 935a45c6cb8SMadhusudhan Chikkature } 936a45c6cb8SMadhusudhan Chikkature 9370ccd76d4SJuha Yrjola static int 93870a3341aSDenis Karpov omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 9390ccd76d4SJuha Yrjola { 9400ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) 9410ccd76d4SJuha Yrjola return DMA_TO_DEVICE; 9420ccd76d4SJuha Yrjola else 9430ccd76d4SJuha Yrjola return DMA_FROM_DEVICE; 9440ccd76d4SJuha Yrjola } 9450ccd76d4SJuha Yrjola 946c5c98927SRussell King static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 947c5c98927SRussell King struct mmc_data *data) 948c5c98927SRussell King { 949c5c98927SRussell King return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 950c5c98927SRussell King } 951c5c98927SRussell King 952b417577dSAdrian Hunter static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 953b417577dSAdrian Hunter { 954b417577dSAdrian Hunter int dma_ch; 95531463b14SVenkatraman S unsigned long flags; 956b417577dSAdrian Hunter 95731463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 958b417577dSAdrian Hunter host->req_in_progress = 0; 959b417577dSAdrian Hunter dma_ch = host->dma_ch; 96031463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 961b417577dSAdrian Hunter 962b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 963b417577dSAdrian Hunter /* Do not complete the request if DMA is still in progress */ 964b417577dSAdrian Hunter if (mrq->data && host->use_dma && dma_ch != -1) 965b417577dSAdrian Hunter return; 966b417577dSAdrian Hunter host->mrq = NULL; 967b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 968f57ba4caSNeilBrown pm_runtime_mark_last_busy(host->dev); 969f57ba4caSNeilBrown pm_runtime_put_autosuspend(host->dev); 970b417577dSAdrian Hunter } 971b417577dSAdrian Hunter 972a45c6cb8SMadhusudhan Chikkature /* 973a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 974a45c6cb8SMadhusudhan Chikkature */ 975a45c6cb8SMadhusudhan Chikkature static void 97670a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 977a45c6cb8SMadhusudhan Chikkature { 9784a694dc9SAdrian Hunter if (!data) { 9794a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 9804a694dc9SAdrian Hunter 98123050103SAdrian Hunter /* TC before CC from CMD6 - don't know why, but it happens */ 98223050103SAdrian Hunter if (host->cmd && host->cmd->opcode == 6 && 98323050103SAdrian Hunter host->response_busy) { 98423050103SAdrian Hunter host->response_busy = 0; 98523050103SAdrian Hunter return; 98623050103SAdrian Hunter } 98723050103SAdrian Hunter 988b417577dSAdrian Hunter omap_hsmmc_request_done(host, mrq); 9894a694dc9SAdrian Hunter return; 9904a694dc9SAdrian Hunter } 9914a694dc9SAdrian Hunter 992a45c6cb8SMadhusudhan Chikkature host->data = NULL; 993a45c6cb8SMadhusudhan Chikkature 994a45c6cb8SMadhusudhan Chikkature if (!data->error) 995a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 996a45c6cb8SMadhusudhan Chikkature else 997a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 998a45c6cb8SMadhusudhan Chikkature 999bf129e1cSBalaji T K if (data->stop && (data->error || !host->mrq->sbc)) 1000fe852273SMing Lei omap_hsmmc_start_command(host, data->stop, NULL); 1001bf129e1cSBalaji T K else 1002bf129e1cSBalaji T K omap_hsmmc_request_done(host, data->mrq); 1003a45c6cb8SMadhusudhan Chikkature } 1004a45c6cb8SMadhusudhan Chikkature 1005a45c6cb8SMadhusudhan Chikkature /* 1006a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 1007a45c6cb8SMadhusudhan Chikkature */ 1008a45c6cb8SMadhusudhan Chikkature static void 100970a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 1010a45c6cb8SMadhusudhan Chikkature { 1011bf129e1cSBalaji T K if (host->mrq->sbc && (host->cmd == host->mrq->sbc) && 1012a2e77152SBalaji T K !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) { 10132177fa94SBalaji T K host->cmd = NULL; 1014bf129e1cSBalaji T K omap_hsmmc_start_dma_transfer(host); 1015bf129e1cSBalaji T K omap_hsmmc_start_command(host, host->mrq->cmd, 1016bf129e1cSBalaji T K host->mrq->data); 1017bf129e1cSBalaji T K return; 1018bf129e1cSBalaji T K } 1019bf129e1cSBalaji T K 10202177fa94SBalaji T K host->cmd = NULL; 10212177fa94SBalaji T K 1022a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 1023a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 1024a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 1025a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 1026a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 1027a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 1028a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 1029a45c6cb8SMadhusudhan Chikkature } else { 1030a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 1031a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 1032a45c6cb8SMadhusudhan Chikkature } 1033a45c6cb8SMadhusudhan Chikkature } 1034b417577dSAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) 1035d4b2c375SBalaji T K omap_hsmmc_request_done(host, host->mrq); 1036a45c6cb8SMadhusudhan Chikkature } 1037a45c6cb8SMadhusudhan Chikkature 1038a45c6cb8SMadhusudhan Chikkature /* 1039a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 1040a45c6cb8SMadhusudhan Chikkature */ 104170a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 1042a45c6cb8SMadhusudhan Chikkature { 1043b417577dSAdrian Hunter int dma_ch; 104431463b14SVenkatraman S unsigned long flags; 1045b417577dSAdrian Hunter 104682788ff5SJarkko Lavinen host->data->error = errno; 1047a45c6cb8SMadhusudhan Chikkature 104831463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 1049b417577dSAdrian Hunter dma_ch = host->dma_ch; 1050b417577dSAdrian Hunter host->dma_ch = -1; 105131463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 1052b417577dSAdrian Hunter 1053b417577dSAdrian Hunter if (host->use_dma && dma_ch != -1) { 1054c5c98927SRussell King struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 1055c5c98927SRussell King 1056c5c98927SRussell King dmaengine_terminate_all(chan); 1057c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1058c5c98927SRussell King host->data->sg, host->data->sg_len, 105970a3341aSDenis Karpov omap_hsmmc_get_dma_dir(host, host->data)); 1060c5c98927SRussell King 1061053bf34fSPer Forlin host->data->host_cookie = 0; 1062a45c6cb8SMadhusudhan Chikkature } 1063a45c6cb8SMadhusudhan Chikkature host->data = NULL; 1064a45c6cb8SMadhusudhan Chikkature } 1065a45c6cb8SMadhusudhan Chikkature 1066a45c6cb8SMadhusudhan Chikkature /* 1067a45c6cb8SMadhusudhan Chikkature * Readable error output 1068a45c6cb8SMadhusudhan Chikkature */ 1069a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 1070699b958bSAdrian Hunter static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 1071a45c6cb8SMadhusudhan Chikkature { 1072a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 107370a3341aSDenis Karpov static const char *omap_hsmmc_status_bits[] = { 1074699b958bSAdrian Hunter "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 1075699b958bSAdrian Hunter "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 1076699b958bSAdrian Hunter "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 1077699b958bSAdrian Hunter "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 1078a45c6cb8SMadhusudhan Chikkature }; 1079a45c6cb8SMadhusudhan Chikkature char res[256]; 1080a45c6cb8SMadhusudhan Chikkature char *buf = res; 1081a45c6cb8SMadhusudhan Chikkature int len, i; 1082a45c6cb8SMadhusudhan Chikkature 1083a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 1084a45c6cb8SMadhusudhan Chikkature buf += len; 1085a45c6cb8SMadhusudhan Chikkature 108670a3341aSDenis Karpov for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 1087a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 108870a3341aSDenis Karpov len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 1089a45c6cb8SMadhusudhan Chikkature buf += len; 1090a45c6cb8SMadhusudhan Chikkature } 1091a45c6cb8SMadhusudhan Chikkature 10928986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 1093a45c6cb8SMadhusudhan Chikkature } 1094699b958bSAdrian Hunter #else 1095699b958bSAdrian Hunter static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 1096699b958bSAdrian Hunter u32 status) 1097699b958bSAdrian Hunter { 1098699b958bSAdrian Hunter } 1099a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 1100a45c6cb8SMadhusudhan Chikkature 11013ebf74b1SJean Pihet /* 11023ebf74b1SJean Pihet * MMC controller internal state machines reset 11033ebf74b1SJean Pihet * 11043ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 11053ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 11063ebf74b1SJean Pihet * Can be called from interrupt context 11073ebf74b1SJean Pihet */ 110870a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 11093ebf74b1SJean Pihet unsigned long bit) 11103ebf74b1SJean Pihet { 11113ebf74b1SJean Pihet unsigned long i = 0; 11121e881786SJianpeng Ma unsigned long limit = MMC_TIMEOUT_US; 11133ebf74b1SJean Pihet 11143ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 11153ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 11163ebf74b1SJean Pihet 111707ad64b6SMadhusudhan Chikkature /* 111807ad64b6SMadhusudhan Chikkature * OMAP4 ES2 and greater has an updated reset logic. 111907ad64b6SMadhusudhan Chikkature * Monitor a 0->1 transition first 112007ad64b6SMadhusudhan Chikkature */ 1121326119c9SAndreas Fenkart if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) { 1122b432b4b3Skishore kadiyala while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 112307ad64b6SMadhusudhan Chikkature && (i++ < limit)) 11241e881786SJianpeng Ma udelay(1); 112507ad64b6SMadhusudhan Chikkature } 112607ad64b6SMadhusudhan Chikkature i = 0; 112707ad64b6SMadhusudhan Chikkature 11283ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 11293ebf74b1SJean Pihet (i++ < limit)) 11301e881786SJianpeng Ma udelay(1); 11313ebf74b1SJean Pihet 11323ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 11333ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 11343ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 11353ebf74b1SJean Pihet __func__); 11363ebf74b1SJean Pihet } 1137a45c6cb8SMadhusudhan Chikkature 113825e1897bSBalaji T K static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, 113925e1897bSBalaji T K int err, int end_cmd) 1140ae4bf788SVenkatraman S { 114125e1897bSBalaji T K if (end_cmd) { 114294d4f272SBalaji T K omap_hsmmc_reset_controller_fsm(host, SRC); 114325e1897bSBalaji T K if (host->cmd) 1144ae4bf788SVenkatraman S host->cmd->error = err; 114525e1897bSBalaji T K } 1146ae4bf788SVenkatraman S 1147ae4bf788SVenkatraman S if (host->data) { 1148ae4bf788SVenkatraman S omap_hsmmc_reset_controller_fsm(host, SRD); 1149ae4bf788SVenkatraman S omap_hsmmc_dma_cleanup(host, err); 1150dc7745bdSBalaji T K } else if (host->mrq && host->mrq->cmd) 1151dc7745bdSBalaji T K host->mrq->cmd->error = err; 1152ae4bf788SVenkatraman S } 1153ae4bf788SVenkatraman S 1154b417577dSAdrian Hunter static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1155a45c6cb8SMadhusudhan Chikkature { 1156a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 1157b417577dSAdrian Hunter int end_cmd = 0, end_trans = 0; 1158a2e77152SBalaji T K int error = 0; 1159a45c6cb8SMadhusudhan Chikkature 1160a45c6cb8SMadhusudhan Chikkature data = host->data; 11618986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1162a45c6cb8SMadhusudhan Chikkature 1163a7e96879SVenkatraman S if (status & ERR_EN) { 1164699b958bSAdrian Hunter omap_hsmmc_dbg_report_irq(host, status); 11654a694dc9SAdrian Hunter 1166a7e96879SVenkatraman S if (status & (CTO_EN | CCRC_EN)) 1167a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1168408806f7SKishon Vijay Abraham I if (host->data || host->response_busy) { 1169408806f7SKishon Vijay Abraham I end_trans = !end_cmd; 1170408806f7SKishon Vijay Abraham I host->response_busy = 0; 1171408806f7SKishon Vijay Abraham I } 1172a7e96879SVenkatraman S if (status & (CTO_EN | DTO_EN)) 117325e1897bSBalaji T K hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); 11745027cd1eSVignesh R else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN | 11755027cd1eSVignesh R BADA_EN)) 117625e1897bSBalaji T K hsmmc_command_incomplete(host, -EILSEQ, end_cmd); 117725e1897bSBalaji T K 1178a2e77152SBalaji T K if (status & ACE_EN) { 1179a2e77152SBalaji T K u32 ac12; 1180a2e77152SBalaji T K ac12 = OMAP_HSMMC_READ(host->base, AC12); 1181a2e77152SBalaji T K if (!(ac12 & ACNE) && host->mrq->sbc) { 1182a2e77152SBalaji T K end_cmd = 1; 1183a2e77152SBalaji T K if (ac12 & ACTO) 1184a2e77152SBalaji T K error = -ETIMEDOUT; 1185a2e77152SBalaji T K else if (ac12 & (ACCE | ACEB | ACIE)) 1186a2e77152SBalaji T K error = -EILSEQ; 1187a2e77152SBalaji T K host->mrq->sbc->error = error; 1188a2e77152SBalaji T K hsmmc_command_incomplete(host, error, end_cmd); 1189a2e77152SBalaji T K } 1190a2e77152SBalaji T K dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12); 1191a2e77152SBalaji T K } 1192a45c6cb8SMadhusudhan Chikkature } 1193a45c6cb8SMadhusudhan Chikkature 11947472bab2SFrancesco Lavra OMAP_HSMMC_WRITE(host->base, STAT, status); 1195a7e96879SVenkatraman S if (end_cmd || ((status & CC_EN) && host->cmd)) 119670a3341aSDenis Karpov omap_hsmmc_cmd_done(host, host->cmd); 1197a7e96879SVenkatraman S if ((end_trans || (status & TC_EN)) && host->mrq) 119870a3341aSDenis Karpov omap_hsmmc_xfer_done(host, data); 1199b417577dSAdrian Hunter } 1200a45c6cb8SMadhusudhan Chikkature 1201b417577dSAdrian Hunter /* 1202b417577dSAdrian Hunter * MMC controller IRQ handler 1203b417577dSAdrian Hunter */ 1204b417577dSAdrian Hunter static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1205b417577dSAdrian Hunter { 1206b417577dSAdrian Hunter struct omap_hsmmc_host *host = dev_id; 1207b417577dSAdrian Hunter int status; 1208b417577dSAdrian Hunter 1209b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 12102cd3a2a5SAndreas Fenkart while (status & (INT_EN_MASK | CIRQ_EN)) { 12112cd3a2a5SAndreas Fenkart if (host->req_in_progress) 1212b417577dSAdrian Hunter omap_hsmmc_do_irq(host, status); 12131f6b9fa4SVenkatraman S 12142cd3a2a5SAndreas Fenkart if (status & CIRQ_EN) 12152cd3a2a5SAndreas Fenkart mmc_signal_sdio_irq(host->mmc); 12162cd3a2a5SAndreas Fenkart 1217b417577dSAdrian Hunter /* Flush posted write */ 1218b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 12191f6b9fa4SVenkatraman S } 12204dffd7a2SAdrian Hunter 1221a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1222a45c6cb8SMadhusudhan Chikkature } 1223a45c6cb8SMadhusudhan Chikkature 122470a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host) 1225e13bb300SAdrian Hunter { 1226e13bb300SAdrian Hunter unsigned long i; 1227e13bb300SAdrian Hunter 1228e13bb300SAdrian Hunter OMAP_HSMMC_WRITE(host->base, HCTL, 1229e13bb300SAdrian Hunter OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1230e13bb300SAdrian Hunter for (i = 0; i < loops_per_jiffy; i++) { 1231e13bb300SAdrian Hunter if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1232e13bb300SAdrian Hunter break; 1233e13bb300SAdrian Hunter cpu_relax(); 1234e13bb300SAdrian Hunter } 1235e13bb300SAdrian Hunter } 1236e13bb300SAdrian Hunter 1237a45c6cb8SMadhusudhan Chikkature /* 1238eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 1239eb250826SDavid Brownell * 1240eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1241eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1242eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 1243a45c6cb8SMadhusudhan Chikkature */ 124470a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1245a45c6cb8SMadhusudhan Chikkature { 1246a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 1247a45c6cb8SMadhusudhan Chikkature int ret; 1248a45c6cb8SMadhusudhan Chikkature 1249a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 1250fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 1251cd03d9a8SRajendra Nayak if (host->dbclk) 125294c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 1253a45c6cb8SMadhusudhan Chikkature 1254a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 1255f7f0f035SAndreas Fenkart ret = omap_hsmmc_set_power(host->dev, 0, 0); 1256a45c6cb8SMadhusudhan Chikkature 1257a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 12582bec0893SAdrian Hunter if (!ret) 1259f7f0f035SAndreas Fenkart ret = omap_hsmmc_set_power(host->dev, 1, vdd); 1260fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1261cd03d9a8SRajendra Nayak if (host->dbclk) 126294c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 12632bec0893SAdrian Hunter 1264a45c6cb8SMadhusudhan Chikkature if (ret != 0) 1265a45c6cb8SMadhusudhan Chikkature goto err; 1266a45c6cb8SMadhusudhan Chikkature 1267a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1268a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1269a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1270eb250826SDavid Brownell 1271a45c6cb8SMadhusudhan Chikkature /* 1272a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 1273a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 127470a3341aSDenis Karpov * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1275a45c6cb8SMadhusudhan Chikkature * 1276eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 1277eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1278eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 1279eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1280eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 1281eb250826SDavid Brownell * 1282eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 1283eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1284eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1285a45c6cb8SMadhusudhan Chikkature */ 1286eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 1287a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 1288eb250826SDavid Brownell else 1289eb250826SDavid Brownell reg_val |= SDVS30; 1290a45c6cb8SMadhusudhan Chikkature 1291a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1292e13bb300SAdrian Hunter set_sd_bus_power(host); 1293a45c6cb8SMadhusudhan Chikkature 1294a45c6cb8SMadhusudhan Chikkature return 0; 1295a45c6cb8SMadhusudhan Chikkature err: 1296b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1297a45c6cb8SMadhusudhan Chikkature return ret; 1298a45c6cb8SMadhusudhan Chikkature } 1299a45c6cb8SMadhusudhan Chikkature 1300b62f6228SAdrian Hunter /* Protect the card while the cover is open */ 1301b62f6228SAdrian Hunter static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1302b62f6228SAdrian Hunter { 1303b5cd43f0SAndreas Fenkart if (!host->get_cover_state) 1304b62f6228SAdrian Hunter return; 1305b62f6228SAdrian Hunter 1306b62f6228SAdrian Hunter host->reqs_blocked = 0; 130780412ca8SAndreas Fenkart if (host->get_cover_state(host->dev)) { 1308b62f6228SAdrian Hunter if (host->protect_card) { 13092cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is closed, " 1310b62f6228SAdrian Hunter "card is now accessible\n", 1311b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1312b62f6228SAdrian Hunter host->protect_card = 0; 1313b62f6228SAdrian Hunter } 1314b62f6228SAdrian Hunter } else { 1315b62f6228SAdrian Hunter if (!host->protect_card) { 13162cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is open, " 1317b62f6228SAdrian Hunter "card is now inaccessible\n", 1318b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1319b62f6228SAdrian Hunter host->protect_card = 1; 1320b62f6228SAdrian Hunter } 1321b62f6228SAdrian Hunter } 1322b62f6228SAdrian Hunter } 1323b62f6228SAdrian Hunter 1324a45c6cb8SMadhusudhan Chikkature /* 1325cde592cbSAndreas Fenkart * irq handler when (cell-phone) cover is mounted/removed 1326cde592cbSAndreas Fenkart */ 1327cde592cbSAndreas Fenkart static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id) 1328cde592cbSAndreas Fenkart { 1329cde592cbSAndreas Fenkart struct omap_hsmmc_host *host = dev_id; 1330cde592cbSAndreas Fenkart 1331cde592cbSAndreas Fenkart sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1332cde592cbSAndreas Fenkart 1333cde592cbSAndreas Fenkart omap_hsmmc_protect_card(host); 1334cde592cbSAndreas Fenkart mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1335cde592cbSAndreas Fenkart return IRQ_HANDLED; 1336cde592cbSAndreas Fenkart } 1337cde592cbSAndreas Fenkart 1338c5c98927SRussell King static void omap_hsmmc_dma_callback(void *param) 13390ccd76d4SJuha Yrjola { 1340c5c98927SRussell King struct omap_hsmmc_host *host = param; 1341c5c98927SRussell King struct dma_chan *chan; 1342770d7432SAdrian Hunter struct mmc_data *data; 1343c5c98927SRussell King int req_in_progress; 1344a45c6cb8SMadhusudhan Chikkature 1345c5c98927SRussell King spin_lock_irq(&host->irq_lock); 1346b417577dSAdrian Hunter if (host->dma_ch < 0) { 1347c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1348a45c6cb8SMadhusudhan Chikkature return; 1349b417577dSAdrian Hunter } 1350a45c6cb8SMadhusudhan Chikkature 1351770d7432SAdrian Hunter data = host->mrq->data; 1352c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 13539782aff8SPer Forlin if (!data->host_cookie) 1354c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1355c5c98927SRussell King data->sg, data->sg_len, 1356b417577dSAdrian Hunter omap_hsmmc_get_dma_dir(host, data)); 1357b417577dSAdrian Hunter 1358b417577dSAdrian Hunter req_in_progress = host->req_in_progress; 1359a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1360c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1361b417577dSAdrian Hunter 1362b417577dSAdrian Hunter /* If DMA has finished after TC, complete the request */ 1363b417577dSAdrian Hunter if (!req_in_progress) { 1364b417577dSAdrian Hunter struct mmc_request *mrq = host->mrq; 1365b417577dSAdrian Hunter 1366b417577dSAdrian Hunter host->mrq = NULL; 1367b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 1368f57ba4caSNeilBrown pm_runtime_mark_last_busy(host->dev); 1369f57ba4caSNeilBrown pm_runtime_put_autosuspend(host->dev); 1370b417577dSAdrian Hunter } 1371a45c6cb8SMadhusudhan Chikkature } 1372a45c6cb8SMadhusudhan Chikkature 13739782aff8SPer Forlin static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 13749782aff8SPer Forlin struct mmc_data *data, 1375c5c98927SRussell King struct omap_hsmmc_next *next, 137626b88520SRussell King struct dma_chan *chan) 13779782aff8SPer Forlin { 13789782aff8SPer Forlin int dma_len; 13799782aff8SPer Forlin 13809782aff8SPer Forlin if (!next && data->host_cookie && 13819782aff8SPer Forlin data->host_cookie != host->next_data.cookie) { 13822cecdf00SRajendra Nayak dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 13839782aff8SPer Forlin " host->next_data.cookie %d\n", 13849782aff8SPer Forlin __func__, data->host_cookie, host->next_data.cookie); 13859782aff8SPer Forlin data->host_cookie = 0; 13869782aff8SPer Forlin } 13879782aff8SPer Forlin 13889782aff8SPer Forlin /* Check if next job is already prepared */ 1389b38313d6SDan Carpenter if (next || data->host_cookie != host->next_data.cookie) { 139026b88520SRussell King dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 13919782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 13929782aff8SPer Forlin 13939782aff8SPer Forlin } else { 13949782aff8SPer Forlin dma_len = host->next_data.dma_len; 13959782aff8SPer Forlin host->next_data.dma_len = 0; 13969782aff8SPer Forlin } 13979782aff8SPer Forlin 13989782aff8SPer Forlin 13999782aff8SPer Forlin if (dma_len == 0) 14009782aff8SPer Forlin return -EINVAL; 14019782aff8SPer Forlin 14029782aff8SPer Forlin if (next) { 14039782aff8SPer Forlin next->dma_len = dma_len; 14049782aff8SPer Forlin data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 14059782aff8SPer Forlin } else 14069782aff8SPer Forlin host->dma_len = dma_len; 14079782aff8SPer Forlin 14089782aff8SPer Forlin return 0; 14099782aff8SPer Forlin } 14109782aff8SPer Forlin 1411a45c6cb8SMadhusudhan Chikkature /* 1412a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 1413a45c6cb8SMadhusudhan Chikkature */ 14149d025334SBalaji T K static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host, 141570a3341aSDenis Karpov struct mmc_request *req) 1416a45c6cb8SMadhusudhan Chikkature { 141726b88520SRussell King struct dma_slave_config cfg; 141826b88520SRussell King struct dma_async_tx_descriptor *tx; 141926b88520SRussell King int ret = 0, i; 1420a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 1421c5c98927SRussell King struct dma_chan *chan; 1422a45c6cb8SMadhusudhan Chikkature 14230ccd76d4SJuha Yrjola /* Sanity check: all the SG entries must be aligned by block size. */ 1424a3f406f8SJarkko Lavinen for (i = 0; i < data->sg_len; i++) { 14250ccd76d4SJuha Yrjola struct scatterlist *sgl; 14260ccd76d4SJuha Yrjola 14270ccd76d4SJuha Yrjola sgl = data->sg + i; 14280ccd76d4SJuha Yrjola if (sgl->length % data->blksz) 14290ccd76d4SJuha Yrjola return -EINVAL; 14300ccd76d4SJuha Yrjola } 14310ccd76d4SJuha Yrjola if ((data->blksz % 4) != 0) 14320ccd76d4SJuha Yrjola /* REVISIT: The MMC buffer increments only when MSB is written. 14330ccd76d4SJuha Yrjola * Return error for blksz which is non multiple of four. 14340ccd76d4SJuha Yrjola */ 14350ccd76d4SJuha Yrjola return -EINVAL; 14360ccd76d4SJuha Yrjola 1437b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1438a45c6cb8SMadhusudhan Chikkature 1439c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 1440c5c98927SRussell King 1441c5c98927SRussell King cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA; 1442c5c98927SRussell King cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA; 1443c5c98927SRussell King cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1444c5c98927SRussell King cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1445c5c98927SRussell King cfg.src_maxburst = data->blksz / 4; 1446c5c98927SRussell King cfg.dst_maxburst = data->blksz / 4; 1447c5c98927SRussell King 1448c5c98927SRussell King ret = dmaengine_slave_config(chan, &cfg); 14499782aff8SPer Forlin if (ret) 14509782aff8SPer Forlin return ret; 1451a45c6cb8SMadhusudhan Chikkature 145226b88520SRussell King ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1453c5c98927SRussell King if (ret) 1454c5c98927SRussell King return ret; 1455a45c6cb8SMadhusudhan Chikkature 1456c5c98927SRussell King tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1457c5c98927SRussell King data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1458c5c98927SRussell King DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1459c5c98927SRussell King if (!tx) { 1460c5c98927SRussell King dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1461c5c98927SRussell King /* FIXME: cleanup */ 1462c5c98927SRussell King return -1; 1463c5c98927SRussell King } 1464c5c98927SRussell King 1465c5c98927SRussell King tx->callback = omap_hsmmc_dma_callback; 1466c5c98927SRussell King tx->callback_param = host; 1467c5c98927SRussell King 1468c5c98927SRussell King /* Does not fail */ 1469c5c98927SRussell King dmaengine_submit(tx); 1470c5c98927SRussell King 147126b88520SRussell King host->dma_ch = 1; 1472c5c98927SRussell King 1473a45c6cb8SMadhusudhan Chikkature return 0; 1474a45c6cb8SMadhusudhan Chikkature } 1475a45c6cb8SMadhusudhan Chikkature 147670a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host, 1477e2bf08d6SAdrian Hunter unsigned int timeout_ns, 1478e2bf08d6SAdrian Hunter unsigned int timeout_clks) 1479a45c6cb8SMadhusudhan Chikkature { 1480a45c6cb8SMadhusudhan Chikkature unsigned int timeout, cycle_ns; 1481a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 1482a45c6cb8SMadhusudhan Chikkature 1483a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1484a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1485a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 1486a45c6cb8SMadhusudhan Chikkature clkd = 1; 1487a45c6cb8SMadhusudhan Chikkature 14886e3076c2SBalaji T K cycle_ns = 1000000000 / (host->clk_rate / clkd); 1489e2bf08d6SAdrian Hunter timeout = timeout_ns / cycle_ns; 1490e2bf08d6SAdrian Hunter timeout += timeout_clks; 1491a45c6cb8SMadhusudhan Chikkature if (timeout) { 1492a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 1493a45c6cb8SMadhusudhan Chikkature dto += 1; 1494a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1495a45c6cb8SMadhusudhan Chikkature } 1496a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 1497a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1498a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 1499a45c6cb8SMadhusudhan Chikkature dto += 1; 1500a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 1501a45c6cb8SMadhusudhan Chikkature dto -= 13; 1502a45c6cb8SMadhusudhan Chikkature else 1503a45c6cb8SMadhusudhan Chikkature dto = 0; 1504a45c6cb8SMadhusudhan Chikkature if (dto > 14) 1505a45c6cb8SMadhusudhan Chikkature dto = 14; 1506a45c6cb8SMadhusudhan Chikkature } 1507a45c6cb8SMadhusudhan Chikkature 1508a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 1509a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 1510a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1511a45c6cb8SMadhusudhan Chikkature } 1512a45c6cb8SMadhusudhan Chikkature 15139d025334SBalaji T K static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host) 15149d025334SBalaji T K { 15159d025334SBalaji T K struct mmc_request *req = host->mrq; 15169d025334SBalaji T K struct dma_chan *chan; 15179d025334SBalaji T K 15189d025334SBalaji T K if (!req->data) 15199d025334SBalaji T K return; 15209d025334SBalaji T K OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 15219d025334SBalaji T K | (req->data->blocks << 16)); 15229d025334SBalaji T K set_data_timeout(host, req->data->timeout_ns, 15239d025334SBalaji T K req->data->timeout_clks); 15249d025334SBalaji T K chan = omap_hsmmc_get_dma_chan(host, req->data); 15259d025334SBalaji T K dma_async_issue_pending(chan); 15269d025334SBalaji T K } 15279d025334SBalaji T K 1528a45c6cb8SMadhusudhan Chikkature /* 1529a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 1530a45c6cb8SMadhusudhan Chikkature */ 1531a45c6cb8SMadhusudhan Chikkature static int 153270a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1533a45c6cb8SMadhusudhan Chikkature { 1534a45c6cb8SMadhusudhan Chikkature int ret; 1535a45c6cb8SMadhusudhan Chikkature host->data = req->data; 1536a45c6cb8SMadhusudhan Chikkature 1537a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 1538a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 1539e2bf08d6SAdrian Hunter /* 1540e2bf08d6SAdrian Hunter * Set an arbitrary 100ms data timeout for commands with 1541e2bf08d6SAdrian Hunter * busy signal. 1542e2bf08d6SAdrian Hunter */ 1543e2bf08d6SAdrian Hunter if (req->cmd->flags & MMC_RSP_BUSY) 1544e2bf08d6SAdrian Hunter set_data_timeout(host, 100000000U, 0); 1545a45c6cb8SMadhusudhan Chikkature return 0; 1546a45c6cb8SMadhusudhan Chikkature } 1547a45c6cb8SMadhusudhan Chikkature 1548a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 15499d025334SBalaji T K ret = omap_hsmmc_setup_dma_transfer(host, req); 1550a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 1551b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); 1552a45c6cb8SMadhusudhan Chikkature return ret; 1553a45c6cb8SMadhusudhan Chikkature } 1554a45c6cb8SMadhusudhan Chikkature } 1555a45c6cb8SMadhusudhan Chikkature return 0; 1556a45c6cb8SMadhusudhan Chikkature } 1557a45c6cb8SMadhusudhan Chikkature 15589782aff8SPer Forlin static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 15599782aff8SPer Forlin int err) 15609782aff8SPer Forlin { 15619782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15629782aff8SPer Forlin struct mmc_data *data = mrq->data; 15639782aff8SPer Forlin 156426b88520SRussell King if (host->use_dma && data->host_cookie) { 1565c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1566c5c98927SRussell King 156726b88520SRussell King dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 15689782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 15699782aff8SPer Forlin data->host_cookie = 0; 15709782aff8SPer Forlin } 15719782aff8SPer Forlin } 15729782aff8SPer Forlin 15739782aff8SPer Forlin static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 15749782aff8SPer Forlin bool is_first_req) 15759782aff8SPer Forlin { 15769782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 15779782aff8SPer Forlin 15789782aff8SPer Forlin if (mrq->data->host_cookie) { 15799782aff8SPer Forlin mrq->data->host_cookie = 0; 15809782aff8SPer Forlin return ; 15819782aff8SPer Forlin } 15829782aff8SPer Forlin 1583c5c98927SRussell King if (host->use_dma) { 1584c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1585c5c98927SRussell King 15869782aff8SPer Forlin if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 158726b88520SRussell King &host->next_data, c)) 15889782aff8SPer Forlin mrq->data->host_cookie = 0; 15899782aff8SPer Forlin } 1590c5c98927SRussell King } 15919782aff8SPer Forlin 1592a45c6cb8SMadhusudhan Chikkature /* 1593a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 1594a45c6cb8SMadhusudhan Chikkature */ 159570a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1596a45c6cb8SMadhusudhan Chikkature { 159770a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1598a3f406f8SJarkko Lavinen int err; 1599a45c6cb8SMadhusudhan Chikkature 1600b417577dSAdrian Hunter BUG_ON(host->req_in_progress); 1601b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1602f57ba4caSNeilBrown pm_runtime_get_sync(host->dev); 1603b62f6228SAdrian Hunter if (host->protect_card) { 1604b62f6228SAdrian Hunter if (host->reqs_blocked < 3) { 1605b62f6228SAdrian Hunter /* 1606b62f6228SAdrian Hunter * Ensure the controller is left in a consistent 1607b62f6228SAdrian Hunter * state by resetting the command and data state 1608b62f6228SAdrian Hunter * machines. 1609b62f6228SAdrian Hunter */ 1610b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRD); 1611b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRC); 1612b62f6228SAdrian Hunter host->reqs_blocked += 1; 1613b62f6228SAdrian Hunter } 1614b62f6228SAdrian Hunter req->cmd->error = -EBADF; 1615b62f6228SAdrian Hunter if (req->data) 1616b62f6228SAdrian Hunter req->data->error = -EBADF; 1617b417577dSAdrian Hunter req->cmd->retries = 0; 1618b62f6228SAdrian Hunter mmc_request_done(mmc, req); 1619f57ba4caSNeilBrown pm_runtime_mark_last_busy(host->dev); 1620f57ba4caSNeilBrown pm_runtime_put_autosuspend(host->dev); 1621b62f6228SAdrian Hunter return; 1622b62f6228SAdrian Hunter } else if (host->reqs_blocked) 1623b62f6228SAdrian Hunter host->reqs_blocked = 0; 1624a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 1625a45c6cb8SMadhusudhan Chikkature host->mrq = req; 16266e3076c2SBalaji T K host->clk_rate = clk_get_rate(host->fclk); 162770a3341aSDenis Karpov err = omap_hsmmc_prepare_data(host, req); 1628a3f406f8SJarkko Lavinen if (err) { 1629a3f406f8SJarkko Lavinen req->cmd->error = err; 1630a3f406f8SJarkko Lavinen if (req->data) 1631a3f406f8SJarkko Lavinen req->data->error = err; 1632a3f406f8SJarkko Lavinen host->mrq = NULL; 1633a3f406f8SJarkko Lavinen mmc_request_done(mmc, req); 1634f57ba4caSNeilBrown pm_runtime_mark_last_busy(host->dev); 1635f57ba4caSNeilBrown pm_runtime_put_autosuspend(host->dev); 1636a3f406f8SJarkko Lavinen return; 1637a3f406f8SJarkko Lavinen } 1638a2e77152SBalaji T K if (req->sbc && !(host->flags & AUTO_CMD23)) { 1639bf129e1cSBalaji T K omap_hsmmc_start_command(host, req->sbc, NULL); 1640bf129e1cSBalaji T K return; 1641bf129e1cSBalaji T K } 1642a3f406f8SJarkko Lavinen 16439d025334SBalaji T K omap_hsmmc_start_dma_transfer(host); 164470a3341aSDenis Karpov omap_hsmmc_start_command(host, req->cmd, req->data); 1645a45c6cb8SMadhusudhan Chikkature } 1646a45c6cb8SMadhusudhan Chikkature 1647a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 164870a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1649a45c6cb8SMadhusudhan Chikkature { 165070a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1651a3621465SAdrian Hunter int do_send_init_stream = 0; 1652a45c6cb8SMadhusudhan Chikkature 1653fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 16545e2ea617SAdrian Hunter 1655a3621465SAdrian Hunter if (ios->power_mode != host->power_mode) { 1656a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 1657a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 1658f7f0f035SAndreas Fenkart omap_hsmmc_set_power(host->dev, 0, 0); 1659a45c6cb8SMadhusudhan Chikkature break; 1660a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 1661f7f0f035SAndreas Fenkart omap_hsmmc_set_power(host->dev, 1, ios->vdd); 1662a45c6cb8SMadhusudhan Chikkature break; 1663a3621465SAdrian Hunter case MMC_POWER_ON: 1664a3621465SAdrian Hunter do_send_init_stream = 1; 1665a3621465SAdrian Hunter break; 1666a3621465SAdrian Hunter } 1667a3621465SAdrian Hunter host->power_mode = ios->power_mode; 1668a45c6cb8SMadhusudhan Chikkature } 1669a45c6cb8SMadhusudhan Chikkature 1670dd498effSDenis Karpov /* FIXME: set registers based only on changes to ios */ 1671dd498effSDenis Karpov 16723796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 1673a45c6cb8SMadhusudhan Chikkature 16744621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1675eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 1676eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 1677eb250826SDavid Brownell */ 1678a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 16792cf171cbSBalaji T K (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1680a45c6cb8SMadhusudhan Chikkature /* 1681a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 1682a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 1683a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 1684a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 1685a45c6cb8SMadhusudhan Chikkature */ 168670a3341aSDenis Karpov if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1687a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1688a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 1689a45c6cb8SMadhusudhan Chikkature } 1690a45c6cb8SMadhusudhan Chikkature } 1691a45c6cb8SMadhusudhan Chikkature 16925934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 1693a45c6cb8SMadhusudhan Chikkature 1694a3621465SAdrian Hunter if (do_send_init_stream) 1695a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 1696a45c6cb8SMadhusudhan Chikkature 16973796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 16985e2ea617SAdrian Hunter 1699fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1700a45c6cb8SMadhusudhan Chikkature } 1701a45c6cb8SMadhusudhan Chikkature 1702a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1703a45c6cb8SMadhusudhan Chikkature { 170470a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1705a45c6cb8SMadhusudhan Chikkature 1706b5cd43f0SAndreas Fenkart if (!host->card_detect) 1707a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 170880412ca8SAndreas Fenkart return host->card_detect(host->dev); 1709a45c6cb8SMadhusudhan Chikkature } 1710a45c6cb8SMadhusudhan Chikkature 17114816858cSGrazvydas Ignotas static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 17124816858cSGrazvydas Ignotas { 17134816858cSGrazvydas Ignotas struct omap_hsmmc_host *host = mmc_priv(mmc); 17144816858cSGrazvydas Ignotas 1715326119c9SAndreas Fenkart if (mmc_pdata(host)->init_card) 1716326119c9SAndreas Fenkart mmc_pdata(host)->init_card(card); 17174816858cSGrazvydas Ignotas } 17184816858cSGrazvydas Ignotas 17192cd3a2a5SAndreas Fenkart static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 17202cd3a2a5SAndreas Fenkart { 17212cd3a2a5SAndreas Fenkart struct omap_hsmmc_host *host = mmc_priv(mmc); 17225a52b08bSBalaji T K u32 irq_mask, con; 17232cd3a2a5SAndreas Fenkart unsigned long flags; 17242cd3a2a5SAndreas Fenkart 17252cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 17262cd3a2a5SAndreas Fenkart 17275a52b08bSBalaji T K con = OMAP_HSMMC_READ(host->base, CON); 17282cd3a2a5SAndreas Fenkart irq_mask = OMAP_HSMMC_READ(host->base, ISE); 17292cd3a2a5SAndreas Fenkart if (enable) { 17302cd3a2a5SAndreas Fenkart host->flags |= HSMMC_SDIO_IRQ_ENABLED; 17312cd3a2a5SAndreas Fenkart irq_mask |= CIRQ_EN; 17325a52b08bSBalaji T K con |= CTPL | CLKEXTFREE; 17332cd3a2a5SAndreas Fenkart } else { 17342cd3a2a5SAndreas Fenkart host->flags &= ~HSMMC_SDIO_IRQ_ENABLED; 17352cd3a2a5SAndreas Fenkart irq_mask &= ~CIRQ_EN; 17365a52b08bSBalaji T K con &= ~(CTPL | CLKEXTFREE); 17372cd3a2a5SAndreas Fenkart } 17385a52b08bSBalaji T K OMAP_HSMMC_WRITE(host->base, CON, con); 17392cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 17402cd3a2a5SAndreas Fenkart 17412cd3a2a5SAndreas Fenkart /* 17422cd3a2a5SAndreas Fenkart * if enable, piggy back detection on current request 17432cd3a2a5SAndreas Fenkart * but always disable immediately 17442cd3a2a5SAndreas Fenkart */ 17452cd3a2a5SAndreas Fenkart if (!host->req_in_progress || !enable) 17462cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 17472cd3a2a5SAndreas Fenkart 17482cd3a2a5SAndreas Fenkart /* flush posted write */ 17492cd3a2a5SAndreas Fenkart OMAP_HSMMC_READ(host->base, IE); 17502cd3a2a5SAndreas Fenkart 17512cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 17522cd3a2a5SAndreas Fenkart } 17532cd3a2a5SAndreas Fenkart 17542cd3a2a5SAndreas Fenkart static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host) 17552cd3a2a5SAndreas Fenkart { 17562cd3a2a5SAndreas Fenkart int ret; 17572cd3a2a5SAndreas Fenkart 17582cd3a2a5SAndreas Fenkart /* 17592cd3a2a5SAndreas Fenkart * For omaps with wake-up path, wakeirq will be irq from pinctrl and 17602cd3a2a5SAndreas Fenkart * for other omaps, wakeirq will be from GPIO (dat line remuxed to 17612cd3a2a5SAndreas Fenkart * gpio). wakeirq is needed to detect sdio irq in runtime suspend state 17622cd3a2a5SAndreas Fenkart * with functional clock disabled. 17632cd3a2a5SAndreas Fenkart */ 17642cd3a2a5SAndreas Fenkart if (!host->dev->of_node || !host->wake_irq) 17652cd3a2a5SAndreas Fenkart return -ENODEV; 17662cd3a2a5SAndreas Fenkart 17675b83b223STony Lindgren ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq); 17682cd3a2a5SAndreas Fenkart if (ret) { 17692cd3a2a5SAndreas Fenkart dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n"); 17702cd3a2a5SAndreas Fenkart goto err; 17712cd3a2a5SAndreas Fenkart } 17722cd3a2a5SAndreas Fenkart 17732cd3a2a5SAndreas Fenkart /* 17742cd3a2a5SAndreas Fenkart * Some omaps don't have wake-up path from deeper idle states 17752cd3a2a5SAndreas Fenkart * and need to remux SDIO DAT1 to GPIO for wake-up from idle. 17762cd3a2a5SAndreas Fenkart */ 17772cd3a2a5SAndreas Fenkart if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) { 1778455e5cd6SAndreas Fenkart struct pinctrl *p = devm_pinctrl_get(host->dev); 1779455e5cd6SAndreas Fenkart if (!p) { 17802cd3a2a5SAndreas Fenkart ret = -ENODEV; 1781455e5cd6SAndreas Fenkart goto err_free_irq; 1782455e5cd6SAndreas Fenkart } 1783455e5cd6SAndreas Fenkart if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) { 1784455e5cd6SAndreas Fenkart dev_info(host->dev, "missing default pinctrl state\n"); 1785455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 1786455e5cd6SAndreas Fenkart ret = -EINVAL; 1787455e5cd6SAndreas Fenkart goto err_free_irq; 1788455e5cd6SAndreas Fenkart } 1789455e5cd6SAndreas Fenkart 1790455e5cd6SAndreas Fenkart if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) { 1791455e5cd6SAndreas Fenkart dev_info(host->dev, "missing idle pinctrl state\n"); 1792455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 1793455e5cd6SAndreas Fenkart ret = -EINVAL; 1794455e5cd6SAndreas Fenkart goto err_free_irq; 1795455e5cd6SAndreas Fenkart } 1796455e5cd6SAndreas Fenkart devm_pinctrl_put(p); 17972cd3a2a5SAndreas Fenkart } 17982cd3a2a5SAndreas Fenkart 17995a52b08bSBalaji T K OMAP_HSMMC_WRITE(host->base, HCTL, 18005a52b08bSBalaji T K OMAP_HSMMC_READ(host->base, HCTL) | IWE); 18012cd3a2a5SAndreas Fenkart return 0; 18022cd3a2a5SAndreas Fenkart 1803455e5cd6SAndreas Fenkart err_free_irq: 18045b83b223STony Lindgren dev_pm_clear_wake_irq(host->dev); 18052cd3a2a5SAndreas Fenkart err: 18062cd3a2a5SAndreas Fenkart dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n"); 18072cd3a2a5SAndreas Fenkart host->wake_irq = 0; 18082cd3a2a5SAndreas Fenkart return ret; 18092cd3a2a5SAndreas Fenkart } 18102cd3a2a5SAndreas Fenkart 181170a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 18121b331e69SKim Kyuwon { 18131b331e69SKim Kyuwon u32 hctl, capa, value; 18141b331e69SKim Kyuwon 18151b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 18164621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 18171b331e69SKim Kyuwon hctl = SDVS30; 18181b331e69SKim Kyuwon capa = VS30 | VS18; 18191b331e69SKim Kyuwon } else { 18201b331e69SKim Kyuwon hctl = SDVS18; 18211b331e69SKim Kyuwon capa = VS18; 18221b331e69SKim Kyuwon } 18231b331e69SKim Kyuwon 18241b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 18251b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 18261b331e69SKim Kyuwon 18271b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 18281b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 18291b331e69SKim Kyuwon 18301b331e69SKim Kyuwon /* Set SD bus power bit */ 1831e13bb300SAdrian Hunter set_sd_bus_power(host); 18321b331e69SKim Kyuwon } 18331b331e69SKim Kyuwon 1834afd8c29dSKuninori Morimoto static int omap_hsmmc_multi_io_quirk(struct mmc_card *card, 1835afd8c29dSKuninori Morimoto unsigned int direction, int blk_size) 1836afd8c29dSKuninori Morimoto { 1837afd8c29dSKuninori Morimoto /* This controller can't do multiblock reads due to hw bugs */ 1838afd8c29dSKuninori Morimoto if (direction == MMC_DATA_READ) 1839afd8c29dSKuninori Morimoto return 1; 1840afd8c29dSKuninori Morimoto 1841afd8c29dSKuninori Morimoto return blk_size; 1842afd8c29dSKuninori Morimoto } 1843afd8c29dSKuninori Morimoto 1844afd8c29dSKuninori Morimoto static struct mmc_host_ops omap_hsmmc_ops = { 18459782aff8SPer Forlin .post_req = omap_hsmmc_post_req, 18469782aff8SPer Forlin .pre_req = omap_hsmmc_pre_req, 184770a3341aSDenis Karpov .request = omap_hsmmc_request, 184870a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1849dd498effSDenis Karpov .get_cd = omap_hsmmc_get_cd, 1850a49d8353SAndreas Fenkart .get_ro = mmc_gpio_get_ro, 18514816858cSGrazvydas Ignotas .init_card = omap_hsmmc_init_card, 18522cd3a2a5SAndreas Fenkart .enable_sdio_irq = omap_hsmmc_enable_sdio_irq, 1853dd498effSDenis Karpov }; 1854dd498effSDenis Karpov 1855d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS 1856d900f712SDenis Karpov 185770a3341aSDenis Karpov static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1858d900f712SDenis Karpov { 1859d900f712SDenis Karpov struct mmc_host *mmc = s->private; 186070a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 186111dd62a7SDenis Karpov 1862bb0635f0SAndreas Fenkart seq_printf(s, "mmc%d:\n", mmc->index); 1863bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq mode\t%s\n", 1864bb0635f0SAndreas Fenkart (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling"); 1865bb0635f0SAndreas Fenkart 1866bb0635f0SAndreas Fenkart if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1867bb0635f0SAndreas Fenkart seq_printf(s, "sdio irq \t%s\n", 1868bb0635f0SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled" 1869bb0635f0SAndreas Fenkart : "disabled"); 1870bb0635f0SAndreas Fenkart } 1871bb0635f0SAndreas Fenkart seq_printf(s, "ctx_loss:\t%d\n", host->context_loss); 18725e2ea617SAdrian Hunter 1873fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1874bb0635f0SAndreas Fenkart seq_puts(s, "\nregs:\n"); 1875d900f712SDenis Karpov seq_printf(s, "CON:\t\t0x%08x\n", 1876d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CON)); 1877bb0635f0SAndreas Fenkart seq_printf(s, "PSTATE:\t\t0x%08x\n", 1878bb0635f0SAndreas Fenkart OMAP_HSMMC_READ(host->base, PSTATE)); 1879d900f712SDenis Karpov seq_printf(s, "HCTL:\t\t0x%08x\n", 1880d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL)); 1881d900f712SDenis Karpov seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1882d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL)); 1883d900f712SDenis Karpov seq_printf(s, "IE:\t\t0x%08x\n", 1884d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, IE)); 1885d900f712SDenis Karpov seq_printf(s, "ISE:\t\t0x%08x\n", 1886d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, ISE)); 1887d900f712SDenis Karpov seq_printf(s, "CAPA:\t\t0x%08x\n", 1888d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA)); 18895e2ea617SAdrian Hunter 1890fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1891fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1892dd498effSDenis Karpov 1893d900f712SDenis Karpov return 0; 1894d900f712SDenis Karpov } 1895d900f712SDenis Karpov 189670a3341aSDenis Karpov static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1897d900f712SDenis Karpov { 189870a3341aSDenis Karpov return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1899d900f712SDenis Karpov } 1900d900f712SDenis Karpov 1901d900f712SDenis Karpov static const struct file_operations mmc_regs_fops = { 190270a3341aSDenis Karpov .open = omap_hsmmc_regs_open, 1903d900f712SDenis Karpov .read = seq_read, 1904d900f712SDenis Karpov .llseek = seq_lseek, 1905d900f712SDenis Karpov .release = single_release, 1906d900f712SDenis Karpov }; 1907d900f712SDenis Karpov 190870a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1909d900f712SDenis Karpov { 1910d900f712SDenis Karpov if (mmc->debugfs_root) 1911d900f712SDenis Karpov debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1912d900f712SDenis Karpov mmc, &mmc_regs_fops); 1913d900f712SDenis Karpov } 1914d900f712SDenis Karpov 1915d900f712SDenis Karpov #else 1916d900f712SDenis Karpov 191770a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1918d900f712SDenis Karpov { 1919d900f712SDenis Karpov } 1920d900f712SDenis Karpov 1921d900f712SDenis Karpov #endif 1922d900f712SDenis Karpov 192346856a68SRajendra Nayak #ifdef CONFIG_OF 192459445b10SNishanth Menon static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = { 192559445b10SNishanth Menon /* See 35xx errata 2.1.1.128 in SPRZ278F */ 192659445b10SNishanth Menon .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, 192759445b10SNishanth Menon }; 192859445b10SNishanth Menon 192959445b10SNishanth Menon static const struct omap_mmc_of_data omap4_mmc_of_data = { 193059445b10SNishanth Menon .reg_offset = 0x100, 193159445b10SNishanth Menon }; 19322cd3a2a5SAndreas Fenkart static const struct omap_mmc_of_data am33xx_mmc_of_data = { 19332cd3a2a5SAndreas Fenkart .reg_offset = 0x100, 19342cd3a2a5SAndreas Fenkart .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING, 19352cd3a2a5SAndreas Fenkart }; 193646856a68SRajendra Nayak 193746856a68SRajendra Nayak static const struct of_device_id omap_mmc_of_match[] = { 193846856a68SRajendra Nayak { 193946856a68SRajendra Nayak .compatible = "ti,omap2-hsmmc", 194046856a68SRajendra Nayak }, 194146856a68SRajendra Nayak { 194259445b10SNishanth Menon .compatible = "ti,omap3-pre-es3-hsmmc", 194359445b10SNishanth Menon .data = &omap3_pre_es3_mmc_of_data, 194459445b10SNishanth Menon }, 194559445b10SNishanth Menon { 194646856a68SRajendra Nayak .compatible = "ti,omap3-hsmmc", 194746856a68SRajendra Nayak }, 194846856a68SRajendra Nayak { 194946856a68SRajendra Nayak .compatible = "ti,omap4-hsmmc", 195059445b10SNishanth Menon .data = &omap4_mmc_of_data, 195146856a68SRajendra Nayak }, 19522cd3a2a5SAndreas Fenkart { 19532cd3a2a5SAndreas Fenkart .compatible = "ti,am33xx-hsmmc", 19542cd3a2a5SAndreas Fenkart .data = &am33xx_mmc_of_data, 19552cd3a2a5SAndreas Fenkart }, 195646856a68SRajendra Nayak {}, 1957b6d085f6SChris Ball }; 195846856a68SRajendra Nayak MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 195946856a68SRajendra Nayak 196055143438SAndreas Fenkart static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 196146856a68SRajendra Nayak { 196255143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata; 196346856a68SRajendra Nayak struct device_node *np = dev->of_node; 196446856a68SRajendra Nayak 196546856a68SRajendra Nayak pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 196646856a68SRajendra Nayak if (!pdata) 196719df45bcSBalaji T K return ERR_PTR(-ENOMEM); /* out of memory */ 196846856a68SRajendra Nayak 196946856a68SRajendra Nayak if (of_find_property(np, "ti,dual-volt", NULL)) 197046856a68SRajendra Nayak pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 197146856a68SRajendra Nayak 1972b7a5646fSAndreas Fenkart pdata->gpio_cd = -EINVAL; 1973b7a5646fSAndreas Fenkart pdata->gpio_cod = -EINVAL; 1974fdb9de12SNeilBrown pdata->gpio_wp = -EINVAL; 197546856a68SRajendra Nayak 197646856a68SRajendra Nayak if (of_find_property(np, "ti,non-removable", NULL)) { 1977326119c9SAndreas Fenkart pdata->nonremovable = true; 1978326119c9SAndreas Fenkart pdata->no_regulator_off_init = true; 197946856a68SRajendra Nayak } 198046856a68SRajendra Nayak 198146856a68SRajendra Nayak if (of_find_property(np, "ti,needs-special-reset", NULL)) 1982326119c9SAndreas Fenkart pdata->features |= HSMMC_HAS_UPDATED_RESET; 198346856a68SRajendra Nayak 1984cd587096SHebbar, Gururaja if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) 1985326119c9SAndreas Fenkart pdata->features |= HSMMC_HAS_HSPE_SUPPORT; 1986cd587096SHebbar, Gururaja 198746856a68SRajendra Nayak return pdata; 198846856a68SRajendra Nayak } 198946856a68SRajendra Nayak #else 199055143438SAndreas Fenkart static inline struct omap_hsmmc_platform_data 199146856a68SRajendra Nayak *of_get_hsmmc_pdata(struct device *dev) 199246856a68SRajendra Nayak { 199319df45bcSBalaji T K return ERR_PTR(-EINVAL); 199446856a68SRajendra Nayak } 199546856a68SRajendra Nayak #endif 199646856a68SRajendra Nayak 1997c3be1efdSBill Pemberton static int omap_hsmmc_probe(struct platform_device *pdev) 1998a45c6cb8SMadhusudhan Chikkature { 199955143438SAndreas Fenkart struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data; 2000a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 200170a3341aSDenis Karpov struct omap_hsmmc_host *host = NULL; 2002a45c6cb8SMadhusudhan Chikkature struct resource *res; 2003db0fefc5SAdrian Hunter int ret, irq; 200446856a68SRajendra Nayak const struct of_device_id *match; 200526b88520SRussell King dma_cap_mask_t mask; 200626b88520SRussell King unsigned tx_req, rx_req; 200759445b10SNishanth Menon const struct omap_mmc_of_data *data; 200877fae219SBalaji T K void __iomem *base; 200946856a68SRajendra Nayak 201046856a68SRajendra Nayak match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 201146856a68SRajendra Nayak if (match) { 201246856a68SRajendra Nayak pdata = of_get_hsmmc_pdata(&pdev->dev); 2013dc642c28SJan Luebbe 2014dc642c28SJan Luebbe if (IS_ERR(pdata)) 2015dc642c28SJan Luebbe return PTR_ERR(pdata); 2016dc642c28SJan Luebbe 201746856a68SRajendra Nayak if (match->data) { 201859445b10SNishanth Menon data = match->data; 201959445b10SNishanth Menon pdata->reg_offset = data->reg_offset; 202059445b10SNishanth Menon pdata->controller_flags |= data->controller_flags; 202146856a68SRajendra Nayak } 202246856a68SRajendra Nayak } 2023a45c6cb8SMadhusudhan Chikkature 2024a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 2025a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 2026a45c6cb8SMadhusudhan Chikkature return -ENXIO; 2027a45c6cb8SMadhusudhan Chikkature } 2028a45c6cb8SMadhusudhan Chikkature 2029a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2030a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 2031a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 2032a45c6cb8SMadhusudhan Chikkature return -ENXIO; 2033a45c6cb8SMadhusudhan Chikkature 203477fae219SBalaji T K base = devm_ioremap_resource(&pdev->dev, res); 203577fae219SBalaji T K if (IS_ERR(base)) 203677fae219SBalaji T K return PTR_ERR(base); 2037a45c6cb8SMadhusudhan Chikkature 203870a3341aSDenis Karpov mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 2039a45c6cb8SMadhusudhan Chikkature if (!mmc) { 2040a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 20411e363e3bSAndreas Fenkart goto err; 2042a45c6cb8SMadhusudhan Chikkature } 2043a45c6cb8SMadhusudhan Chikkature 2044fdb9de12SNeilBrown ret = mmc_of_parse(mmc); 2045fdb9de12SNeilBrown if (ret) 2046fdb9de12SNeilBrown goto err1; 2047fdb9de12SNeilBrown 2048a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 2049a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 2050a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 2051a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 2052a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 2053a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 2054a45c6cb8SMadhusudhan Chikkature host->irq = irq; 2055fc307df8SBalaji T K host->mapbase = res->start + pdata->reg_offset; 205677fae219SBalaji T K host->base = base + pdata->reg_offset; 20576da20c89SAdrian Hunter host->power_mode = MMC_POWER_OFF; 20589782aff8SPer Forlin host->next_data.cookie = 1; 2059bb2726b5STony Lindgren host->pbias_enabled = 0; 20603f77f702SKishon Vijay Abraham I host->vqmmc_enabled = 0; 2061a45c6cb8SMadhusudhan Chikkature 206241afa314SNeilBrown ret = omap_hsmmc_gpio_init(mmc, host, pdata); 20631e363e3bSAndreas Fenkart if (ret) 20641e363e3bSAndreas Fenkart goto err_gpio; 20651e363e3bSAndreas Fenkart 2066a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 2067a45c6cb8SMadhusudhan Chikkature 20682cd3a2a5SAndreas Fenkart if (pdev->dev.of_node) 20692cd3a2a5SAndreas Fenkart host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1); 20702cd3a2a5SAndreas Fenkart 207170a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ops; 2072dd498effSDenis Karpov 20736b206efeSAndy Shevchenko mmc->f_min = OMAP_MMC_MIN_CLOCK; 2074d418ed87SDaniel Mack 2075d418ed87SDaniel Mack if (pdata->max_freq > 0) 2076d418ed87SDaniel Mack mmc->f_max = pdata->max_freq; 2077fdb9de12SNeilBrown else if (mmc->f_max == 0) 20786b206efeSAndy Shevchenko mmc->f_max = OMAP_MMC_MAX_CLOCK; 2079a45c6cb8SMadhusudhan Chikkature 20804dffd7a2SAdrian Hunter spin_lock_init(&host->irq_lock); 2081a45c6cb8SMadhusudhan Chikkature 20829618195eSBalaji T K host->fclk = devm_clk_get(&pdev->dev, "fck"); 2083a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 2084a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 2085a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 2086a45c6cb8SMadhusudhan Chikkature goto err1; 2087a45c6cb8SMadhusudhan Chikkature } 2088a45c6cb8SMadhusudhan Chikkature 20899b68256cSPaul Walmsley if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 20909b68256cSPaul Walmsley dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 2091afd8c29dSKuninori Morimoto omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk; 20929b68256cSPaul Walmsley } 2093dd498effSDenis Karpov 20945b83b223STony Lindgren device_init_wakeup(&pdev->dev, true); 2095fa4aa2d4SBalaji T K pm_runtime_enable(host->dev); 2096fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2097fa4aa2d4SBalaji T K pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 2098fa4aa2d4SBalaji T K pm_runtime_use_autosuspend(host->dev); 2099a45c6cb8SMadhusudhan Chikkature 210092a3aebfSBalaji T K omap_hsmmc_context_save(host); 210192a3aebfSBalaji T K 21029618195eSBalaji T K host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck"); 2103a45c6cb8SMadhusudhan Chikkature /* 2104a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 2105a45c6cb8SMadhusudhan Chikkature */ 2106cd03d9a8SRajendra Nayak if (IS_ERR(host->dbclk)) { 2107cd03d9a8SRajendra Nayak host->dbclk = NULL; 210894c18149SRajendra Nayak } else if (clk_prepare_enable(host->dbclk) != 0) { 2109cd03d9a8SRajendra Nayak dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 2110cd03d9a8SRajendra Nayak host->dbclk = NULL; 21112bec0893SAdrian Hunter } 2112a45c6cb8SMadhusudhan Chikkature 21130ccd76d4SJuha Yrjola /* Since we do only SG emulation, we can have as many segs 21140ccd76d4SJuha Yrjola * as we want. */ 2115a36274e0SMartin K. Petersen mmc->max_segs = 1024; 21160ccd76d4SJuha Yrjola 2117a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 2118a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 2119a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2120a45c6cb8SMadhusudhan Chikkature mmc->max_seg_size = mmc->max_req_size; 2121a45c6cb8SMadhusudhan Chikkature 212213189e78SJarkko Lavinen mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 212393caf8e6SAdrian Hunter MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 2124a45c6cb8SMadhusudhan Chikkature 2125326119c9SAndreas Fenkart mmc->caps |= mmc_pdata(host)->caps; 21263a63833eSSukumar Ghorai if (mmc->caps & MMC_CAP_8_BIT_DATA) 2127a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 2128a45c6cb8SMadhusudhan Chikkature 2129326119c9SAndreas Fenkart if (mmc_pdata(host)->nonremovable) 213023d99bb9SAdrian Hunter mmc->caps |= MMC_CAP_NONREMOVABLE; 213123d99bb9SAdrian Hunter 2132fdb9de12SNeilBrown mmc->pm_caps |= mmc_pdata(host)->pm_caps; 21336fdc75deSEliad Peller 213470a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 2135a45c6cb8SMadhusudhan Chikkature 21364a29b559SSantosh Shilimkar if (!pdev->dev.of_node) { 2137b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 2138b7bf773bSBalaji T K if (!res) { 2139b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n"); 21409c17d08cSKevin Hilman ret = -ENXIO; 2141f3e2f1ddSGrazvydas Ignotas goto err_irq; 2142a45c6cb8SMadhusudhan Chikkature } 214326b88520SRussell King tx_req = res->start; 2144b7bf773bSBalaji T K 2145b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 2146b7bf773bSBalaji T K if (!res) { 2147b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n"); 21489c17d08cSKevin Hilman ret = -ENXIO; 2149b7bf773bSBalaji T K goto err_irq; 2150b7bf773bSBalaji T K } 215126b88520SRussell King rx_req = res->start; 21524a29b559SSantosh Shilimkar } 2153c5c98927SRussell King 2154c5c98927SRussell King dma_cap_zero(mask); 2155c5c98927SRussell King dma_cap_set(DMA_SLAVE, mask); 215626b88520SRussell King 2157d272fbf0SMatt Porter host->rx_chan = 2158d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 2159d272fbf0SMatt Porter &rx_req, &pdev->dev, "rx"); 2160d272fbf0SMatt Porter 2161c5c98927SRussell King if (!host->rx_chan) { 216226b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req); 216304e8c7bcSKevin Hilman ret = -ENXIO; 216426b88520SRussell King goto err_irq; 2165c5c98927SRussell King } 216626b88520SRussell King 2167d272fbf0SMatt Porter host->tx_chan = 2168d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 2169d272fbf0SMatt Porter &tx_req, &pdev->dev, "tx"); 2170d272fbf0SMatt Porter 2171c5c98927SRussell King if (!host->tx_chan) { 217226b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req); 217304e8c7bcSKevin Hilman ret = -ENXIO; 217426b88520SRussell King goto err_irq; 2175c5c98927SRussell King } 2176a45c6cb8SMadhusudhan Chikkature 2177a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 2178e1538ed7SBalaji T K ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0, 2179a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 2180a45c6cb8SMadhusudhan Chikkature if (ret) { 2181b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 2182a45c6cb8SMadhusudhan Chikkature goto err_irq; 2183a45c6cb8SMadhusudhan Chikkature } 2184a45c6cb8SMadhusudhan Chikkature 2185db0fefc5SAdrian Hunter ret = omap_hsmmc_reg_get(host); 2186db0fefc5SAdrian Hunter if (ret) 2187bb09d151SAndreas Fenkart goto err_irq; 2188db0fefc5SAdrian Hunter 2189326119c9SAndreas Fenkart mmc->ocr_avail = mmc_pdata(host)->ocr_mask; 2190a45c6cb8SMadhusudhan Chikkature 2191b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 2192a45c6cb8SMadhusudhan Chikkature 21932cd3a2a5SAndreas Fenkart /* 21942cd3a2a5SAndreas Fenkart * For now, only support SDIO interrupt if we have a separate 21952cd3a2a5SAndreas Fenkart * wake-up interrupt configured from device tree. This is because 21962cd3a2a5SAndreas Fenkart * the wake-up interrupt is needed for idle state and some 21972cd3a2a5SAndreas Fenkart * platforms need special quirks. And we don't want to add new 21982cd3a2a5SAndreas Fenkart * legacy mux platform init code callbacks any longer as we 21992cd3a2a5SAndreas Fenkart * are moving to DT based booting anyways. 22002cd3a2a5SAndreas Fenkart */ 22012cd3a2a5SAndreas Fenkart ret = omap_hsmmc_configure_wake_irq(host); 22022cd3a2a5SAndreas Fenkart if (!ret) 22032cd3a2a5SAndreas Fenkart mmc->caps |= MMC_CAP_SDIO_IRQ; 22042cd3a2a5SAndreas Fenkart 2205b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2206b62f6228SAdrian Hunter 2207a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 2208a45c6cb8SMadhusudhan Chikkature 2209326119c9SAndreas Fenkart if (mmc_pdata(host)->name != NULL) { 2210a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2211a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2212a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 2213a45c6cb8SMadhusudhan Chikkature } 2214cde592cbSAndreas Fenkart if (host->get_cover_state) { 2215a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, 2216a45c6cb8SMadhusudhan Chikkature &dev_attr_cover_switch); 2217a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2218db0fefc5SAdrian Hunter goto err_slot_name; 2219a45c6cb8SMadhusudhan Chikkature } 2220a45c6cb8SMadhusudhan Chikkature 222170a3341aSDenis Karpov omap_hsmmc_debugfs(mmc); 2222fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2223fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2224d900f712SDenis Karpov 2225a45c6cb8SMadhusudhan Chikkature return 0; 2226a45c6cb8SMadhusudhan Chikkature 2227a45c6cb8SMadhusudhan Chikkature err_slot_name: 2228a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 2229a45c6cb8SMadhusudhan Chikkature err_irq: 22305b83b223STony Lindgren device_init_wakeup(&pdev->dev, false); 2231c5c98927SRussell King if (host->tx_chan) 2232c5c98927SRussell King dma_release_channel(host->tx_chan); 2233c5c98927SRussell King if (host->rx_chan) 2234c5c98927SRussell King dma_release_channel(host->rx_chan); 2235d59d77edSBalaji T K pm_runtime_put_sync(host->dev); 223637f6190dSTony Lindgren pm_runtime_disable(host->dev); 22379618195eSBalaji T K if (host->dbclk) 223894c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2239a45c6cb8SMadhusudhan Chikkature err1: 22401e363e3bSAndreas Fenkart err_gpio: 2241a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 2242db0fefc5SAdrian Hunter err: 2243a45c6cb8SMadhusudhan Chikkature return ret; 2244a45c6cb8SMadhusudhan Chikkature } 2245a45c6cb8SMadhusudhan Chikkature 22466e0ee714SBill Pemberton static int omap_hsmmc_remove(struct platform_device *pdev) 2247a45c6cb8SMadhusudhan Chikkature { 224870a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2249a45c6cb8SMadhusudhan Chikkature 2250fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2251a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 2252a45c6cb8SMadhusudhan Chikkature 2253c5c98927SRussell King if (host->tx_chan) 2254c5c98927SRussell King dma_release_channel(host->tx_chan); 2255c5c98927SRussell King if (host->rx_chan) 2256c5c98927SRussell King dma_release_channel(host->rx_chan); 2257c5c98927SRussell King 2258fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2259fa4aa2d4SBalaji T K pm_runtime_disable(host->dev); 22605b83b223STony Lindgren device_init_wakeup(&pdev->dev, false); 22619618195eSBalaji T K if (host->dbclk) 226294c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2263a45c6cb8SMadhusudhan Chikkature 22649d1f0286SBalaji T K mmc_free_host(host->mmc); 2265a45c6cb8SMadhusudhan Chikkature 2266a45c6cb8SMadhusudhan Chikkature return 0; 2267a45c6cb8SMadhusudhan Chikkature } 2268a45c6cb8SMadhusudhan Chikkature 22693d3bbfbdSRuss Dill #ifdef CONFIG_PM_SLEEP 2270a791daa1SKevin Hilman static int omap_hsmmc_suspend(struct device *dev) 2271a45c6cb8SMadhusudhan Chikkature { 2272927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2273927ce944SFelipe Balbi 2274927ce944SFelipe Balbi if (!host) 2275927ce944SFelipe Balbi return 0; 2276a45c6cb8SMadhusudhan Chikkature 2277fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 227831f9d463SEliad Peller 227931f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 22802cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 22812cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 22822cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 228331f9d463SEliad Peller OMAP_HSMMC_WRITE(host->base, HCTL, 228431f9d463SEliad Peller OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 228531f9d463SEliad Peller } 2286927ce944SFelipe Balbi 2287cd03d9a8SRajendra Nayak if (host->dbclk) 228894c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 22893932afd5SUlf Hansson 2290fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 22913932afd5SUlf Hansson return 0; 2292a45c6cb8SMadhusudhan Chikkature } 2293a45c6cb8SMadhusudhan Chikkature 2294a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 2295a791daa1SKevin Hilman static int omap_hsmmc_resume(struct device *dev) 2296a45c6cb8SMadhusudhan Chikkature { 2297927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2298927ce944SFelipe Balbi 2299927ce944SFelipe Balbi if (!host) 2300927ce944SFelipe Balbi return 0; 2301a45c6cb8SMadhusudhan Chikkature 2302fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 230311dd62a7SDenis Karpov 2304cd03d9a8SRajendra Nayak if (host->dbclk) 230594c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 23062bec0893SAdrian Hunter 230731f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 230870a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 23091b331e69SKim Kyuwon 2310b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2311fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2312fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 23133932afd5SUlf Hansson return 0; 2314a45c6cb8SMadhusudhan Chikkature } 2315a45c6cb8SMadhusudhan Chikkature #endif 2316a45c6cb8SMadhusudhan Chikkature 2317fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_suspend(struct device *dev) 2318fa4aa2d4SBalaji T K { 2319fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 23202cd3a2a5SAndreas Fenkart unsigned long flags; 2321f945901fSAndreas Fenkart int ret = 0; 2322fa4aa2d4SBalaji T K 2323fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2324fa4aa2d4SBalaji T K omap_hsmmc_context_save(host); 2325927ce944SFelipe Balbi dev_dbg(dev, "disabled\n"); 2326fa4aa2d4SBalaji T K 23272cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 23282cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 23292cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 23302cd3a2a5SAndreas Fenkart /* disable sdio irq handling to prevent race */ 23312cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, 0); 23322cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, 0); 2333f945901fSAndreas Fenkart 2334f945901fSAndreas Fenkart if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) { 2335f945901fSAndreas Fenkart /* 2336f945901fSAndreas Fenkart * dat1 line low, pending sdio irq 2337f945901fSAndreas Fenkart * race condition: possible irq handler running on 2338f945901fSAndreas Fenkart * multi-core, abort 2339f945901fSAndreas Fenkart */ 2340f945901fSAndreas Fenkart dev_dbg(dev, "pending sdio irq, abort suspend\n"); 23412cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 2342f945901fSAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 2343f945901fSAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 2344f945901fSAndreas Fenkart pm_runtime_mark_last_busy(dev); 2345f945901fSAndreas Fenkart ret = -EBUSY; 2346f945901fSAndreas Fenkart goto abort; 2347f945901fSAndreas Fenkart } 23482cd3a2a5SAndreas Fenkart 234997978a44SAndreas Fenkart pinctrl_pm_select_idle_state(dev); 235097978a44SAndreas Fenkart } else { 235197978a44SAndreas Fenkart pinctrl_pm_select_idle_state(dev); 23522cd3a2a5SAndreas Fenkart } 235397978a44SAndreas Fenkart 2354f945901fSAndreas Fenkart abort: 23552cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2356f945901fSAndreas Fenkart return ret; 2357fa4aa2d4SBalaji T K } 2358fa4aa2d4SBalaji T K 2359fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_resume(struct device *dev) 2360fa4aa2d4SBalaji T K { 2361fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 23622cd3a2a5SAndreas Fenkart unsigned long flags; 2363fa4aa2d4SBalaji T K 2364fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2365fa4aa2d4SBalaji T K omap_hsmmc_context_restore(host); 2366927ce944SFelipe Balbi dev_dbg(dev, "enabled\n"); 2367fa4aa2d4SBalaji T K 23682cd3a2a5SAndreas Fenkart spin_lock_irqsave(&host->irq_lock, flags); 23692cd3a2a5SAndreas Fenkart if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && 23702cd3a2a5SAndreas Fenkart (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { 23712cd3a2a5SAndreas Fenkart 237297978a44SAndreas Fenkart pinctrl_pm_select_default_state(host->dev); 237397978a44SAndreas Fenkart 237497978a44SAndreas Fenkart /* irq lost, if pinmux incorrect */ 23752cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 23762cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); 23772cd3a2a5SAndreas Fenkart OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); 237897978a44SAndreas Fenkart } else { 237997978a44SAndreas Fenkart pinctrl_pm_select_default_state(host->dev); 23802cd3a2a5SAndreas Fenkart } 23812cd3a2a5SAndreas Fenkart spin_unlock_irqrestore(&host->irq_lock, flags); 2382fa4aa2d4SBalaji T K return 0; 2383fa4aa2d4SBalaji T K } 2384fa4aa2d4SBalaji T K 2385a791daa1SKevin Hilman static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 23863d3bbfbdSRuss Dill SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume) 2387fa4aa2d4SBalaji T K .runtime_suspend = omap_hsmmc_runtime_suspend, 2388fa4aa2d4SBalaji T K .runtime_resume = omap_hsmmc_runtime_resume, 2389a791daa1SKevin Hilman }; 2390a791daa1SKevin Hilman 2391a791daa1SKevin Hilman static struct platform_driver omap_hsmmc_driver = { 2392efa25fd3SFelipe Balbi .probe = omap_hsmmc_probe, 23930433c143SBill Pemberton .remove = omap_hsmmc_remove, 2394a45c6cb8SMadhusudhan Chikkature .driver = { 2395a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 2396a791daa1SKevin Hilman .pm = &omap_hsmmc_dev_pm_ops, 239746856a68SRajendra Nayak .of_match_table = of_match_ptr(omap_mmc_of_match), 2398a45c6cb8SMadhusudhan Chikkature }, 2399a45c6cb8SMadhusudhan Chikkature }; 2400a45c6cb8SMadhusudhan Chikkature 2401b796450bSFelipe Balbi module_platform_driver(omap_hsmmc_driver); 2402a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2403a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 2404a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 2405a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 2406