1a45c6cb8SMadhusudhan Chikkature /* 2a45c6cb8SMadhusudhan Chikkature * drivers/mmc/host/omap_hsmmc.c 3a45c6cb8SMadhusudhan Chikkature * 4a45c6cb8SMadhusudhan Chikkature * Driver for OMAP2430/3430 MMC controller. 5a45c6cb8SMadhusudhan Chikkature * 6a45c6cb8SMadhusudhan Chikkature * Copyright (C) 2007 Texas Instruments. 7a45c6cb8SMadhusudhan Chikkature * 8a45c6cb8SMadhusudhan Chikkature * Authors: 9a45c6cb8SMadhusudhan Chikkature * Syed Mohammed Khasim <x0khasim@ti.com> 10a45c6cb8SMadhusudhan Chikkature * Madhusudhan <madhu.cr@ti.com> 11a45c6cb8SMadhusudhan Chikkature * Mohit Jalori <mjalori@ti.com> 12a45c6cb8SMadhusudhan Chikkature * 13a45c6cb8SMadhusudhan Chikkature * This file is licensed under the terms of the GNU General Public License 14a45c6cb8SMadhusudhan Chikkature * version 2. This program is licensed "as is" without any warranty of any 15a45c6cb8SMadhusudhan Chikkature * kind, whether express or implied. 16a45c6cb8SMadhusudhan Chikkature */ 17a45c6cb8SMadhusudhan Chikkature 18a45c6cb8SMadhusudhan Chikkature #include <linux/module.h> 19a45c6cb8SMadhusudhan Chikkature #include <linux/init.h> 20ac330f44SAndy Shevchenko #include <linux/kernel.h> 21d900f712SDenis Karpov #include <linux/debugfs.h> 22c5c98927SRussell King #include <linux/dmaengine.h> 23d900f712SDenis Karpov #include <linux/seq_file.h> 24031cd037SFelipe Balbi #include <linux/sizes.h> 25a45c6cb8SMadhusudhan Chikkature #include <linux/interrupt.h> 26a45c6cb8SMadhusudhan Chikkature #include <linux/delay.h> 27a45c6cb8SMadhusudhan Chikkature #include <linux/dma-mapping.h> 28a45c6cb8SMadhusudhan Chikkature #include <linux/platform_device.h> 29a45c6cb8SMadhusudhan Chikkature #include <linux/timer.h> 30a45c6cb8SMadhusudhan Chikkature #include <linux/clk.h> 3146856a68SRajendra Nayak #include <linux/of.h> 3246856a68SRajendra Nayak #include <linux/of_gpio.h> 3346856a68SRajendra Nayak #include <linux/of_device.h> 343451c067SRussell King #include <linux/omap-dma.h> 35a45c6cb8SMadhusudhan Chikkature #include <linux/mmc/host.h> 3613189e78SJarkko Lavinen #include <linux/mmc/core.h> 3793caf8e6SAdrian Hunter #include <linux/mmc/mmc.h> 38a45c6cb8SMadhusudhan Chikkature #include <linux/io.h> 39db0fefc5SAdrian Hunter #include <linux/gpio.h> 40db0fefc5SAdrian Hunter #include <linux/regulator/consumer.h> 4146b76035SDaniel Mack #include <linux/pinctrl/consumer.h> 42fa4aa2d4SBalaji T K #include <linux/pm_runtime.h> 4368f39e74STony Lindgren #include <linux/platform_data/mmc-omap.h> 44a45c6cb8SMadhusudhan Chikkature 45a45c6cb8SMadhusudhan Chikkature /* OMAP HSMMC Host Controller Registers */ 4611dd62a7SDenis Karpov #define OMAP_HSMMC_SYSSTATUS 0x0014 47a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CON 0x002C 48a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_BLK 0x0104 49a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ARG 0x0108 50a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CMD 0x010C 51a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP10 0x0110 52a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP32 0x0114 53a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP54 0x0118 54a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_RSP76 0x011C 55a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_DATA 0x0120 56a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_HCTL 0x0128 57a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_SYSCTL 0x012C 58a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_STAT 0x0130 59a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_IE 0x0134 60a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_ISE 0x0138 61a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_CAPA 0x0140 62a45c6cb8SMadhusudhan Chikkature 63a45c6cb8SMadhusudhan Chikkature #define VS18 (1 << 26) 64a45c6cb8SMadhusudhan Chikkature #define VS30 (1 << 25) 65cd587096SHebbar, Gururaja #define HSS (1 << 21) 66a45c6cb8SMadhusudhan Chikkature #define SDVS18 (0x5 << 9) 67a45c6cb8SMadhusudhan Chikkature #define SDVS30 (0x6 << 9) 68eb250826SDavid Brownell #define SDVS33 (0x7 << 9) 691b331e69SKim Kyuwon #define SDVS_MASK 0x00000E00 70a45c6cb8SMadhusudhan Chikkature #define SDVSCLR 0xFFFFF1FF 71a45c6cb8SMadhusudhan Chikkature #define SDVSDET 0x00000400 72a45c6cb8SMadhusudhan Chikkature #define AUTOIDLE 0x1 73a45c6cb8SMadhusudhan Chikkature #define SDBP (1 << 8) 74a45c6cb8SMadhusudhan Chikkature #define DTO 0xe 75a45c6cb8SMadhusudhan Chikkature #define ICE 0x1 76a45c6cb8SMadhusudhan Chikkature #define ICS 0x2 77a45c6cb8SMadhusudhan Chikkature #define CEN (1 << 2) 78a45c6cb8SMadhusudhan Chikkature #define CLKD_MASK 0x0000FFC0 79a45c6cb8SMadhusudhan Chikkature #define CLKD_SHIFT 6 80a45c6cb8SMadhusudhan Chikkature #define DTO_MASK 0x000F0000 81a45c6cb8SMadhusudhan Chikkature #define DTO_SHIFT 16 82a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM (1 << 1) 83a45c6cb8SMadhusudhan Chikkature #define DP_SELECT (1 << 21) 84a45c6cb8SMadhusudhan Chikkature #define DDIR (1 << 4) 85a7e96879SVenkatraman S #define DMAE 0x1 86a45c6cb8SMadhusudhan Chikkature #define MSBS (1 << 5) 87a45c6cb8SMadhusudhan Chikkature #define BCE (1 << 1) 88a45c6cb8SMadhusudhan Chikkature #define FOUR_BIT (1 << 1) 89cd587096SHebbar, Gururaja #define HSPE (1 << 2) 9003b5d924SBalaji T K #define DDR (1 << 19) 9173153010SJarkko Lavinen #define DW8 (1 << 5) 92a45c6cb8SMadhusudhan Chikkature #define OD 0x1 93a45c6cb8SMadhusudhan Chikkature #define STAT_CLEAR 0xFFFFFFFF 94a45c6cb8SMadhusudhan Chikkature #define INIT_STREAM_CMD 0x00000000 95a45c6cb8SMadhusudhan Chikkature #define DUAL_VOLT_OCR_BIT 7 96a45c6cb8SMadhusudhan Chikkature #define SRC (1 << 25) 97a45c6cb8SMadhusudhan Chikkature #define SRD (1 << 26) 9811dd62a7SDenis Karpov #define SOFTRESET (1 << 1) 9911dd62a7SDenis Karpov #define RESETDONE (1 << 0) 100a45c6cb8SMadhusudhan Chikkature 101a7e96879SVenkatraman S /* Interrupt masks for IE and ISE register */ 102a7e96879SVenkatraman S #define CC_EN (1 << 0) 103a7e96879SVenkatraman S #define TC_EN (1 << 1) 104a7e96879SVenkatraman S #define BWR_EN (1 << 4) 105a7e96879SVenkatraman S #define BRR_EN (1 << 5) 106a7e96879SVenkatraman S #define ERR_EN (1 << 15) 107a7e96879SVenkatraman S #define CTO_EN (1 << 16) 108a7e96879SVenkatraman S #define CCRC_EN (1 << 17) 109a7e96879SVenkatraman S #define CEB_EN (1 << 18) 110a7e96879SVenkatraman S #define CIE_EN (1 << 19) 111a7e96879SVenkatraman S #define DTO_EN (1 << 20) 112a7e96879SVenkatraman S #define DCRC_EN (1 << 21) 113a7e96879SVenkatraman S #define DEB_EN (1 << 22) 114a7e96879SVenkatraman S #define CERR_EN (1 << 28) 115a7e96879SVenkatraman S #define BADA_EN (1 << 29) 116a7e96879SVenkatraman S 117a7e96879SVenkatraman S #define INT_EN_MASK (BADA_EN | CERR_EN | DEB_EN | DCRC_EN |\ 118a7e96879SVenkatraman S DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ 119a7e96879SVenkatraman S BRR_EN | BWR_EN | TC_EN | CC_EN) 120a7e96879SVenkatraman S 121fa4aa2d4SBalaji T K #define MMC_AUTOSUSPEND_DELAY 100 122a45c6cb8SMadhusudhan Chikkature #define MMC_TIMEOUT_MS 20 1236b206efeSAndy Shevchenko #define OMAP_MMC_MIN_CLOCK 400000 1246b206efeSAndy Shevchenko #define OMAP_MMC_MAX_CLOCK 52000000 1250005ae73SKishore Kadiyala #define DRIVER_NAME "omap_hsmmc" 126a45c6cb8SMadhusudhan Chikkature 127a45c6cb8SMadhusudhan Chikkature /* 128a45c6cb8SMadhusudhan Chikkature * One controller can have multiple slots, like on some omap boards using 129a45c6cb8SMadhusudhan Chikkature * omap.c controller driver. Luckily this is not currently done on any known 130a45c6cb8SMadhusudhan Chikkature * omap_hsmmc.c device. 131a45c6cb8SMadhusudhan Chikkature */ 132a45c6cb8SMadhusudhan Chikkature #define mmc_slot(host) (host->pdata->slots[host->slot_id]) 133a45c6cb8SMadhusudhan Chikkature 134a45c6cb8SMadhusudhan Chikkature /* 135a45c6cb8SMadhusudhan Chikkature * MMC Host controller read/write API's 136a45c6cb8SMadhusudhan Chikkature */ 137a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_READ(base, reg) \ 138a45c6cb8SMadhusudhan Chikkature __raw_readl((base) + OMAP_HSMMC_##reg) 139a45c6cb8SMadhusudhan Chikkature 140a45c6cb8SMadhusudhan Chikkature #define OMAP_HSMMC_WRITE(base, reg, val) \ 141a45c6cb8SMadhusudhan Chikkature __raw_writel((val), (base) + OMAP_HSMMC_##reg) 142a45c6cb8SMadhusudhan Chikkature 1439782aff8SPer Forlin struct omap_hsmmc_next { 1449782aff8SPer Forlin unsigned int dma_len; 1459782aff8SPer Forlin s32 cookie; 1469782aff8SPer Forlin }; 1479782aff8SPer Forlin 14870a3341aSDenis Karpov struct omap_hsmmc_host { 149a45c6cb8SMadhusudhan Chikkature struct device *dev; 150a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 151a45c6cb8SMadhusudhan Chikkature struct mmc_request *mrq; 152a45c6cb8SMadhusudhan Chikkature struct mmc_command *cmd; 153a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 154a45c6cb8SMadhusudhan Chikkature struct clk *fclk; 155a45c6cb8SMadhusudhan Chikkature struct clk *dbclk; 156db0fefc5SAdrian Hunter /* 157db0fefc5SAdrian Hunter * vcc == configured supply 158db0fefc5SAdrian Hunter * vcc_aux == optional 159db0fefc5SAdrian Hunter * - MMC1, supply for DAT4..DAT7 160db0fefc5SAdrian Hunter * - MMC2/MMC2, external level shifter voltage supply, for 161db0fefc5SAdrian Hunter * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) 162db0fefc5SAdrian Hunter */ 163db0fefc5SAdrian Hunter struct regulator *vcc; 164db0fefc5SAdrian Hunter struct regulator *vcc_aux; 165cf5ae40bSTony Lindgren int pbias_disable; 166a45c6cb8SMadhusudhan Chikkature void __iomem *base; 167a45c6cb8SMadhusudhan Chikkature resource_size_t mapbase; 1684dffd7a2SAdrian Hunter spinlock_t irq_lock; /* Prevent races with irq handler */ 169a45c6cb8SMadhusudhan Chikkature unsigned int dma_len; 1700ccd76d4SJuha Yrjola unsigned int dma_sg_idx; 171a45c6cb8SMadhusudhan Chikkature unsigned char bus_mode; 172a3621465SAdrian Hunter unsigned char power_mode; 173a45c6cb8SMadhusudhan Chikkature int suspended; 1740a82e06eSTony Lindgren u32 con; 1750a82e06eSTony Lindgren u32 hctl; 1760a82e06eSTony Lindgren u32 sysctl; 1770a82e06eSTony Lindgren u32 capa; 178a45c6cb8SMadhusudhan Chikkature int irq; 179a45c6cb8SMadhusudhan Chikkature int use_dma, dma_ch; 180c5c98927SRussell King struct dma_chan *tx_chan; 181c5c98927SRussell King struct dma_chan *rx_chan; 182a45c6cb8SMadhusudhan Chikkature int slot_id; 1834a694dc9SAdrian Hunter int response_busy; 18411dd62a7SDenis Karpov int context_loss; 185b62f6228SAdrian Hunter int protect_card; 186b62f6228SAdrian Hunter int reqs_blocked; 187db0fefc5SAdrian Hunter int use_reg; 188b417577dSAdrian Hunter int req_in_progress; 1899782aff8SPer Forlin struct omap_hsmmc_next next_data; 190a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata; 191a45c6cb8SMadhusudhan Chikkature }; 192a45c6cb8SMadhusudhan Chikkature 193db0fefc5SAdrian Hunter static int omap_hsmmc_card_detect(struct device *dev, int slot) 194db0fefc5SAdrian Hunter { 1959ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 1969ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 197db0fefc5SAdrian Hunter 198db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 199db0fefc5SAdrian Hunter return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 200db0fefc5SAdrian Hunter } 201db0fefc5SAdrian Hunter 202db0fefc5SAdrian Hunter static int omap_hsmmc_get_wp(struct device *dev, int slot) 203db0fefc5SAdrian Hunter { 2049ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2059ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 206db0fefc5SAdrian Hunter 207db0fefc5SAdrian Hunter /* NOTE: assumes write protect signal is active-high */ 208db0fefc5SAdrian Hunter return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); 209db0fefc5SAdrian Hunter } 210db0fefc5SAdrian Hunter 211db0fefc5SAdrian Hunter static int omap_hsmmc_get_cover_state(struct device *dev, int slot) 212db0fefc5SAdrian Hunter { 2139ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2149ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 215db0fefc5SAdrian Hunter 216db0fefc5SAdrian Hunter /* NOTE: assumes card detect signal is active-low */ 217db0fefc5SAdrian Hunter return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 218db0fefc5SAdrian Hunter } 219db0fefc5SAdrian Hunter 220db0fefc5SAdrian Hunter #ifdef CONFIG_PM 221db0fefc5SAdrian Hunter 222db0fefc5SAdrian Hunter static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) 223db0fefc5SAdrian Hunter { 2249ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2259ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 226db0fefc5SAdrian Hunter 227db0fefc5SAdrian Hunter disable_irq(mmc->slots[0].card_detect_irq); 228db0fefc5SAdrian Hunter return 0; 229db0fefc5SAdrian Hunter } 230db0fefc5SAdrian Hunter 231db0fefc5SAdrian Hunter static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) 232db0fefc5SAdrian Hunter { 2339ea28ecbSBalaji T K struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2349ea28ecbSBalaji T K struct omap_mmc_platform_data *mmc = host->pdata; 235db0fefc5SAdrian Hunter 236db0fefc5SAdrian Hunter enable_irq(mmc->slots[0].card_detect_irq); 237db0fefc5SAdrian Hunter return 0; 238db0fefc5SAdrian Hunter } 239db0fefc5SAdrian Hunter 240db0fefc5SAdrian Hunter #else 241db0fefc5SAdrian Hunter 242db0fefc5SAdrian Hunter #define omap_hsmmc_suspend_cdirq NULL 243db0fefc5SAdrian Hunter #define omap_hsmmc_resume_cdirq NULL 244db0fefc5SAdrian Hunter 245db0fefc5SAdrian Hunter #endif 246db0fefc5SAdrian Hunter 247b702b106SAdrian Hunter #ifdef CONFIG_REGULATOR 248b702b106SAdrian Hunter 24969b07eceSRajendra Nayak static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on, 250db0fefc5SAdrian Hunter int vdd) 251db0fefc5SAdrian Hunter { 252db0fefc5SAdrian Hunter struct omap_hsmmc_host *host = 253db0fefc5SAdrian Hunter platform_get_drvdata(to_platform_device(dev)); 254db0fefc5SAdrian Hunter int ret = 0; 255db0fefc5SAdrian Hunter 256db0fefc5SAdrian Hunter /* 257db0fefc5SAdrian Hunter * If we don't see a Vcc regulator, assume it's a fixed 258db0fefc5SAdrian Hunter * voltage always-on regulator. 259db0fefc5SAdrian Hunter */ 260db0fefc5SAdrian Hunter if (!host->vcc) 261db0fefc5SAdrian Hunter return 0; 2621f84b71bSRajendra Nayak /* 263cf5ae40bSTony Lindgren * With DT, never turn OFF the regulator for MMC1. This is because 2641f84b71bSRajendra Nayak * the pbias cell programming support is still missing when 2651f84b71bSRajendra Nayak * booting with Device tree 2661f84b71bSRajendra Nayak */ 267cf5ae40bSTony Lindgren if (host->pbias_disable && !vdd) 2681f84b71bSRajendra Nayak return 0; 269db0fefc5SAdrian Hunter 270db0fefc5SAdrian Hunter if (mmc_slot(host).before_set_reg) 271db0fefc5SAdrian Hunter mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 272db0fefc5SAdrian Hunter 273db0fefc5SAdrian Hunter /* 274db0fefc5SAdrian Hunter * Assume Vcc regulator is used only to power the card ... OMAP 275db0fefc5SAdrian Hunter * VDDS is used to power the pins, optionally with a transceiver to 276db0fefc5SAdrian Hunter * support cards using voltages other than VDDS (1.8V nominal). When a 277db0fefc5SAdrian Hunter * transceiver is used, DAT3..7 are muxed as transceiver control pins. 278db0fefc5SAdrian Hunter * 279db0fefc5SAdrian Hunter * In some cases this regulator won't support enable/disable; 280db0fefc5SAdrian Hunter * e.g. it's a fixed rail for a WLAN chip. 281db0fefc5SAdrian Hunter * 282db0fefc5SAdrian Hunter * In other cases vcc_aux switches interface power. Example, for 283db0fefc5SAdrian Hunter * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 284db0fefc5SAdrian Hunter * chips/cards need an interface voltage rail too. 285db0fefc5SAdrian Hunter */ 286db0fefc5SAdrian Hunter if (power_on) { 28799fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 288db0fefc5SAdrian Hunter /* Enable interface voltage rail, if needed */ 289db0fefc5SAdrian Hunter if (ret == 0 && host->vcc_aux) { 290db0fefc5SAdrian Hunter ret = regulator_enable(host->vcc_aux); 291db0fefc5SAdrian Hunter if (ret < 0) 29299fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 29399fc5131SLinus Walleij host->vcc, 0); 294db0fefc5SAdrian Hunter } 295db0fefc5SAdrian Hunter } else { 29699fc5131SLinus Walleij /* Shut down the rail */ 2976da20c89SAdrian Hunter if (host->vcc_aux) 298db0fefc5SAdrian Hunter ret = regulator_disable(host->vcc_aux); 29999fc5131SLinus Walleij if (!ret) { 30099fc5131SLinus Walleij /* Then proceed to shut down the local regulator */ 30199fc5131SLinus Walleij ret = mmc_regulator_set_ocr(host->mmc, 30299fc5131SLinus Walleij host->vcc, 0); 30399fc5131SLinus Walleij } 304db0fefc5SAdrian Hunter } 305db0fefc5SAdrian Hunter 306db0fefc5SAdrian Hunter if (mmc_slot(host).after_set_reg) 307db0fefc5SAdrian Hunter mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 308db0fefc5SAdrian Hunter 309db0fefc5SAdrian Hunter return ret; 310db0fefc5SAdrian Hunter } 311db0fefc5SAdrian Hunter 312db0fefc5SAdrian Hunter static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 313db0fefc5SAdrian Hunter { 314db0fefc5SAdrian Hunter struct regulator *reg; 31564be9782Skishore kadiyala int ocr_value = 0; 316db0fefc5SAdrian Hunter 317db0fefc5SAdrian Hunter reg = regulator_get(host->dev, "vmmc"); 318db0fefc5SAdrian Hunter if (IS_ERR(reg)) { 319b1e056aeSVenkatraman S dev_err(host->dev, "vmmc regulator missing\n"); 3201fdc90fbSNeilBrown return PTR_ERR(reg); 321db0fefc5SAdrian Hunter } else { 3221fdc90fbSNeilBrown mmc_slot(host).set_power = omap_hsmmc_set_power; 323db0fefc5SAdrian Hunter host->vcc = reg; 32464be9782Skishore kadiyala ocr_value = mmc_regulator_get_ocrmask(reg); 32564be9782Skishore kadiyala if (!mmc_slot(host).ocr_mask) { 32664be9782Skishore kadiyala mmc_slot(host).ocr_mask = ocr_value; 32764be9782Skishore kadiyala } else { 32864be9782Skishore kadiyala if (!(mmc_slot(host).ocr_mask & ocr_value)) { 3292cecdf00SRajendra Nayak dev_err(host->dev, "ocrmask %x is not supported\n", 330e3f1adb6SRajendra Nayak mmc_slot(host).ocr_mask); 33164be9782Skishore kadiyala mmc_slot(host).ocr_mask = 0; 33264be9782Skishore kadiyala return -EINVAL; 33364be9782Skishore kadiyala } 33464be9782Skishore kadiyala } 335db0fefc5SAdrian Hunter 336db0fefc5SAdrian Hunter /* Allow an aux regulator */ 337db0fefc5SAdrian Hunter reg = regulator_get(host->dev, "vmmc_aux"); 338db0fefc5SAdrian Hunter host->vcc_aux = IS_ERR(reg) ? NULL : reg; 339db0fefc5SAdrian Hunter 340b1c1df7aSBalaji T K /* For eMMC do not power off when not in sleep state */ 341b1c1df7aSBalaji T K if (mmc_slot(host).no_regulator_off_init) 342b1c1df7aSBalaji T K return 0; 343db0fefc5SAdrian Hunter /* 344db0fefc5SAdrian Hunter * UGLY HACK: workaround regulator framework bugs. 345db0fefc5SAdrian Hunter * When the bootloader leaves a supply active, it's 346db0fefc5SAdrian Hunter * initialized with zero usecount ... and we can't 347db0fefc5SAdrian Hunter * disable it without first enabling it. Until the 348db0fefc5SAdrian Hunter * framework is fixed, we need a workaround like this 349db0fefc5SAdrian Hunter * (which is safe for MMC, but not in general). 350db0fefc5SAdrian Hunter */ 351e840ce13SAdrian Hunter if (regulator_is_enabled(host->vcc) > 0 || 352e840ce13SAdrian Hunter (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) { 353e840ce13SAdrian Hunter int vdd = ffs(mmc_slot(host).ocr_mask) - 1; 354e840ce13SAdrian Hunter 355e840ce13SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 356e840ce13SAdrian Hunter 1, vdd); 357e840ce13SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 358e840ce13SAdrian Hunter 0, 0); 359db0fefc5SAdrian Hunter } 360db0fefc5SAdrian Hunter } 361db0fefc5SAdrian Hunter 362db0fefc5SAdrian Hunter return 0; 363db0fefc5SAdrian Hunter } 364db0fefc5SAdrian Hunter 365db0fefc5SAdrian Hunter static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 366db0fefc5SAdrian Hunter { 367db0fefc5SAdrian Hunter regulator_put(host->vcc); 368db0fefc5SAdrian Hunter regulator_put(host->vcc_aux); 369db0fefc5SAdrian Hunter mmc_slot(host).set_power = NULL; 370db0fefc5SAdrian Hunter } 371db0fefc5SAdrian Hunter 372b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 373b702b106SAdrian Hunter { 374b702b106SAdrian Hunter return 1; 375b702b106SAdrian Hunter } 376b702b106SAdrian Hunter 377b702b106SAdrian Hunter #else 378b702b106SAdrian Hunter 379b702b106SAdrian Hunter static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 380b702b106SAdrian Hunter { 381b702b106SAdrian Hunter return -EINVAL; 382b702b106SAdrian Hunter } 383b702b106SAdrian Hunter 384b702b106SAdrian Hunter static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 385b702b106SAdrian Hunter { 386b702b106SAdrian Hunter } 387b702b106SAdrian Hunter 388b702b106SAdrian Hunter static inline int omap_hsmmc_have_reg(void) 389b702b106SAdrian Hunter { 390b702b106SAdrian Hunter return 0; 391b702b106SAdrian Hunter } 392b702b106SAdrian Hunter 393b702b106SAdrian Hunter #endif 394b702b106SAdrian Hunter 395b702b106SAdrian Hunter static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) 396b702b106SAdrian Hunter { 397b702b106SAdrian Hunter int ret; 398b702b106SAdrian Hunter 399b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) { 400b702b106SAdrian Hunter if (pdata->slots[0].cover) 401b702b106SAdrian Hunter pdata->slots[0].get_cover_state = 402b702b106SAdrian Hunter omap_hsmmc_get_cover_state; 403b702b106SAdrian Hunter else 404b702b106SAdrian Hunter pdata->slots[0].card_detect = omap_hsmmc_card_detect; 405b702b106SAdrian Hunter pdata->slots[0].card_detect_irq = 406b702b106SAdrian Hunter gpio_to_irq(pdata->slots[0].switch_pin); 407b702b106SAdrian Hunter ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd"); 408b702b106SAdrian Hunter if (ret) 409b702b106SAdrian Hunter return ret; 410b702b106SAdrian Hunter ret = gpio_direction_input(pdata->slots[0].switch_pin); 411b702b106SAdrian Hunter if (ret) 412b702b106SAdrian Hunter goto err_free_sp; 413b702b106SAdrian Hunter } else 414b702b106SAdrian Hunter pdata->slots[0].switch_pin = -EINVAL; 415b702b106SAdrian Hunter 416b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].gpio_wp)) { 417b702b106SAdrian Hunter pdata->slots[0].get_ro = omap_hsmmc_get_wp; 418b702b106SAdrian Hunter ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp"); 419b702b106SAdrian Hunter if (ret) 420b702b106SAdrian Hunter goto err_free_cd; 421b702b106SAdrian Hunter ret = gpio_direction_input(pdata->slots[0].gpio_wp); 422b702b106SAdrian Hunter if (ret) 423b702b106SAdrian Hunter goto err_free_wp; 424b702b106SAdrian Hunter } else 425b702b106SAdrian Hunter pdata->slots[0].gpio_wp = -EINVAL; 426b702b106SAdrian Hunter 427b702b106SAdrian Hunter return 0; 428b702b106SAdrian Hunter 429b702b106SAdrian Hunter err_free_wp: 430b702b106SAdrian Hunter gpio_free(pdata->slots[0].gpio_wp); 431b702b106SAdrian Hunter err_free_cd: 432b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) 433b702b106SAdrian Hunter err_free_sp: 434b702b106SAdrian Hunter gpio_free(pdata->slots[0].switch_pin); 435b702b106SAdrian Hunter return ret; 436b702b106SAdrian Hunter } 437b702b106SAdrian Hunter 438b702b106SAdrian Hunter static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) 439b702b106SAdrian Hunter { 440b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].gpio_wp)) 441b702b106SAdrian Hunter gpio_free(pdata->slots[0].gpio_wp); 442b702b106SAdrian Hunter if (gpio_is_valid(pdata->slots[0].switch_pin)) 443b702b106SAdrian Hunter gpio_free(pdata->slots[0].switch_pin); 444b702b106SAdrian Hunter } 445b702b106SAdrian Hunter 446a45c6cb8SMadhusudhan Chikkature /* 447e0c7f99bSAndy Shevchenko * Start clock to the card 448e0c7f99bSAndy Shevchenko */ 449e0c7f99bSAndy Shevchenko static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 450e0c7f99bSAndy Shevchenko { 451e0c7f99bSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 452e0c7f99bSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 453e0c7f99bSAndy Shevchenko } 454e0c7f99bSAndy Shevchenko 455e0c7f99bSAndy Shevchenko /* 456a45c6cb8SMadhusudhan Chikkature * Stop clock to the card 457a45c6cb8SMadhusudhan Chikkature */ 45870a3341aSDenis Karpov static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 459a45c6cb8SMadhusudhan Chikkature { 460a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, 461a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 462a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 4637122bbb0SMasanari Iida dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); 464a45c6cb8SMadhusudhan Chikkature } 465a45c6cb8SMadhusudhan Chikkature 46693caf8e6SAdrian Hunter static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 46793caf8e6SAdrian Hunter struct mmc_command *cmd) 468b417577dSAdrian Hunter { 469b417577dSAdrian Hunter unsigned int irq_mask; 470b417577dSAdrian Hunter 471b417577dSAdrian Hunter if (host->use_dma) 472a7e96879SVenkatraman S irq_mask = INT_EN_MASK & ~(BRR_EN | BWR_EN); 473b417577dSAdrian Hunter else 474b417577dSAdrian Hunter irq_mask = INT_EN_MASK; 475b417577dSAdrian Hunter 47693caf8e6SAdrian Hunter /* Disable timeout for erases */ 47793caf8e6SAdrian Hunter if (cmd->opcode == MMC_ERASE) 478a7e96879SVenkatraman S irq_mask &= ~DTO_EN; 47993caf8e6SAdrian Hunter 480b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 481b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 482b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 483b417577dSAdrian Hunter } 484b417577dSAdrian Hunter 485b417577dSAdrian Hunter static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 486b417577dSAdrian Hunter { 487b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, ISE, 0); 488b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, 0); 489b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 490b417577dSAdrian Hunter } 491b417577dSAdrian Hunter 492ac330f44SAndy Shevchenko /* Calculate divisor for the given clock frequency */ 493d83b6e03SBalaji TK static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 494ac330f44SAndy Shevchenko { 495ac330f44SAndy Shevchenko u16 dsor = 0; 496ac330f44SAndy Shevchenko 497ac330f44SAndy Shevchenko if (ios->clock) { 498d83b6e03SBalaji TK dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 499ac330f44SAndy Shevchenko if (dsor > 250) 500ac330f44SAndy Shevchenko dsor = 250; 501ac330f44SAndy Shevchenko } 502ac330f44SAndy Shevchenko 503ac330f44SAndy Shevchenko return dsor; 504ac330f44SAndy Shevchenko } 505ac330f44SAndy Shevchenko 5065934df2fSAndy Shevchenko static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 5075934df2fSAndy Shevchenko { 5085934df2fSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5095934df2fSAndy Shevchenko unsigned long regval; 5105934df2fSAndy Shevchenko unsigned long timeout; 511cd587096SHebbar, Gururaja unsigned long clkdiv; 5125934df2fSAndy Shevchenko 5138986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 5145934df2fSAndy Shevchenko 5155934df2fSAndy Shevchenko omap_hsmmc_stop_clock(host); 5165934df2fSAndy Shevchenko 5175934df2fSAndy Shevchenko regval = OMAP_HSMMC_READ(host->base, SYSCTL); 5185934df2fSAndy Shevchenko regval = regval & ~(CLKD_MASK | DTO_MASK); 519cd587096SHebbar, Gururaja clkdiv = calc_divisor(host, ios); 520cd587096SHebbar, Gururaja regval = regval | (clkdiv << 6) | (DTO << 16); 5215934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 5225934df2fSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, SYSCTL, 5235934df2fSAndy Shevchenko OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 5245934df2fSAndy Shevchenko 5255934df2fSAndy Shevchenko /* Wait till the ICS bit is set */ 5265934df2fSAndy Shevchenko timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 5275934df2fSAndy Shevchenko while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 5285934df2fSAndy Shevchenko && time_before(jiffies, timeout)) 5295934df2fSAndy Shevchenko cpu_relax(); 5305934df2fSAndy Shevchenko 531cd587096SHebbar, Gururaja /* 532cd587096SHebbar, Gururaja * Enable High-Speed Support 533cd587096SHebbar, Gururaja * Pre-Requisites 534cd587096SHebbar, Gururaja * - Controller should support High-Speed-Enable Bit 535cd587096SHebbar, Gururaja * - Controller should not be using DDR Mode 536cd587096SHebbar, Gururaja * - Controller should advertise that it supports High Speed 537cd587096SHebbar, Gururaja * in capabilities register 538cd587096SHebbar, Gururaja * - MMC/SD clock coming out of controller > 25MHz 539cd587096SHebbar, Gururaja */ 540cd587096SHebbar, Gururaja if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) && 541cd587096SHebbar, Gururaja (ios->timing != MMC_TIMING_UHS_DDR50) && 542cd587096SHebbar, Gururaja ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 543cd587096SHebbar, Gururaja regval = OMAP_HSMMC_READ(host->base, HCTL); 544cd587096SHebbar, Gururaja if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 545cd587096SHebbar, Gururaja regval |= HSPE; 546cd587096SHebbar, Gururaja else 547cd587096SHebbar, Gururaja regval &= ~HSPE; 548cd587096SHebbar, Gururaja 549cd587096SHebbar, Gururaja OMAP_HSMMC_WRITE(host->base, HCTL, regval); 550cd587096SHebbar, Gururaja } 551cd587096SHebbar, Gururaja 5525934df2fSAndy Shevchenko omap_hsmmc_start_clock(host); 5535934df2fSAndy Shevchenko } 5545934df2fSAndy Shevchenko 5553796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 5563796fb8aSAndy Shevchenko { 5573796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5583796fb8aSAndy Shevchenko u32 con; 5593796fb8aSAndy Shevchenko 5603796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 56103b5d924SBalaji T K if (ios->timing == MMC_TIMING_UHS_DDR50) 56203b5d924SBalaji T K con |= DDR; /* configure in DDR mode */ 56303b5d924SBalaji T K else 56403b5d924SBalaji T K con &= ~DDR; 5653796fb8aSAndy Shevchenko switch (ios->bus_width) { 5663796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_8: 5673796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 5683796fb8aSAndy Shevchenko break; 5693796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_4: 5703796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 5713796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 5723796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 5733796fb8aSAndy Shevchenko break; 5743796fb8aSAndy Shevchenko case MMC_BUS_WIDTH_1: 5753796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 5763796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, HCTL, 5773796fb8aSAndy Shevchenko OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 5783796fb8aSAndy Shevchenko break; 5793796fb8aSAndy Shevchenko } 5803796fb8aSAndy Shevchenko } 5813796fb8aSAndy Shevchenko 5823796fb8aSAndy Shevchenko static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 5833796fb8aSAndy Shevchenko { 5843796fb8aSAndy Shevchenko struct mmc_ios *ios = &host->mmc->ios; 5853796fb8aSAndy Shevchenko u32 con; 5863796fb8aSAndy Shevchenko 5873796fb8aSAndy Shevchenko con = OMAP_HSMMC_READ(host->base, CON); 5883796fb8aSAndy Shevchenko if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 5893796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con | OD); 5903796fb8aSAndy Shevchenko else 5913796fb8aSAndy Shevchenko OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 5923796fb8aSAndy Shevchenko } 5933796fb8aSAndy Shevchenko 59411dd62a7SDenis Karpov #ifdef CONFIG_PM 59511dd62a7SDenis Karpov 59611dd62a7SDenis Karpov /* 59711dd62a7SDenis Karpov * Restore the MMC host context, if it was lost as result of a 59811dd62a7SDenis Karpov * power state change. 59911dd62a7SDenis Karpov */ 60070a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 60111dd62a7SDenis Karpov { 60211dd62a7SDenis Karpov struct mmc_ios *ios = &host->mmc->ios; 6033796fb8aSAndy Shevchenko u32 hctl, capa; 60411dd62a7SDenis Karpov unsigned long timeout; 60511dd62a7SDenis Karpov 6066c31b215SVenkatraman S if (!OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) 6076c31b215SVenkatraman S return 1; 60811dd62a7SDenis Karpov 6090a82e06eSTony Lindgren if (host->con == OMAP_HSMMC_READ(host->base, CON) && 6100a82e06eSTony Lindgren host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && 6110a82e06eSTony Lindgren host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && 6120a82e06eSTony Lindgren host->capa == OMAP_HSMMC_READ(host->base, CAPA)) 6130a82e06eSTony Lindgren return 0; 6140a82e06eSTony Lindgren 6150a82e06eSTony Lindgren host->context_loss++; 6160a82e06eSTony Lindgren 617c2200efbSBalaji T K if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 61811dd62a7SDenis Karpov if (host->power_mode != MMC_POWER_OFF && 61911dd62a7SDenis Karpov (1 << ios->vdd) <= MMC_VDD_23_24) 62011dd62a7SDenis Karpov hctl = SDVS18; 62111dd62a7SDenis Karpov else 62211dd62a7SDenis Karpov hctl = SDVS30; 62311dd62a7SDenis Karpov capa = VS30 | VS18; 62411dd62a7SDenis Karpov } else { 62511dd62a7SDenis Karpov hctl = SDVS18; 62611dd62a7SDenis Karpov capa = VS18; 62711dd62a7SDenis Karpov } 62811dd62a7SDenis Karpov 62911dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 63011dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | hctl); 63111dd62a7SDenis Karpov 63211dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, CAPA, 63311dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA) | capa); 63411dd62a7SDenis Karpov 63511dd62a7SDenis Karpov OMAP_HSMMC_WRITE(host->base, HCTL, 63611dd62a7SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 63711dd62a7SDenis Karpov 63811dd62a7SDenis Karpov timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 63911dd62a7SDenis Karpov while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 64011dd62a7SDenis Karpov && time_before(jiffies, timeout)) 64111dd62a7SDenis Karpov ; 64211dd62a7SDenis Karpov 643b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 64411dd62a7SDenis Karpov 64511dd62a7SDenis Karpov /* Do not initialize card-specific things if the power is off */ 64611dd62a7SDenis Karpov if (host->power_mode == MMC_POWER_OFF) 64711dd62a7SDenis Karpov goto out; 64811dd62a7SDenis Karpov 6493796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 65011dd62a7SDenis Karpov 6515934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 65211dd62a7SDenis Karpov 6533796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 6543796fb8aSAndy Shevchenko 65511dd62a7SDenis Karpov out: 6560a82e06eSTony Lindgren dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", 6570a82e06eSTony Lindgren host->context_loss); 65811dd62a7SDenis Karpov return 0; 65911dd62a7SDenis Karpov } 66011dd62a7SDenis Karpov 66111dd62a7SDenis Karpov /* 66211dd62a7SDenis Karpov * Save the MMC host context (store the number of power state changes so far). 66311dd62a7SDenis Karpov */ 66470a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 66511dd62a7SDenis Karpov { 6660a82e06eSTony Lindgren host->con = OMAP_HSMMC_READ(host->base, CON); 6670a82e06eSTony Lindgren host->hctl = OMAP_HSMMC_READ(host->base, HCTL); 6680a82e06eSTony Lindgren host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); 6690a82e06eSTony Lindgren host->capa = OMAP_HSMMC_READ(host->base, CAPA); 67011dd62a7SDenis Karpov } 67111dd62a7SDenis Karpov 67211dd62a7SDenis Karpov #else 67311dd62a7SDenis Karpov 67470a3341aSDenis Karpov static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 67511dd62a7SDenis Karpov { 67611dd62a7SDenis Karpov return 0; 67711dd62a7SDenis Karpov } 67811dd62a7SDenis Karpov 67970a3341aSDenis Karpov static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 68011dd62a7SDenis Karpov { 68111dd62a7SDenis Karpov } 68211dd62a7SDenis Karpov 68311dd62a7SDenis Karpov #endif 68411dd62a7SDenis Karpov 685a45c6cb8SMadhusudhan Chikkature /* 686a45c6cb8SMadhusudhan Chikkature * Send init stream sequence to card 687a45c6cb8SMadhusudhan Chikkature * before sending IDLE command 688a45c6cb8SMadhusudhan Chikkature */ 68970a3341aSDenis Karpov static void send_init_stream(struct omap_hsmmc_host *host) 690a45c6cb8SMadhusudhan Chikkature { 691a45c6cb8SMadhusudhan Chikkature int reg = 0; 692a45c6cb8SMadhusudhan Chikkature unsigned long timeout; 693a45c6cb8SMadhusudhan Chikkature 694b62f6228SAdrian Hunter if (host->protect_card) 695b62f6228SAdrian Hunter return; 696b62f6228SAdrian Hunter 697a45c6cb8SMadhusudhan Chikkature disable_irq(host->irq); 698b417577dSAdrian Hunter 699b417577dSAdrian Hunter OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 700a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 701a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 702a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 703a45c6cb8SMadhusudhan Chikkature 704a45c6cb8SMadhusudhan Chikkature timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 705a7e96879SVenkatraman S while ((reg != CC_EN) && time_before(jiffies, timeout)) 706a7e96879SVenkatraman S reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; 707a45c6cb8SMadhusudhan Chikkature 708a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CON, 709a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 710c653a6d4SAdrian Hunter 711c653a6d4SAdrian Hunter OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 712c653a6d4SAdrian Hunter OMAP_HSMMC_READ(host->base, STAT); 713c653a6d4SAdrian Hunter 714a45c6cb8SMadhusudhan Chikkature enable_irq(host->irq); 715a45c6cb8SMadhusudhan Chikkature } 716a45c6cb8SMadhusudhan Chikkature 717a45c6cb8SMadhusudhan Chikkature static inline 71870a3341aSDenis Karpov int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 719a45c6cb8SMadhusudhan Chikkature { 720a45c6cb8SMadhusudhan Chikkature int r = 1; 721a45c6cb8SMadhusudhan Chikkature 722191d1f1dSDenis Karpov if (mmc_slot(host).get_cover_state) 723191d1f1dSDenis Karpov r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); 724a45c6cb8SMadhusudhan Chikkature return r; 725a45c6cb8SMadhusudhan Chikkature } 726a45c6cb8SMadhusudhan Chikkature 727a45c6cb8SMadhusudhan Chikkature static ssize_t 72870a3341aSDenis Karpov omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 729a45c6cb8SMadhusudhan Chikkature char *buf) 730a45c6cb8SMadhusudhan Chikkature { 731a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 73270a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 733a45c6cb8SMadhusudhan Chikkature 73470a3341aSDenis Karpov return sprintf(buf, "%s\n", 73570a3341aSDenis Karpov omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 736a45c6cb8SMadhusudhan Chikkature } 737a45c6cb8SMadhusudhan Chikkature 73870a3341aSDenis Karpov static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 739a45c6cb8SMadhusudhan Chikkature 740a45c6cb8SMadhusudhan Chikkature static ssize_t 74170a3341aSDenis Karpov omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 742a45c6cb8SMadhusudhan Chikkature char *buf) 743a45c6cb8SMadhusudhan Chikkature { 744a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 74570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 746a45c6cb8SMadhusudhan Chikkature 747191d1f1dSDenis Karpov return sprintf(buf, "%s\n", mmc_slot(host).name); 748a45c6cb8SMadhusudhan Chikkature } 749a45c6cb8SMadhusudhan Chikkature 75070a3341aSDenis Karpov static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 751a45c6cb8SMadhusudhan Chikkature 752a45c6cb8SMadhusudhan Chikkature /* 753a45c6cb8SMadhusudhan Chikkature * Configure the response type and send the cmd. 754a45c6cb8SMadhusudhan Chikkature */ 755a45c6cb8SMadhusudhan Chikkature static void 75670a3341aSDenis Karpov omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 757a45c6cb8SMadhusudhan Chikkature struct mmc_data *data) 758a45c6cb8SMadhusudhan Chikkature { 759a45c6cb8SMadhusudhan Chikkature int cmdreg = 0, resptype = 0, cmdtype = 0; 760a45c6cb8SMadhusudhan Chikkature 7618986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 762a45c6cb8SMadhusudhan Chikkature mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 763a45c6cb8SMadhusudhan Chikkature host->cmd = cmd; 764a45c6cb8SMadhusudhan Chikkature 76593caf8e6SAdrian Hunter omap_hsmmc_enable_irq(host, cmd); 766a45c6cb8SMadhusudhan Chikkature 7674a694dc9SAdrian Hunter host->response_busy = 0; 768a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 769a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) 770a45c6cb8SMadhusudhan Chikkature resptype = 1; 7714a694dc9SAdrian Hunter else if (cmd->flags & MMC_RSP_BUSY) { 7724a694dc9SAdrian Hunter resptype = 3; 7734a694dc9SAdrian Hunter host->response_busy = 1; 7744a694dc9SAdrian Hunter } else 775a45c6cb8SMadhusudhan Chikkature resptype = 2; 776a45c6cb8SMadhusudhan Chikkature } 777a45c6cb8SMadhusudhan Chikkature 778a45c6cb8SMadhusudhan Chikkature /* 779a45c6cb8SMadhusudhan Chikkature * Unlike OMAP1 controller, the cmdtype does not seem to be based on 780a45c6cb8SMadhusudhan Chikkature * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 781a45c6cb8SMadhusudhan Chikkature * a val of 0x3, rest 0x0. 782a45c6cb8SMadhusudhan Chikkature */ 783a45c6cb8SMadhusudhan Chikkature if (cmd == host->mrq->stop) 784a45c6cb8SMadhusudhan Chikkature cmdtype = 0x3; 785a45c6cb8SMadhusudhan Chikkature 786a45c6cb8SMadhusudhan Chikkature cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 787a45c6cb8SMadhusudhan Chikkature 788a45c6cb8SMadhusudhan Chikkature if (data) { 789a45c6cb8SMadhusudhan Chikkature cmdreg |= DP_SELECT | MSBS | BCE; 790a45c6cb8SMadhusudhan Chikkature if (data->flags & MMC_DATA_READ) 791a45c6cb8SMadhusudhan Chikkature cmdreg |= DDIR; 792a45c6cb8SMadhusudhan Chikkature else 793a45c6cb8SMadhusudhan Chikkature cmdreg &= ~(DDIR); 794a45c6cb8SMadhusudhan Chikkature } 795a45c6cb8SMadhusudhan Chikkature 796a45c6cb8SMadhusudhan Chikkature if (host->use_dma) 797a7e96879SVenkatraman S cmdreg |= DMAE; 798a45c6cb8SMadhusudhan Chikkature 799b417577dSAdrian Hunter host->req_in_progress = 1; 8004dffd7a2SAdrian Hunter 801a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 802a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 803a45c6cb8SMadhusudhan Chikkature } 804a45c6cb8SMadhusudhan Chikkature 8050ccd76d4SJuha Yrjola static int 80670a3341aSDenis Karpov omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 8070ccd76d4SJuha Yrjola { 8080ccd76d4SJuha Yrjola if (data->flags & MMC_DATA_WRITE) 8090ccd76d4SJuha Yrjola return DMA_TO_DEVICE; 8100ccd76d4SJuha Yrjola else 8110ccd76d4SJuha Yrjola return DMA_FROM_DEVICE; 8120ccd76d4SJuha Yrjola } 8130ccd76d4SJuha Yrjola 814c5c98927SRussell King static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 815c5c98927SRussell King struct mmc_data *data) 816c5c98927SRussell King { 817c5c98927SRussell King return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 818c5c98927SRussell King } 819c5c98927SRussell King 820b417577dSAdrian Hunter static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 821b417577dSAdrian Hunter { 822b417577dSAdrian Hunter int dma_ch; 82331463b14SVenkatraman S unsigned long flags; 824b417577dSAdrian Hunter 82531463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 826b417577dSAdrian Hunter host->req_in_progress = 0; 827b417577dSAdrian Hunter dma_ch = host->dma_ch; 82831463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 829b417577dSAdrian Hunter 830b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 831b417577dSAdrian Hunter /* Do not complete the request if DMA is still in progress */ 832b417577dSAdrian Hunter if (mrq->data && host->use_dma && dma_ch != -1) 833b417577dSAdrian Hunter return; 834b417577dSAdrian Hunter host->mrq = NULL; 835b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 836b417577dSAdrian Hunter } 837b417577dSAdrian Hunter 838a45c6cb8SMadhusudhan Chikkature /* 839a45c6cb8SMadhusudhan Chikkature * Notify the transfer complete to MMC core 840a45c6cb8SMadhusudhan Chikkature */ 841a45c6cb8SMadhusudhan Chikkature static void 84270a3341aSDenis Karpov omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 843a45c6cb8SMadhusudhan Chikkature { 8444a694dc9SAdrian Hunter if (!data) { 8454a694dc9SAdrian Hunter struct mmc_request *mrq = host->mrq; 8464a694dc9SAdrian Hunter 84723050103SAdrian Hunter /* TC before CC from CMD6 - don't know why, but it happens */ 84823050103SAdrian Hunter if (host->cmd && host->cmd->opcode == 6 && 84923050103SAdrian Hunter host->response_busy) { 85023050103SAdrian Hunter host->response_busy = 0; 85123050103SAdrian Hunter return; 85223050103SAdrian Hunter } 85323050103SAdrian Hunter 854b417577dSAdrian Hunter omap_hsmmc_request_done(host, mrq); 8554a694dc9SAdrian Hunter return; 8564a694dc9SAdrian Hunter } 8574a694dc9SAdrian Hunter 858a45c6cb8SMadhusudhan Chikkature host->data = NULL; 859a45c6cb8SMadhusudhan Chikkature 860a45c6cb8SMadhusudhan Chikkature if (!data->error) 861a45c6cb8SMadhusudhan Chikkature data->bytes_xfered += data->blocks * (data->blksz); 862a45c6cb8SMadhusudhan Chikkature else 863a45c6cb8SMadhusudhan Chikkature data->bytes_xfered = 0; 864a45c6cb8SMadhusudhan Chikkature 865fe852273SMing Lei if (!data->stop) { 866dba3c29eSBalaji T K omap_hsmmc_request_done(host, data->mrq); 867fe852273SMing Lei return; 868dba3c29eSBalaji T K } 869fe852273SMing Lei omap_hsmmc_start_command(host, data->stop, NULL); 870a45c6cb8SMadhusudhan Chikkature } 871a45c6cb8SMadhusudhan Chikkature 872a45c6cb8SMadhusudhan Chikkature /* 873a45c6cb8SMadhusudhan Chikkature * Notify the core about command completion 874a45c6cb8SMadhusudhan Chikkature */ 875a45c6cb8SMadhusudhan Chikkature static void 87670a3341aSDenis Karpov omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 877a45c6cb8SMadhusudhan Chikkature { 878a45c6cb8SMadhusudhan Chikkature host->cmd = NULL; 879a45c6cb8SMadhusudhan Chikkature 880a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_PRESENT) { 881a45c6cb8SMadhusudhan Chikkature if (cmd->flags & MMC_RSP_136) { 882a45c6cb8SMadhusudhan Chikkature /* response type 2 */ 883a45c6cb8SMadhusudhan Chikkature cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 884a45c6cb8SMadhusudhan Chikkature cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 885a45c6cb8SMadhusudhan Chikkature cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 886a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 887a45c6cb8SMadhusudhan Chikkature } else { 888a45c6cb8SMadhusudhan Chikkature /* response types 1, 1b, 3, 4, 5, 6 */ 889a45c6cb8SMadhusudhan Chikkature cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 890a45c6cb8SMadhusudhan Chikkature } 891a45c6cb8SMadhusudhan Chikkature } 892b417577dSAdrian Hunter if ((host->data == NULL && !host->response_busy) || cmd->error) 893b417577dSAdrian Hunter omap_hsmmc_request_done(host, cmd->mrq); 894a45c6cb8SMadhusudhan Chikkature } 895a45c6cb8SMadhusudhan Chikkature 896a45c6cb8SMadhusudhan Chikkature /* 897a45c6cb8SMadhusudhan Chikkature * DMA clean up for command errors 898a45c6cb8SMadhusudhan Chikkature */ 89970a3341aSDenis Karpov static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 900a45c6cb8SMadhusudhan Chikkature { 901b417577dSAdrian Hunter int dma_ch; 90231463b14SVenkatraman S unsigned long flags; 903b417577dSAdrian Hunter 90482788ff5SJarkko Lavinen host->data->error = errno; 905a45c6cb8SMadhusudhan Chikkature 90631463b14SVenkatraman S spin_lock_irqsave(&host->irq_lock, flags); 907b417577dSAdrian Hunter dma_ch = host->dma_ch; 908b417577dSAdrian Hunter host->dma_ch = -1; 90931463b14SVenkatraman S spin_unlock_irqrestore(&host->irq_lock, flags); 910b417577dSAdrian Hunter 911b417577dSAdrian Hunter if (host->use_dma && dma_ch != -1) { 912c5c98927SRussell King struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 913c5c98927SRussell King 914c5c98927SRussell King dmaengine_terminate_all(chan); 915c5c98927SRussell King dma_unmap_sg(chan->device->dev, 916c5c98927SRussell King host->data->sg, host->data->sg_len, 91770a3341aSDenis Karpov omap_hsmmc_get_dma_dir(host, host->data)); 918c5c98927SRussell King 919053bf34fSPer Forlin host->data->host_cookie = 0; 920a45c6cb8SMadhusudhan Chikkature } 921a45c6cb8SMadhusudhan Chikkature host->data = NULL; 922a45c6cb8SMadhusudhan Chikkature } 923a45c6cb8SMadhusudhan Chikkature 924a45c6cb8SMadhusudhan Chikkature /* 925a45c6cb8SMadhusudhan Chikkature * Readable error output 926a45c6cb8SMadhusudhan Chikkature */ 927a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_MMC_DEBUG 928699b958bSAdrian Hunter static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 929a45c6cb8SMadhusudhan Chikkature { 930a45c6cb8SMadhusudhan Chikkature /* --- means reserved bit without definition at documentation */ 93170a3341aSDenis Karpov static const char *omap_hsmmc_status_bits[] = { 932699b958bSAdrian Hunter "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 933699b958bSAdrian Hunter "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 934699b958bSAdrian Hunter "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 935699b958bSAdrian Hunter "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 936a45c6cb8SMadhusudhan Chikkature }; 937a45c6cb8SMadhusudhan Chikkature char res[256]; 938a45c6cb8SMadhusudhan Chikkature char *buf = res; 939a45c6cb8SMadhusudhan Chikkature int len, i; 940a45c6cb8SMadhusudhan Chikkature 941a45c6cb8SMadhusudhan Chikkature len = sprintf(buf, "MMC IRQ 0x%x :", status); 942a45c6cb8SMadhusudhan Chikkature buf += len; 943a45c6cb8SMadhusudhan Chikkature 94470a3341aSDenis Karpov for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 945a45c6cb8SMadhusudhan Chikkature if (status & (1 << i)) { 94670a3341aSDenis Karpov len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 947a45c6cb8SMadhusudhan Chikkature buf += len; 948a45c6cb8SMadhusudhan Chikkature } 949a45c6cb8SMadhusudhan Chikkature 9508986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 951a45c6cb8SMadhusudhan Chikkature } 952699b958bSAdrian Hunter #else 953699b958bSAdrian Hunter static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 954699b958bSAdrian Hunter u32 status) 955699b958bSAdrian Hunter { 956699b958bSAdrian Hunter } 957a45c6cb8SMadhusudhan Chikkature #endif /* CONFIG_MMC_DEBUG */ 958a45c6cb8SMadhusudhan Chikkature 9593ebf74b1SJean Pihet /* 9603ebf74b1SJean Pihet * MMC controller internal state machines reset 9613ebf74b1SJean Pihet * 9623ebf74b1SJean Pihet * Used to reset command or data internal state machines, using respectively 9633ebf74b1SJean Pihet * SRC or SRD bit of SYSCTL register 9643ebf74b1SJean Pihet * Can be called from interrupt context 9653ebf74b1SJean Pihet */ 96670a3341aSDenis Karpov static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 9673ebf74b1SJean Pihet unsigned long bit) 9683ebf74b1SJean Pihet { 9693ebf74b1SJean Pihet unsigned long i = 0; 9703ebf74b1SJean Pihet unsigned long limit = (loops_per_jiffy * 9713ebf74b1SJean Pihet msecs_to_jiffies(MMC_TIMEOUT_MS)); 9723ebf74b1SJean Pihet 9733ebf74b1SJean Pihet OMAP_HSMMC_WRITE(host->base, SYSCTL, 9743ebf74b1SJean Pihet OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 9753ebf74b1SJean Pihet 97607ad64b6SMadhusudhan Chikkature /* 97707ad64b6SMadhusudhan Chikkature * OMAP4 ES2 and greater has an updated reset logic. 97807ad64b6SMadhusudhan Chikkature * Monitor a 0->1 transition first 97907ad64b6SMadhusudhan Chikkature */ 98007ad64b6SMadhusudhan Chikkature if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) { 981b432b4b3Skishore kadiyala while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 98207ad64b6SMadhusudhan Chikkature && (i++ < limit)) 98307ad64b6SMadhusudhan Chikkature cpu_relax(); 98407ad64b6SMadhusudhan Chikkature } 98507ad64b6SMadhusudhan Chikkature i = 0; 98607ad64b6SMadhusudhan Chikkature 9873ebf74b1SJean Pihet while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 9883ebf74b1SJean Pihet (i++ < limit)) 9893ebf74b1SJean Pihet cpu_relax(); 9903ebf74b1SJean Pihet 9913ebf74b1SJean Pihet if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 9923ebf74b1SJean Pihet dev_err(mmc_dev(host->mmc), 9933ebf74b1SJean Pihet "Timeout waiting on controller reset in %s\n", 9943ebf74b1SJean Pihet __func__); 9953ebf74b1SJean Pihet } 996a45c6cb8SMadhusudhan Chikkature 99725e1897bSBalaji T K static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, 99825e1897bSBalaji T K int err, int end_cmd) 999ae4bf788SVenkatraman S { 100025e1897bSBalaji T K if (end_cmd) { 100194d4f272SBalaji T K omap_hsmmc_reset_controller_fsm(host, SRC); 100225e1897bSBalaji T K if (host->cmd) 1003ae4bf788SVenkatraman S host->cmd->error = err; 100425e1897bSBalaji T K } 1005ae4bf788SVenkatraman S 1006ae4bf788SVenkatraman S if (host->data) { 1007ae4bf788SVenkatraman S omap_hsmmc_reset_controller_fsm(host, SRD); 1008ae4bf788SVenkatraman S omap_hsmmc_dma_cleanup(host, err); 1009dc7745bdSBalaji T K } else if (host->mrq && host->mrq->cmd) 1010dc7745bdSBalaji T K host->mrq->cmd->error = err; 1011ae4bf788SVenkatraman S } 1012ae4bf788SVenkatraman S 1013b417577dSAdrian Hunter static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1014a45c6cb8SMadhusudhan Chikkature { 1015a45c6cb8SMadhusudhan Chikkature struct mmc_data *data; 1016b417577dSAdrian Hunter int end_cmd = 0, end_trans = 0; 1017a45c6cb8SMadhusudhan Chikkature 1018a45c6cb8SMadhusudhan Chikkature data = host->data; 10198986d31bSVenkatraman S dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1020a45c6cb8SMadhusudhan Chikkature 1021a7e96879SVenkatraman S if (status & ERR_EN) { 1022699b958bSAdrian Hunter omap_hsmmc_dbg_report_irq(host, status); 10234a694dc9SAdrian Hunter 1024a7e96879SVenkatraman S if (status & (CTO_EN | CCRC_EN)) 1025a45c6cb8SMadhusudhan Chikkature end_cmd = 1; 1026a7e96879SVenkatraman S if (status & (CTO_EN | DTO_EN)) 102725e1897bSBalaji T K hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); 1028a7e96879SVenkatraman S else if (status & (CCRC_EN | DCRC_EN)) 102925e1897bSBalaji T K hsmmc_command_incomplete(host, -EILSEQ, end_cmd); 103025e1897bSBalaji T K 1031ae4bf788SVenkatraman S if (host->data || host->response_busy) { 103225e1897bSBalaji T K end_trans = !end_cmd; 1033ae4bf788SVenkatraman S host->response_busy = 0; 1034a45c6cb8SMadhusudhan Chikkature } 1035a45c6cb8SMadhusudhan Chikkature } 1036a45c6cb8SMadhusudhan Chikkature 10377472bab2SFrancesco Lavra OMAP_HSMMC_WRITE(host->base, STAT, status); 1038a7e96879SVenkatraman S if (end_cmd || ((status & CC_EN) && host->cmd)) 103970a3341aSDenis Karpov omap_hsmmc_cmd_done(host, host->cmd); 1040a7e96879SVenkatraman S if ((end_trans || (status & TC_EN)) && host->mrq) 104170a3341aSDenis Karpov omap_hsmmc_xfer_done(host, data); 1042b417577dSAdrian Hunter } 1043a45c6cb8SMadhusudhan Chikkature 1044b417577dSAdrian Hunter /* 1045b417577dSAdrian Hunter * MMC controller IRQ handler 1046b417577dSAdrian Hunter */ 1047b417577dSAdrian Hunter static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1048b417577dSAdrian Hunter { 1049b417577dSAdrian Hunter struct omap_hsmmc_host *host = dev_id; 1050b417577dSAdrian Hunter int status; 1051b417577dSAdrian Hunter 1052b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 10531f6b9fa4SVenkatraman S while (status & INT_EN_MASK && host->req_in_progress) { 1054b417577dSAdrian Hunter omap_hsmmc_do_irq(host, status); 10551f6b9fa4SVenkatraman S 1056b417577dSAdrian Hunter /* Flush posted write */ 1057b417577dSAdrian Hunter status = OMAP_HSMMC_READ(host->base, STAT); 10581f6b9fa4SVenkatraman S } 10594dffd7a2SAdrian Hunter 1060a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1061a45c6cb8SMadhusudhan Chikkature } 1062a45c6cb8SMadhusudhan Chikkature 106370a3341aSDenis Karpov static void set_sd_bus_power(struct omap_hsmmc_host *host) 1064e13bb300SAdrian Hunter { 1065e13bb300SAdrian Hunter unsigned long i; 1066e13bb300SAdrian Hunter 1067e13bb300SAdrian Hunter OMAP_HSMMC_WRITE(host->base, HCTL, 1068e13bb300SAdrian Hunter OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1069e13bb300SAdrian Hunter for (i = 0; i < loops_per_jiffy; i++) { 1070e13bb300SAdrian Hunter if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1071e13bb300SAdrian Hunter break; 1072e13bb300SAdrian Hunter cpu_relax(); 1073e13bb300SAdrian Hunter } 1074e13bb300SAdrian Hunter } 1075e13bb300SAdrian Hunter 1076a45c6cb8SMadhusudhan Chikkature /* 1077eb250826SDavid Brownell * Switch MMC interface voltage ... only relevant for MMC1. 1078eb250826SDavid Brownell * 1079eb250826SDavid Brownell * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1080eb250826SDavid Brownell * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1081eb250826SDavid Brownell * Some chips, like eMMC ones, use internal transceivers. 1082a45c6cb8SMadhusudhan Chikkature */ 108370a3341aSDenis Karpov static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1084a45c6cb8SMadhusudhan Chikkature { 1085a45c6cb8SMadhusudhan Chikkature u32 reg_val = 0; 1086a45c6cb8SMadhusudhan Chikkature int ret; 1087a45c6cb8SMadhusudhan Chikkature 1088a45c6cb8SMadhusudhan Chikkature /* Disable the clocks */ 1089fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 1090cd03d9a8SRajendra Nayak if (host->dbclk) 109194c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 1092a45c6cb8SMadhusudhan Chikkature 1093a45c6cb8SMadhusudhan Chikkature /* Turn the power off */ 1094a45c6cb8SMadhusudhan Chikkature ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 1095a45c6cb8SMadhusudhan Chikkature 1096a45c6cb8SMadhusudhan Chikkature /* Turn the power ON with given VDD 1.8 or 3.0v */ 10972bec0893SAdrian Hunter if (!ret) 10982bec0893SAdrian Hunter ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, 10992bec0893SAdrian Hunter vdd); 1100fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1101cd03d9a8SRajendra Nayak if (host->dbclk) 110294c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 11032bec0893SAdrian Hunter 1104a45c6cb8SMadhusudhan Chikkature if (ret != 0) 1105a45c6cb8SMadhusudhan Chikkature goto err; 1106a45c6cb8SMadhusudhan Chikkature 1107a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, 1108a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1109a45c6cb8SMadhusudhan Chikkature reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1110eb250826SDavid Brownell 1111a45c6cb8SMadhusudhan Chikkature /* 1112a45c6cb8SMadhusudhan Chikkature * If a MMC dual voltage card is detected, the set_ios fn calls 1113a45c6cb8SMadhusudhan Chikkature * this fn with VDD bit set for 1.8V. Upon card removal from the 111470a3341aSDenis Karpov * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1115a45c6cb8SMadhusudhan Chikkature * 1116eb250826SDavid Brownell * Cope with a bit of slop in the range ... per data sheets: 1117eb250826SDavid Brownell * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1118eb250826SDavid Brownell * but recommended values are 1.71V to 1.89V 1119eb250826SDavid Brownell * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1120eb250826SDavid Brownell * but recommended values are 2.7V to 3.3V 1121eb250826SDavid Brownell * 1122eb250826SDavid Brownell * Board setup code shouldn't permit anything very out-of-range. 1123eb250826SDavid Brownell * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1124eb250826SDavid Brownell * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1125a45c6cb8SMadhusudhan Chikkature */ 1126eb250826SDavid Brownell if ((1 << vdd) <= MMC_VDD_23_24) 1127a45c6cb8SMadhusudhan Chikkature reg_val |= SDVS18; 1128eb250826SDavid Brownell else 1129eb250826SDavid Brownell reg_val |= SDVS30; 1130a45c6cb8SMadhusudhan Chikkature 1131a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1132e13bb300SAdrian Hunter set_sd_bus_power(host); 1133a45c6cb8SMadhusudhan Chikkature 1134a45c6cb8SMadhusudhan Chikkature return 0; 1135a45c6cb8SMadhusudhan Chikkature err: 1136b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1137a45c6cb8SMadhusudhan Chikkature return ret; 1138a45c6cb8SMadhusudhan Chikkature } 1139a45c6cb8SMadhusudhan Chikkature 1140b62f6228SAdrian Hunter /* Protect the card while the cover is open */ 1141b62f6228SAdrian Hunter static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1142b62f6228SAdrian Hunter { 1143b62f6228SAdrian Hunter if (!mmc_slot(host).get_cover_state) 1144b62f6228SAdrian Hunter return; 1145b62f6228SAdrian Hunter 1146b62f6228SAdrian Hunter host->reqs_blocked = 0; 1147b62f6228SAdrian Hunter if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) { 1148b62f6228SAdrian Hunter if (host->protect_card) { 11492cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is closed, " 1150b62f6228SAdrian Hunter "card is now accessible\n", 1151b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1152b62f6228SAdrian Hunter host->protect_card = 0; 1153b62f6228SAdrian Hunter } 1154b62f6228SAdrian Hunter } else { 1155b62f6228SAdrian Hunter if (!host->protect_card) { 11562cecdf00SRajendra Nayak dev_info(host->dev, "%s: cover is open, " 1157b62f6228SAdrian Hunter "card is now inaccessible\n", 1158b62f6228SAdrian Hunter mmc_hostname(host->mmc)); 1159b62f6228SAdrian Hunter host->protect_card = 1; 1160b62f6228SAdrian Hunter } 1161b62f6228SAdrian Hunter } 1162b62f6228SAdrian Hunter } 1163b62f6228SAdrian Hunter 1164a45c6cb8SMadhusudhan Chikkature /* 11657efab4f3SNeilBrown * irq handler to notify the core about card insertion/removal 1166a45c6cb8SMadhusudhan Chikkature */ 11677efab4f3SNeilBrown static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id) 1168a45c6cb8SMadhusudhan Chikkature { 11697efab4f3SNeilBrown struct omap_hsmmc_host *host = dev_id; 1170249d0fa9SDavid Brownell struct omap_mmc_slot_data *slot = &mmc_slot(host); 1171a6b2240dSAdrian Hunter int carddetect; 1172249d0fa9SDavid Brownell 1173a6b2240dSAdrian Hunter if (host->suspended) 11747efab4f3SNeilBrown return IRQ_HANDLED; 1175a45c6cb8SMadhusudhan Chikkature 1176a45c6cb8SMadhusudhan Chikkature sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1177a6b2240dSAdrian Hunter 1178191d1f1dSDenis Karpov if (slot->card_detect) 1179db0fefc5SAdrian Hunter carddetect = slot->card_detect(host->dev, host->slot_id); 1180b62f6228SAdrian Hunter else { 1181b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 1182a6b2240dSAdrian Hunter carddetect = -ENOSYS; 1183b62f6228SAdrian Hunter } 1184a6b2240dSAdrian Hunter 1185cdeebaddSMadhusudhan Chikkature if (carddetect) 1186a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1187cdeebaddSMadhusudhan Chikkature else 1188a45c6cb8SMadhusudhan Chikkature mmc_detect_change(host->mmc, (HZ * 50) / 1000); 1189a45c6cb8SMadhusudhan Chikkature return IRQ_HANDLED; 1190a45c6cb8SMadhusudhan Chikkature } 1191a45c6cb8SMadhusudhan Chikkature 1192c5c98927SRussell King static void omap_hsmmc_dma_callback(void *param) 11930ccd76d4SJuha Yrjola { 1194c5c98927SRussell King struct omap_hsmmc_host *host = param; 1195c5c98927SRussell King struct dma_chan *chan; 1196770d7432SAdrian Hunter struct mmc_data *data; 1197c5c98927SRussell King int req_in_progress; 1198a45c6cb8SMadhusudhan Chikkature 1199c5c98927SRussell King spin_lock_irq(&host->irq_lock); 1200b417577dSAdrian Hunter if (host->dma_ch < 0) { 1201c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1202a45c6cb8SMadhusudhan Chikkature return; 1203b417577dSAdrian Hunter } 1204a45c6cb8SMadhusudhan Chikkature 1205770d7432SAdrian Hunter data = host->mrq->data; 1206c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 12079782aff8SPer Forlin if (!data->host_cookie) 1208c5c98927SRussell King dma_unmap_sg(chan->device->dev, 1209c5c98927SRussell King data->sg, data->sg_len, 1210b417577dSAdrian Hunter omap_hsmmc_get_dma_dir(host, data)); 1211b417577dSAdrian Hunter 1212b417577dSAdrian Hunter req_in_progress = host->req_in_progress; 1213a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1214c5c98927SRussell King spin_unlock_irq(&host->irq_lock); 1215b417577dSAdrian Hunter 1216b417577dSAdrian Hunter /* If DMA has finished after TC, complete the request */ 1217b417577dSAdrian Hunter if (!req_in_progress) { 1218b417577dSAdrian Hunter struct mmc_request *mrq = host->mrq; 1219b417577dSAdrian Hunter 1220b417577dSAdrian Hunter host->mrq = NULL; 1221b417577dSAdrian Hunter mmc_request_done(host->mmc, mrq); 1222b417577dSAdrian Hunter } 1223a45c6cb8SMadhusudhan Chikkature } 1224a45c6cb8SMadhusudhan Chikkature 12259782aff8SPer Forlin static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 12269782aff8SPer Forlin struct mmc_data *data, 1227c5c98927SRussell King struct omap_hsmmc_next *next, 122826b88520SRussell King struct dma_chan *chan) 12299782aff8SPer Forlin { 12309782aff8SPer Forlin int dma_len; 12319782aff8SPer Forlin 12329782aff8SPer Forlin if (!next && data->host_cookie && 12339782aff8SPer Forlin data->host_cookie != host->next_data.cookie) { 12342cecdf00SRajendra Nayak dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 12359782aff8SPer Forlin " host->next_data.cookie %d\n", 12369782aff8SPer Forlin __func__, data->host_cookie, host->next_data.cookie); 12379782aff8SPer Forlin data->host_cookie = 0; 12389782aff8SPer Forlin } 12399782aff8SPer Forlin 12409782aff8SPer Forlin /* Check if next job is already prepared */ 12419782aff8SPer Forlin if (next || 12429782aff8SPer Forlin (!next && data->host_cookie != host->next_data.cookie)) { 124326b88520SRussell King dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 12449782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 12459782aff8SPer Forlin 12469782aff8SPer Forlin } else { 12479782aff8SPer Forlin dma_len = host->next_data.dma_len; 12489782aff8SPer Forlin host->next_data.dma_len = 0; 12499782aff8SPer Forlin } 12509782aff8SPer Forlin 12519782aff8SPer Forlin 12529782aff8SPer Forlin if (dma_len == 0) 12539782aff8SPer Forlin return -EINVAL; 12549782aff8SPer Forlin 12559782aff8SPer Forlin if (next) { 12569782aff8SPer Forlin next->dma_len = dma_len; 12579782aff8SPer Forlin data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 12589782aff8SPer Forlin } else 12599782aff8SPer Forlin host->dma_len = dma_len; 12609782aff8SPer Forlin 12619782aff8SPer Forlin return 0; 12629782aff8SPer Forlin } 12639782aff8SPer Forlin 1264a45c6cb8SMadhusudhan Chikkature /* 1265a45c6cb8SMadhusudhan Chikkature * Routine to configure and start DMA for the MMC card 1266a45c6cb8SMadhusudhan Chikkature */ 126770a3341aSDenis Karpov static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host, 126870a3341aSDenis Karpov struct mmc_request *req) 1269a45c6cb8SMadhusudhan Chikkature { 127026b88520SRussell King struct dma_slave_config cfg; 127126b88520SRussell King struct dma_async_tx_descriptor *tx; 127226b88520SRussell King int ret = 0, i; 1273a45c6cb8SMadhusudhan Chikkature struct mmc_data *data = req->data; 1274c5c98927SRussell King struct dma_chan *chan; 1275a45c6cb8SMadhusudhan Chikkature 12760ccd76d4SJuha Yrjola /* Sanity check: all the SG entries must be aligned by block size. */ 1277a3f406f8SJarkko Lavinen for (i = 0; i < data->sg_len; i++) { 12780ccd76d4SJuha Yrjola struct scatterlist *sgl; 12790ccd76d4SJuha Yrjola 12800ccd76d4SJuha Yrjola sgl = data->sg + i; 12810ccd76d4SJuha Yrjola if (sgl->length % data->blksz) 12820ccd76d4SJuha Yrjola return -EINVAL; 12830ccd76d4SJuha Yrjola } 12840ccd76d4SJuha Yrjola if ((data->blksz % 4) != 0) 12850ccd76d4SJuha Yrjola /* REVISIT: The MMC buffer increments only when MSB is written. 12860ccd76d4SJuha Yrjola * Return error for blksz which is non multiple of four. 12870ccd76d4SJuha Yrjola */ 12880ccd76d4SJuha Yrjola return -EINVAL; 12890ccd76d4SJuha Yrjola 1290b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1291a45c6cb8SMadhusudhan Chikkature 1292c5c98927SRussell King chan = omap_hsmmc_get_dma_chan(host, data); 1293c5c98927SRussell King 1294c5c98927SRussell King cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA; 1295c5c98927SRussell King cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA; 1296c5c98927SRussell King cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1297c5c98927SRussell King cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1298c5c98927SRussell King cfg.src_maxburst = data->blksz / 4; 1299c5c98927SRussell King cfg.dst_maxburst = data->blksz / 4; 1300c5c98927SRussell King 1301c5c98927SRussell King ret = dmaengine_slave_config(chan, &cfg); 13029782aff8SPer Forlin if (ret) 13039782aff8SPer Forlin return ret; 1304a45c6cb8SMadhusudhan Chikkature 130526b88520SRussell King ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1306c5c98927SRussell King if (ret) 1307c5c98927SRussell King return ret; 1308a45c6cb8SMadhusudhan Chikkature 1309c5c98927SRussell King tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1310c5c98927SRussell King data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1311c5c98927SRussell King DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1312c5c98927SRussell King if (!tx) { 1313c5c98927SRussell King dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1314c5c98927SRussell King /* FIXME: cleanup */ 1315c5c98927SRussell King return -1; 1316c5c98927SRussell King } 1317c5c98927SRussell King 1318c5c98927SRussell King tx->callback = omap_hsmmc_dma_callback; 1319c5c98927SRussell King tx->callback_param = host; 1320c5c98927SRussell King 1321c5c98927SRussell King /* Does not fail */ 1322c5c98927SRussell King dmaengine_submit(tx); 1323c5c98927SRussell King 132426b88520SRussell King host->dma_ch = 1; 1325c5c98927SRussell King 1326c5c98927SRussell King dma_async_issue_pending(chan); 1327a45c6cb8SMadhusudhan Chikkature 1328a45c6cb8SMadhusudhan Chikkature return 0; 1329a45c6cb8SMadhusudhan Chikkature } 1330a45c6cb8SMadhusudhan Chikkature 133170a3341aSDenis Karpov static void set_data_timeout(struct omap_hsmmc_host *host, 1332e2bf08d6SAdrian Hunter unsigned int timeout_ns, 1333e2bf08d6SAdrian Hunter unsigned int timeout_clks) 1334a45c6cb8SMadhusudhan Chikkature { 1335a45c6cb8SMadhusudhan Chikkature unsigned int timeout, cycle_ns; 1336a45c6cb8SMadhusudhan Chikkature uint32_t reg, clkd, dto = 0; 1337a45c6cb8SMadhusudhan Chikkature 1338a45c6cb8SMadhusudhan Chikkature reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1339a45c6cb8SMadhusudhan Chikkature clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1340a45c6cb8SMadhusudhan Chikkature if (clkd == 0) 1341a45c6cb8SMadhusudhan Chikkature clkd = 1; 1342a45c6cb8SMadhusudhan Chikkature 1343a45c6cb8SMadhusudhan Chikkature cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); 1344e2bf08d6SAdrian Hunter timeout = timeout_ns / cycle_ns; 1345e2bf08d6SAdrian Hunter timeout += timeout_clks; 1346a45c6cb8SMadhusudhan Chikkature if (timeout) { 1347a45c6cb8SMadhusudhan Chikkature while ((timeout & 0x80000000) == 0) { 1348a45c6cb8SMadhusudhan Chikkature dto += 1; 1349a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1350a45c6cb8SMadhusudhan Chikkature } 1351a45c6cb8SMadhusudhan Chikkature dto = 31 - dto; 1352a45c6cb8SMadhusudhan Chikkature timeout <<= 1; 1353a45c6cb8SMadhusudhan Chikkature if (timeout && dto) 1354a45c6cb8SMadhusudhan Chikkature dto += 1; 1355a45c6cb8SMadhusudhan Chikkature if (dto >= 13) 1356a45c6cb8SMadhusudhan Chikkature dto -= 13; 1357a45c6cb8SMadhusudhan Chikkature else 1358a45c6cb8SMadhusudhan Chikkature dto = 0; 1359a45c6cb8SMadhusudhan Chikkature if (dto > 14) 1360a45c6cb8SMadhusudhan Chikkature dto = 14; 1361a45c6cb8SMadhusudhan Chikkature } 1362a45c6cb8SMadhusudhan Chikkature 1363a45c6cb8SMadhusudhan Chikkature reg &= ~DTO_MASK; 1364a45c6cb8SMadhusudhan Chikkature reg |= dto << DTO_SHIFT; 1365a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1366a45c6cb8SMadhusudhan Chikkature } 1367a45c6cb8SMadhusudhan Chikkature 1368a45c6cb8SMadhusudhan Chikkature /* 1369a45c6cb8SMadhusudhan Chikkature * Configure block length for MMC/SD cards and initiate the transfer. 1370a45c6cb8SMadhusudhan Chikkature */ 1371a45c6cb8SMadhusudhan Chikkature static int 137270a3341aSDenis Karpov omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1373a45c6cb8SMadhusudhan Chikkature { 1374a45c6cb8SMadhusudhan Chikkature int ret; 1375a45c6cb8SMadhusudhan Chikkature host->data = req->data; 1376a45c6cb8SMadhusudhan Chikkature 1377a45c6cb8SMadhusudhan Chikkature if (req->data == NULL) { 1378a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, 0); 1379e2bf08d6SAdrian Hunter /* 1380e2bf08d6SAdrian Hunter * Set an arbitrary 100ms data timeout for commands with 1381e2bf08d6SAdrian Hunter * busy signal. 1382e2bf08d6SAdrian Hunter */ 1383e2bf08d6SAdrian Hunter if (req->cmd->flags & MMC_RSP_BUSY) 1384e2bf08d6SAdrian Hunter set_data_timeout(host, 100000000U, 0); 1385a45c6cb8SMadhusudhan Chikkature return 0; 1386a45c6cb8SMadhusudhan Chikkature } 1387a45c6cb8SMadhusudhan Chikkature 1388a45c6cb8SMadhusudhan Chikkature OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 1389a45c6cb8SMadhusudhan Chikkature | (req->data->blocks << 16)); 1390e2bf08d6SAdrian Hunter set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks); 1391a45c6cb8SMadhusudhan Chikkature 1392a45c6cb8SMadhusudhan Chikkature if (host->use_dma) { 139370a3341aSDenis Karpov ret = omap_hsmmc_start_dma_transfer(host, req); 1394a45c6cb8SMadhusudhan Chikkature if (ret != 0) { 1395b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); 1396a45c6cb8SMadhusudhan Chikkature return ret; 1397a45c6cb8SMadhusudhan Chikkature } 1398a45c6cb8SMadhusudhan Chikkature } 1399a45c6cb8SMadhusudhan Chikkature return 0; 1400a45c6cb8SMadhusudhan Chikkature } 1401a45c6cb8SMadhusudhan Chikkature 14029782aff8SPer Forlin static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 14039782aff8SPer Forlin int err) 14049782aff8SPer Forlin { 14059782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 14069782aff8SPer Forlin struct mmc_data *data = mrq->data; 14079782aff8SPer Forlin 140826b88520SRussell King if (host->use_dma && data->host_cookie) { 1409c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1410c5c98927SRussell King 141126b88520SRussell King dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 14129782aff8SPer Forlin omap_hsmmc_get_dma_dir(host, data)); 14139782aff8SPer Forlin data->host_cookie = 0; 14149782aff8SPer Forlin } 14159782aff8SPer Forlin } 14169782aff8SPer Forlin 14179782aff8SPer Forlin static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 14189782aff8SPer Forlin bool is_first_req) 14199782aff8SPer Forlin { 14209782aff8SPer Forlin struct omap_hsmmc_host *host = mmc_priv(mmc); 14219782aff8SPer Forlin 14229782aff8SPer Forlin if (mrq->data->host_cookie) { 14239782aff8SPer Forlin mrq->data->host_cookie = 0; 14249782aff8SPer Forlin return ; 14259782aff8SPer Forlin } 14269782aff8SPer Forlin 1427c5c98927SRussell King if (host->use_dma) { 1428c5c98927SRussell King struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1429c5c98927SRussell King 14309782aff8SPer Forlin if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 143126b88520SRussell King &host->next_data, c)) 14329782aff8SPer Forlin mrq->data->host_cookie = 0; 14339782aff8SPer Forlin } 1434c5c98927SRussell King } 14359782aff8SPer Forlin 1436a45c6cb8SMadhusudhan Chikkature /* 1437a45c6cb8SMadhusudhan Chikkature * Request function. for read/write operation 1438a45c6cb8SMadhusudhan Chikkature */ 143970a3341aSDenis Karpov static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1440a45c6cb8SMadhusudhan Chikkature { 144170a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1442a3f406f8SJarkko Lavinen int err; 1443a45c6cb8SMadhusudhan Chikkature 1444b417577dSAdrian Hunter BUG_ON(host->req_in_progress); 1445b417577dSAdrian Hunter BUG_ON(host->dma_ch != -1); 1446b62f6228SAdrian Hunter if (host->protect_card) { 1447b62f6228SAdrian Hunter if (host->reqs_blocked < 3) { 1448b62f6228SAdrian Hunter /* 1449b62f6228SAdrian Hunter * Ensure the controller is left in a consistent 1450b62f6228SAdrian Hunter * state by resetting the command and data state 1451b62f6228SAdrian Hunter * machines. 1452b62f6228SAdrian Hunter */ 1453b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRD); 1454b62f6228SAdrian Hunter omap_hsmmc_reset_controller_fsm(host, SRC); 1455b62f6228SAdrian Hunter host->reqs_blocked += 1; 1456b62f6228SAdrian Hunter } 1457b62f6228SAdrian Hunter req->cmd->error = -EBADF; 1458b62f6228SAdrian Hunter if (req->data) 1459b62f6228SAdrian Hunter req->data->error = -EBADF; 1460b417577dSAdrian Hunter req->cmd->retries = 0; 1461b62f6228SAdrian Hunter mmc_request_done(mmc, req); 1462b62f6228SAdrian Hunter return; 1463b62f6228SAdrian Hunter } else if (host->reqs_blocked) 1464b62f6228SAdrian Hunter host->reqs_blocked = 0; 1465a45c6cb8SMadhusudhan Chikkature WARN_ON(host->mrq != NULL); 1466a45c6cb8SMadhusudhan Chikkature host->mrq = req; 146770a3341aSDenis Karpov err = omap_hsmmc_prepare_data(host, req); 1468a3f406f8SJarkko Lavinen if (err) { 1469a3f406f8SJarkko Lavinen req->cmd->error = err; 1470a3f406f8SJarkko Lavinen if (req->data) 1471a3f406f8SJarkko Lavinen req->data->error = err; 1472a3f406f8SJarkko Lavinen host->mrq = NULL; 1473a3f406f8SJarkko Lavinen mmc_request_done(mmc, req); 1474a3f406f8SJarkko Lavinen return; 1475a3f406f8SJarkko Lavinen } 1476a3f406f8SJarkko Lavinen 147770a3341aSDenis Karpov omap_hsmmc_start_command(host, req->cmd, req->data); 1478a45c6cb8SMadhusudhan Chikkature } 1479a45c6cb8SMadhusudhan Chikkature 1480a45c6cb8SMadhusudhan Chikkature /* Routine to configure clock values. Exposed API to core */ 148170a3341aSDenis Karpov static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1482a45c6cb8SMadhusudhan Chikkature { 148370a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1484a3621465SAdrian Hunter int do_send_init_stream = 0; 1485a45c6cb8SMadhusudhan Chikkature 1486fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 14875e2ea617SAdrian Hunter 1488a3621465SAdrian Hunter if (ios->power_mode != host->power_mode) { 1489a45c6cb8SMadhusudhan Chikkature switch (ios->power_mode) { 1490a45c6cb8SMadhusudhan Chikkature case MMC_POWER_OFF: 1491a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1492a3621465SAdrian Hunter 0, 0); 1493a45c6cb8SMadhusudhan Chikkature break; 1494a45c6cb8SMadhusudhan Chikkature case MMC_POWER_UP: 1495a3621465SAdrian Hunter mmc_slot(host).set_power(host->dev, host->slot_id, 1496a3621465SAdrian Hunter 1, ios->vdd); 1497a45c6cb8SMadhusudhan Chikkature break; 1498a3621465SAdrian Hunter case MMC_POWER_ON: 1499a3621465SAdrian Hunter do_send_init_stream = 1; 1500a3621465SAdrian Hunter break; 1501a3621465SAdrian Hunter } 1502a3621465SAdrian Hunter host->power_mode = ios->power_mode; 1503a45c6cb8SMadhusudhan Chikkature } 1504a45c6cb8SMadhusudhan Chikkature 1505dd498effSDenis Karpov /* FIXME: set registers based only on changes to ios */ 1506dd498effSDenis Karpov 15073796fb8aSAndy Shevchenko omap_hsmmc_set_bus_width(host); 1508a45c6cb8SMadhusudhan Chikkature 15094621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1510eb250826SDavid Brownell /* Only MMC1 can interface at 3V without some flavor 1511eb250826SDavid Brownell * of external transceiver; but they all handle 1.8V. 1512eb250826SDavid Brownell */ 1513a45c6cb8SMadhusudhan Chikkature if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 15141f84b71bSRajendra Nayak (ios->vdd == DUAL_VOLT_OCR_BIT) && 15151f84b71bSRajendra Nayak /* 15161f84b71bSRajendra Nayak * With pbias cell programming missing, this 1517cf5ae40bSTony Lindgren * can't be allowed on MMC1 when booting with device 15181f84b71bSRajendra Nayak * tree. 15191f84b71bSRajendra Nayak */ 1520cf5ae40bSTony Lindgren !host->pbias_disable) { 1521a45c6cb8SMadhusudhan Chikkature /* 1522a45c6cb8SMadhusudhan Chikkature * The mmc_select_voltage fn of the core does 1523a45c6cb8SMadhusudhan Chikkature * not seem to set the power_mode to 1524a45c6cb8SMadhusudhan Chikkature * MMC_POWER_UP upon recalculating the voltage. 1525a45c6cb8SMadhusudhan Chikkature * vdd 1.8v. 1526a45c6cb8SMadhusudhan Chikkature */ 152770a3341aSDenis Karpov if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1528a45c6cb8SMadhusudhan Chikkature dev_dbg(mmc_dev(host->mmc), 1529a45c6cb8SMadhusudhan Chikkature "Switch operation failed\n"); 1530a45c6cb8SMadhusudhan Chikkature } 1531a45c6cb8SMadhusudhan Chikkature } 1532a45c6cb8SMadhusudhan Chikkature 15335934df2fSAndy Shevchenko omap_hsmmc_set_clock(host); 1534a45c6cb8SMadhusudhan Chikkature 1535a3621465SAdrian Hunter if (do_send_init_stream) 1536a45c6cb8SMadhusudhan Chikkature send_init_stream(host); 1537a45c6cb8SMadhusudhan Chikkature 15383796fb8aSAndy Shevchenko omap_hsmmc_set_bus_mode(host); 15395e2ea617SAdrian Hunter 1540fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1541a45c6cb8SMadhusudhan Chikkature } 1542a45c6cb8SMadhusudhan Chikkature 1543a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1544a45c6cb8SMadhusudhan Chikkature { 154570a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1546a45c6cb8SMadhusudhan Chikkature 1547191d1f1dSDenis Karpov if (!mmc_slot(host).card_detect) 1548a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1549db0fefc5SAdrian Hunter return mmc_slot(host).card_detect(host->dev, host->slot_id); 1550a45c6cb8SMadhusudhan Chikkature } 1551a45c6cb8SMadhusudhan Chikkature 1552a45c6cb8SMadhusudhan Chikkature static int omap_hsmmc_get_ro(struct mmc_host *mmc) 1553a45c6cb8SMadhusudhan Chikkature { 155470a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1555a45c6cb8SMadhusudhan Chikkature 1556191d1f1dSDenis Karpov if (!mmc_slot(host).get_ro) 1557a45c6cb8SMadhusudhan Chikkature return -ENOSYS; 1558191d1f1dSDenis Karpov return mmc_slot(host).get_ro(host->dev, 0); 1559a45c6cb8SMadhusudhan Chikkature } 1560a45c6cb8SMadhusudhan Chikkature 15614816858cSGrazvydas Ignotas static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 15624816858cSGrazvydas Ignotas { 15634816858cSGrazvydas Ignotas struct omap_hsmmc_host *host = mmc_priv(mmc); 15644816858cSGrazvydas Ignotas 15654816858cSGrazvydas Ignotas if (mmc_slot(host).init_card) 15664816858cSGrazvydas Ignotas mmc_slot(host).init_card(card); 15674816858cSGrazvydas Ignotas } 15684816858cSGrazvydas Ignotas 156970a3341aSDenis Karpov static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 15701b331e69SKim Kyuwon { 15711b331e69SKim Kyuwon u32 hctl, capa, value; 15721b331e69SKim Kyuwon 15731b331e69SKim Kyuwon /* Only MMC1 supports 3.0V */ 15744621d5f8SKishore Kadiyala if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 15751b331e69SKim Kyuwon hctl = SDVS30; 15761b331e69SKim Kyuwon capa = VS30 | VS18; 15771b331e69SKim Kyuwon } else { 15781b331e69SKim Kyuwon hctl = SDVS18; 15791b331e69SKim Kyuwon capa = VS18; 15801b331e69SKim Kyuwon } 15811b331e69SKim Kyuwon 15821b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 15831b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 15841b331e69SKim Kyuwon 15851b331e69SKim Kyuwon value = OMAP_HSMMC_READ(host->base, CAPA); 15861b331e69SKim Kyuwon OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 15871b331e69SKim Kyuwon 15881b331e69SKim Kyuwon /* Set SD bus power bit */ 1589e13bb300SAdrian Hunter set_sd_bus_power(host); 15901b331e69SKim Kyuwon } 15911b331e69SKim Kyuwon 159270a3341aSDenis Karpov static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) 1593dd498effSDenis Karpov { 159470a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1595dd498effSDenis Karpov 1596fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1597fa4aa2d4SBalaji T K 1598dd498effSDenis Karpov return 0; 1599dd498effSDenis Karpov } 1600dd498effSDenis Karpov 1601907d2e7cSAdrian Hunter static int omap_hsmmc_disable_fclk(struct mmc_host *mmc) 1602dd498effSDenis Karpov { 160370a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 1604dd498effSDenis Karpov 1605fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1606fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1607fa4aa2d4SBalaji T K 1608dd498effSDenis Karpov return 0; 1609dd498effSDenis Karpov } 1610dd498effSDenis Karpov 161170a3341aSDenis Karpov static const struct mmc_host_ops omap_hsmmc_ops = { 161270a3341aSDenis Karpov .enable = omap_hsmmc_enable_fclk, 161370a3341aSDenis Karpov .disable = omap_hsmmc_disable_fclk, 16149782aff8SPer Forlin .post_req = omap_hsmmc_post_req, 16159782aff8SPer Forlin .pre_req = omap_hsmmc_pre_req, 161670a3341aSDenis Karpov .request = omap_hsmmc_request, 161770a3341aSDenis Karpov .set_ios = omap_hsmmc_set_ios, 1618dd498effSDenis Karpov .get_cd = omap_hsmmc_get_cd, 1619dd498effSDenis Karpov .get_ro = omap_hsmmc_get_ro, 16204816858cSGrazvydas Ignotas .init_card = omap_hsmmc_init_card, 1621dd498effSDenis Karpov /* NYET -- enable_sdio_irq */ 1622dd498effSDenis Karpov }; 1623dd498effSDenis Karpov 1624d900f712SDenis Karpov #ifdef CONFIG_DEBUG_FS 1625d900f712SDenis Karpov 162670a3341aSDenis Karpov static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1627d900f712SDenis Karpov { 1628d900f712SDenis Karpov struct mmc_host *mmc = s->private; 162970a3341aSDenis Karpov struct omap_hsmmc_host *host = mmc_priv(mmc); 163011dd62a7SDenis Karpov 16310a82e06eSTony Lindgren seq_printf(s, "mmc%d:\n ctx_loss:\t%d\n\nregs:\n", 16320a82e06eSTony Lindgren mmc->index, host->context_loss); 16335e2ea617SAdrian Hunter 16347a8c2cefSBalaji T K if (host->suspended) { 1635dd498effSDenis Karpov seq_printf(s, "host suspended, can't read registers\n"); 1636dd498effSDenis Karpov return 0; 1637dd498effSDenis Karpov } 1638dd498effSDenis Karpov 1639fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1640d900f712SDenis Karpov 1641d900f712SDenis Karpov seq_printf(s, "CON:\t\t0x%08x\n", 1642d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CON)); 1643d900f712SDenis Karpov seq_printf(s, "HCTL:\t\t0x%08x\n", 1644d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, HCTL)); 1645d900f712SDenis Karpov seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1646d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, SYSCTL)); 1647d900f712SDenis Karpov seq_printf(s, "IE:\t\t0x%08x\n", 1648d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, IE)); 1649d900f712SDenis Karpov seq_printf(s, "ISE:\t\t0x%08x\n", 1650d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, ISE)); 1651d900f712SDenis Karpov seq_printf(s, "CAPA:\t\t0x%08x\n", 1652d900f712SDenis Karpov OMAP_HSMMC_READ(host->base, CAPA)); 16535e2ea617SAdrian Hunter 1654fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 1655fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 1656dd498effSDenis Karpov 1657d900f712SDenis Karpov return 0; 1658d900f712SDenis Karpov } 1659d900f712SDenis Karpov 166070a3341aSDenis Karpov static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1661d900f712SDenis Karpov { 166270a3341aSDenis Karpov return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1663d900f712SDenis Karpov } 1664d900f712SDenis Karpov 1665d900f712SDenis Karpov static const struct file_operations mmc_regs_fops = { 166670a3341aSDenis Karpov .open = omap_hsmmc_regs_open, 1667d900f712SDenis Karpov .read = seq_read, 1668d900f712SDenis Karpov .llseek = seq_lseek, 1669d900f712SDenis Karpov .release = single_release, 1670d900f712SDenis Karpov }; 1671d900f712SDenis Karpov 167270a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1673d900f712SDenis Karpov { 1674d900f712SDenis Karpov if (mmc->debugfs_root) 1675d900f712SDenis Karpov debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1676d900f712SDenis Karpov mmc, &mmc_regs_fops); 1677d900f712SDenis Karpov } 1678d900f712SDenis Karpov 1679d900f712SDenis Karpov #else 1680d900f712SDenis Karpov 168170a3341aSDenis Karpov static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1682d900f712SDenis Karpov { 1683d900f712SDenis Karpov } 1684d900f712SDenis Karpov 1685d900f712SDenis Karpov #endif 1686d900f712SDenis Karpov 168746856a68SRajendra Nayak #ifdef CONFIG_OF 168846856a68SRajendra Nayak static u16 omap4_reg_offset = 0x100; 168946856a68SRajendra Nayak 169046856a68SRajendra Nayak static const struct of_device_id omap_mmc_of_match[] = { 169146856a68SRajendra Nayak { 169246856a68SRajendra Nayak .compatible = "ti,omap2-hsmmc", 169346856a68SRajendra Nayak }, 169446856a68SRajendra Nayak { 169546856a68SRajendra Nayak .compatible = "ti,omap3-hsmmc", 169646856a68SRajendra Nayak }, 169746856a68SRajendra Nayak { 169846856a68SRajendra Nayak .compatible = "ti,omap4-hsmmc", 169946856a68SRajendra Nayak .data = &omap4_reg_offset, 170046856a68SRajendra Nayak }, 170146856a68SRajendra Nayak {}, 1702b6d085f6SChris Ball }; 170346856a68SRajendra Nayak MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 170446856a68SRajendra Nayak 170546856a68SRajendra Nayak static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 170646856a68SRajendra Nayak { 170746856a68SRajendra Nayak struct omap_mmc_platform_data *pdata; 170846856a68SRajendra Nayak struct device_node *np = dev->of_node; 1709d8714e87SDaniel Mack u32 bus_width, max_freq; 1710dc642c28SJan Luebbe int cd_gpio, wp_gpio; 1711dc642c28SJan Luebbe 1712dc642c28SJan Luebbe cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); 1713dc642c28SJan Luebbe wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 1714dc642c28SJan Luebbe if (cd_gpio == -EPROBE_DEFER || wp_gpio == -EPROBE_DEFER) 1715dc642c28SJan Luebbe return ERR_PTR(-EPROBE_DEFER); 171646856a68SRajendra Nayak 171746856a68SRajendra Nayak pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 171846856a68SRajendra Nayak if (!pdata) 171946856a68SRajendra Nayak return NULL; /* out of memory */ 172046856a68SRajendra Nayak 172146856a68SRajendra Nayak if (of_find_property(np, "ti,dual-volt", NULL)) 172246856a68SRajendra Nayak pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 172346856a68SRajendra Nayak 172446856a68SRajendra Nayak /* This driver only supports 1 slot */ 172546856a68SRajendra Nayak pdata->nr_slots = 1; 1726dc642c28SJan Luebbe pdata->slots[0].switch_pin = cd_gpio; 1727dc642c28SJan Luebbe pdata->slots[0].gpio_wp = wp_gpio; 172846856a68SRajendra Nayak 172946856a68SRajendra Nayak if (of_find_property(np, "ti,non-removable", NULL)) { 173046856a68SRajendra Nayak pdata->slots[0].nonremovable = true; 173146856a68SRajendra Nayak pdata->slots[0].no_regulator_off_init = true; 173246856a68SRajendra Nayak } 17337f217794SArnd Bergmann of_property_read_u32(np, "bus-width", &bus_width); 173446856a68SRajendra Nayak if (bus_width == 4) 173546856a68SRajendra Nayak pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA; 173646856a68SRajendra Nayak else if (bus_width == 8) 173746856a68SRajendra Nayak pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA; 173846856a68SRajendra Nayak 173946856a68SRajendra Nayak if (of_find_property(np, "ti,needs-special-reset", NULL)) 174046856a68SRajendra Nayak pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET; 174146856a68SRajendra Nayak 1742d8714e87SDaniel Mack if (!of_property_read_u32(np, "max-frequency", &max_freq)) 1743d8714e87SDaniel Mack pdata->max_freq = max_freq; 1744d8714e87SDaniel Mack 1745cd587096SHebbar, Gururaja if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) 1746cd587096SHebbar, Gururaja pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT; 1747cd587096SHebbar, Gururaja 174846856a68SRajendra Nayak return pdata; 174946856a68SRajendra Nayak } 175046856a68SRajendra Nayak #else 175146856a68SRajendra Nayak static inline struct omap_mmc_platform_data 175246856a68SRajendra Nayak *of_get_hsmmc_pdata(struct device *dev) 175346856a68SRajendra Nayak { 175446856a68SRajendra Nayak return NULL; 175546856a68SRajendra Nayak } 175646856a68SRajendra Nayak #endif 175746856a68SRajendra Nayak 1758c3be1efdSBill Pemberton static int omap_hsmmc_probe(struct platform_device *pdev) 1759a45c6cb8SMadhusudhan Chikkature { 1760a45c6cb8SMadhusudhan Chikkature struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 1761a45c6cb8SMadhusudhan Chikkature struct mmc_host *mmc; 176270a3341aSDenis Karpov struct omap_hsmmc_host *host = NULL; 1763a45c6cb8SMadhusudhan Chikkature struct resource *res; 1764db0fefc5SAdrian Hunter int ret, irq; 176546856a68SRajendra Nayak const struct of_device_id *match; 176626b88520SRussell King dma_cap_mask_t mask; 176726b88520SRussell King unsigned tx_req, rx_req; 176846b76035SDaniel Mack struct pinctrl *pinctrl; 176946856a68SRajendra Nayak 177046856a68SRajendra Nayak match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 177146856a68SRajendra Nayak if (match) { 177246856a68SRajendra Nayak pdata = of_get_hsmmc_pdata(&pdev->dev); 1773dc642c28SJan Luebbe 1774dc642c28SJan Luebbe if (IS_ERR(pdata)) 1775dc642c28SJan Luebbe return PTR_ERR(pdata); 1776dc642c28SJan Luebbe 177746856a68SRajendra Nayak if (match->data) { 1778efc9b736SUwe Kleine-König const u16 *offsetp = match->data; 177946856a68SRajendra Nayak pdata->reg_offset = *offsetp; 178046856a68SRajendra Nayak } 178146856a68SRajendra Nayak } 1782a45c6cb8SMadhusudhan Chikkature 1783a45c6cb8SMadhusudhan Chikkature if (pdata == NULL) { 1784a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "Platform Data is missing\n"); 1785a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1786a45c6cb8SMadhusudhan Chikkature } 1787a45c6cb8SMadhusudhan Chikkature 1788a45c6cb8SMadhusudhan Chikkature if (pdata->nr_slots == 0) { 1789a45c6cb8SMadhusudhan Chikkature dev_err(&pdev->dev, "No Slots\n"); 1790a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1791a45c6cb8SMadhusudhan Chikkature } 1792a45c6cb8SMadhusudhan Chikkature 1793a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1794a45c6cb8SMadhusudhan Chikkature irq = platform_get_irq(pdev, 0); 1795a45c6cb8SMadhusudhan Chikkature if (res == NULL || irq < 0) 1796a45c6cb8SMadhusudhan Chikkature return -ENXIO; 1797a45c6cb8SMadhusudhan Chikkature 1798984b203aSChris Ball res = request_mem_region(res->start, resource_size(res), pdev->name); 1799a45c6cb8SMadhusudhan Chikkature if (res == NULL) 1800a45c6cb8SMadhusudhan Chikkature return -EBUSY; 1801a45c6cb8SMadhusudhan Chikkature 1802db0fefc5SAdrian Hunter ret = omap_hsmmc_gpio_init(pdata); 1803db0fefc5SAdrian Hunter if (ret) 1804db0fefc5SAdrian Hunter goto err; 1805db0fefc5SAdrian Hunter 180670a3341aSDenis Karpov mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 1807a45c6cb8SMadhusudhan Chikkature if (!mmc) { 1808a45c6cb8SMadhusudhan Chikkature ret = -ENOMEM; 1809db0fefc5SAdrian Hunter goto err_alloc; 1810a45c6cb8SMadhusudhan Chikkature } 1811a45c6cb8SMadhusudhan Chikkature 1812a45c6cb8SMadhusudhan Chikkature host = mmc_priv(mmc); 1813a45c6cb8SMadhusudhan Chikkature host->mmc = mmc; 1814a45c6cb8SMadhusudhan Chikkature host->pdata = pdata; 1815a45c6cb8SMadhusudhan Chikkature host->dev = &pdev->dev; 1816a45c6cb8SMadhusudhan Chikkature host->use_dma = 1; 1817a45c6cb8SMadhusudhan Chikkature host->dma_ch = -1; 1818a45c6cb8SMadhusudhan Chikkature host->irq = irq; 1819a45c6cb8SMadhusudhan Chikkature host->slot_id = 0; 1820fc307df8SBalaji T K host->mapbase = res->start + pdata->reg_offset; 1821a45c6cb8SMadhusudhan Chikkature host->base = ioremap(host->mapbase, SZ_4K); 18226da20c89SAdrian Hunter host->power_mode = MMC_POWER_OFF; 18239782aff8SPer Forlin host->next_data.cookie = 1; 1824a45c6cb8SMadhusudhan Chikkature 1825a45c6cb8SMadhusudhan Chikkature platform_set_drvdata(pdev, host); 1826a45c6cb8SMadhusudhan Chikkature 182770a3341aSDenis Karpov mmc->ops = &omap_hsmmc_ops; 1828dd498effSDenis Karpov 1829e0eb2424SAdrian Hunter /* 1830e0eb2424SAdrian Hunter * If regulator_disable can only put vcc_aux to sleep then there is 1831e0eb2424SAdrian Hunter * no off state. 1832e0eb2424SAdrian Hunter */ 1833e0eb2424SAdrian Hunter if (mmc_slot(host).vcc_aux_disable_is_sleep) 1834e0eb2424SAdrian Hunter mmc_slot(host).no_off = 1; 1835e0eb2424SAdrian Hunter 18366b206efeSAndy Shevchenko mmc->f_min = OMAP_MMC_MIN_CLOCK; 1837d418ed87SDaniel Mack 1838d418ed87SDaniel Mack if (pdata->max_freq > 0) 1839d418ed87SDaniel Mack mmc->f_max = pdata->max_freq; 1840d418ed87SDaniel Mack else 18416b206efeSAndy Shevchenko mmc->f_max = OMAP_MMC_MAX_CLOCK; 1842a45c6cb8SMadhusudhan Chikkature 18434dffd7a2SAdrian Hunter spin_lock_init(&host->irq_lock); 1844a45c6cb8SMadhusudhan Chikkature 18456f7607ccSRussell King host->fclk = clk_get(&pdev->dev, "fck"); 1846a45c6cb8SMadhusudhan Chikkature if (IS_ERR(host->fclk)) { 1847a45c6cb8SMadhusudhan Chikkature ret = PTR_ERR(host->fclk); 1848a45c6cb8SMadhusudhan Chikkature host->fclk = NULL; 1849a45c6cb8SMadhusudhan Chikkature goto err1; 1850a45c6cb8SMadhusudhan Chikkature } 1851a45c6cb8SMadhusudhan Chikkature 18529b68256cSPaul Walmsley if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 18539b68256cSPaul Walmsley dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 18549b68256cSPaul Walmsley mmc->caps2 |= MMC_CAP2_NO_MULTI_READ; 18559b68256cSPaul Walmsley } 1856dd498effSDenis Karpov 1857fa4aa2d4SBalaji T K pm_runtime_enable(host->dev); 1858fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 1859fa4aa2d4SBalaji T K pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 1860fa4aa2d4SBalaji T K pm_runtime_use_autosuspend(host->dev); 1861a45c6cb8SMadhusudhan Chikkature 186292a3aebfSBalaji T K omap_hsmmc_context_save(host); 186392a3aebfSBalaji T K 1864cf5ae40bSTony Lindgren /* This can be removed once we support PBIAS with DT */ 1865e002264fSBalaji T K if (host->dev->of_node && res->start == 0x4809c000) 1866cf5ae40bSTony Lindgren host->pbias_disable = 1; 1867cf5ae40bSTony Lindgren 1868a45c6cb8SMadhusudhan Chikkature host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); 1869a45c6cb8SMadhusudhan Chikkature /* 1870a45c6cb8SMadhusudhan Chikkature * MMC can still work without debounce clock. 1871a45c6cb8SMadhusudhan Chikkature */ 1872cd03d9a8SRajendra Nayak if (IS_ERR(host->dbclk)) { 1873cd03d9a8SRajendra Nayak host->dbclk = NULL; 187494c18149SRajendra Nayak } else if (clk_prepare_enable(host->dbclk) != 0) { 1875cd03d9a8SRajendra Nayak dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 1876cd03d9a8SRajendra Nayak clk_put(host->dbclk); 1877cd03d9a8SRajendra Nayak host->dbclk = NULL; 18782bec0893SAdrian Hunter } 1879a45c6cb8SMadhusudhan Chikkature 18800ccd76d4SJuha Yrjola /* Since we do only SG emulation, we can have as many segs 18810ccd76d4SJuha Yrjola * as we want. */ 1882a36274e0SMartin K. Petersen mmc->max_segs = 1024; 18830ccd76d4SJuha Yrjola 1884a45c6cb8SMadhusudhan Chikkature mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 1885a45c6cb8SMadhusudhan Chikkature mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 1886a45c6cb8SMadhusudhan Chikkature mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1887a45c6cb8SMadhusudhan Chikkature mmc->max_seg_size = mmc->max_req_size; 1888a45c6cb8SMadhusudhan Chikkature 188913189e78SJarkko Lavinen mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 189093caf8e6SAdrian Hunter MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 1891a45c6cb8SMadhusudhan Chikkature 18923a63833eSSukumar Ghorai mmc->caps |= mmc_slot(host).caps; 18933a63833eSSukumar Ghorai if (mmc->caps & MMC_CAP_8_BIT_DATA) 1894a45c6cb8SMadhusudhan Chikkature mmc->caps |= MMC_CAP_4_BIT_DATA; 1895a45c6cb8SMadhusudhan Chikkature 1896191d1f1dSDenis Karpov if (mmc_slot(host).nonremovable) 189723d99bb9SAdrian Hunter mmc->caps |= MMC_CAP_NONREMOVABLE; 189823d99bb9SAdrian Hunter 18996fdc75deSEliad Peller mmc->pm_caps = mmc_slot(host).pm_caps; 19006fdc75deSEliad Peller 190170a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 1902a45c6cb8SMadhusudhan Chikkature 19034a29b559SSantosh Shilimkar if (!pdev->dev.of_node) { 1904b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 1905b7bf773bSBalaji T K if (!res) { 1906b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n"); 19079c17d08cSKevin Hilman ret = -ENXIO; 1908f3e2f1ddSGrazvydas Ignotas goto err_irq; 1909a45c6cb8SMadhusudhan Chikkature } 191026b88520SRussell King tx_req = res->start; 1911b7bf773bSBalaji T K 1912b7bf773bSBalaji T K res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 1913b7bf773bSBalaji T K if (!res) { 1914b7bf773bSBalaji T K dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n"); 19159c17d08cSKevin Hilman ret = -ENXIO; 1916b7bf773bSBalaji T K goto err_irq; 1917b7bf773bSBalaji T K } 191826b88520SRussell King rx_req = res->start; 19194a29b559SSantosh Shilimkar } 1920c5c98927SRussell King 1921c5c98927SRussell King dma_cap_zero(mask); 1922c5c98927SRussell King dma_cap_set(DMA_SLAVE, mask); 192326b88520SRussell King 1924d272fbf0SMatt Porter host->rx_chan = 1925d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 1926d272fbf0SMatt Porter &rx_req, &pdev->dev, "rx"); 1927d272fbf0SMatt Porter 1928c5c98927SRussell King if (!host->rx_chan) { 192926b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req); 193004e8c7bcSKevin Hilman ret = -ENXIO; 193126b88520SRussell King goto err_irq; 1932c5c98927SRussell King } 193326b88520SRussell King 1934d272fbf0SMatt Porter host->tx_chan = 1935d272fbf0SMatt Porter dma_request_slave_channel_compat(mask, omap_dma_filter_fn, 1936d272fbf0SMatt Porter &tx_req, &pdev->dev, "tx"); 1937d272fbf0SMatt Porter 1938c5c98927SRussell King if (!host->tx_chan) { 193926b88520SRussell King dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req); 194004e8c7bcSKevin Hilman ret = -ENXIO; 194126b88520SRussell King goto err_irq; 1942c5c98927SRussell King } 1943a45c6cb8SMadhusudhan Chikkature 1944a45c6cb8SMadhusudhan Chikkature /* Request IRQ for MMC operations */ 1945d9618e9fSYong Zhang ret = request_irq(host->irq, omap_hsmmc_irq, 0, 1946a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 1947a45c6cb8SMadhusudhan Chikkature if (ret) { 1948b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 1949a45c6cb8SMadhusudhan Chikkature goto err_irq; 1950a45c6cb8SMadhusudhan Chikkature } 1951a45c6cb8SMadhusudhan Chikkature 1952a45c6cb8SMadhusudhan Chikkature if (pdata->init != NULL) { 1953a45c6cb8SMadhusudhan Chikkature if (pdata->init(&pdev->dev) != 0) { 1954b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), 195570a3341aSDenis Karpov "Unable to configure MMC IRQs\n"); 1956a45c6cb8SMadhusudhan Chikkature goto err_irq_cd_init; 1957a45c6cb8SMadhusudhan Chikkature } 1958a45c6cb8SMadhusudhan Chikkature } 1959db0fefc5SAdrian Hunter 1960b702b106SAdrian Hunter if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) { 1961db0fefc5SAdrian Hunter ret = omap_hsmmc_reg_get(host); 1962db0fefc5SAdrian Hunter if (ret) 1963db0fefc5SAdrian Hunter goto err_reg; 1964db0fefc5SAdrian Hunter host->use_reg = 1; 1965db0fefc5SAdrian Hunter } 1966db0fefc5SAdrian Hunter 1967b583f26dSDavid Brownell mmc->ocr_avail = mmc_slot(host).ocr_mask; 1968a45c6cb8SMadhusudhan Chikkature 1969a45c6cb8SMadhusudhan Chikkature /* Request IRQ for card detect */ 1970e1a55f5eSAdrian Hunter if ((mmc_slot(host).card_detect_irq)) { 19717efab4f3SNeilBrown ret = request_threaded_irq(mmc_slot(host).card_detect_irq, 19727efab4f3SNeilBrown NULL, 19737efab4f3SNeilBrown omap_hsmmc_detect, 1974db35f83eSMing Lei IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1975a45c6cb8SMadhusudhan Chikkature mmc_hostname(mmc), host); 1976a45c6cb8SMadhusudhan Chikkature if (ret) { 1977b1e056aeSVenkatraman S dev_err(mmc_dev(host->mmc), 1978a45c6cb8SMadhusudhan Chikkature "Unable to grab MMC CD IRQ\n"); 1979a45c6cb8SMadhusudhan Chikkature goto err_irq_cd; 1980a45c6cb8SMadhusudhan Chikkature } 198172f2e2c7Skishore kadiyala pdata->suspend = omap_hsmmc_suspend_cdirq; 198272f2e2c7Skishore kadiyala pdata->resume = omap_hsmmc_resume_cdirq; 1983a45c6cb8SMadhusudhan Chikkature } 1984a45c6cb8SMadhusudhan Chikkature 1985b417577dSAdrian Hunter omap_hsmmc_disable_irq(host); 1986a45c6cb8SMadhusudhan Chikkature 198746b76035SDaniel Mack pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 198846b76035SDaniel Mack if (IS_ERR(pinctrl)) 198946b76035SDaniel Mack dev_warn(&pdev->dev, 199046b76035SDaniel Mack "pins are not configured from the driver\n"); 199146b76035SDaniel Mack 1992b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 1993b62f6228SAdrian Hunter 1994a45c6cb8SMadhusudhan Chikkature mmc_add_host(mmc); 1995a45c6cb8SMadhusudhan Chikkature 1996191d1f1dSDenis Karpov if (mmc_slot(host).name != NULL) { 1997a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 1998a45c6cb8SMadhusudhan Chikkature if (ret < 0) 1999a45c6cb8SMadhusudhan Chikkature goto err_slot_name; 2000a45c6cb8SMadhusudhan Chikkature } 2001191d1f1dSDenis Karpov if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { 2002a45c6cb8SMadhusudhan Chikkature ret = device_create_file(&mmc->class_dev, 2003a45c6cb8SMadhusudhan Chikkature &dev_attr_cover_switch); 2004a45c6cb8SMadhusudhan Chikkature if (ret < 0) 2005db0fefc5SAdrian Hunter goto err_slot_name; 2006a45c6cb8SMadhusudhan Chikkature } 2007a45c6cb8SMadhusudhan Chikkature 200870a3341aSDenis Karpov omap_hsmmc_debugfs(mmc); 2009fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2010fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2011d900f712SDenis Karpov 2012a45c6cb8SMadhusudhan Chikkature return 0; 2013a45c6cb8SMadhusudhan Chikkature 2014a45c6cb8SMadhusudhan Chikkature err_slot_name: 2015a45c6cb8SMadhusudhan Chikkature mmc_remove_host(mmc); 2016a45c6cb8SMadhusudhan Chikkature free_irq(mmc_slot(host).card_detect_irq, host); 2017db0fefc5SAdrian Hunter err_irq_cd: 2018db0fefc5SAdrian Hunter if (host->use_reg) 2019db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2020db0fefc5SAdrian Hunter err_reg: 2021db0fefc5SAdrian Hunter if (host->pdata->cleanup) 2022db0fefc5SAdrian Hunter host->pdata->cleanup(&pdev->dev); 2023a45c6cb8SMadhusudhan Chikkature err_irq_cd_init: 2024a45c6cb8SMadhusudhan Chikkature free_irq(host->irq, host); 2025a45c6cb8SMadhusudhan Chikkature err_irq: 2026c5c98927SRussell King if (host->tx_chan) 2027c5c98927SRussell King dma_release_channel(host->tx_chan); 2028c5c98927SRussell King if (host->rx_chan) 2029c5c98927SRussell King dma_release_channel(host->rx_chan); 2030d59d77edSBalaji T K pm_runtime_put_sync(host->dev); 203137f6190dSTony Lindgren pm_runtime_disable(host->dev); 2032a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 2033cd03d9a8SRajendra Nayak if (host->dbclk) { 203494c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2035a45c6cb8SMadhusudhan Chikkature clk_put(host->dbclk); 2036a45c6cb8SMadhusudhan Chikkature } 2037a45c6cb8SMadhusudhan Chikkature err1: 2038a45c6cb8SMadhusudhan Chikkature iounmap(host->base); 2039a45c6cb8SMadhusudhan Chikkature mmc_free_host(mmc); 2040db0fefc5SAdrian Hunter err_alloc: 2041db0fefc5SAdrian Hunter omap_hsmmc_gpio_free(pdata); 2042db0fefc5SAdrian Hunter err: 204348b332f9SRussell King res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 204448b332f9SRussell King if (res) 2045984b203aSChris Ball release_mem_region(res->start, resource_size(res)); 2046a45c6cb8SMadhusudhan Chikkature return ret; 2047a45c6cb8SMadhusudhan Chikkature } 2048a45c6cb8SMadhusudhan Chikkature 20496e0ee714SBill Pemberton static int omap_hsmmc_remove(struct platform_device *pdev) 2050a45c6cb8SMadhusudhan Chikkature { 205170a3341aSDenis Karpov struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2052a45c6cb8SMadhusudhan Chikkature struct resource *res; 2053a45c6cb8SMadhusudhan Chikkature 2054fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2055a45c6cb8SMadhusudhan Chikkature mmc_remove_host(host->mmc); 2056db0fefc5SAdrian Hunter if (host->use_reg) 2057db0fefc5SAdrian Hunter omap_hsmmc_reg_put(host); 2058a45c6cb8SMadhusudhan Chikkature if (host->pdata->cleanup) 2059a45c6cb8SMadhusudhan Chikkature host->pdata->cleanup(&pdev->dev); 2060a45c6cb8SMadhusudhan Chikkature free_irq(host->irq, host); 2061a45c6cb8SMadhusudhan Chikkature if (mmc_slot(host).card_detect_irq) 2062a45c6cb8SMadhusudhan Chikkature free_irq(mmc_slot(host).card_detect_irq, host); 2063a45c6cb8SMadhusudhan Chikkature 2064c5c98927SRussell King if (host->tx_chan) 2065c5c98927SRussell King dma_release_channel(host->tx_chan); 2066c5c98927SRussell King if (host->rx_chan) 2067c5c98927SRussell King dma_release_channel(host->rx_chan); 2068c5c98927SRussell King 2069fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2070fa4aa2d4SBalaji T K pm_runtime_disable(host->dev); 2071a45c6cb8SMadhusudhan Chikkature clk_put(host->fclk); 2072cd03d9a8SRajendra Nayak if (host->dbclk) { 207394c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 2074a45c6cb8SMadhusudhan Chikkature clk_put(host->dbclk); 2075a45c6cb8SMadhusudhan Chikkature } 2076a45c6cb8SMadhusudhan Chikkature 20779ea28ecbSBalaji T K omap_hsmmc_gpio_free(host->pdata); 2078a45c6cb8SMadhusudhan Chikkature iounmap(host->base); 20799d1f0286SBalaji T K mmc_free_host(host->mmc); 2080a45c6cb8SMadhusudhan Chikkature 2081a45c6cb8SMadhusudhan Chikkature res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2082a45c6cb8SMadhusudhan Chikkature if (res) 2083984b203aSChris Ball release_mem_region(res->start, resource_size(res)); 2084a45c6cb8SMadhusudhan Chikkature 2085a45c6cb8SMadhusudhan Chikkature return 0; 2086a45c6cb8SMadhusudhan Chikkature } 2087a45c6cb8SMadhusudhan Chikkature 2088a45c6cb8SMadhusudhan Chikkature #ifdef CONFIG_PM 2089a48ce884SFelipe Balbi static int omap_hsmmc_prepare(struct device *dev) 2090a48ce884SFelipe Balbi { 2091a48ce884SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2092a48ce884SFelipe Balbi 2093a48ce884SFelipe Balbi if (host->pdata->suspend) 2094a48ce884SFelipe Balbi return host->pdata->suspend(dev, host->slot_id); 2095a48ce884SFelipe Balbi 2096a48ce884SFelipe Balbi return 0; 2097a48ce884SFelipe Balbi } 2098a48ce884SFelipe Balbi 2099a48ce884SFelipe Balbi static void omap_hsmmc_complete(struct device *dev) 2100a48ce884SFelipe Balbi { 2101a48ce884SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2102a48ce884SFelipe Balbi 2103a48ce884SFelipe Balbi if (host->pdata->resume) 2104a48ce884SFelipe Balbi host->pdata->resume(dev, host->slot_id); 2105a48ce884SFelipe Balbi 2106a48ce884SFelipe Balbi } 2107a48ce884SFelipe Balbi 2108a791daa1SKevin Hilman static int omap_hsmmc_suspend(struct device *dev) 2109a45c6cb8SMadhusudhan Chikkature { 2110a45c6cb8SMadhusudhan Chikkature int ret = 0; 2111927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2112927ce944SFelipe Balbi 2113927ce944SFelipe Balbi if (!host) 2114927ce944SFelipe Balbi return 0; 2115a45c6cb8SMadhusudhan Chikkature 2116a45c6cb8SMadhusudhan Chikkature if (host && host->suspended) 2117a45c6cb8SMadhusudhan Chikkature return 0; 2118a45c6cb8SMadhusudhan Chikkature 2119fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 2120a45c6cb8SMadhusudhan Chikkature host->suspended = 1; 21211a13f8faSMatt Fleming ret = mmc_suspend_host(host->mmc); 2122fa4aa2d4SBalaji T K 212331f9d463SEliad Peller if (ret) { 2124a6b2240dSAdrian Hunter host->suspended = 0; 212531f9d463SEliad Peller goto err; 2126a6b2240dSAdrian Hunter } 212731f9d463SEliad Peller 212831f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 212931f9d463SEliad Peller omap_hsmmc_disable_irq(host); 213031f9d463SEliad Peller OMAP_HSMMC_WRITE(host->base, HCTL, 213131f9d463SEliad Peller OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 213231f9d463SEliad Peller } 2133927ce944SFelipe Balbi 2134cd03d9a8SRajendra Nayak if (host->dbclk) 213594c18149SRajendra Nayak clk_disable_unprepare(host->dbclk); 213631f9d463SEliad Peller err: 2137fa4aa2d4SBalaji T K pm_runtime_put_sync(host->dev); 2138a45c6cb8SMadhusudhan Chikkature return ret; 2139a45c6cb8SMadhusudhan Chikkature } 2140a45c6cb8SMadhusudhan Chikkature 2141a45c6cb8SMadhusudhan Chikkature /* Routine to resume the MMC device */ 2142a791daa1SKevin Hilman static int omap_hsmmc_resume(struct device *dev) 2143a45c6cb8SMadhusudhan Chikkature { 2144a45c6cb8SMadhusudhan Chikkature int ret = 0; 2145927ce944SFelipe Balbi struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2146927ce944SFelipe Balbi 2147927ce944SFelipe Balbi if (!host) 2148927ce944SFelipe Balbi return 0; 2149a45c6cb8SMadhusudhan Chikkature 2150a45c6cb8SMadhusudhan Chikkature if (host && !host->suspended) 2151a45c6cb8SMadhusudhan Chikkature return 0; 2152a45c6cb8SMadhusudhan Chikkature 2153fa4aa2d4SBalaji T K pm_runtime_get_sync(host->dev); 215411dd62a7SDenis Karpov 2155cd03d9a8SRajendra Nayak if (host->dbclk) 215694c18149SRajendra Nayak clk_prepare_enable(host->dbclk); 21572bec0893SAdrian Hunter 215831f9d463SEliad Peller if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 215970a3341aSDenis Karpov omap_hsmmc_conf_bus_power(host); 21601b331e69SKim Kyuwon 2161b62f6228SAdrian Hunter omap_hsmmc_protect_card(host); 2162b62f6228SAdrian Hunter 2163a45c6cb8SMadhusudhan Chikkature /* Notify the core to resume the host */ 2164a45c6cb8SMadhusudhan Chikkature ret = mmc_resume_host(host->mmc); 2165a45c6cb8SMadhusudhan Chikkature if (ret == 0) 2166a45c6cb8SMadhusudhan Chikkature host->suspended = 0; 2167fa4aa2d4SBalaji T K 2168fa4aa2d4SBalaji T K pm_runtime_mark_last_busy(host->dev); 2169fa4aa2d4SBalaji T K pm_runtime_put_autosuspend(host->dev); 2170a45c6cb8SMadhusudhan Chikkature 2171a45c6cb8SMadhusudhan Chikkature return ret; 2172a45c6cb8SMadhusudhan Chikkature 2173a45c6cb8SMadhusudhan Chikkature } 2174a45c6cb8SMadhusudhan Chikkature 2175a45c6cb8SMadhusudhan Chikkature #else 2176a48ce884SFelipe Balbi #define omap_hsmmc_prepare NULL 2177a48ce884SFelipe Balbi #define omap_hsmmc_complete NULL 217870a3341aSDenis Karpov #define omap_hsmmc_suspend NULL 217970a3341aSDenis Karpov #define omap_hsmmc_resume NULL 2180a45c6cb8SMadhusudhan Chikkature #endif 2181a45c6cb8SMadhusudhan Chikkature 2182fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_suspend(struct device *dev) 2183fa4aa2d4SBalaji T K { 2184fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 2185fa4aa2d4SBalaji T K 2186fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2187fa4aa2d4SBalaji T K omap_hsmmc_context_save(host); 2188927ce944SFelipe Balbi dev_dbg(dev, "disabled\n"); 2189fa4aa2d4SBalaji T K 2190fa4aa2d4SBalaji T K return 0; 2191fa4aa2d4SBalaji T K } 2192fa4aa2d4SBalaji T K 2193fa4aa2d4SBalaji T K static int omap_hsmmc_runtime_resume(struct device *dev) 2194fa4aa2d4SBalaji T K { 2195fa4aa2d4SBalaji T K struct omap_hsmmc_host *host; 2196fa4aa2d4SBalaji T K 2197fa4aa2d4SBalaji T K host = platform_get_drvdata(to_platform_device(dev)); 2198fa4aa2d4SBalaji T K omap_hsmmc_context_restore(host); 2199927ce944SFelipe Balbi dev_dbg(dev, "enabled\n"); 2200fa4aa2d4SBalaji T K 2201fa4aa2d4SBalaji T K return 0; 2202fa4aa2d4SBalaji T K } 2203fa4aa2d4SBalaji T K 2204a791daa1SKevin Hilman static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 220570a3341aSDenis Karpov .suspend = omap_hsmmc_suspend, 220670a3341aSDenis Karpov .resume = omap_hsmmc_resume, 2207a48ce884SFelipe Balbi .prepare = omap_hsmmc_prepare, 2208a48ce884SFelipe Balbi .complete = omap_hsmmc_complete, 2209fa4aa2d4SBalaji T K .runtime_suspend = omap_hsmmc_runtime_suspend, 2210fa4aa2d4SBalaji T K .runtime_resume = omap_hsmmc_runtime_resume, 2211a791daa1SKevin Hilman }; 2212a791daa1SKevin Hilman 2213a791daa1SKevin Hilman static struct platform_driver omap_hsmmc_driver = { 2214efa25fd3SFelipe Balbi .probe = omap_hsmmc_probe, 22150433c143SBill Pemberton .remove = omap_hsmmc_remove, 2216a45c6cb8SMadhusudhan Chikkature .driver = { 2217a45c6cb8SMadhusudhan Chikkature .name = DRIVER_NAME, 2218a45c6cb8SMadhusudhan Chikkature .owner = THIS_MODULE, 2219a791daa1SKevin Hilman .pm = &omap_hsmmc_dev_pm_ops, 222046856a68SRajendra Nayak .of_match_table = of_match_ptr(omap_mmc_of_match), 2221a45c6cb8SMadhusudhan Chikkature }, 2222a45c6cb8SMadhusudhan Chikkature }; 2223a45c6cb8SMadhusudhan Chikkature 2224b796450bSFelipe Balbi module_platform_driver(omap_hsmmc_driver); 2225a45c6cb8SMadhusudhan Chikkature MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2226a45c6cb8SMadhusudhan Chikkature MODULE_LICENSE("GPL"); 2227a45c6cb8SMadhusudhan Chikkature MODULE_ALIAS("platform:" DRIVER_NAME); 2228a45c6cb8SMadhusudhan Chikkature MODULE_AUTHOR("Texas Instruments Inc"); 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