1 /* 2 * linux/drivers/mmc/host/omap.c 3 * 4 * Copyright (C) 2004 Nokia Corporation 5 * Written by Tuukka Tikkanen and Juha Yrj�l�<juha.yrjola@nokia.com> 6 * Misc hacks here and there by Tony Lindgren <tony@atomide.com> 7 * Other hacks (DMA, SD, etc) by David Brownell 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/init.h> 17 #include <linux/ioport.h> 18 #include <linux/platform_device.h> 19 #include <linux/interrupt.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/delay.h> 22 #include <linux/spinlock.h> 23 #include <linux/timer.h> 24 #include <linux/mmc/host.h> 25 #include <linux/mmc/card.h> 26 #include <linux/clk.h> 27 #include <linux/scatterlist.h> 28 #include <linux/i2c/tps65010.h> 29 30 #include <asm/io.h> 31 #include <asm/irq.h> 32 33 #include <plat/board.h> 34 #include <plat/mmc.h> 35 #include <mach/gpio.h> 36 #include <plat/dma.h> 37 #include <plat/mux.h> 38 #include <plat/fpga.h> 39 40 #define OMAP_MMC_REG_CMD 0x00 41 #define OMAP_MMC_REG_ARGL 0x04 42 #define OMAP_MMC_REG_ARGH 0x08 43 #define OMAP_MMC_REG_CON 0x0c 44 #define OMAP_MMC_REG_STAT 0x10 45 #define OMAP_MMC_REG_IE 0x14 46 #define OMAP_MMC_REG_CTO 0x18 47 #define OMAP_MMC_REG_DTO 0x1c 48 #define OMAP_MMC_REG_DATA 0x20 49 #define OMAP_MMC_REG_BLEN 0x24 50 #define OMAP_MMC_REG_NBLK 0x28 51 #define OMAP_MMC_REG_BUF 0x2c 52 #define OMAP_MMC_REG_SDIO 0x34 53 #define OMAP_MMC_REG_REV 0x3c 54 #define OMAP_MMC_REG_RSP0 0x40 55 #define OMAP_MMC_REG_RSP1 0x44 56 #define OMAP_MMC_REG_RSP2 0x48 57 #define OMAP_MMC_REG_RSP3 0x4c 58 #define OMAP_MMC_REG_RSP4 0x50 59 #define OMAP_MMC_REG_RSP5 0x54 60 #define OMAP_MMC_REG_RSP6 0x58 61 #define OMAP_MMC_REG_RSP7 0x5c 62 #define OMAP_MMC_REG_IOSR 0x60 63 #define OMAP_MMC_REG_SYSC 0x64 64 #define OMAP_MMC_REG_SYSS 0x68 65 66 #define OMAP_MMC_STAT_CARD_ERR (1 << 14) 67 #define OMAP_MMC_STAT_CARD_IRQ (1 << 13) 68 #define OMAP_MMC_STAT_OCR_BUSY (1 << 12) 69 #define OMAP_MMC_STAT_A_EMPTY (1 << 11) 70 #define OMAP_MMC_STAT_A_FULL (1 << 10) 71 #define OMAP_MMC_STAT_CMD_CRC (1 << 8) 72 #define OMAP_MMC_STAT_CMD_TOUT (1 << 7) 73 #define OMAP_MMC_STAT_DATA_CRC (1 << 6) 74 #define OMAP_MMC_STAT_DATA_TOUT (1 << 5) 75 #define OMAP_MMC_STAT_END_BUSY (1 << 4) 76 #define OMAP_MMC_STAT_END_OF_DATA (1 << 3) 77 #define OMAP_MMC_STAT_CARD_BUSY (1 << 2) 78 #define OMAP_MMC_STAT_END_OF_CMD (1 << 0) 79 80 #define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg) 81 #define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg) 82 83 /* 84 * Command types 85 */ 86 #define OMAP_MMC_CMDTYPE_BC 0 87 #define OMAP_MMC_CMDTYPE_BCR 1 88 #define OMAP_MMC_CMDTYPE_AC 2 89 #define OMAP_MMC_CMDTYPE_ADTC 3 90 91 92 #define DRIVER_NAME "mmci-omap" 93 94 /* Specifies how often in millisecs to poll for card status changes 95 * when the cover switch is open */ 96 #define OMAP_MMC_COVER_POLL_DELAY 500 97 98 struct mmc_omap_host; 99 100 struct mmc_omap_slot { 101 int id; 102 unsigned int vdd; 103 u16 saved_con; 104 u16 bus_mode; 105 unsigned int fclk_freq; 106 unsigned powered:1; 107 108 struct tasklet_struct cover_tasklet; 109 struct timer_list cover_timer; 110 unsigned cover_open; 111 112 struct mmc_request *mrq; 113 struct mmc_omap_host *host; 114 struct mmc_host *mmc; 115 struct omap_mmc_slot_data *pdata; 116 }; 117 118 struct mmc_omap_host { 119 int initialized; 120 int suspended; 121 struct mmc_request * mrq; 122 struct mmc_command * cmd; 123 struct mmc_data * data; 124 struct mmc_host * mmc; 125 struct device * dev; 126 unsigned char id; /* 16xx chips have 2 MMC blocks */ 127 struct clk * iclk; 128 struct clk * fclk; 129 struct resource *mem_res; 130 void __iomem *virt_base; 131 unsigned int phys_base; 132 int irq; 133 unsigned char bus_mode; 134 unsigned char hw_bus_mode; 135 136 struct work_struct cmd_abort_work; 137 unsigned abort:1; 138 struct timer_list cmd_abort_timer; 139 140 struct work_struct slot_release_work; 141 struct mmc_omap_slot *next_slot; 142 struct work_struct send_stop_work; 143 struct mmc_data *stop_data; 144 145 unsigned int sg_len; 146 int sg_idx; 147 u16 * buffer; 148 u32 buffer_bytes_left; 149 u32 total_bytes_left; 150 151 unsigned use_dma:1; 152 unsigned brs_received:1, dma_done:1; 153 unsigned dma_is_read:1; 154 unsigned dma_in_use:1; 155 int dma_ch; 156 spinlock_t dma_lock; 157 struct timer_list dma_timer; 158 unsigned dma_len; 159 160 struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS]; 161 struct mmc_omap_slot *current_slot; 162 spinlock_t slot_lock; 163 wait_queue_head_t slot_wq; 164 int nr_slots; 165 166 struct timer_list clk_timer; 167 spinlock_t clk_lock; /* for changing enabled state */ 168 unsigned int fclk_enabled:1; 169 170 struct omap_mmc_platform_data *pdata; 171 }; 172 173 static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot) 174 { 175 unsigned long tick_ns; 176 177 if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) { 178 tick_ns = (1000000000 + slot->fclk_freq - 1) / slot->fclk_freq; 179 ndelay(8 * tick_ns); 180 } 181 } 182 183 static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable) 184 { 185 unsigned long flags; 186 187 spin_lock_irqsave(&host->clk_lock, flags); 188 if (host->fclk_enabled != enable) { 189 host->fclk_enabled = enable; 190 if (enable) 191 clk_enable(host->fclk); 192 else 193 clk_disable(host->fclk); 194 } 195 spin_unlock_irqrestore(&host->clk_lock, flags); 196 } 197 198 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed) 199 { 200 struct mmc_omap_host *host = slot->host; 201 unsigned long flags; 202 203 if (claimed) 204 goto no_claim; 205 spin_lock_irqsave(&host->slot_lock, flags); 206 while (host->mmc != NULL) { 207 spin_unlock_irqrestore(&host->slot_lock, flags); 208 wait_event(host->slot_wq, host->mmc == NULL); 209 spin_lock_irqsave(&host->slot_lock, flags); 210 } 211 host->mmc = slot->mmc; 212 spin_unlock_irqrestore(&host->slot_lock, flags); 213 no_claim: 214 del_timer(&host->clk_timer); 215 if (host->current_slot != slot || !claimed) 216 mmc_omap_fclk_offdelay(host->current_slot); 217 218 if (host->current_slot != slot) { 219 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00); 220 if (host->pdata->switch_slot != NULL) 221 host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id); 222 host->current_slot = slot; 223 } 224 225 if (claimed) { 226 mmc_omap_fclk_enable(host, 1); 227 228 /* Doing the dummy read here seems to work around some bug 229 * at least in OMAP24xx silicon where the command would not 230 * start after writing the CMD register. Sigh. */ 231 OMAP_MMC_READ(host, CON); 232 233 OMAP_MMC_WRITE(host, CON, slot->saved_con); 234 } else 235 mmc_omap_fclk_enable(host, 0); 236 } 237 238 static void mmc_omap_start_request(struct mmc_omap_host *host, 239 struct mmc_request *req); 240 241 static void mmc_omap_slot_release_work(struct work_struct *work) 242 { 243 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, 244 slot_release_work); 245 struct mmc_omap_slot *next_slot = host->next_slot; 246 struct mmc_request *rq; 247 248 host->next_slot = NULL; 249 mmc_omap_select_slot(next_slot, 1); 250 251 rq = next_slot->mrq; 252 next_slot->mrq = NULL; 253 mmc_omap_start_request(host, rq); 254 } 255 256 static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled) 257 { 258 struct mmc_omap_host *host = slot->host; 259 unsigned long flags; 260 int i; 261 262 BUG_ON(slot == NULL || host->mmc == NULL); 263 264 if (clk_enabled) 265 /* Keeps clock running for at least 8 cycles on valid freq */ 266 mod_timer(&host->clk_timer, jiffies + HZ/10); 267 else { 268 del_timer(&host->clk_timer); 269 mmc_omap_fclk_offdelay(slot); 270 mmc_omap_fclk_enable(host, 0); 271 } 272 273 spin_lock_irqsave(&host->slot_lock, flags); 274 /* Check for any pending requests */ 275 for (i = 0; i < host->nr_slots; i++) { 276 struct mmc_omap_slot *new_slot; 277 278 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL) 279 continue; 280 281 BUG_ON(host->next_slot != NULL); 282 new_slot = host->slots[i]; 283 /* The current slot should not have a request in queue */ 284 BUG_ON(new_slot == host->current_slot); 285 286 host->next_slot = new_slot; 287 host->mmc = new_slot->mmc; 288 spin_unlock_irqrestore(&host->slot_lock, flags); 289 schedule_work(&host->slot_release_work); 290 return; 291 } 292 293 host->mmc = NULL; 294 wake_up(&host->slot_wq); 295 spin_unlock_irqrestore(&host->slot_lock, flags); 296 } 297 298 static inline 299 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot) 300 { 301 if (slot->pdata->get_cover_state) 302 return slot->pdata->get_cover_state(mmc_dev(slot->mmc), 303 slot->id); 304 return 0; 305 } 306 307 static ssize_t 308 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr, 309 char *buf) 310 { 311 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 312 struct mmc_omap_slot *slot = mmc_priv(mmc); 313 314 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" : 315 "closed"); 316 } 317 318 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL); 319 320 static ssize_t 321 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr, 322 char *buf) 323 { 324 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 325 struct mmc_omap_slot *slot = mmc_priv(mmc); 326 327 return sprintf(buf, "%s\n", slot->pdata->name); 328 } 329 330 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL); 331 332 static void 333 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd) 334 { 335 u32 cmdreg; 336 u32 resptype; 337 u32 cmdtype; 338 339 host->cmd = cmd; 340 341 resptype = 0; 342 cmdtype = 0; 343 344 /* Our hardware needs to know exact type */ 345 switch (mmc_resp_type(cmd)) { 346 case MMC_RSP_NONE: 347 break; 348 case MMC_RSP_R1: 349 case MMC_RSP_R1B: 350 /* resp 1, 1b, 6, 7 */ 351 resptype = 1; 352 break; 353 case MMC_RSP_R2: 354 resptype = 2; 355 break; 356 case MMC_RSP_R3: 357 resptype = 3; 358 break; 359 default: 360 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd)); 361 break; 362 } 363 364 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) { 365 cmdtype = OMAP_MMC_CMDTYPE_ADTC; 366 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) { 367 cmdtype = OMAP_MMC_CMDTYPE_BC; 368 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) { 369 cmdtype = OMAP_MMC_CMDTYPE_BCR; 370 } else { 371 cmdtype = OMAP_MMC_CMDTYPE_AC; 372 } 373 374 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12); 375 376 if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN) 377 cmdreg |= 1 << 6; 378 379 if (cmd->flags & MMC_RSP_BUSY) 380 cmdreg |= 1 << 11; 381 382 if (host->data && !(host->data->flags & MMC_DATA_WRITE)) 383 cmdreg |= 1 << 15; 384 385 mod_timer(&host->cmd_abort_timer, jiffies + HZ/2); 386 387 OMAP_MMC_WRITE(host, CTO, 200); 388 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff); 389 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16); 390 OMAP_MMC_WRITE(host, IE, 391 OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL | 392 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT | 393 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT | 394 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR | 395 OMAP_MMC_STAT_END_OF_DATA); 396 OMAP_MMC_WRITE(host, CMD, cmdreg); 397 } 398 399 static void 400 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data, 401 int abort) 402 { 403 enum dma_data_direction dma_data_dir; 404 405 BUG_ON(host->dma_ch < 0); 406 if (data->error) 407 omap_stop_dma(host->dma_ch); 408 /* Release DMA channel lazily */ 409 mod_timer(&host->dma_timer, jiffies + HZ); 410 if (data->flags & MMC_DATA_WRITE) 411 dma_data_dir = DMA_TO_DEVICE; 412 else 413 dma_data_dir = DMA_FROM_DEVICE; 414 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len, 415 dma_data_dir); 416 } 417 418 static void mmc_omap_send_stop_work(struct work_struct *work) 419 { 420 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, 421 send_stop_work); 422 struct mmc_omap_slot *slot = host->current_slot; 423 struct mmc_data *data = host->stop_data; 424 unsigned long tick_ns; 425 426 tick_ns = (1000000000 + slot->fclk_freq - 1)/slot->fclk_freq; 427 ndelay(8*tick_ns); 428 429 mmc_omap_start_command(host, data->stop); 430 } 431 432 static void 433 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data) 434 { 435 if (host->dma_in_use) 436 mmc_omap_release_dma(host, data, data->error); 437 438 host->data = NULL; 439 host->sg_len = 0; 440 441 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing 442 * dozens of requests until the card finishes writing data. 443 * It'd be cheaper to just wait till an EOFB interrupt arrives... 444 */ 445 446 if (!data->stop) { 447 struct mmc_host *mmc; 448 449 host->mrq = NULL; 450 mmc = host->mmc; 451 mmc_omap_release_slot(host->current_slot, 1); 452 mmc_request_done(mmc, data->mrq); 453 return; 454 } 455 456 host->stop_data = data; 457 schedule_work(&host->send_stop_work); 458 } 459 460 static void 461 mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops) 462 { 463 struct mmc_omap_slot *slot = host->current_slot; 464 unsigned int restarts, passes, timeout; 465 u16 stat = 0; 466 467 /* Sending abort takes 80 clocks. Have some extra and round up */ 468 timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq; 469 restarts = 0; 470 while (restarts < maxloops) { 471 OMAP_MMC_WRITE(host, STAT, 0xFFFF); 472 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7)); 473 474 passes = 0; 475 while (passes < timeout) { 476 stat = OMAP_MMC_READ(host, STAT); 477 if (stat & OMAP_MMC_STAT_END_OF_CMD) 478 goto out; 479 udelay(1); 480 passes++; 481 } 482 483 restarts++; 484 } 485 out: 486 OMAP_MMC_WRITE(host, STAT, stat); 487 } 488 489 static void 490 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data) 491 { 492 if (host->dma_in_use) 493 mmc_omap_release_dma(host, data, 1); 494 495 host->data = NULL; 496 host->sg_len = 0; 497 498 mmc_omap_send_abort(host, 10000); 499 } 500 501 static void 502 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data) 503 { 504 unsigned long flags; 505 int done; 506 507 if (!host->dma_in_use) { 508 mmc_omap_xfer_done(host, data); 509 return; 510 } 511 done = 0; 512 spin_lock_irqsave(&host->dma_lock, flags); 513 if (host->dma_done) 514 done = 1; 515 else 516 host->brs_received = 1; 517 spin_unlock_irqrestore(&host->dma_lock, flags); 518 if (done) 519 mmc_omap_xfer_done(host, data); 520 } 521 522 static void 523 mmc_omap_dma_timer(unsigned long data) 524 { 525 struct mmc_omap_host *host = (struct mmc_omap_host *) data; 526 527 BUG_ON(host->dma_ch < 0); 528 omap_free_dma(host->dma_ch); 529 host->dma_ch = -1; 530 } 531 532 static void 533 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data) 534 { 535 unsigned long flags; 536 int done; 537 538 done = 0; 539 spin_lock_irqsave(&host->dma_lock, flags); 540 if (host->brs_received) 541 done = 1; 542 else 543 host->dma_done = 1; 544 spin_unlock_irqrestore(&host->dma_lock, flags); 545 if (done) 546 mmc_omap_xfer_done(host, data); 547 } 548 549 static void 550 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd) 551 { 552 host->cmd = NULL; 553 554 del_timer(&host->cmd_abort_timer); 555 556 if (cmd->flags & MMC_RSP_PRESENT) { 557 if (cmd->flags & MMC_RSP_136) { 558 /* response type 2 */ 559 cmd->resp[3] = 560 OMAP_MMC_READ(host, RSP0) | 561 (OMAP_MMC_READ(host, RSP1) << 16); 562 cmd->resp[2] = 563 OMAP_MMC_READ(host, RSP2) | 564 (OMAP_MMC_READ(host, RSP3) << 16); 565 cmd->resp[1] = 566 OMAP_MMC_READ(host, RSP4) | 567 (OMAP_MMC_READ(host, RSP5) << 16); 568 cmd->resp[0] = 569 OMAP_MMC_READ(host, RSP6) | 570 (OMAP_MMC_READ(host, RSP7) << 16); 571 } else { 572 /* response types 1, 1b, 3, 4, 5, 6 */ 573 cmd->resp[0] = 574 OMAP_MMC_READ(host, RSP6) | 575 (OMAP_MMC_READ(host, RSP7) << 16); 576 } 577 } 578 579 if (host->data == NULL || cmd->error) { 580 struct mmc_host *mmc; 581 582 if (host->data != NULL) 583 mmc_omap_abort_xfer(host, host->data); 584 host->mrq = NULL; 585 mmc = host->mmc; 586 mmc_omap_release_slot(host->current_slot, 1); 587 mmc_request_done(mmc, cmd->mrq); 588 } 589 } 590 591 /* 592 * Abort stuck command. Can occur when card is removed while it is being 593 * read. 594 */ 595 static void mmc_omap_abort_command(struct work_struct *work) 596 { 597 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, 598 cmd_abort_work); 599 BUG_ON(!host->cmd); 600 601 dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n", 602 host->cmd->opcode); 603 604 if (host->cmd->error == 0) 605 host->cmd->error = -ETIMEDOUT; 606 607 if (host->data == NULL) { 608 struct mmc_command *cmd; 609 struct mmc_host *mmc; 610 611 cmd = host->cmd; 612 host->cmd = NULL; 613 mmc_omap_send_abort(host, 10000); 614 615 host->mrq = NULL; 616 mmc = host->mmc; 617 mmc_omap_release_slot(host->current_slot, 1); 618 mmc_request_done(mmc, cmd->mrq); 619 } else 620 mmc_omap_cmd_done(host, host->cmd); 621 622 host->abort = 0; 623 enable_irq(host->irq); 624 } 625 626 static void 627 mmc_omap_cmd_timer(unsigned long data) 628 { 629 struct mmc_omap_host *host = (struct mmc_omap_host *) data; 630 unsigned long flags; 631 632 spin_lock_irqsave(&host->slot_lock, flags); 633 if (host->cmd != NULL && !host->abort) { 634 OMAP_MMC_WRITE(host, IE, 0); 635 disable_irq(host->irq); 636 host->abort = 1; 637 schedule_work(&host->cmd_abort_work); 638 } 639 spin_unlock_irqrestore(&host->slot_lock, flags); 640 } 641 642 /* PIO only */ 643 static void 644 mmc_omap_sg_to_buf(struct mmc_omap_host *host) 645 { 646 struct scatterlist *sg; 647 648 sg = host->data->sg + host->sg_idx; 649 host->buffer_bytes_left = sg->length; 650 host->buffer = sg_virt(sg); 651 if (host->buffer_bytes_left > host->total_bytes_left) 652 host->buffer_bytes_left = host->total_bytes_left; 653 } 654 655 static void 656 mmc_omap_clk_timer(unsigned long data) 657 { 658 struct mmc_omap_host *host = (struct mmc_omap_host *) data; 659 660 mmc_omap_fclk_enable(host, 0); 661 } 662 663 /* PIO only */ 664 static void 665 mmc_omap_xfer_data(struct mmc_omap_host *host, int write) 666 { 667 int n; 668 669 if (host->buffer_bytes_left == 0) { 670 host->sg_idx++; 671 BUG_ON(host->sg_idx == host->sg_len); 672 mmc_omap_sg_to_buf(host); 673 } 674 n = 64; 675 if (n > host->buffer_bytes_left) 676 n = host->buffer_bytes_left; 677 host->buffer_bytes_left -= n; 678 host->total_bytes_left -= n; 679 host->data->bytes_xfered += n; 680 681 if (write) { 682 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n); 683 } else { 684 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n); 685 } 686 } 687 688 static inline void mmc_omap_report_irq(u16 status) 689 { 690 static const char *mmc_omap_status_bits[] = { 691 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO", 692 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR" 693 }; 694 int i, c = 0; 695 696 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++) 697 if (status & (1 << i)) { 698 if (c) 699 printk(" "); 700 printk("%s", mmc_omap_status_bits[i]); 701 c++; 702 } 703 } 704 705 static irqreturn_t mmc_omap_irq(int irq, void *dev_id) 706 { 707 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id; 708 u16 status; 709 int end_command; 710 int end_transfer; 711 int transfer_error, cmd_error; 712 713 if (host->cmd == NULL && host->data == NULL) { 714 status = OMAP_MMC_READ(host, STAT); 715 dev_info(mmc_dev(host->slots[0]->mmc), 716 "Spurious IRQ 0x%04x\n", status); 717 if (status != 0) { 718 OMAP_MMC_WRITE(host, STAT, status); 719 OMAP_MMC_WRITE(host, IE, 0); 720 } 721 return IRQ_HANDLED; 722 } 723 724 end_command = 0; 725 end_transfer = 0; 726 transfer_error = 0; 727 cmd_error = 0; 728 729 while ((status = OMAP_MMC_READ(host, STAT)) != 0) { 730 int cmd; 731 732 OMAP_MMC_WRITE(host, STAT, status); 733 if (host->cmd != NULL) 734 cmd = host->cmd->opcode; 735 else 736 cmd = -1; 737 #ifdef CONFIG_MMC_DEBUG 738 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ", 739 status, cmd); 740 mmc_omap_report_irq(status); 741 printk("\n"); 742 #endif 743 if (host->total_bytes_left) { 744 if ((status & OMAP_MMC_STAT_A_FULL) || 745 (status & OMAP_MMC_STAT_END_OF_DATA)) 746 mmc_omap_xfer_data(host, 0); 747 if (status & OMAP_MMC_STAT_A_EMPTY) 748 mmc_omap_xfer_data(host, 1); 749 } 750 751 if (status & OMAP_MMC_STAT_END_OF_DATA) 752 end_transfer = 1; 753 754 if (status & OMAP_MMC_STAT_DATA_TOUT) { 755 dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n", 756 cmd); 757 if (host->data) { 758 host->data->error = -ETIMEDOUT; 759 transfer_error = 1; 760 } 761 } 762 763 if (status & OMAP_MMC_STAT_DATA_CRC) { 764 if (host->data) { 765 host->data->error = -EILSEQ; 766 dev_dbg(mmc_dev(host->mmc), 767 "data CRC error, bytes left %d\n", 768 host->total_bytes_left); 769 transfer_error = 1; 770 } else { 771 dev_dbg(mmc_dev(host->mmc), "data CRC error\n"); 772 } 773 } 774 775 if (status & OMAP_MMC_STAT_CMD_TOUT) { 776 /* Timeouts are routine with some commands */ 777 if (host->cmd) { 778 struct mmc_omap_slot *slot = 779 host->current_slot; 780 if (slot == NULL || 781 !mmc_omap_cover_is_open(slot)) 782 dev_err(mmc_dev(host->mmc), 783 "command timeout (CMD%d)\n", 784 cmd); 785 host->cmd->error = -ETIMEDOUT; 786 end_command = 1; 787 cmd_error = 1; 788 } 789 } 790 791 if (status & OMAP_MMC_STAT_CMD_CRC) { 792 if (host->cmd) { 793 dev_err(mmc_dev(host->mmc), 794 "command CRC error (CMD%d, arg 0x%08x)\n", 795 cmd, host->cmd->arg); 796 host->cmd->error = -EILSEQ; 797 end_command = 1; 798 cmd_error = 1; 799 } else 800 dev_err(mmc_dev(host->mmc), 801 "command CRC error without cmd?\n"); 802 } 803 804 if (status & OMAP_MMC_STAT_CARD_ERR) { 805 dev_dbg(mmc_dev(host->mmc), 806 "ignoring card status error (CMD%d)\n", 807 cmd); 808 end_command = 1; 809 } 810 811 /* 812 * NOTE: On 1610 the END_OF_CMD may come too early when 813 * starting a write 814 */ 815 if ((status & OMAP_MMC_STAT_END_OF_CMD) && 816 (!(status & OMAP_MMC_STAT_A_EMPTY))) { 817 end_command = 1; 818 } 819 } 820 821 if (cmd_error && host->data) { 822 del_timer(&host->cmd_abort_timer); 823 host->abort = 1; 824 OMAP_MMC_WRITE(host, IE, 0); 825 disable_irq_nosync(host->irq); 826 schedule_work(&host->cmd_abort_work); 827 return IRQ_HANDLED; 828 } 829 830 if (end_command) 831 mmc_omap_cmd_done(host, host->cmd); 832 if (host->data != NULL) { 833 if (transfer_error) 834 mmc_omap_xfer_done(host, host->data); 835 else if (end_transfer) 836 mmc_omap_end_of_data(host, host->data); 837 } 838 839 return IRQ_HANDLED; 840 } 841 842 void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed) 843 { 844 int cover_open; 845 struct mmc_omap_host *host = dev_get_drvdata(dev); 846 struct mmc_omap_slot *slot = host->slots[num]; 847 848 BUG_ON(num >= host->nr_slots); 849 850 /* Other subsystems can call in here before we're initialised. */ 851 if (host->nr_slots == 0 || !host->slots[num]) 852 return; 853 854 cover_open = mmc_omap_cover_is_open(slot); 855 if (cover_open != slot->cover_open) { 856 slot->cover_open = cover_open; 857 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch"); 858 } 859 860 tasklet_hi_schedule(&slot->cover_tasklet); 861 } 862 863 static void mmc_omap_cover_timer(unsigned long arg) 864 { 865 struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg; 866 tasklet_schedule(&slot->cover_tasklet); 867 } 868 869 static void mmc_omap_cover_handler(unsigned long param) 870 { 871 struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param; 872 int cover_open = mmc_omap_cover_is_open(slot); 873 874 mmc_detect_change(slot->mmc, 0); 875 if (!cover_open) 876 return; 877 878 /* 879 * If no card is inserted, we postpone polling until 880 * the cover has been closed. 881 */ 882 if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card)) 883 return; 884 885 mod_timer(&slot->cover_timer, 886 jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY)); 887 } 888 889 /* Prepare to transfer the next segment of a scatterlist */ 890 static void 891 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data) 892 { 893 int dma_ch = host->dma_ch; 894 unsigned long data_addr; 895 u16 buf, frame; 896 u32 count; 897 struct scatterlist *sg = &data->sg[host->sg_idx]; 898 int src_port = 0; 899 int dst_port = 0; 900 int sync_dev = 0; 901 902 data_addr = host->phys_base + OMAP_MMC_REG_DATA; 903 frame = data->blksz; 904 count = sg_dma_len(sg); 905 906 if ((data->blocks == 1) && (count > data->blksz)) 907 count = frame; 908 909 host->dma_len = count; 910 911 /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx. 912 * Use 16 or 32 word frames when the blocksize is at least that large. 913 * Blocksize is usually 512 bytes; but not for some SD reads. 914 */ 915 if (cpu_is_omap15xx() && frame > 32) 916 frame = 32; 917 else if (frame > 64) 918 frame = 64; 919 count /= frame; 920 frame >>= 1; 921 922 if (!(data->flags & MMC_DATA_WRITE)) { 923 buf = 0x800f | ((frame - 1) << 8); 924 925 if (cpu_class_is_omap1()) { 926 src_port = OMAP_DMA_PORT_TIPB; 927 dst_port = OMAP_DMA_PORT_EMIFF; 928 } 929 if (cpu_is_omap24xx()) 930 sync_dev = OMAP24XX_DMA_MMC1_RX; 931 932 omap_set_dma_src_params(dma_ch, src_port, 933 OMAP_DMA_AMODE_CONSTANT, 934 data_addr, 0, 0); 935 omap_set_dma_dest_params(dma_ch, dst_port, 936 OMAP_DMA_AMODE_POST_INC, 937 sg_dma_address(sg), 0, 0); 938 omap_set_dma_dest_data_pack(dma_ch, 1); 939 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4); 940 } else { 941 buf = 0x0f80 | ((frame - 1) << 0); 942 943 if (cpu_class_is_omap1()) { 944 src_port = OMAP_DMA_PORT_EMIFF; 945 dst_port = OMAP_DMA_PORT_TIPB; 946 } 947 if (cpu_is_omap24xx()) 948 sync_dev = OMAP24XX_DMA_MMC1_TX; 949 950 omap_set_dma_dest_params(dma_ch, dst_port, 951 OMAP_DMA_AMODE_CONSTANT, 952 data_addr, 0, 0); 953 omap_set_dma_src_params(dma_ch, src_port, 954 OMAP_DMA_AMODE_POST_INC, 955 sg_dma_address(sg), 0, 0); 956 omap_set_dma_src_data_pack(dma_ch, 1); 957 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4); 958 } 959 960 /* Max limit for DMA frame count is 0xffff */ 961 BUG_ON(count > 0xffff); 962 963 OMAP_MMC_WRITE(host, BUF, buf); 964 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16, 965 frame, count, OMAP_DMA_SYNC_FRAME, 966 sync_dev, 0); 967 } 968 969 /* A scatterlist segment completed */ 970 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data) 971 { 972 struct mmc_omap_host *host = (struct mmc_omap_host *) data; 973 struct mmc_data *mmcdat = host->data; 974 975 if (unlikely(host->dma_ch < 0)) { 976 dev_err(mmc_dev(host->mmc), 977 "DMA callback while DMA not enabled\n"); 978 return; 979 } 980 /* FIXME: We really should do something to _handle_ the errors */ 981 if (ch_status & OMAP1_DMA_TOUT_IRQ) { 982 dev_err(mmc_dev(host->mmc),"DMA timeout\n"); 983 return; 984 } 985 if (ch_status & OMAP_DMA_DROP_IRQ) { 986 dev_err(mmc_dev(host->mmc), "DMA sync error\n"); 987 return; 988 } 989 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) { 990 return; 991 } 992 mmcdat->bytes_xfered += host->dma_len; 993 host->sg_idx++; 994 if (host->sg_idx < host->sg_len) { 995 mmc_omap_prepare_dma(host, host->data); 996 omap_start_dma(host->dma_ch); 997 } else 998 mmc_omap_dma_done(host, host->data); 999 } 1000 1001 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data) 1002 { 1003 const char *dma_dev_name; 1004 int sync_dev, dma_ch, is_read, r; 1005 1006 is_read = !(data->flags & MMC_DATA_WRITE); 1007 del_timer_sync(&host->dma_timer); 1008 if (host->dma_ch >= 0) { 1009 if (is_read == host->dma_is_read) 1010 return 0; 1011 omap_free_dma(host->dma_ch); 1012 host->dma_ch = -1; 1013 } 1014 1015 if (is_read) { 1016 if (host->id == 0) { 1017 sync_dev = OMAP_DMA_MMC_RX; 1018 dma_dev_name = "MMC1 read"; 1019 } else { 1020 sync_dev = OMAP_DMA_MMC2_RX; 1021 dma_dev_name = "MMC2 read"; 1022 } 1023 } else { 1024 if (host->id == 0) { 1025 sync_dev = OMAP_DMA_MMC_TX; 1026 dma_dev_name = "MMC1 write"; 1027 } else { 1028 sync_dev = OMAP_DMA_MMC2_TX; 1029 dma_dev_name = "MMC2 write"; 1030 } 1031 } 1032 r = omap_request_dma(sync_dev, dma_dev_name, mmc_omap_dma_cb, 1033 host, &dma_ch); 1034 if (r != 0) { 1035 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r); 1036 return r; 1037 } 1038 host->dma_ch = dma_ch; 1039 host->dma_is_read = is_read; 1040 1041 return 0; 1042 } 1043 1044 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req) 1045 { 1046 u16 reg; 1047 1048 reg = OMAP_MMC_READ(host, SDIO); 1049 reg &= ~(1 << 5); 1050 OMAP_MMC_WRITE(host, SDIO, reg); 1051 /* Set maximum timeout */ 1052 OMAP_MMC_WRITE(host, CTO, 0xff); 1053 } 1054 1055 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req) 1056 { 1057 unsigned int timeout, cycle_ns; 1058 u16 reg; 1059 1060 cycle_ns = 1000000000 / host->current_slot->fclk_freq; 1061 timeout = req->data->timeout_ns / cycle_ns; 1062 timeout += req->data->timeout_clks; 1063 1064 /* Check if we need to use timeout multiplier register */ 1065 reg = OMAP_MMC_READ(host, SDIO); 1066 if (timeout > 0xffff) { 1067 reg |= (1 << 5); 1068 timeout /= 1024; 1069 } else 1070 reg &= ~(1 << 5); 1071 OMAP_MMC_WRITE(host, SDIO, reg); 1072 OMAP_MMC_WRITE(host, DTO, timeout); 1073 } 1074 1075 static void 1076 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req) 1077 { 1078 struct mmc_data *data = req->data; 1079 int i, use_dma, block_size; 1080 unsigned sg_len; 1081 1082 host->data = data; 1083 if (data == NULL) { 1084 OMAP_MMC_WRITE(host, BLEN, 0); 1085 OMAP_MMC_WRITE(host, NBLK, 0); 1086 OMAP_MMC_WRITE(host, BUF, 0); 1087 host->dma_in_use = 0; 1088 set_cmd_timeout(host, req); 1089 return; 1090 } 1091 1092 block_size = data->blksz; 1093 1094 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1); 1095 OMAP_MMC_WRITE(host, BLEN, block_size - 1); 1096 set_data_timeout(host, req); 1097 1098 /* cope with calling layer confusion; it issues "single 1099 * block" writes using multi-block scatterlists. 1100 */ 1101 sg_len = (data->blocks == 1) ? 1 : data->sg_len; 1102 1103 /* Only do DMA for entire blocks */ 1104 use_dma = host->use_dma; 1105 if (use_dma) { 1106 for (i = 0; i < sg_len; i++) { 1107 if ((data->sg[i].length % block_size) != 0) { 1108 use_dma = 0; 1109 break; 1110 } 1111 } 1112 } 1113 1114 host->sg_idx = 0; 1115 if (use_dma) { 1116 if (mmc_omap_get_dma_channel(host, data) == 0) { 1117 enum dma_data_direction dma_data_dir; 1118 1119 if (data->flags & MMC_DATA_WRITE) 1120 dma_data_dir = DMA_TO_DEVICE; 1121 else 1122 dma_data_dir = DMA_FROM_DEVICE; 1123 1124 host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, 1125 sg_len, dma_data_dir); 1126 host->total_bytes_left = 0; 1127 mmc_omap_prepare_dma(host, req->data); 1128 host->brs_received = 0; 1129 host->dma_done = 0; 1130 host->dma_in_use = 1; 1131 } else 1132 use_dma = 0; 1133 } 1134 1135 /* Revert to PIO? */ 1136 if (!use_dma) { 1137 OMAP_MMC_WRITE(host, BUF, 0x1f1f); 1138 host->total_bytes_left = data->blocks * block_size; 1139 host->sg_len = sg_len; 1140 mmc_omap_sg_to_buf(host); 1141 host->dma_in_use = 0; 1142 } 1143 } 1144 1145 static void mmc_omap_start_request(struct mmc_omap_host *host, 1146 struct mmc_request *req) 1147 { 1148 BUG_ON(host->mrq != NULL); 1149 1150 host->mrq = req; 1151 1152 /* only touch fifo AFTER the controller readies it */ 1153 mmc_omap_prepare_data(host, req); 1154 mmc_omap_start_command(host, req->cmd); 1155 if (host->dma_in_use) 1156 omap_start_dma(host->dma_ch); 1157 BUG_ON(irqs_disabled()); 1158 } 1159 1160 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req) 1161 { 1162 struct mmc_omap_slot *slot = mmc_priv(mmc); 1163 struct mmc_omap_host *host = slot->host; 1164 unsigned long flags; 1165 1166 spin_lock_irqsave(&host->slot_lock, flags); 1167 if (host->mmc != NULL) { 1168 BUG_ON(slot->mrq != NULL); 1169 slot->mrq = req; 1170 spin_unlock_irqrestore(&host->slot_lock, flags); 1171 return; 1172 } else 1173 host->mmc = mmc; 1174 spin_unlock_irqrestore(&host->slot_lock, flags); 1175 mmc_omap_select_slot(slot, 1); 1176 mmc_omap_start_request(host, req); 1177 } 1178 1179 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on, 1180 int vdd) 1181 { 1182 struct mmc_omap_host *host; 1183 1184 host = slot->host; 1185 1186 if (slot->pdata->set_power != NULL) 1187 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on, 1188 vdd); 1189 1190 if (cpu_is_omap24xx()) { 1191 u16 w; 1192 1193 if (power_on) { 1194 w = OMAP_MMC_READ(host, CON); 1195 OMAP_MMC_WRITE(host, CON, w | (1 << 11)); 1196 } else { 1197 w = OMAP_MMC_READ(host, CON); 1198 OMAP_MMC_WRITE(host, CON, w & ~(1 << 11)); 1199 } 1200 } 1201 } 1202 1203 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios) 1204 { 1205 struct mmc_omap_slot *slot = mmc_priv(mmc); 1206 struct mmc_omap_host *host = slot->host; 1207 int func_clk_rate = clk_get_rate(host->fclk); 1208 int dsor; 1209 1210 if (ios->clock == 0) 1211 return 0; 1212 1213 dsor = func_clk_rate / ios->clock; 1214 if (dsor < 1) 1215 dsor = 1; 1216 1217 if (func_clk_rate / dsor > ios->clock) 1218 dsor++; 1219 1220 if (dsor > 250) 1221 dsor = 250; 1222 1223 slot->fclk_freq = func_clk_rate / dsor; 1224 1225 if (ios->bus_width == MMC_BUS_WIDTH_4) 1226 dsor |= 1 << 15; 1227 1228 return dsor; 1229 } 1230 1231 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1232 { 1233 struct mmc_omap_slot *slot = mmc_priv(mmc); 1234 struct mmc_omap_host *host = slot->host; 1235 int i, dsor; 1236 int clk_enabled; 1237 1238 mmc_omap_select_slot(slot, 0); 1239 1240 dsor = mmc_omap_calc_divisor(mmc, ios); 1241 1242 if (ios->vdd != slot->vdd) 1243 slot->vdd = ios->vdd; 1244 1245 clk_enabled = 0; 1246 switch (ios->power_mode) { 1247 case MMC_POWER_OFF: 1248 mmc_omap_set_power(slot, 0, ios->vdd); 1249 break; 1250 case MMC_POWER_UP: 1251 /* Cannot touch dsor yet, just power up MMC */ 1252 mmc_omap_set_power(slot, 1, ios->vdd); 1253 goto exit; 1254 case MMC_POWER_ON: 1255 mmc_omap_fclk_enable(host, 1); 1256 clk_enabled = 1; 1257 dsor |= 1 << 11; 1258 break; 1259 } 1260 1261 if (slot->bus_mode != ios->bus_mode) { 1262 if (slot->pdata->set_bus_mode != NULL) 1263 slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id, 1264 ios->bus_mode); 1265 slot->bus_mode = ios->bus_mode; 1266 } 1267 1268 /* On insanely high arm_per frequencies something sometimes 1269 * goes somehow out of sync, and the POW bit is not being set, 1270 * which results in the while loop below getting stuck. 1271 * Writing to the CON register twice seems to do the trick. */ 1272 for (i = 0; i < 2; i++) 1273 OMAP_MMC_WRITE(host, CON, dsor); 1274 slot->saved_con = dsor; 1275 if (ios->power_mode == MMC_POWER_ON) { 1276 /* worst case at 400kHz, 80 cycles makes 200 microsecs */ 1277 int usecs = 250; 1278 1279 /* Send clock cycles, poll completion */ 1280 OMAP_MMC_WRITE(host, IE, 0); 1281 OMAP_MMC_WRITE(host, STAT, 0xffff); 1282 OMAP_MMC_WRITE(host, CMD, 1 << 7); 1283 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) { 1284 udelay(1); 1285 usecs--; 1286 } 1287 OMAP_MMC_WRITE(host, STAT, 1); 1288 } 1289 1290 exit: 1291 mmc_omap_release_slot(slot, clk_enabled); 1292 } 1293 1294 static const struct mmc_host_ops mmc_omap_ops = { 1295 .request = mmc_omap_request, 1296 .set_ios = mmc_omap_set_ios, 1297 }; 1298 1299 static int __init mmc_omap_new_slot(struct mmc_omap_host *host, int id) 1300 { 1301 struct mmc_omap_slot *slot = NULL; 1302 struct mmc_host *mmc; 1303 int r; 1304 1305 mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev); 1306 if (mmc == NULL) 1307 return -ENOMEM; 1308 1309 slot = mmc_priv(mmc); 1310 slot->host = host; 1311 slot->mmc = mmc; 1312 slot->id = id; 1313 slot->pdata = &host->pdata->slots[id]; 1314 1315 host->slots[id] = slot; 1316 1317 mmc->caps = 0; 1318 if (host->pdata->slots[id].wires >= 4) 1319 mmc->caps |= MMC_CAP_4_BIT_DATA; 1320 1321 mmc->ops = &mmc_omap_ops; 1322 mmc->f_min = 400000; 1323 1324 if (cpu_class_is_omap2()) 1325 mmc->f_max = 48000000; 1326 else 1327 mmc->f_max = 24000000; 1328 if (host->pdata->max_freq) 1329 mmc->f_max = min(host->pdata->max_freq, mmc->f_max); 1330 mmc->ocr_avail = slot->pdata->ocr_mask; 1331 1332 /* Use scatterlist DMA to reduce per-transfer costs. 1333 * NOTE max_seg_size assumption that small blocks aren't 1334 * normally used (except e.g. for reading SD registers). 1335 */ 1336 mmc->max_phys_segs = 32; 1337 mmc->max_hw_segs = 32; 1338 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */ 1339 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */ 1340 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1341 mmc->max_seg_size = mmc->max_req_size; 1342 1343 r = mmc_add_host(mmc); 1344 if (r < 0) 1345 goto err_remove_host; 1346 1347 if (slot->pdata->name != NULL) { 1348 r = device_create_file(&mmc->class_dev, 1349 &dev_attr_slot_name); 1350 if (r < 0) 1351 goto err_remove_host; 1352 } 1353 1354 if (slot->pdata->get_cover_state != NULL) { 1355 r = device_create_file(&mmc->class_dev, 1356 &dev_attr_cover_switch); 1357 if (r < 0) 1358 goto err_remove_slot_name; 1359 1360 setup_timer(&slot->cover_timer, mmc_omap_cover_timer, 1361 (unsigned long)slot); 1362 tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler, 1363 (unsigned long)slot); 1364 tasklet_schedule(&slot->cover_tasklet); 1365 } 1366 1367 return 0; 1368 1369 err_remove_slot_name: 1370 if (slot->pdata->name != NULL) 1371 device_remove_file(&mmc->class_dev, &dev_attr_slot_name); 1372 err_remove_host: 1373 mmc_remove_host(mmc); 1374 mmc_free_host(mmc); 1375 return r; 1376 } 1377 1378 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot) 1379 { 1380 struct mmc_host *mmc = slot->mmc; 1381 1382 if (slot->pdata->name != NULL) 1383 device_remove_file(&mmc->class_dev, &dev_attr_slot_name); 1384 if (slot->pdata->get_cover_state != NULL) 1385 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch); 1386 1387 tasklet_kill(&slot->cover_tasklet); 1388 del_timer_sync(&slot->cover_timer); 1389 flush_scheduled_work(); 1390 1391 mmc_remove_host(mmc); 1392 mmc_free_host(mmc); 1393 } 1394 1395 static int __init mmc_omap_probe(struct platform_device *pdev) 1396 { 1397 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 1398 struct mmc_omap_host *host = NULL; 1399 struct resource *res; 1400 int i, ret = 0; 1401 int irq; 1402 1403 if (pdata == NULL) { 1404 dev_err(&pdev->dev, "platform data missing\n"); 1405 return -ENXIO; 1406 } 1407 if (pdata->nr_slots == 0) { 1408 dev_err(&pdev->dev, "no slots\n"); 1409 return -ENXIO; 1410 } 1411 1412 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1413 irq = platform_get_irq(pdev, 0); 1414 if (res == NULL || irq < 0) 1415 return -ENXIO; 1416 1417 res = request_mem_region(res->start, res->end - res->start + 1, 1418 pdev->name); 1419 if (res == NULL) 1420 return -EBUSY; 1421 1422 host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL); 1423 if (host == NULL) { 1424 ret = -ENOMEM; 1425 goto err_free_mem_region; 1426 } 1427 1428 INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work); 1429 INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work); 1430 1431 INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command); 1432 setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer, 1433 (unsigned long) host); 1434 1435 spin_lock_init(&host->clk_lock); 1436 setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host); 1437 1438 spin_lock_init(&host->dma_lock); 1439 setup_timer(&host->dma_timer, mmc_omap_dma_timer, (unsigned long) host); 1440 spin_lock_init(&host->slot_lock); 1441 init_waitqueue_head(&host->slot_wq); 1442 1443 host->pdata = pdata; 1444 host->dev = &pdev->dev; 1445 platform_set_drvdata(pdev, host); 1446 1447 host->id = pdev->id; 1448 host->mem_res = res; 1449 host->irq = irq; 1450 1451 host->use_dma = 1; 1452 host->dev->dma_mask = &pdata->dma_mask; 1453 host->dma_ch = -1; 1454 1455 host->irq = irq; 1456 host->phys_base = host->mem_res->start; 1457 host->virt_base = ioremap(res->start, res->end - res->start + 1); 1458 if (!host->virt_base) 1459 goto err_ioremap; 1460 1461 host->iclk = clk_get(&pdev->dev, "ick"); 1462 if (IS_ERR(host->iclk)) { 1463 ret = PTR_ERR(host->iclk); 1464 goto err_free_mmc_host; 1465 } 1466 clk_enable(host->iclk); 1467 1468 host->fclk = clk_get(&pdev->dev, "fck"); 1469 if (IS_ERR(host->fclk)) { 1470 ret = PTR_ERR(host->fclk); 1471 goto err_free_iclk; 1472 } 1473 1474 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host); 1475 if (ret) 1476 goto err_free_fclk; 1477 1478 if (pdata->init != NULL) { 1479 ret = pdata->init(&pdev->dev); 1480 if (ret < 0) 1481 goto err_free_irq; 1482 } 1483 1484 host->nr_slots = pdata->nr_slots; 1485 for (i = 0; i < pdata->nr_slots; i++) { 1486 ret = mmc_omap_new_slot(host, i); 1487 if (ret < 0) { 1488 while (--i >= 0) 1489 mmc_omap_remove_slot(host->slots[i]); 1490 1491 goto err_plat_cleanup; 1492 } 1493 } 1494 1495 return 0; 1496 1497 err_plat_cleanup: 1498 if (pdata->cleanup) 1499 pdata->cleanup(&pdev->dev); 1500 err_free_irq: 1501 free_irq(host->irq, host); 1502 err_free_fclk: 1503 clk_put(host->fclk); 1504 err_free_iclk: 1505 clk_disable(host->iclk); 1506 clk_put(host->iclk); 1507 err_free_mmc_host: 1508 iounmap(host->virt_base); 1509 err_ioremap: 1510 kfree(host); 1511 err_free_mem_region: 1512 release_mem_region(res->start, res->end - res->start + 1); 1513 return ret; 1514 } 1515 1516 static int mmc_omap_remove(struct platform_device *pdev) 1517 { 1518 struct mmc_omap_host *host = platform_get_drvdata(pdev); 1519 int i; 1520 1521 platform_set_drvdata(pdev, NULL); 1522 1523 BUG_ON(host == NULL); 1524 1525 for (i = 0; i < host->nr_slots; i++) 1526 mmc_omap_remove_slot(host->slots[i]); 1527 1528 if (host->pdata->cleanup) 1529 host->pdata->cleanup(&pdev->dev); 1530 1531 mmc_omap_fclk_enable(host, 0); 1532 free_irq(host->irq, host); 1533 clk_put(host->fclk); 1534 clk_disable(host->iclk); 1535 clk_put(host->iclk); 1536 1537 iounmap(host->virt_base); 1538 release_mem_region(pdev->resource[0].start, 1539 pdev->resource[0].end - pdev->resource[0].start + 1); 1540 1541 kfree(host); 1542 1543 return 0; 1544 } 1545 1546 #ifdef CONFIG_PM 1547 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg) 1548 { 1549 int i, ret = 0; 1550 struct mmc_omap_host *host = platform_get_drvdata(pdev); 1551 1552 if (host == NULL || host->suspended) 1553 return 0; 1554 1555 for (i = 0; i < host->nr_slots; i++) { 1556 struct mmc_omap_slot *slot; 1557 1558 slot = host->slots[i]; 1559 ret = mmc_suspend_host(slot->mmc, mesg); 1560 if (ret < 0) { 1561 while (--i >= 0) { 1562 slot = host->slots[i]; 1563 mmc_resume_host(slot->mmc); 1564 } 1565 return ret; 1566 } 1567 } 1568 host->suspended = 1; 1569 return 0; 1570 } 1571 1572 static int mmc_omap_resume(struct platform_device *pdev) 1573 { 1574 int i, ret = 0; 1575 struct mmc_omap_host *host = platform_get_drvdata(pdev); 1576 1577 if (host == NULL || !host->suspended) 1578 return 0; 1579 1580 for (i = 0; i < host->nr_slots; i++) { 1581 struct mmc_omap_slot *slot; 1582 slot = host->slots[i]; 1583 ret = mmc_resume_host(slot->mmc); 1584 if (ret < 0) 1585 return ret; 1586 1587 host->suspended = 0; 1588 } 1589 return 0; 1590 } 1591 #else 1592 #define mmc_omap_suspend NULL 1593 #define mmc_omap_resume NULL 1594 #endif 1595 1596 static struct platform_driver mmc_omap_driver = { 1597 .remove = mmc_omap_remove, 1598 .suspend = mmc_omap_suspend, 1599 .resume = mmc_omap_resume, 1600 .driver = { 1601 .name = DRIVER_NAME, 1602 .owner = THIS_MODULE, 1603 }, 1604 }; 1605 1606 static int __init mmc_omap_init(void) 1607 { 1608 return platform_driver_probe(&mmc_omap_driver, mmc_omap_probe); 1609 } 1610 1611 static void __exit mmc_omap_exit(void) 1612 { 1613 platform_driver_unregister(&mmc_omap_driver); 1614 } 1615 1616 module_init(mmc_omap_init); 1617 module_exit(mmc_omap_exit); 1618 1619 MODULE_DESCRIPTION("OMAP Multimedia Card driver"); 1620 MODULE_LICENSE("GPL"); 1621 MODULE_ALIAS("platform:" DRIVER_NAME); 1622 MODULE_AUTHOR("Juha Yrj�l�"); 1623