1 /* 2 * Portions copyright (C) 2003 Russell King, PXA MMCI Driver 3 * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver 4 * 5 * Copyright 2008 Embedded Alley Solutions, Inc. 6 * Copyright 2009-2011 Freescale Semiconductor, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, write to the Free Software Foundation, Inc., 20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 21 */ 22 23 #include <linux/kernel.h> 24 #include <linux/init.h> 25 #include <linux/ioport.h> 26 #include <linux/of.h> 27 #include <linux/of_device.h> 28 #include <linux/of_gpio.h> 29 #include <linux/platform_device.h> 30 #include <linux/delay.h> 31 #include <linux/interrupt.h> 32 #include <linux/dma-mapping.h> 33 #include <linux/dmaengine.h> 34 #include <linux/highmem.h> 35 #include <linux/clk.h> 36 #include <linux/err.h> 37 #include <linux/completion.h> 38 #include <linux/mmc/host.h> 39 #include <linux/mmc/mmc.h> 40 #include <linux/mmc/sdio.h> 41 #include <linux/gpio.h> 42 #include <linux/regulator/consumer.h> 43 #include <linux/module.h> 44 #include <linux/pinctrl/consumer.h> 45 #include <linux/stmp_device.h> 46 #include <linux/spi/mxs-spi.h> 47 48 #define DRIVER_NAME "mxs-mmc" 49 50 #define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \ 51 BM_SSP_CTRL1_RESP_ERR_IRQ | \ 52 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \ 53 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \ 54 BM_SSP_CTRL1_DATA_CRC_IRQ | \ 55 BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \ 56 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \ 57 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ) 58 59 /* card detect polling timeout */ 60 #define MXS_MMC_DETECT_TIMEOUT (HZ/2) 61 62 struct mxs_mmc_host { 63 struct mxs_ssp ssp; 64 65 struct mmc_host *mmc; 66 struct mmc_request *mrq; 67 struct mmc_command *cmd; 68 struct mmc_data *data; 69 70 unsigned char bus_width; 71 spinlock_t lock; 72 int sdio_irq_en; 73 int wp_gpio; 74 bool wp_inverted; 75 }; 76 77 static int mxs_mmc_get_ro(struct mmc_host *mmc) 78 { 79 struct mxs_mmc_host *host = mmc_priv(mmc); 80 int ret; 81 82 if (!gpio_is_valid(host->wp_gpio)) 83 return -EINVAL; 84 85 ret = gpio_get_value(host->wp_gpio); 86 87 if (host->wp_inverted) 88 ret = !ret; 89 90 return ret; 91 } 92 93 static int mxs_mmc_get_cd(struct mmc_host *mmc) 94 { 95 struct mxs_mmc_host *host = mmc_priv(mmc); 96 struct mxs_ssp *ssp = &host->ssp; 97 98 return !(readl(ssp->base + HW_SSP_STATUS(ssp)) & 99 BM_SSP_STATUS_CARD_DETECT); 100 } 101 102 static void mxs_mmc_reset(struct mxs_mmc_host *host) 103 { 104 struct mxs_ssp *ssp = &host->ssp; 105 u32 ctrl0, ctrl1; 106 107 stmp_reset_block(ssp->base); 108 109 ctrl0 = BM_SSP_CTRL0_IGNORE_CRC; 110 ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) | 111 BF_SSP(0x7, CTRL1_WORD_LENGTH) | 112 BM_SSP_CTRL1_DMA_ENABLE | 113 BM_SSP_CTRL1_POLARITY | 114 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN | 115 BM_SSP_CTRL1_DATA_CRC_IRQ_EN | 116 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN | 117 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN | 118 BM_SSP_CTRL1_RESP_ERR_IRQ_EN; 119 120 writel(BF_SSP(0xffff, TIMING_TIMEOUT) | 121 BF_SSP(2, TIMING_CLOCK_DIVIDE) | 122 BF_SSP(0, TIMING_CLOCK_RATE), 123 ssp->base + HW_SSP_TIMING(ssp)); 124 125 if (host->sdio_irq_en) { 126 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 127 ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN; 128 } 129 130 writel(ctrl0, ssp->base + HW_SSP_CTRL0); 131 writel(ctrl1, ssp->base + HW_SSP_CTRL1(ssp)); 132 } 133 134 static void mxs_mmc_start_cmd(struct mxs_mmc_host *host, 135 struct mmc_command *cmd); 136 137 static void mxs_mmc_request_done(struct mxs_mmc_host *host) 138 { 139 struct mmc_command *cmd = host->cmd; 140 struct mmc_data *data = host->data; 141 struct mmc_request *mrq = host->mrq; 142 struct mxs_ssp *ssp = &host->ssp; 143 144 if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) { 145 if (mmc_resp_type(cmd) & MMC_RSP_136) { 146 cmd->resp[3] = readl(ssp->base + HW_SSP_SDRESP0(ssp)); 147 cmd->resp[2] = readl(ssp->base + HW_SSP_SDRESP1(ssp)); 148 cmd->resp[1] = readl(ssp->base + HW_SSP_SDRESP2(ssp)); 149 cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP3(ssp)); 150 } else { 151 cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP0(ssp)); 152 } 153 } 154 155 if (data) { 156 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 157 data->sg_len, ssp->dma_dir); 158 /* 159 * If there was an error on any block, we mark all 160 * data blocks as being in error. 161 */ 162 if (!data->error) 163 data->bytes_xfered = data->blocks * data->blksz; 164 else 165 data->bytes_xfered = 0; 166 167 host->data = NULL; 168 if (mrq->stop) { 169 mxs_mmc_start_cmd(host, mrq->stop); 170 return; 171 } 172 } 173 174 host->mrq = NULL; 175 mmc_request_done(host->mmc, mrq); 176 } 177 178 static void mxs_mmc_dma_irq_callback(void *param) 179 { 180 struct mxs_mmc_host *host = param; 181 182 mxs_mmc_request_done(host); 183 } 184 185 static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id) 186 { 187 struct mxs_mmc_host *host = dev_id; 188 struct mmc_command *cmd = host->cmd; 189 struct mmc_data *data = host->data; 190 struct mxs_ssp *ssp = &host->ssp; 191 u32 stat; 192 193 spin_lock(&host->lock); 194 195 stat = readl(ssp->base + HW_SSP_CTRL1(ssp)); 196 writel(stat & MXS_MMC_IRQ_BITS, 197 ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR); 198 199 spin_unlock(&host->lock); 200 201 if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN)) 202 mmc_signal_sdio_irq(host->mmc); 203 204 if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ) 205 cmd->error = -ETIMEDOUT; 206 else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ) 207 cmd->error = -EIO; 208 209 if (data) { 210 if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | 211 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ)) 212 data->error = -ETIMEDOUT; 213 else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ) 214 data->error = -EILSEQ; 215 else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | 216 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)) 217 data->error = -EIO; 218 } 219 220 return IRQ_HANDLED; 221 } 222 223 static struct dma_async_tx_descriptor *mxs_mmc_prep_dma( 224 struct mxs_mmc_host *host, unsigned long flags) 225 { 226 struct mxs_ssp *ssp = &host->ssp; 227 struct dma_async_tx_descriptor *desc; 228 struct mmc_data *data = host->data; 229 struct scatterlist * sgl; 230 unsigned int sg_len; 231 232 if (data) { 233 /* data */ 234 dma_map_sg(mmc_dev(host->mmc), data->sg, 235 data->sg_len, ssp->dma_dir); 236 sgl = data->sg; 237 sg_len = data->sg_len; 238 } else { 239 /* pio */ 240 sgl = (struct scatterlist *) ssp->ssp_pio_words; 241 sg_len = SSP_PIO_NUM; 242 } 243 244 desc = dmaengine_prep_slave_sg(ssp->dmach, 245 sgl, sg_len, ssp->slave_dirn, flags); 246 if (desc) { 247 desc->callback = mxs_mmc_dma_irq_callback; 248 desc->callback_param = host; 249 } else { 250 if (data) 251 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 252 data->sg_len, ssp->dma_dir); 253 } 254 255 return desc; 256 } 257 258 static void mxs_mmc_bc(struct mxs_mmc_host *host) 259 { 260 struct mxs_ssp *ssp = &host->ssp; 261 struct mmc_command *cmd = host->cmd; 262 struct dma_async_tx_descriptor *desc; 263 u32 ctrl0, cmd0, cmd1; 264 265 ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC; 266 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC; 267 cmd1 = cmd->arg; 268 269 if (host->sdio_irq_en) { 270 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 271 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 272 } 273 274 ssp->ssp_pio_words[0] = ctrl0; 275 ssp->ssp_pio_words[1] = cmd0; 276 ssp->ssp_pio_words[2] = cmd1; 277 ssp->dma_dir = DMA_NONE; 278 ssp->slave_dirn = DMA_TRANS_NONE; 279 desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK); 280 if (!desc) 281 goto out; 282 283 dmaengine_submit(desc); 284 dma_async_issue_pending(ssp->dmach); 285 return; 286 287 out: 288 dev_warn(mmc_dev(host->mmc), 289 "%s: failed to prep dma\n", __func__); 290 } 291 292 static void mxs_mmc_ac(struct mxs_mmc_host *host) 293 { 294 struct mxs_ssp *ssp = &host->ssp; 295 struct mmc_command *cmd = host->cmd; 296 struct dma_async_tx_descriptor *desc; 297 u32 ignore_crc, get_resp, long_resp; 298 u32 ctrl0, cmd0, cmd1; 299 300 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ? 301 0 : BM_SSP_CTRL0_IGNORE_CRC; 302 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ? 303 BM_SSP_CTRL0_GET_RESP : 0; 304 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ? 305 BM_SSP_CTRL0_LONG_RESP : 0; 306 307 ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp; 308 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD); 309 cmd1 = cmd->arg; 310 311 if (host->sdio_irq_en) { 312 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 313 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 314 } 315 316 ssp->ssp_pio_words[0] = ctrl0; 317 ssp->ssp_pio_words[1] = cmd0; 318 ssp->ssp_pio_words[2] = cmd1; 319 ssp->dma_dir = DMA_NONE; 320 ssp->slave_dirn = DMA_TRANS_NONE; 321 desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK); 322 if (!desc) 323 goto out; 324 325 dmaengine_submit(desc); 326 dma_async_issue_pending(ssp->dmach); 327 return; 328 329 out: 330 dev_warn(mmc_dev(host->mmc), 331 "%s: failed to prep dma\n", __func__); 332 } 333 334 static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns) 335 { 336 const unsigned int ssp_timeout_mul = 4096; 337 /* 338 * Calculate ticks in ms since ns are large numbers 339 * and might overflow 340 */ 341 const unsigned int clock_per_ms = clock_rate / 1000; 342 const unsigned int ms = ns / 1000; 343 const unsigned int ticks = ms * clock_per_ms; 344 const unsigned int ssp_ticks = ticks / ssp_timeout_mul; 345 346 WARN_ON(ssp_ticks == 0); 347 return ssp_ticks; 348 } 349 350 static void mxs_mmc_adtc(struct mxs_mmc_host *host) 351 { 352 struct mmc_command *cmd = host->cmd; 353 struct mmc_data *data = cmd->data; 354 struct dma_async_tx_descriptor *desc; 355 struct scatterlist *sgl = data->sg, *sg; 356 unsigned int sg_len = data->sg_len; 357 unsigned int i; 358 359 unsigned short dma_data_dir, timeout; 360 enum dma_transfer_direction slave_dirn; 361 unsigned int data_size = 0, log2_blksz; 362 unsigned int blocks = data->blocks; 363 364 struct mxs_ssp *ssp = &host->ssp; 365 366 u32 ignore_crc, get_resp, long_resp, read; 367 u32 ctrl0, cmd0, cmd1, val; 368 369 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ? 370 0 : BM_SSP_CTRL0_IGNORE_CRC; 371 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ? 372 BM_SSP_CTRL0_GET_RESP : 0; 373 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ? 374 BM_SSP_CTRL0_LONG_RESP : 0; 375 376 if (data->flags & MMC_DATA_WRITE) { 377 dma_data_dir = DMA_TO_DEVICE; 378 slave_dirn = DMA_MEM_TO_DEV; 379 read = 0; 380 } else { 381 dma_data_dir = DMA_FROM_DEVICE; 382 slave_dirn = DMA_DEV_TO_MEM; 383 read = BM_SSP_CTRL0_READ; 384 } 385 386 ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) | 387 ignore_crc | get_resp | long_resp | 388 BM_SSP_CTRL0_DATA_XFER | read | 389 BM_SSP_CTRL0_WAIT_FOR_IRQ | 390 BM_SSP_CTRL0_ENABLE; 391 392 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD); 393 394 /* get logarithm to base 2 of block size for setting register */ 395 log2_blksz = ilog2(data->blksz); 396 397 /* 398 * take special care of the case that data size from data->sg 399 * is not equal to blocks x blksz 400 */ 401 for_each_sg(sgl, sg, sg_len, i) 402 data_size += sg->length; 403 404 if (data_size != data->blocks * data->blksz) 405 blocks = 1; 406 407 /* xfer count, block size and count need to be set differently */ 408 if (ssp_is_old(ssp)) { 409 ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT); 410 cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) | 411 BF_SSP(blocks - 1, CMD0_BLOCK_COUNT); 412 } else { 413 writel(data_size, ssp->base + HW_SSP_XFER_SIZE); 414 writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) | 415 BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT), 416 ssp->base + HW_SSP_BLOCK_SIZE); 417 } 418 419 if ((cmd->opcode == MMC_STOP_TRANSMISSION) || 420 (cmd->opcode == SD_IO_RW_EXTENDED)) 421 cmd0 |= BM_SSP_CMD0_APPEND_8CYC; 422 423 cmd1 = cmd->arg; 424 425 if (host->sdio_irq_en) { 426 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 427 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 428 } 429 430 /* set the timeout count */ 431 timeout = mxs_ns_to_ssp_ticks(ssp->clk_rate, data->timeout_ns); 432 val = readl(ssp->base + HW_SSP_TIMING(ssp)); 433 val &= ~(BM_SSP_TIMING_TIMEOUT); 434 val |= BF_SSP(timeout, TIMING_TIMEOUT); 435 writel(val, ssp->base + HW_SSP_TIMING(ssp)); 436 437 /* pio */ 438 ssp->ssp_pio_words[0] = ctrl0; 439 ssp->ssp_pio_words[1] = cmd0; 440 ssp->ssp_pio_words[2] = cmd1; 441 ssp->dma_dir = DMA_NONE; 442 ssp->slave_dirn = DMA_TRANS_NONE; 443 desc = mxs_mmc_prep_dma(host, 0); 444 if (!desc) 445 goto out; 446 447 /* append data sg */ 448 WARN_ON(host->data != NULL); 449 host->data = data; 450 ssp->dma_dir = dma_data_dir; 451 ssp->slave_dirn = slave_dirn; 452 desc = mxs_mmc_prep_dma(host, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 453 if (!desc) 454 goto out; 455 456 dmaengine_submit(desc); 457 dma_async_issue_pending(ssp->dmach); 458 return; 459 out: 460 dev_warn(mmc_dev(host->mmc), 461 "%s: failed to prep dma\n", __func__); 462 } 463 464 static void mxs_mmc_start_cmd(struct mxs_mmc_host *host, 465 struct mmc_command *cmd) 466 { 467 host->cmd = cmd; 468 469 switch (mmc_cmd_type(cmd)) { 470 case MMC_CMD_BC: 471 mxs_mmc_bc(host); 472 break; 473 case MMC_CMD_BCR: 474 mxs_mmc_ac(host); 475 break; 476 case MMC_CMD_AC: 477 mxs_mmc_ac(host); 478 break; 479 case MMC_CMD_ADTC: 480 mxs_mmc_adtc(host); 481 break; 482 default: 483 dev_warn(mmc_dev(host->mmc), 484 "%s: unknown MMC command\n", __func__); 485 break; 486 } 487 } 488 489 static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 490 { 491 struct mxs_mmc_host *host = mmc_priv(mmc); 492 493 WARN_ON(host->mrq != NULL); 494 host->mrq = mrq; 495 mxs_mmc_start_cmd(host, mrq->cmd); 496 } 497 498 static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 499 { 500 struct mxs_mmc_host *host = mmc_priv(mmc); 501 502 if (ios->bus_width == MMC_BUS_WIDTH_8) 503 host->bus_width = 2; 504 else if (ios->bus_width == MMC_BUS_WIDTH_4) 505 host->bus_width = 1; 506 else 507 host->bus_width = 0; 508 509 if (ios->clock) 510 mxs_ssp_set_clk_rate(&host->ssp, ios->clock); 511 } 512 513 static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 514 { 515 struct mxs_mmc_host *host = mmc_priv(mmc); 516 struct mxs_ssp *ssp = &host->ssp; 517 unsigned long flags; 518 519 spin_lock_irqsave(&host->lock, flags); 520 521 host->sdio_irq_en = enable; 522 523 if (enable) { 524 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, 525 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); 526 writel(BM_SSP_CTRL1_SDIO_IRQ_EN, 527 ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_SET); 528 } else { 529 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, 530 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); 531 writel(BM_SSP_CTRL1_SDIO_IRQ_EN, 532 ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR); 533 } 534 535 spin_unlock_irqrestore(&host->lock, flags); 536 537 if (enable && readl(ssp->base + HW_SSP_STATUS(ssp)) & 538 BM_SSP_STATUS_SDIO_IRQ) 539 mmc_signal_sdio_irq(host->mmc); 540 541 } 542 543 static const struct mmc_host_ops mxs_mmc_ops = { 544 .request = mxs_mmc_request, 545 .get_ro = mxs_mmc_get_ro, 546 .get_cd = mxs_mmc_get_cd, 547 .set_ios = mxs_mmc_set_ios, 548 .enable_sdio_irq = mxs_mmc_enable_sdio_irq, 549 }; 550 551 static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param) 552 { 553 struct mxs_mmc_host *host = param; 554 struct mxs_ssp *ssp = &host->ssp; 555 556 if (!mxs_dma_is_apbh(chan)) 557 return false; 558 559 if (chan->chan_id != ssp->dma_channel) 560 return false; 561 562 chan->private = &ssp->dma_data; 563 564 return true; 565 } 566 567 static struct platform_device_id mxs_ssp_ids[] = { 568 { 569 .name = "imx23-mmc", 570 .driver_data = IMX23_SSP, 571 }, { 572 .name = "imx28-mmc", 573 .driver_data = IMX28_SSP, 574 }, { 575 /* sentinel */ 576 } 577 }; 578 MODULE_DEVICE_TABLE(platform, mxs_ssp_ids); 579 580 static const struct of_device_id mxs_mmc_dt_ids[] = { 581 { .compatible = "fsl,imx23-mmc", .data = (void *) IMX23_SSP, }, 582 { .compatible = "fsl,imx28-mmc", .data = (void *) IMX28_SSP, }, 583 { /* sentinel */ } 584 }; 585 MODULE_DEVICE_TABLE(of, mxs_mmc_dt_ids); 586 587 static int mxs_mmc_probe(struct platform_device *pdev) 588 { 589 const struct of_device_id *of_id = 590 of_match_device(mxs_mmc_dt_ids, &pdev->dev); 591 struct device_node *np = pdev->dev.of_node; 592 struct mxs_mmc_host *host; 593 struct mmc_host *mmc; 594 struct resource *iores, *dmares; 595 struct pinctrl *pinctrl; 596 int ret = 0, irq_err, irq_dma; 597 dma_cap_mask_t mask; 598 struct regulator *reg_vmmc; 599 enum of_gpio_flags flags; 600 struct mxs_ssp *ssp; 601 u32 bus_width = 0; 602 603 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 604 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0); 605 irq_err = platform_get_irq(pdev, 0); 606 irq_dma = platform_get_irq(pdev, 1); 607 if (!iores || irq_err < 0 || irq_dma < 0) 608 return -EINVAL; 609 610 mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev); 611 if (!mmc) 612 return -ENOMEM; 613 614 host = mmc_priv(mmc); 615 ssp = &host->ssp; 616 ssp->dev = &pdev->dev; 617 ssp->base = devm_request_and_ioremap(&pdev->dev, iores); 618 if (!ssp->base) { 619 ret = -EADDRNOTAVAIL; 620 goto out_mmc_free; 621 } 622 623 if (np) { 624 ssp->devid = (enum mxs_ssp_id) of_id->data; 625 /* 626 * TODO: This is a temporary solution and should be changed 627 * to use generic DMA binding later when the helpers get in. 628 */ 629 ret = of_property_read_u32(np, "fsl,ssp-dma-channel", 630 &ssp->dma_channel); 631 if (ret) { 632 dev_err(mmc_dev(host->mmc), 633 "failed to get dma channel\n"); 634 goto out_mmc_free; 635 } 636 } else { 637 ssp->devid = pdev->id_entry->driver_data; 638 ssp->dma_channel = dmares->start; 639 } 640 641 host->mmc = mmc; 642 host->sdio_irq_en = 0; 643 644 reg_vmmc = devm_regulator_get(&pdev->dev, "vmmc"); 645 if (!IS_ERR(reg_vmmc)) { 646 ret = regulator_enable(reg_vmmc); 647 if (ret) { 648 dev_err(&pdev->dev, 649 "Failed to enable vmmc regulator: %d\n", ret); 650 goto out_mmc_free; 651 } 652 } 653 654 pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 655 if (IS_ERR(pinctrl)) { 656 ret = PTR_ERR(pinctrl); 657 goto out_mmc_free; 658 } 659 660 ssp->clk = clk_get(&pdev->dev, NULL); 661 if (IS_ERR(ssp->clk)) { 662 ret = PTR_ERR(ssp->clk); 663 goto out_mmc_free; 664 } 665 clk_prepare_enable(ssp->clk); 666 667 mxs_mmc_reset(host); 668 669 dma_cap_zero(mask); 670 dma_cap_set(DMA_SLAVE, mask); 671 ssp->dma_data.chan_irq = irq_dma; 672 ssp->dmach = dma_request_channel(mask, mxs_mmc_dma_filter, host); 673 if (!ssp->dmach) { 674 dev_err(mmc_dev(host->mmc), 675 "%s: failed to request dma\n", __func__); 676 goto out_clk_put; 677 } 678 679 /* set mmc core parameters */ 680 mmc->ops = &mxs_mmc_ops; 681 mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 682 MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL; 683 684 of_property_read_u32(np, "bus-width", &bus_width); 685 if (bus_width == 4) 686 mmc->caps |= MMC_CAP_4_BIT_DATA; 687 else if (bus_width == 8) 688 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA; 689 host->wp_gpio = of_get_named_gpio_flags(np, "wp-gpios", 0, &flags); 690 691 if (flags & OF_GPIO_ACTIVE_LOW) 692 host->wp_inverted = 1; 693 694 mmc->f_min = 400000; 695 mmc->f_max = 288000000; 696 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 697 698 mmc->max_segs = 52; 699 mmc->max_blk_size = 1 << 0xf; 700 mmc->max_blk_count = (ssp_is_old(ssp)) ? 0xff : 0xffffff; 701 mmc->max_req_size = (ssp_is_old(ssp)) ? 0xffff : 0xffffffff; 702 mmc->max_seg_size = dma_get_max_seg_size(ssp->dmach->device->dev); 703 704 platform_set_drvdata(pdev, mmc); 705 706 ret = devm_request_irq(&pdev->dev, irq_err, mxs_mmc_irq_handler, 0, 707 DRIVER_NAME, host); 708 if (ret) 709 goto out_free_dma; 710 711 spin_lock_init(&host->lock); 712 713 ret = mmc_add_host(mmc); 714 if (ret) 715 goto out_free_dma; 716 717 dev_info(mmc_dev(host->mmc), "initialized\n"); 718 719 return 0; 720 721 out_free_dma: 722 if (ssp->dmach) 723 dma_release_channel(ssp->dmach); 724 out_clk_put: 725 clk_disable_unprepare(ssp->clk); 726 clk_put(ssp->clk); 727 out_mmc_free: 728 mmc_free_host(mmc); 729 return ret; 730 } 731 732 static int mxs_mmc_remove(struct platform_device *pdev) 733 { 734 struct mmc_host *mmc = platform_get_drvdata(pdev); 735 struct mxs_mmc_host *host = mmc_priv(mmc); 736 struct mxs_ssp *ssp = &host->ssp; 737 738 mmc_remove_host(mmc); 739 740 platform_set_drvdata(pdev, NULL); 741 742 if (ssp->dmach) 743 dma_release_channel(ssp->dmach); 744 745 clk_disable_unprepare(ssp->clk); 746 clk_put(ssp->clk); 747 748 mmc_free_host(mmc); 749 750 return 0; 751 } 752 753 #ifdef CONFIG_PM 754 static int mxs_mmc_suspend(struct device *dev) 755 { 756 struct mmc_host *mmc = dev_get_drvdata(dev); 757 struct mxs_mmc_host *host = mmc_priv(mmc); 758 struct mxs_ssp *ssp = &host->ssp; 759 int ret = 0; 760 761 ret = mmc_suspend_host(mmc); 762 763 clk_disable_unprepare(ssp->clk); 764 765 return ret; 766 } 767 768 static int mxs_mmc_resume(struct device *dev) 769 { 770 struct mmc_host *mmc = dev_get_drvdata(dev); 771 struct mxs_mmc_host *host = mmc_priv(mmc); 772 struct mxs_ssp *ssp = &host->ssp; 773 int ret = 0; 774 775 clk_prepare_enable(ssp->clk); 776 777 ret = mmc_resume_host(mmc); 778 779 return ret; 780 } 781 782 static const struct dev_pm_ops mxs_mmc_pm_ops = { 783 .suspend = mxs_mmc_suspend, 784 .resume = mxs_mmc_resume, 785 }; 786 #endif 787 788 static struct platform_driver mxs_mmc_driver = { 789 .probe = mxs_mmc_probe, 790 .remove = mxs_mmc_remove, 791 .id_table = mxs_ssp_ids, 792 .driver = { 793 .name = DRIVER_NAME, 794 .owner = THIS_MODULE, 795 #ifdef CONFIG_PM 796 .pm = &mxs_mmc_pm_ops, 797 #endif 798 .of_match_table = mxs_mmc_dt_ids, 799 }, 800 }; 801 802 module_platform_driver(mxs_mmc_driver); 803 804 MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral"); 805 MODULE_AUTHOR("Freescale Semiconductor"); 806 MODULE_LICENSE("GPL"); 807 MODULE_ALIAS("platform:" DRIVER_NAME); 808