1 /* 2 * Portions copyright (C) 2003 Russell King, PXA MMCI Driver 3 * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver 4 * 5 * Copyright 2008 Embedded Alley Solutions, Inc. 6 * Copyright 2009-2011 Freescale Semiconductor, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, write to the Free Software Foundation, Inc., 20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 21 */ 22 23 #include <linux/kernel.h> 24 #include <linux/init.h> 25 #include <linux/ioport.h> 26 #include <linux/of.h> 27 #include <linux/of_device.h> 28 #include <linux/of_gpio.h> 29 #include <linux/platform_device.h> 30 #include <linux/delay.h> 31 #include <linux/interrupt.h> 32 #include <linux/dma-mapping.h> 33 #include <linux/dmaengine.h> 34 #include <linux/highmem.h> 35 #include <linux/clk.h> 36 #include <linux/err.h> 37 #include <linux/completion.h> 38 #include <linux/mmc/host.h> 39 #include <linux/mmc/mmc.h> 40 #include <linux/mmc/sdio.h> 41 #include <linux/gpio.h> 42 #include <linux/regulator/consumer.h> 43 #include <linux/module.h> 44 #include <linux/pinctrl/consumer.h> 45 #include <linux/stmp_device.h> 46 #include <linux/spi/mxs-spi.h> 47 48 #define DRIVER_NAME "mxs-mmc" 49 50 #define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \ 51 BM_SSP_CTRL1_RESP_ERR_IRQ | \ 52 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \ 53 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \ 54 BM_SSP_CTRL1_DATA_CRC_IRQ | \ 55 BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \ 56 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \ 57 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ) 58 59 /* card detect polling timeout */ 60 #define MXS_MMC_DETECT_TIMEOUT (HZ/2) 61 62 struct mxs_mmc_host { 63 struct mxs_ssp ssp; 64 65 struct mmc_host *mmc; 66 struct mmc_request *mrq; 67 struct mmc_command *cmd; 68 struct mmc_data *data; 69 70 unsigned char bus_width; 71 spinlock_t lock; 72 int sdio_irq_en; 73 int wp_gpio; 74 bool wp_inverted; 75 bool cd_inverted; 76 bool broken_cd; 77 bool non_removable; 78 }; 79 80 static int mxs_mmc_get_ro(struct mmc_host *mmc) 81 { 82 struct mxs_mmc_host *host = mmc_priv(mmc); 83 int ret; 84 85 if (!gpio_is_valid(host->wp_gpio)) 86 return -EINVAL; 87 88 ret = gpio_get_value(host->wp_gpio); 89 90 if (host->wp_inverted) 91 ret = !ret; 92 93 return ret; 94 } 95 96 static int mxs_mmc_get_cd(struct mmc_host *mmc) 97 { 98 struct mxs_mmc_host *host = mmc_priv(mmc); 99 struct mxs_ssp *ssp = &host->ssp; 100 101 return host->non_removable || host->broken_cd || 102 !(readl(ssp->base + HW_SSP_STATUS(ssp)) & 103 BM_SSP_STATUS_CARD_DETECT) ^ host->cd_inverted; 104 } 105 106 static void mxs_mmc_reset(struct mxs_mmc_host *host) 107 { 108 struct mxs_ssp *ssp = &host->ssp; 109 u32 ctrl0, ctrl1; 110 111 stmp_reset_block(ssp->base); 112 113 ctrl0 = BM_SSP_CTRL0_IGNORE_CRC; 114 ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) | 115 BF_SSP(0x7, CTRL1_WORD_LENGTH) | 116 BM_SSP_CTRL1_DMA_ENABLE | 117 BM_SSP_CTRL1_POLARITY | 118 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN | 119 BM_SSP_CTRL1_DATA_CRC_IRQ_EN | 120 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN | 121 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN | 122 BM_SSP_CTRL1_RESP_ERR_IRQ_EN; 123 124 writel(BF_SSP(0xffff, TIMING_TIMEOUT) | 125 BF_SSP(2, TIMING_CLOCK_DIVIDE) | 126 BF_SSP(0, TIMING_CLOCK_RATE), 127 ssp->base + HW_SSP_TIMING(ssp)); 128 129 if (host->sdio_irq_en) { 130 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 131 ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN; 132 } 133 134 writel(ctrl0, ssp->base + HW_SSP_CTRL0); 135 writel(ctrl1, ssp->base + HW_SSP_CTRL1(ssp)); 136 } 137 138 static void mxs_mmc_start_cmd(struct mxs_mmc_host *host, 139 struct mmc_command *cmd); 140 141 static void mxs_mmc_request_done(struct mxs_mmc_host *host) 142 { 143 struct mmc_command *cmd = host->cmd; 144 struct mmc_data *data = host->data; 145 struct mmc_request *mrq = host->mrq; 146 struct mxs_ssp *ssp = &host->ssp; 147 148 if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) { 149 if (mmc_resp_type(cmd) & MMC_RSP_136) { 150 cmd->resp[3] = readl(ssp->base + HW_SSP_SDRESP0(ssp)); 151 cmd->resp[2] = readl(ssp->base + HW_SSP_SDRESP1(ssp)); 152 cmd->resp[1] = readl(ssp->base + HW_SSP_SDRESP2(ssp)); 153 cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP3(ssp)); 154 } else { 155 cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP0(ssp)); 156 } 157 } 158 159 if (data) { 160 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 161 data->sg_len, ssp->dma_dir); 162 /* 163 * If there was an error on any block, we mark all 164 * data blocks as being in error. 165 */ 166 if (!data->error) 167 data->bytes_xfered = data->blocks * data->blksz; 168 else 169 data->bytes_xfered = 0; 170 171 host->data = NULL; 172 if (mrq->stop) { 173 mxs_mmc_start_cmd(host, mrq->stop); 174 return; 175 } 176 } 177 178 host->mrq = NULL; 179 mmc_request_done(host->mmc, mrq); 180 } 181 182 static void mxs_mmc_dma_irq_callback(void *param) 183 { 184 struct mxs_mmc_host *host = param; 185 186 mxs_mmc_request_done(host); 187 } 188 189 static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id) 190 { 191 struct mxs_mmc_host *host = dev_id; 192 struct mmc_command *cmd = host->cmd; 193 struct mmc_data *data = host->data; 194 struct mxs_ssp *ssp = &host->ssp; 195 u32 stat; 196 197 spin_lock(&host->lock); 198 199 stat = readl(ssp->base + HW_SSP_CTRL1(ssp)); 200 writel(stat & MXS_MMC_IRQ_BITS, 201 ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR); 202 203 spin_unlock(&host->lock); 204 205 if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN)) 206 mmc_signal_sdio_irq(host->mmc); 207 208 if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ) 209 cmd->error = -ETIMEDOUT; 210 else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ) 211 cmd->error = -EIO; 212 213 if (data) { 214 if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | 215 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ)) 216 data->error = -ETIMEDOUT; 217 else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ) 218 data->error = -EILSEQ; 219 else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | 220 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)) 221 data->error = -EIO; 222 } 223 224 return IRQ_HANDLED; 225 } 226 227 static struct dma_async_tx_descriptor *mxs_mmc_prep_dma( 228 struct mxs_mmc_host *host, unsigned long flags) 229 { 230 struct mxs_ssp *ssp = &host->ssp; 231 struct dma_async_tx_descriptor *desc; 232 struct mmc_data *data = host->data; 233 struct scatterlist * sgl; 234 unsigned int sg_len; 235 236 if (data) { 237 /* data */ 238 dma_map_sg(mmc_dev(host->mmc), data->sg, 239 data->sg_len, ssp->dma_dir); 240 sgl = data->sg; 241 sg_len = data->sg_len; 242 } else { 243 /* pio */ 244 sgl = (struct scatterlist *) ssp->ssp_pio_words; 245 sg_len = SSP_PIO_NUM; 246 } 247 248 desc = dmaengine_prep_slave_sg(ssp->dmach, 249 sgl, sg_len, ssp->slave_dirn, flags); 250 if (desc) { 251 desc->callback = mxs_mmc_dma_irq_callback; 252 desc->callback_param = host; 253 } else { 254 if (data) 255 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 256 data->sg_len, ssp->dma_dir); 257 } 258 259 return desc; 260 } 261 262 static void mxs_mmc_bc(struct mxs_mmc_host *host) 263 { 264 struct mxs_ssp *ssp = &host->ssp; 265 struct mmc_command *cmd = host->cmd; 266 struct dma_async_tx_descriptor *desc; 267 u32 ctrl0, cmd0, cmd1; 268 269 ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC; 270 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC; 271 cmd1 = cmd->arg; 272 273 if (host->sdio_irq_en) { 274 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 275 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 276 } 277 278 ssp->ssp_pio_words[0] = ctrl0; 279 ssp->ssp_pio_words[1] = cmd0; 280 ssp->ssp_pio_words[2] = cmd1; 281 ssp->dma_dir = DMA_NONE; 282 ssp->slave_dirn = DMA_TRANS_NONE; 283 desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK); 284 if (!desc) 285 goto out; 286 287 dmaengine_submit(desc); 288 dma_async_issue_pending(ssp->dmach); 289 return; 290 291 out: 292 dev_warn(mmc_dev(host->mmc), 293 "%s: failed to prep dma\n", __func__); 294 } 295 296 static void mxs_mmc_ac(struct mxs_mmc_host *host) 297 { 298 struct mxs_ssp *ssp = &host->ssp; 299 struct mmc_command *cmd = host->cmd; 300 struct dma_async_tx_descriptor *desc; 301 u32 ignore_crc, get_resp, long_resp; 302 u32 ctrl0, cmd0, cmd1; 303 304 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ? 305 0 : BM_SSP_CTRL0_IGNORE_CRC; 306 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ? 307 BM_SSP_CTRL0_GET_RESP : 0; 308 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ? 309 BM_SSP_CTRL0_LONG_RESP : 0; 310 311 ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp; 312 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD); 313 cmd1 = cmd->arg; 314 315 if (host->sdio_irq_en) { 316 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 317 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 318 } 319 320 ssp->ssp_pio_words[0] = ctrl0; 321 ssp->ssp_pio_words[1] = cmd0; 322 ssp->ssp_pio_words[2] = cmd1; 323 ssp->dma_dir = DMA_NONE; 324 ssp->slave_dirn = DMA_TRANS_NONE; 325 desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK); 326 if (!desc) 327 goto out; 328 329 dmaengine_submit(desc); 330 dma_async_issue_pending(ssp->dmach); 331 return; 332 333 out: 334 dev_warn(mmc_dev(host->mmc), 335 "%s: failed to prep dma\n", __func__); 336 } 337 338 static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns) 339 { 340 const unsigned int ssp_timeout_mul = 4096; 341 /* 342 * Calculate ticks in ms since ns are large numbers 343 * and might overflow 344 */ 345 const unsigned int clock_per_ms = clock_rate / 1000; 346 const unsigned int ms = ns / 1000; 347 const unsigned int ticks = ms * clock_per_ms; 348 const unsigned int ssp_ticks = ticks / ssp_timeout_mul; 349 350 WARN_ON(ssp_ticks == 0); 351 return ssp_ticks; 352 } 353 354 static void mxs_mmc_adtc(struct mxs_mmc_host *host) 355 { 356 struct mmc_command *cmd = host->cmd; 357 struct mmc_data *data = cmd->data; 358 struct dma_async_tx_descriptor *desc; 359 struct scatterlist *sgl = data->sg, *sg; 360 unsigned int sg_len = data->sg_len; 361 unsigned int i; 362 363 unsigned short dma_data_dir, timeout; 364 enum dma_transfer_direction slave_dirn; 365 unsigned int data_size = 0, log2_blksz; 366 unsigned int blocks = data->blocks; 367 368 struct mxs_ssp *ssp = &host->ssp; 369 370 u32 ignore_crc, get_resp, long_resp, read; 371 u32 ctrl0, cmd0, cmd1, val; 372 373 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ? 374 0 : BM_SSP_CTRL0_IGNORE_CRC; 375 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ? 376 BM_SSP_CTRL0_GET_RESP : 0; 377 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ? 378 BM_SSP_CTRL0_LONG_RESP : 0; 379 380 if (data->flags & MMC_DATA_WRITE) { 381 dma_data_dir = DMA_TO_DEVICE; 382 slave_dirn = DMA_MEM_TO_DEV; 383 read = 0; 384 } else { 385 dma_data_dir = DMA_FROM_DEVICE; 386 slave_dirn = DMA_DEV_TO_MEM; 387 read = BM_SSP_CTRL0_READ; 388 } 389 390 ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) | 391 ignore_crc | get_resp | long_resp | 392 BM_SSP_CTRL0_DATA_XFER | read | 393 BM_SSP_CTRL0_WAIT_FOR_IRQ | 394 BM_SSP_CTRL0_ENABLE; 395 396 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD); 397 398 /* get logarithm to base 2 of block size for setting register */ 399 log2_blksz = ilog2(data->blksz); 400 401 /* 402 * take special care of the case that data size from data->sg 403 * is not equal to blocks x blksz 404 */ 405 for_each_sg(sgl, sg, sg_len, i) 406 data_size += sg->length; 407 408 if (data_size != data->blocks * data->blksz) 409 blocks = 1; 410 411 /* xfer count, block size and count need to be set differently */ 412 if (ssp_is_old(ssp)) { 413 ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT); 414 cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) | 415 BF_SSP(blocks - 1, CMD0_BLOCK_COUNT); 416 } else { 417 writel(data_size, ssp->base + HW_SSP_XFER_SIZE); 418 writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) | 419 BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT), 420 ssp->base + HW_SSP_BLOCK_SIZE); 421 } 422 423 if ((cmd->opcode == MMC_STOP_TRANSMISSION) || 424 (cmd->opcode == SD_IO_RW_EXTENDED)) 425 cmd0 |= BM_SSP_CMD0_APPEND_8CYC; 426 427 cmd1 = cmd->arg; 428 429 if (host->sdio_irq_en) { 430 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 431 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 432 } 433 434 /* set the timeout count */ 435 timeout = mxs_ns_to_ssp_ticks(ssp->clk_rate, data->timeout_ns); 436 val = readl(ssp->base + HW_SSP_TIMING(ssp)); 437 val &= ~(BM_SSP_TIMING_TIMEOUT); 438 val |= BF_SSP(timeout, TIMING_TIMEOUT); 439 writel(val, ssp->base + HW_SSP_TIMING(ssp)); 440 441 /* pio */ 442 ssp->ssp_pio_words[0] = ctrl0; 443 ssp->ssp_pio_words[1] = cmd0; 444 ssp->ssp_pio_words[2] = cmd1; 445 ssp->dma_dir = DMA_NONE; 446 ssp->slave_dirn = DMA_TRANS_NONE; 447 desc = mxs_mmc_prep_dma(host, 0); 448 if (!desc) 449 goto out; 450 451 /* append data sg */ 452 WARN_ON(host->data != NULL); 453 host->data = data; 454 ssp->dma_dir = dma_data_dir; 455 ssp->slave_dirn = slave_dirn; 456 desc = mxs_mmc_prep_dma(host, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 457 if (!desc) 458 goto out; 459 460 dmaengine_submit(desc); 461 dma_async_issue_pending(ssp->dmach); 462 return; 463 out: 464 dev_warn(mmc_dev(host->mmc), 465 "%s: failed to prep dma\n", __func__); 466 } 467 468 static void mxs_mmc_start_cmd(struct mxs_mmc_host *host, 469 struct mmc_command *cmd) 470 { 471 host->cmd = cmd; 472 473 switch (mmc_cmd_type(cmd)) { 474 case MMC_CMD_BC: 475 mxs_mmc_bc(host); 476 break; 477 case MMC_CMD_BCR: 478 mxs_mmc_ac(host); 479 break; 480 case MMC_CMD_AC: 481 mxs_mmc_ac(host); 482 break; 483 case MMC_CMD_ADTC: 484 mxs_mmc_adtc(host); 485 break; 486 default: 487 dev_warn(mmc_dev(host->mmc), 488 "%s: unknown MMC command\n", __func__); 489 break; 490 } 491 } 492 493 static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 494 { 495 struct mxs_mmc_host *host = mmc_priv(mmc); 496 497 WARN_ON(host->mrq != NULL); 498 host->mrq = mrq; 499 mxs_mmc_start_cmd(host, mrq->cmd); 500 } 501 502 static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 503 { 504 struct mxs_mmc_host *host = mmc_priv(mmc); 505 506 if (ios->bus_width == MMC_BUS_WIDTH_8) 507 host->bus_width = 2; 508 else if (ios->bus_width == MMC_BUS_WIDTH_4) 509 host->bus_width = 1; 510 else 511 host->bus_width = 0; 512 513 if (ios->clock) 514 mxs_ssp_set_clk_rate(&host->ssp, ios->clock); 515 } 516 517 static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 518 { 519 struct mxs_mmc_host *host = mmc_priv(mmc); 520 struct mxs_ssp *ssp = &host->ssp; 521 unsigned long flags; 522 523 spin_lock_irqsave(&host->lock, flags); 524 525 host->sdio_irq_en = enable; 526 527 if (enable) { 528 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, 529 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); 530 writel(BM_SSP_CTRL1_SDIO_IRQ_EN, 531 ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_SET); 532 } else { 533 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, 534 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); 535 writel(BM_SSP_CTRL1_SDIO_IRQ_EN, 536 ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR); 537 } 538 539 spin_unlock_irqrestore(&host->lock, flags); 540 541 if (enable && readl(ssp->base + HW_SSP_STATUS(ssp)) & 542 BM_SSP_STATUS_SDIO_IRQ) 543 mmc_signal_sdio_irq(host->mmc); 544 545 } 546 547 static const struct mmc_host_ops mxs_mmc_ops = { 548 .request = mxs_mmc_request, 549 .get_ro = mxs_mmc_get_ro, 550 .get_cd = mxs_mmc_get_cd, 551 .set_ios = mxs_mmc_set_ios, 552 .enable_sdio_irq = mxs_mmc_enable_sdio_irq, 553 }; 554 555 static struct platform_device_id mxs_ssp_ids[] = { 556 { 557 .name = "imx23-mmc", 558 .driver_data = IMX23_SSP, 559 }, { 560 .name = "imx28-mmc", 561 .driver_data = IMX28_SSP, 562 }, { 563 /* sentinel */ 564 } 565 }; 566 MODULE_DEVICE_TABLE(platform, mxs_ssp_ids); 567 568 static const struct of_device_id mxs_mmc_dt_ids[] = { 569 { .compatible = "fsl,imx23-mmc", .data = (void *) IMX23_SSP, }, 570 { .compatible = "fsl,imx28-mmc", .data = (void *) IMX28_SSP, }, 571 { /* sentinel */ } 572 }; 573 MODULE_DEVICE_TABLE(of, mxs_mmc_dt_ids); 574 575 static int mxs_mmc_probe(struct platform_device *pdev) 576 { 577 const struct of_device_id *of_id = 578 of_match_device(mxs_mmc_dt_ids, &pdev->dev); 579 struct device_node *np = pdev->dev.of_node; 580 struct mxs_mmc_host *host; 581 struct mmc_host *mmc; 582 struct resource *iores; 583 struct pinctrl *pinctrl; 584 int ret = 0, irq_err; 585 struct regulator *reg_vmmc; 586 enum of_gpio_flags flags; 587 struct mxs_ssp *ssp; 588 u32 bus_width = 0; 589 590 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 591 irq_err = platform_get_irq(pdev, 0); 592 if (!iores || irq_err < 0) 593 return -EINVAL; 594 595 mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev); 596 if (!mmc) 597 return -ENOMEM; 598 599 host = mmc_priv(mmc); 600 ssp = &host->ssp; 601 ssp->dev = &pdev->dev; 602 ssp->base = devm_ioremap_resource(&pdev->dev, iores); 603 if (IS_ERR(ssp->base)) { 604 ret = PTR_ERR(ssp->base); 605 goto out_mmc_free; 606 } 607 608 ssp->devid = (enum mxs_ssp_id) of_id->data; 609 610 host->mmc = mmc; 611 host->sdio_irq_en = 0; 612 613 reg_vmmc = devm_regulator_get(&pdev->dev, "vmmc"); 614 if (!IS_ERR(reg_vmmc)) { 615 ret = regulator_enable(reg_vmmc); 616 if (ret) { 617 dev_err(&pdev->dev, 618 "Failed to enable vmmc regulator: %d\n", ret); 619 goto out_mmc_free; 620 } 621 } 622 623 pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 624 if (IS_ERR(pinctrl)) { 625 ret = PTR_ERR(pinctrl); 626 goto out_mmc_free; 627 } 628 629 ssp->clk = clk_get(&pdev->dev, NULL); 630 if (IS_ERR(ssp->clk)) { 631 ret = PTR_ERR(ssp->clk); 632 goto out_mmc_free; 633 } 634 clk_prepare_enable(ssp->clk); 635 636 mxs_mmc_reset(host); 637 638 ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx"); 639 if (!ssp->dmach) { 640 dev_err(mmc_dev(host->mmc), 641 "%s: failed to request dma\n", __func__); 642 goto out_clk_put; 643 } 644 645 /* set mmc core parameters */ 646 mmc->ops = &mxs_mmc_ops; 647 mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 648 MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL; 649 650 of_property_read_u32(np, "bus-width", &bus_width); 651 if (bus_width == 4) 652 mmc->caps |= MMC_CAP_4_BIT_DATA; 653 else if (bus_width == 8) 654 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA; 655 host->broken_cd = of_property_read_bool(np, "broken-cd"); 656 host->non_removable = of_property_read_bool(np, "non-removable"); 657 if (host->non_removable) 658 mmc->caps |= MMC_CAP_NONREMOVABLE; 659 host->wp_gpio = of_get_named_gpio_flags(np, "wp-gpios", 0, &flags); 660 if (flags & OF_GPIO_ACTIVE_LOW) 661 host->wp_inverted = 1; 662 663 host->cd_inverted = of_property_read_bool(np, "cd-inverted"); 664 665 mmc->f_min = 400000; 666 mmc->f_max = 288000000; 667 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 668 669 mmc->max_segs = 52; 670 mmc->max_blk_size = 1 << 0xf; 671 mmc->max_blk_count = (ssp_is_old(ssp)) ? 0xff : 0xffffff; 672 mmc->max_req_size = (ssp_is_old(ssp)) ? 0xffff : 0xffffffff; 673 mmc->max_seg_size = dma_get_max_seg_size(ssp->dmach->device->dev); 674 675 platform_set_drvdata(pdev, mmc); 676 677 ret = devm_request_irq(&pdev->dev, irq_err, mxs_mmc_irq_handler, 0, 678 DRIVER_NAME, host); 679 if (ret) 680 goto out_free_dma; 681 682 spin_lock_init(&host->lock); 683 684 ret = mmc_add_host(mmc); 685 if (ret) 686 goto out_free_dma; 687 688 dev_info(mmc_dev(host->mmc), "initialized\n"); 689 690 return 0; 691 692 out_free_dma: 693 if (ssp->dmach) 694 dma_release_channel(ssp->dmach); 695 out_clk_put: 696 clk_disable_unprepare(ssp->clk); 697 clk_put(ssp->clk); 698 out_mmc_free: 699 mmc_free_host(mmc); 700 return ret; 701 } 702 703 static int mxs_mmc_remove(struct platform_device *pdev) 704 { 705 struct mmc_host *mmc = platform_get_drvdata(pdev); 706 struct mxs_mmc_host *host = mmc_priv(mmc); 707 struct mxs_ssp *ssp = &host->ssp; 708 709 mmc_remove_host(mmc); 710 711 platform_set_drvdata(pdev, NULL); 712 713 if (ssp->dmach) 714 dma_release_channel(ssp->dmach); 715 716 clk_disable_unprepare(ssp->clk); 717 clk_put(ssp->clk); 718 719 mmc_free_host(mmc); 720 721 return 0; 722 } 723 724 #ifdef CONFIG_PM 725 static int mxs_mmc_suspend(struct device *dev) 726 { 727 struct mmc_host *mmc = dev_get_drvdata(dev); 728 struct mxs_mmc_host *host = mmc_priv(mmc); 729 struct mxs_ssp *ssp = &host->ssp; 730 int ret = 0; 731 732 ret = mmc_suspend_host(mmc); 733 734 clk_disable_unprepare(ssp->clk); 735 736 return ret; 737 } 738 739 static int mxs_mmc_resume(struct device *dev) 740 { 741 struct mmc_host *mmc = dev_get_drvdata(dev); 742 struct mxs_mmc_host *host = mmc_priv(mmc); 743 struct mxs_ssp *ssp = &host->ssp; 744 int ret = 0; 745 746 clk_prepare_enable(ssp->clk); 747 748 ret = mmc_resume_host(mmc); 749 750 return ret; 751 } 752 753 static const struct dev_pm_ops mxs_mmc_pm_ops = { 754 .suspend = mxs_mmc_suspend, 755 .resume = mxs_mmc_resume, 756 }; 757 #endif 758 759 static struct platform_driver mxs_mmc_driver = { 760 .probe = mxs_mmc_probe, 761 .remove = mxs_mmc_remove, 762 .id_table = mxs_ssp_ids, 763 .driver = { 764 .name = DRIVER_NAME, 765 .owner = THIS_MODULE, 766 #ifdef CONFIG_PM 767 .pm = &mxs_mmc_pm_ops, 768 #endif 769 .of_match_table = mxs_mmc_dt_ids, 770 }, 771 }; 772 773 module_platform_driver(mxs_mmc_driver); 774 775 MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral"); 776 MODULE_AUTHOR("Freescale Semiconductor"); 777 MODULE_LICENSE("GPL"); 778 MODULE_ALIAS("platform:" DRIVER_NAME); 779