1 /* 2 * Portions copyright (C) 2003 Russell King, PXA MMCI Driver 3 * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver 4 * 5 * Copyright 2008 Embedded Alley Solutions, Inc. 6 * Copyright 2009-2011 Freescale Semiconductor, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, write to the Free Software Foundation, Inc., 20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 21 */ 22 23 #include <linux/kernel.h> 24 #include <linux/init.h> 25 #include <linux/ioport.h> 26 #include <linux/of.h> 27 #include <linux/of_device.h> 28 #include <linux/platform_device.h> 29 #include <linux/delay.h> 30 #include <linux/interrupt.h> 31 #include <linux/dma-mapping.h> 32 #include <linux/dmaengine.h> 33 #include <linux/highmem.h> 34 #include <linux/clk.h> 35 #include <linux/err.h> 36 #include <linux/completion.h> 37 #include <linux/mmc/host.h> 38 #include <linux/mmc/mmc.h> 39 #include <linux/mmc/sdio.h> 40 #include <linux/mmc/slot-gpio.h> 41 #include <linux/regulator/consumer.h> 42 #include <linux/module.h> 43 #include <linux/stmp_device.h> 44 #include <linux/spi/mxs-spi.h> 45 46 #define DRIVER_NAME "mxs-mmc" 47 48 #define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \ 49 BM_SSP_CTRL1_RESP_ERR_IRQ | \ 50 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \ 51 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \ 52 BM_SSP_CTRL1_DATA_CRC_IRQ | \ 53 BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \ 54 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \ 55 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ) 56 57 /* card detect polling timeout */ 58 #define MXS_MMC_DETECT_TIMEOUT (HZ/2) 59 60 struct mxs_mmc_host { 61 struct mxs_ssp ssp; 62 63 struct mmc_host *mmc; 64 struct mmc_request *mrq; 65 struct mmc_command *cmd; 66 struct mmc_data *data; 67 68 unsigned char bus_width; 69 spinlock_t lock; 70 int sdio_irq_en; 71 bool broken_cd; 72 }; 73 74 static int mxs_mmc_get_cd(struct mmc_host *mmc) 75 { 76 struct mxs_mmc_host *host = mmc_priv(mmc); 77 struct mxs_ssp *ssp = &host->ssp; 78 int present, ret; 79 80 if (host->broken_cd) 81 return -ENOSYS; 82 83 ret = mmc_gpio_get_cd(mmc); 84 if (ret >= 0) 85 return ret; 86 87 present = mmc->caps & MMC_CAP_NEEDS_POLL || 88 !(readl(ssp->base + HW_SSP_STATUS(ssp)) & 89 BM_SSP_STATUS_CARD_DETECT); 90 91 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) 92 present = !present; 93 94 return present; 95 } 96 97 static int mxs_mmc_reset(struct mxs_mmc_host *host) 98 { 99 struct mxs_ssp *ssp = &host->ssp; 100 u32 ctrl0, ctrl1; 101 int ret; 102 103 ret = stmp_reset_block(ssp->base); 104 if (ret) 105 return ret; 106 107 ctrl0 = BM_SSP_CTRL0_IGNORE_CRC; 108 ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) | 109 BF_SSP(0x7, CTRL1_WORD_LENGTH) | 110 BM_SSP_CTRL1_DMA_ENABLE | 111 BM_SSP_CTRL1_POLARITY | 112 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN | 113 BM_SSP_CTRL1_DATA_CRC_IRQ_EN | 114 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN | 115 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN | 116 BM_SSP_CTRL1_RESP_ERR_IRQ_EN; 117 118 writel(BF_SSP(0xffff, TIMING_TIMEOUT) | 119 BF_SSP(2, TIMING_CLOCK_DIVIDE) | 120 BF_SSP(0, TIMING_CLOCK_RATE), 121 ssp->base + HW_SSP_TIMING(ssp)); 122 123 if (host->sdio_irq_en) { 124 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 125 ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN; 126 } 127 128 writel(ctrl0, ssp->base + HW_SSP_CTRL0); 129 writel(ctrl1, ssp->base + HW_SSP_CTRL1(ssp)); 130 return 0; 131 } 132 133 static void mxs_mmc_start_cmd(struct mxs_mmc_host *host, 134 struct mmc_command *cmd); 135 136 static void mxs_mmc_request_done(struct mxs_mmc_host *host) 137 { 138 struct mmc_command *cmd = host->cmd; 139 struct mmc_data *data = host->data; 140 struct mmc_request *mrq = host->mrq; 141 struct mxs_ssp *ssp = &host->ssp; 142 143 if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) { 144 if (mmc_resp_type(cmd) & MMC_RSP_136) { 145 cmd->resp[3] = readl(ssp->base + HW_SSP_SDRESP0(ssp)); 146 cmd->resp[2] = readl(ssp->base + HW_SSP_SDRESP1(ssp)); 147 cmd->resp[1] = readl(ssp->base + HW_SSP_SDRESP2(ssp)); 148 cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP3(ssp)); 149 } else { 150 cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP0(ssp)); 151 } 152 } 153 154 if (cmd == mrq->sbc) { 155 /* Finished CMD23, now send actual command. */ 156 mxs_mmc_start_cmd(host, mrq->cmd); 157 return; 158 } else if (data) { 159 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 160 data->sg_len, ssp->dma_dir); 161 /* 162 * If there was an error on any block, we mark all 163 * data blocks as being in error. 164 */ 165 if (!data->error) 166 data->bytes_xfered = data->blocks * data->blksz; 167 else 168 data->bytes_xfered = 0; 169 170 host->data = NULL; 171 if (data->stop && (data->error || !mrq->sbc)) { 172 mxs_mmc_start_cmd(host, mrq->stop); 173 return; 174 } 175 } 176 177 host->mrq = NULL; 178 mmc_request_done(host->mmc, mrq); 179 } 180 181 static void mxs_mmc_dma_irq_callback(void *param) 182 { 183 struct mxs_mmc_host *host = param; 184 185 mxs_mmc_request_done(host); 186 } 187 188 static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id) 189 { 190 struct mxs_mmc_host *host = dev_id; 191 struct mmc_command *cmd = host->cmd; 192 struct mmc_data *data = host->data; 193 struct mxs_ssp *ssp = &host->ssp; 194 u32 stat; 195 196 spin_lock(&host->lock); 197 198 stat = readl(ssp->base + HW_SSP_CTRL1(ssp)); 199 writel(stat & MXS_MMC_IRQ_BITS, 200 ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR); 201 202 spin_unlock(&host->lock); 203 204 if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN)) 205 mmc_signal_sdio_irq(host->mmc); 206 207 if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ) 208 cmd->error = -ETIMEDOUT; 209 else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ) 210 cmd->error = -EIO; 211 212 if (data) { 213 if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | 214 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ)) 215 data->error = -ETIMEDOUT; 216 else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ) 217 data->error = -EILSEQ; 218 else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | 219 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)) 220 data->error = -EIO; 221 } 222 223 return IRQ_HANDLED; 224 } 225 226 static struct dma_async_tx_descriptor *mxs_mmc_prep_dma( 227 struct mxs_mmc_host *host, unsigned long flags) 228 { 229 struct mxs_ssp *ssp = &host->ssp; 230 struct dma_async_tx_descriptor *desc; 231 struct mmc_data *data = host->data; 232 struct scatterlist * sgl; 233 unsigned int sg_len; 234 235 if (data) { 236 /* data */ 237 dma_map_sg(mmc_dev(host->mmc), data->sg, 238 data->sg_len, ssp->dma_dir); 239 sgl = data->sg; 240 sg_len = data->sg_len; 241 } else { 242 /* pio */ 243 sgl = (struct scatterlist *) ssp->ssp_pio_words; 244 sg_len = SSP_PIO_NUM; 245 } 246 247 desc = dmaengine_prep_slave_sg(ssp->dmach, 248 sgl, sg_len, ssp->slave_dirn, flags); 249 if (desc) { 250 desc->callback = mxs_mmc_dma_irq_callback; 251 desc->callback_param = host; 252 } else { 253 if (data) 254 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 255 data->sg_len, ssp->dma_dir); 256 } 257 258 return desc; 259 } 260 261 static void mxs_mmc_bc(struct mxs_mmc_host *host) 262 { 263 struct mxs_ssp *ssp = &host->ssp; 264 struct mmc_command *cmd = host->cmd; 265 struct dma_async_tx_descriptor *desc; 266 u32 ctrl0, cmd0, cmd1; 267 268 ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC; 269 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC; 270 cmd1 = cmd->arg; 271 272 if (host->sdio_irq_en) { 273 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 274 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 275 } 276 277 ssp->ssp_pio_words[0] = ctrl0; 278 ssp->ssp_pio_words[1] = cmd0; 279 ssp->ssp_pio_words[2] = cmd1; 280 ssp->dma_dir = DMA_NONE; 281 ssp->slave_dirn = DMA_TRANS_NONE; 282 desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK); 283 if (!desc) 284 goto out; 285 286 dmaengine_submit(desc); 287 dma_async_issue_pending(ssp->dmach); 288 return; 289 290 out: 291 dev_warn(mmc_dev(host->mmc), 292 "%s: failed to prep dma\n", __func__); 293 } 294 295 static void mxs_mmc_ac(struct mxs_mmc_host *host) 296 { 297 struct mxs_ssp *ssp = &host->ssp; 298 struct mmc_command *cmd = host->cmd; 299 struct dma_async_tx_descriptor *desc; 300 u32 ignore_crc, get_resp, long_resp; 301 u32 ctrl0, cmd0, cmd1; 302 303 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ? 304 0 : BM_SSP_CTRL0_IGNORE_CRC; 305 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ? 306 BM_SSP_CTRL0_GET_RESP : 0; 307 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ? 308 BM_SSP_CTRL0_LONG_RESP : 0; 309 310 ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp; 311 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD); 312 cmd1 = cmd->arg; 313 314 if (cmd->opcode == MMC_STOP_TRANSMISSION) 315 cmd0 |= BM_SSP_CMD0_APPEND_8CYC; 316 317 if (host->sdio_irq_en) { 318 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 319 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 320 } 321 322 ssp->ssp_pio_words[0] = ctrl0; 323 ssp->ssp_pio_words[1] = cmd0; 324 ssp->ssp_pio_words[2] = cmd1; 325 ssp->dma_dir = DMA_NONE; 326 ssp->slave_dirn = DMA_TRANS_NONE; 327 desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK); 328 if (!desc) 329 goto out; 330 331 dmaengine_submit(desc); 332 dma_async_issue_pending(ssp->dmach); 333 return; 334 335 out: 336 dev_warn(mmc_dev(host->mmc), 337 "%s: failed to prep dma\n", __func__); 338 } 339 340 static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns) 341 { 342 const unsigned int ssp_timeout_mul = 4096; 343 /* 344 * Calculate ticks in ms since ns are large numbers 345 * and might overflow 346 */ 347 const unsigned int clock_per_ms = clock_rate / 1000; 348 const unsigned int ms = ns / 1000; 349 const unsigned int ticks = ms * clock_per_ms; 350 const unsigned int ssp_ticks = ticks / ssp_timeout_mul; 351 352 WARN_ON(ssp_ticks == 0); 353 return ssp_ticks; 354 } 355 356 static void mxs_mmc_adtc(struct mxs_mmc_host *host) 357 { 358 struct mmc_command *cmd = host->cmd; 359 struct mmc_data *data = cmd->data; 360 struct dma_async_tx_descriptor *desc; 361 struct scatterlist *sgl = data->sg, *sg; 362 unsigned int sg_len = data->sg_len; 363 unsigned int i; 364 365 unsigned short dma_data_dir, timeout; 366 enum dma_transfer_direction slave_dirn; 367 unsigned int data_size = 0, log2_blksz; 368 unsigned int blocks = data->blocks; 369 370 struct mxs_ssp *ssp = &host->ssp; 371 372 u32 ignore_crc, get_resp, long_resp, read; 373 u32 ctrl0, cmd0, cmd1, val; 374 375 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ? 376 0 : BM_SSP_CTRL0_IGNORE_CRC; 377 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ? 378 BM_SSP_CTRL0_GET_RESP : 0; 379 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ? 380 BM_SSP_CTRL0_LONG_RESP : 0; 381 382 if (data->flags & MMC_DATA_WRITE) { 383 dma_data_dir = DMA_TO_DEVICE; 384 slave_dirn = DMA_MEM_TO_DEV; 385 read = 0; 386 } else { 387 dma_data_dir = DMA_FROM_DEVICE; 388 slave_dirn = DMA_DEV_TO_MEM; 389 read = BM_SSP_CTRL0_READ; 390 } 391 392 ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) | 393 ignore_crc | get_resp | long_resp | 394 BM_SSP_CTRL0_DATA_XFER | read | 395 BM_SSP_CTRL0_WAIT_FOR_IRQ | 396 BM_SSP_CTRL0_ENABLE; 397 398 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD); 399 400 /* get logarithm to base 2 of block size for setting register */ 401 log2_blksz = ilog2(data->blksz); 402 403 /* 404 * take special care of the case that data size from data->sg 405 * is not equal to blocks x blksz 406 */ 407 for_each_sg(sgl, sg, sg_len, i) 408 data_size += sg->length; 409 410 if (data_size != data->blocks * data->blksz) 411 blocks = 1; 412 413 /* xfer count, block size and count need to be set differently */ 414 if (ssp_is_old(ssp)) { 415 ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT); 416 cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) | 417 BF_SSP(blocks - 1, CMD0_BLOCK_COUNT); 418 } else { 419 writel(data_size, ssp->base + HW_SSP_XFER_SIZE); 420 writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) | 421 BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT), 422 ssp->base + HW_SSP_BLOCK_SIZE); 423 } 424 425 if (cmd->opcode == SD_IO_RW_EXTENDED) 426 cmd0 |= BM_SSP_CMD0_APPEND_8CYC; 427 428 cmd1 = cmd->arg; 429 430 if (host->sdio_irq_en) { 431 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 432 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 433 } 434 435 /* set the timeout count */ 436 timeout = mxs_ns_to_ssp_ticks(ssp->clk_rate, data->timeout_ns); 437 val = readl(ssp->base + HW_SSP_TIMING(ssp)); 438 val &= ~(BM_SSP_TIMING_TIMEOUT); 439 val |= BF_SSP(timeout, TIMING_TIMEOUT); 440 writel(val, ssp->base + HW_SSP_TIMING(ssp)); 441 442 /* pio */ 443 ssp->ssp_pio_words[0] = ctrl0; 444 ssp->ssp_pio_words[1] = cmd0; 445 ssp->ssp_pio_words[2] = cmd1; 446 ssp->dma_dir = DMA_NONE; 447 ssp->slave_dirn = DMA_TRANS_NONE; 448 desc = mxs_mmc_prep_dma(host, 0); 449 if (!desc) 450 goto out; 451 452 /* append data sg */ 453 WARN_ON(host->data != NULL); 454 host->data = data; 455 ssp->dma_dir = dma_data_dir; 456 ssp->slave_dirn = slave_dirn; 457 desc = mxs_mmc_prep_dma(host, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 458 if (!desc) 459 goto out; 460 461 dmaengine_submit(desc); 462 dma_async_issue_pending(ssp->dmach); 463 return; 464 out: 465 dev_warn(mmc_dev(host->mmc), 466 "%s: failed to prep dma\n", __func__); 467 } 468 469 static void mxs_mmc_start_cmd(struct mxs_mmc_host *host, 470 struct mmc_command *cmd) 471 { 472 host->cmd = cmd; 473 474 switch (mmc_cmd_type(cmd)) { 475 case MMC_CMD_BC: 476 mxs_mmc_bc(host); 477 break; 478 case MMC_CMD_BCR: 479 mxs_mmc_ac(host); 480 break; 481 case MMC_CMD_AC: 482 mxs_mmc_ac(host); 483 break; 484 case MMC_CMD_ADTC: 485 mxs_mmc_adtc(host); 486 break; 487 default: 488 dev_warn(mmc_dev(host->mmc), 489 "%s: unknown MMC command\n", __func__); 490 break; 491 } 492 } 493 494 static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 495 { 496 struct mxs_mmc_host *host = mmc_priv(mmc); 497 498 WARN_ON(host->mrq != NULL); 499 host->mrq = mrq; 500 501 if (mrq->sbc) 502 mxs_mmc_start_cmd(host, mrq->sbc); 503 else 504 mxs_mmc_start_cmd(host, mrq->cmd); 505 } 506 507 static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 508 { 509 struct mxs_mmc_host *host = mmc_priv(mmc); 510 511 if (ios->bus_width == MMC_BUS_WIDTH_8) 512 host->bus_width = 2; 513 else if (ios->bus_width == MMC_BUS_WIDTH_4) 514 host->bus_width = 1; 515 else 516 host->bus_width = 0; 517 518 if (ios->clock) 519 mxs_ssp_set_clk_rate(&host->ssp, ios->clock); 520 } 521 522 static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 523 { 524 struct mxs_mmc_host *host = mmc_priv(mmc); 525 struct mxs_ssp *ssp = &host->ssp; 526 unsigned long flags; 527 528 spin_lock_irqsave(&host->lock, flags); 529 530 host->sdio_irq_en = enable; 531 532 if (enable) { 533 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, 534 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); 535 writel(BM_SSP_CTRL1_SDIO_IRQ_EN, 536 ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_SET); 537 } else { 538 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, 539 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); 540 writel(BM_SSP_CTRL1_SDIO_IRQ_EN, 541 ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR); 542 } 543 544 spin_unlock_irqrestore(&host->lock, flags); 545 546 if (enable && readl(ssp->base + HW_SSP_STATUS(ssp)) & 547 BM_SSP_STATUS_SDIO_IRQ) 548 mmc_signal_sdio_irq(host->mmc); 549 550 } 551 552 static const struct mmc_host_ops mxs_mmc_ops = { 553 .request = mxs_mmc_request, 554 .get_ro = mmc_gpio_get_ro, 555 .get_cd = mxs_mmc_get_cd, 556 .set_ios = mxs_mmc_set_ios, 557 .enable_sdio_irq = mxs_mmc_enable_sdio_irq, 558 }; 559 560 static const struct platform_device_id mxs_ssp_ids[] = { 561 { 562 .name = "imx23-mmc", 563 .driver_data = IMX23_SSP, 564 }, { 565 .name = "imx28-mmc", 566 .driver_data = IMX28_SSP, 567 }, { 568 /* sentinel */ 569 } 570 }; 571 MODULE_DEVICE_TABLE(platform, mxs_ssp_ids); 572 573 static const struct of_device_id mxs_mmc_dt_ids[] = { 574 { .compatible = "fsl,imx23-mmc", .data = (void *) IMX23_SSP, }, 575 { .compatible = "fsl,imx28-mmc", .data = (void *) IMX28_SSP, }, 576 { /* sentinel */ } 577 }; 578 MODULE_DEVICE_TABLE(of, mxs_mmc_dt_ids); 579 580 static int mxs_mmc_probe(struct platform_device *pdev) 581 { 582 const struct of_device_id *of_id = 583 of_match_device(mxs_mmc_dt_ids, &pdev->dev); 584 struct device_node *np = pdev->dev.of_node; 585 struct mxs_mmc_host *host; 586 struct mmc_host *mmc; 587 struct resource *iores; 588 int ret = 0, irq_err; 589 struct regulator *reg_vmmc; 590 struct mxs_ssp *ssp; 591 592 irq_err = platform_get_irq(pdev, 0); 593 if (irq_err < 0) 594 return irq_err; 595 596 mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev); 597 if (!mmc) 598 return -ENOMEM; 599 600 host = mmc_priv(mmc); 601 ssp = &host->ssp; 602 ssp->dev = &pdev->dev; 603 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 604 ssp->base = devm_ioremap_resource(&pdev->dev, iores); 605 if (IS_ERR(ssp->base)) { 606 ret = PTR_ERR(ssp->base); 607 goto out_mmc_free; 608 } 609 610 ssp->devid = (enum mxs_ssp_id) of_id->data; 611 612 host->mmc = mmc; 613 host->sdio_irq_en = 0; 614 615 reg_vmmc = devm_regulator_get(&pdev->dev, "vmmc"); 616 if (!IS_ERR(reg_vmmc)) { 617 ret = regulator_enable(reg_vmmc); 618 if (ret) { 619 dev_err(&pdev->dev, 620 "Failed to enable vmmc regulator: %d\n", ret); 621 goto out_mmc_free; 622 } 623 } 624 625 ssp->clk = devm_clk_get(&pdev->dev, NULL); 626 if (IS_ERR(ssp->clk)) { 627 ret = PTR_ERR(ssp->clk); 628 goto out_mmc_free; 629 } 630 ret = clk_prepare_enable(ssp->clk); 631 if (ret) 632 goto out_mmc_free; 633 634 ret = mxs_mmc_reset(host); 635 if (ret) { 636 dev_err(&pdev->dev, "Failed to reset mmc: %d\n", ret); 637 goto out_clk_disable; 638 } 639 640 ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx"); 641 if (!ssp->dmach) { 642 dev_err(mmc_dev(host->mmc), 643 "%s: failed to request dma\n", __func__); 644 ret = -ENODEV; 645 goto out_clk_disable; 646 } 647 648 /* set mmc core parameters */ 649 mmc->ops = &mxs_mmc_ops; 650 mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 651 MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL | MMC_CAP_CMD23; 652 653 host->broken_cd = of_property_read_bool(np, "broken-cd"); 654 655 mmc->f_min = 400000; 656 mmc->f_max = 288000000; 657 658 ret = mmc_of_parse(mmc); 659 if (ret) 660 goto out_clk_disable; 661 662 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 663 664 mmc->max_segs = 52; 665 mmc->max_blk_size = 1 << 0xf; 666 mmc->max_blk_count = (ssp_is_old(ssp)) ? 0xff : 0xffffff; 667 mmc->max_req_size = (ssp_is_old(ssp)) ? 0xffff : 0xffffffff; 668 mmc->max_seg_size = dma_get_max_seg_size(ssp->dmach->device->dev); 669 670 platform_set_drvdata(pdev, mmc); 671 672 spin_lock_init(&host->lock); 673 674 ret = devm_request_irq(&pdev->dev, irq_err, mxs_mmc_irq_handler, 0, 675 dev_name(&pdev->dev), host); 676 if (ret) 677 goto out_free_dma; 678 679 ret = mmc_add_host(mmc); 680 if (ret) 681 goto out_free_dma; 682 683 dev_info(mmc_dev(host->mmc), "initialized\n"); 684 685 return 0; 686 687 out_free_dma: 688 dma_release_channel(ssp->dmach); 689 out_clk_disable: 690 clk_disable_unprepare(ssp->clk); 691 out_mmc_free: 692 mmc_free_host(mmc); 693 return ret; 694 } 695 696 static int mxs_mmc_remove(struct platform_device *pdev) 697 { 698 struct mmc_host *mmc = platform_get_drvdata(pdev); 699 struct mxs_mmc_host *host = mmc_priv(mmc); 700 struct mxs_ssp *ssp = &host->ssp; 701 702 mmc_remove_host(mmc); 703 704 if (ssp->dmach) 705 dma_release_channel(ssp->dmach); 706 707 clk_disable_unprepare(ssp->clk); 708 709 mmc_free_host(mmc); 710 711 return 0; 712 } 713 714 #ifdef CONFIG_PM_SLEEP 715 static int mxs_mmc_suspend(struct device *dev) 716 { 717 struct mmc_host *mmc = dev_get_drvdata(dev); 718 struct mxs_mmc_host *host = mmc_priv(mmc); 719 struct mxs_ssp *ssp = &host->ssp; 720 721 clk_disable_unprepare(ssp->clk); 722 return 0; 723 } 724 725 static int mxs_mmc_resume(struct device *dev) 726 { 727 struct mmc_host *mmc = dev_get_drvdata(dev); 728 struct mxs_mmc_host *host = mmc_priv(mmc); 729 struct mxs_ssp *ssp = &host->ssp; 730 731 return clk_prepare_enable(ssp->clk); 732 } 733 #endif 734 735 static SIMPLE_DEV_PM_OPS(mxs_mmc_pm_ops, mxs_mmc_suspend, mxs_mmc_resume); 736 737 static struct platform_driver mxs_mmc_driver = { 738 .probe = mxs_mmc_probe, 739 .remove = mxs_mmc_remove, 740 .id_table = mxs_ssp_ids, 741 .driver = { 742 .name = DRIVER_NAME, 743 .pm = &mxs_mmc_pm_ops, 744 .of_match_table = mxs_mmc_dt_ids, 745 }, 746 }; 747 748 module_platform_driver(mxs_mmc_driver); 749 750 MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral"); 751 MODULE_AUTHOR("Freescale Semiconductor"); 752 MODULE_LICENSE("GPL"); 753 MODULE_ALIAS("platform:" DRIVER_NAME); 754