1 /* 2 * Portions copyright (C) 2003 Russell King, PXA MMCI Driver 3 * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver 4 * 5 * Copyright 2008 Embedded Alley Solutions, Inc. 6 * Copyright 2009-2011 Freescale Semiconductor, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, write to the Free Software Foundation, Inc., 20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 21 */ 22 23 #include <linux/kernel.h> 24 #include <linux/init.h> 25 #include <linux/ioport.h> 26 #include <linux/of.h> 27 #include <linux/of_device.h> 28 #include <linux/of_gpio.h> 29 #include <linux/platform_device.h> 30 #include <linux/delay.h> 31 #include <linux/interrupt.h> 32 #include <linux/dma-mapping.h> 33 #include <linux/dmaengine.h> 34 #include <linux/highmem.h> 35 #include <linux/clk.h> 36 #include <linux/err.h> 37 #include <linux/completion.h> 38 #include <linux/mmc/host.h> 39 #include <linux/mmc/mmc.h> 40 #include <linux/mmc/sdio.h> 41 #include <linux/gpio.h> 42 #include <linux/regulator/consumer.h> 43 #include <linux/module.h> 44 #include <linux/stmp_device.h> 45 #include <linux/spi/mxs-spi.h> 46 47 #define DRIVER_NAME "mxs-mmc" 48 49 #define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \ 50 BM_SSP_CTRL1_RESP_ERR_IRQ | \ 51 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \ 52 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \ 53 BM_SSP_CTRL1_DATA_CRC_IRQ | \ 54 BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \ 55 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \ 56 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ) 57 58 /* card detect polling timeout */ 59 #define MXS_MMC_DETECT_TIMEOUT (HZ/2) 60 61 struct mxs_mmc_host { 62 struct mxs_ssp ssp; 63 64 struct mmc_host *mmc; 65 struct mmc_request *mrq; 66 struct mmc_command *cmd; 67 struct mmc_data *data; 68 69 unsigned char bus_width; 70 spinlock_t lock; 71 int sdio_irq_en; 72 int wp_gpio; 73 bool wp_inverted; 74 bool cd_inverted; 75 bool broken_cd; 76 bool non_removable; 77 }; 78 79 static int mxs_mmc_get_ro(struct mmc_host *mmc) 80 { 81 struct mxs_mmc_host *host = mmc_priv(mmc); 82 int ret; 83 84 if (!gpio_is_valid(host->wp_gpio)) 85 return -EINVAL; 86 87 ret = gpio_get_value(host->wp_gpio); 88 89 if (host->wp_inverted) 90 ret = !ret; 91 92 return ret; 93 } 94 95 static int mxs_mmc_get_cd(struct mmc_host *mmc) 96 { 97 struct mxs_mmc_host *host = mmc_priv(mmc); 98 struct mxs_ssp *ssp = &host->ssp; 99 100 return host->non_removable || host->broken_cd || 101 !(readl(ssp->base + HW_SSP_STATUS(ssp)) & 102 BM_SSP_STATUS_CARD_DETECT) ^ host->cd_inverted; 103 } 104 105 static void mxs_mmc_reset(struct mxs_mmc_host *host) 106 { 107 struct mxs_ssp *ssp = &host->ssp; 108 u32 ctrl0, ctrl1; 109 110 stmp_reset_block(ssp->base); 111 112 ctrl0 = BM_SSP_CTRL0_IGNORE_CRC; 113 ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) | 114 BF_SSP(0x7, CTRL1_WORD_LENGTH) | 115 BM_SSP_CTRL1_DMA_ENABLE | 116 BM_SSP_CTRL1_POLARITY | 117 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN | 118 BM_SSP_CTRL1_DATA_CRC_IRQ_EN | 119 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN | 120 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN | 121 BM_SSP_CTRL1_RESP_ERR_IRQ_EN; 122 123 writel(BF_SSP(0xffff, TIMING_TIMEOUT) | 124 BF_SSP(2, TIMING_CLOCK_DIVIDE) | 125 BF_SSP(0, TIMING_CLOCK_RATE), 126 ssp->base + HW_SSP_TIMING(ssp)); 127 128 if (host->sdio_irq_en) { 129 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 130 ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN; 131 } 132 133 writel(ctrl0, ssp->base + HW_SSP_CTRL0); 134 writel(ctrl1, ssp->base + HW_SSP_CTRL1(ssp)); 135 } 136 137 static void mxs_mmc_start_cmd(struct mxs_mmc_host *host, 138 struct mmc_command *cmd); 139 140 static void mxs_mmc_request_done(struct mxs_mmc_host *host) 141 { 142 struct mmc_command *cmd = host->cmd; 143 struct mmc_data *data = host->data; 144 struct mmc_request *mrq = host->mrq; 145 struct mxs_ssp *ssp = &host->ssp; 146 147 if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) { 148 if (mmc_resp_type(cmd) & MMC_RSP_136) { 149 cmd->resp[3] = readl(ssp->base + HW_SSP_SDRESP0(ssp)); 150 cmd->resp[2] = readl(ssp->base + HW_SSP_SDRESP1(ssp)); 151 cmd->resp[1] = readl(ssp->base + HW_SSP_SDRESP2(ssp)); 152 cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP3(ssp)); 153 } else { 154 cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP0(ssp)); 155 } 156 } 157 158 if (data) { 159 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 160 data->sg_len, ssp->dma_dir); 161 /* 162 * If there was an error on any block, we mark all 163 * data blocks as being in error. 164 */ 165 if (!data->error) 166 data->bytes_xfered = data->blocks * data->blksz; 167 else 168 data->bytes_xfered = 0; 169 170 host->data = NULL; 171 if (mrq->stop) { 172 mxs_mmc_start_cmd(host, mrq->stop); 173 return; 174 } 175 } 176 177 host->mrq = NULL; 178 mmc_request_done(host->mmc, mrq); 179 } 180 181 static void mxs_mmc_dma_irq_callback(void *param) 182 { 183 struct mxs_mmc_host *host = param; 184 185 mxs_mmc_request_done(host); 186 } 187 188 static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id) 189 { 190 struct mxs_mmc_host *host = dev_id; 191 struct mmc_command *cmd = host->cmd; 192 struct mmc_data *data = host->data; 193 struct mxs_ssp *ssp = &host->ssp; 194 u32 stat; 195 196 spin_lock(&host->lock); 197 198 stat = readl(ssp->base + HW_SSP_CTRL1(ssp)); 199 writel(stat & MXS_MMC_IRQ_BITS, 200 ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR); 201 202 spin_unlock(&host->lock); 203 204 if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN)) 205 mmc_signal_sdio_irq(host->mmc); 206 207 if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ) 208 cmd->error = -ETIMEDOUT; 209 else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ) 210 cmd->error = -EIO; 211 212 if (data) { 213 if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | 214 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ)) 215 data->error = -ETIMEDOUT; 216 else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ) 217 data->error = -EILSEQ; 218 else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | 219 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)) 220 data->error = -EIO; 221 } 222 223 return IRQ_HANDLED; 224 } 225 226 static struct dma_async_tx_descriptor *mxs_mmc_prep_dma( 227 struct mxs_mmc_host *host, unsigned long flags) 228 { 229 struct mxs_ssp *ssp = &host->ssp; 230 struct dma_async_tx_descriptor *desc; 231 struct mmc_data *data = host->data; 232 struct scatterlist * sgl; 233 unsigned int sg_len; 234 235 if (data) { 236 /* data */ 237 dma_map_sg(mmc_dev(host->mmc), data->sg, 238 data->sg_len, ssp->dma_dir); 239 sgl = data->sg; 240 sg_len = data->sg_len; 241 } else { 242 /* pio */ 243 sgl = (struct scatterlist *) ssp->ssp_pio_words; 244 sg_len = SSP_PIO_NUM; 245 } 246 247 desc = dmaengine_prep_slave_sg(ssp->dmach, 248 sgl, sg_len, ssp->slave_dirn, flags); 249 if (desc) { 250 desc->callback = mxs_mmc_dma_irq_callback; 251 desc->callback_param = host; 252 } else { 253 if (data) 254 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 255 data->sg_len, ssp->dma_dir); 256 } 257 258 return desc; 259 } 260 261 static void mxs_mmc_bc(struct mxs_mmc_host *host) 262 { 263 struct mxs_ssp *ssp = &host->ssp; 264 struct mmc_command *cmd = host->cmd; 265 struct dma_async_tx_descriptor *desc; 266 u32 ctrl0, cmd0, cmd1; 267 268 ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC; 269 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC; 270 cmd1 = cmd->arg; 271 272 if (host->sdio_irq_en) { 273 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 274 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 275 } 276 277 ssp->ssp_pio_words[0] = ctrl0; 278 ssp->ssp_pio_words[1] = cmd0; 279 ssp->ssp_pio_words[2] = cmd1; 280 ssp->dma_dir = DMA_NONE; 281 ssp->slave_dirn = DMA_TRANS_NONE; 282 desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK); 283 if (!desc) 284 goto out; 285 286 dmaengine_submit(desc); 287 dma_async_issue_pending(ssp->dmach); 288 return; 289 290 out: 291 dev_warn(mmc_dev(host->mmc), 292 "%s: failed to prep dma\n", __func__); 293 } 294 295 static void mxs_mmc_ac(struct mxs_mmc_host *host) 296 { 297 struct mxs_ssp *ssp = &host->ssp; 298 struct mmc_command *cmd = host->cmd; 299 struct dma_async_tx_descriptor *desc; 300 u32 ignore_crc, get_resp, long_resp; 301 u32 ctrl0, cmd0, cmd1; 302 303 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ? 304 0 : BM_SSP_CTRL0_IGNORE_CRC; 305 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ? 306 BM_SSP_CTRL0_GET_RESP : 0; 307 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ? 308 BM_SSP_CTRL0_LONG_RESP : 0; 309 310 ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp; 311 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD); 312 cmd1 = cmd->arg; 313 314 if (host->sdio_irq_en) { 315 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 316 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 317 } 318 319 ssp->ssp_pio_words[0] = ctrl0; 320 ssp->ssp_pio_words[1] = cmd0; 321 ssp->ssp_pio_words[2] = cmd1; 322 ssp->dma_dir = DMA_NONE; 323 ssp->slave_dirn = DMA_TRANS_NONE; 324 desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK); 325 if (!desc) 326 goto out; 327 328 dmaengine_submit(desc); 329 dma_async_issue_pending(ssp->dmach); 330 return; 331 332 out: 333 dev_warn(mmc_dev(host->mmc), 334 "%s: failed to prep dma\n", __func__); 335 } 336 337 static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns) 338 { 339 const unsigned int ssp_timeout_mul = 4096; 340 /* 341 * Calculate ticks in ms since ns are large numbers 342 * and might overflow 343 */ 344 const unsigned int clock_per_ms = clock_rate / 1000; 345 const unsigned int ms = ns / 1000; 346 const unsigned int ticks = ms * clock_per_ms; 347 const unsigned int ssp_ticks = ticks / ssp_timeout_mul; 348 349 WARN_ON(ssp_ticks == 0); 350 return ssp_ticks; 351 } 352 353 static void mxs_mmc_adtc(struct mxs_mmc_host *host) 354 { 355 struct mmc_command *cmd = host->cmd; 356 struct mmc_data *data = cmd->data; 357 struct dma_async_tx_descriptor *desc; 358 struct scatterlist *sgl = data->sg, *sg; 359 unsigned int sg_len = data->sg_len; 360 unsigned int i; 361 362 unsigned short dma_data_dir, timeout; 363 enum dma_transfer_direction slave_dirn; 364 unsigned int data_size = 0, log2_blksz; 365 unsigned int blocks = data->blocks; 366 367 struct mxs_ssp *ssp = &host->ssp; 368 369 u32 ignore_crc, get_resp, long_resp, read; 370 u32 ctrl0, cmd0, cmd1, val; 371 372 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ? 373 0 : BM_SSP_CTRL0_IGNORE_CRC; 374 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ? 375 BM_SSP_CTRL0_GET_RESP : 0; 376 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ? 377 BM_SSP_CTRL0_LONG_RESP : 0; 378 379 if (data->flags & MMC_DATA_WRITE) { 380 dma_data_dir = DMA_TO_DEVICE; 381 slave_dirn = DMA_MEM_TO_DEV; 382 read = 0; 383 } else { 384 dma_data_dir = DMA_FROM_DEVICE; 385 slave_dirn = DMA_DEV_TO_MEM; 386 read = BM_SSP_CTRL0_READ; 387 } 388 389 ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) | 390 ignore_crc | get_resp | long_resp | 391 BM_SSP_CTRL0_DATA_XFER | read | 392 BM_SSP_CTRL0_WAIT_FOR_IRQ | 393 BM_SSP_CTRL0_ENABLE; 394 395 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD); 396 397 /* get logarithm to base 2 of block size for setting register */ 398 log2_blksz = ilog2(data->blksz); 399 400 /* 401 * take special care of the case that data size from data->sg 402 * is not equal to blocks x blksz 403 */ 404 for_each_sg(sgl, sg, sg_len, i) 405 data_size += sg->length; 406 407 if (data_size != data->blocks * data->blksz) 408 blocks = 1; 409 410 /* xfer count, block size and count need to be set differently */ 411 if (ssp_is_old(ssp)) { 412 ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT); 413 cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) | 414 BF_SSP(blocks - 1, CMD0_BLOCK_COUNT); 415 } else { 416 writel(data_size, ssp->base + HW_SSP_XFER_SIZE); 417 writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) | 418 BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT), 419 ssp->base + HW_SSP_BLOCK_SIZE); 420 } 421 422 if ((cmd->opcode == MMC_STOP_TRANSMISSION) || 423 (cmd->opcode == SD_IO_RW_EXTENDED)) 424 cmd0 |= BM_SSP_CMD0_APPEND_8CYC; 425 426 cmd1 = cmd->arg; 427 428 if (host->sdio_irq_en) { 429 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 430 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 431 } 432 433 /* set the timeout count */ 434 timeout = mxs_ns_to_ssp_ticks(ssp->clk_rate, data->timeout_ns); 435 val = readl(ssp->base + HW_SSP_TIMING(ssp)); 436 val &= ~(BM_SSP_TIMING_TIMEOUT); 437 val |= BF_SSP(timeout, TIMING_TIMEOUT); 438 writel(val, ssp->base + HW_SSP_TIMING(ssp)); 439 440 /* pio */ 441 ssp->ssp_pio_words[0] = ctrl0; 442 ssp->ssp_pio_words[1] = cmd0; 443 ssp->ssp_pio_words[2] = cmd1; 444 ssp->dma_dir = DMA_NONE; 445 ssp->slave_dirn = DMA_TRANS_NONE; 446 desc = mxs_mmc_prep_dma(host, 0); 447 if (!desc) 448 goto out; 449 450 /* append data sg */ 451 WARN_ON(host->data != NULL); 452 host->data = data; 453 ssp->dma_dir = dma_data_dir; 454 ssp->slave_dirn = slave_dirn; 455 desc = mxs_mmc_prep_dma(host, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 456 if (!desc) 457 goto out; 458 459 dmaengine_submit(desc); 460 dma_async_issue_pending(ssp->dmach); 461 return; 462 out: 463 dev_warn(mmc_dev(host->mmc), 464 "%s: failed to prep dma\n", __func__); 465 } 466 467 static void mxs_mmc_start_cmd(struct mxs_mmc_host *host, 468 struct mmc_command *cmd) 469 { 470 host->cmd = cmd; 471 472 switch (mmc_cmd_type(cmd)) { 473 case MMC_CMD_BC: 474 mxs_mmc_bc(host); 475 break; 476 case MMC_CMD_BCR: 477 mxs_mmc_ac(host); 478 break; 479 case MMC_CMD_AC: 480 mxs_mmc_ac(host); 481 break; 482 case MMC_CMD_ADTC: 483 mxs_mmc_adtc(host); 484 break; 485 default: 486 dev_warn(mmc_dev(host->mmc), 487 "%s: unknown MMC command\n", __func__); 488 break; 489 } 490 } 491 492 static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 493 { 494 struct mxs_mmc_host *host = mmc_priv(mmc); 495 496 WARN_ON(host->mrq != NULL); 497 host->mrq = mrq; 498 mxs_mmc_start_cmd(host, mrq->cmd); 499 } 500 501 static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 502 { 503 struct mxs_mmc_host *host = mmc_priv(mmc); 504 505 if (ios->bus_width == MMC_BUS_WIDTH_8) 506 host->bus_width = 2; 507 else if (ios->bus_width == MMC_BUS_WIDTH_4) 508 host->bus_width = 1; 509 else 510 host->bus_width = 0; 511 512 if (ios->clock) 513 mxs_ssp_set_clk_rate(&host->ssp, ios->clock); 514 } 515 516 static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 517 { 518 struct mxs_mmc_host *host = mmc_priv(mmc); 519 struct mxs_ssp *ssp = &host->ssp; 520 unsigned long flags; 521 522 spin_lock_irqsave(&host->lock, flags); 523 524 host->sdio_irq_en = enable; 525 526 if (enable) { 527 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, 528 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); 529 writel(BM_SSP_CTRL1_SDIO_IRQ_EN, 530 ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_SET); 531 } else { 532 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, 533 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); 534 writel(BM_SSP_CTRL1_SDIO_IRQ_EN, 535 ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR); 536 } 537 538 spin_unlock_irqrestore(&host->lock, flags); 539 540 if (enable && readl(ssp->base + HW_SSP_STATUS(ssp)) & 541 BM_SSP_STATUS_SDIO_IRQ) 542 mmc_signal_sdio_irq(host->mmc); 543 544 } 545 546 static const struct mmc_host_ops mxs_mmc_ops = { 547 .request = mxs_mmc_request, 548 .get_ro = mxs_mmc_get_ro, 549 .get_cd = mxs_mmc_get_cd, 550 .set_ios = mxs_mmc_set_ios, 551 .enable_sdio_irq = mxs_mmc_enable_sdio_irq, 552 }; 553 554 static struct platform_device_id mxs_ssp_ids[] = { 555 { 556 .name = "imx23-mmc", 557 .driver_data = IMX23_SSP, 558 }, { 559 .name = "imx28-mmc", 560 .driver_data = IMX28_SSP, 561 }, { 562 /* sentinel */ 563 } 564 }; 565 MODULE_DEVICE_TABLE(platform, mxs_ssp_ids); 566 567 static const struct of_device_id mxs_mmc_dt_ids[] = { 568 { .compatible = "fsl,imx23-mmc", .data = (void *) IMX23_SSP, }, 569 { .compatible = "fsl,imx28-mmc", .data = (void *) IMX28_SSP, }, 570 { /* sentinel */ } 571 }; 572 MODULE_DEVICE_TABLE(of, mxs_mmc_dt_ids); 573 574 static int mxs_mmc_probe(struct platform_device *pdev) 575 { 576 const struct of_device_id *of_id = 577 of_match_device(mxs_mmc_dt_ids, &pdev->dev); 578 struct device_node *np = pdev->dev.of_node; 579 struct mxs_mmc_host *host; 580 struct mmc_host *mmc; 581 struct resource *iores; 582 int ret = 0, irq_err; 583 struct regulator *reg_vmmc; 584 enum of_gpio_flags flags; 585 struct mxs_ssp *ssp; 586 u32 bus_width = 0; 587 588 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 589 irq_err = platform_get_irq(pdev, 0); 590 if (!iores || irq_err < 0) 591 return -EINVAL; 592 593 mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev); 594 if (!mmc) 595 return -ENOMEM; 596 597 host = mmc_priv(mmc); 598 ssp = &host->ssp; 599 ssp->dev = &pdev->dev; 600 ssp->base = devm_ioremap_resource(&pdev->dev, iores); 601 if (IS_ERR(ssp->base)) { 602 ret = PTR_ERR(ssp->base); 603 goto out_mmc_free; 604 } 605 606 ssp->devid = (enum mxs_ssp_id) of_id->data; 607 608 host->mmc = mmc; 609 host->sdio_irq_en = 0; 610 611 reg_vmmc = devm_regulator_get(&pdev->dev, "vmmc"); 612 if (!IS_ERR(reg_vmmc)) { 613 ret = regulator_enable(reg_vmmc); 614 if (ret) { 615 dev_err(&pdev->dev, 616 "Failed to enable vmmc regulator: %d\n", ret); 617 goto out_mmc_free; 618 } 619 } 620 621 ssp->clk = devm_clk_get(&pdev->dev, NULL); 622 if (IS_ERR(ssp->clk)) { 623 ret = PTR_ERR(ssp->clk); 624 goto out_mmc_free; 625 } 626 clk_prepare_enable(ssp->clk); 627 628 mxs_mmc_reset(host); 629 630 ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx"); 631 if (!ssp->dmach) { 632 dev_err(mmc_dev(host->mmc), 633 "%s: failed to request dma\n", __func__); 634 ret = -ENODEV; 635 goto out_clk_disable; 636 } 637 638 /* set mmc core parameters */ 639 mmc->ops = &mxs_mmc_ops; 640 mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 641 MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL; 642 643 of_property_read_u32(np, "bus-width", &bus_width); 644 if (bus_width == 4) 645 mmc->caps |= MMC_CAP_4_BIT_DATA; 646 else if (bus_width == 8) 647 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA; 648 host->broken_cd = of_property_read_bool(np, "broken-cd"); 649 host->non_removable = of_property_read_bool(np, "non-removable"); 650 if (host->non_removable) 651 mmc->caps |= MMC_CAP_NONREMOVABLE; 652 host->wp_gpio = of_get_named_gpio_flags(np, "wp-gpios", 0, &flags); 653 if (flags & OF_GPIO_ACTIVE_LOW) 654 host->wp_inverted = 1; 655 656 host->cd_inverted = of_property_read_bool(np, "cd-inverted"); 657 658 mmc->f_min = 400000; 659 mmc->f_max = 288000000; 660 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 661 662 mmc->max_segs = 52; 663 mmc->max_blk_size = 1 << 0xf; 664 mmc->max_blk_count = (ssp_is_old(ssp)) ? 0xff : 0xffffff; 665 mmc->max_req_size = (ssp_is_old(ssp)) ? 0xffff : 0xffffffff; 666 mmc->max_seg_size = dma_get_max_seg_size(ssp->dmach->device->dev); 667 668 platform_set_drvdata(pdev, mmc); 669 670 ret = devm_request_irq(&pdev->dev, irq_err, mxs_mmc_irq_handler, 0, 671 DRIVER_NAME, host); 672 if (ret) 673 goto out_free_dma; 674 675 spin_lock_init(&host->lock); 676 677 ret = mmc_add_host(mmc); 678 if (ret) 679 goto out_free_dma; 680 681 dev_info(mmc_dev(host->mmc), "initialized\n"); 682 683 return 0; 684 685 out_free_dma: 686 if (ssp->dmach) 687 dma_release_channel(ssp->dmach); 688 out_clk_disable: 689 clk_disable_unprepare(ssp->clk); 690 out_mmc_free: 691 mmc_free_host(mmc); 692 return ret; 693 } 694 695 static int mxs_mmc_remove(struct platform_device *pdev) 696 { 697 struct mmc_host *mmc = platform_get_drvdata(pdev); 698 struct mxs_mmc_host *host = mmc_priv(mmc); 699 struct mxs_ssp *ssp = &host->ssp; 700 701 mmc_remove_host(mmc); 702 703 if (ssp->dmach) 704 dma_release_channel(ssp->dmach); 705 706 clk_disable_unprepare(ssp->clk); 707 708 mmc_free_host(mmc); 709 710 return 0; 711 } 712 713 #ifdef CONFIG_PM 714 static int mxs_mmc_suspend(struct device *dev) 715 { 716 struct mmc_host *mmc = dev_get_drvdata(dev); 717 struct mxs_mmc_host *host = mmc_priv(mmc); 718 struct mxs_ssp *ssp = &host->ssp; 719 int ret = 0; 720 721 ret = mmc_suspend_host(mmc); 722 723 clk_disable_unprepare(ssp->clk); 724 725 return ret; 726 } 727 728 static int mxs_mmc_resume(struct device *dev) 729 { 730 struct mmc_host *mmc = dev_get_drvdata(dev); 731 struct mxs_mmc_host *host = mmc_priv(mmc); 732 struct mxs_ssp *ssp = &host->ssp; 733 int ret = 0; 734 735 clk_prepare_enable(ssp->clk); 736 737 ret = mmc_resume_host(mmc); 738 739 return ret; 740 } 741 742 static const struct dev_pm_ops mxs_mmc_pm_ops = { 743 .suspend = mxs_mmc_suspend, 744 .resume = mxs_mmc_resume, 745 }; 746 #endif 747 748 static struct platform_driver mxs_mmc_driver = { 749 .probe = mxs_mmc_probe, 750 .remove = mxs_mmc_remove, 751 .id_table = mxs_ssp_ids, 752 .driver = { 753 .name = DRIVER_NAME, 754 .owner = THIS_MODULE, 755 #ifdef CONFIG_PM 756 .pm = &mxs_mmc_pm_ops, 757 #endif 758 .of_match_table = mxs_mmc_dt_ids, 759 }, 760 }; 761 762 module_platform_driver(mxs_mmc_driver); 763 764 MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral"); 765 MODULE_AUTHOR("Freescale Semiconductor"); 766 MODULE_LICENSE("GPL"); 767 MODULE_ALIAS("platform:" DRIVER_NAME); 768