1 /* 2 * Portions copyright (C) 2003 Russell King, PXA MMCI Driver 3 * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver 4 * 5 * Copyright 2008 Embedded Alley Solutions, Inc. 6 * Copyright 2009-2011 Freescale Semiconductor, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, write to the Free Software Foundation, Inc., 20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 21 */ 22 23 #include <linux/kernel.h> 24 #include <linux/init.h> 25 #include <linux/ioport.h> 26 #include <linux/platform_device.h> 27 #include <linux/delay.h> 28 #include <linux/interrupt.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/dmaengine.h> 31 #include <linux/highmem.h> 32 #include <linux/clk.h> 33 #include <linux/err.h> 34 #include <linux/completion.h> 35 #include <linux/mmc/host.h> 36 #include <linux/mmc/mmc.h> 37 #include <linux/mmc/sdio.h> 38 #include <linux/gpio.h> 39 #include <linux/regulator/consumer.h> 40 #include <linux/module.h> 41 #include <linux/fsl/mxs-dma.h> 42 #include <linux/pinctrl/consumer.h> 43 #include <linux/stmp_device.h> 44 #include <linux/mmc/mxs-mmc.h> 45 46 #define DRIVER_NAME "mxs-mmc" 47 48 /* card detect polling timeout */ 49 #define MXS_MMC_DETECT_TIMEOUT (HZ/2) 50 51 #define ssp_is_old(host) ((host)->devid == IMX23_MMC) 52 53 /* SSP registers */ 54 #define HW_SSP_CTRL0 0x000 55 #define BM_SSP_CTRL0_RUN (1 << 29) 56 #define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28) 57 #define BM_SSP_CTRL0_IGNORE_CRC (1 << 26) 58 #define BM_SSP_CTRL0_READ (1 << 25) 59 #define BM_SSP_CTRL0_DATA_XFER (1 << 24) 60 #define BP_SSP_CTRL0_BUS_WIDTH (22) 61 #define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22) 62 #define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21) 63 #define BM_SSP_CTRL0_LONG_RESP (1 << 19) 64 #define BM_SSP_CTRL0_GET_RESP (1 << 17) 65 #define BM_SSP_CTRL0_ENABLE (1 << 16) 66 #define BP_SSP_CTRL0_XFER_COUNT (0) 67 #define BM_SSP_CTRL0_XFER_COUNT (0xffff) 68 #define HW_SSP_CMD0 0x010 69 #define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25) 70 #define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22) 71 #define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21) 72 #define BM_SSP_CMD0_APPEND_8CYC (1 << 20) 73 #define BP_SSP_CMD0_BLOCK_SIZE (16) 74 #define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16) 75 #define BP_SSP_CMD0_BLOCK_COUNT (8) 76 #define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8) 77 #define BP_SSP_CMD0_CMD (0) 78 #define BM_SSP_CMD0_CMD (0xff) 79 #define HW_SSP_CMD1 0x020 80 #define HW_SSP_XFER_SIZE 0x030 81 #define HW_SSP_BLOCK_SIZE 0x040 82 #define BP_SSP_BLOCK_SIZE_BLOCK_COUNT (4) 83 #define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4) 84 #define BP_SSP_BLOCK_SIZE_BLOCK_SIZE (0) 85 #define BM_SSP_BLOCK_SIZE_BLOCK_SIZE (0xf) 86 #define HW_SSP_TIMING(h) (ssp_is_old(h) ? 0x050 : 0x070) 87 #define BP_SSP_TIMING_TIMEOUT (16) 88 #define BM_SSP_TIMING_TIMEOUT (0xffff << 16) 89 #define BP_SSP_TIMING_CLOCK_DIVIDE (8) 90 #define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8) 91 #define BP_SSP_TIMING_CLOCK_RATE (0) 92 #define BM_SSP_TIMING_CLOCK_RATE (0xff) 93 #define HW_SSP_CTRL1(h) (ssp_is_old(h) ? 0x060 : 0x080) 94 #define BM_SSP_CTRL1_SDIO_IRQ (1 << 31) 95 #define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30) 96 #define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29) 97 #define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28) 98 #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27) 99 #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26) 100 #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25) 101 #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24) 102 #define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23) 103 #define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22) 104 #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21) 105 #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20) 106 #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17) 107 #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16) 108 #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15) 109 #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14) 110 #define BM_SSP_CTRL1_DMA_ENABLE (1 << 13) 111 #define BM_SSP_CTRL1_POLARITY (1 << 9) 112 #define BP_SSP_CTRL1_WORD_LENGTH (4) 113 #define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4) 114 #define BP_SSP_CTRL1_SSP_MODE (0) 115 #define BM_SSP_CTRL1_SSP_MODE (0xf) 116 #define HW_SSP_SDRESP0(h) (ssp_is_old(h) ? 0x080 : 0x0a0) 117 #define HW_SSP_SDRESP1(h) (ssp_is_old(h) ? 0x090 : 0x0b0) 118 #define HW_SSP_SDRESP2(h) (ssp_is_old(h) ? 0x0a0 : 0x0c0) 119 #define HW_SSP_SDRESP3(h) (ssp_is_old(h) ? 0x0b0 : 0x0d0) 120 #define HW_SSP_STATUS(h) (ssp_is_old(h) ? 0x0c0 : 0x100) 121 #define BM_SSP_STATUS_CARD_DETECT (1 << 28) 122 #define BM_SSP_STATUS_SDIO_IRQ (1 << 17) 123 124 #define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field) 125 126 #define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \ 127 BM_SSP_CTRL1_RESP_ERR_IRQ | \ 128 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \ 129 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \ 130 BM_SSP_CTRL1_DATA_CRC_IRQ | \ 131 BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \ 132 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \ 133 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ) 134 135 #define SSP_PIO_NUM 3 136 137 enum mxs_mmc_id { 138 IMX23_MMC, 139 IMX28_MMC, 140 }; 141 142 struct mxs_mmc_host { 143 struct mmc_host *mmc; 144 struct mmc_request *mrq; 145 struct mmc_command *cmd; 146 struct mmc_data *data; 147 148 void __iomem *base; 149 int irq; 150 struct resource *res; 151 struct resource *dma_res; 152 struct clk *clk; 153 unsigned int clk_rate; 154 155 struct dma_chan *dmach; 156 struct mxs_dma_data dma_data; 157 unsigned int dma_dir; 158 enum dma_transfer_direction slave_dirn; 159 u32 ssp_pio_words[SSP_PIO_NUM]; 160 161 enum mxs_mmc_id devid; 162 unsigned char bus_width; 163 spinlock_t lock; 164 int sdio_irq_en; 165 }; 166 167 static int mxs_mmc_get_ro(struct mmc_host *mmc) 168 { 169 struct mxs_mmc_host *host = mmc_priv(mmc); 170 struct mxs_mmc_platform_data *pdata = 171 mmc_dev(host->mmc)->platform_data; 172 173 if (!pdata) 174 return -EFAULT; 175 176 if (!gpio_is_valid(pdata->wp_gpio)) 177 return -EINVAL; 178 179 return gpio_get_value(pdata->wp_gpio); 180 } 181 182 static int mxs_mmc_get_cd(struct mmc_host *mmc) 183 { 184 struct mxs_mmc_host *host = mmc_priv(mmc); 185 186 return !(readl(host->base + HW_SSP_STATUS(host)) & 187 BM_SSP_STATUS_CARD_DETECT); 188 } 189 190 static void mxs_mmc_reset(struct mxs_mmc_host *host) 191 { 192 u32 ctrl0, ctrl1; 193 194 stmp_reset_block(host->base); 195 196 ctrl0 = BM_SSP_CTRL0_IGNORE_CRC; 197 ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) | 198 BF_SSP(0x7, CTRL1_WORD_LENGTH) | 199 BM_SSP_CTRL1_DMA_ENABLE | 200 BM_SSP_CTRL1_POLARITY | 201 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN | 202 BM_SSP_CTRL1_DATA_CRC_IRQ_EN | 203 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN | 204 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN | 205 BM_SSP_CTRL1_RESP_ERR_IRQ_EN; 206 207 writel(BF_SSP(0xffff, TIMING_TIMEOUT) | 208 BF_SSP(2, TIMING_CLOCK_DIVIDE) | 209 BF_SSP(0, TIMING_CLOCK_RATE), 210 host->base + HW_SSP_TIMING(host)); 211 212 if (host->sdio_irq_en) { 213 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 214 ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN; 215 } 216 217 writel(ctrl0, host->base + HW_SSP_CTRL0); 218 writel(ctrl1, host->base + HW_SSP_CTRL1(host)); 219 } 220 221 static void mxs_mmc_start_cmd(struct mxs_mmc_host *host, 222 struct mmc_command *cmd); 223 224 static void mxs_mmc_request_done(struct mxs_mmc_host *host) 225 { 226 struct mmc_command *cmd = host->cmd; 227 struct mmc_data *data = host->data; 228 struct mmc_request *mrq = host->mrq; 229 230 if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) { 231 if (mmc_resp_type(cmd) & MMC_RSP_136) { 232 cmd->resp[3] = readl(host->base + HW_SSP_SDRESP0(host)); 233 cmd->resp[2] = readl(host->base + HW_SSP_SDRESP1(host)); 234 cmd->resp[1] = readl(host->base + HW_SSP_SDRESP2(host)); 235 cmd->resp[0] = readl(host->base + HW_SSP_SDRESP3(host)); 236 } else { 237 cmd->resp[0] = readl(host->base + HW_SSP_SDRESP0(host)); 238 } 239 } 240 241 if (data) { 242 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 243 data->sg_len, host->dma_dir); 244 /* 245 * If there was an error on any block, we mark all 246 * data blocks as being in error. 247 */ 248 if (!data->error) 249 data->bytes_xfered = data->blocks * data->blksz; 250 else 251 data->bytes_xfered = 0; 252 253 host->data = NULL; 254 if (mrq->stop) { 255 mxs_mmc_start_cmd(host, mrq->stop); 256 return; 257 } 258 } 259 260 host->mrq = NULL; 261 mmc_request_done(host->mmc, mrq); 262 } 263 264 static void mxs_mmc_dma_irq_callback(void *param) 265 { 266 struct mxs_mmc_host *host = param; 267 268 mxs_mmc_request_done(host); 269 } 270 271 static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id) 272 { 273 struct mxs_mmc_host *host = dev_id; 274 struct mmc_command *cmd = host->cmd; 275 struct mmc_data *data = host->data; 276 u32 stat; 277 278 spin_lock(&host->lock); 279 280 stat = readl(host->base + HW_SSP_CTRL1(host)); 281 writel(stat & MXS_MMC_IRQ_BITS, 282 host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_CLR); 283 284 if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN)) 285 mmc_signal_sdio_irq(host->mmc); 286 287 spin_unlock(&host->lock); 288 289 if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ) 290 cmd->error = -ETIMEDOUT; 291 else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ) 292 cmd->error = -EIO; 293 294 if (data) { 295 if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | 296 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ)) 297 data->error = -ETIMEDOUT; 298 else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ) 299 data->error = -EILSEQ; 300 else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | 301 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)) 302 data->error = -EIO; 303 } 304 305 return IRQ_HANDLED; 306 } 307 308 static struct dma_async_tx_descriptor *mxs_mmc_prep_dma( 309 struct mxs_mmc_host *host, unsigned long flags) 310 { 311 struct dma_async_tx_descriptor *desc; 312 struct mmc_data *data = host->data; 313 struct scatterlist * sgl; 314 unsigned int sg_len; 315 316 if (data) { 317 /* data */ 318 dma_map_sg(mmc_dev(host->mmc), data->sg, 319 data->sg_len, host->dma_dir); 320 sgl = data->sg; 321 sg_len = data->sg_len; 322 } else { 323 /* pio */ 324 sgl = (struct scatterlist *) host->ssp_pio_words; 325 sg_len = SSP_PIO_NUM; 326 } 327 328 desc = dmaengine_prep_slave_sg(host->dmach, 329 sgl, sg_len, host->slave_dirn, flags); 330 if (desc) { 331 desc->callback = mxs_mmc_dma_irq_callback; 332 desc->callback_param = host; 333 } else { 334 if (data) 335 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 336 data->sg_len, host->dma_dir); 337 } 338 339 return desc; 340 } 341 342 static void mxs_mmc_bc(struct mxs_mmc_host *host) 343 { 344 struct mmc_command *cmd = host->cmd; 345 struct dma_async_tx_descriptor *desc; 346 u32 ctrl0, cmd0, cmd1; 347 348 ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC; 349 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC; 350 cmd1 = cmd->arg; 351 352 if (host->sdio_irq_en) { 353 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 354 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 355 } 356 357 host->ssp_pio_words[0] = ctrl0; 358 host->ssp_pio_words[1] = cmd0; 359 host->ssp_pio_words[2] = cmd1; 360 host->dma_dir = DMA_NONE; 361 host->slave_dirn = DMA_TRANS_NONE; 362 desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK); 363 if (!desc) 364 goto out; 365 366 dmaengine_submit(desc); 367 dma_async_issue_pending(host->dmach); 368 return; 369 370 out: 371 dev_warn(mmc_dev(host->mmc), 372 "%s: failed to prep dma\n", __func__); 373 } 374 375 static void mxs_mmc_ac(struct mxs_mmc_host *host) 376 { 377 struct mmc_command *cmd = host->cmd; 378 struct dma_async_tx_descriptor *desc; 379 u32 ignore_crc, get_resp, long_resp; 380 u32 ctrl0, cmd0, cmd1; 381 382 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ? 383 0 : BM_SSP_CTRL0_IGNORE_CRC; 384 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ? 385 BM_SSP_CTRL0_GET_RESP : 0; 386 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ? 387 BM_SSP_CTRL0_LONG_RESP : 0; 388 389 ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp; 390 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD); 391 cmd1 = cmd->arg; 392 393 if (host->sdio_irq_en) { 394 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 395 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 396 } 397 398 host->ssp_pio_words[0] = ctrl0; 399 host->ssp_pio_words[1] = cmd0; 400 host->ssp_pio_words[2] = cmd1; 401 host->dma_dir = DMA_NONE; 402 host->slave_dirn = DMA_TRANS_NONE; 403 desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK); 404 if (!desc) 405 goto out; 406 407 dmaengine_submit(desc); 408 dma_async_issue_pending(host->dmach); 409 return; 410 411 out: 412 dev_warn(mmc_dev(host->mmc), 413 "%s: failed to prep dma\n", __func__); 414 } 415 416 static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns) 417 { 418 const unsigned int ssp_timeout_mul = 4096; 419 /* 420 * Calculate ticks in ms since ns are large numbers 421 * and might overflow 422 */ 423 const unsigned int clock_per_ms = clock_rate / 1000; 424 const unsigned int ms = ns / 1000; 425 const unsigned int ticks = ms * clock_per_ms; 426 const unsigned int ssp_ticks = ticks / ssp_timeout_mul; 427 428 WARN_ON(ssp_ticks == 0); 429 return ssp_ticks; 430 } 431 432 static void mxs_mmc_adtc(struct mxs_mmc_host *host) 433 { 434 struct mmc_command *cmd = host->cmd; 435 struct mmc_data *data = cmd->data; 436 struct dma_async_tx_descriptor *desc; 437 struct scatterlist *sgl = data->sg, *sg; 438 unsigned int sg_len = data->sg_len; 439 int i; 440 441 unsigned short dma_data_dir, timeout; 442 enum dma_transfer_direction slave_dirn; 443 unsigned int data_size = 0, log2_blksz; 444 unsigned int blocks = data->blocks; 445 446 u32 ignore_crc, get_resp, long_resp, read; 447 u32 ctrl0, cmd0, cmd1, val; 448 449 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ? 450 0 : BM_SSP_CTRL0_IGNORE_CRC; 451 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ? 452 BM_SSP_CTRL0_GET_RESP : 0; 453 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ? 454 BM_SSP_CTRL0_LONG_RESP : 0; 455 456 if (data->flags & MMC_DATA_WRITE) { 457 dma_data_dir = DMA_TO_DEVICE; 458 slave_dirn = DMA_MEM_TO_DEV; 459 read = 0; 460 } else { 461 dma_data_dir = DMA_FROM_DEVICE; 462 slave_dirn = DMA_DEV_TO_MEM; 463 read = BM_SSP_CTRL0_READ; 464 } 465 466 ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) | 467 ignore_crc | get_resp | long_resp | 468 BM_SSP_CTRL0_DATA_XFER | read | 469 BM_SSP_CTRL0_WAIT_FOR_IRQ | 470 BM_SSP_CTRL0_ENABLE; 471 472 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD); 473 474 /* get logarithm to base 2 of block size for setting register */ 475 log2_blksz = ilog2(data->blksz); 476 477 /* 478 * take special care of the case that data size from data->sg 479 * is not equal to blocks x blksz 480 */ 481 for_each_sg(sgl, sg, sg_len, i) 482 data_size += sg->length; 483 484 if (data_size != data->blocks * data->blksz) 485 blocks = 1; 486 487 /* xfer count, block size and count need to be set differently */ 488 if (ssp_is_old(host)) { 489 ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT); 490 cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) | 491 BF_SSP(blocks - 1, CMD0_BLOCK_COUNT); 492 } else { 493 writel(data_size, host->base + HW_SSP_XFER_SIZE); 494 writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) | 495 BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT), 496 host->base + HW_SSP_BLOCK_SIZE); 497 } 498 499 if ((cmd->opcode == MMC_STOP_TRANSMISSION) || 500 (cmd->opcode == SD_IO_RW_EXTENDED)) 501 cmd0 |= BM_SSP_CMD0_APPEND_8CYC; 502 503 cmd1 = cmd->arg; 504 505 if (host->sdio_irq_en) { 506 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 507 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 508 } 509 510 /* set the timeout count */ 511 timeout = mxs_ns_to_ssp_ticks(host->clk_rate, data->timeout_ns); 512 val = readl(host->base + HW_SSP_TIMING(host)); 513 val &= ~(BM_SSP_TIMING_TIMEOUT); 514 val |= BF_SSP(timeout, TIMING_TIMEOUT); 515 writel(val, host->base + HW_SSP_TIMING(host)); 516 517 /* pio */ 518 host->ssp_pio_words[0] = ctrl0; 519 host->ssp_pio_words[1] = cmd0; 520 host->ssp_pio_words[2] = cmd1; 521 host->dma_dir = DMA_NONE; 522 host->slave_dirn = DMA_TRANS_NONE; 523 desc = mxs_mmc_prep_dma(host, 0); 524 if (!desc) 525 goto out; 526 527 /* append data sg */ 528 WARN_ON(host->data != NULL); 529 host->data = data; 530 host->dma_dir = dma_data_dir; 531 host->slave_dirn = slave_dirn; 532 desc = mxs_mmc_prep_dma(host, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 533 if (!desc) 534 goto out; 535 536 dmaengine_submit(desc); 537 dma_async_issue_pending(host->dmach); 538 return; 539 out: 540 dev_warn(mmc_dev(host->mmc), 541 "%s: failed to prep dma\n", __func__); 542 } 543 544 static void mxs_mmc_start_cmd(struct mxs_mmc_host *host, 545 struct mmc_command *cmd) 546 { 547 host->cmd = cmd; 548 549 switch (mmc_cmd_type(cmd)) { 550 case MMC_CMD_BC: 551 mxs_mmc_bc(host); 552 break; 553 case MMC_CMD_BCR: 554 mxs_mmc_ac(host); 555 break; 556 case MMC_CMD_AC: 557 mxs_mmc_ac(host); 558 break; 559 case MMC_CMD_ADTC: 560 mxs_mmc_adtc(host); 561 break; 562 default: 563 dev_warn(mmc_dev(host->mmc), 564 "%s: unknown MMC command\n", __func__); 565 break; 566 } 567 } 568 569 static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 570 { 571 struct mxs_mmc_host *host = mmc_priv(mmc); 572 573 WARN_ON(host->mrq != NULL); 574 host->mrq = mrq; 575 mxs_mmc_start_cmd(host, mrq->cmd); 576 } 577 578 static void mxs_mmc_set_clk_rate(struct mxs_mmc_host *host, unsigned int rate) 579 { 580 unsigned int ssp_clk, ssp_sck; 581 u32 clock_divide, clock_rate; 582 u32 val; 583 584 ssp_clk = clk_get_rate(host->clk); 585 586 for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) { 587 clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide); 588 clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0; 589 if (clock_rate <= 255) 590 break; 591 } 592 593 if (clock_divide > 254) { 594 dev_err(mmc_dev(host->mmc), 595 "%s: cannot set clock to %d\n", __func__, rate); 596 return; 597 } 598 599 ssp_sck = ssp_clk / clock_divide / (1 + clock_rate); 600 601 val = readl(host->base + HW_SSP_TIMING(host)); 602 val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE); 603 val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE); 604 val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE); 605 writel(val, host->base + HW_SSP_TIMING(host)); 606 607 host->clk_rate = ssp_sck; 608 609 dev_dbg(mmc_dev(host->mmc), 610 "%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n", 611 __func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate); 612 } 613 614 static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 615 { 616 struct mxs_mmc_host *host = mmc_priv(mmc); 617 618 if (ios->bus_width == MMC_BUS_WIDTH_8) 619 host->bus_width = 2; 620 else if (ios->bus_width == MMC_BUS_WIDTH_4) 621 host->bus_width = 1; 622 else 623 host->bus_width = 0; 624 625 if (ios->clock) 626 mxs_mmc_set_clk_rate(host, ios->clock); 627 } 628 629 static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 630 { 631 struct mxs_mmc_host *host = mmc_priv(mmc); 632 unsigned long flags; 633 634 spin_lock_irqsave(&host->lock, flags); 635 636 host->sdio_irq_en = enable; 637 638 if (enable) { 639 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, 640 host->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); 641 writel(BM_SSP_CTRL1_SDIO_IRQ_EN, 642 host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_SET); 643 644 if (readl(host->base + HW_SSP_STATUS(host)) & 645 BM_SSP_STATUS_SDIO_IRQ) 646 mmc_signal_sdio_irq(host->mmc); 647 648 } else { 649 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, 650 host->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); 651 writel(BM_SSP_CTRL1_SDIO_IRQ_EN, 652 host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_CLR); 653 } 654 655 spin_unlock_irqrestore(&host->lock, flags); 656 } 657 658 static const struct mmc_host_ops mxs_mmc_ops = { 659 .request = mxs_mmc_request, 660 .get_ro = mxs_mmc_get_ro, 661 .get_cd = mxs_mmc_get_cd, 662 .set_ios = mxs_mmc_set_ios, 663 .enable_sdio_irq = mxs_mmc_enable_sdio_irq, 664 }; 665 666 static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param) 667 { 668 struct mxs_mmc_host *host = param; 669 670 if (!mxs_dma_is_apbh(chan)) 671 return false; 672 673 if (chan->chan_id != host->dma_res->start) 674 return false; 675 676 chan->private = &host->dma_data; 677 678 return true; 679 } 680 681 static struct platform_device_id mxs_mmc_ids[] = { 682 { 683 .name = "imx23-mmc", 684 .driver_data = IMX23_MMC, 685 }, { 686 .name = "imx28-mmc", 687 .driver_data = IMX28_MMC, 688 }, { 689 /* sentinel */ 690 } 691 }; 692 MODULE_DEVICE_TABLE(platform, mxs_mmc_ids); 693 694 static int mxs_mmc_probe(struct platform_device *pdev) 695 { 696 struct mxs_mmc_host *host; 697 struct mmc_host *mmc; 698 struct resource *iores, *dmares, *r; 699 struct mxs_mmc_platform_data *pdata; 700 struct pinctrl *pinctrl; 701 int ret = 0, irq_err, irq_dma; 702 dma_cap_mask_t mask; 703 704 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 705 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0); 706 irq_err = platform_get_irq(pdev, 0); 707 irq_dma = platform_get_irq(pdev, 1); 708 if (!iores || !dmares || irq_err < 0 || irq_dma < 0) 709 return -EINVAL; 710 711 r = request_mem_region(iores->start, resource_size(iores), pdev->name); 712 if (!r) 713 return -EBUSY; 714 715 mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev); 716 if (!mmc) { 717 ret = -ENOMEM; 718 goto out_release_mem; 719 } 720 721 host = mmc_priv(mmc); 722 host->base = ioremap(r->start, resource_size(r)); 723 if (!host->base) { 724 ret = -ENOMEM; 725 goto out_mmc_free; 726 } 727 728 host->devid = pdev->id_entry->driver_data; 729 host->mmc = mmc; 730 host->res = r; 731 host->dma_res = dmares; 732 host->irq = irq_err; 733 host->sdio_irq_en = 0; 734 735 pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 736 if (IS_ERR(pinctrl)) { 737 ret = PTR_ERR(pinctrl); 738 goto out_iounmap; 739 } 740 741 host->clk = clk_get(&pdev->dev, NULL); 742 if (IS_ERR(host->clk)) { 743 ret = PTR_ERR(host->clk); 744 goto out_iounmap; 745 } 746 clk_prepare_enable(host->clk); 747 748 mxs_mmc_reset(host); 749 750 dma_cap_zero(mask); 751 dma_cap_set(DMA_SLAVE, mask); 752 host->dma_data.chan_irq = irq_dma; 753 host->dmach = dma_request_channel(mask, mxs_mmc_dma_filter, host); 754 if (!host->dmach) { 755 dev_err(mmc_dev(host->mmc), 756 "%s: failed to request dma\n", __func__); 757 goto out_clk_put; 758 } 759 760 /* set mmc core parameters */ 761 mmc->ops = &mxs_mmc_ops; 762 mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 763 MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL; 764 765 pdata = mmc_dev(host->mmc)->platform_data; 766 if (pdata) { 767 if (pdata->flags & SLOTF_8_BIT_CAPABLE) 768 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA; 769 if (pdata->flags & SLOTF_4_BIT_CAPABLE) 770 mmc->caps |= MMC_CAP_4_BIT_DATA; 771 } 772 773 mmc->f_min = 400000; 774 mmc->f_max = 288000000; 775 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 776 777 mmc->max_segs = 52; 778 mmc->max_blk_size = 1 << 0xf; 779 mmc->max_blk_count = (ssp_is_old(host)) ? 0xff : 0xffffff; 780 mmc->max_req_size = (ssp_is_old(host)) ? 0xffff : 0xffffffff; 781 mmc->max_seg_size = dma_get_max_seg_size(host->dmach->device->dev); 782 783 platform_set_drvdata(pdev, mmc); 784 785 ret = request_irq(host->irq, mxs_mmc_irq_handler, 0, DRIVER_NAME, host); 786 if (ret) 787 goto out_free_dma; 788 789 spin_lock_init(&host->lock); 790 791 ret = mmc_add_host(mmc); 792 if (ret) 793 goto out_free_irq; 794 795 dev_info(mmc_dev(host->mmc), "initialized\n"); 796 797 return 0; 798 799 out_free_irq: 800 free_irq(host->irq, host); 801 out_free_dma: 802 if (host->dmach) 803 dma_release_channel(host->dmach); 804 out_clk_put: 805 clk_disable_unprepare(host->clk); 806 clk_put(host->clk); 807 out_iounmap: 808 iounmap(host->base); 809 out_mmc_free: 810 mmc_free_host(mmc); 811 out_release_mem: 812 release_mem_region(iores->start, resource_size(iores)); 813 return ret; 814 } 815 816 static int mxs_mmc_remove(struct platform_device *pdev) 817 { 818 struct mmc_host *mmc = platform_get_drvdata(pdev); 819 struct mxs_mmc_host *host = mmc_priv(mmc); 820 struct resource *res = host->res; 821 822 mmc_remove_host(mmc); 823 824 free_irq(host->irq, host); 825 826 platform_set_drvdata(pdev, NULL); 827 828 if (host->dmach) 829 dma_release_channel(host->dmach); 830 831 clk_disable_unprepare(host->clk); 832 clk_put(host->clk); 833 834 iounmap(host->base); 835 836 mmc_free_host(mmc); 837 838 release_mem_region(res->start, resource_size(res)); 839 840 return 0; 841 } 842 843 #ifdef CONFIG_PM 844 static int mxs_mmc_suspend(struct device *dev) 845 { 846 struct mmc_host *mmc = dev_get_drvdata(dev); 847 struct mxs_mmc_host *host = mmc_priv(mmc); 848 int ret = 0; 849 850 ret = mmc_suspend_host(mmc); 851 852 clk_disable_unprepare(host->clk); 853 854 return ret; 855 } 856 857 static int mxs_mmc_resume(struct device *dev) 858 { 859 struct mmc_host *mmc = dev_get_drvdata(dev); 860 struct mxs_mmc_host *host = mmc_priv(mmc); 861 int ret = 0; 862 863 clk_prepare_enable(host->clk); 864 865 ret = mmc_resume_host(mmc); 866 867 return ret; 868 } 869 870 static const struct dev_pm_ops mxs_mmc_pm_ops = { 871 .suspend = mxs_mmc_suspend, 872 .resume = mxs_mmc_resume, 873 }; 874 #endif 875 876 static struct platform_driver mxs_mmc_driver = { 877 .probe = mxs_mmc_probe, 878 .remove = mxs_mmc_remove, 879 .id_table = mxs_mmc_ids, 880 .driver = { 881 .name = DRIVER_NAME, 882 .owner = THIS_MODULE, 883 #ifdef CONFIG_PM 884 .pm = &mxs_mmc_pm_ops, 885 #endif 886 }, 887 }; 888 889 module_platform_driver(mxs_mmc_driver); 890 891 MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral"); 892 MODULE_AUTHOR("Freescale Semiconductor"); 893 MODULE_LICENSE("GPL"); 894