1 /* 2 * Portions copyright (C) 2003 Russell King, PXA MMCI Driver 3 * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver 4 * 5 * Copyright 2008 Embedded Alley Solutions, Inc. 6 * Copyright 2009-2011 Freescale Semiconductor, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, write to the Free Software Foundation, Inc., 20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 21 */ 22 23 #include <linux/kernel.h> 24 #include <linux/init.h> 25 #include <linux/ioport.h> 26 #include <linux/platform_device.h> 27 #include <linux/delay.h> 28 #include <linux/interrupt.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/dmaengine.h> 31 #include <linux/highmem.h> 32 #include <linux/clk.h> 33 #include <linux/err.h> 34 #include <linux/completion.h> 35 #include <linux/mmc/host.h> 36 #include <linux/mmc/mmc.h> 37 #include <linux/mmc/sdio.h> 38 #include <linux/gpio.h> 39 #include <linux/regulator/consumer.h> 40 #include <linux/module.h> 41 42 #include <mach/mxs.h> 43 #include <mach/common.h> 44 #include <mach/dma.h> 45 #include <mach/mmc.h> 46 47 #define DRIVER_NAME "mxs-mmc" 48 49 /* card detect polling timeout */ 50 #define MXS_MMC_DETECT_TIMEOUT (HZ/2) 51 52 #define SSP_VERSION_LATEST 4 53 #define ssp_is_old() (host->version < SSP_VERSION_LATEST) 54 55 /* SSP registers */ 56 #define HW_SSP_CTRL0 0x000 57 #define BM_SSP_CTRL0_RUN (1 << 29) 58 #define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28) 59 #define BM_SSP_CTRL0_IGNORE_CRC (1 << 26) 60 #define BM_SSP_CTRL0_READ (1 << 25) 61 #define BM_SSP_CTRL0_DATA_XFER (1 << 24) 62 #define BP_SSP_CTRL0_BUS_WIDTH (22) 63 #define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22) 64 #define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21) 65 #define BM_SSP_CTRL0_LONG_RESP (1 << 19) 66 #define BM_SSP_CTRL0_GET_RESP (1 << 17) 67 #define BM_SSP_CTRL0_ENABLE (1 << 16) 68 #define BP_SSP_CTRL0_XFER_COUNT (0) 69 #define BM_SSP_CTRL0_XFER_COUNT (0xffff) 70 #define HW_SSP_CMD0 0x010 71 #define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25) 72 #define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22) 73 #define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21) 74 #define BM_SSP_CMD0_APPEND_8CYC (1 << 20) 75 #define BP_SSP_CMD0_BLOCK_SIZE (16) 76 #define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16) 77 #define BP_SSP_CMD0_BLOCK_COUNT (8) 78 #define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8) 79 #define BP_SSP_CMD0_CMD (0) 80 #define BM_SSP_CMD0_CMD (0xff) 81 #define HW_SSP_CMD1 0x020 82 #define HW_SSP_XFER_SIZE 0x030 83 #define HW_SSP_BLOCK_SIZE 0x040 84 #define BP_SSP_BLOCK_SIZE_BLOCK_COUNT (4) 85 #define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4) 86 #define BP_SSP_BLOCK_SIZE_BLOCK_SIZE (0) 87 #define BM_SSP_BLOCK_SIZE_BLOCK_SIZE (0xf) 88 #define HW_SSP_TIMING (ssp_is_old() ? 0x050 : 0x070) 89 #define BP_SSP_TIMING_TIMEOUT (16) 90 #define BM_SSP_TIMING_TIMEOUT (0xffff << 16) 91 #define BP_SSP_TIMING_CLOCK_DIVIDE (8) 92 #define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8) 93 #define BP_SSP_TIMING_CLOCK_RATE (0) 94 #define BM_SSP_TIMING_CLOCK_RATE (0xff) 95 #define HW_SSP_CTRL1 (ssp_is_old() ? 0x060 : 0x080) 96 #define BM_SSP_CTRL1_SDIO_IRQ (1 << 31) 97 #define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30) 98 #define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29) 99 #define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28) 100 #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27) 101 #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26) 102 #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25) 103 #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24) 104 #define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23) 105 #define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22) 106 #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21) 107 #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20) 108 #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17) 109 #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16) 110 #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15) 111 #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14) 112 #define BM_SSP_CTRL1_DMA_ENABLE (1 << 13) 113 #define BM_SSP_CTRL1_POLARITY (1 << 9) 114 #define BP_SSP_CTRL1_WORD_LENGTH (4) 115 #define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4) 116 #define BP_SSP_CTRL1_SSP_MODE (0) 117 #define BM_SSP_CTRL1_SSP_MODE (0xf) 118 #define HW_SSP_SDRESP0 (ssp_is_old() ? 0x080 : 0x0a0) 119 #define HW_SSP_SDRESP1 (ssp_is_old() ? 0x090 : 0x0b0) 120 #define HW_SSP_SDRESP2 (ssp_is_old() ? 0x0a0 : 0x0c0) 121 #define HW_SSP_SDRESP3 (ssp_is_old() ? 0x0b0 : 0x0d0) 122 #define HW_SSP_STATUS (ssp_is_old() ? 0x0c0 : 0x100) 123 #define BM_SSP_STATUS_CARD_DETECT (1 << 28) 124 #define BM_SSP_STATUS_SDIO_IRQ (1 << 17) 125 #define HW_SSP_VERSION (cpu_is_mx23() ? 0x110 : 0x130) 126 #define BP_SSP_VERSION_MAJOR (24) 127 128 #define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field) 129 130 #define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \ 131 BM_SSP_CTRL1_RESP_ERR_IRQ | \ 132 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \ 133 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \ 134 BM_SSP_CTRL1_DATA_CRC_IRQ | \ 135 BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \ 136 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \ 137 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ) 138 139 #define SSP_PIO_NUM 3 140 141 struct mxs_mmc_host { 142 struct mmc_host *mmc; 143 struct mmc_request *mrq; 144 struct mmc_command *cmd; 145 struct mmc_data *data; 146 147 void __iomem *base; 148 int irq; 149 struct resource *res; 150 struct resource *dma_res; 151 struct clk *clk; 152 unsigned int clk_rate; 153 154 struct dma_chan *dmach; 155 struct mxs_dma_data dma_data; 156 unsigned int dma_dir; 157 u32 ssp_pio_words[SSP_PIO_NUM]; 158 159 unsigned int version; 160 unsigned char bus_width; 161 spinlock_t lock; 162 int sdio_irq_en; 163 }; 164 165 static int mxs_mmc_get_ro(struct mmc_host *mmc) 166 { 167 struct mxs_mmc_host *host = mmc_priv(mmc); 168 struct mxs_mmc_platform_data *pdata = 169 mmc_dev(host->mmc)->platform_data; 170 171 if (!pdata) 172 return -EFAULT; 173 174 if (!gpio_is_valid(pdata->wp_gpio)) 175 return -EINVAL; 176 177 return gpio_get_value(pdata->wp_gpio); 178 } 179 180 static int mxs_mmc_get_cd(struct mmc_host *mmc) 181 { 182 struct mxs_mmc_host *host = mmc_priv(mmc); 183 184 return !(readl(host->base + HW_SSP_STATUS) & 185 BM_SSP_STATUS_CARD_DETECT); 186 } 187 188 static void mxs_mmc_reset(struct mxs_mmc_host *host) 189 { 190 u32 ctrl0, ctrl1; 191 192 mxs_reset_block(host->base); 193 194 ctrl0 = BM_SSP_CTRL0_IGNORE_CRC; 195 ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) | 196 BF_SSP(0x7, CTRL1_WORD_LENGTH) | 197 BM_SSP_CTRL1_DMA_ENABLE | 198 BM_SSP_CTRL1_POLARITY | 199 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN | 200 BM_SSP_CTRL1_DATA_CRC_IRQ_EN | 201 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN | 202 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN | 203 BM_SSP_CTRL1_RESP_ERR_IRQ_EN; 204 205 writel(BF_SSP(0xffff, TIMING_TIMEOUT) | 206 BF_SSP(2, TIMING_CLOCK_DIVIDE) | 207 BF_SSP(0, TIMING_CLOCK_RATE), 208 host->base + HW_SSP_TIMING); 209 210 if (host->sdio_irq_en) { 211 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 212 ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN; 213 } 214 215 writel(ctrl0, host->base + HW_SSP_CTRL0); 216 writel(ctrl1, host->base + HW_SSP_CTRL1); 217 } 218 219 static void mxs_mmc_start_cmd(struct mxs_mmc_host *host, 220 struct mmc_command *cmd); 221 222 static void mxs_mmc_request_done(struct mxs_mmc_host *host) 223 { 224 struct mmc_command *cmd = host->cmd; 225 struct mmc_data *data = host->data; 226 struct mmc_request *mrq = host->mrq; 227 228 if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) { 229 if (mmc_resp_type(cmd) & MMC_RSP_136) { 230 cmd->resp[3] = readl(host->base + HW_SSP_SDRESP0); 231 cmd->resp[2] = readl(host->base + HW_SSP_SDRESP1); 232 cmd->resp[1] = readl(host->base + HW_SSP_SDRESP2); 233 cmd->resp[0] = readl(host->base + HW_SSP_SDRESP3); 234 } else { 235 cmd->resp[0] = readl(host->base + HW_SSP_SDRESP0); 236 } 237 } 238 239 if (data) { 240 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 241 data->sg_len, host->dma_dir); 242 /* 243 * If there was an error on any block, we mark all 244 * data blocks as being in error. 245 */ 246 if (!data->error) 247 data->bytes_xfered = data->blocks * data->blksz; 248 else 249 data->bytes_xfered = 0; 250 251 host->data = NULL; 252 if (mrq->stop) { 253 mxs_mmc_start_cmd(host, mrq->stop); 254 return; 255 } 256 } 257 258 host->mrq = NULL; 259 mmc_request_done(host->mmc, mrq); 260 } 261 262 static void mxs_mmc_dma_irq_callback(void *param) 263 { 264 struct mxs_mmc_host *host = param; 265 266 mxs_mmc_request_done(host); 267 } 268 269 static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id) 270 { 271 struct mxs_mmc_host *host = dev_id; 272 struct mmc_command *cmd = host->cmd; 273 struct mmc_data *data = host->data; 274 u32 stat; 275 276 spin_lock(&host->lock); 277 278 stat = readl(host->base + HW_SSP_CTRL1); 279 writel(stat & MXS_MMC_IRQ_BITS, 280 host->base + HW_SSP_CTRL1 + MXS_CLR_ADDR); 281 282 if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN)) 283 mmc_signal_sdio_irq(host->mmc); 284 285 spin_unlock(&host->lock); 286 287 if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ) 288 cmd->error = -ETIMEDOUT; 289 else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ) 290 cmd->error = -EIO; 291 292 if (data) { 293 if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | 294 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ)) 295 data->error = -ETIMEDOUT; 296 else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ) 297 data->error = -EILSEQ; 298 else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | 299 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)) 300 data->error = -EIO; 301 } 302 303 return IRQ_HANDLED; 304 } 305 306 static struct dma_async_tx_descriptor *mxs_mmc_prep_dma( 307 struct mxs_mmc_host *host, unsigned int append) 308 { 309 struct dma_async_tx_descriptor *desc; 310 struct mmc_data *data = host->data; 311 struct scatterlist * sgl; 312 unsigned int sg_len; 313 314 if (data) { 315 /* data */ 316 dma_map_sg(mmc_dev(host->mmc), data->sg, 317 data->sg_len, host->dma_dir); 318 sgl = data->sg; 319 sg_len = data->sg_len; 320 } else { 321 /* pio */ 322 sgl = (struct scatterlist *) host->ssp_pio_words; 323 sg_len = SSP_PIO_NUM; 324 } 325 326 desc = host->dmach->device->device_prep_slave_sg(host->dmach, 327 sgl, sg_len, host->dma_dir, append); 328 if (desc) { 329 desc->callback = mxs_mmc_dma_irq_callback; 330 desc->callback_param = host; 331 } else { 332 if (data) 333 dma_unmap_sg(mmc_dev(host->mmc), data->sg, 334 data->sg_len, host->dma_dir); 335 } 336 337 return desc; 338 } 339 340 static void mxs_mmc_bc(struct mxs_mmc_host *host) 341 { 342 struct mmc_command *cmd = host->cmd; 343 struct dma_async_tx_descriptor *desc; 344 u32 ctrl0, cmd0, cmd1; 345 346 ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC; 347 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC; 348 cmd1 = cmd->arg; 349 350 if (host->sdio_irq_en) { 351 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 352 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 353 } 354 355 host->ssp_pio_words[0] = ctrl0; 356 host->ssp_pio_words[1] = cmd0; 357 host->ssp_pio_words[2] = cmd1; 358 host->dma_dir = DMA_NONE; 359 desc = mxs_mmc_prep_dma(host, 0); 360 if (!desc) 361 goto out; 362 363 dmaengine_submit(desc); 364 return; 365 366 out: 367 dev_warn(mmc_dev(host->mmc), 368 "%s: failed to prep dma\n", __func__); 369 } 370 371 static void mxs_mmc_ac(struct mxs_mmc_host *host) 372 { 373 struct mmc_command *cmd = host->cmd; 374 struct dma_async_tx_descriptor *desc; 375 u32 ignore_crc, get_resp, long_resp; 376 u32 ctrl0, cmd0, cmd1; 377 378 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ? 379 0 : BM_SSP_CTRL0_IGNORE_CRC; 380 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ? 381 BM_SSP_CTRL0_GET_RESP : 0; 382 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ? 383 BM_SSP_CTRL0_LONG_RESP : 0; 384 385 ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp; 386 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD); 387 cmd1 = cmd->arg; 388 389 if (host->sdio_irq_en) { 390 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 391 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 392 } 393 394 host->ssp_pio_words[0] = ctrl0; 395 host->ssp_pio_words[1] = cmd0; 396 host->ssp_pio_words[2] = cmd1; 397 host->dma_dir = DMA_NONE; 398 desc = mxs_mmc_prep_dma(host, 0); 399 if (!desc) 400 goto out; 401 402 dmaengine_submit(desc); 403 return; 404 405 out: 406 dev_warn(mmc_dev(host->mmc), 407 "%s: failed to prep dma\n", __func__); 408 } 409 410 static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns) 411 { 412 const unsigned int ssp_timeout_mul = 4096; 413 /* 414 * Calculate ticks in ms since ns are large numbers 415 * and might overflow 416 */ 417 const unsigned int clock_per_ms = clock_rate / 1000; 418 const unsigned int ms = ns / 1000; 419 const unsigned int ticks = ms * clock_per_ms; 420 const unsigned int ssp_ticks = ticks / ssp_timeout_mul; 421 422 WARN_ON(ssp_ticks == 0); 423 return ssp_ticks; 424 } 425 426 static void mxs_mmc_adtc(struct mxs_mmc_host *host) 427 { 428 struct mmc_command *cmd = host->cmd; 429 struct mmc_data *data = cmd->data; 430 struct dma_async_tx_descriptor *desc; 431 struct scatterlist *sgl = data->sg, *sg; 432 unsigned int sg_len = data->sg_len; 433 int i; 434 435 unsigned short dma_data_dir, timeout; 436 unsigned int data_size = 0, log2_blksz; 437 unsigned int blocks = data->blocks; 438 439 u32 ignore_crc, get_resp, long_resp, read; 440 u32 ctrl0, cmd0, cmd1, val; 441 442 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ? 443 0 : BM_SSP_CTRL0_IGNORE_CRC; 444 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ? 445 BM_SSP_CTRL0_GET_RESP : 0; 446 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ? 447 BM_SSP_CTRL0_LONG_RESP : 0; 448 449 if (data->flags & MMC_DATA_WRITE) { 450 dma_data_dir = DMA_TO_DEVICE; 451 read = 0; 452 } else { 453 dma_data_dir = DMA_FROM_DEVICE; 454 read = BM_SSP_CTRL0_READ; 455 } 456 457 ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) | 458 ignore_crc | get_resp | long_resp | 459 BM_SSP_CTRL0_DATA_XFER | read | 460 BM_SSP_CTRL0_WAIT_FOR_IRQ | 461 BM_SSP_CTRL0_ENABLE; 462 463 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD); 464 465 /* get logarithm to base 2 of block size for setting register */ 466 log2_blksz = ilog2(data->blksz); 467 468 /* 469 * take special care of the case that data size from data->sg 470 * is not equal to blocks x blksz 471 */ 472 for_each_sg(sgl, sg, sg_len, i) 473 data_size += sg->length; 474 475 if (data_size != data->blocks * data->blksz) 476 blocks = 1; 477 478 /* xfer count, block size and count need to be set differently */ 479 if (ssp_is_old()) { 480 ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT); 481 cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) | 482 BF_SSP(blocks - 1, CMD0_BLOCK_COUNT); 483 } else { 484 writel(data_size, host->base + HW_SSP_XFER_SIZE); 485 writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) | 486 BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT), 487 host->base + HW_SSP_BLOCK_SIZE); 488 } 489 490 if ((cmd->opcode == MMC_STOP_TRANSMISSION) || 491 (cmd->opcode == SD_IO_RW_EXTENDED)) 492 cmd0 |= BM_SSP_CMD0_APPEND_8CYC; 493 494 cmd1 = cmd->arg; 495 496 if (host->sdio_irq_en) { 497 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 498 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 499 } 500 501 /* set the timeout count */ 502 timeout = mxs_ns_to_ssp_ticks(host->clk_rate, data->timeout_ns); 503 val = readl(host->base + HW_SSP_TIMING); 504 val &= ~(BM_SSP_TIMING_TIMEOUT); 505 val |= BF_SSP(timeout, TIMING_TIMEOUT); 506 writel(val, host->base + HW_SSP_TIMING); 507 508 /* pio */ 509 host->ssp_pio_words[0] = ctrl0; 510 host->ssp_pio_words[1] = cmd0; 511 host->ssp_pio_words[2] = cmd1; 512 host->dma_dir = DMA_NONE; 513 desc = mxs_mmc_prep_dma(host, 0); 514 if (!desc) 515 goto out; 516 517 /* append data sg */ 518 WARN_ON(host->data != NULL); 519 host->data = data; 520 host->dma_dir = dma_data_dir; 521 desc = mxs_mmc_prep_dma(host, 1); 522 if (!desc) 523 goto out; 524 525 dmaengine_submit(desc); 526 return; 527 out: 528 dev_warn(mmc_dev(host->mmc), 529 "%s: failed to prep dma\n", __func__); 530 } 531 532 static void mxs_mmc_start_cmd(struct mxs_mmc_host *host, 533 struct mmc_command *cmd) 534 { 535 host->cmd = cmd; 536 537 switch (mmc_cmd_type(cmd)) { 538 case MMC_CMD_BC: 539 mxs_mmc_bc(host); 540 break; 541 case MMC_CMD_BCR: 542 mxs_mmc_ac(host); 543 break; 544 case MMC_CMD_AC: 545 mxs_mmc_ac(host); 546 break; 547 case MMC_CMD_ADTC: 548 mxs_mmc_adtc(host); 549 break; 550 default: 551 dev_warn(mmc_dev(host->mmc), 552 "%s: unknown MMC command\n", __func__); 553 break; 554 } 555 } 556 557 static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 558 { 559 struct mxs_mmc_host *host = mmc_priv(mmc); 560 561 WARN_ON(host->mrq != NULL); 562 host->mrq = mrq; 563 mxs_mmc_start_cmd(host, mrq->cmd); 564 } 565 566 static void mxs_mmc_set_clk_rate(struct mxs_mmc_host *host, unsigned int rate) 567 { 568 unsigned int ssp_clk, ssp_sck; 569 u32 clock_divide, clock_rate; 570 u32 val; 571 572 ssp_clk = clk_get_rate(host->clk); 573 574 for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) { 575 clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide); 576 clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0; 577 if (clock_rate <= 255) 578 break; 579 } 580 581 if (clock_divide > 254) { 582 dev_err(mmc_dev(host->mmc), 583 "%s: cannot set clock to %d\n", __func__, rate); 584 return; 585 } 586 587 ssp_sck = ssp_clk / clock_divide / (1 + clock_rate); 588 589 val = readl(host->base + HW_SSP_TIMING); 590 val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE); 591 val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE); 592 val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE); 593 writel(val, host->base + HW_SSP_TIMING); 594 595 host->clk_rate = ssp_sck; 596 597 dev_dbg(mmc_dev(host->mmc), 598 "%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n", 599 __func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate); 600 } 601 602 static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 603 { 604 struct mxs_mmc_host *host = mmc_priv(mmc); 605 606 if (ios->bus_width == MMC_BUS_WIDTH_8) 607 host->bus_width = 2; 608 else if (ios->bus_width == MMC_BUS_WIDTH_4) 609 host->bus_width = 1; 610 else 611 host->bus_width = 0; 612 613 if (ios->clock) 614 mxs_mmc_set_clk_rate(host, ios->clock); 615 } 616 617 static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 618 { 619 struct mxs_mmc_host *host = mmc_priv(mmc); 620 unsigned long flags; 621 622 spin_lock_irqsave(&host->lock, flags); 623 624 host->sdio_irq_en = enable; 625 626 if (enable) { 627 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, 628 host->base + HW_SSP_CTRL0 + MXS_SET_ADDR); 629 writel(BM_SSP_CTRL1_SDIO_IRQ_EN, 630 host->base + HW_SSP_CTRL1 + MXS_SET_ADDR); 631 632 if (readl(host->base + HW_SSP_STATUS) & BM_SSP_STATUS_SDIO_IRQ) 633 mmc_signal_sdio_irq(host->mmc); 634 635 } else { 636 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, 637 host->base + HW_SSP_CTRL0 + MXS_CLR_ADDR); 638 writel(BM_SSP_CTRL1_SDIO_IRQ_EN, 639 host->base + HW_SSP_CTRL1 + MXS_CLR_ADDR); 640 } 641 642 spin_unlock_irqrestore(&host->lock, flags); 643 } 644 645 static const struct mmc_host_ops mxs_mmc_ops = { 646 .request = mxs_mmc_request, 647 .get_ro = mxs_mmc_get_ro, 648 .get_cd = mxs_mmc_get_cd, 649 .set_ios = mxs_mmc_set_ios, 650 .enable_sdio_irq = mxs_mmc_enable_sdio_irq, 651 }; 652 653 static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param) 654 { 655 struct mxs_mmc_host *host = param; 656 657 if (!mxs_dma_is_apbh(chan)) 658 return false; 659 660 if (chan->chan_id != host->dma_res->start) 661 return false; 662 663 chan->private = &host->dma_data; 664 665 return true; 666 } 667 668 static int mxs_mmc_probe(struct platform_device *pdev) 669 { 670 struct mxs_mmc_host *host; 671 struct mmc_host *mmc; 672 struct resource *iores, *dmares, *r; 673 struct mxs_mmc_platform_data *pdata; 674 int ret = 0, irq_err, irq_dma; 675 dma_cap_mask_t mask; 676 677 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 678 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0); 679 irq_err = platform_get_irq(pdev, 0); 680 irq_dma = platform_get_irq(pdev, 1); 681 if (!iores || !dmares || irq_err < 0 || irq_dma < 0) 682 return -EINVAL; 683 684 r = request_mem_region(iores->start, resource_size(iores), pdev->name); 685 if (!r) 686 return -EBUSY; 687 688 mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev); 689 if (!mmc) { 690 ret = -ENOMEM; 691 goto out_release_mem; 692 } 693 694 host = mmc_priv(mmc); 695 host->base = ioremap(r->start, resource_size(r)); 696 if (!host->base) { 697 ret = -ENOMEM; 698 goto out_mmc_free; 699 } 700 701 /* only major verion does matter */ 702 host->version = readl(host->base + HW_SSP_VERSION) >> 703 BP_SSP_VERSION_MAJOR; 704 705 host->mmc = mmc; 706 host->res = r; 707 host->dma_res = dmares; 708 host->irq = irq_err; 709 host->sdio_irq_en = 0; 710 711 host->clk = clk_get(&pdev->dev, NULL); 712 if (IS_ERR(host->clk)) { 713 ret = PTR_ERR(host->clk); 714 goto out_iounmap; 715 } 716 clk_enable(host->clk); 717 718 mxs_mmc_reset(host); 719 720 dma_cap_zero(mask); 721 dma_cap_set(DMA_SLAVE, mask); 722 host->dma_data.chan_irq = irq_dma; 723 host->dmach = dma_request_channel(mask, mxs_mmc_dma_filter, host); 724 if (!host->dmach) { 725 dev_err(mmc_dev(host->mmc), 726 "%s: failed to request dma\n", __func__); 727 goto out_clk_put; 728 } 729 730 /* set mmc core parameters */ 731 mmc->ops = &mxs_mmc_ops; 732 mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 733 MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL; 734 735 pdata = mmc_dev(host->mmc)->platform_data; 736 if (pdata) { 737 if (pdata->flags & SLOTF_8_BIT_CAPABLE) 738 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA; 739 if (pdata->flags & SLOTF_4_BIT_CAPABLE) 740 mmc->caps |= MMC_CAP_4_BIT_DATA; 741 } 742 743 mmc->f_min = 400000; 744 mmc->f_max = 288000000; 745 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 746 747 mmc->max_segs = 52; 748 mmc->max_blk_size = 1 << 0xf; 749 mmc->max_blk_count = (ssp_is_old()) ? 0xff : 0xffffff; 750 mmc->max_req_size = (ssp_is_old()) ? 0xffff : 0xffffffff; 751 mmc->max_seg_size = dma_get_max_seg_size(host->dmach->device->dev); 752 753 platform_set_drvdata(pdev, mmc); 754 755 ret = request_irq(host->irq, mxs_mmc_irq_handler, 0, DRIVER_NAME, host); 756 if (ret) 757 goto out_free_dma; 758 759 spin_lock_init(&host->lock); 760 761 ret = mmc_add_host(mmc); 762 if (ret) 763 goto out_free_irq; 764 765 dev_info(mmc_dev(host->mmc), "initialized\n"); 766 767 return 0; 768 769 out_free_irq: 770 free_irq(host->irq, host); 771 out_free_dma: 772 if (host->dmach) 773 dma_release_channel(host->dmach); 774 out_clk_put: 775 clk_disable(host->clk); 776 clk_put(host->clk); 777 out_iounmap: 778 iounmap(host->base); 779 out_mmc_free: 780 mmc_free_host(mmc); 781 out_release_mem: 782 release_mem_region(iores->start, resource_size(iores)); 783 return ret; 784 } 785 786 static int mxs_mmc_remove(struct platform_device *pdev) 787 { 788 struct mmc_host *mmc = platform_get_drvdata(pdev); 789 struct mxs_mmc_host *host = mmc_priv(mmc); 790 struct resource *res = host->res; 791 792 mmc_remove_host(mmc); 793 794 free_irq(host->irq, host); 795 796 platform_set_drvdata(pdev, NULL); 797 798 if (host->dmach) 799 dma_release_channel(host->dmach); 800 801 clk_disable(host->clk); 802 clk_put(host->clk); 803 804 iounmap(host->base); 805 806 mmc_free_host(mmc); 807 808 release_mem_region(res->start, resource_size(res)); 809 810 return 0; 811 } 812 813 #ifdef CONFIG_PM 814 static int mxs_mmc_suspend(struct device *dev) 815 { 816 struct mmc_host *mmc = dev_get_drvdata(dev); 817 struct mxs_mmc_host *host = mmc_priv(mmc); 818 int ret = 0; 819 820 ret = mmc_suspend_host(mmc); 821 822 clk_disable(host->clk); 823 824 return ret; 825 } 826 827 static int mxs_mmc_resume(struct device *dev) 828 { 829 struct mmc_host *mmc = dev_get_drvdata(dev); 830 struct mxs_mmc_host *host = mmc_priv(mmc); 831 int ret = 0; 832 833 clk_enable(host->clk); 834 835 ret = mmc_resume_host(mmc); 836 837 return ret; 838 } 839 840 static const struct dev_pm_ops mxs_mmc_pm_ops = { 841 .suspend = mxs_mmc_suspend, 842 .resume = mxs_mmc_resume, 843 }; 844 #endif 845 846 static struct platform_driver mxs_mmc_driver = { 847 .probe = mxs_mmc_probe, 848 .remove = mxs_mmc_remove, 849 .driver = { 850 .name = DRIVER_NAME, 851 .owner = THIS_MODULE, 852 #ifdef CONFIG_PM 853 .pm = &mxs_mmc_pm_ops, 854 #endif 855 }, 856 }; 857 858 static int __init mxs_mmc_init(void) 859 { 860 return platform_driver_register(&mxs_mmc_driver); 861 } 862 863 static void __exit mxs_mmc_exit(void) 864 { 865 platform_driver_unregister(&mxs_mmc_driver); 866 } 867 868 module_init(mxs_mmc_init); 869 module_exit(mxs_mmc_exit); 870 871 MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral"); 872 MODULE_AUTHOR("Freescale Semiconductor"); 873 MODULE_LICENSE("GPL"); 874