1e4243f13SShawn Guo /* 2e4243f13SShawn Guo * Portions copyright (C) 2003 Russell King, PXA MMCI Driver 3e4243f13SShawn Guo * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver 4e4243f13SShawn Guo * 5e4243f13SShawn Guo * Copyright 2008 Embedded Alley Solutions, Inc. 6e4243f13SShawn Guo * Copyright 2009-2011 Freescale Semiconductor, Inc. 7e4243f13SShawn Guo * 8e4243f13SShawn Guo * This program is free software; you can redistribute it and/or modify 9e4243f13SShawn Guo * it under the terms of the GNU General Public License as published by 10e4243f13SShawn Guo * the Free Software Foundation; either version 2 of the License, or 11e4243f13SShawn Guo * (at your option) any later version. 12e4243f13SShawn Guo * 13e4243f13SShawn Guo * This program is distributed in the hope that it will be useful, 14e4243f13SShawn Guo * but WITHOUT ANY WARRANTY; without even the implied warranty of 15e4243f13SShawn Guo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16e4243f13SShawn Guo * GNU General Public License for more details. 17e4243f13SShawn Guo * 18e4243f13SShawn Guo * You should have received a copy of the GNU General Public License along 19e4243f13SShawn Guo * with this program; if not, write to the Free Software Foundation, Inc., 20e4243f13SShawn Guo * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 21e4243f13SShawn Guo */ 22e4243f13SShawn Guo 23e4243f13SShawn Guo #include <linux/kernel.h> 24e4243f13SShawn Guo #include <linux/init.h> 25e4243f13SShawn Guo #include <linux/ioport.h> 266de4d817SShawn Guo #include <linux/of.h> 276de4d817SShawn Guo #include <linux/of_device.h> 286de4d817SShawn Guo #include <linux/of_gpio.h> 29e4243f13SShawn Guo #include <linux/platform_device.h> 30e4243f13SShawn Guo #include <linux/delay.h> 31e4243f13SShawn Guo #include <linux/interrupt.h> 32e4243f13SShawn Guo #include <linux/dma-mapping.h> 33e4243f13SShawn Guo #include <linux/dmaengine.h> 34e4243f13SShawn Guo #include <linux/highmem.h> 35e4243f13SShawn Guo #include <linux/clk.h> 36e4243f13SShawn Guo #include <linux/err.h> 37e4243f13SShawn Guo #include <linux/completion.h> 38e4243f13SShawn Guo #include <linux/mmc/host.h> 39e4243f13SShawn Guo #include <linux/mmc/mmc.h> 40e4243f13SShawn Guo #include <linux/mmc/sdio.h> 41e4243f13SShawn Guo #include <linux/gpio.h> 42e4243f13SShawn Guo #include <linux/regulator/consumer.h> 4388b47679SPaul Gortmaker #include <linux/module.h> 4439468604SHuang Shijie #include <linux/fsl/mxs-dma.h> 459c92cf24SShawn Guo #include <linux/pinctrl/consumer.h> 4670e60206SShawn Guo #include <linux/stmp_device.h> 4781f38ee8SShawn Guo #include <linux/mmc/mxs-mmc.h> 48e4243f13SShawn Guo 49e4243f13SShawn Guo #define DRIVER_NAME "mxs-mmc" 50e4243f13SShawn Guo 51e4243f13SShawn Guo /* card detect polling timeout */ 52e4243f13SShawn Guo #define MXS_MMC_DETECT_TIMEOUT (HZ/2) 53e4243f13SShawn Guo 54ef9b4d39SShawn Guo #define ssp_is_old(host) ((host)->devid == IMX23_MMC) 55e4243f13SShawn Guo 56e4243f13SShawn Guo /* SSP registers */ 57e4243f13SShawn Guo #define HW_SSP_CTRL0 0x000 58e4243f13SShawn Guo #define BM_SSP_CTRL0_RUN (1 << 29) 59e4243f13SShawn Guo #define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28) 60e4243f13SShawn Guo #define BM_SSP_CTRL0_IGNORE_CRC (1 << 26) 61e4243f13SShawn Guo #define BM_SSP_CTRL0_READ (1 << 25) 62e4243f13SShawn Guo #define BM_SSP_CTRL0_DATA_XFER (1 << 24) 63e4243f13SShawn Guo #define BP_SSP_CTRL0_BUS_WIDTH (22) 64e4243f13SShawn Guo #define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22) 65e4243f13SShawn Guo #define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21) 66e4243f13SShawn Guo #define BM_SSP_CTRL0_LONG_RESP (1 << 19) 67e4243f13SShawn Guo #define BM_SSP_CTRL0_GET_RESP (1 << 17) 68e4243f13SShawn Guo #define BM_SSP_CTRL0_ENABLE (1 << 16) 69e4243f13SShawn Guo #define BP_SSP_CTRL0_XFER_COUNT (0) 70e4243f13SShawn Guo #define BM_SSP_CTRL0_XFER_COUNT (0xffff) 71e4243f13SShawn Guo #define HW_SSP_CMD0 0x010 72e4243f13SShawn Guo #define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25) 73e4243f13SShawn Guo #define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22) 74e4243f13SShawn Guo #define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21) 75e4243f13SShawn Guo #define BM_SSP_CMD0_APPEND_8CYC (1 << 20) 76e4243f13SShawn Guo #define BP_SSP_CMD0_BLOCK_SIZE (16) 77e4243f13SShawn Guo #define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16) 78e4243f13SShawn Guo #define BP_SSP_CMD0_BLOCK_COUNT (8) 79e4243f13SShawn Guo #define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8) 80e4243f13SShawn Guo #define BP_SSP_CMD0_CMD (0) 81e4243f13SShawn Guo #define BM_SSP_CMD0_CMD (0xff) 82e4243f13SShawn Guo #define HW_SSP_CMD1 0x020 83e4243f13SShawn Guo #define HW_SSP_XFER_SIZE 0x030 84e4243f13SShawn Guo #define HW_SSP_BLOCK_SIZE 0x040 85e4243f13SShawn Guo #define BP_SSP_BLOCK_SIZE_BLOCK_COUNT (4) 86e4243f13SShawn Guo #define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4) 87e4243f13SShawn Guo #define BP_SSP_BLOCK_SIZE_BLOCK_SIZE (0) 88e4243f13SShawn Guo #define BM_SSP_BLOCK_SIZE_BLOCK_SIZE (0xf) 89e0bf141dSShawn Guo #define HW_SSP_TIMING(h) (ssp_is_old(h) ? 0x050 : 0x070) 90e4243f13SShawn Guo #define BP_SSP_TIMING_TIMEOUT (16) 91e4243f13SShawn Guo #define BM_SSP_TIMING_TIMEOUT (0xffff << 16) 92e4243f13SShawn Guo #define BP_SSP_TIMING_CLOCK_DIVIDE (8) 93e4243f13SShawn Guo #define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8) 94e4243f13SShawn Guo #define BP_SSP_TIMING_CLOCK_RATE (0) 95e4243f13SShawn Guo #define BM_SSP_TIMING_CLOCK_RATE (0xff) 96e0bf141dSShawn Guo #define HW_SSP_CTRL1(h) (ssp_is_old(h) ? 0x060 : 0x080) 97e4243f13SShawn Guo #define BM_SSP_CTRL1_SDIO_IRQ (1 << 31) 98e4243f13SShawn Guo #define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30) 99e4243f13SShawn Guo #define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29) 100e4243f13SShawn Guo #define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28) 101e4243f13SShawn Guo #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27) 102e4243f13SShawn Guo #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26) 103e4243f13SShawn Guo #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25) 104e4243f13SShawn Guo #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24) 105e4243f13SShawn Guo #define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23) 106e4243f13SShawn Guo #define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22) 107e4243f13SShawn Guo #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21) 108e4243f13SShawn Guo #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20) 109e4243f13SShawn Guo #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17) 110e4243f13SShawn Guo #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16) 111e4243f13SShawn Guo #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15) 112e4243f13SShawn Guo #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14) 113e4243f13SShawn Guo #define BM_SSP_CTRL1_DMA_ENABLE (1 << 13) 114e4243f13SShawn Guo #define BM_SSP_CTRL1_POLARITY (1 << 9) 115e4243f13SShawn Guo #define BP_SSP_CTRL1_WORD_LENGTH (4) 116e4243f13SShawn Guo #define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4) 117e4243f13SShawn Guo #define BP_SSP_CTRL1_SSP_MODE (0) 118e4243f13SShawn Guo #define BM_SSP_CTRL1_SSP_MODE (0xf) 119e0bf141dSShawn Guo #define HW_SSP_SDRESP0(h) (ssp_is_old(h) ? 0x080 : 0x0a0) 120e0bf141dSShawn Guo #define HW_SSP_SDRESP1(h) (ssp_is_old(h) ? 0x090 : 0x0b0) 121e0bf141dSShawn Guo #define HW_SSP_SDRESP2(h) (ssp_is_old(h) ? 0x0a0 : 0x0c0) 122e0bf141dSShawn Guo #define HW_SSP_SDRESP3(h) (ssp_is_old(h) ? 0x0b0 : 0x0d0) 123e0bf141dSShawn Guo #define HW_SSP_STATUS(h) (ssp_is_old(h) ? 0x0c0 : 0x100) 124e4243f13SShawn Guo #define BM_SSP_STATUS_CARD_DETECT (1 << 28) 125e4243f13SShawn Guo #define BM_SSP_STATUS_SDIO_IRQ (1 << 17) 126e4243f13SShawn Guo 127e4243f13SShawn Guo #define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field) 128e4243f13SShawn Guo 129e4243f13SShawn Guo #define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \ 130e4243f13SShawn Guo BM_SSP_CTRL1_RESP_ERR_IRQ | \ 131e4243f13SShawn Guo BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \ 132e4243f13SShawn Guo BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \ 133e4243f13SShawn Guo BM_SSP_CTRL1_DATA_CRC_IRQ | \ 134e4243f13SShawn Guo BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \ 135e4243f13SShawn Guo BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \ 136e4243f13SShawn Guo BM_SSP_CTRL1_FIFO_OVERRUN_IRQ) 137e4243f13SShawn Guo 138e4243f13SShawn Guo #define SSP_PIO_NUM 3 139e4243f13SShawn Guo 140ef9b4d39SShawn Guo enum mxs_mmc_id { 141ef9b4d39SShawn Guo IMX23_MMC, 142ef9b4d39SShawn Guo IMX28_MMC, 143ef9b4d39SShawn Guo }; 144ef9b4d39SShawn Guo 145e4243f13SShawn Guo struct mxs_mmc_host { 146e4243f13SShawn Guo struct mmc_host *mmc; 147e4243f13SShawn Guo struct mmc_request *mrq; 148e4243f13SShawn Guo struct mmc_command *cmd; 149e4243f13SShawn Guo struct mmc_data *data; 150e4243f13SShawn Guo 151e4243f13SShawn Guo void __iomem *base; 152b60188c8SShawn Guo int dma_channel; 153e4243f13SShawn Guo struct clk *clk; 154e4243f13SShawn Guo unsigned int clk_rate; 155e4243f13SShawn Guo 156e4243f13SShawn Guo struct dma_chan *dmach; 157e4243f13SShawn Guo struct mxs_dma_data dma_data; 158e4243f13SShawn Guo unsigned int dma_dir; 15905f5799cSVinod Koul enum dma_transfer_direction slave_dirn; 160e4243f13SShawn Guo u32 ssp_pio_words[SSP_PIO_NUM]; 161e4243f13SShawn Guo 162ef9b4d39SShawn Guo enum mxs_mmc_id devid; 163e4243f13SShawn Guo unsigned char bus_width; 164e4243f13SShawn Guo spinlock_t lock; 165e4243f13SShawn Guo int sdio_irq_en; 16631b0ff5eSShawn Guo int wp_gpio; 167b6e76f10SMarek Vasut bool wp_inverted; 168e4243f13SShawn Guo }; 169e4243f13SShawn Guo 170e4243f13SShawn Guo static int mxs_mmc_get_ro(struct mmc_host *mmc) 171e4243f13SShawn Guo { 172e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 173b6e76f10SMarek Vasut int ret; 174e4243f13SShawn Guo 17531b0ff5eSShawn Guo if (!gpio_is_valid(host->wp_gpio)) 176e4243f13SShawn Guo return -EINVAL; 177e4243f13SShawn Guo 178b6e76f10SMarek Vasut ret = gpio_get_value(host->wp_gpio); 179b6e76f10SMarek Vasut 180b6e76f10SMarek Vasut if (host->wp_inverted) 181b6e76f10SMarek Vasut ret = !ret; 182b6e76f10SMarek Vasut 183b6e76f10SMarek Vasut return ret; 184e4243f13SShawn Guo } 185e4243f13SShawn Guo 186e4243f13SShawn Guo static int mxs_mmc_get_cd(struct mmc_host *mmc) 187e4243f13SShawn Guo { 188e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 189e4243f13SShawn Guo 190e0bf141dSShawn Guo return !(readl(host->base + HW_SSP_STATUS(host)) & 191e4243f13SShawn Guo BM_SSP_STATUS_CARD_DETECT); 192e4243f13SShawn Guo } 193e4243f13SShawn Guo 194e4243f13SShawn Guo static void mxs_mmc_reset(struct mxs_mmc_host *host) 195e4243f13SShawn Guo { 196e4243f13SShawn Guo u32 ctrl0, ctrl1; 197e4243f13SShawn Guo 19870e60206SShawn Guo stmp_reset_block(host->base); 199e4243f13SShawn Guo 200e4243f13SShawn Guo ctrl0 = BM_SSP_CTRL0_IGNORE_CRC; 201e4243f13SShawn Guo ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) | 202e4243f13SShawn Guo BF_SSP(0x7, CTRL1_WORD_LENGTH) | 203e4243f13SShawn Guo BM_SSP_CTRL1_DMA_ENABLE | 204e4243f13SShawn Guo BM_SSP_CTRL1_POLARITY | 205e4243f13SShawn Guo BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN | 206e4243f13SShawn Guo BM_SSP_CTRL1_DATA_CRC_IRQ_EN | 207e4243f13SShawn Guo BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN | 208e4243f13SShawn Guo BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN | 209e4243f13SShawn Guo BM_SSP_CTRL1_RESP_ERR_IRQ_EN; 210e4243f13SShawn Guo 211e4243f13SShawn Guo writel(BF_SSP(0xffff, TIMING_TIMEOUT) | 212e4243f13SShawn Guo BF_SSP(2, TIMING_CLOCK_DIVIDE) | 213e4243f13SShawn Guo BF_SSP(0, TIMING_CLOCK_RATE), 214e0bf141dSShawn Guo host->base + HW_SSP_TIMING(host)); 215e4243f13SShawn Guo 216e4243f13SShawn Guo if (host->sdio_irq_en) { 217e4243f13SShawn Guo ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 218e4243f13SShawn Guo ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN; 219e4243f13SShawn Guo } 220e4243f13SShawn Guo 221e4243f13SShawn Guo writel(ctrl0, host->base + HW_SSP_CTRL0); 222e0bf141dSShawn Guo writel(ctrl1, host->base + HW_SSP_CTRL1(host)); 223e4243f13SShawn Guo } 224e4243f13SShawn Guo 225e4243f13SShawn Guo static void mxs_mmc_start_cmd(struct mxs_mmc_host *host, 226e4243f13SShawn Guo struct mmc_command *cmd); 227e4243f13SShawn Guo 228e4243f13SShawn Guo static void mxs_mmc_request_done(struct mxs_mmc_host *host) 229e4243f13SShawn Guo { 230e4243f13SShawn Guo struct mmc_command *cmd = host->cmd; 231e4243f13SShawn Guo struct mmc_data *data = host->data; 232e4243f13SShawn Guo struct mmc_request *mrq = host->mrq; 233e4243f13SShawn Guo 234e4243f13SShawn Guo if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) { 235e4243f13SShawn Guo if (mmc_resp_type(cmd) & MMC_RSP_136) { 236e0bf141dSShawn Guo cmd->resp[3] = readl(host->base + HW_SSP_SDRESP0(host)); 237e0bf141dSShawn Guo cmd->resp[2] = readl(host->base + HW_SSP_SDRESP1(host)); 238e0bf141dSShawn Guo cmd->resp[1] = readl(host->base + HW_SSP_SDRESP2(host)); 239e0bf141dSShawn Guo cmd->resp[0] = readl(host->base + HW_SSP_SDRESP3(host)); 240e4243f13SShawn Guo } else { 241e0bf141dSShawn Guo cmd->resp[0] = readl(host->base + HW_SSP_SDRESP0(host)); 242e4243f13SShawn Guo } 243e4243f13SShawn Guo } 244e4243f13SShawn Guo 245e4243f13SShawn Guo if (data) { 246e4243f13SShawn Guo dma_unmap_sg(mmc_dev(host->mmc), data->sg, 247e4243f13SShawn Guo data->sg_len, host->dma_dir); 248e4243f13SShawn Guo /* 249e4243f13SShawn Guo * If there was an error on any block, we mark all 250e4243f13SShawn Guo * data blocks as being in error. 251e4243f13SShawn Guo */ 252e4243f13SShawn Guo if (!data->error) 253e4243f13SShawn Guo data->bytes_xfered = data->blocks * data->blksz; 254e4243f13SShawn Guo else 255e4243f13SShawn Guo data->bytes_xfered = 0; 256e4243f13SShawn Guo 257e4243f13SShawn Guo host->data = NULL; 258e4243f13SShawn Guo if (mrq->stop) { 259e4243f13SShawn Guo mxs_mmc_start_cmd(host, mrq->stop); 260e4243f13SShawn Guo return; 261e4243f13SShawn Guo } 262e4243f13SShawn Guo } 263e4243f13SShawn Guo 264e4243f13SShawn Guo host->mrq = NULL; 265e4243f13SShawn Guo mmc_request_done(host->mmc, mrq); 266e4243f13SShawn Guo } 267e4243f13SShawn Guo 268e4243f13SShawn Guo static void mxs_mmc_dma_irq_callback(void *param) 269e4243f13SShawn Guo { 270e4243f13SShawn Guo struct mxs_mmc_host *host = param; 271e4243f13SShawn Guo 272e4243f13SShawn Guo mxs_mmc_request_done(host); 273e4243f13SShawn Guo } 274e4243f13SShawn Guo 275e4243f13SShawn Guo static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id) 276e4243f13SShawn Guo { 277e4243f13SShawn Guo struct mxs_mmc_host *host = dev_id; 278e4243f13SShawn Guo struct mmc_command *cmd = host->cmd; 279e4243f13SShawn Guo struct mmc_data *data = host->data; 280e4243f13SShawn Guo u32 stat; 281e4243f13SShawn Guo 282e4243f13SShawn Guo spin_lock(&host->lock); 283e4243f13SShawn Guo 284e0bf141dSShawn Guo stat = readl(host->base + HW_SSP_CTRL1(host)); 285e4243f13SShawn Guo writel(stat & MXS_MMC_IRQ_BITS, 286e0bf141dSShawn Guo host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_CLR); 287e4243f13SShawn Guo 2881af36b2aSLauri Hintsala spin_unlock(&host->lock); 2891af36b2aSLauri Hintsala 290e4243f13SShawn Guo if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN)) 291e4243f13SShawn Guo mmc_signal_sdio_irq(host->mmc); 292e4243f13SShawn Guo 293e4243f13SShawn Guo if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ) 294e4243f13SShawn Guo cmd->error = -ETIMEDOUT; 295e4243f13SShawn Guo else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ) 296e4243f13SShawn Guo cmd->error = -EIO; 297e4243f13SShawn Guo 298e4243f13SShawn Guo if (data) { 299e4243f13SShawn Guo if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | 300e4243f13SShawn Guo BM_SSP_CTRL1_RECV_TIMEOUT_IRQ)) 301e4243f13SShawn Guo data->error = -ETIMEDOUT; 302e4243f13SShawn Guo else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ) 303e4243f13SShawn Guo data->error = -EILSEQ; 304e4243f13SShawn Guo else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | 305e4243f13SShawn Guo BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)) 306e4243f13SShawn Guo data->error = -EIO; 307e4243f13SShawn Guo } 308e4243f13SShawn Guo 309e4243f13SShawn Guo return IRQ_HANDLED; 310e4243f13SShawn Guo } 311e4243f13SShawn Guo 312e4243f13SShawn Guo static struct dma_async_tx_descriptor *mxs_mmc_prep_dma( 313921de864SHuang Shijie struct mxs_mmc_host *host, unsigned long flags) 314e4243f13SShawn Guo { 315e4243f13SShawn Guo struct dma_async_tx_descriptor *desc; 316e4243f13SShawn Guo struct mmc_data *data = host->data; 317e4243f13SShawn Guo struct scatterlist * sgl; 318e4243f13SShawn Guo unsigned int sg_len; 319e4243f13SShawn Guo 320e4243f13SShawn Guo if (data) { 321e4243f13SShawn Guo /* data */ 322e4243f13SShawn Guo dma_map_sg(mmc_dev(host->mmc), data->sg, 323e4243f13SShawn Guo data->sg_len, host->dma_dir); 324e4243f13SShawn Guo sgl = data->sg; 325e4243f13SShawn Guo sg_len = data->sg_len; 326e4243f13SShawn Guo } else { 327e4243f13SShawn Guo /* pio */ 328e4243f13SShawn Guo sgl = (struct scatterlist *) host->ssp_pio_words; 329e4243f13SShawn Guo sg_len = SSP_PIO_NUM; 330e4243f13SShawn Guo } 331e4243f13SShawn Guo 33216052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(host->dmach, 333921de864SHuang Shijie sgl, sg_len, host->slave_dirn, flags); 334e4243f13SShawn Guo if (desc) { 335e4243f13SShawn Guo desc->callback = mxs_mmc_dma_irq_callback; 336e4243f13SShawn Guo desc->callback_param = host; 337e4243f13SShawn Guo } else { 338e4243f13SShawn Guo if (data) 339e4243f13SShawn Guo dma_unmap_sg(mmc_dev(host->mmc), data->sg, 340e4243f13SShawn Guo data->sg_len, host->dma_dir); 341e4243f13SShawn Guo } 342e4243f13SShawn Guo 343e4243f13SShawn Guo return desc; 344e4243f13SShawn Guo } 345e4243f13SShawn Guo 346e4243f13SShawn Guo static void mxs_mmc_bc(struct mxs_mmc_host *host) 347e4243f13SShawn Guo { 348e4243f13SShawn Guo struct mmc_command *cmd = host->cmd; 349e4243f13SShawn Guo struct dma_async_tx_descriptor *desc; 350e4243f13SShawn Guo u32 ctrl0, cmd0, cmd1; 351e4243f13SShawn Guo 352e4243f13SShawn Guo ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC; 353e4243f13SShawn Guo cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC; 354e4243f13SShawn Guo cmd1 = cmd->arg; 355e4243f13SShawn Guo 356e4243f13SShawn Guo if (host->sdio_irq_en) { 357e4243f13SShawn Guo ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 358e4243f13SShawn Guo cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 359e4243f13SShawn Guo } 360e4243f13SShawn Guo 361e4243f13SShawn Guo host->ssp_pio_words[0] = ctrl0; 362e4243f13SShawn Guo host->ssp_pio_words[1] = cmd0; 363e4243f13SShawn Guo host->ssp_pio_words[2] = cmd1; 364e4243f13SShawn Guo host->dma_dir = DMA_NONE; 365a4e3e86dSShawn Guo host->slave_dirn = DMA_TRANS_NONE; 366921de864SHuang Shijie desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK); 367e4243f13SShawn Guo if (!desc) 368e4243f13SShawn Guo goto out; 369e4243f13SShawn Guo 370e4243f13SShawn Guo dmaengine_submit(desc); 371d04525edSShawn Guo dma_async_issue_pending(host->dmach); 372e4243f13SShawn Guo return; 373e4243f13SShawn Guo 374e4243f13SShawn Guo out: 375e4243f13SShawn Guo dev_warn(mmc_dev(host->mmc), 376e4243f13SShawn Guo "%s: failed to prep dma\n", __func__); 377e4243f13SShawn Guo } 378e4243f13SShawn Guo 379e4243f13SShawn Guo static void mxs_mmc_ac(struct mxs_mmc_host *host) 380e4243f13SShawn Guo { 381e4243f13SShawn Guo struct mmc_command *cmd = host->cmd; 382e4243f13SShawn Guo struct dma_async_tx_descriptor *desc; 383e4243f13SShawn Guo u32 ignore_crc, get_resp, long_resp; 384e4243f13SShawn Guo u32 ctrl0, cmd0, cmd1; 385e4243f13SShawn Guo 386e4243f13SShawn Guo ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ? 387e4243f13SShawn Guo 0 : BM_SSP_CTRL0_IGNORE_CRC; 388e4243f13SShawn Guo get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ? 389e4243f13SShawn Guo BM_SSP_CTRL0_GET_RESP : 0; 390e4243f13SShawn Guo long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ? 391e4243f13SShawn Guo BM_SSP_CTRL0_LONG_RESP : 0; 392e4243f13SShawn Guo 393e4243f13SShawn Guo ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp; 394e4243f13SShawn Guo cmd0 = BF_SSP(cmd->opcode, CMD0_CMD); 395e4243f13SShawn Guo cmd1 = cmd->arg; 396e4243f13SShawn Guo 397e4243f13SShawn Guo if (host->sdio_irq_en) { 398e4243f13SShawn Guo ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 399e4243f13SShawn Guo cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 400e4243f13SShawn Guo } 401e4243f13SShawn Guo 402e4243f13SShawn Guo host->ssp_pio_words[0] = ctrl0; 403e4243f13SShawn Guo host->ssp_pio_words[1] = cmd0; 404e4243f13SShawn Guo host->ssp_pio_words[2] = cmd1; 405e4243f13SShawn Guo host->dma_dir = DMA_NONE; 406a4e3e86dSShawn Guo host->slave_dirn = DMA_TRANS_NONE; 407921de864SHuang Shijie desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK); 408e4243f13SShawn Guo if (!desc) 409e4243f13SShawn Guo goto out; 410e4243f13SShawn Guo 411e4243f13SShawn Guo dmaengine_submit(desc); 412d04525edSShawn Guo dma_async_issue_pending(host->dmach); 413e4243f13SShawn Guo return; 414e4243f13SShawn Guo 415e4243f13SShawn Guo out: 416e4243f13SShawn Guo dev_warn(mmc_dev(host->mmc), 417e4243f13SShawn Guo "%s: failed to prep dma\n", __func__); 418e4243f13SShawn Guo } 419e4243f13SShawn Guo 420e4243f13SShawn Guo static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns) 421e4243f13SShawn Guo { 422e4243f13SShawn Guo const unsigned int ssp_timeout_mul = 4096; 423e4243f13SShawn Guo /* 424e4243f13SShawn Guo * Calculate ticks in ms since ns are large numbers 425e4243f13SShawn Guo * and might overflow 426e4243f13SShawn Guo */ 427e4243f13SShawn Guo const unsigned int clock_per_ms = clock_rate / 1000; 428e4243f13SShawn Guo const unsigned int ms = ns / 1000; 429e4243f13SShawn Guo const unsigned int ticks = ms * clock_per_ms; 430e4243f13SShawn Guo const unsigned int ssp_ticks = ticks / ssp_timeout_mul; 431e4243f13SShawn Guo 432e4243f13SShawn Guo WARN_ON(ssp_ticks == 0); 433e4243f13SShawn Guo return ssp_ticks; 434e4243f13SShawn Guo } 435e4243f13SShawn Guo 436e4243f13SShawn Guo static void mxs_mmc_adtc(struct mxs_mmc_host *host) 437e4243f13SShawn Guo { 438e4243f13SShawn Guo struct mmc_command *cmd = host->cmd; 439e4243f13SShawn Guo struct mmc_data *data = cmd->data; 440e4243f13SShawn Guo struct dma_async_tx_descriptor *desc; 441e4243f13SShawn Guo struct scatterlist *sgl = data->sg, *sg; 442e4243f13SShawn Guo unsigned int sg_len = data->sg_len; 443e4243f13SShawn Guo int i; 444e4243f13SShawn Guo 445e4243f13SShawn Guo unsigned short dma_data_dir, timeout; 44605f5799cSVinod Koul enum dma_transfer_direction slave_dirn; 447e4243f13SShawn Guo unsigned int data_size = 0, log2_blksz; 448e4243f13SShawn Guo unsigned int blocks = data->blocks; 449e4243f13SShawn Guo 450e4243f13SShawn Guo u32 ignore_crc, get_resp, long_resp, read; 451e4243f13SShawn Guo u32 ctrl0, cmd0, cmd1, val; 452e4243f13SShawn Guo 453e4243f13SShawn Guo ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ? 454e4243f13SShawn Guo 0 : BM_SSP_CTRL0_IGNORE_CRC; 455e4243f13SShawn Guo get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ? 456e4243f13SShawn Guo BM_SSP_CTRL0_GET_RESP : 0; 457e4243f13SShawn Guo long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ? 458e4243f13SShawn Guo BM_SSP_CTRL0_LONG_RESP : 0; 459e4243f13SShawn Guo 460e4243f13SShawn Guo if (data->flags & MMC_DATA_WRITE) { 461e4243f13SShawn Guo dma_data_dir = DMA_TO_DEVICE; 46205f5799cSVinod Koul slave_dirn = DMA_MEM_TO_DEV; 463e4243f13SShawn Guo read = 0; 464e4243f13SShawn Guo } else { 465e4243f13SShawn Guo dma_data_dir = DMA_FROM_DEVICE; 46605f5799cSVinod Koul slave_dirn = DMA_DEV_TO_MEM; 467e4243f13SShawn Guo read = BM_SSP_CTRL0_READ; 468e4243f13SShawn Guo } 469e4243f13SShawn Guo 470e4243f13SShawn Guo ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) | 471e4243f13SShawn Guo ignore_crc | get_resp | long_resp | 472e4243f13SShawn Guo BM_SSP_CTRL0_DATA_XFER | read | 473e4243f13SShawn Guo BM_SSP_CTRL0_WAIT_FOR_IRQ | 474e4243f13SShawn Guo BM_SSP_CTRL0_ENABLE; 475e4243f13SShawn Guo 476e4243f13SShawn Guo cmd0 = BF_SSP(cmd->opcode, CMD0_CMD); 477e4243f13SShawn Guo 478e4243f13SShawn Guo /* get logarithm to base 2 of block size for setting register */ 479e4243f13SShawn Guo log2_blksz = ilog2(data->blksz); 480e4243f13SShawn Guo 481e4243f13SShawn Guo /* 482e4243f13SShawn Guo * take special care of the case that data size from data->sg 483e4243f13SShawn Guo * is not equal to blocks x blksz 484e4243f13SShawn Guo */ 485e4243f13SShawn Guo for_each_sg(sgl, sg, sg_len, i) 486e4243f13SShawn Guo data_size += sg->length; 487e4243f13SShawn Guo 488e4243f13SShawn Guo if (data_size != data->blocks * data->blksz) 489e4243f13SShawn Guo blocks = 1; 490e4243f13SShawn Guo 491e4243f13SShawn Guo /* xfer count, block size and count need to be set differently */ 492e0bf141dSShawn Guo if (ssp_is_old(host)) { 493e4243f13SShawn Guo ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT); 494e4243f13SShawn Guo cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) | 495e4243f13SShawn Guo BF_SSP(blocks - 1, CMD0_BLOCK_COUNT); 496e4243f13SShawn Guo } else { 497e4243f13SShawn Guo writel(data_size, host->base + HW_SSP_XFER_SIZE); 498e4243f13SShawn Guo writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) | 499e4243f13SShawn Guo BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT), 500e4243f13SShawn Guo host->base + HW_SSP_BLOCK_SIZE); 501e4243f13SShawn Guo } 502e4243f13SShawn Guo 503e4243f13SShawn Guo if ((cmd->opcode == MMC_STOP_TRANSMISSION) || 504e4243f13SShawn Guo (cmd->opcode == SD_IO_RW_EXTENDED)) 505e4243f13SShawn Guo cmd0 |= BM_SSP_CMD0_APPEND_8CYC; 506e4243f13SShawn Guo 507e4243f13SShawn Guo cmd1 = cmd->arg; 508e4243f13SShawn Guo 509e4243f13SShawn Guo if (host->sdio_irq_en) { 510e4243f13SShawn Guo ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 511e4243f13SShawn Guo cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 512e4243f13SShawn Guo } 513e4243f13SShawn Guo 514e4243f13SShawn Guo /* set the timeout count */ 515e4243f13SShawn Guo timeout = mxs_ns_to_ssp_ticks(host->clk_rate, data->timeout_ns); 516e0bf141dSShawn Guo val = readl(host->base + HW_SSP_TIMING(host)); 517e4243f13SShawn Guo val &= ~(BM_SSP_TIMING_TIMEOUT); 518e4243f13SShawn Guo val |= BF_SSP(timeout, TIMING_TIMEOUT); 519e0bf141dSShawn Guo writel(val, host->base + HW_SSP_TIMING(host)); 520e4243f13SShawn Guo 521e4243f13SShawn Guo /* pio */ 522e4243f13SShawn Guo host->ssp_pio_words[0] = ctrl0; 523e4243f13SShawn Guo host->ssp_pio_words[1] = cmd0; 524e4243f13SShawn Guo host->ssp_pio_words[2] = cmd1; 525e4243f13SShawn Guo host->dma_dir = DMA_NONE; 526a4e3e86dSShawn Guo host->slave_dirn = DMA_TRANS_NONE; 527e4243f13SShawn Guo desc = mxs_mmc_prep_dma(host, 0); 528e4243f13SShawn Guo if (!desc) 529e4243f13SShawn Guo goto out; 530e4243f13SShawn Guo 531e4243f13SShawn Guo /* append data sg */ 532e4243f13SShawn Guo WARN_ON(host->data != NULL); 533e4243f13SShawn Guo host->data = data; 534e4243f13SShawn Guo host->dma_dir = dma_data_dir; 53505f5799cSVinod Koul host->slave_dirn = slave_dirn; 536921de864SHuang Shijie desc = mxs_mmc_prep_dma(host, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 537e4243f13SShawn Guo if (!desc) 538e4243f13SShawn Guo goto out; 539e4243f13SShawn Guo 540e4243f13SShawn Guo dmaengine_submit(desc); 541d04525edSShawn Guo dma_async_issue_pending(host->dmach); 542e4243f13SShawn Guo return; 543e4243f13SShawn Guo out: 544e4243f13SShawn Guo dev_warn(mmc_dev(host->mmc), 545e4243f13SShawn Guo "%s: failed to prep dma\n", __func__); 546e4243f13SShawn Guo } 547e4243f13SShawn Guo 548e4243f13SShawn Guo static void mxs_mmc_start_cmd(struct mxs_mmc_host *host, 549e4243f13SShawn Guo struct mmc_command *cmd) 550e4243f13SShawn Guo { 551e4243f13SShawn Guo host->cmd = cmd; 552e4243f13SShawn Guo 553e4243f13SShawn Guo switch (mmc_cmd_type(cmd)) { 554e4243f13SShawn Guo case MMC_CMD_BC: 555e4243f13SShawn Guo mxs_mmc_bc(host); 556e4243f13SShawn Guo break; 557e4243f13SShawn Guo case MMC_CMD_BCR: 558e4243f13SShawn Guo mxs_mmc_ac(host); 559e4243f13SShawn Guo break; 560e4243f13SShawn Guo case MMC_CMD_AC: 561e4243f13SShawn Guo mxs_mmc_ac(host); 562e4243f13SShawn Guo break; 563e4243f13SShawn Guo case MMC_CMD_ADTC: 564e4243f13SShawn Guo mxs_mmc_adtc(host); 565e4243f13SShawn Guo break; 566e4243f13SShawn Guo default: 567e4243f13SShawn Guo dev_warn(mmc_dev(host->mmc), 568e4243f13SShawn Guo "%s: unknown MMC command\n", __func__); 569e4243f13SShawn Guo break; 570e4243f13SShawn Guo } 571e4243f13SShawn Guo } 572e4243f13SShawn Guo 573e4243f13SShawn Guo static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 574e4243f13SShawn Guo { 575e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 576e4243f13SShawn Guo 577e4243f13SShawn Guo WARN_ON(host->mrq != NULL); 578e4243f13SShawn Guo host->mrq = mrq; 579e4243f13SShawn Guo mxs_mmc_start_cmd(host, mrq->cmd); 580e4243f13SShawn Guo } 581e4243f13SShawn Guo 582e4243f13SShawn Guo static void mxs_mmc_set_clk_rate(struct mxs_mmc_host *host, unsigned int rate) 583e4243f13SShawn Guo { 584d982dcdcSKoen Beel unsigned int ssp_clk, ssp_sck; 585d982dcdcSKoen Beel u32 clock_divide, clock_rate; 586e4243f13SShawn Guo u32 val; 587e4243f13SShawn Guo 588d982dcdcSKoen Beel ssp_clk = clk_get_rate(host->clk); 589e4243f13SShawn Guo 590d982dcdcSKoen Beel for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) { 591d982dcdcSKoen Beel clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide); 592d982dcdcSKoen Beel clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0; 593d982dcdcSKoen Beel if (clock_rate <= 255) 594e4243f13SShawn Guo break; 595e4243f13SShawn Guo } 596e4243f13SShawn Guo 597d982dcdcSKoen Beel if (clock_divide > 254) { 598e4243f13SShawn Guo dev_err(mmc_dev(host->mmc), 599e4243f13SShawn Guo "%s: cannot set clock to %d\n", __func__, rate); 600e4243f13SShawn Guo return; 601e4243f13SShawn Guo } 602e4243f13SShawn Guo 603d982dcdcSKoen Beel ssp_sck = ssp_clk / clock_divide / (1 + clock_rate); 604e4243f13SShawn Guo 605e0bf141dSShawn Guo val = readl(host->base + HW_SSP_TIMING(host)); 606e4243f13SShawn Guo val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE); 607d982dcdcSKoen Beel val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE); 608d982dcdcSKoen Beel val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE); 609e0bf141dSShawn Guo writel(val, host->base + HW_SSP_TIMING(host)); 610e4243f13SShawn Guo 611d982dcdcSKoen Beel host->clk_rate = ssp_sck; 612e4243f13SShawn Guo 613e4243f13SShawn Guo dev_dbg(mmc_dev(host->mmc), 614d982dcdcSKoen Beel "%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n", 615d982dcdcSKoen Beel __func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate); 616e4243f13SShawn Guo } 617e4243f13SShawn Guo 618e4243f13SShawn Guo static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 619e4243f13SShawn Guo { 620e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 621e4243f13SShawn Guo 622e4243f13SShawn Guo if (ios->bus_width == MMC_BUS_WIDTH_8) 623e4243f13SShawn Guo host->bus_width = 2; 624e4243f13SShawn Guo else if (ios->bus_width == MMC_BUS_WIDTH_4) 625e4243f13SShawn Guo host->bus_width = 1; 626e4243f13SShawn Guo else 627e4243f13SShawn Guo host->bus_width = 0; 628e4243f13SShawn Guo 629e4243f13SShawn Guo if (ios->clock) 630e4243f13SShawn Guo mxs_mmc_set_clk_rate(host, ios->clock); 631e4243f13SShawn Guo } 632e4243f13SShawn Guo 633e4243f13SShawn Guo static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 634e4243f13SShawn Guo { 635e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 636e4243f13SShawn Guo unsigned long flags; 637e4243f13SShawn Guo 638e4243f13SShawn Guo spin_lock_irqsave(&host->lock, flags); 639e4243f13SShawn Guo 640e4243f13SShawn Guo host->sdio_irq_en = enable; 641e4243f13SShawn Guo 642e4243f13SShawn Guo if (enable) { 643e4243f13SShawn Guo writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, 64470e60206SShawn Guo host->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); 645e4243f13SShawn Guo writel(BM_SSP_CTRL1_SDIO_IRQ_EN, 646e0bf141dSShawn Guo host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_SET); 647e4243f13SShawn Guo } else { 648e4243f13SShawn Guo writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, 64970e60206SShawn Guo host->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); 650e4243f13SShawn Guo writel(BM_SSP_CTRL1_SDIO_IRQ_EN, 651e0bf141dSShawn Guo host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_CLR); 652e4243f13SShawn Guo } 653e4243f13SShawn Guo 654e4243f13SShawn Guo spin_unlock_irqrestore(&host->lock, flags); 655fc108d24SLauri Hintsala 656fc108d24SLauri Hintsala if (enable && readl(host->base + HW_SSP_STATUS(host)) & 657fc108d24SLauri Hintsala BM_SSP_STATUS_SDIO_IRQ) 658fc108d24SLauri Hintsala mmc_signal_sdio_irq(host->mmc); 659fc108d24SLauri Hintsala 660e4243f13SShawn Guo } 661e4243f13SShawn Guo 662e4243f13SShawn Guo static const struct mmc_host_ops mxs_mmc_ops = { 663e4243f13SShawn Guo .request = mxs_mmc_request, 664e4243f13SShawn Guo .get_ro = mxs_mmc_get_ro, 665e4243f13SShawn Guo .get_cd = mxs_mmc_get_cd, 666e4243f13SShawn Guo .set_ios = mxs_mmc_set_ios, 667e4243f13SShawn Guo .enable_sdio_irq = mxs_mmc_enable_sdio_irq, 668e4243f13SShawn Guo }; 669e4243f13SShawn Guo 670e4243f13SShawn Guo static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param) 671e4243f13SShawn Guo { 672e4243f13SShawn Guo struct mxs_mmc_host *host = param; 673e4243f13SShawn Guo 674e4243f13SShawn Guo if (!mxs_dma_is_apbh(chan)) 675e4243f13SShawn Guo return false; 676e4243f13SShawn Guo 677b60188c8SShawn Guo if (chan->chan_id != host->dma_channel) 678e4243f13SShawn Guo return false; 679e4243f13SShawn Guo 680e4243f13SShawn Guo chan->private = &host->dma_data; 681e4243f13SShawn Guo 682e4243f13SShawn Guo return true; 683e4243f13SShawn Guo } 684e4243f13SShawn Guo 685ef9b4d39SShawn Guo static struct platform_device_id mxs_mmc_ids[] = { 686ef9b4d39SShawn Guo { 687ef9b4d39SShawn Guo .name = "imx23-mmc", 688ef9b4d39SShawn Guo .driver_data = IMX23_MMC, 689ef9b4d39SShawn Guo }, { 690ef9b4d39SShawn Guo .name = "imx28-mmc", 691ef9b4d39SShawn Guo .driver_data = IMX28_MMC, 692ef9b4d39SShawn Guo }, { 693ef9b4d39SShawn Guo /* sentinel */ 694ef9b4d39SShawn Guo } 695ef9b4d39SShawn Guo }; 696ef9b4d39SShawn Guo MODULE_DEVICE_TABLE(platform, mxs_mmc_ids); 697ef9b4d39SShawn Guo 6986de4d817SShawn Guo static const struct of_device_id mxs_mmc_dt_ids[] = { 6996de4d817SShawn Guo { .compatible = "fsl,imx23-mmc", .data = (void *) IMX23_MMC, }, 7006de4d817SShawn Guo { .compatible = "fsl,imx28-mmc", .data = (void *) IMX28_MMC, }, 7016de4d817SShawn Guo { /* sentinel */ } 7026de4d817SShawn Guo }; 7036de4d817SShawn Guo MODULE_DEVICE_TABLE(of, mxs_mmc_dt_ids); 7046de4d817SShawn Guo 705e4243f13SShawn Guo static int mxs_mmc_probe(struct platform_device *pdev) 706e4243f13SShawn Guo { 7076de4d817SShawn Guo const struct of_device_id *of_id = 7086de4d817SShawn Guo of_match_device(mxs_mmc_dt_ids, &pdev->dev); 7096de4d817SShawn Guo struct device_node *np = pdev->dev.of_node; 710e4243f13SShawn Guo struct mxs_mmc_host *host; 711e4243f13SShawn Guo struct mmc_host *mmc; 712df06bfc7SShawn Guo struct resource *iores, *dmares; 713e4243f13SShawn Guo struct mxs_mmc_platform_data *pdata; 7149c92cf24SShawn Guo struct pinctrl *pinctrl; 715e4243f13SShawn Guo int ret = 0, irq_err, irq_dma; 716e4243f13SShawn Guo dma_cap_mask_t mask; 7174dc5a79fSShawn Guo struct regulator *reg_vmmc; 718b6e76f10SMarek Vasut enum of_gpio_flags flags; 719e4243f13SShawn Guo 720e4243f13SShawn Guo iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 721e4243f13SShawn Guo dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0); 722e4243f13SShawn Guo irq_err = platform_get_irq(pdev, 0); 723e4243f13SShawn Guo irq_dma = platform_get_irq(pdev, 1); 7246de4d817SShawn Guo if (!iores || irq_err < 0 || irq_dma < 0) 725e4243f13SShawn Guo return -EINVAL; 726e4243f13SShawn Guo 727e4243f13SShawn Guo mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev); 728df06bfc7SShawn Guo if (!mmc) 729df06bfc7SShawn Guo return -ENOMEM; 730e4243f13SShawn Guo 731e4243f13SShawn Guo host = mmc_priv(mmc); 732df06bfc7SShawn Guo host->base = devm_request_and_ioremap(&pdev->dev, iores); 733e4243f13SShawn Guo if (!host->base) { 734df06bfc7SShawn Guo ret = -EADDRNOTAVAIL; 735e4243f13SShawn Guo goto out_mmc_free; 736e4243f13SShawn Guo } 737e4243f13SShawn Guo 7386de4d817SShawn Guo if (np) { 7396de4d817SShawn Guo host->devid = (enum mxs_mmc_id) of_id->data; 7406de4d817SShawn Guo /* 7416de4d817SShawn Guo * TODO: This is a temporary solution and should be changed 7426de4d817SShawn Guo * to use generic DMA binding later when the helpers get in. 7436de4d817SShawn Guo */ 7446de4d817SShawn Guo ret = of_property_read_u32(np, "fsl,ssp-dma-channel", 7456de4d817SShawn Guo &host->dma_channel); 7466de4d817SShawn Guo if (ret) { 7476de4d817SShawn Guo dev_err(mmc_dev(host->mmc), 7486de4d817SShawn Guo "failed to get dma channel\n"); 7496de4d817SShawn Guo goto out_mmc_free; 7506de4d817SShawn Guo } 7516de4d817SShawn Guo } else { 752ef9b4d39SShawn Guo host->devid = pdev->id_entry->driver_data; 753b60188c8SShawn Guo host->dma_channel = dmares->start; 7546de4d817SShawn Guo } 7556de4d817SShawn Guo 7566de4d817SShawn Guo host->mmc = mmc; 757e4243f13SShawn Guo host->sdio_irq_en = 0; 758e4243f13SShawn Guo 7594dc5a79fSShawn Guo reg_vmmc = devm_regulator_get(&pdev->dev, "vmmc"); 7604dc5a79fSShawn Guo if (!IS_ERR(reg_vmmc)) { 7614dc5a79fSShawn Guo ret = regulator_enable(reg_vmmc); 7624dc5a79fSShawn Guo if (ret) { 7634dc5a79fSShawn Guo dev_err(&pdev->dev, 7644dc5a79fSShawn Guo "Failed to enable vmmc regulator: %d\n", ret); 7654dc5a79fSShawn Guo goto out_mmc_free; 7664dc5a79fSShawn Guo } 7674dc5a79fSShawn Guo } 7684dc5a79fSShawn Guo 7699c92cf24SShawn Guo pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 7709c92cf24SShawn Guo if (IS_ERR(pinctrl)) { 7719c92cf24SShawn Guo ret = PTR_ERR(pinctrl); 7726de4d817SShawn Guo goto out_mmc_free; 7739c92cf24SShawn Guo } 7749c92cf24SShawn Guo 775e4243f13SShawn Guo host->clk = clk_get(&pdev->dev, NULL); 776e4243f13SShawn Guo if (IS_ERR(host->clk)) { 777e4243f13SShawn Guo ret = PTR_ERR(host->clk); 778df06bfc7SShawn Guo goto out_mmc_free; 779e4243f13SShawn Guo } 780efdfc52cSShawn Guo clk_prepare_enable(host->clk); 781e4243f13SShawn Guo 782e4243f13SShawn Guo mxs_mmc_reset(host); 783e4243f13SShawn Guo 784e4243f13SShawn Guo dma_cap_zero(mask); 785e4243f13SShawn Guo dma_cap_set(DMA_SLAVE, mask); 786e4243f13SShawn Guo host->dma_data.chan_irq = irq_dma; 787e4243f13SShawn Guo host->dmach = dma_request_channel(mask, mxs_mmc_dma_filter, host); 788e4243f13SShawn Guo if (!host->dmach) { 789e4243f13SShawn Guo dev_err(mmc_dev(host->mmc), 790e4243f13SShawn Guo "%s: failed to request dma\n", __func__); 791e4243f13SShawn Guo goto out_clk_put; 792e4243f13SShawn Guo } 793e4243f13SShawn Guo 794e4243f13SShawn Guo /* set mmc core parameters */ 795e4243f13SShawn Guo mmc->ops = &mxs_mmc_ops; 796e4243f13SShawn Guo mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 797e4243f13SShawn Guo MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL; 798e4243f13SShawn Guo 799e4243f13SShawn Guo pdata = mmc_dev(host->mmc)->platform_data; 8006de4d817SShawn Guo if (!pdata) { 8016de4d817SShawn Guo u32 bus_width = 0; 8026de4d817SShawn Guo of_property_read_u32(np, "bus-width", &bus_width); 8036de4d817SShawn Guo if (bus_width == 4) 8046de4d817SShawn Guo mmc->caps |= MMC_CAP_4_BIT_DATA; 8056de4d817SShawn Guo else if (bus_width == 8) 8066de4d817SShawn Guo mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA; 807b6e76f10SMarek Vasut host->wp_gpio = of_get_named_gpio_flags(np, "wp-gpios", 0, 808b6e76f10SMarek Vasut &flags); 809b6e76f10SMarek Vasut if (flags & OF_GPIO_ACTIVE_LOW) 810b6e76f10SMarek Vasut host->wp_inverted = 1; 8116de4d817SShawn Guo } else { 812e4243f13SShawn Guo if (pdata->flags & SLOTF_8_BIT_CAPABLE) 813e4243f13SShawn Guo mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA; 814e4243f13SShawn Guo if (pdata->flags & SLOTF_4_BIT_CAPABLE) 815e4243f13SShawn Guo mmc->caps |= MMC_CAP_4_BIT_DATA; 81631b0ff5eSShawn Guo host->wp_gpio = pdata->wp_gpio; 817e4243f13SShawn Guo } 818e4243f13SShawn Guo 819e4243f13SShawn Guo mmc->f_min = 400000; 820e4243f13SShawn Guo mmc->f_max = 288000000; 821e4243f13SShawn Guo mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 822e4243f13SShawn Guo 823e4243f13SShawn Guo mmc->max_segs = 52; 824e4243f13SShawn Guo mmc->max_blk_size = 1 << 0xf; 825e0bf141dSShawn Guo mmc->max_blk_count = (ssp_is_old(host)) ? 0xff : 0xffffff; 826e0bf141dSShawn Guo mmc->max_req_size = (ssp_is_old(host)) ? 0xffff : 0xffffffff; 827e4243f13SShawn Guo mmc->max_seg_size = dma_get_max_seg_size(host->dmach->device->dev); 828e4243f13SShawn Guo 829e4243f13SShawn Guo platform_set_drvdata(pdev, mmc); 830e4243f13SShawn Guo 831df06bfc7SShawn Guo ret = devm_request_irq(&pdev->dev, irq_err, mxs_mmc_irq_handler, 0, 832df06bfc7SShawn Guo DRIVER_NAME, host); 833e4243f13SShawn Guo if (ret) 834e4243f13SShawn Guo goto out_free_dma; 835e4243f13SShawn Guo 836e4243f13SShawn Guo spin_lock_init(&host->lock); 837e4243f13SShawn Guo 838e4243f13SShawn Guo ret = mmc_add_host(mmc); 839e4243f13SShawn Guo if (ret) 840df06bfc7SShawn Guo goto out_free_dma; 841e4243f13SShawn Guo 842e4243f13SShawn Guo dev_info(mmc_dev(host->mmc), "initialized\n"); 843e4243f13SShawn Guo 844e4243f13SShawn Guo return 0; 845e4243f13SShawn Guo 846e4243f13SShawn Guo out_free_dma: 847e4243f13SShawn Guo if (host->dmach) 848e4243f13SShawn Guo dma_release_channel(host->dmach); 849e4243f13SShawn Guo out_clk_put: 850efdfc52cSShawn Guo clk_disable_unprepare(host->clk); 851e4243f13SShawn Guo clk_put(host->clk); 852e4243f13SShawn Guo out_mmc_free: 853e4243f13SShawn Guo mmc_free_host(mmc); 854e4243f13SShawn Guo return ret; 855e4243f13SShawn Guo } 856e4243f13SShawn Guo 857e4243f13SShawn Guo static int mxs_mmc_remove(struct platform_device *pdev) 858e4243f13SShawn Guo { 859e4243f13SShawn Guo struct mmc_host *mmc = platform_get_drvdata(pdev); 860e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 861e4243f13SShawn Guo 862e4243f13SShawn Guo mmc_remove_host(mmc); 863e4243f13SShawn Guo 864e4243f13SShawn Guo platform_set_drvdata(pdev, NULL); 865e4243f13SShawn Guo 866e4243f13SShawn Guo if (host->dmach) 867e4243f13SShawn Guo dma_release_channel(host->dmach); 868e4243f13SShawn Guo 869efdfc52cSShawn Guo clk_disable_unprepare(host->clk); 870e4243f13SShawn Guo clk_put(host->clk); 871e4243f13SShawn Guo 872e4243f13SShawn Guo mmc_free_host(mmc); 873e4243f13SShawn Guo 874e4243f13SShawn Guo return 0; 875e4243f13SShawn Guo } 876e4243f13SShawn Guo 877e4243f13SShawn Guo #ifdef CONFIG_PM 878e4243f13SShawn Guo static int mxs_mmc_suspend(struct device *dev) 879e4243f13SShawn Guo { 880e4243f13SShawn Guo struct mmc_host *mmc = dev_get_drvdata(dev); 881e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 882e4243f13SShawn Guo int ret = 0; 883e4243f13SShawn Guo 884e4243f13SShawn Guo ret = mmc_suspend_host(mmc); 885e4243f13SShawn Guo 886efdfc52cSShawn Guo clk_disable_unprepare(host->clk); 887e4243f13SShawn Guo 888e4243f13SShawn Guo return ret; 889e4243f13SShawn Guo } 890e4243f13SShawn Guo 891e4243f13SShawn Guo static int mxs_mmc_resume(struct device *dev) 892e4243f13SShawn Guo { 893e4243f13SShawn Guo struct mmc_host *mmc = dev_get_drvdata(dev); 894e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 895e4243f13SShawn Guo int ret = 0; 896e4243f13SShawn Guo 897efdfc52cSShawn Guo clk_prepare_enable(host->clk); 898e4243f13SShawn Guo 899e4243f13SShawn Guo ret = mmc_resume_host(mmc); 900e4243f13SShawn Guo 901e4243f13SShawn Guo return ret; 902e4243f13SShawn Guo } 903e4243f13SShawn Guo 904e4243f13SShawn Guo static const struct dev_pm_ops mxs_mmc_pm_ops = { 905e4243f13SShawn Guo .suspend = mxs_mmc_suspend, 906e4243f13SShawn Guo .resume = mxs_mmc_resume, 907e4243f13SShawn Guo }; 908e4243f13SShawn Guo #endif 909e4243f13SShawn Guo 910e4243f13SShawn Guo static struct platform_driver mxs_mmc_driver = { 911e4243f13SShawn Guo .probe = mxs_mmc_probe, 912e4243f13SShawn Guo .remove = mxs_mmc_remove, 913ef9b4d39SShawn Guo .id_table = mxs_mmc_ids, 914e4243f13SShawn Guo .driver = { 915e4243f13SShawn Guo .name = DRIVER_NAME, 916e4243f13SShawn Guo .owner = THIS_MODULE, 917e4243f13SShawn Guo #ifdef CONFIG_PM 918e4243f13SShawn Guo .pm = &mxs_mmc_pm_ops, 919e4243f13SShawn Guo #endif 920a3e545e9SMarek Vasut .of_match_table = mxs_mmc_dt_ids, 921e4243f13SShawn Guo }, 922e4243f13SShawn Guo }; 923e4243f13SShawn Guo 924d1f81a64SAxel Lin module_platform_driver(mxs_mmc_driver); 925e4243f13SShawn Guo 926e4243f13SShawn Guo MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral"); 927e4243f13SShawn Guo MODULE_AUTHOR("Freescale Semiconductor"); 928e4243f13SShawn Guo MODULE_LICENSE("GPL"); 929