1e4243f13SShawn Guo /* 2e4243f13SShawn Guo * Portions copyright (C) 2003 Russell King, PXA MMCI Driver 3e4243f13SShawn Guo * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver 4e4243f13SShawn Guo * 5e4243f13SShawn Guo * Copyright 2008 Embedded Alley Solutions, Inc. 6e4243f13SShawn Guo * Copyright 2009-2011 Freescale Semiconductor, Inc. 7e4243f13SShawn Guo * 8e4243f13SShawn Guo * This program is free software; you can redistribute it and/or modify 9e4243f13SShawn Guo * it under the terms of the GNU General Public License as published by 10e4243f13SShawn Guo * the Free Software Foundation; either version 2 of the License, or 11e4243f13SShawn Guo * (at your option) any later version. 12e4243f13SShawn Guo * 13e4243f13SShawn Guo * This program is distributed in the hope that it will be useful, 14e4243f13SShawn Guo * but WITHOUT ANY WARRANTY; without even the implied warranty of 15e4243f13SShawn Guo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16e4243f13SShawn Guo * GNU General Public License for more details. 17e4243f13SShawn Guo * 18e4243f13SShawn Guo * You should have received a copy of the GNU General Public License along 19e4243f13SShawn Guo * with this program; if not, write to the Free Software Foundation, Inc., 20e4243f13SShawn Guo * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 21e4243f13SShawn Guo */ 22e4243f13SShawn Guo 23e4243f13SShawn Guo #include <linux/kernel.h> 24e4243f13SShawn Guo #include <linux/init.h> 25e4243f13SShawn Guo #include <linux/ioport.h> 266de4d817SShawn Guo #include <linux/of.h> 276de4d817SShawn Guo #include <linux/of_device.h> 286de4d817SShawn Guo #include <linux/of_gpio.h> 29e4243f13SShawn Guo #include <linux/platform_device.h> 30e4243f13SShawn Guo #include <linux/delay.h> 31e4243f13SShawn Guo #include <linux/interrupt.h> 32e4243f13SShawn Guo #include <linux/dma-mapping.h> 33e4243f13SShawn Guo #include <linux/dmaengine.h> 34e4243f13SShawn Guo #include <linux/highmem.h> 35e4243f13SShawn Guo #include <linux/clk.h> 36e4243f13SShawn Guo #include <linux/err.h> 37e4243f13SShawn Guo #include <linux/completion.h> 38e4243f13SShawn Guo #include <linux/mmc/host.h> 39e4243f13SShawn Guo #include <linux/mmc/mmc.h> 40e4243f13SShawn Guo #include <linux/mmc/sdio.h> 41e4243f13SShawn Guo #include <linux/gpio.h> 42e4243f13SShawn Guo #include <linux/regulator/consumer.h> 4388b47679SPaul Gortmaker #include <linux/module.h> 449c92cf24SShawn Guo #include <linux/pinctrl/consumer.h> 4570e60206SShawn Guo #include <linux/stmp_device.h> 4681f38ee8SShawn Guo #include <linux/mmc/mxs-mmc.h> 478be3d3b2SMarek Vasut #include <linux/spi/mxs-spi.h> 48e4243f13SShawn Guo 49e4243f13SShawn Guo #define DRIVER_NAME "mxs-mmc" 50e4243f13SShawn Guo 51e4243f13SShawn Guo #define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \ 52e4243f13SShawn Guo BM_SSP_CTRL1_RESP_ERR_IRQ | \ 53e4243f13SShawn Guo BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \ 54e4243f13SShawn Guo BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \ 55e4243f13SShawn Guo BM_SSP_CTRL1_DATA_CRC_IRQ | \ 56e4243f13SShawn Guo BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \ 57e4243f13SShawn Guo BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \ 58e4243f13SShawn Guo BM_SSP_CTRL1_FIFO_OVERRUN_IRQ) 59e4243f13SShawn Guo 608be3d3b2SMarek Vasut /* card detect polling timeout */ 618be3d3b2SMarek Vasut #define MXS_MMC_DETECT_TIMEOUT (HZ/2) 62ef9b4d39SShawn Guo 63e4243f13SShawn Guo struct mxs_mmc_host { 64829c1bf4SMarek Vasut struct mxs_ssp ssp; 65829c1bf4SMarek Vasut 66e4243f13SShawn Guo struct mmc_host *mmc; 67e4243f13SShawn Guo struct mmc_request *mrq; 68e4243f13SShawn Guo struct mmc_command *cmd; 69e4243f13SShawn Guo struct mmc_data *data; 70e4243f13SShawn Guo 71e4243f13SShawn Guo unsigned char bus_width; 72e4243f13SShawn Guo spinlock_t lock; 73e4243f13SShawn Guo int sdio_irq_en; 7431b0ff5eSShawn Guo int wp_gpio; 75b6e76f10SMarek Vasut bool wp_inverted; 76e4243f13SShawn Guo }; 77e4243f13SShawn Guo 78e4243f13SShawn Guo static int mxs_mmc_get_ro(struct mmc_host *mmc) 79e4243f13SShawn Guo { 80e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 81b6e76f10SMarek Vasut int ret; 82e4243f13SShawn Guo 8331b0ff5eSShawn Guo if (!gpio_is_valid(host->wp_gpio)) 84e4243f13SShawn Guo return -EINVAL; 85e4243f13SShawn Guo 86b6e76f10SMarek Vasut ret = gpio_get_value(host->wp_gpio); 87b6e76f10SMarek Vasut 88b6e76f10SMarek Vasut if (host->wp_inverted) 89b6e76f10SMarek Vasut ret = !ret; 90b6e76f10SMarek Vasut 91b6e76f10SMarek Vasut return ret; 92e4243f13SShawn Guo } 93e4243f13SShawn Guo 94e4243f13SShawn Guo static int mxs_mmc_get_cd(struct mmc_host *mmc) 95e4243f13SShawn Guo { 96e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 97829c1bf4SMarek Vasut struct mxs_ssp *ssp = &host->ssp; 98e4243f13SShawn Guo 99829c1bf4SMarek Vasut return !(readl(ssp->base + HW_SSP_STATUS(ssp)) & 100e4243f13SShawn Guo BM_SSP_STATUS_CARD_DETECT); 101e4243f13SShawn Guo } 102e4243f13SShawn Guo 103e4243f13SShawn Guo static void mxs_mmc_reset(struct mxs_mmc_host *host) 104e4243f13SShawn Guo { 105829c1bf4SMarek Vasut struct mxs_ssp *ssp = &host->ssp; 106e4243f13SShawn Guo u32 ctrl0, ctrl1; 107e4243f13SShawn Guo 108829c1bf4SMarek Vasut stmp_reset_block(ssp->base); 109e4243f13SShawn Guo 110e4243f13SShawn Guo ctrl0 = BM_SSP_CTRL0_IGNORE_CRC; 111e4243f13SShawn Guo ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) | 112e4243f13SShawn Guo BF_SSP(0x7, CTRL1_WORD_LENGTH) | 113e4243f13SShawn Guo BM_SSP_CTRL1_DMA_ENABLE | 114e4243f13SShawn Guo BM_SSP_CTRL1_POLARITY | 115e4243f13SShawn Guo BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN | 116e4243f13SShawn Guo BM_SSP_CTRL1_DATA_CRC_IRQ_EN | 117e4243f13SShawn Guo BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN | 118e4243f13SShawn Guo BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN | 119e4243f13SShawn Guo BM_SSP_CTRL1_RESP_ERR_IRQ_EN; 120e4243f13SShawn Guo 121e4243f13SShawn Guo writel(BF_SSP(0xffff, TIMING_TIMEOUT) | 122e4243f13SShawn Guo BF_SSP(2, TIMING_CLOCK_DIVIDE) | 123e4243f13SShawn Guo BF_SSP(0, TIMING_CLOCK_RATE), 124829c1bf4SMarek Vasut ssp->base + HW_SSP_TIMING(ssp)); 125e4243f13SShawn Guo 126e4243f13SShawn Guo if (host->sdio_irq_en) { 127e4243f13SShawn Guo ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 128e4243f13SShawn Guo ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN; 129e4243f13SShawn Guo } 130e4243f13SShawn Guo 131829c1bf4SMarek Vasut writel(ctrl0, ssp->base + HW_SSP_CTRL0); 132829c1bf4SMarek Vasut writel(ctrl1, ssp->base + HW_SSP_CTRL1(ssp)); 133e4243f13SShawn Guo } 134e4243f13SShawn Guo 135e4243f13SShawn Guo static void mxs_mmc_start_cmd(struct mxs_mmc_host *host, 136e4243f13SShawn Guo struct mmc_command *cmd); 137e4243f13SShawn Guo 138e4243f13SShawn Guo static void mxs_mmc_request_done(struct mxs_mmc_host *host) 139e4243f13SShawn Guo { 140e4243f13SShawn Guo struct mmc_command *cmd = host->cmd; 141e4243f13SShawn Guo struct mmc_data *data = host->data; 142e4243f13SShawn Guo struct mmc_request *mrq = host->mrq; 143829c1bf4SMarek Vasut struct mxs_ssp *ssp = &host->ssp; 144e4243f13SShawn Guo 145e4243f13SShawn Guo if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) { 146e4243f13SShawn Guo if (mmc_resp_type(cmd) & MMC_RSP_136) { 147829c1bf4SMarek Vasut cmd->resp[3] = readl(ssp->base + HW_SSP_SDRESP0(ssp)); 148829c1bf4SMarek Vasut cmd->resp[2] = readl(ssp->base + HW_SSP_SDRESP1(ssp)); 149829c1bf4SMarek Vasut cmd->resp[1] = readl(ssp->base + HW_SSP_SDRESP2(ssp)); 150829c1bf4SMarek Vasut cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP3(ssp)); 151e4243f13SShawn Guo } else { 152829c1bf4SMarek Vasut cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP0(ssp)); 153e4243f13SShawn Guo } 154e4243f13SShawn Guo } 155e4243f13SShawn Guo 156e4243f13SShawn Guo if (data) { 157e4243f13SShawn Guo dma_unmap_sg(mmc_dev(host->mmc), data->sg, 15865defb9bSMarek Vasut data->sg_len, ssp->dma_dir); 159e4243f13SShawn Guo /* 160e4243f13SShawn Guo * If there was an error on any block, we mark all 161e4243f13SShawn Guo * data blocks as being in error. 162e4243f13SShawn Guo */ 163e4243f13SShawn Guo if (!data->error) 164e4243f13SShawn Guo data->bytes_xfered = data->blocks * data->blksz; 165e4243f13SShawn Guo else 166e4243f13SShawn Guo data->bytes_xfered = 0; 167e4243f13SShawn Guo 168e4243f13SShawn Guo host->data = NULL; 169e4243f13SShawn Guo if (mrq->stop) { 170e4243f13SShawn Guo mxs_mmc_start_cmd(host, mrq->stop); 171e4243f13SShawn Guo return; 172e4243f13SShawn Guo } 173e4243f13SShawn Guo } 174e4243f13SShawn Guo 175e4243f13SShawn Guo host->mrq = NULL; 176e4243f13SShawn Guo mmc_request_done(host->mmc, mrq); 177e4243f13SShawn Guo } 178e4243f13SShawn Guo 179e4243f13SShawn Guo static void mxs_mmc_dma_irq_callback(void *param) 180e4243f13SShawn Guo { 181e4243f13SShawn Guo struct mxs_mmc_host *host = param; 182e4243f13SShawn Guo 183e4243f13SShawn Guo mxs_mmc_request_done(host); 184e4243f13SShawn Guo } 185e4243f13SShawn Guo 186e4243f13SShawn Guo static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id) 187e4243f13SShawn Guo { 188e4243f13SShawn Guo struct mxs_mmc_host *host = dev_id; 189e4243f13SShawn Guo struct mmc_command *cmd = host->cmd; 190e4243f13SShawn Guo struct mmc_data *data = host->data; 191829c1bf4SMarek Vasut struct mxs_ssp *ssp = &host->ssp; 192e4243f13SShawn Guo u32 stat; 193e4243f13SShawn Guo 194e4243f13SShawn Guo spin_lock(&host->lock); 195e4243f13SShawn Guo 196829c1bf4SMarek Vasut stat = readl(ssp->base + HW_SSP_CTRL1(ssp)); 197e4243f13SShawn Guo writel(stat & MXS_MMC_IRQ_BITS, 198829c1bf4SMarek Vasut ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR); 199e4243f13SShawn Guo 2001af36b2aSLauri Hintsala spin_unlock(&host->lock); 2011af36b2aSLauri Hintsala 202e4243f13SShawn Guo if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN)) 203e4243f13SShawn Guo mmc_signal_sdio_irq(host->mmc); 204e4243f13SShawn Guo 205e4243f13SShawn Guo if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ) 206e4243f13SShawn Guo cmd->error = -ETIMEDOUT; 207e4243f13SShawn Guo else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ) 208e4243f13SShawn Guo cmd->error = -EIO; 209e4243f13SShawn Guo 210e4243f13SShawn Guo if (data) { 211e4243f13SShawn Guo if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | 212e4243f13SShawn Guo BM_SSP_CTRL1_RECV_TIMEOUT_IRQ)) 213e4243f13SShawn Guo data->error = -ETIMEDOUT; 214e4243f13SShawn Guo else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ) 215e4243f13SShawn Guo data->error = -EILSEQ; 216e4243f13SShawn Guo else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | 217e4243f13SShawn Guo BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)) 218e4243f13SShawn Guo data->error = -EIO; 219e4243f13SShawn Guo } 220e4243f13SShawn Guo 221e4243f13SShawn Guo return IRQ_HANDLED; 222e4243f13SShawn Guo } 223e4243f13SShawn Guo 224e4243f13SShawn Guo static struct dma_async_tx_descriptor *mxs_mmc_prep_dma( 225921de864SHuang Shijie struct mxs_mmc_host *host, unsigned long flags) 226e4243f13SShawn Guo { 22765defb9bSMarek Vasut struct mxs_ssp *ssp = &host->ssp; 228e4243f13SShawn Guo struct dma_async_tx_descriptor *desc; 229e4243f13SShawn Guo struct mmc_data *data = host->data; 230e4243f13SShawn Guo struct scatterlist * sgl; 231e4243f13SShawn Guo unsigned int sg_len; 232e4243f13SShawn Guo 233e4243f13SShawn Guo if (data) { 234e4243f13SShawn Guo /* data */ 235e4243f13SShawn Guo dma_map_sg(mmc_dev(host->mmc), data->sg, 23665defb9bSMarek Vasut data->sg_len, ssp->dma_dir); 237e4243f13SShawn Guo sgl = data->sg; 238e4243f13SShawn Guo sg_len = data->sg_len; 239e4243f13SShawn Guo } else { 240e4243f13SShawn Guo /* pio */ 24165defb9bSMarek Vasut sgl = (struct scatterlist *) ssp->ssp_pio_words; 242e4243f13SShawn Guo sg_len = SSP_PIO_NUM; 243e4243f13SShawn Guo } 244e4243f13SShawn Guo 24565defb9bSMarek Vasut desc = dmaengine_prep_slave_sg(ssp->dmach, 24665defb9bSMarek Vasut sgl, sg_len, ssp->slave_dirn, flags); 247e4243f13SShawn Guo if (desc) { 248e4243f13SShawn Guo desc->callback = mxs_mmc_dma_irq_callback; 249e4243f13SShawn Guo desc->callback_param = host; 250e4243f13SShawn Guo } else { 251e4243f13SShawn Guo if (data) 252e4243f13SShawn Guo dma_unmap_sg(mmc_dev(host->mmc), data->sg, 25365defb9bSMarek Vasut data->sg_len, ssp->dma_dir); 254e4243f13SShawn Guo } 255e4243f13SShawn Guo 256e4243f13SShawn Guo return desc; 257e4243f13SShawn Guo } 258e4243f13SShawn Guo 259e4243f13SShawn Guo static void mxs_mmc_bc(struct mxs_mmc_host *host) 260e4243f13SShawn Guo { 26165defb9bSMarek Vasut struct mxs_ssp *ssp = &host->ssp; 262e4243f13SShawn Guo struct mmc_command *cmd = host->cmd; 263e4243f13SShawn Guo struct dma_async_tx_descriptor *desc; 264e4243f13SShawn Guo u32 ctrl0, cmd0, cmd1; 265e4243f13SShawn Guo 266e4243f13SShawn Guo ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC; 267e4243f13SShawn Guo cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC; 268e4243f13SShawn Guo cmd1 = cmd->arg; 269e4243f13SShawn Guo 270e4243f13SShawn Guo if (host->sdio_irq_en) { 271e4243f13SShawn Guo ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 272e4243f13SShawn Guo cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 273e4243f13SShawn Guo } 274e4243f13SShawn Guo 27565defb9bSMarek Vasut ssp->ssp_pio_words[0] = ctrl0; 27665defb9bSMarek Vasut ssp->ssp_pio_words[1] = cmd0; 27765defb9bSMarek Vasut ssp->ssp_pio_words[2] = cmd1; 27865defb9bSMarek Vasut ssp->dma_dir = DMA_NONE; 27965defb9bSMarek Vasut ssp->slave_dirn = DMA_TRANS_NONE; 280921de864SHuang Shijie desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK); 281e4243f13SShawn Guo if (!desc) 282e4243f13SShawn Guo goto out; 283e4243f13SShawn Guo 284e4243f13SShawn Guo dmaengine_submit(desc); 28565defb9bSMarek Vasut dma_async_issue_pending(ssp->dmach); 286e4243f13SShawn Guo return; 287e4243f13SShawn Guo 288e4243f13SShawn Guo out: 289e4243f13SShawn Guo dev_warn(mmc_dev(host->mmc), 290e4243f13SShawn Guo "%s: failed to prep dma\n", __func__); 291e4243f13SShawn Guo } 292e4243f13SShawn Guo 293e4243f13SShawn Guo static void mxs_mmc_ac(struct mxs_mmc_host *host) 294e4243f13SShawn Guo { 29565defb9bSMarek Vasut struct mxs_ssp *ssp = &host->ssp; 296e4243f13SShawn Guo struct mmc_command *cmd = host->cmd; 297e4243f13SShawn Guo struct dma_async_tx_descriptor *desc; 298e4243f13SShawn Guo u32 ignore_crc, get_resp, long_resp; 299e4243f13SShawn Guo u32 ctrl0, cmd0, cmd1; 300e4243f13SShawn Guo 301e4243f13SShawn Guo ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ? 302e4243f13SShawn Guo 0 : BM_SSP_CTRL0_IGNORE_CRC; 303e4243f13SShawn Guo get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ? 304e4243f13SShawn Guo BM_SSP_CTRL0_GET_RESP : 0; 305e4243f13SShawn Guo long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ? 306e4243f13SShawn Guo BM_SSP_CTRL0_LONG_RESP : 0; 307e4243f13SShawn Guo 308e4243f13SShawn Guo ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp; 309e4243f13SShawn Guo cmd0 = BF_SSP(cmd->opcode, CMD0_CMD); 310e4243f13SShawn Guo cmd1 = cmd->arg; 311e4243f13SShawn Guo 312e4243f13SShawn Guo if (host->sdio_irq_en) { 313e4243f13SShawn Guo ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 314e4243f13SShawn Guo cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 315e4243f13SShawn Guo } 316e4243f13SShawn Guo 31765defb9bSMarek Vasut ssp->ssp_pio_words[0] = ctrl0; 31865defb9bSMarek Vasut ssp->ssp_pio_words[1] = cmd0; 31965defb9bSMarek Vasut ssp->ssp_pio_words[2] = cmd1; 32065defb9bSMarek Vasut ssp->dma_dir = DMA_NONE; 32165defb9bSMarek Vasut ssp->slave_dirn = DMA_TRANS_NONE; 322921de864SHuang Shijie desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK); 323e4243f13SShawn Guo if (!desc) 324e4243f13SShawn Guo goto out; 325e4243f13SShawn Guo 326e4243f13SShawn Guo dmaengine_submit(desc); 32765defb9bSMarek Vasut dma_async_issue_pending(ssp->dmach); 328e4243f13SShawn Guo return; 329e4243f13SShawn Guo 330e4243f13SShawn Guo out: 331e4243f13SShawn Guo dev_warn(mmc_dev(host->mmc), 332e4243f13SShawn Guo "%s: failed to prep dma\n", __func__); 333e4243f13SShawn Guo } 334e4243f13SShawn Guo 335e4243f13SShawn Guo static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns) 336e4243f13SShawn Guo { 337e4243f13SShawn Guo const unsigned int ssp_timeout_mul = 4096; 338e4243f13SShawn Guo /* 339e4243f13SShawn Guo * Calculate ticks in ms since ns are large numbers 340e4243f13SShawn Guo * and might overflow 341e4243f13SShawn Guo */ 342e4243f13SShawn Guo const unsigned int clock_per_ms = clock_rate / 1000; 343e4243f13SShawn Guo const unsigned int ms = ns / 1000; 344e4243f13SShawn Guo const unsigned int ticks = ms * clock_per_ms; 345e4243f13SShawn Guo const unsigned int ssp_ticks = ticks / ssp_timeout_mul; 346e4243f13SShawn Guo 347e4243f13SShawn Guo WARN_ON(ssp_ticks == 0); 348e4243f13SShawn Guo return ssp_ticks; 349e4243f13SShawn Guo } 350e4243f13SShawn Guo 351e4243f13SShawn Guo static void mxs_mmc_adtc(struct mxs_mmc_host *host) 352e4243f13SShawn Guo { 353e4243f13SShawn Guo struct mmc_command *cmd = host->cmd; 354e4243f13SShawn Guo struct mmc_data *data = cmd->data; 355e4243f13SShawn Guo struct dma_async_tx_descriptor *desc; 356e4243f13SShawn Guo struct scatterlist *sgl = data->sg, *sg; 357e4243f13SShawn Guo unsigned int sg_len = data->sg_len; 358e4243f13SShawn Guo int i; 359e4243f13SShawn Guo 360e4243f13SShawn Guo unsigned short dma_data_dir, timeout; 36105f5799cSVinod Koul enum dma_transfer_direction slave_dirn; 362e4243f13SShawn Guo unsigned int data_size = 0, log2_blksz; 363e4243f13SShawn Guo unsigned int blocks = data->blocks; 364e4243f13SShawn Guo 365829c1bf4SMarek Vasut struct mxs_ssp *ssp = &host->ssp; 366829c1bf4SMarek Vasut 367e4243f13SShawn Guo u32 ignore_crc, get_resp, long_resp, read; 368e4243f13SShawn Guo u32 ctrl0, cmd0, cmd1, val; 369e4243f13SShawn Guo 370e4243f13SShawn Guo ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ? 371e4243f13SShawn Guo 0 : BM_SSP_CTRL0_IGNORE_CRC; 372e4243f13SShawn Guo get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ? 373e4243f13SShawn Guo BM_SSP_CTRL0_GET_RESP : 0; 374e4243f13SShawn Guo long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ? 375e4243f13SShawn Guo BM_SSP_CTRL0_LONG_RESP : 0; 376e4243f13SShawn Guo 377e4243f13SShawn Guo if (data->flags & MMC_DATA_WRITE) { 378e4243f13SShawn Guo dma_data_dir = DMA_TO_DEVICE; 37905f5799cSVinod Koul slave_dirn = DMA_MEM_TO_DEV; 380e4243f13SShawn Guo read = 0; 381e4243f13SShawn Guo } else { 382e4243f13SShawn Guo dma_data_dir = DMA_FROM_DEVICE; 38305f5799cSVinod Koul slave_dirn = DMA_DEV_TO_MEM; 384e4243f13SShawn Guo read = BM_SSP_CTRL0_READ; 385e4243f13SShawn Guo } 386e4243f13SShawn Guo 387e4243f13SShawn Guo ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) | 388e4243f13SShawn Guo ignore_crc | get_resp | long_resp | 389e4243f13SShawn Guo BM_SSP_CTRL0_DATA_XFER | read | 390e4243f13SShawn Guo BM_SSP_CTRL0_WAIT_FOR_IRQ | 391e4243f13SShawn Guo BM_SSP_CTRL0_ENABLE; 392e4243f13SShawn Guo 393e4243f13SShawn Guo cmd0 = BF_SSP(cmd->opcode, CMD0_CMD); 394e4243f13SShawn Guo 395e4243f13SShawn Guo /* get logarithm to base 2 of block size for setting register */ 396e4243f13SShawn Guo log2_blksz = ilog2(data->blksz); 397e4243f13SShawn Guo 398e4243f13SShawn Guo /* 399e4243f13SShawn Guo * take special care of the case that data size from data->sg 400e4243f13SShawn Guo * is not equal to blocks x blksz 401e4243f13SShawn Guo */ 402e4243f13SShawn Guo for_each_sg(sgl, sg, sg_len, i) 403e4243f13SShawn Guo data_size += sg->length; 404e4243f13SShawn Guo 405e4243f13SShawn Guo if (data_size != data->blocks * data->blksz) 406e4243f13SShawn Guo blocks = 1; 407e4243f13SShawn Guo 408e4243f13SShawn Guo /* xfer count, block size and count need to be set differently */ 409829c1bf4SMarek Vasut if (ssp_is_old(ssp)) { 410e4243f13SShawn Guo ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT); 411e4243f13SShawn Guo cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) | 412e4243f13SShawn Guo BF_SSP(blocks - 1, CMD0_BLOCK_COUNT); 413e4243f13SShawn Guo } else { 414829c1bf4SMarek Vasut writel(data_size, ssp->base + HW_SSP_XFER_SIZE); 415e4243f13SShawn Guo writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) | 416e4243f13SShawn Guo BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT), 417829c1bf4SMarek Vasut ssp->base + HW_SSP_BLOCK_SIZE); 418e4243f13SShawn Guo } 419e4243f13SShawn Guo 420e4243f13SShawn Guo if ((cmd->opcode == MMC_STOP_TRANSMISSION) || 421e4243f13SShawn Guo (cmd->opcode == SD_IO_RW_EXTENDED)) 422e4243f13SShawn Guo cmd0 |= BM_SSP_CMD0_APPEND_8CYC; 423e4243f13SShawn Guo 424e4243f13SShawn Guo cmd1 = cmd->arg; 425e4243f13SShawn Guo 426e4243f13SShawn Guo if (host->sdio_irq_en) { 427e4243f13SShawn Guo ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 428e4243f13SShawn Guo cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 429e4243f13SShawn Guo } 430e4243f13SShawn Guo 431e4243f13SShawn Guo /* set the timeout count */ 432829c1bf4SMarek Vasut timeout = mxs_ns_to_ssp_ticks(ssp->clk_rate, data->timeout_ns); 433829c1bf4SMarek Vasut val = readl(ssp->base + HW_SSP_TIMING(ssp)); 434e4243f13SShawn Guo val &= ~(BM_SSP_TIMING_TIMEOUT); 435e4243f13SShawn Guo val |= BF_SSP(timeout, TIMING_TIMEOUT); 436829c1bf4SMarek Vasut writel(val, ssp->base + HW_SSP_TIMING(ssp)); 437e4243f13SShawn Guo 438e4243f13SShawn Guo /* pio */ 43965defb9bSMarek Vasut ssp->ssp_pio_words[0] = ctrl0; 44065defb9bSMarek Vasut ssp->ssp_pio_words[1] = cmd0; 44165defb9bSMarek Vasut ssp->ssp_pio_words[2] = cmd1; 44265defb9bSMarek Vasut ssp->dma_dir = DMA_NONE; 44365defb9bSMarek Vasut ssp->slave_dirn = DMA_TRANS_NONE; 444e4243f13SShawn Guo desc = mxs_mmc_prep_dma(host, 0); 445e4243f13SShawn Guo if (!desc) 446e4243f13SShawn Guo goto out; 447e4243f13SShawn Guo 448e4243f13SShawn Guo /* append data sg */ 449e4243f13SShawn Guo WARN_ON(host->data != NULL); 450e4243f13SShawn Guo host->data = data; 45165defb9bSMarek Vasut ssp->dma_dir = dma_data_dir; 45265defb9bSMarek Vasut ssp->slave_dirn = slave_dirn; 453921de864SHuang Shijie desc = mxs_mmc_prep_dma(host, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 454e4243f13SShawn Guo if (!desc) 455e4243f13SShawn Guo goto out; 456e4243f13SShawn Guo 457e4243f13SShawn Guo dmaengine_submit(desc); 45865defb9bSMarek Vasut dma_async_issue_pending(ssp->dmach); 459e4243f13SShawn Guo return; 460e4243f13SShawn Guo out: 461e4243f13SShawn Guo dev_warn(mmc_dev(host->mmc), 462e4243f13SShawn Guo "%s: failed to prep dma\n", __func__); 463e4243f13SShawn Guo } 464e4243f13SShawn Guo 465e4243f13SShawn Guo static void mxs_mmc_start_cmd(struct mxs_mmc_host *host, 466e4243f13SShawn Guo struct mmc_command *cmd) 467e4243f13SShawn Guo { 468e4243f13SShawn Guo host->cmd = cmd; 469e4243f13SShawn Guo 470e4243f13SShawn Guo switch (mmc_cmd_type(cmd)) { 471e4243f13SShawn Guo case MMC_CMD_BC: 472e4243f13SShawn Guo mxs_mmc_bc(host); 473e4243f13SShawn Guo break; 474e4243f13SShawn Guo case MMC_CMD_BCR: 475e4243f13SShawn Guo mxs_mmc_ac(host); 476e4243f13SShawn Guo break; 477e4243f13SShawn Guo case MMC_CMD_AC: 478e4243f13SShawn Guo mxs_mmc_ac(host); 479e4243f13SShawn Guo break; 480e4243f13SShawn Guo case MMC_CMD_ADTC: 481e4243f13SShawn Guo mxs_mmc_adtc(host); 482e4243f13SShawn Guo break; 483e4243f13SShawn Guo default: 484e4243f13SShawn Guo dev_warn(mmc_dev(host->mmc), 485e4243f13SShawn Guo "%s: unknown MMC command\n", __func__); 486e4243f13SShawn Guo break; 487e4243f13SShawn Guo } 488e4243f13SShawn Guo } 489e4243f13SShawn Guo 490e4243f13SShawn Guo static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 491e4243f13SShawn Guo { 492e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 493e4243f13SShawn Guo 494e4243f13SShawn Guo WARN_ON(host->mrq != NULL); 495e4243f13SShawn Guo host->mrq = mrq; 496e4243f13SShawn Guo mxs_mmc_start_cmd(host, mrq->cmd); 497e4243f13SShawn Guo } 498e4243f13SShawn Guo 499e4243f13SShawn Guo static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 500e4243f13SShawn Guo { 501e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 502e4243f13SShawn Guo 503e4243f13SShawn Guo if (ios->bus_width == MMC_BUS_WIDTH_8) 504e4243f13SShawn Guo host->bus_width = 2; 505e4243f13SShawn Guo else if (ios->bus_width == MMC_BUS_WIDTH_4) 506e4243f13SShawn Guo host->bus_width = 1; 507e4243f13SShawn Guo else 508e4243f13SShawn Guo host->bus_width = 0; 509e4243f13SShawn Guo 510e4243f13SShawn Guo if (ios->clock) 51113082398SMarek Vasut mxs_ssp_set_clk_rate(&host->ssp, ios->clock); 512e4243f13SShawn Guo } 513e4243f13SShawn Guo 514e4243f13SShawn Guo static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 515e4243f13SShawn Guo { 516e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 517829c1bf4SMarek Vasut struct mxs_ssp *ssp = &host->ssp; 518e4243f13SShawn Guo unsigned long flags; 519e4243f13SShawn Guo 520e4243f13SShawn Guo spin_lock_irqsave(&host->lock, flags); 521e4243f13SShawn Guo 522e4243f13SShawn Guo host->sdio_irq_en = enable; 523e4243f13SShawn Guo 524e4243f13SShawn Guo if (enable) { 525e4243f13SShawn Guo writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, 526829c1bf4SMarek Vasut ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); 527e4243f13SShawn Guo writel(BM_SSP_CTRL1_SDIO_IRQ_EN, 528e0bf141dSShawn Guo host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_SET); 529e4243f13SShawn Guo } else { 530e4243f13SShawn Guo writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, 531829c1bf4SMarek Vasut ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); 532e4243f13SShawn Guo writel(BM_SSP_CTRL1_SDIO_IRQ_EN, 533829c1bf4SMarek Vasut ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR); 534e4243f13SShawn Guo } 535e4243f13SShawn Guo 536e4243f13SShawn Guo spin_unlock_irqrestore(&host->lock, flags); 537fc108d24SLauri Hintsala 538ac48f6cbSMark Brown if (enable && readl(ssp->base + HW_SSP_STATUS(ssp)) & 539fc108d24SLauri Hintsala BM_SSP_STATUS_SDIO_IRQ) 540fc108d24SLauri Hintsala mmc_signal_sdio_irq(host->mmc); 541fc108d24SLauri Hintsala 542e4243f13SShawn Guo } 543e4243f13SShawn Guo 544e4243f13SShawn Guo static const struct mmc_host_ops mxs_mmc_ops = { 545e4243f13SShawn Guo .request = mxs_mmc_request, 546e4243f13SShawn Guo .get_ro = mxs_mmc_get_ro, 547e4243f13SShawn Guo .get_cd = mxs_mmc_get_cd, 548e4243f13SShawn Guo .set_ios = mxs_mmc_set_ios, 549e4243f13SShawn Guo .enable_sdio_irq = mxs_mmc_enable_sdio_irq, 550e4243f13SShawn Guo }; 551e4243f13SShawn Guo 552e4243f13SShawn Guo static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param) 553e4243f13SShawn Guo { 554e4243f13SShawn Guo struct mxs_mmc_host *host = param; 55565defb9bSMarek Vasut struct mxs_ssp *ssp = &host->ssp; 556e4243f13SShawn Guo 557e4243f13SShawn Guo if (!mxs_dma_is_apbh(chan)) 558e4243f13SShawn Guo return false; 559e4243f13SShawn Guo 56065defb9bSMarek Vasut if (chan->chan_id != ssp->dma_channel) 561e4243f13SShawn Guo return false; 562e4243f13SShawn Guo 56365defb9bSMarek Vasut chan->private = &ssp->dma_data; 564e4243f13SShawn Guo 565e4243f13SShawn Guo return true; 566e4243f13SShawn Guo } 567e4243f13SShawn Guo 568600a991fSMarek Vasut static struct platform_device_id mxs_ssp_ids[] = { 569ef9b4d39SShawn Guo { 570ef9b4d39SShawn Guo .name = "imx23-mmc", 571600a991fSMarek Vasut .driver_data = IMX23_SSP, 572ef9b4d39SShawn Guo }, { 573ef9b4d39SShawn Guo .name = "imx28-mmc", 574600a991fSMarek Vasut .driver_data = IMX28_SSP, 575ef9b4d39SShawn Guo }, { 576ef9b4d39SShawn Guo /* sentinel */ 577ef9b4d39SShawn Guo } 578ef9b4d39SShawn Guo }; 579600a991fSMarek Vasut MODULE_DEVICE_TABLE(platform, mxs_ssp_ids); 580ef9b4d39SShawn Guo 5816de4d817SShawn Guo static const struct of_device_id mxs_mmc_dt_ids[] = { 582600a991fSMarek Vasut { .compatible = "fsl,imx23-mmc", .data = (void *) IMX23_SSP, }, 583600a991fSMarek Vasut { .compatible = "fsl,imx28-mmc", .data = (void *) IMX28_SSP, }, 5846de4d817SShawn Guo { /* sentinel */ } 5856de4d817SShawn Guo }; 5866de4d817SShawn Guo MODULE_DEVICE_TABLE(of, mxs_mmc_dt_ids); 5876de4d817SShawn Guo 588e4243f13SShawn Guo static int mxs_mmc_probe(struct platform_device *pdev) 589e4243f13SShawn Guo { 5906de4d817SShawn Guo const struct of_device_id *of_id = 5916de4d817SShawn Guo of_match_device(mxs_mmc_dt_ids, &pdev->dev); 5926de4d817SShawn Guo struct device_node *np = pdev->dev.of_node; 593e4243f13SShawn Guo struct mxs_mmc_host *host; 594e4243f13SShawn Guo struct mmc_host *mmc; 595df06bfc7SShawn Guo struct resource *iores, *dmares; 596e4243f13SShawn Guo struct mxs_mmc_platform_data *pdata; 5979c92cf24SShawn Guo struct pinctrl *pinctrl; 598e4243f13SShawn Guo int ret = 0, irq_err, irq_dma; 599e4243f13SShawn Guo dma_cap_mask_t mask; 6004dc5a79fSShawn Guo struct regulator *reg_vmmc; 601b6e76f10SMarek Vasut enum of_gpio_flags flags; 602829c1bf4SMarek Vasut struct mxs_ssp *ssp; 603e4243f13SShawn Guo 604e4243f13SShawn Guo iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 605e4243f13SShawn Guo dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0); 606e4243f13SShawn Guo irq_err = platform_get_irq(pdev, 0); 607e4243f13SShawn Guo irq_dma = platform_get_irq(pdev, 1); 6086de4d817SShawn Guo if (!iores || irq_err < 0 || irq_dma < 0) 609e4243f13SShawn Guo return -EINVAL; 610e4243f13SShawn Guo 611e4243f13SShawn Guo mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev); 612df06bfc7SShawn Guo if (!mmc) 613df06bfc7SShawn Guo return -ENOMEM; 614e4243f13SShawn Guo 615e4243f13SShawn Guo host = mmc_priv(mmc); 616829c1bf4SMarek Vasut ssp = &host->ssp; 617829c1bf4SMarek Vasut ssp->dev = &pdev->dev; 618829c1bf4SMarek Vasut ssp->base = devm_request_and_ioremap(&pdev->dev, iores); 619829c1bf4SMarek Vasut if (!ssp->base) { 620df06bfc7SShawn Guo ret = -EADDRNOTAVAIL; 621e4243f13SShawn Guo goto out_mmc_free; 622e4243f13SShawn Guo } 623e4243f13SShawn Guo 6246de4d817SShawn Guo if (np) { 625829c1bf4SMarek Vasut ssp->devid = (enum mxs_ssp_id) of_id->data; 6266de4d817SShawn Guo /* 6276de4d817SShawn Guo * TODO: This is a temporary solution and should be changed 6286de4d817SShawn Guo * to use generic DMA binding later when the helpers get in. 6296de4d817SShawn Guo */ 6306de4d817SShawn Guo ret = of_property_read_u32(np, "fsl,ssp-dma-channel", 63165defb9bSMarek Vasut &ssp->dma_channel); 6326de4d817SShawn Guo if (ret) { 6336de4d817SShawn Guo dev_err(mmc_dev(host->mmc), 6346de4d817SShawn Guo "failed to get dma channel\n"); 6356de4d817SShawn Guo goto out_mmc_free; 6366de4d817SShawn Guo } 6376de4d817SShawn Guo } else { 638829c1bf4SMarek Vasut ssp->devid = pdev->id_entry->driver_data; 63965defb9bSMarek Vasut ssp->dma_channel = dmares->start; 6406de4d817SShawn Guo } 6416de4d817SShawn Guo 6426de4d817SShawn Guo host->mmc = mmc; 643e4243f13SShawn Guo host->sdio_irq_en = 0; 644e4243f13SShawn Guo 6454dc5a79fSShawn Guo reg_vmmc = devm_regulator_get(&pdev->dev, "vmmc"); 6464dc5a79fSShawn Guo if (!IS_ERR(reg_vmmc)) { 6474dc5a79fSShawn Guo ret = regulator_enable(reg_vmmc); 6484dc5a79fSShawn Guo if (ret) { 6494dc5a79fSShawn Guo dev_err(&pdev->dev, 6504dc5a79fSShawn Guo "Failed to enable vmmc regulator: %d\n", ret); 6514dc5a79fSShawn Guo goto out_mmc_free; 6524dc5a79fSShawn Guo } 6534dc5a79fSShawn Guo } 6544dc5a79fSShawn Guo 6559c92cf24SShawn Guo pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 6569c92cf24SShawn Guo if (IS_ERR(pinctrl)) { 6579c92cf24SShawn Guo ret = PTR_ERR(pinctrl); 6586de4d817SShawn Guo goto out_mmc_free; 6599c92cf24SShawn Guo } 6609c92cf24SShawn Guo 661829c1bf4SMarek Vasut ssp->clk = clk_get(&pdev->dev, NULL); 662829c1bf4SMarek Vasut if (IS_ERR(ssp->clk)) { 663829c1bf4SMarek Vasut ret = PTR_ERR(ssp->clk); 664df06bfc7SShawn Guo goto out_mmc_free; 665e4243f13SShawn Guo } 666829c1bf4SMarek Vasut clk_prepare_enable(ssp->clk); 667e4243f13SShawn Guo 668e4243f13SShawn Guo mxs_mmc_reset(host); 669e4243f13SShawn Guo 670e4243f13SShawn Guo dma_cap_zero(mask); 671e4243f13SShawn Guo dma_cap_set(DMA_SLAVE, mask); 67265defb9bSMarek Vasut ssp->dma_data.chan_irq = irq_dma; 67365defb9bSMarek Vasut ssp->dmach = dma_request_channel(mask, mxs_mmc_dma_filter, host); 67465defb9bSMarek Vasut if (!ssp->dmach) { 675e4243f13SShawn Guo dev_err(mmc_dev(host->mmc), 676e4243f13SShawn Guo "%s: failed to request dma\n", __func__); 677e4243f13SShawn Guo goto out_clk_put; 678e4243f13SShawn Guo } 679e4243f13SShawn Guo 680e4243f13SShawn Guo /* set mmc core parameters */ 681e4243f13SShawn Guo mmc->ops = &mxs_mmc_ops; 682e4243f13SShawn Guo mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 683e4243f13SShawn Guo MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL; 684e4243f13SShawn Guo 685e4243f13SShawn Guo pdata = mmc_dev(host->mmc)->platform_data; 6866de4d817SShawn Guo if (!pdata) { 6876de4d817SShawn Guo u32 bus_width = 0; 6886de4d817SShawn Guo of_property_read_u32(np, "bus-width", &bus_width); 6896de4d817SShawn Guo if (bus_width == 4) 6906de4d817SShawn Guo mmc->caps |= MMC_CAP_4_BIT_DATA; 6916de4d817SShawn Guo else if (bus_width == 8) 6926de4d817SShawn Guo mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA; 693b6e76f10SMarek Vasut host->wp_gpio = of_get_named_gpio_flags(np, "wp-gpios", 0, 694b6e76f10SMarek Vasut &flags); 695b6e76f10SMarek Vasut if (flags & OF_GPIO_ACTIVE_LOW) 696b6e76f10SMarek Vasut host->wp_inverted = 1; 6976de4d817SShawn Guo } else { 698e4243f13SShawn Guo if (pdata->flags & SLOTF_8_BIT_CAPABLE) 699e4243f13SShawn Guo mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA; 700e4243f13SShawn Guo if (pdata->flags & SLOTF_4_BIT_CAPABLE) 701e4243f13SShawn Guo mmc->caps |= MMC_CAP_4_BIT_DATA; 70231b0ff5eSShawn Guo host->wp_gpio = pdata->wp_gpio; 703e4243f13SShawn Guo } 704e4243f13SShawn Guo 705e4243f13SShawn Guo mmc->f_min = 400000; 706e4243f13SShawn Guo mmc->f_max = 288000000; 707e4243f13SShawn Guo mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 708e4243f13SShawn Guo 709e4243f13SShawn Guo mmc->max_segs = 52; 710e4243f13SShawn Guo mmc->max_blk_size = 1 << 0xf; 711829c1bf4SMarek Vasut mmc->max_blk_count = (ssp_is_old(ssp)) ? 0xff : 0xffffff; 712829c1bf4SMarek Vasut mmc->max_req_size = (ssp_is_old(ssp)) ? 0xffff : 0xffffffff; 71365defb9bSMarek Vasut mmc->max_seg_size = dma_get_max_seg_size(ssp->dmach->device->dev); 714e4243f13SShawn Guo 715e4243f13SShawn Guo platform_set_drvdata(pdev, mmc); 716e4243f13SShawn Guo 717df06bfc7SShawn Guo ret = devm_request_irq(&pdev->dev, irq_err, mxs_mmc_irq_handler, 0, 718df06bfc7SShawn Guo DRIVER_NAME, host); 719e4243f13SShawn Guo if (ret) 720e4243f13SShawn Guo goto out_free_dma; 721e4243f13SShawn Guo 722e4243f13SShawn Guo spin_lock_init(&host->lock); 723e4243f13SShawn Guo 724e4243f13SShawn Guo ret = mmc_add_host(mmc); 725e4243f13SShawn Guo if (ret) 726df06bfc7SShawn Guo goto out_free_dma; 727e4243f13SShawn Guo 728e4243f13SShawn Guo dev_info(mmc_dev(host->mmc), "initialized\n"); 729e4243f13SShawn Guo 730e4243f13SShawn Guo return 0; 731e4243f13SShawn Guo 732e4243f13SShawn Guo out_free_dma: 73365defb9bSMarek Vasut if (ssp->dmach) 73465defb9bSMarek Vasut dma_release_channel(ssp->dmach); 735e4243f13SShawn Guo out_clk_put: 736829c1bf4SMarek Vasut clk_disable_unprepare(ssp->clk); 737829c1bf4SMarek Vasut clk_put(ssp->clk); 738e4243f13SShawn Guo out_mmc_free: 739e4243f13SShawn Guo mmc_free_host(mmc); 740e4243f13SShawn Guo return ret; 741e4243f13SShawn Guo } 742e4243f13SShawn Guo 743e4243f13SShawn Guo static int mxs_mmc_remove(struct platform_device *pdev) 744e4243f13SShawn Guo { 745e4243f13SShawn Guo struct mmc_host *mmc = platform_get_drvdata(pdev); 746e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 747829c1bf4SMarek Vasut struct mxs_ssp *ssp = &host->ssp; 748e4243f13SShawn Guo 749e4243f13SShawn Guo mmc_remove_host(mmc); 750e4243f13SShawn Guo 751e4243f13SShawn Guo platform_set_drvdata(pdev, NULL); 752e4243f13SShawn Guo 75365defb9bSMarek Vasut if (ssp->dmach) 75465defb9bSMarek Vasut dma_release_channel(ssp->dmach); 755e4243f13SShawn Guo 756829c1bf4SMarek Vasut clk_disable_unprepare(ssp->clk); 757829c1bf4SMarek Vasut clk_put(ssp->clk); 758e4243f13SShawn Guo 759e4243f13SShawn Guo mmc_free_host(mmc); 760e4243f13SShawn Guo 761e4243f13SShawn Guo return 0; 762e4243f13SShawn Guo } 763e4243f13SShawn Guo 764e4243f13SShawn Guo #ifdef CONFIG_PM 765e4243f13SShawn Guo static int mxs_mmc_suspend(struct device *dev) 766e4243f13SShawn Guo { 767e4243f13SShawn Guo struct mmc_host *mmc = dev_get_drvdata(dev); 768e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 769829c1bf4SMarek Vasut struct mxs_ssp *ssp = &host->ssp; 770e4243f13SShawn Guo int ret = 0; 771e4243f13SShawn Guo 772e4243f13SShawn Guo ret = mmc_suspend_host(mmc); 773e4243f13SShawn Guo 774829c1bf4SMarek Vasut clk_disable_unprepare(ssp->clk); 775e4243f13SShawn Guo 776e4243f13SShawn Guo return ret; 777e4243f13SShawn Guo } 778e4243f13SShawn Guo 779e4243f13SShawn Guo static int mxs_mmc_resume(struct device *dev) 780e4243f13SShawn Guo { 781e4243f13SShawn Guo struct mmc_host *mmc = dev_get_drvdata(dev); 782e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 783829c1bf4SMarek Vasut struct mxs_ssp *ssp = &host->ssp; 784e4243f13SShawn Guo int ret = 0; 785e4243f13SShawn Guo 786829c1bf4SMarek Vasut clk_prepare_enable(ssp->clk); 787e4243f13SShawn Guo 788e4243f13SShawn Guo ret = mmc_resume_host(mmc); 789e4243f13SShawn Guo 790e4243f13SShawn Guo return ret; 791e4243f13SShawn Guo } 792e4243f13SShawn Guo 793e4243f13SShawn Guo static const struct dev_pm_ops mxs_mmc_pm_ops = { 794e4243f13SShawn Guo .suspend = mxs_mmc_suspend, 795e4243f13SShawn Guo .resume = mxs_mmc_resume, 796e4243f13SShawn Guo }; 797e4243f13SShawn Guo #endif 798e4243f13SShawn Guo 799e4243f13SShawn Guo static struct platform_driver mxs_mmc_driver = { 800e4243f13SShawn Guo .probe = mxs_mmc_probe, 801e4243f13SShawn Guo .remove = mxs_mmc_remove, 802600a991fSMarek Vasut .id_table = mxs_ssp_ids, 803e4243f13SShawn Guo .driver = { 804e4243f13SShawn Guo .name = DRIVER_NAME, 805e4243f13SShawn Guo .owner = THIS_MODULE, 806e4243f13SShawn Guo #ifdef CONFIG_PM 807e4243f13SShawn Guo .pm = &mxs_mmc_pm_ops, 808e4243f13SShawn Guo #endif 809a3e545e9SMarek Vasut .of_match_table = mxs_mmc_dt_ids, 810e4243f13SShawn Guo }, 811e4243f13SShawn Guo }; 812e4243f13SShawn Guo 813d1f81a64SAxel Lin module_platform_driver(mxs_mmc_driver); 814e4243f13SShawn Guo 815e4243f13SShawn Guo MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral"); 816e4243f13SShawn Guo MODULE_AUTHOR("Freescale Semiconductor"); 817e4243f13SShawn Guo MODULE_LICENSE("GPL"); 818