1e4243f13SShawn Guo /* 2e4243f13SShawn Guo * Portions copyright (C) 2003 Russell King, PXA MMCI Driver 3e4243f13SShawn Guo * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver 4e4243f13SShawn Guo * 5e4243f13SShawn Guo * Copyright 2008 Embedded Alley Solutions, Inc. 6e4243f13SShawn Guo * Copyright 2009-2011 Freescale Semiconductor, Inc. 7e4243f13SShawn Guo * 8e4243f13SShawn Guo * This program is free software; you can redistribute it and/or modify 9e4243f13SShawn Guo * it under the terms of the GNU General Public License as published by 10e4243f13SShawn Guo * the Free Software Foundation; either version 2 of the License, or 11e4243f13SShawn Guo * (at your option) any later version. 12e4243f13SShawn Guo * 13e4243f13SShawn Guo * This program is distributed in the hope that it will be useful, 14e4243f13SShawn Guo * but WITHOUT ANY WARRANTY; without even the implied warranty of 15e4243f13SShawn Guo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16e4243f13SShawn Guo * GNU General Public License for more details. 17e4243f13SShawn Guo * 18e4243f13SShawn Guo * You should have received a copy of the GNU General Public License along 19e4243f13SShawn Guo * with this program; if not, write to the Free Software Foundation, Inc., 20e4243f13SShawn Guo * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 21e4243f13SShawn Guo */ 22e4243f13SShawn Guo 23e4243f13SShawn Guo #include <linux/kernel.h> 24e4243f13SShawn Guo #include <linux/init.h> 25e4243f13SShawn Guo #include <linux/ioport.h> 266de4d817SShawn Guo #include <linux/of.h> 276de4d817SShawn Guo #include <linux/of_device.h> 286de4d817SShawn Guo #include <linux/of_gpio.h> 29e4243f13SShawn Guo #include <linux/platform_device.h> 30e4243f13SShawn Guo #include <linux/delay.h> 31e4243f13SShawn Guo #include <linux/interrupt.h> 32e4243f13SShawn Guo #include <linux/dma-mapping.h> 33e4243f13SShawn Guo #include <linux/dmaengine.h> 34e4243f13SShawn Guo #include <linux/highmem.h> 35e4243f13SShawn Guo #include <linux/clk.h> 36e4243f13SShawn Guo #include <linux/err.h> 37e4243f13SShawn Guo #include <linux/completion.h> 38e4243f13SShawn Guo #include <linux/mmc/host.h> 39e4243f13SShawn Guo #include <linux/mmc/mmc.h> 40e4243f13SShawn Guo #include <linux/mmc/sdio.h> 41e4243f13SShawn Guo #include <linux/gpio.h> 42e4243f13SShawn Guo #include <linux/regulator/consumer.h> 4388b47679SPaul Gortmaker #include <linux/module.h> 449c92cf24SShawn Guo #include <linux/pinctrl/consumer.h> 4570e60206SShawn Guo #include <linux/stmp_device.h> 468be3d3b2SMarek Vasut #include <linux/spi/mxs-spi.h> 47e4243f13SShawn Guo 48e4243f13SShawn Guo #define DRIVER_NAME "mxs-mmc" 49e4243f13SShawn Guo 50e4243f13SShawn Guo #define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \ 51e4243f13SShawn Guo BM_SSP_CTRL1_RESP_ERR_IRQ | \ 52e4243f13SShawn Guo BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \ 53e4243f13SShawn Guo BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \ 54e4243f13SShawn Guo BM_SSP_CTRL1_DATA_CRC_IRQ | \ 55e4243f13SShawn Guo BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \ 56e4243f13SShawn Guo BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \ 57e4243f13SShawn Guo BM_SSP_CTRL1_FIFO_OVERRUN_IRQ) 58e4243f13SShawn Guo 598be3d3b2SMarek Vasut /* card detect polling timeout */ 608be3d3b2SMarek Vasut #define MXS_MMC_DETECT_TIMEOUT (HZ/2) 61ef9b4d39SShawn Guo 62e4243f13SShawn Guo struct mxs_mmc_host { 63829c1bf4SMarek Vasut struct mxs_ssp ssp; 64829c1bf4SMarek Vasut 65e4243f13SShawn Guo struct mmc_host *mmc; 66e4243f13SShawn Guo struct mmc_request *mrq; 67e4243f13SShawn Guo struct mmc_command *cmd; 68e4243f13SShawn Guo struct mmc_data *data; 69e4243f13SShawn Guo 70e4243f13SShawn Guo unsigned char bus_width; 71e4243f13SShawn Guo spinlock_t lock; 72e4243f13SShawn Guo int sdio_irq_en; 7331b0ff5eSShawn Guo int wp_gpio; 74b6e76f10SMarek Vasut bool wp_inverted; 75e4243f13SShawn Guo }; 76e4243f13SShawn Guo 77e4243f13SShawn Guo static int mxs_mmc_get_ro(struct mmc_host *mmc) 78e4243f13SShawn Guo { 79e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 80b6e76f10SMarek Vasut int ret; 81e4243f13SShawn Guo 8231b0ff5eSShawn Guo if (!gpio_is_valid(host->wp_gpio)) 83e4243f13SShawn Guo return -EINVAL; 84e4243f13SShawn Guo 85b6e76f10SMarek Vasut ret = gpio_get_value(host->wp_gpio); 86b6e76f10SMarek Vasut 87b6e76f10SMarek Vasut if (host->wp_inverted) 88b6e76f10SMarek Vasut ret = !ret; 89b6e76f10SMarek Vasut 90b6e76f10SMarek Vasut return ret; 91e4243f13SShawn Guo } 92e4243f13SShawn Guo 93e4243f13SShawn Guo static int mxs_mmc_get_cd(struct mmc_host *mmc) 94e4243f13SShawn Guo { 95e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 96829c1bf4SMarek Vasut struct mxs_ssp *ssp = &host->ssp; 97e4243f13SShawn Guo 98829c1bf4SMarek Vasut return !(readl(ssp->base + HW_SSP_STATUS(ssp)) & 99e4243f13SShawn Guo BM_SSP_STATUS_CARD_DETECT); 100e4243f13SShawn Guo } 101e4243f13SShawn Guo 102e4243f13SShawn Guo static void mxs_mmc_reset(struct mxs_mmc_host *host) 103e4243f13SShawn Guo { 104829c1bf4SMarek Vasut struct mxs_ssp *ssp = &host->ssp; 105e4243f13SShawn Guo u32 ctrl0, ctrl1; 106e4243f13SShawn Guo 107829c1bf4SMarek Vasut stmp_reset_block(ssp->base); 108e4243f13SShawn Guo 109e4243f13SShawn Guo ctrl0 = BM_SSP_CTRL0_IGNORE_CRC; 110e4243f13SShawn Guo ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) | 111e4243f13SShawn Guo BF_SSP(0x7, CTRL1_WORD_LENGTH) | 112e4243f13SShawn Guo BM_SSP_CTRL1_DMA_ENABLE | 113e4243f13SShawn Guo BM_SSP_CTRL1_POLARITY | 114e4243f13SShawn Guo BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN | 115e4243f13SShawn Guo BM_SSP_CTRL1_DATA_CRC_IRQ_EN | 116e4243f13SShawn Guo BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN | 117e4243f13SShawn Guo BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN | 118e4243f13SShawn Guo BM_SSP_CTRL1_RESP_ERR_IRQ_EN; 119e4243f13SShawn Guo 120e4243f13SShawn Guo writel(BF_SSP(0xffff, TIMING_TIMEOUT) | 121e4243f13SShawn Guo BF_SSP(2, TIMING_CLOCK_DIVIDE) | 122e4243f13SShawn Guo BF_SSP(0, TIMING_CLOCK_RATE), 123829c1bf4SMarek Vasut ssp->base + HW_SSP_TIMING(ssp)); 124e4243f13SShawn Guo 125e4243f13SShawn Guo if (host->sdio_irq_en) { 126e4243f13SShawn Guo ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 127e4243f13SShawn Guo ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN; 128e4243f13SShawn Guo } 129e4243f13SShawn Guo 130829c1bf4SMarek Vasut writel(ctrl0, ssp->base + HW_SSP_CTRL0); 131829c1bf4SMarek Vasut writel(ctrl1, ssp->base + HW_SSP_CTRL1(ssp)); 132e4243f13SShawn Guo } 133e4243f13SShawn Guo 134e4243f13SShawn Guo static void mxs_mmc_start_cmd(struct mxs_mmc_host *host, 135e4243f13SShawn Guo struct mmc_command *cmd); 136e4243f13SShawn Guo 137e4243f13SShawn Guo static void mxs_mmc_request_done(struct mxs_mmc_host *host) 138e4243f13SShawn Guo { 139e4243f13SShawn Guo struct mmc_command *cmd = host->cmd; 140e4243f13SShawn Guo struct mmc_data *data = host->data; 141e4243f13SShawn Guo struct mmc_request *mrq = host->mrq; 142829c1bf4SMarek Vasut struct mxs_ssp *ssp = &host->ssp; 143e4243f13SShawn Guo 144e4243f13SShawn Guo if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) { 145e4243f13SShawn Guo if (mmc_resp_type(cmd) & MMC_RSP_136) { 146829c1bf4SMarek Vasut cmd->resp[3] = readl(ssp->base + HW_SSP_SDRESP0(ssp)); 147829c1bf4SMarek Vasut cmd->resp[2] = readl(ssp->base + HW_SSP_SDRESP1(ssp)); 148829c1bf4SMarek Vasut cmd->resp[1] = readl(ssp->base + HW_SSP_SDRESP2(ssp)); 149829c1bf4SMarek Vasut cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP3(ssp)); 150e4243f13SShawn Guo } else { 151829c1bf4SMarek Vasut cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP0(ssp)); 152e4243f13SShawn Guo } 153e4243f13SShawn Guo } 154e4243f13SShawn Guo 155e4243f13SShawn Guo if (data) { 156e4243f13SShawn Guo dma_unmap_sg(mmc_dev(host->mmc), data->sg, 15765defb9bSMarek Vasut data->sg_len, ssp->dma_dir); 158e4243f13SShawn Guo /* 159e4243f13SShawn Guo * If there was an error on any block, we mark all 160e4243f13SShawn Guo * data blocks as being in error. 161e4243f13SShawn Guo */ 162e4243f13SShawn Guo if (!data->error) 163e4243f13SShawn Guo data->bytes_xfered = data->blocks * data->blksz; 164e4243f13SShawn Guo else 165e4243f13SShawn Guo data->bytes_xfered = 0; 166e4243f13SShawn Guo 167e4243f13SShawn Guo host->data = NULL; 168e4243f13SShawn Guo if (mrq->stop) { 169e4243f13SShawn Guo mxs_mmc_start_cmd(host, mrq->stop); 170e4243f13SShawn Guo return; 171e4243f13SShawn Guo } 172e4243f13SShawn Guo } 173e4243f13SShawn Guo 174e4243f13SShawn Guo host->mrq = NULL; 175e4243f13SShawn Guo mmc_request_done(host->mmc, mrq); 176e4243f13SShawn Guo } 177e4243f13SShawn Guo 178e4243f13SShawn Guo static void mxs_mmc_dma_irq_callback(void *param) 179e4243f13SShawn Guo { 180e4243f13SShawn Guo struct mxs_mmc_host *host = param; 181e4243f13SShawn Guo 182e4243f13SShawn Guo mxs_mmc_request_done(host); 183e4243f13SShawn Guo } 184e4243f13SShawn Guo 185e4243f13SShawn Guo static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id) 186e4243f13SShawn Guo { 187e4243f13SShawn Guo struct mxs_mmc_host *host = dev_id; 188e4243f13SShawn Guo struct mmc_command *cmd = host->cmd; 189e4243f13SShawn Guo struct mmc_data *data = host->data; 190829c1bf4SMarek Vasut struct mxs_ssp *ssp = &host->ssp; 191e4243f13SShawn Guo u32 stat; 192e4243f13SShawn Guo 193e4243f13SShawn Guo spin_lock(&host->lock); 194e4243f13SShawn Guo 195829c1bf4SMarek Vasut stat = readl(ssp->base + HW_SSP_CTRL1(ssp)); 196e4243f13SShawn Guo writel(stat & MXS_MMC_IRQ_BITS, 197829c1bf4SMarek Vasut ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR); 198e4243f13SShawn Guo 1991af36b2aSLauri Hintsala spin_unlock(&host->lock); 2001af36b2aSLauri Hintsala 201e4243f13SShawn Guo if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN)) 202e4243f13SShawn Guo mmc_signal_sdio_irq(host->mmc); 203e4243f13SShawn Guo 204e4243f13SShawn Guo if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ) 205e4243f13SShawn Guo cmd->error = -ETIMEDOUT; 206e4243f13SShawn Guo else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ) 207e4243f13SShawn Guo cmd->error = -EIO; 208e4243f13SShawn Guo 209e4243f13SShawn Guo if (data) { 210e4243f13SShawn Guo if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | 211e4243f13SShawn Guo BM_SSP_CTRL1_RECV_TIMEOUT_IRQ)) 212e4243f13SShawn Guo data->error = -ETIMEDOUT; 213e4243f13SShawn Guo else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ) 214e4243f13SShawn Guo data->error = -EILSEQ; 215e4243f13SShawn Guo else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | 216e4243f13SShawn Guo BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)) 217e4243f13SShawn Guo data->error = -EIO; 218e4243f13SShawn Guo } 219e4243f13SShawn Guo 220e4243f13SShawn Guo return IRQ_HANDLED; 221e4243f13SShawn Guo } 222e4243f13SShawn Guo 223e4243f13SShawn Guo static struct dma_async_tx_descriptor *mxs_mmc_prep_dma( 224921de864SHuang Shijie struct mxs_mmc_host *host, unsigned long flags) 225e4243f13SShawn Guo { 22665defb9bSMarek Vasut struct mxs_ssp *ssp = &host->ssp; 227e4243f13SShawn Guo struct dma_async_tx_descriptor *desc; 228e4243f13SShawn Guo struct mmc_data *data = host->data; 229e4243f13SShawn Guo struct scatterlist * sgl; 230e4243f13SShawn Guo unsigned int sg_len; 231e4243f13SShawn Guo 232e4243f13SShawn Guo if (data) { 233e4243f13SShawn Guo /* data */ 234e4243f13SShawn Guo dma_map_sg(mmc_dev(host->mmc), data->sg, 23565defb9bSMarek Vasut data->sg_len, ssp->dma_dir); 236e4243f13SShawn Guo sgl = data->sg; 237e4243f13SShawn Guo sg_len = data->sg_len; 238e4243f13SShawn Guo } else { 239e4243f13SShawn Guo /* pio */ 24065defb9bSMarek Vasut sgl = (struct scatterlist *) ssp->ssp_pio_words; 241e4243f13SShawn Guo sg_len = SSP_PIO_NUM; 242e4243f13SShawn Guo } 243e4243f13SShawn Guo 24465defb9bSMarek Vasut desc = dmaengine_prep_slave_sg(ssp->dmach, 24565defb9bSMarek Vasut sgl, sg_len, ssp->slave_dirn, flags); 246e4243f13SShawn Guo if (desc) { 247e4243f13SShawn Guo desc->callback = mxs_mmc_dma_irq_callback; 248e4243f13SShawn Guo desc->callback_param = host; 249e4243f13SShawn Guo } else { 250e4243f13SShawn Guo if (data) 251e4243f13SShawn Guo dma_unmap_sg(mmc_dev(host->mmc), data->sg, 25265defb9bSMarek Vasut data->sg_len, ssp->dma_dir); 253e4243f13SShawn Guo } 254e4243f13SShawn Guo 255e4243f13SShawn Guo return desc; 256e4243f13SShawn Guo } 257e4243f13SShawn Guo 258e4243f13SShawn Guo static void mxs_mmc_bc(struct mxs_mmc_host *host) 259e4243f13SShawn Guo { 26065defb9bSMarek Vasut struct mxs_ssp *ssp = &host->ssp; 261e4243f13SShawn Guo struct mmc_command *cmd = host->cmd; 262e4243f13SShawn Guo struct dma_async_tx_descriptor *desc; 263e4243f13SShawn Guo u32 ctrl0, cmd0, cmd1; 264e4243f13SShawn Guo 265e4243f13SShawn Guo ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC; 266e4243f13SShawn Guo cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC; 267e4243f13SShawn Guo cmd1 = cmd->arg; 268e4243f13SShawn Guo 269e4243f13SShawn Guo if (host->sdio_irq_en) { 270e4243f13SShawn Guo ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 271e4243f13SShawn Guo cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 272e4243f13SShawn Guo } 273e4243f13SShawn Guo 27465defb9bSMarek Vasut ssp->ssp_pio_words[0] = ctrl0; 27565defb9bSMarek Vasut ssp->ssp_pio_words[1] = cmd0; 27665defb9bSMarek Vasut ssp->ssp_pio_words[2] = cmd1; 27765defb9bSMarek Vasut ssp->dma_dir = DMA_NONE; 27865defb9bSMarek Vasut ssp->slave_dirn = DMA_TRANS_NONE; 279921de864SHuang Shijie desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK); 280e4243f13SShawn Guo if (!desc) 281e4243f13SShawn Guo goto out; 282e4243f13SShawn Guo 283e4243f13SShawn Guo dmaengine_submit(desc); 28465defb9bSMarek Vasut dma_async_issue_pending(ssp->dmach); 285e4243f13SShawn Guo return; 286e4243f13SShawn Guo 287e4243f13SShawn Guo out: 288e4243f13SShawn Guo dev_warn(mmc_dev(host->mmc), 289e4243f13SShawn Guo "%s: failed to prep dma\n", __func__); 290e4243f13SShawn Guo } 291e4243f13SShawn Guo 292e4243f13SShawn Guo static void mxs_mmc_ac(struct mxs_mmc_host *host) 293e4243f13SShawn Guo { 29465defb9bSMarek Vasut struct mxs_ssp *ssp = &host->ssp; 295e4243f13SShawn Guo struct mmc_command *cmd = host->cmd; 296e4243f13SShawn Guo struct dma_async_tx_descriptor *desc; 297e4243f13SShawn Guo u32 ignore_crc, get_resp, long_resp; 298e4243f13SShawn Guo u32 ctrl0, cmd0, cmd1; 299e4243f13SShawn Guo 300e4243f13SShawn Guo ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ? 301e4243f13SShawn Guo 0 : BM_SSP_CTRL0_IGNORE_CRC; 302e4243f13SShawn Guo get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ? 303e4243f13SShawn Guo BM_SSP_CTRL0_GET_RESP : 0; 304e4243f13SShawn Guo long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ? 305e4243f13SShawn Guo BM_SSP_CTRL0_LONG_RESP : 0; 306e4243f13SShawn Guo 307e4243f13SShawn Guo ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp; 308e4243f13SShawn Guo cmd0 = BF_SSP(cmd->opcode, CMD0_CMD); 309e4243f13SShawn Guo cmd1 = cmd->arg; 310e4243f13SShawn Guo 311e4243f13SShawn Guo if (host->sdio_irq_en) { 312e4243f13SShawn Guo ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 313e4243f13SShawn Guo cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 314e4243f13SShawn Guo } 315e4243f13SShawn Guo 31665defb9bSMarek Vasut ssp->ssp_pio_words[0] = ctrl0; 31765defb9bSMarek Vasut ssp->ssp_pio_words[1] = cmd0; 31865defb9bSMarek Vasut ssp->ssp_pio_words[2] = cmd1; 31965defb9bSMarek Vasut ssp->dma_dir = DMA_NONE; 32065defb9bSMarek Vasut ssp->slave_dirn = DMA_TRANS_NONE; 321921de864SHuang Shijie desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK); 322e4243f13SShawn Guo if (!desc) 323e4243f13SShawn Guo goto out; 324e4243f13SShawn Guo 325e4243f13SShawn Guo dmaengine_submit(desc); 32665defb9bSMarek Vasut dma_async_issue_pending(ssp->dmach); 327e4243f13SShawn Guo return; 328e4243f13SShawn Guo 329e4243f13SShawn Guo out: 330e4243f13SShawn Guo dev_warn(mmc_dev(host->mmc), 331e4243f13SShawn Guo "%s: failed to prep dma\n", __func__); 332e4243f13SShawn Guo } 333e4243f13SShawn Guo 334e4243f13SShawn Guo static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns) 335e4243f13SShawn Guo { 336e4243f13SShawn Guo const unsigned int ssp_timeout_mul = 4096; 337e4243f13SShawn Guo /* 338e4243f13SShawn Guo * Calculate ticks in ms since ns are large numbers 339e4243f13SShawn Guo * and might overflow 340e4243f13SShawn Guo */ 341e4243f13SShawn Guo const unsigned int clock_per_ms = clock_rate / 1000; 342e4243f13SShawn Guo const unsigned int ms = ns / 1000; 343e4243f13SShawn Guo const unsigned int ticks = ms * clock_per_ms; 344e4243f13SShawn Guo const unsigned int ssp_ticks = ticks / ssp_timeout_mul; 345e4243f13SShawn Guo 346e4243f13SShawn Guo WARN_ON(ssp_ticks == 0); 347e4243f13SShawn Guo return ssp_ticks; 348e4243f13SShawn Guo } 349e4243f13SShawn Guo 350e4243f13SShawn Guo static void mxs_mmc_adtc(struct mxs_mmc_host *host) 351e4243f13SShawn Guo { 352e4243f13SShawn Guo struct mmc_command *cmd = host->cmd; 353e4243f13SShawn Guo struct mmc_data *data = cmd->data; 354e4243f13SShawn Guo struct dma_async_tx_descriptor *desc; 355e4243f13SShawn Guo struct scatterlist *sgl = data->sg, *sg; 356e4243f13SShawn Guo unsigned int sg_len = data->sg_len; 357e4243f13SShawn Guo int i; 358e4243f13SShawn Guo 359e4243f13SShawn Guo unsigned short dma_data_dir, timeout; 36005f5799cSVinod Koul enum dma_transfer_direction slave_dirn; 361e4243f13SShawn Guo unsigned int data_size = 0, log2_blksz; 362e4243f13SShawn Guo unsigned int blocks = data->blocks; 363e4243f13SShawn Guo 364829c1bf4SMarek Vasut struct mxs_ssp *ssp = &host->ssp; 365829c1bf4SMarek Vasut 366e4243f13SShawn Guo u32 ignore_crc, get_resp, long_resp, read; 367e4243f13SShawn Guo u32 ctrl0, cmd0, cmd1, val; 368e4243f13SShawn Guo 369e4243f13SShawn Guo ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ? 370e4243f13SShawn Guo 0 : BM_SSP_CTRL0_IGNORE_CRC; 371e4243f13SShawn Guo get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ? 372e4243f13SShawn Guo BM_SSP_CTRL0_GET_RESP : 0; 373e4243f13SShawn Guo long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ? 374e4243f13SShawn Guo BM_SSP_CTRL0_LONG_RESP : 0; 375e4243f13SShawn Guo 376e4243f13SShawn Guo if (data->flags & MMC_DATA_WRITE) { 377e4243f13SShawn Guo dma_data_dir = DMA_TO_DEVICE; 37805f5799cSVinod Koul slave_dirn = DMA_MEM_TO_DEV; 379e4243f13SShawn Guo read = 0; 380e4243f13SShawn Guo } else { 381e4243f13SShawn Guo dma_data_dir = DMA_FROM_DEVICE; 38205f5799cSVinod Koul slave_dirn = DMA_DEV_TO_MEM; 383e4243f13SShawn Guo read = BM_SSP_CTRL0_READ; 384e4243f13SShawn Guo } 385e4243f13SShawn Guo 386e4243f13SShawn Guo ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) | 387e4243f13SShawn Guo ignore_crc | get_resp | long_resp | 388e4243f13SShawn Guo BM_SSP_CTRL0_DATA_XFER | read | 389e4243f13SShawn Guo BM_SSP_CTRL0_WAIT_FOR_IRQ | 390e4243f13SShawn Guo BM_SSP_CTRL0_ENABLE; 391e4243f13SShawn Guo 392e4243f13SShawn Guo cmd0 = BF_SSP(cmd->opcode, CMD0_CMD); 393e4243f13SShawn Guo 394e4243f13SShawn Guo /* get logarithm to base 2 of block size for setting register */ 395e4243f13SShawn Guo log2_blksz = ilog2(data->blksz); 396e4243f13SShawn Guo 397e4243f13SShawn Guo /* 398e4243f13SShawn Guo * take special care of the case that data size from data->sg 399e4243f13SShawn Guo * is not equal to blocks x blksz 400e4243f13SShawn Guo */ 401e4243f13SShawn Guo for_each_sg(sgl, sg, sg_len, i) 402e4243f13SShawn Guo data_size += sg->length; 403e4243f13SShawn Guo 404e4243f13SShawn Guo if (data_size != data->blocks * data->blksz) 405e4243f13SShawn Guo blocks = 1; 406e4243f13SShawn Guo 407e4243f13SShawn Guo /* xfer count, block size and count need to be set differently */ 408829c1bf4SMarek Vasut if (ssp_is_old(ssp)) { 409e4243f13SShawn Guo ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT); 410e4243f13SShawn Guo cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) | 411e4243f13SShawn Guo BF_SSP(blocks - 1, CMD0_BLOCK_COUNT); 412e4243f13SShawn Guo } else { 413829c1bf4SMarek Vasut writel(data_size, ssp->base + HW_SSP_XFER_SIZE); 414e4243f13SShawn Guo writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) | 415e4243f13SShawn Guo BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT), 416829c1bf4SMarek Vasut ssp->base + HW_SSP_BLOCK_SIZE); 417e4243f13SShawn Guo } 418e4243f13SShawn Guo 419e4243f13SShawn Guo if ((cmd->opcode == MMC_STOP_TRANSMISSION) || 420e4243f13SShawn Guo (cmd->opcode == SD_IO_RW_EXTENDED)) 421e4243f13SShawn Guo cmd0 |= BM_SSP_CMD0_APPEND_8CYC; 422e4243f13SShawn Guo 423e4243f13SShawn Guo cmd1 = cmd->arg; 424e4243f13SShawn Guo 425e4243f13SShawn Guo if (host->sdio_irq_en) { 426e4243f13SShawn Guo ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 427e4243f13SShawn Guo cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 428e4243f13SShawn Guo } 429e4243f13SShawn Guo 430e4243f13SShawn Guo /* set the timeout count */ 431829c1bf4SMarek Vasut timeout = mxs_ns_to_ssp_ticks(ssp->clk_rate, data->timeout_ns); 432829c1bf4SMarek Vasut val = readl(ssp->base + HW_SSP_TIMING(ssp)); 433e4243f13SShawn Guo val &= ~(BM_SSP_TIMING_TIMEOUT); 434e4243f13SShawn Guo val |= BF_SSP(timeout, TIMING_TIMEOUT); 435829c1bf4SMarek Vasut writel(val, ssp->base + HW_SSP_TIMING(ssp)); 436e4243f13SShawn Guo 437e4243f13SShawn Guo /* pio */ 43865defb9bSMarek Vasut ssp->ssp_pio_words[0] = ctrl0; 43965defb9bSMarek Vasut ssp->ssp_pio_words[1] = cmd0; 44065defb9bSMarek Vasut ssp->ssp_pio_words[2] = cmd1; 44165defb9bSMarek Vasut ssp->dma_dir = DMA_NONE; 44265defb9bSMarek Vasut ssp->slave_dirn = DMA_TRANS_NONE; 443e4243f13SShawn Guo desc = mxs_mmc_prep_dma(host, 0); 444e4243f13SShawn Guo if (!desc) 445e4243f13SShawn Guo goto out; 446e4243f13SShawn Guo 447e4243f13SShawn Guo /* append data sg */ 448e4243f13SShawn Guo WARN_ON(host->data != NULL); 449e4243f13SShawn Guo host->data = data; 45065defb9bSMarek Vasut ssp->dma_dir = dma_data_dir; 45165defb9bSMarek Vasut ssp->slave_dirn = slave_dirn; 452921de864SHuang Shijie desc = mxs_mmc_prep_dma(host, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 453e4243f13SShawn Guo if (!desc) 454e4243f13SShawn Guo goto out; 455e4243f13SShawn Guo 456e4243f13SShawn Guo dmaengine_submit(desc); 45765defb9bSMarek Vasut dma_async_issue_pending(ssp->dmach); 458e4243f13SShawn Guo return; 459e4243f13SShawn Guo out: 460e4243f13SShawn Guo dev_warn(mmc_dev(host->mmc), 461e4243f13SShawn Guo "%s: failed to prep dma\n", __func__); 462e4243f13SShawn Guo } 463e4243f13SShawn Guo 464e4243f13SShawn Guo static void mxs_mmc_start_cmd(struct mxs_mmc_host *host, 465e4243f13SShawn Guo struct mmc_command *cmd) 466e4243f13SShawn Guo { 467e4243f13SShawn Guo host->cmd = cmd; 468e4243f13SShawn Guo 469e4243f13SShawn Guo switch (mmc_cmd_type(cmd)) { 470e4243f13SShawn Guo case MMC_CMD_BC: 471e4243f13SShawn Guo mxs_mmc_bc(host); 472e4243f13SShawn Guo break; 473e4243f13SShawn Guo case MMC_CMD_BCR: 474e4243f13SShawn Guo mxs_mmc_ac(host); 475e4243f13SShawn Guo break; 476e4243f13SShawn Guo case MMC_CMD_AC: 477e4243f13SShawn Guo mxs_mmc_ac(host); 478e4243f13SShawn Guo break; 479e4243f13SShawn Guo case MMC_CMD_ADTC: 480e4243f13SShawn Guo mxs_mmc_adtc(host); 481e4243f13SShawn Guo break; 482e4243f13SShawn Guo default: 483e4243f13SShawn Guo dev_warn(mmc_dev(host->mmc), 484e4243f13SShawn Guo "%s: unknown MMC command\n", __func__); 485e4243f13SShawn Guo break; 486e4243f13SShawn Guo } 487e4243f13SShawn Guo } 488e4243f13SShawn Guo 489e4243f13SShawn Guo static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 490e4243f13SShawn Guo { 491e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 492e4243f13SShawn Guo 493e4243f13SShawn Guo WARN_ON(host->mrq != NULL); 494e4243f13SShawn Guo host->mrq = mrq; 495e4243f13SShawn Guo mxs_mmc_start_cmd(host, mrq->cmd); 496e4243f13SShawn Guo } 497e4243f13SShawn Guo 498e4243f13SShawn Guo static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 499e4243f13SShawn Guo { 500e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 501e4243f13SShawn Guo 502e4243f13SShawn Guo if (ios->bus_width == MMC_BUS_WIDTH_8) 503e4243f13SShawn Guo host->bus_width = 2; 504e4243f13SShawn Guo else if (ios->bus_width == MMC_BUS_WIDTH_4) 505e4243f13SShawn Guo host->bus_width = 1; 506e4243f13SShawn Guo else 507e4243f13SShawn Guo host->bus_width = 0; 508e4243f13SShawn Guo 509e4243f13SShawn Guo if (ios->clock) 51013082398SMarek Vasut mxs_ssp_set_clk_rate(&host->ssp, ios->clock); 511e4243f13SShawn Guo } 512e4243f13SShawn Guo 513e4243f13SShawn Guo static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 514e4243f13SShawn Guo { 515e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 516829c1bf4SMarek Vasut struct mxs_ssp *ssp = &host->ssp; 517e4243f13SShawn Guo unsigned long flags; 518e4243f13SShawn Guo 519e4243f13SShawn Guo spin_lock_irqsave(&host->lock, flags); 520e4243f13SShawn Guo 521e4243f13SShawn Guo host->sdio_irq_en = enable; 522e4243f13SShawn Guo 523e4243f13SShawn Guo if (enable) { 524e4243f13SShawn Guo writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, 525829c1bf4SMarek Vasut ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); 526e4243f13SShawn Guo writel(BM_SSP_CTRL1_SDIO_IRQ_EN, 5274c5bb2e4SMarek Vasut ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_SET); 528e4243f13SShawn Guo } else { 529e4243f13SShawn Guo writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, 530829c1bf4SMarek Vasut ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); 531e4243f13SShawn Guo writel(BM_SSP_CTRL1_SDIO_IRQ_EN, 532829c1bf4SMarek Vasut ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR); 533e4243f13SShawn Guo } 534e4243f13SShawn Guo 535e4243f13SShawn Guo spin_unlock_irqrestore(&host->lock, flags); 536fc108d24SLauri Hintsala 537ac48f6cbSMark Brown if (enable && readl(ssp->base + HW_SSP_STATUS(ssp)) & 538fc108d24SLauri Hintsala BM_SSP_STATUS_SDIO_IRQ) 539fc108d24SLauri Hintsala mmc_signal_sdio_irq(host->mmc); 540fc108d24SLauri Hintsala 541e4243f13SShawn Guo } 542e4243f13SShawn Guo 543e4243f13SShawn Guo static const struct mmc_host_ops mxs_mmc_ops = { 544e4243f13SShawn Guo .request = mxs_mmc_request, 545e4243f13SShawn Guo .get_ro = mxs_mmc_get_ro, 546e4243f13SShawn Guo .get_cd = mxs_mmc_get_cd, 547e4243f13SShawn Guo .set_ios = mxs_mmc_set_ios, 548e4243f13SShawn Guo .enable_sdio_irq = mxs_mmc_enable_sdio_irq, 549e4243f13SShawn Guo }; 550e4243f13SShawn Guo 551e4243f13SShawn Guo static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param) 552e4243f13SShawn Guo { 553e4243f13SShawn Guo struct mxs_mmc_host *host = param; 55465defb9bSMarek Vasut struct mxs_ssp *ssp = &host->ssp; 555e4243f13SShawn Guo 556e4243f13SShawn Guo if (!mxs_dma_is_apbh(chan)) 557e4243f13SShawn Guo return false; 558e4243f13SShawn Guo 55965defb9bSMarek Vasut if (chan->chan_id != ssp->dma_channel) 560e4243f13SShawn Guo return false; 561e4243f13SShawn Guo 56265defb9bSMarek Vasut chan->private = &ssp->dma_data; 563e4243f13SShawn Guo 564e4243f13SShawn Guo return true; 565e4243f13SShawn Guo } 566e4243f13SShawn Guo 567600a991fSMarek Vasut static struct platform_device_id mxs_ssp_ids[] = { 568ef9b4d39SShawn Guo { 569ef9b4d39SShawn Guo .name = "imx23-mmc", 570600a991fSMarek Vasut .driver_data = IMX23_SSP, 571ef9b4d39SShawn Guo }, { 572ef9b4d39SShawn Guo .name = "imx28-mmc", 573600a991fSMarek Vasut .driver_data = IMX28_SSP, 574ef9b4d39SShawn Guo }, { 575ef9b4d39SShawn Guo /* sentinel */ 576ef9b4d39SShawn Guo } 577ef9b4d39SShawn Guo }; 578600a991fSMarek Vasut MODULE_DEVICE_TABLE(platform, mxs_ssp_ids); 579ef9b4d39SShawn Guo 5806de4d817SShawn Guo static const struct of_device_id mxs_mmc_dt_ids[] = { 581600a991fSMarek Vasut { .compatible = "fsl,imx23-mmc", .data = (void *) IMX23_SSP, }, 582600a991fSMarek Vasut { .compatible = "fsl,imx28-mmc", .data = (void *) IMX28_SSP, }, 5836de4d817SShawn Guo { /* sentinel */ } 5846de4d817SShawn Guo }; 5856de4d817SShawn Guo MODULE_DEVICE_TABLE(of, mxs_mmc_dt_ids); 5866de4d817SShawn Guo 587e4243f13SShawn Guo static int mxs_mmc_probe(struct platform_device *pdev) 588e4243f13SShawn Guo { 5896de4d817SShawn Guo const struct of_device_id *of_id = 5906de4d817SShawn Guo of_match_device(mxs_mmc_dt_ids, &pdev->dev); 5916de4d817SShawn Guo struct device_node *np = pdev->dev.of_node; 592e4243f13SShawn Guo struct mxs_mmc_host *host; 593e4243f13SShawn Guo struct mmc_host *mmc; 594df06bfc7SShawn Guo struct resource *iores, *dmares; 5959c92cf24SShawn Guo struct pinctrl *pinctrl; 596e4243f13SShawn Guo int ret = 0, irq_err, irq_dma; 597e4243f13SShawn Guo dma_cap_mask_t mask; 5984dc5a79fSShawn Guo struct regulator *reg_vmmc; 599b6e76f10SMarek Vasut enum of_gpio_flags flags; 600829c1bf4SMarek Vasut struct mxs_ssp *ssp; 601d6ed91afSFabio Estevam u32 bus_width = 0; 602e4243f13SShawn Guo 603e4243f13SShawn Guo iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 604e4243f13SShawn Guo dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0); 605e4243f13SShawn Guo irq_err = platform_get_irq(pdev, 0); 606e4243f13SShawn Guo irq_dma = platform_get_irq(pdev, 1); 6076de4d817SShawn Guo if (!iores || irq_err < 0 || irq_dma < 0) 608e4243f13SShawn Guo return -EINVAL; 609e4243f13SShawn Guo 610e4243f13SShawn Guo mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev); 611df06bfc7SShawn Guo if (!mmc) 612df06bfc7SShawn Guo return -ENOMEM; 613e4243f13SShawn Guo 614e4243f13SShawn Guo host = mmc_priv(mmc); 615829c1bf4SMarek Vasut ssp = &host->ssp; 616829c1bf4SMarek Vasut ssp->dev = &pdev->dev; 617a3e2cd7fSThierry Reding ssp->base = devm_ioremap_resource(&pdev->dev, iores); 618a3e2cd7fSThierry Reding if (IS_ERR(ssp->base)) { 619a3e2cd7fSThierry Reding ret = PTR_ERR(ssp->base); 620e4243f13SShawn Guo goto out_mmc_free; 621e4243f13SShawn Guo } 622e4243f13SShawn Guo 6236de4d817SShawn Guo if (np) { 624829c1bf4SMarek Vasut ssp->devid = (enum mxs_ssp_id) of_id->data; 6256de4d817SShawn Guo /* 6266de4d817SShawn Guo * TODO: This is a temporary solution and should be changed 6276de4d817SShawn Guo * to use generic DMA binding later when the helpers get in. 6286de4d817SShawn Guo */ 6296de4d817SShawn Guo ret = of_property_read_u32(np, "fsl,ssp-dma-channel", 63065defb9bSMarek Vasut &ssp->dma_channel); 6316de4d817SShawn Guo if (ret) { 6326de4d817SShawn Guo dev_err(mmc_dev(host->mmc), 6336de4d817SShawn Guo "failed to get dma channel\n"); 6346de4d817SShawn Guo goto out_mmc_free; 6356de4d817SShawn Guo } 6366de4d817SShawn Guo } else { 637829c1bf4SMarek Vasut ssp->devid = pdev->id_entry->driver_data; 63865defb9bSMarek Vasut ssp->dma_channel = dmares->start; 6396de4d817SShawn Guo } 6406de4d817SShawn Guo 6416de4d817SShawn Guo host->mmc = mmc; 642e4243f13SShawn Guo host->sdio_irq_en = 0; 643e4243f13SShawn Guo 6444dc5a79fSShawn Guo reg_vmmc = devm_regulator_get(&pdev->dev, "vmmc"); 6454dc5a79fSShawn Guo if (!IS_ERR(reg_vmmc)) { 6464dc5a79fSShawn Guo ret = regulator_enable(reg_vmmc); 6474dc5a79fSShawn Guo if (ret) { 6484dc5a79fSShawn Guo dev_err(&pdev->dev, 6494dc5a79fSShawn Guo "Failed to enable vmmc regulator: %d\n", ret); 6504dc5a79fSShawn Guo goto out_mmc_free; 6514dc5a79fSShawn Guo } 6524dc5a79fSShawn Guo } 6534dc5a79fSShawn Guo 6549c92cf24SShawn Guo pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 6559c92cf24SShawn Guo if (IS_ERR(pinctrl)) { 6569c92cf24SShawn Guo ret = PTR_ERR(pinctrl); 6576de4d817SShawn Guo goto out_mmc_free; 6589c92cf24SShawn Guo } 6599c92cf24SShawn Guo 660829c1bf4SMarek Vasut ssp->clk = clk_get(&pdev->dev, NULL); 661829c1bf4SMarek Vasut if (IS_ERR(ssp->clk)) { 662829c1bf4SMarek Vasut ret = PTR_ERR(ssp->clk); 663df06bfc7SShawn Guo goto out_mmc_free; 664e4243f13SShawn Guo } 665829c1bf4SMarek Vasut clk_prepare_enable(ssp->clk); 666e4243f13SShawn Guo 667e4243f13SShawn Guo mxs_mmc_reset(host); 668e4243f13SShawn Guo 669e4243f13SShawn Guo dma_cap_zero(mask); 670e4243f13SShawn Guo dma_cap_set(DMA_SLAVE, mask); 67165defb9bSMarek Vasut ssp->dma_data.chan_irq = irq_dma; 67265defb9bSMarek Vasut ssp->dmach = dma_request_channel(mask, mxs_mmc_dma_filter, host); 67365defb9bSMarek Vasut if (!ssp->dmach) { 674e4243f13SShawn Guo dev_err(mmc_dev(host->mmc), 675e4243f13SShawn Guo "%s: failed to request dma\n", __func__); 676e4243f13SShawn Guo goto out_clk_put; 677e4243f13SShawn Guo } 678e4243f13SShawn Guo 679e4243f13SShawn Guo /* set mmc core parameters */ 680e4243f13SShawn Guo mmc->ops = &mxs_mmc_ops; 681e4243f13SShawn Guo mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 682e4243f13SShawn Guo MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL; 683e4243f13SShawn Guo 6846de4d817SShawn Guo of_property_read_u32(np, "bus-width", &bus_width); 6856de4d817SShawn Guo if (bus_width == 4) 6866de4d817SShawn Guo mmc->caps |= MMC_CAP_4_BIT_DATA; 6876de4d817SShawn Guo else if (bus_width == 8) 6886de4d817SShawn Guo mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA; 689d6ed91afSFabio Estevam host->wp_gpio = of_get_named_gpio_flags(np, "wp-gpios", 0, &flags); 690d6ed91afSFabio Estevam 691b6e76f10SMarek Vasut if (flags & OF_GPIO_ACTIVE_LOW) 692b6e76f10SMarek Vasut host->wp_inverted = 1; 693e4243f13SShawn Guo 694e4243f13SShawn Guo mmc->f_min = 400000; 695e4243f13SShawn Guo mmc->f_max = 288000000; 696e4243f13SShawn Guo mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 697e4243f13SShawn Guo 698e4243f13SShawn Guo mmc->max_segs = 52; 699e4243f13SShawn Guo mmc->max_blk_size = 1 << 0xf; 700829c1bf4SMarek Vasut mmc->max_blk_count = (ssp_is_old(ssp)) ? 0xff : 0xffffff; 701829c1bf4SMarek Vasut mmc->max_req_size = (ssp_is_old(ssp)) ? 0xffff : 0xffffffff; 70265defb9bSMarek Vasut mmc->max_seg_size = dma_get_max_seg_size(ssp->dmach->device->dev); 703e4243f13SShawn Guo 704e4243f13SShawn Guo platform_set_drvdata(pdev, mmc); 705e4243f13SShawn Guo 706df06bfc7SShawn Guo ret = devm_request_irq(&pdev->dev, irq_err, mxs_mmc_irq_handler, 0, 707df06bfc7SShawn Guo DRIVER_NAME, host); 708e4243f13SShawn Guo if (ret) 709e4243f13SShawn Guo goto out_free_dma; 710e4243f13SShawn Guo 711e4243f13SShawn Guo spin_lock_init(&host->lock); 712e4243f13SShawn Guo 713e4243f13SShawn Guo ret = mmc_add_host(mmc); 714e4243f13SShawn Guo if (ret) 715df06bfc7SShawn Guo goto out_free_dma; 716e4243f13SShawn Guo 717e4243f13SShawn Guo dev_info(mmc_dev(host->mmc), "initialized\n"); 718e4243f13SShawn Guo 719e4243f13SShawn Guo return 0; 720e4243f13SShawn Guo 721e4243f13SShawn Guo out_free_dma: 72265defb9bSMarek Vasut if (ssp->dmach) 72365defb9bSMarek Vasut dma_release_channel(ssp->dmach); 724e4243f13SShawn Guo out_clk_put: 725829c1bf4SMarek Vasut clk_disable_unprepare(ssp->clk); 726829c1bf4SMarek Vasut clk_put(ssp->clk); 727e4243f13SShawn Guo out_mmc_free: 728e4243f13SShawn Guo mmc_free_host(mmc); 729e4243f13SShawn Guo return ret; 730e4243f13SShawn Guo } 731e4243f13SShawn Guo 732e4243f13SShawn Guo static int mxs_mmc_remove(struct platform_device *pdev) 733e4243f13SShawn Guo { 734e4243f13SShawn Guo struct mmc_host *mmc = platform_get_drvdata(pdev); 735e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 736829c1bf4SMarek Vasut struct mxs_ssp *ssp = &host->ssp; 737e4243f13SShawn Guo 738e4243f13SShawn Guo mmc_remove_host(mmc); 739e4243f13SShawn Guo 740e4243f13SShawn Guo platform_set_drvdata(pdev, NULL); 741e4243f13SShawn Guo 74265defb9bSMarek Vasut if (ssp->dmach) 74365defb9bSMarek Vasut dma_release_channel(ssp->dmach); 744e4243f13SShawn Guo 745829c1bf4SMarek Vasut clk_disable_unprepare(ssp->clk); 746829c1bf4SMarek Vasut clk_put(ssp->clk); 747e4243f13SShawn Guo 748e4243f13SShawn Guo mmc_free_host(mmc); 749e4243f13SShawn Guo 750e4243f13SShawn Guo return 0; 751e4243f13SShawn Guo } 752e4243f13SShawn Guo 753e4243f13SShawn Guo #ifdef CONFIG_PM 754e4243f13SShawn Guo static int mxs_mmc_suspend(struct device *dev) 755e4243f13SShawn Guo { 756e4243f13SShawn Guo struct mmc_host *mmc = dev_get_drvdata(dev); 757e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 758829c1bf4SMarek Vasut struct mxs_ssp *ssp = &host->ssp; 759e4243f13SShawn Guo int ret = 0; 760e4243f13SShawn Guo 761e4243f13SShawn Guo ret = mmc_suspend_host(mmc); 762e4243f13SShawn Guo 763829c1bf4SMarek Vasut clk_disable_unprepare(ssp->clk); 764e4243f13SShawn Guo 765e4243f13SShawn Guo return ret; 766e4243f13SShawn Guo } 767e4243f13SShawn Guo 768e4243f13SShawn Guo static int mxs_mmc_resume(struct device *dev) 769e4243f13SShawn Guo { 770e4243f13SShawn Guo struct mmc_host *mmc = dev_get_drvdata(dev); 771e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 772829c1bf4SMarek Vasut struct mxs_ssp *ssp = &host->ssp; 773e4243f13SShawn Guo int ret = 0; 774e4243f13SShawn Guo 775829c1bf4SMarek Vasut clk_prepare_enable(ssp->clk); 776e4243f13SShawn Guo 777e4243f13SShawn Guo ret = mmc_resume_host(mmc); 778e4243f13SShawn Guo 779e4243f13SShawn Guo return ret; 780e4243f13SShawn Guo } 781e4243f13SShawn Guo 782e4243f13SShawn Guo static const struct dev_pm_ops mxs_mmc_pm_ops = { 783e4243f13SShawn Guo .suspend = mxs_mmc_suspend, 784e4243f13SShawn Guo .resume = mxs_mmc_resume, 785e4243f13SShawn Guo }; 786e4243f13SShawn Guo #endif 787e4243f13SShawn Guo 788e4243f13SShawn Guo static struct platform_driver mxs_mmc_driver = { 789e4243f13SShawn Guo .probe = mxs_mmc_probe, 790e4243f13SShawn Guo .remove = mxs_mmc_remove, 791600a991fSMarek Vasut .id_table = mxs_ssp_ids, 792e4243f13SShawn Guo .driver = { 793e4243f13SShawn Guo .name = DRIVER_NAME, 794e4243f13SShawn Guo .owner = THIS_MODULE, 795e4243f13SShawn Guo #ifdef CONFIG_PM 796e4243f13SShawn Guo .pm = &mxs_mmc_pm_ops, 797e4243f13SShawn Guo #endif 798a3e545e9SMarek Vasut .of_match_table = mxs_mmc_dt_ids, 799e4243f13SShawn Guo }, 800e4243f13SShawn Guo }; 801e4243f13SShawn Guo 802d1f81a64SAxel Lin module_platform_driver(mxs_mmc_driver); 803e4243f13SShawn Guo 804e4243f13SShawn Guo MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral"); 805e4243f13SShawn Guo MODULE_AUTHOR("Freescale Semiconductor"); 806e4243f13SShawn Guo MODULE_LICENSE("GPL"); 807