1e4243f13SShawn Guo /* 2e4243f13SShawn Guo * Portions copyright (C) 2003 Russell King, PXA MMCI Driver 3e4243f13SShawn Guo * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver 4e4243f13SShawn Guo * 5e4243f13SShawn Guo * Copyright 2008 Embedded Alley Solutions, Inc. 6e4243f13SShawn Guo * Copyright 2009-2011 Freescale Semiconductor, Inc. 7e4243f13SShawn Guo * 8e4243f13SShawn Guo * This program is free software; you can redistribute it and/or modify 9e4243f13SShawn Guo * it under the terms of the GNU General Public License as published by 10e4243f13SShawn Guo * the Free Software Foundation; either version 2 of the License, or 11e4243f13SShawn Guo * (at your option) any later version. 12e4243f13SShawn Guo * 13e4243f13SShawn Guo * This program is distributed in the hope that it will be useful, 14e4243f13SShawn Guo * but WITHOUT ANY WARRANTY; without even the implied warranty of 15e4243f13SShawn Guo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16e4243f13SShawn Guo * GNU General Public License for more details. 17e4243f13SShawn Guo * 18e4243f13SShawn Guo * You should have received a copy of the GNU General Public License along 19e4243f13SShawn Guo * with this program; if not, write to the Free Software Foundation, Inc., 20e4243f13SShawn Guo * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 21e4243f13SShawn Guo */ 22e4243f13SShawn Guo 23e4243f13SShawn Guo #include <linux/kernel.h> 24e4243f13SShawn Guo #include <linux/init.h> 25e4243f13SShawn Guo #include <linux/ioport.h> 26e4243f13SShawn Guo #include <linux/platform_device.h> 27e4243f13SShawn Guo #include <linux/delay.h> 28e4243f13SShawn Guo #include <linux/interrupt.h> 29e4243f13SShawn Guo #include <linux/dma-mapping.h> 30e4243f13SShawn Guo #include <linux/dmaengine.h> 31e4243f13SShawn Guo #include <linux/highmem.h> 32e4243f13SShawn Guo #include <linux/clk.h> 33e4243f13SShawn Guo #include <linux/err.h> 34e4243f13SShawn Guo #include <linux/completion.h> 35e4243f13SShawn Guo #include <linux/mmc/host.h> 36e4243f13SShawn Guo #include <linux/mmc/mmc.h> 37e4243f13SShawn Guo #include <linux/mmc/sdio.h> 38e4243f13SShawn Guo #include <linux/gpio.h> 39e4243f13SShawn Guo #include <linux/regulator/consumer.h> 4088b47679SPaul Gortmaker #include <linux/module.h> 4139468604SHuang Shijie #include <linux/fsl/mxs-dma.h> 429c92cf24SShawn Guo #include <linux/pinctrl/consumer.h> 43e4243f13SShawn Guo 44e4243f13SShawn Guo #include <mach/mxs.h> 45e4243f13SShawn Guo #include <mach/common.h> 46e4243f13SShawn Guo #include <mach/mmc.h> 47e4243f13SShawn Guo 48e4243f13SShawn Guo #define DRIVER_NAME "mxs-mmc" 49e4243f13SShawn Guo 50e4243f13SShawn Guo /* card detect polling timeout */ 51e4243f13SShawn Guo #define MXS_MMC_DETECT_TIMEOUT (HZ/2) 52e4243f13SShawn Guo 53e4243f13SShawn Guo #define SSP_VERSION_LATEST 4 54e4243f13SShawn Guo #define ssp_is_old() (host->version < SSP_VERSION_LATEST) 55e4243f13SShawn Guo 56e4243f13SShawn Guo /* SSP registers */ 57e4243f13SShawn Guo #define HW_SSP_CTRL0 0x000 58e4243f13SShawn Guo #define BM_SSP_CTRL0_RUN (1 << 29) 59e4243f13SShawn Guo #define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28) 60e4243f13SShawn Guo #define BM_SSP_CTRL0_IGNORE_CRC (1 << 26) 61e4243f13SShawn Guo #define BM_SSP_CTRL0_READ (1 << 25) 62e4243f13SShawn Guo #define BM_SSP_CTRL0_DATA_XFER (1 << 24) 63e4243f13SShawn Guo #define BP_SSP_CTRL0_BUS_WIDTH (22) 64e4243f13SShawn Guo #define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22) 65e4243f13SShawn Guo #define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21) 66e4243f13SShawn Guo #define BM_SSP_CTRL0_LONG_RESP (1 << 19) 67e4243f13SShawn Guo #define BM_SSP_CTRL0_GET_RESP (1 << 17) 68e4243f13SShawn Guo #define BM_SSP_CTRL0_ENABLE (1 << 16) 69e4243f13SShawn Guo #define BP_SSP_CTRL0_XFER_COUNT (0) 70e4243f13SShawn Guo #define BM_SSP_CTRL0_XFER_COUNT (0xffff) 71e4243f13SShawn Guo #define HW_SSP_CMD0 0x010 72e4243f13SShawn Guo #define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25) 73e4243f13SShawn Guo #define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22) 74e4243f13SShawn Guo #define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21) 75e4243f13SShawn Guo #define BM_SSP_CMD0_APPEND_8CYC (1 << 20) 76e4243f13SShawn Guo #define BP_SSP_CMD0_BLOCK_SIZE (16) 77e4243f13SShawn Guo #define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16) 78e4243f13SShawn Guo #define BP_SSP_CMD0_BLOCK_COUNT (8) 79e4243f13SShawn Guo #define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8) 80e4243f13SShawn Guo #define BP_SSP_CMD0_CMD (0) 81e4243f13SShawn Guo #define BM_SSP_CMD0_CMD (0xff) 82e4243f13SShawn Guo #define HW_SSP_CMD1 0x020 83e4243f13SShawn Guo #define HW_SSP_XFER_SIZE 0x030 84e4243f13SShawn Guo #define HW_SSP_BLOCK_SIZE 0x040 85e4243f13SShawn Guo #define BP_SSP_BLOCK_SIZE_BLOCK_COUNT (4) 86e4243f13SShawn Guo #define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4) 87e4243f13SShawn Guo #define BP_SSP_BLOCK_SIZE_BLOCK_SIZE (0) 88e4243f13SShawn Guo #define BM_SSP_BLOCK_SIZE_BLOCK_SIZE (0xf) 89e4243f13SShawn Guo #define HW_SSP_TIMING (ssp_is_old() ? 0x050 : 0x070) 90e4243f13SShawn Guo #define BP_SSP_TIMING_TIMEOUT (16) 91e4243f13SShawn Guo #define BM_SSP_TIMING_TIMEOUT (0xffff << 16) 92e4243f13SShawn Guo #define BP_SSP_TIMING_CLOCK_DIVIDE (8) 93e4243f13SShawn Guo #define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8) 94e4243f13SShawn Guo #define BP_SSP_TIMING_CLOCK_RATE (0) 95e4243f13SShawn Guo #define BM_SSP_TIMING_CLOCK_RATE (0xff) 96e4243f13SShawn Guo #define HW_SSP_CTRL1 (ssp_is_old() ? 0x060 : 0x080) 97e4243f13SShawn Guo #define BM_SSP_CTRL1_SDIO_IRQ (1 << 31) 98e4243f13SShawn Guo #define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30) 99e4243f13SShawn Guo #define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29) 100e4243f13SShawn Guo #define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28) 101e4243f13SShawn Guo #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27) 102e4243f13SShawn Guo #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26) 103e4243f13SShawn Guo #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25) 104e4243f13SShawn Guo #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24) 105e4243f13SShawn Guo #define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23) 106e4243f13SShawn Guo #define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22) 107e4243f13SShawn Guo #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21) 108e4243f13SShawn Guo #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20) 109e4243f13SShawn Guo #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17) 110e4243f13SShawn Guo #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16) 111e4243f13SShawn Guo #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15) 112e4243f13SShawn Guo #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14) 113e4243f13SShawn Guo #define BM_SSP_CTRL1_DMA_ENABLE (1 << 13) 114e4243f13SShawn Guo #define BM_SSP_CTRL1_POLARITY (1 << 9) 115e4243f13SShawn Guo #define BP_SSP_CTRL1_WORD_LENGTH (4) 116e4243f13SShawn Guo #define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4) 117e4243f13SShawn Guo #define BP_SSP_CTRL1_SSP_MODE (0) 118e4243f13SShawn Guo #define BM_SSP_CTRL1_SSP_MODE (0xf) 119e4243f13SShawn Guo #define HW_SSP_SDRESP0 (ssp_is_old() ? 0x080 : 0x0a0) 120e4243f13SShawn Guo #define HW_SSP_SDRESP1 (ssp_is_old() ? 0x090 : 0x0b0) 121e4243f13SShawn Guo #define HW_SSP_SDRESP2 (ssp_is_old() ? 0x0a0 : 0x0c0) 122e4243f13SShawn Guo #define HW_SSP_SDRESP3 (ssp_is_old() ? 0x0b0 : 0x0d0) 123e4243f13SShawn Guo #define HW_SSP_STATUS (ssp_is_old() ? 0x0c0 : 0x100) 124e4243f13SShawn Guo #define BM_SSP_STATUS_CARD_DETECT (1 << 28) 125e4243f13SShawn Guo #define BM_SSP_STATUS_SDIO_IRQ (1 << 17) 126e4243f13SShawn Guo #define HW_SSP_VERSION (cpu_is_mx23() ? 0x110 : 0x130) 127e4243f13SShawn Guo #define BP_SSP_VERSION_MAJOR (24) 128e4243f13SShawn Guo 129e4243f13SShawn Guo #define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field) 130e4243f13SShawn Guo 131e4243f13SShawn Guo #define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \ 132e4243f13SShawn Guo BM_SSP_CTRL1_RESP_ERR_IRQ | \ 133e4243f13SShawn Guo BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \ 134e4243f13SShawn Guo BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \ 135e4243f13SShawn Guo BM_SSP_CTRL1_DATA_CRC_IRQ | \ 136e4243f13SShawn Guo BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \ 137e4243f13SShawn Guo BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \ 138e4243f13SShawn Guo BM_SSP_CTRL1_FIFO_OVERRUN_IRQ) 139e4243f13SShawn Guo 140e4243f13SShawn Guo #define SSP_PIO_NUM 3 141e4243f13SShawn Guo 142e4243f13SShawn Guo struct mxs_mmc_host { 143e4243f13SShawn Guo struct mmc_host *mmc; 144e4243f13SShawn Guo struct mmc_request *mrq; 145e4243f13SShawn Guo struct mmc_command *cmd; 146e4243f13SShawn Guo struct mmc_data *data; 147e4243f13SShawn Guo 148e4243f13SShawn Guo void __iomem *base; 149e4243f13SShawn Guo int irq; 150e4243f13SShawn Guo struct resource *res; 151e4243f13SShawn Guo struct resource *dma_res; 152e4243f13SShawn Guo struct clk *clk; 153e4243f13SShawn Guo unsigned int clk_rate; 154e4243f13SShawn Guo 155e4243f13SShawn Guo struct dma_chan *dmach; 156e4243f13SShawn Guo struct mxs_dma_data dma_data; 157e4243f13SShawn Guo unsigned int dma_dir; 15805f5799cSVinod Koul enum dma_transfer_direction slave_dirn; 159e4243f13SShawn Guo u32 ssp_pio_words[SSP_PIO_NUM]; 160e4243f13SShawn Guo 161e4243f13SShawn Guo unsigned int version; 162e4243f13SShawn Guo unsigned char bus_width; 163e4243f13SShawn Guo spinlock_t lock; 164e4243f13SShawn Guo int sdio_irq_en; 165e4243f13SShawn Guo }; 166e4243f13SShawn Guo 167e4243f13SShawn Guo static int mxs_mmc_get_ro(struct mmc_host *mmc) 168e4243f13SShawn Guo { 169e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 170e4243f13SShawn Guo struct mxs_mmc_platform_data *pdata = 171e4243f13SShawn Guo mmc_dev(host->mmc)->platform_data; 172e4243f13SShawn Guo 173e4243f13SShawn Guo if (!pdata) 174e4243f13SShawn Guo return -EFAULT; 175e4243f13SShawn Guo 176e4243f13SShawn Guo if (!gpio_is_valid(pdata->wp_gpio)) 177e4243f13SShawn Guo return -EINVAL; 178e4243f13SShawn Guo 179e4243f13SShawn Guo return gpio_get_value(pdata->wp_gpio); 180e4243f13SShawn Guo } 181e4243f13SShawn Guo 182e4243f13SShawn Guo static int mxs_mmc_get_cd(struct mmc_host *mmc) 183e4243f13SShawn Guo { 184e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 185e4243f13SShawn Guo 186e4243f13SShawn Guo return !(readl(host->base + HW_SSP_STATUS) & 187e4243f13SShawn Guo BM_SSP_STATUS_CARD_DETECT); 188e4243f13SShawn Guo } 189e4243f13SShawn Guo 190e4243f13SShawn Guo static void mxs_mmc_reset(struct mxs_mmc_host *host) 191e4243f13SShawn Guo { 192e4243f13SShawn Guo u32 ctrl0, ctrl1; 193e4243f13SShawn Guo 194e4243f13SShawn Guo mxs_reset_block(host->base); 195e4243f13SShawn Guo 196e4243f13SShawn Guo ctrl0 = BM_SSP_CTRL0_IGNORE_CRC; 197e4243f13SShawn Guo ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) | 198e4243f13SShawn Guo BF_SSP(0x7, CTRL1_WORD_LENGTH) | 199e4243f13SShawn Guo BM_SSP_CTRL1_DMA_ENABLE | 200e4243f13SShawn Guo BM_SSP_CTRL1_POLARITY | 201e4243f13SShawn Guo BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN | 202e4243f13SShawn Guo BM_SSP_CTRL1_DATA_CRC_IRQ_EN | 203e4243f13SShawn Guo BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN | 204e4243f13SShawn Guo BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN | 205e4243f13SShawn Guo BM_SSP_CTRL1_RESP_ERR_IRQ_EN; 206e4243f13SShawn Guo 207e4243f13SShawn Guo writel(BF_SSP(0xffff, TIMING_TIMEOUT) | 208e4243f13SShawn Guo BF_SSP(2, TIMING_CLOCK_DIVIDE) | 209e4243f13SShawn Guo BF_SSP(0, TIMING_CLOCK_RATE), 210e4243f13SShawn Guo host->base + HW_SSP_TIMING); 211e4243f13SShawn Guo 212e4243f13SShawn Guo if (host->sdio_irq_en) { 213e4243f13SShawn Guo ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 214e4243f13SShawn Guo ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN; 215e4243f13SShawn Guo } 216e4243f13SShawn Guo 217e4243f13SShawn Guo writel(ctrl0, host->base + HW_SSP_CTRL0); 218e4243f13SShawn Guo writel(ctrl1, host->base + HW_SSP_CTRL1); 219e4243f13SShawn Guo } 220e4243f13SShawn Guo 221e4243f13SShawn Guo static void mxs_mmc_start_cmd(struct mxs_mmc_host *host, 222e4243f13SShawn Guo struct mmc_command *cmd); 223e4243f13SShawn Guo 224e4243f13SShawn Guo static void mxs_mmc_request_done(struct mxs_mmc_host *host) 225e4243f13SShawn Guo { 226e4243f13SShawn Guo struct mmc_command *cmd = host->cmd; 227e4243f13SShawn Guo struct mmc_data *data = host->data; 228e4243f13SShawn Guo struct mmc_request *mrq = host->mrq; 229e4243f13SShawn Guo 230e4243f13SShawn Guo if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) { 231e4243f13SShawn Guo if (mmc_resp_type(cmd) & MMC_RSP_136) { 232e4243f13SShawn Guo cmd->resp[3] = readl(host->base + HW_SSP_SDRESP0); 233e4243f13SShawn Guo cmd->resp[2] = readl(host->base + HW_SSP_SDRESP1); 234e4243f13SShawn Guo cmd->resp[1] = readl(host->base + HW_SSP_SDRESP2); 235e4243f13SShawn Guo cmd->resp[0] = readl(host->base + HW_SSP_SDRESP3); 236e4243f13SShawn Guo } else { 237e4243f13SShawn Guo cmd->resp[0] = readl(host->base + HW_SSP_SDRESP0); 238e4243f13SShawn Guo } 239e4243f13SShawn Guo } 240e4243f13SShawn Guo 241e4243f13SShawn Guo if (data) { 242e4243f13SShawn Guo dma_unmap_sg(mmc_dev(host->mmc), data->sg, 243e4243f13SShawn Guo data->sg_len, host->dma_dir); 244e4243f13SShawn Guo /* 245e4243f13SShawn Guo * If there was an error on any block, we mark all 246e4243f13SShawn Guo * data blocks as being in error. 247e4243f13SShawn Guo */ 248e4243f13SShawn Guo if (!data->error) 249e4243f13SShawn Guo data->bytes_xfered = data->blocks * data->blksz; 250e4243f13SShawn Guo else 251e4243f13SShawn Guo data->bytes_xfered = 0; 252e4243f13SShawn Guo 253e4243f13SShawn Guo host->data = NULL; 254e4243f13SShawn Guo if (mrq->stop) { 255e4243f13SShawn Guo mxs_mmc_start_cmd(host, mrq->stop); 256e4243f13SShawn Guo return; 257e4243f13SShawn Guo } 258e4243f13SShawn Guo } 259e4243f13SShawn Guo 260e4243f13SShawn Guo host->mrq = NULL; 261e4243f13SShawn Guo mmc_request_done(host->mmc, mrq); 262e4243f13SShawn Guo } 263e4243f13SShawn Guo 264e4243f13SShawn Guo static void mxs_mmc_dma_irq_callback(void *param) 265e4243f13SShawn Guo { 266e4243f13SShawn Guo struct mxs_mmc_host *host = param; 267e4243f13SShawn Guo 268e4243f13SShawn Guo mxs_mmc_request_done(host); 269e4243f13SShawn Guo } 270e4243f13SShawn Guo 271e4243f13SShawn Guo static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id) 272e4243f13SShawn Guo { 273e4243f13SShawn Guo struct mxs_mmc_host *host = dev_id; 274e4243f13SShawn Guo struct mmc_command *cmd = host->cmd; 275e4243f13SShawn Guo struct mmc_data *data = host->data; 276e4243f13SShawn Guo u32 stat; 277e4243f13SShawn Guo 278e4243f13SShawn Guo spin_lock(&host->lock); 279e4243f13SShawn Guo 280e4243f13SShawn Guo stat = readl(host->base + HW_SSP_CTRL1); 281e4243f13SShawn Guo writel(stat & MXS_MMC_IRQ_BITS, 282e4243f13SShawn Guo host->base + HW_SSP_CTRL1 + MXS_CLR_ADDR); 283e4243f13SShawn Guo 284e4243f13SShawn Guo if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN)) 285e4243f13SShawn Guo mmc_signal_sdio_irq(host->mmc); 286e4243f13SShawn Guo 287e4243f13SShawn Guo spin_unlock(&host->lock); 288e4243f13SShawn Guo 289e4243f13SShawn Guo if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ) 290e4243f13SShawn Guo cmd->error = -ETIMEDOUT; 291e4243f13SShawn Guo else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ) 292e4243f13SShawn Guo cmd->error = -EIO; 293e4243f13SShawn Guo 294e4243f13SShawn Guo if (data) { 295e4243f13SShawn Guo if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | 296e4243f13SShawn Guo BM_SSP_CTRL1_RECV_TIMEOUT_IRQ)) 297e4243f13SShawn Guo data->error = -ETIMEDOUT; 298e4243f13SShawn Guo else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ) 299e4243f13SShawn Guo data->error = -EILSEQ; 300e4243f13SShawn Guo else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | 301e4243f13SShawn Guo BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)) 302e4243f13SShawn Guo data->error = -EIO; 303e4243f13SShawn Guo } 304e4243f13SShawn Guo 305e4243f13SShawn Guo return IRQ_HANDLED; 306e4243f13SShawn Guo } 307e4243f13SShawn Guo 308e4243f13SShawn Guo static struct dma_async_tx_descriptor *mxs_mmc_prep_dma( 309921de864SHuang Shijie struct mxs_mmc_host *host, unsigned long flags) 310e4243f13SShawn Guo { 311e4243f13SShawn Guo struct dma_async_tx_descriptor *desc; 312e4243f13SShawn Guo struct mmc_data *data = host->data; 313e4243f13SShawn Guo struct scatterlist * sgl; 314e4243f13SShawn Guo unsigned int sg_len; 315e4243f13SShawn Guo 316e4243f13SShawn Guo if (data) { 317e4243f13SShawn Guo /* data */ 318e4243f13SShawn Guo dma_map_sg(mmc_dev(host->mmc), data->sg, 319e4243f13SShawn Guo data->sg_len, host->dma_dir); 320e4243f13SShawn Guo sgl = data->sg; 321e4243f13SShawn Guo sg_len = data->sg_len; 322e4243f13SShawn Guo } else { 323e4243f13SShawn Guo /* pio */ 324e4243f13SShawn Guo sgl = (struct scatterlist *) host->ssp_pio_words; 325e4243f13SShawn Guo sg_len = SSP_PIO_NUM; 326e4243f13SShawn Guo } 327e4243f13SShawn Guo 32816052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(host->dmach, 329921de864SHuang Shijie sgl, sg_len, host->slave_dirn, flags); 330e4243f13SShawn Guo if (desc) { 331e4243f13SShawn Guo desc->callback = mxs_mmc_dma_irq_callback; 332e4243f13SShawn Guo desc->callback_param = host; 333e4243f13SShawn Guo } else { 334e4243f13SShawn Guo if (data) 335e4243f13SShawn Guo dma_unmap_sg(mmc_dev(host->mmc), data->sg, 336e4243f13SShawn Guo data->sg_len, host->dma_dir); 337e4243f13SShawn Guo } 338e4243f13SShawn Guo 339e4243f13SShawn Guo return desc; 340e4243f13SShawn Guo } 341e4243f13SShawn Guo 342e4243f13SShawn Guo static void mxs_mmc_bc(struct mxs_mmc_host *host) 343e4243f13SShawn Guo { 344e4243f13SShawn Guo struct mmc_command *cmd = host->cmd; 345e4243f13SShawn Guo struct dma_async_tx_descriptor *desc; 346e4243f13SShawn Guo u32 ctrl0, cmd0, cmd1; 347e4243f13SShawn Guo 348e4243f13SShawn Guo ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC; 349e4243f13SShawn Guo cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC; 350e4243f13SShawn Guo cmd1 = cmd->arg; 351e4243f13SShawn Guo 352e4243f13SShawn Guo if (host->sdio_irq_en) { 353e4243f13SShawn Guo ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 354e4243f13SShawn Guo cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 355e4243f13SShawn Guo } 356e4243f13SShawn Guo 357e4243f13SShawn Guo host->ssp_pio_words[0] = ctrl0; 358e4243f13SShawn Guo host->ssp_pio_words[1] = cmd0; 359e4243f13SShawn Guo host->ssp_pio_words[2] = cmd1; 360e4243f13SShawn Guo host->dma_dir = DMA_NONE; 361a4e3e86dSShawn Guo host->slave_dirn = DMA_TRANS_NONE; 362921de864SHuang Shijie desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK); 363e4243f13SShawn Guo if (!desc) 364e4243f13SShawn Guo goto out; 365e4243f13SShawn Guo 366e4243f13SShawn Guo dmaengine_submit(desc); 367d04525edSShawn Guo dma_async_issue_pending(host->dmach); 368e4243f13SShawn Guo return; 369e4243f13SShawn Guo 370e4243f13SShawn Guo out: 371e4243f13SShawn Guo dev_warn(mmc_dev(host->mmc), 372e4243f13SShawn Guo "%s: failed to prep dma\n", __func__); 373e4243f13SShawn Guo } 374e4243f13SShawn Guo 375e4243f13SShawn Guo static void mxs_mmc_ac(struct mxs_mmc_host *host) 376e4243f13SShawn Guo { 377e4243f13SShawn Guo struct mmc_command *cmd = host->cmd; 378e4243f13SShawn Guo struct dma_async_tx_descriptor *desc; 379e4243f13SShawn Guo u32 ignore_crc, get_resp, long_resp; 380e4243f13SShawn Guo u32 ctrl0, cmd0, cmd1; 381e4243f13SShawn Guo 382e4243f13SShawn Guo ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ? 383e4243f13SShawn Guo 0 : BM_SSP_CTRL0_IGNORE_CRC; 384e4243f13SShawn Guo get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ? 385e4243f13SShawn Guo BM_SSP_CTRL0_GET_RESP : 0; 386e4243f13SShawn Guo long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ? 387e4243f13SShawn Guo BM_SSP_CTRL0_LONG_RESP : 0; 388e4243f13SShawn Guo 389e4243f13SShawn Guo ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp; 390e4243f13SShawn Guo cmd0 = BF_SSP(cmd->opcode, CMD0_CMD); 391e4243f13SShawn Guo cmd1 = cmd->arg; 392e4243f13SShawn Guo 393e4243f13SShawn Guo if (host->sdio_irq_en) { 394e4243f13SShawn Guo ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 395e4243f13SShawn Guo cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 396e4243f13SShawn Guo } 397e4243f13SShawn Guo 398e4243f13SShawn Guo host->ssp_pio_words[0] = ctrl0; 399e4243f13SShawn Guo host->ssp_pio_words[1] = cmd0; 400e4243f13SShawn Guo host->ssp_pio_words[2] = cmd1; 401e4243f13SShawn Guo host->dma_dir = DMA_NONE; 402a4e3e86dSShawn Guo host->slave_dirn = DMA_TRANS_NONE; 403921de864SHuang Shijie desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK); 404e4243f13SShawn Guo if (!desc) 405e4243f13SShawn Guo goto out; 406e4243f13SShawn Guo 407e4243f13SShawn Guo dmaengine_submit(desc); 408d04525edSShawn Guo dma_async_issue_pending(host->dmach); 409e4243f13SShawn Guo return; 410e4243f13SShawn Guo 411e4243f13SShawn Guo out: 412e4243f13SShawn Guo dev_warn(mmc_dev(host->mmc), 413e4243f13SShawn Guo "%s: failed to prep dma\n", __func__); 414e4243f13SShawn Guo } 415e4243f13SShawn Guo 416e4243f13SShawn Guo static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns) 417e4243f13SShawn Guo { 418e4243f13SShawn Guo const unsigned int ssp_timeout_mul = 4096; 419e4243f13SShawn Guo /* 420e4243f13SShawn Guo * Calculate ticks in ms since ns are large numbers 421e4243f13SShawn Guo * and might overflow 422e4243f13SShawn Guo */ 423e4243f13SShawn Guo const unsigned int clock_per_ms = clock_rate / 1000; 424e4243f13SShawn Guo const unsigned int ms = ns / 1000; 425e4243f13SShawn Guo const unsigned int ticks = ms * clock_per_ms; 426e4243f13SShawn Guo const unsigned int ssp_ticks = ticks / ssp_timeout_mul; 427e4243f13SShawn Guo 428e4243f13SShawn Guo WARN_ON(ssp_ticks == 0); 429e4243f13SShawn Guo return ssp_ticks; 430e4243f13SShawn Guo } 431e4243f13SShawn Guo 432e4243f13SShawn Guo static void mxs_mmc_adtc(struct mxs_mmc_host *host) 433e4243f13SShawn Guo { 434e4243f13SShawn Guo struct mmc_command *cmd = host->cmd; 435e4243f13SShawn Guo struct mmc_data *data = cmd->data; 436e4243f13SShawn Guo struct dma_async_tx_descriptor *desc; 437e4243f13SShawn Guo struct scatterlist *sgl = data->sg, *sg; 438e4243f13SShawn Guo unsigned int sg_len = data->sg_len; 439e4243f13SShawn Guo int i; 440e4243f13SShawn Guo 441e4243f13SShawn Guo unsigned short dma_data_dir, timeout; 44205f5799cSVinod Koul enum dma_transfer_direction slave_dirn; 443e4243f13SShawn Guo unsigned int data_size = 0, log2_blksz; 444e4243f13SShawn Guo unsigned int blocks = data->blocks; 445e4243f13SShawn Guo 446e4243f13SShawn Guo u32 ignore_crc, get_resp, long_resp, read; 447e4243f13SShawn Guo u32 ctrl0, cmd0, cmd1, val; 448e4243f13SShawn Guo 449e4243f13SShawn Guo ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ? 450e4243f13SShawn Guo 0 : BM_SSP_CTRL0_IGNORE_CRC; 451e4243f13SShawn Guo get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ? 452e4243f13SShawn Guo BM_SSP_CTRL0_GET_RESP : 0; 453e4243f13SShawn Guo long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ? 454e4243f13SShawn Guo BM_SSP_CTRL0_LONG_RESP : 0; 455e4243f13SShawn Guo 456e4243f13SShawn Guo if (data->flags & MMC_DATA_WRITE) { 457e4243f13SShawn Guo dma_data_dir = DMA_TO_DEVICE; 45805f5799cSVinod Koul slave_dirn = DMA_MEM_TO_DEV; 459e4243f13SShawn Guo read = 0; 460e4243f13SShawn Guo } else { 461e4243f13SShawn Guo dma_data_dir = DMA_FROM_DEVICE; 46205f5799cSVinod Koul slave_dirn = DMA_DEV_TO_MEM; 463e4243f13SShawn Guo read = BM_SSP_CTRL0_READ; 464e4243f13SShawn Guo } 465e4243f13SShawn Guo 466e4243f13SShawn Guo ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) | 467e4243f13SShawn Guo ignore_crc | get_resp | long_resp | 468e4243f13SShawn Guo BM_SSP_CTRL0_DATA_XFER | read | 469e4243f13SShawn Guo BM_SSP_CTRL0_WAIT_FOR_IRQ | 470e4243f13SShawn Guo BM_SSP_CTRL0_ENABLE; 471e4243f13SShawn Guo 472e4243f13SShawn Guo cmd0 = BF_SSP(cmd->opcode, CMD0_CMD); 473e4243f13SShawn Guo 474e4243f13SShawn Guo /* get logarithm to base 2 of block size for setting register */ 475e4243f13SShawn Guo log2_blksz = ilog2(data->blksz); 476e4243f13SShawn Guo 477e4243f13SShawn Guo /* 478e4243f13SShawn Guo * take special care of the case that data size from data->sg 479e4243f13SShawn Guo * is not equal to blocks x blksz 480e4243f13SShawn Guo */ 481e4243f13SShawn Guo for_each_sg(sgl, sg, sg_len, i) 482e4243f13SShawn Guo data_size += sg->length; 483e4243f13SShawn Guo 484e4243f13SShawn Guo if (data_size != data->blocks * data->blksz) 485e4243f13SShawn Guo blocks = 1; 486e4243f13SShawn Guo 487e4243f13SShawn Guo /* xfer count, block size and count need to be set differently */ 488e4243f13SShawn Guo if (ssp_is_old()) { 489e4243f13SShawn Guo ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT); 490e4243f13SShawn Guo cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) | 491e4243f13SShawn Guo BF_SSP(blocks - 1, CMD0_BLOCK_COUNT); 492e4243f13SShawn Guo } else { 493e4243f13SShawn Guo writel(data_size, host->base + HW_SSP_XFER_SIZE); 494e4243f13SShawn Guo writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) | 495e4243f13SShawn Guo BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT), 496e4243f13SShawn Guo host->base + HW_SSP_BLOCK_SIZE); 497e4243f13SShawn Guo } 498e4243f13SShawn Guo 499e4243f13SShawn Guo if ((cmd->opcode == MMC_STOP_TRANSMISSION) || 500e4243f13SShawn Guo (cmd->opcode == SD_IO_RW_EXTENDED)) 501e4243f13SShawn Guo cmd0 |= BM_SSP_CMD0_APPEND_8CYC; 502e4243f13SShawn Guo 503e4243f13SShawn Guo cmd1 = cmd->arg; 504e4243f13SShawn Guo 505e4243f13SShawn Guo if (host->sdio_irq_en) { 506e4243f13SShawn Guo ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 507e4243f13SShawn Guo cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 508e4243f13SShawn Guo } 509e4243f13SShawn Guo 510e4243f13SShawn Guo /* set the timeout count */ 511e4243f13SShawn Guo timeout = mxs_ns_to_ssp_ticks(host->clk_rate, data->timeout_ns); 512e4243f13SShawn Guo val = readl(host->base + HW_SSP_TIMING); 513e4243f13SShawn Guo val &= ~(BM_SSP_TIMING_TIMEOUT); 514e4243f13SShawn Guo val |= BF_SSP(timeout, TIMING_TIMEOUT); 515e4243f13SShawn Guo writel(val, host->base + HW_SSP_TIMING); 516e4243f13SShawn Guo 517e4243f13SShawn Guo /* pio */ 518e4243f13SShawn Guo host->ssp_pio_words[0] = ctrl0; 519e4243f13SShawn Guo host->ssp_pio_words[1] = cmd0; 520e4243f13SShawn Guo host->ssp_pio_words[2] = cmd1; 521e4243f13SShawn Guo host->dma_dir = DMA_NONE; 522a4e3e86dSShawn Guo host->slave_dirn = DMA_TRANS_NONE; 523e4243f13SShawn Guo desc = mxs_mmc_prep_dma(host, 0); 524e4243f13SShawn Guo if (!desc) 525e4243f13SShawn Guo goto out; 526e4243f13SShawn Guo 527e4243f13SShawn Guo /* append data sg */ 528e4243f13SShawn Guo WARN_ON(host->data != NULL); 529e4243f13SShawn Guo host->data = data; 530e4243f13SShawn Guo host->dma_dir = dma_data_dir; 53105f5799cSVinod Koul host->slave_dirn = slave_dirn; 532921de864SHuang Shijie desc = mxs_mmc_prep_dma(host, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 533e4243f13SShawn Guo if (!desc) 534e4243f13SShawn Guo goto out; 535e4243f13SShawn Guo 536e4243f13SShawn Guo dmaengine_submit(desc); 537d04525edSShawn Guo dma_async_issue_pending(host->dmach); 538e4243f13SShawn Guo return; 539e4243f13SShawn Guo out: 540e4243f13SShawn Guo dev_warn(mmc_dev(host->mmc), 541e4243f13SShawn Guo "%s: failed to prep dma\n", __func__); 542e4243f13SShawn Guo } 543e4243f13SShawn Guo 544e4243f13SShawn Guo static void mxs_mmc_start_cmd(struct mxs_mmc_host *host, 545e4243f13SShawn Guo struct mmc_command *cmd) 546e4243f13SShawn Guo { 547e4243f13SShawn Guo host->cmd = cmd; 548e4243f13SShawn Guo 549e4243f13SShawn Guo switch (mmc_cmd_type(cmd)) { 550e4243f13SShawn Guo case MMC_CMD_BC: 551e4243f13SShawn Guo mxs_mmc_bc(host); 552e4243f13SShawn Guo break; 553e4243f13SShawn Guo case MMC_CMD_BCR: 554e4243f13SShawn Guo mxs_mmc_ac(host); 555e4243f13SShawn Guo break; 556e4243f13SShawn Guo case MMC_CMD_AC: 557e4243f13SShawn Guo mxs_mmc_ac(host); 558e4243f13SShawn Guo break; 559e4243f13SShawn Guo case MMC_CMD_ADTC: 560e4243f13SShawn Guo mxs_mmc_adtc(host); 561e4243f13SShawn Guo break; 562e4243f13SShawn Guo default: 563e4243f13SShawn Guo dev_warn(mmc_dev(host->mmc), 564e4243f13SShawn Guo "%s: unknown MMC command\n", __func__); 565e4243f13SShawn Guo break; 566e4243f13SShawn Guo } 567e4243f13SShawn Guo } 568e4243f13SShawn Guo 569e4243f13SShawn Guo static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 570e4243f13SShawn Guo { 571e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 572e4243f13SShawn Guo 573e4243f13SShawn Guo WARN_ON(host->mrq != NULL); 574e4243f13SShawn Guo host->mrq = mrq; 575e4243f13SShawn Guo mxs_mmc_start_cmd(host, mrq->cmd); 576e4243f13SShawn Guo } 577e4243f13SShawn Guo 578e4243f13SShawn Guo static void mxs_mmc_set_clk_rate(struct mxs_mmc_host *host, unsigned int rate) 579e4243f13SShawn Guo { 580d982dcdcSKoen Beel unsigned int ssp_clk, ssp_sck; 581d982dcdcSKoen Beel u32 clock_divide, clock_rate; 582e4243f13SShawn Guo u32 val; 583e4243f13SShawn Guo 584d982dcdcSKoen Beel ssp_clk = clk_get_rate(host->clk); 585e4243f13SShawn Guo 586d982dcdcSKoen Beel for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) { 587d982dcdcSKoen Beel clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide); 588d982dcdcSKoen Beel clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0; 589d982dcdcSKoen Beel if (clock_rate <= 255) 590e4243f13SShawn Guo break; 591e4243f13SShawn Guo } 592e4243f13SShawn Guo 593d982dcdcSKoen Beel if (clock_divide > 254) { 594e4243f13SShawn Guo dev_err(mmc_dev(host->mmc), 595e4243f13SShawn Guo "%s: cannot set clock to %d\n", __func__, rate); 596e4243f13SShawn Guo return; 597e4243f13SShawn Guo } 598e4243f13SShawn Guo 599d982dcdcSKoen Beel ssp_sck = ssp_clk / clock_divide / (1 + clock_rate); 600e4243f13SShawn Guo 601e4243f13SShawn Guo val = readl(host->base + HW_SSP_TIMING); 602e4243f13SShawn Guo val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE); 603d982dcdcSKoen Beel val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE); 604d982dcdcSKoen Beel val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE); 605e4243f13SShawn Guo writel(val, host->base + HW_SSP_TIMING); 606e4243f13SShawn Guo 607d982dcdcSKoen Beel host->clk_rate = ssp_sck; 608e4243f13SShawn Guo 609e4243f13SShawn Guo dev_dbg(mmc_dev(host->mmc), 610d982dcdcSKoen Beel "%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n", 611d982dcdcSKoen Beel __func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate); 612e4243f13SShawn Guo } 613e4243f13SShawn Guo 614e4243f13SShawn Guo static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 615e4243f13SShawn Guo { 616e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 617e4243f13SShawn Guo 618e4243f13SShawn Guo if (ios->bus_width == MMC_BUS_WIDTH_8) 619e4243f13SShawn Guo host->bus_width = 2; 620e4243f13SShawn Guo else if (ios->bus_width == MMC_BUS_WIDTH_4) 621e4243f13SShawn Guo host->bus_width = 1; 622e4243f13SShawn Guo else 623e4243f13SShawn Guo host->bus_width = 0; 624e4243f13SShawn Guo 625e4243f13SShawn Guo if (ios->clock) 626e4243f13SShawn Guo mxs_mmc_set_clk_rate(host, ios->clock); 627e4243f13SShawn Guo } 628e4243f13SShawn Guo 629e4243f13SShawn Guo static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 630e4243f13SShawn Guo { 631e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 632e4243f13SShawn Guo unsigned long flags; 633e4243f13SShawn Guo 634e4243f13SShawn Guo spin_lock_irqsave(&host->lock, flags); 635e4243f13SShawn Guo 636e4243f13SShawn Guo host->sdio_irq_en = enable; 637e4243f13SShawn Guo 638e4243f13SShawn Guo if (enable) { 639e4243f13SShawn Guo writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, 640e4243f13SShawn Guo host->base + HW_SSP_CTRL0 + MXS_SET_ADDR); 641e4243f13SShawn Guo writel(BM_SSP_CTRL1_SDIO_IRQ_EN, 642e4243f13SShawn Guo host->base + HW_SSP_CTRL1 + MXS_SET_ADDR); 643e4243f13SShawn Guo 644e4243f13SShawn Guo if (readl(host->base + HW_SSP_STATUS) & BM_SSP_STATUS_SDIO_IRQ) 645e4243f13SShawn Guo mmc_signal_sdio_irq(host->mmc); 646e4243f13SShawn Guo 647e4243f13SShawn Guo } else { 648e4243f13SShawn Guo writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, 649e4243f13SShawn Guo host->base + HW_SSP_CTRL0 + MXS_CLR_ADDR); 650e4243f13SShawn Guo writel(BM_SSP_CTRL1_SDIO_IRQ_EN, 651e4243f13SShawn Guo host->base + HW_SSP_CTRL1 + MXS_CLR_ADDR); 652e4243f13SShawn Guo } 653e4243f13SShawn Guo 654e4243f13SShawn Guo spin_unlock_irqrestore(&host->lock, flags); 655e4243f13SShawn Guo } 656e4243f13SShawn Guo 657e4243f13SShawn Guo static const struct mmc_host_ops mxs_mmc_ops = { 658e4243f13SShawn Guo .request = mxs_mmc_request, 659e4243f13SShawn Guo .get_ro = mxs_mmc_get_ro, 660e4243f13SShawn Guo .get_cd = mxs_mmc_get_cd, 661e4243f13SShawn Guo .set_ios = mxs_mmc_set_ios, 662e4243f13SShawn Guo .enable_sdio_irq = mxs_mmc_enable_sdio_irq, 663e4243f13SShawn Guo }; 664e4243f13SShawn Guo 665e4243f13SShawn Guo static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param) 666e4243f13SShawn Guo { 667e4243f13SShawn Guo struct mxs_mmc_host *host = param; 668e4243f13SShawn Guo 669e4243f13SShawn Guo if (!mxs_dma_is_apbh(chan)) 670e4243f13SShawn Guo return false; 671e4243f13SShawn Guo 672e4243f13SShawn Guo if (chan->chan_id != host->dma_res->start) 673e4243f13SShawn Guo return false; 674e4243f13SShawn Guo 675e4243f13SShawn Guo chan->private = &host->dma_data; 676e4243f13SShawn Guo 677e4243f13SShawn Guo return true; 678e4243f13SShawn Guo } 679e4243f13SShawn Guo 680e4243f13SShawn Guo static int mxs_mmc_probe(struct platform_device *pdev) 681e4243f13SShawn Guo { 682e4243f13SShawn Guo struct mxs_mmc_host *host; 683e4243f13SShawn Guo struct mmc_host *mmc; 684e4243f13SShawn Guo struct resource *iores, *dmares, *r; 685e4243f13SShawn Guo struct mxs_mmc_platform_data *pdata; 6869c92cf24SShawn Guo struct pinctrl *pinctrl; 687e4243f13SShawn Guo int ret = 0, irq_err, irq_dma; 688e4243f13SShawn Guo dma_cap_mask_t mask; 689e4243f13SShawn Guo 690e4243f13SShawn Guo iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 691e4243f13SShawn Guo dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0); 692e4243f13SShawn Guo irq_err = platform_get_irq(pdev, 0); 693e4243f13SShawn Guo irq_dma = platform_get_irq(pdev, 1); 694e4243f13SShawn Guo if (!iores || !dmares || irq_err < 0 || irq_dma < 0) 695e4243f13SShawn Guo return -EINVAL; 696e4243f13SShawn Guo 697e4243f13SShawn Guo r = request_mem_region(iores->start, resource_size(iores), pdev->name); 698e4243f13SShawn Guo if (!r) 699e4243f13SShawn Guo return -EBUSY; 700e4243f13SShawn Guo 701e4243f13SShawn Guo mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev); 702e4243f13SShawn Guo if (!mmc) { 703e4243f13SShawn Guo ret = -ENOMEM; 704e4243f13SShawn Guo goto out_release_mem; 705e4243f13SShawn Guo } 706e4243f13SShawn Guo 707e4243f13SShawn Guo host = mmc_priv(mmc); 708e4243f13SShawn Guo host->base = ioremap(r->start, resource_size(r)); 709e4243f13SShawn Guo if (!host->base) { 710e4243f13SShawn Guo ret = -ENOMEM; 711e4243f13SShawn Guo goto out_mmc_free; 712e4243f13SShawn Guo } 713e4243f13SShawn Guo 714e4243f13SShawn Guo /* only major verion does matter */ 715e4243f13SShawn Guo host->version = readl(host->base + HW_SSP_VERSION) >> 716e4243f13SShawn Guo BP_SSP_VERSION_MAJOR; 717e4243f13SShawn Guo 718e4243f13SShawn Guo host->mmc = mmc; 719e4243f13SShawn Guo host->res = r; 720e4243f13SShawn Guo host->dma_res = dmares; 721e4243f13SShawn Guo host->irq = irq_err; 722e4243f13SShawn Guo host->sdio_irq_en = 0; 723e4243f13SShawn Guo 7249c92cf24SShawn Guo pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 7259c92cf24SShawn Guo if (IS_ERR(pinctrl)) { 7269c92cf24SShawn Guo ret = PTR_ERR(pinctrl); 7279c92cf24SShawn Guo goto out_iounmap; 7289c92cf24SShawn Guo } 7299c92cf24SShawn Guo 730e4243f13SShawn Guo host->clk = clk_get(&pdev->dev, NULL); 731e4243f13SShawn Guo if (IS_ERR(host->clk)) { 732e4243f13SShawn Guo ret = PTR_ERR(host->clk); 733e4243f13SShawn Guo goto out_iounmap; 734e4243f13SShawn Guo } 735efdfc52cSShawn Guo clk_prepare_enable(host->clk); 736e4243f13SShawn Guo 737e4243f13SShawn Guo mxs_mmc_reset(host); 738e4243f13SShawn Guo 739e4243f13SShawn Guo dma_cap_zero(mask); 740e4243f13SShawn Guo dma_cap_set(DMA_SLAVE, mask); 741e4243f13SShawn Guo host->dma_data.chan_irq = irq_dma; 742e4243f13SShawn Guo host->dmach = dma_request_channel(mask, mxs_mmc_dma_filter, host); 743e4243f13SShawn Guo if (!host->dmach) { 744e4243f13SShawn Guo dev_err(mmc_dev(host->mmc), 745e4243f13SShawn Guo "%s: failed to request dma\n", __func__); 746e4243f13SShawn Guo goto out_clk_put; 747e4243f13SShawn Guo } 748e4243f13SShawn Guo 749e4243f13SShawn Guo /* set mmc core parameters */ 750e4243f13SShawn Guo mmc->ops = &mxs_mmc_ops; 751e4243f13SShawn Guo mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 752e4243f13SShawn Guo MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL; 753e4243f13SShawn Guo 754e4243f13SShawn Guo pdata = mmc_dev(host->mmc)->platform_data; 755e4243f13SShawn Guo if (pdata) { 756e4243f13SShawn Guo if (pdata->flags & SLOTF_8_BIT_CAPABLE) 757e4243f13SShawn Guo mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA; 758e4243f13SShawn Guo if (pdata->flags & SLOTF_4_BIT_CAPABLE) 759e4243f13SShawn Guo mmc->caps |= MMC_CAP_4_BIT_DATA; 760e4243f13SShawn Guo } 761e4243f13SShawn Guo 762e4243f13SShawn Guo mmc->f_min = 400000; 763e4243f13SShawn Guo mmc->f_max = 288000000; 764e4243f13SShawn Guo mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 765e4243f13SShawn Guo 766e4243f13SShawn Guo mmc->max_segs = 52; 767e4243f13SShawn Guo mmc->max_blk_size = 1 << 0xf; 768e4243f13SShawn Guo mmc->max_blk_count = (ssp_is_old()) ? 0xff : 0xffffff; 769e4243f13SShawn Guo mmc->max_req_size = (ssp_is_old()) ? 0xffff : 0xffffffff; 770e4243f13SShawn Guo mmc->max_seg_size = dma_get_max_seg_size(host->dmach->device->dev); 771e4243f13SShawn Guo 772e4243f13SShawn Guo platform_set_drvdata(pdev, mmc); 773e4243f13SShawn Guo 774e4243f13SShawn Guo ret = request_irq(host->irq, mxs_mmc_irq_handler, 0, DRIVER_NAME, host); 775e4243f13SShawn Guo if (ret) 776e4243f13SShawn Guo goto out_free_dma; 777e4243f13SShawn Guo 778e4243f13SShawn Guo spin_lock_init(&host->lock); 779e4243f13SShawn Guo 780e4243f13SShawn Guo ret = mmc_add_host(mmc); 781e4243f13SShawn Guo if (ret) 782e4243f13SShawn Guo goto out_free_irq; 783e4243f13SShawn Guo 784e4243f13SShawn Guo dev_info(mmc_dev(host->mmc), "initialized\n"); 785e4243f13SShawn Guo 786e4243f13SShawn Guo return 0; 787e4243f13SShawn Guo 788e4243f13SShawn Guo out_free_irq: 789e4243f13SShawn Guo free_irq(host->irq, host); 790e4243f13SShawn Guo out_free_dma: 791e4243f13SShawn Guo if (host->dmach) 792e4243f13SShawn Guo dma_release_channel(host->dmach); 793e4243f13SShawn Guo out_clk_put: 794efdfc52cSShawn Guo clk_disable_unprepare(host->clk); 795e4243f13SShawn Guo clk_put(host->clk); 796e4243f13SShawn Guo out_iounmap: 797e4243f13SShawn Guo iounmap(host->base); 798e4243f13SShawn Guo out_mmc_free: 799e4243f13SShawn Guo mmc_free_host(mmc); 800e4243f13SShawn Guo out_release_mem: 801e4243f13SShawn Guo release_mem_region(iores->start, resource_size(iores)); 802e4243f13SShawn Guo return ret; 803e4243f13SShawn Guo } 804e4243f13SShawn Guo 805e4243f13SShawn Guo static int mxs_mmc_remove(struct platform_device *pdev) 806e4243f13SShawn Guo { 807e4243f13SShawn Guo struct mmc_host *mmc = platform_get_drvdata(pdev); 808e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 809e4243f13SShawn Guo struct resource *res = host->res; 810e4243f13SShawn Guo 811e4243f13SShawn Guo mmc_remove_host(mmc); 812e4243f13SShawn Guo 813e4243f13SShawn Guo free_irq(host->irq, host); 814e4243f13SShawn Guo 815e4243f13SShawn Guo platform_set_drvdata(pdev, NULL); 816e4243f13SShawn Guo 817e4243f13SShawn Guo if (host->dmach) 818e4243f13SShawn Guo dma_release_channel(host->dmach); 819e4243f13SShawn Guo 820efdfc52cSShawn Guo clk_disable_unprepare(host->clk); 821e4243f13SShawn Guo clk_put(host->clk); 822e4243f13SShawn Guo 823e4243f13SShawn Guo iounmap(host->base); 824e4243f13SShawn Guo 825e4243f13SShawn Guo mmc_free_host(mmc); 826e4243f13SShawn Guo 827e4243f13SShawn Guo release_mem_region(res->start, resource_size(res)); 828e4243f13SShawn Guo 829e4243f13SShawn Guo return 0; 830e4243f13SShawn Guo } 831e4243f13SShawn Guo 832e4243f13SShawn Guo #ifdef CONFIG_PM 833e4243f13SShawn Guo static int mxs_mmc_suspend(struct device *dev) 834e4243f13SShawn Guo { 835e4243f13SShawn Guo struct mmc_host *mmc = dev_get_drvdata(dev); 836e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 837e4243f13SShawn Guo int ret = 0; 838e4243f13SShawn Guo 839e4243f13SShawn Guo ret = mmc_suspend_host(mmc); 840e4243f13SShawn Guo 841efdfc52cSShawn Guo clk_disable_unprepare(host->clk); 842e4243f13SShawn Guo 843e4243f13SShawn Guo return ret; 844e4243f13SShawn Guo } 845e4243f13SShawn Guo 846e4243f13SShawn Guo static int mxs_mmc_resume(struct device *dev) 847e4243f13SShawn Guo { 848e4243f13SShawn Guo struct mmc_host *mmc = dev_get_drvdata(dev); 849e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 850e4243f13SShawn Guo int ret = 0; 851e4243f13SShawn Guo 852efdfc52cSShawn Guo clk_prepare_enable(host->clk); 853e4243f13SShawn Guo 854e4243f13SShawn Guo ret = mmc_resume_host(mmc); 855e4243f13SShawn Guo 856e4243f13SShawn Guo return ret; 857e4243f13SShawn Guo } 858e4243f13SShawn Guo 859e4243f13SShawn Guo static const struct dev_pm_ops mxs_mmc_pm_ops = { 860e4243f13SShawn Guo .suspend = mxs_mmc_suspend, 861e4243f13SShawn Guo .resume = mxs_mmc_resume, 862e4243f13SShawn Guo }; 863e4243f13SShawn Guo #endif 864e4243f13SShawn Guo 865e4243f13SShawn Guo static struct platform_driver mxs_mmc_driver = { 866e4243f13SShawn Guo .probe = mxs_mmc_probe, 867e4243f13SShawn Guo .remove = mxs_mmc_remove, 868e4243f13SShawn Guo .driver = { 869e4243f13SShawn Guo .name = DRIVER_NAME, 870e4243f13SShawn Guo .owner = THIS_MODULE, 871e4243f13SShawn Guo #ifdef CONFIG_PM 872e4243f13SShawn Guo .pm = &mxs_mmc_pm_ops, 873e4243f13SShawn Guo #endif 874e4243f13SShawn Guo }, 875e4243f13SShawn Guo }; 876e4243f13SShawn Guo 877d1f81a64SAxel Lin module_platform_driver(mxs_mmc_driver); 878e4243f13SShawn Guo 879e4243f13SShawn Guo MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral"); 880e4243f13SShawn Guo MODULE_AUTHOR("Freescale Semiconductor"); 881e4243f13SShawn Guo MODULE_LICENSE("GPL"); 882