1e4243f13SShawn Guo /* 2e4243f13SShawn Guo * Portions copyright (C) 2003 Russell King, PXA MMCI Driver 3e4243f13SShawn Guo * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver 4e4243f13SShawn Guo * 5e4243f13SShawn Guo * Copyright 2008 Embedded Alley Solutions, Inc. 6e4243f13SShawn Guo * Copyright 2009-2011 Freescale Semiconductor, Inc. 7e4243f13SShawn Guo * 8e4243f13SShawn Guo * This program is free software; you can redistribute it and/or modify 9e4243f13SShawn Guo * it under the terms of the GNU General Public License as published by 10e4243f13SShawn Guo * the Free Software Foundation; either version 2 of the License, or 11e4243f13SShawn Guo * (at your option) any later version. 12e4243f13SShawn Guo * 13e4243f13SShawn Guo * This program is distributed in the hope that it will be useful, 14e4243f13SShawn Guo * but WITHOUT ANY WARRANTY; without even the implied warranty of 15e4243f13SShawn Guo * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16e4243f13SShawn Guo * GNU General Public License for more details. 17e4243f13SShawn Guo * 18e4243f13SShawn Guo * You should have received a copy of the GNU General Public License along 19e4243f13SShawn Guo * with this program; if not, write to the Free Software Foundation, Inc., 20e4243f13SShawn Guo * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 21e4243f13SShawn Guo */ 22e4243f13SShawn Guo 23e4243f13SShawn Guo #include <linux/kernel.h> 24e4243f13SShawn Guo #include <linux/init.h> 25e4243f13SShawn Guo #include <linux/ioport.h> 26e4243f13SShawn Guo #include <linux/platform_device.h> 27e4243f13SShawn Guo #include <linux/delay.h> 28e4243f13SShawn Guo #include <linux/interrupt.h> 29e4243f13SShawn Guo #include <linux/dma-mapping.h> 30e4243f13SShawn Guo #include <linux/dmaengine.h> 31e4243f13SShawn Guo #include <linux/highmem.h> 32e4243f13SShawn Guo #include <linux/clk.h> 33e4243f13SShawn Guo #include <linux/err.h> 34e4243f13SShawn Guo #include <linux/completion.h> 35e4243f13SShawn Guo #include <linux/mmc/host.h> 36e4243f13SShawn Guo #include <linux/mmc/mmc.h> 37e4243f13SShawn Guo #include <linux/mmc/sdio.h> 38e4243f13SShawn Guo #include <linux/gpio.h> 39e4243f13SShawn Guo #include <linux/regulator/consumer.h> 4088b47679SPaul Gortmaker #include <linux/module.h> 41e4243f13SShawn Guo 42e4243f13SShawn Guo #include <mach/mxs.h> 43e4243f13SShawn Guo #include <mach/common.h> 44e4243f13SShawn Guo #include <mach/dma.h> 45e4243f13SShawn Guo #include <mach/mmc.h> 46e4243f13SShawn Guo 47e4243f13SShawn Guo #define DRIVER_NAME "mxs-mmc" 48e4243f13SShawn Guo 49e4243f13SShawn Guo /* card detect polling timeout */ 50e4243f13SShawn Guo #define MXS_MMC_DETECT_TIMEOUT (HZ/2) 51e4243f13SShawn Guo 52e4243f13SShawn Guo #define SSP_VERSION_LATEST 4 53e4243f13SShawn Guo #define ssp_is_old() (host->version < SSP_VERSION_LATEST) 54e4243f13SShawn Guo 55e4243f13SShawn Guo /* SSP registers */ 56e4243f13SShawn Guo #define HW_SSP_CTRL0 0x000 57e4243f13SShawn Guo #define BM_SSP_CTRL0_RUN (1 << 29) 58e4243f13SShawn Guo #define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28) 59e4243f13SShawn Guo #define BM_SSP_CTRL0_IGNORE_CRC (1 << 26) 60e4243f13SShawn Guo #define BM_SSP_CTRL0_READ (1 << 25) 61e4243f13SShawn Guo #define BM_SSP_CTRL0_DATA_XFER (1 << 24) 62e4243f13SShawn Guo #define BP_SSP_CTRL0_BUS_WIDTH (22) 63e4243f13SShawn Guo #define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22) 64e4243f13SShawn Guo #define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21) 65e4243f13SShawn Guo #define BM_SSP_CTRL0_LONG_RESP (1 << 19) 66e4243f13SShawn Guo #define BM_SSP_CTRL0_GET_RESP (1 << 17) 67e4243f13SShawn Guo #define BM_SSP_CTRL0_ENABLE (1 << 16) 68e4243f13SShawn Guo #define BP_SSP_CTRL0_XFER_COUNT (0) 69e4243f13SShawn Guo #define BM_SSP_CTRL0_XFER_COUNT (0xffff) 70e4243f13SShawn Guo #define HW_SSP_CMD0 0x010 71e4243f13SShawn Guo #define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25) 72e4243f13SShawn Guo #define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22) 73e4243f13SShawn Guo #define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21) 74e4243f13SShawn Guo #define BM_SSP_CMD0_APPEND_8CYC (1 << 20) 75e4243f13SShawn Guo #define BP_SSP_CMD0_BLOCK_SIZE (16) 76e4243f13SShawn Guo #define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16) 77e4243f13SShawn Guo #define BP_SSP_CMD0_BLOCK_COUNT (8) 78e4243f13SShawn Guo #define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8) 79e4243f13SShawn Guo #define BP_SSP_CMD0_CMD (0) 80e4243f13SShawn Guo #define BM_SSP_CMD0_CMD (0xff) 81e4243f13SShawn Guo #define HW_SSP_CMD1 0x020 82e4243f13SShawn Guo #define HW_SSP_XFER_SIZE 0x030 83e4243f13SShawn Guo #define HW_SSP_BLOCK_SIZE 0x040 84e4243f13SShawn Guo #define BP_SSP_BLOCK_SIZE_BLOCK_COUNT (4) 85e4243f13SShawn Guo #define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4) 86e4243f13SShawn Guo #define BP_SSP_BLOCK_SIZE_BLOCK_SIZE (0) 87e4243f13SShawn Guo #define BM_SSP_BLOCK_SIZE_BLOCK_SIZE (0xf) 88e4243f13SShawn Guo #define HW_SSP_TIMING (ssp_is_old() ? 0x050 : 0x070) 89e4243f13SShawn Guo #define BP_SSP_TIMING_TIMEOUT (16) 90e4243f13SShawn Guo #define BM_SSP_TIMING_TIMEOUT (0xffff << 16) 91e4243f13SShawn Guo #define BP_SSP_TIMING_CLOCK_DIVIDE (8) 92e4243f13SShawn Guo #define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8) 93e4243f13SShawn Guo #define BP_SSP_TIMING_CLOCK_RATE (0) 94e4243f13SShawn Guo #define BM_SSP_TIMING_CLOCK_RATE (0xff) 95e4243f13SShawn Guo #define HW_SSP_CTRL1 (ssp_is_old() ? 0x060 : 0x080) 96e4243f13SShawn Guo #define BM_SSP_CTRL1_SDIO_IRQ (1 << 31) 97e4243f13SShawn Guo #define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30) 98e4243f13SShawn Guo #define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29) 99e4243f13SShawn Guo #define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28) 100e4243f13SShawn Guo #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27) 101e4243f13SShawn Guo #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26) 102e4243f13SShawn Guo #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25) 103e4243f13SShawn Guo #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24) 104e4243f13SShawn Guo #define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23) 105e4243f13SShawn Guo #define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22) 106e4243f13SShawn Guo #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21) 107e4243f13SShawn Guo #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20) 108e4243f13SShawn Guo #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17) 109e4243f13SShawn Guo #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16) 110e4243f13SShawn Guo #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15) 111e4243f13SShawn Guo #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14) 112e4243f13SShawn Guo #define BM_SSP_CTRL1_DMA_ENABLE (1 << 13) 113e4243f13SShawn Guo #define BM_SSP_CTRL1_POLARITY (1 << 9) 114e4243f13SShawn Guo #define BP_SSP_CTRL1_WORD_LENGTH (4) 115e4243f13SShawn Guo #define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4) 116e4243f13SShawn Guo #define BP_SSP_CTRL1_SSP_MODE (0) 117e4243f13SShawn Guo #define BM_SSP_CTRL1_SSP_MODE (0xf) 118e4243f13SShawn Guo #define HW_SSP_SDRESP0 (ssp_is_old() ? 0x080 : 0x0a0) 119e4243f13SShawn Guo #define HW_SSP_SDRESP1 (ssp_is_old() ? 0x090 : 0x0b0) 120e4243f13SShawn Guo #define HW_SSP_SDRESP2 (ssp_is_old() ? 0x0a0 : 0x0c0) 121e4243f13SShawn Guo #define HW_SSP_SDRESP3 (ssp_is_old() ? 0x0b0 : 0x0d0) 122e4243f13SShawn Guo #define HW_SSP_STATUS (ssp_is_old() ? 0x0c0 : 0x100) 123e4243f13SShawn Guo #define BM_SSP_STATUS_CARD_DETECT (1 << 28) 124e4243f13SShawn Guo #define BM_SSP_STATUS_SDIO_IRQ (1 << 17) 125e4243f13SShawn Guo #define HW_SSP_VERSION (cpu_is_mx23() ? 0x110 : 0x130) 126e4243f13SShawn Guo #define BP_SSP_VERSION_MAJOR (24) 127e4243f13SShawn Guo 128e4243f13SShawn Guo #define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field) 129e4243f13SShawn Guo 130e4243f13SShawn Guo #define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \ 131e4243f13SShawn Guo BM_SSP_CTRL1_RESP_ERR_IRQ | \ 132e4243f13SShawn Guo BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \ 133e4243f13SShawn Guo BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \ 134e4243f13SShawn Guo BM_SSP_CTRL1_DATA_CRC_IRQ | \ 135e4243f13SShawn Guo BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \ 136e4243f13SShawn Guo BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \ 137e4243f13SShawn Guo BM_SSP_CTRL1_FIFO_OVERRUN_IRQ) 138e4243f13SShawn Guo 139e4243f13SShawn Guo #define SSP_PIO_NUM 3 140e4243f13SShawn Guo 141e4243f13SShawn Guo struct mxs_mmc_host { 142e4243f13SShawn Guo struct mmc_host *mmc; 143e4243f13SShawn Guo struct mmc_request *mrq; 144e4243f13SShawn Guo struct mmc_command *cmd; 145e4243f13SShawn Guo struct mmc_data *data; 146e4243f13SShawn Guo 147e4243f13SShawn Guo void __iomem *base; 148e4243f13SShawn Guo int irq; 149e4243f13SShawn Guo struct resource *res; 150e4243f13SShawn Guo struct resource *dma_res; 151e4243f13SShawn Guo struct clk *clk; 152e4243f13SShawn Guo unsigned int clk_rate; 153e4243f13SShawn Guo 154e4243f13SShawn Guo struct dma_chan *dmach; 155e4243f13SShawn Guo struct mxs_dma_data dma_data; 156e4243f13SShawn Guo unsigned int dma_dir; 157e4243f13SShawn Guo u32 ssp_pio_words[SSP_PIO_NUM]; 158e4243f13SShawn Guo 159e4243f13SShawn Guo unsigned int version; 160e4243f13SShawn Guo unsigned char bus_width; 161e4243f13SShawn Guo spinlock_t lock; 162e4243f13SShawn Guo int sdio_irq_en; 163e4243f13SShawn Guo }; 164e4243f13SShawn Guo 165e4243f13SShawn Guo static int mxs_mmc_get_ro(struct mmc_host *mmc) 166e4243f13SShawn Guo { 167e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 168e4243f13SShawn Guo struct mxs_mmc_platform_data *pdata = 169e4243f13SShawn Guo mmc_dev(host->mmc)->platform_data; 170e4243f13SShawn Guo 171e4243f13SShawn Guo if (!pdata) 172e4243f13SShawn Guo return -EFAULT; 173e4243f13SShawn Guo 174e4243f13SShawn Guo if (!gpio_is_valid(pdata->wp_gpio)) 175e4243f13SShawn Guo return -EINVAL; 176e4243f13SShawn Guo 177e4243f13SShawn Guo return gpio_get_value(pdata->wp_gpio); 178e4243f13SShawn Guo } 179e4243f13SShawn Guo 180e4243f13SShawn Guo static int mxs_mmc_get_cd(struct mmc_host *mmc) 181e4243f13SShawn Guo { 182e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 183e4243f13SShawn Guo 184e4243f13SShawn Guo return !(readl(host->base + HW_SSP_STATUS) & 185e4243f13SShawn Guo BM_SSP_STATUS_CARD_DETECT); 186e4243f13SShawn Guo } 187e4243f13SShawn Guo 188e4243f13SShawn Guo static void mxs_mmc_reset(struct mxs_mmc_host *host) 189e4243f13SShawn Guo { 190e4243f13SShawn Guo u32 ctrl0, ctrl1; 191e4243f13SShawn Guo 192e4243f13SShawn Guo mxs_reset_block(host->base); 193e4243f13SShawn Guo 194e4243f13SShawn Guo ctrl0 = BM_SSP_CTRL0_IGNORE_CRC; 195e4243f13SShawn Guo ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) | 196e4243f13SShawn Guo BF_SSP(0x7, CTRL1_WORD_LENGTH) | 197e4243f13SShawn Guo BM_SSP_CTRL1_DMA_ENABLE | 198e4243f13SShawn Guo BM_SSP_CTRL1_POLARITY | 199e4243f13SShawn Guo BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN | 200e4243f13SShawn Guo BM_SSP_CTRL1_DATA_CRC_IRQ_EN | 201e4243f13SShawn Guo BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN | 202e4243f13SShawn Guo BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN | 203e4243f13SShawn Guo BM_SSP_CTRL1_RESP_ERR_IRQ_EN; 204e4243f13SShawn Guo 205e4243f13SShawn Guo writel(BF_SSP(0xffff, TIMING_TIMEOUT) | 206e4243f13SShawn Guo BF_SSP(2, TIMING_CLOCK_DIVIDE) | 207e4243f13SShawn Guo BF_SSP(0, TIMING_CLOCK_RATE), 208e4243f13SShawn Guo host->base + HW_SSP_TIMING); 209e4243f13SShawn Guo 210e4243f13SShawn Guo if (host->sdio_irq_en) { 211e4243f13SShawn Guo ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 212e4243f13SShawn Guo ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN; 213e4243f13SShawn Guo } 214e4243f13SShawn Guo 215e4243f13SShawn Guo writel(ctrl0, host->base + HW_SSP_CTRL0); 216e4243f13SShawn Guo writel(ctrl1, host->base + HW_SSP_CTRL1); 217e4243f13SShawn Guo } 218e4243f13SShawn Guo 219e4243f13SShawn Guo static void mxs_mmc_start_cmd(struct mxs_mmc_host *host, 220e4243f13SShawn Guo struct mmc_command *cmd); 221e4243f13SShawn Guo 222e4243f13SShawn Guo static void mxs_mmc_request_done(struct mxs_mmc_host *host) 223e4243f13SShawn Guo { 224e4243f13SShawn Guo struct mmc_command *cmd = host->cmd; 225e4243f13SShawn Guo struct mmc_data *data = host->data; 226e4243f13SShawn Guo struct mmc_request *mrq = host->mrq; 227e4243f13SShawn Guo 228e4243f13SShawn Guo if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) { 229e4243f13SShawn Guo if (mmc_resp_type(cmd) & MMC_RSP_136) { 230e4243f13SShawn Guo cmd->resp[3] = readl(host->base + HW_SSP_SDRESP0); 231e4243f13SShawn Guo cmd->resp[2] = readl(host->base + HW_SSP_SDRESP1); 232e4243f13SShawn Guo cmd->resp[1] = readl(host->base + HW_SSP_SDRESP2); 233e4243f13SShawn Guo cmd->resp[0] = readl(host->base + HW_SSP_SDRESP3); 234e4243f13SShawn Guo } else { 235e4243f13SShawn Guo cmd->resp[0] = readl(host->base + HW_SSP_SDRESP0); 236e4243f13SShawn Guo } 237e4243f13SShawn Guo } 238e4243f13SShawn Guo 239e4243f13SShawn Guo if (data) { 240e4243f13SShawn Guo dma_unmap_sg(mmc_dev(host->mmc), data->sg, 241e4243f13SShawn Guo data->sg_len, host->dma_dir); 242e4243f13SShawn Guo /* 243e4243f13SShawn Guo * If there was an error on any block, we mark all 244e4243f13SShawn Guo * data blocks as being in error. 245e4243f13SShawn Guo */ 246e4243f13SShawn Guo if (!data->error) 247e4243f13SShawn Guo data->bytes_xfered = data->blocks * data->blksz; 248e4243f13SShawn Guo else 249e4243f13SShawn Guo data->bytes_xfered = 0; 250e4243f13SShawn Guo 251e4243f13SShawn Guo host->data = NULL; 252e4243f13SShawn Guo if (mrq->stop) { 253e4243f13SShawn Guo mxs_mmc_start_cmd(host, mrq->stop); 254e4243f13SShawn Guo return; 255e4243f13SShawn Guo } 256e4243f13SShawn Guo } 257e4243f13SShawn Guo 258e4243f13SShawn Guo host->mrq = NULL; 259e4243f13SShawn Guo mmc_request_done(host->mmc, mrq); 260e4243f13SShawn Guo } 261e4243f13SShawn Guo 262e4243f13SShawn Guo static void mxs_mmc_dma_irq_callback(void *param) 263e4243f13SShawn Guo { 264e4243f13SShawn Guo struct mxs_mmc_host *host = param; 265e4243f13SShawn Guo 266e4243f13SShawn Guo mxs_mmc_request_done(host); 267e4243f13SShawn Guo } 268e4243f13SShawn Guo 269e4243f13SShawn Guo static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id) 270e4243f13SShawn Guo { 271e4243f13SShawn Guo struct mxs_mmc_host *host = dev_id; 272e4243f13SShawn Guo struct mmc_command *cmd = host->cmd; 273e4243f13SShawn Guo struct mmc_data *data = host->data; 274e4243f13SShawn Guo u32 stat; 275e4243f13SShawn Guo 276e4243f13SShawn Guo spin_lock(&host->lock); 277e4243f13SShawn Guo 278e4243f13SShawn Guo stat = readl(host->base + HW_SSP_CTRL1); 279e4243f13SShawn Guo writel(stat & MXS_MMC_IRQ_BITS, 280e4243f13SShawn Guo host->base + HW_SSP_CTRL1 + MXS_CLR_ADDR); 281e4243f13SShawn Guo 282e4243f13SShawn Guo if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN)) 283e4243f13SShawn Guo mmc_signal_sdio_irq(host->mmc); 284e4243f13SShawn Guo 285e4243f13SShawn Guo spin_unlock(&host->lock); 286e4243f13SShawn Guo 287e4243f13SShawn Guo if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ) 288e4243f13SShawn Guo cmd->error = -ETIMEDOUT; 289e4243f13SShawn Guo else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ) 290e4243f13SShawn Guo cmd->error = -EIO; 291e4243f13SShawn Guo 292e4243f13SShawn Guo if (data) { 293e4243f13SShawn Guo if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | 294e4243f13SShawn Guo BM_SSP_CTRL1_RECV_TIMEOUT_IRQ)) 295e4243f13SShawn Guo data->error = -ETIMEDOUT; 296e4243f13SShawn Guo else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ) 297e4243f13SShawn Guo data->error = -EILSEQ; 298e4243f13SShawn Guo else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | 299e4243f13SShawn Guo BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)) 300e4243f13SShawn Guo data->error = -EIO; 301e4243f13SShawn Guo } 302e4243f13SShawn Guo 303e4243f13SShawn Guo return IRQ_HANDLED; 304e4243f13SShawn Guo } 305e4243f13SShawn Guo 306e4243f13SShawn Guo static struct dma_async_tx_descriptor *mxs_mmc_prep_dma( 307e4243f13SShawn Guo struct mxs_mmc_host *host, unsigned int append) 308e4243f13SShawn Guo { 309e4243f13SShawn Guo struct dma_async_tx_descriptor *desc; 310e4243f13SShawn Guo struct mmc_data *data = host->data; 311e4243f13SShawn Guo struct scatterlist * sgl; 312e4243f13SShawn Guo unsigned int sg_len; 313e4243f13SShawn Guo 314e4243f13SShawn Guo if (data) { 315e4243f13SShawn Guo /* data */ 316e4243f13SShawn Guo dma_map_sg(mmc_dev(host->mmc), data->sg, 317e4243f13SShawn Guo data->sg_len, host->dma_dir); 318e4243f13SShawn Guo sgl = data->sg; 319e4243f13SShawn Guo sg_len = data->sg_len; 320e4243f13SShawn Guo } else { 321e4243f13SShawn Guo /* pio */ 322e4243f13SShawn Guo sgl = (struct scatterlist *) host->ssp_pio_words; 323e4243f13SShawn Guo sg_len = SSP_PIO_NUM; 324e4243f13SShawn Guo } 325e4243f13SShawn Guo 326e4243f13SShawn Guo desc = host->dmach->device->device_prep_slave_sg(host->dmach, 327e4243f13SShawn Guo sgl, sg_len, host->dma_dir, append); 328e4243f13SShawn Guo if (desc) { 329e4243f13SShawn Guo desc->callback = mxs_mmc_dma_irq_callback; 330e4243f13SShawn Guo desc->callback_param = host; 331e4243f13SShawn Guo } else { 332e4243f13SShawn Guo if (data) 333e4243f13SShawn Guo dma_unmap_sg(mmc_dev(host->mmc), data->sg, 334e4243f13SShawn Guo data->sg_len, host->dma_dir); 335e4243f13SShawn Guo } 336e4243f13SShawn Guo 337e4243f13SShawn Guo return desc; 338e4243f13SShawn Guo } 339e4243f13SShawn Guo 340e4243f13SShawn Guo static void mxs_mmc_bc(struct mxs_mmc_host *host) 341e4243f13SShawn Guo { 342e4243f13SShawn Guo struct mmc_command *cmd = host->cmd; 343e4243f13SShawn Guo struct dma_async_tx_descriptor *desc; 344e4243f13SShawn Guo u32 ctrl0, cmd0, cmd1; 345e4243f13SShawn Guo 346e4243f13SShawn Guo ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC; 347e4243f13SShawn Guo cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC; 348e4243f13SShawn Guo cmd1 = cmd->arg; 349e4243f13SShawn Guo 350e4243f13SShawn Guo if (host->sdio_irq_en) { 351e4243f13SShawn Guo ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 352e4243f13SShawn Guo cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 353e4243f13SShawn Guo } 354e4243f13SShawn Guo 355e4243f13SShawn Guo host->ssp_pio_words[0] = ctrl0; 356e4243f13SShawn Guo host->ssp_pio_words[1] = cmd0; 357e4243f13SShawn Guo host->ssp_pio_words[2] = cmd1; 358e4243f13SShawn Guo host->dma_dir = DMA_NONE; 359e4243f13SShawn Guo desc = mxs_mmc_prep_dma(host, 0); 360e4243f13SShawn Guo if (!desc) 361e4243f13SShawn Guo goto out; 362e4243f13SShawn Guo 363e4243f13SShawn Guo dmaengine_submit(desc); 364e4243f13SShawn Guo return; 365e4243f13SShawn Guo 366e4243f13SShawn Guo out: 367e4243f13SShawn Guo dev_warn(mmc_dev(host->mmc), 368e4243f13SShawn Guo "%s: failed to prep dma\n", __func__); 369e4243f13SShawn Guo } 370e4243f13SShawn Guo 371e4243f13SShawn Guo static void mxs_mmc_ac(struct mxs_mmc_host *host) 372e4243f13SShawn Guo { 373e4243f13SShawn Guo struct mmc_command *cmd = host->cmd; 374e4243f13SShawn Guo struct dma_async_tx_descriptor *desc; 375e4243f13SShawn Guo u32 ignore_crc, get_resp, long_resp; 376e4243f13SShawn Guo u32 ctrl0, cmd0, cmd1; 377e4243f13SShawn Guo 378e4243f13SShawn Guo ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ? 379e4243f13SShawn Guo 0 : BM_SSP_CTRL0_IGNORE_CRC; 380e4243f13SShawn Guo get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ? 381e4243f13SShawn Guo BM_SSP_CTRL0_GET_RESP : 0; 382e4243f13SShawn Guo long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ? 383e4243f13SShawn Guo BM_SSP_CTRL0_LONG_RESP : 0; 384e4243f13SShawn Guo 385e4243f13SShawn Guo ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp; 386e4243f13SShawn Guo cmd0 = BF_SSP(cmd->opcode, CMD0_CMD); 387e4243f13SShawn Guo cmd1 = cmd->arg; 388e4243f13SShawn Guo 389e4243f13SShawn Guo if (host->sdio_irq_en) { 390e4243f13SShawn Guo ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 391e4243f13SShawn Guo cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 392e4243f13SShawn Guo } 393e4243f13SShawn Guo 394e4243f13SShawn Guo host->ssp_pio_words[0] = ctrl0; 395e4243f13SShawn Guo host->ssp_pio_words[1] = cmd0; 396e4243f13SShawn Guo host->ssp_pio_words[2] = cmd1; 397e4243f13SShawn Guo host->dma_dir = DMA_NONE; 398e4243f13SShawn Guo desc = mxs_mmc_prep_dma(host, 0); 399e4243f13SShawn Guo if (!desc) 400e4243f13SShawn Guo goto out; 401e4243f13SShawn Guo 402e4243f13SShawn Guo dmaengine_submit(desc); 403e4243f13SShawn Guo return; 404e4243f13SShawn Guo 405e4243f13SShawn Guo out: 406e4243f13SShawn Guo dev_warn(mmc_dev(host->mmc), 407e4243f13SShawn Guo "%s: failed to prep dma\n", __func__); 408e4243f13SShawn Guo } 409e4243f13SShawn Guo 410e4243f13SShawn Guo static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns) 411e4243f13SShawn Guo { 412e4243f13SShawn Guo const unsigned int ssp_timeout_mul = 4096; 413e4243f13SShawn Guo /* 414e4243f13SShawn Guo * Calculate ticks in ms since ns are large numbers 415e4243f13SShawn Guo * and might overflow 416e4243f13SShawn Guo */ 417e4243f13SShawn Guo const unsigned int clock_per_ms = clock_rate / 1000; 418e4243f13SShawn Guo const unsigned int ms = ns / 1000; 419e4243f13SShawn Guo const unsigned int ticks = ms * clock_per_ms; 420e4243f13SShawn Guo const unsigned int ssp_ticks = ticks / ssp_timeout_mul; 421e4243f13SShawn Guo 422e4243f13SShawn Guo WARN_ON(ssp_ticks == 0); 423e4243f13SShawn Guo return ssp_ticks; 424e4243f13SShawn Guo } 425e4243f13SShawn Guo 426e4243f13SShawn Guo static void mxs_mmc_adtc(struct mxs_mmc_host *host) 427e4243f13SShawn Guo { 428e4243f13SShawn Guo struct mmc_command *cmd = host->cmd; 429e4243f13SShawn Guo struct mmc_data *data = cmd->data; 430e4243f13SShawn Guo struct dma_async_tx_descriptor *desc; 431e4243f13SShawn Guo struct scatterlist *sgl = data->sg, *sg; 432e4243f13SShawn Guo unsigned int sg_len = data->sg_len; 433e4243f13SShawn Guo int i; 434e4243f13SShawn Guo 435e4243f13SShawn Guo unsigned short dma_data_dir, timeout; 436e4243f13SShawn Guo unsigned int data_size = 0, log2_blksz; 437e4243f13SShawn Guo unsigned int blocks = data->blocks; 438e4243f13SShawn Guo 439e4243f13SShawn Guo u32 ignore_crc, get_resp, long_resp, read; 440e4243f13SShawn Guo u32 ctrl0, cmd0, cmd1, val; 441e4243f13SShawn Guo 442e4243f13SShawn Guo ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ? 443e4243f13SShawn Guo 0 : BM_SSP_CTRL0_IGNORE_CRC; 444e4243f13SShawn Guo get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ? 445e4243f13SShawn Guo BM_SSP_CTRL0_GET_RESP : 0; 446e4243f13SShawn Guo long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ? 447e4243f13SShawn Guo BM_SSP_CTRL0_LONG_RESP : 0; 448e4243f13SShawn Guo 449e4243f13SShawn Guo if (data->flags & MMC_DATA_WRITE) { 450e4243f13SShawn Guo dma_data_dir = DMA_TO_DEVICE; 451e4243f13SShawn Guo read = 0; 452e4243f13SShawn Guo } else { 453e4243f13SShawn Guo dma_data_dir = DMA_FROM_DEVICE; 454e4243f13SShawn Guo read = BM_SSP_CTRL0_READ; 455e4243f13SShawn Guo } 456e4243f13SShawn Guo 457e4243f13SShawn Guo ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) | 458e4243f13SShawn Guo ignore_crc | get_resp | long_resp | 459e4243f13SShawn Guo BM_SSP_CTRL0_DATA_XFER | read | 460e4243f13SShawn Guo BM_SSP_CTRL0_WAIT_FOR_IRQ | 461e4243f13SShawn Guo BM_SSP_CTRL0_ENABLE; 462e4243f13SShawn Guo 463e4243f13SShawn Guo cmd0 = BF_SSP(cmd->opcode, CMD0_CMD); 464e4243f13SShawn Guo 465e4243f13SShawn Guo /* get logarithm to base 2 of block size for setting register */ 466e4243f13SShawn Guo log2_blksz = ilog2(data->blksz); 467e4243f13SShawn Guo 468e4243f13SShawn Guo /* 469e4243f13SShawn Guo * take special care of the case that data size from data->sg 470e4243f13SShawn Guo * is not equal to blocks x blksz 471e4243f13SShawn Guo */ 472e4243f13SShawn Guo for_each_sg(sgl, sg, sg_len, i) 473e4243f13SShawn Guo data_size += sg->length; 474e4243f13SShawn Guo 475e4243f13SShawn Guo if (data_size != data->blocks * data->blksz) 476e4243f13SShawn Guo blocks = 1; 477e4243f13SShawn Guo 478e4243f13SShawn Guo /* xfer count, block size and count need to be set differently */ 479e4243f13SShawn Guo if (ssp_is_old()) { 480e4243f13SShawn Guo ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT); 481e4243f13SShawn Guo cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) | 482e4243f13SShawn Guo BF_SSP(blocks - 1, CMD0_BLOCK_COUNT); 483e4243f13SShawn Guo } else { 484e4243f13SShawn Guo writel(data_size, host->base + HW_SSP_XFER_SIZE); 485e4243f13SShawn Guo writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) | 486e4243f13SShawn Guo BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT), 487e4243f13SShawn Guo host->base + HW_SSP_BLOCK_SIZE); 488e4243f13SShawn Guo } 489e4243f13SShawn Guo 490e4243f13SShawn Guo if ((cmd->opcode == MMC_STOP_TRANSMISSION) || 491e4243f13SShawn Guo (cmd->opcode == SD_IO_RW_EXTENDED)) 492e4243f13SShawn Guo cmd0 |= BM_SSP_CMD0_APPEND_8CYC; 493e4243f13SShawn Guo 494e4243f13SShawn Guo cmd1 = cmd->arg; 495e4243f13SShawn Guo 496e4243f13SShawn Guo if (host->sdio_irq_en) { 497e4243f13SShawn Guo ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK; 498e4243f13SShawn Guo cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN; 499e4243f13SShawn Guo } 500e4243f13SShawn Guo 501e4243f13SShawn Guo /* set the timeout count */ 502e4243f13SShawn Guo timeout = mxs_ns_to_ssp_ticks(host->clk_rate, data->timeout_ns); 503e4243f13SShawn Guo val = readl(host->base + HW_SSP_TIMING); 504e4243f13SShawn Guo val &= ~(BM_SSP_TIMING_TIMEOUT); 505e4243f13SShawn Guo val |= BF_SSP(timeout, TIMING_TIMEOUT); 506e4243f13SShawn Guo writel(val, host->base + HW_SSP_TIMING); 507e4243f13SShawn Guo 508e4243f13SShawn Guo /* pio */ 509e4243f13SShawn Guo host->ssp_pio_words[0] = ctrl0; 510e4243f13SShawn Guo host->ssp_pio_words[1] = cmd0; 511e4243f13SShawn Guo host->ssp_pio_words[2] = cmd1; 512e4243f13SShawn Guo host->dma_dir = DMA_NONE; 513e4243f13SShawn Guo desc = mxs_mmc_prep_dma(host, 0); 514e4243f13SShawn Guo if (!desc) 515e4243f13SShawn Guo goto out; 516e4243f13SShawn Guo 517e4243f13SShawn Guo /* append data sg */ 518e4243f13SShawn Guo WARN_ON(host->data != NULL); 519e4243f13SShawn Guo host->data = data; 520e4243f13SShawn Guo host->dma_dir = dma_data_dir; 521e4243f13SShawn Guo desc = mxs_mmc_prep_dma(host, 1); 522e4243f13SShawn Guo if (!desc) 523e4243f13SShawn Guo goto out; 524e4243f13SShawn Guo 525e4243f13SShawn Guo dmaengine_submit(desc); 526e4243f13SShawn Guo return; 527e4243f13SShawn Guo out: 528e4243f13SShawn Guo dev_warn(mmc_dev(host->mmc), 529e4243f13SShawn Guo "%s: failed to prep dma\n", __func__); 530e4243f13SShawn Guo } 531e4243f13SShawn Guo 532e4243f13SShawn Guo static void mxs_mmc_start_cmd(struct mxs_mmc_host *host, 533e4243f13SShawn Guo struct mmc_command *cmd) 534e4243f13SShawn Guo { 535e4243f13SShawn Guo host->cmd = cmd; 536e4243f13SShawn Guo 537e4243f13SShawn Guo switch (mmc_cmd_type(cmd)) { 538e4243f13SShawn Guo case MMC_CMD_BC: 539e4243f13SShawn Guo mxs_mmc_bc(host); 540e4243f13SShawn Guo break; 541e4243f13SShawn Guo case MMC_CMD_BCR: 542e4243f13SShawn Guo mxs_mmc_ac(host); 543e4243f13SShawn Guo break; 544e4243f13SShawn Guo case MMC_CMD_AC: 545e4243f13SShawn Guo mxs_mmc_ac(host); 546e4243f13SShawn Guo break; 547e4243f13SShawn Guo case MMC_CMD_ADTC: 548e4243f13SShawn Guo mxs_mmc_adtc(host); 549e4243f13SShawn Guo break; 550e4243f13SShawn Guo default: 551e4243f13SShawn Guo dev_warn(mmc_dev(host->mmc), 552e4243f13SShawn Guo "%s: unknown MMC command\n", __func__); 553e4243f13SShawn Guo break; 554e4243f13SShawn Guo } 555e4243f13SShawn Guo } 556e4243f13SShawn Guo 557e4243f13SShawn Guo static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 558e4243f13SShawn Guo { 559e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 560e4243f13SShawn Guo 561e4243f13SShawn Guo WARN_ON(host->mrq != NULL); 562e4243f13SShawn Guo host->mrq = mrq; 563e4243f13SShawn Guo mxs_mmc_start_cmd(host, mrq->cmd); 564e4243f13SShawn Guo } 565e4243f13SShawn Guo 566e4243f13SShawn Guo static void mxs_mmc_set_clk_rate(struct mxs_mmc_host *host, unsigned int rate) 567e4243f13SShawn Guo { 568d982dcdcSKoen Beel unsigned int ssp_clk, ssp_sck; 569d982dcdcSKoen Beel u32 clock_divide, clock_rate; 570e4243f13SShawn Guo u32 val; 571e4243f13SShawn Guo 572d982dcdcSKoen Beel ssp_clk = clk_get_rate(host->clk); 573e4243f13SShawn Guo 574d982dcdcSKoen Beel for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) { 575d982dcdcSKoen Beel clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide); 576d982dcdcSKoen Beel clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0; 577d982dcdcSKoen Beel if (clock_rate <= 255) 578e4243f13SShawn Guo break; 579e4243f13SShawn Guo } 580e4243f13SShawn Guo 581d982dcdcSKoen Beel if (clock_divide > 254) { 582e4243f13SShawn Guo dev_err(mmc_dev(host->mmc), 583e4243f13SShawn Guo "%s: cannot set clock to %d\n", __func__, rate); 584e4243f13SShawn Guo return; 585e4243f13SShawn Guo } 586e4243f13SShawn Guo 587d982dcdcSKoen Beel ssp_sck = ssp_clk / clock_divide / (1 + clock_rate); 588e4243f13SShawn Guo 589e4243f13SShawn Guo val = readl(host->base + HW_SSP_TIMING); 590e4243f13SShawn Guo val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE); 591d982dcdcSKoen Beel val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE); 592d982dcdcSKoen Beel val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE); 593e4243f13SShawn Guo writel(val, host->base + HW_SSP_TIMING); 594e4243f13SShawn Guo 595d982dcdcSKoen Beel host->clk_rate = ssp_sck; 596e4243f13SShawn Guo 597e4243f13SShawn Guo dev_dbg(mmc_dev(host->mmc), 598d982dcdcSKoen Beel "%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n", 599d982dcdcSKoen Beel __func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate); 600e4243f13SShawn Guo } 601e4243f13SShawn Guo 602e4243f13SShawn Guo static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 603e4243f13SShawn Guo { 604e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 605e4243f13SShawn Guo 606e4243f13SShawn Guo if (ios->bus_width == MMC_BUS_WIDTH_8) 607e4243f13SShawn Guo host->bus_width = 2; 608e4243f13SShawn Guo else if (ios->bus_width == MMC_BUS_WIDTH_4) 609e4243f13SShawn Guo host->bus_width = 1; 610e4243f13SShawn Guo else 611e4243f13SShawn Guo host->bus_width = 0; 612e4243f13SShawn Guo 613e4243f13SShawn Guo if (ios->clock) 614e4243f13SShawn Guo mxs_mmc_set_clk_rate(host, ios->clock); 615e4243f13SShawn Guo } 616e4243f13SShawn Guo 617e4243f13SShawn Guo static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 618e4243f13SShawn Guo { 619e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 620e4243f13SShawn Guo unsigned long flags; 621e4243f13SShawn Guo 622e4243f13SShawn Guo spin_lock_irqsave(&host->lock, flags); 623e4243f13SShawn Guo 624e4243f13SShawn Guo host->sdio_irq_en = enable; 625e4243f13SShawn Guo 626e4243f13SShawn Guo if (enable) { 627e4243f13SShawn Guo writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, 628e4243f13SShawn Guo host->base + HW_SSP_CTRL0 + MXS_SET_ADDR); 629e4243f13SShawn Guo writel(BM_SSP_CTRL1_SDIO_IRQ_EN, 630e4243f13SShawn Guo host->base + HW_SSP_CTRL1 + MXS_SET_ADDR); 631e4243f13SShawn Guo 632e4243f13SShawn Guo if (readl(host->base + HW_SSP_STATUS) & BM_SSP_STATUS_SDIO_IRQ) 633e4243f13SShawn Guo mmc_signal_sdio_irq(host->mmc); 634e4243f13SShawn Guo 635e4243f13SShawn Guo } else { 636e4243f13SShawn Guo writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK, 637e4243f13SShawn Guo host->base + HW_SSP_CTRL0 + MXS_CLR_ADDR); 638e4243f13SShawn Guo writel(BM_SSP_CTRL1_SDIO_IRQ_EN, 639e4243f13SShawn Guo host->base + HW_SSP_CTRL1 + MXS_CLR_ADDR); 640e4243f13SShawn Guo } 641e4243f13SShawn Guo 642e4243f13SShawn Guo spin_unlock_irqrestore(&host->lock, flags); 643e4243f13SShawn Guo } 644e4243f13SShawn Guo 645e4243f13SShawn Guo static const struct mmc_host_ops mxs_mmc_ops = { 646e4243f13SShawn Guo .request = mxs_mmc_request, 647e4243f13SShawn Guo .get_ro = mxs_mmc_get_ro, 648e4243f13SShawn Guo .get_cd = mxs_mmc_get_cd, 649e4243f13SShawn Guo .set_ios = mxs_mmc_set_ios, 650e4243f13SShawn Guo .enable_sdio_irq = mxs_mmc_enable_sdio_irq, 651e4243f13SShawn Guo }; 652e4243f13SShawn Guo 653e4243f13SShawn Guo static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param) 654e4243f13SShawn Guo { 655e4243f13SShawn Guo struct mxs_mmc_host *host = param; 656e4243f13SShawn Guo 657e4243f13SShawn Guo if (!mxs_dma_is_apbh(chan)) 658e4243f13SShawn Guo return false; 659e4243f13SShawn Guo 660e4243f13SShawn Guo if (chan->chan_id != host->dma_res->start) 661e4243f13SShawn Guo return false; 662e4243f13SShawn Guo 663e4243f13SShawn Guo chan->private = &host->dma_data; 664e4243f13SShawn Guo 665e4243f13SShawn Guo return true; 666e4243f13SShawn Guo } 667e4243f13SShawn Guo 668e4243f13SShawn Guo static int mxs_mmc_probe(struct platform_device *pdev) 669e4243f13SShawn Guo { 670e4243f13SShawn Guo struct mxs_mmc_host *host; 671e4243f13SShawn Guo struct mmc_host *mmc; 672e4243f13SShawn Guo struct resource *iores, *dmares, *r; 673e4243f13SShawn Guo struct mxs_mmc_platform_data *pdata; 674e4243f13SShawn Guo int ret = 0, irq_err, irq_dma; 675e4243f13SShawn Guo dma_cap_mask_t mask; 676e4243f13SShawn Guo 677e4243f13SShawn Guo iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 678e4243f13SShawn Guo dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0); 679e4243f13SShawn Guo irq_err = platform_get_irq(pdev, 0); 680e4243f13SShawn Guo irq_dma = platform_get_irq(pdev, 1); 681e4243f13SShawn Guo if (!iores || !dmares || irq_err < 0 || irq_dma < 0) 682e4243f13SShawn Guo return -EINVAL; 683e4243f13SShawn Guo 684e4243f13SShawn Guo r = request_mem_region(iores->start, resource_size(iores), pdev->name); 685e4243f13SShawn Guo if (!r) 686e4243f13SShawn Guo return -EBUSY; 687e4243f13SShawn Guo 688e4243f13SShawn Guo mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev); 689e4243f13SShawn Guo if (!mmc) { 690e4243f13SShawn Guo ret = -ENOMEM; 691e4243f13SShawn Guo goto out_release_mem; 692e4243f13SShawn Guo } 693e4243f13SShawn Guo 694e4243f13SShawn Guo host = mmc_priv(mmc); 695e4243f13SShawn Guo host->base = ioremap(r->start, resource_size(r)); 696e4243f13SShawn Guo if (!host->base) { 697e4243f13SShawn Guo ret = -ENOMEM; 698e4243f13SShawn Guo goto out_mmc_free; 699e4243f13SShawn Guo } 700e4243f13SShawn Guo 701e4243f13SShawn Guo /* only major verion does matter */ 702e4243f13SShawn Guo host->version = readl(host->base + HW_SSP_VERSION) >> 703e4243f13SShawn Guo BP_SSP_VERSION_MAJOR; 704e4243f13SShawn Guo 705e4243f13SShawn Guo host->mmc = mmc; 706e4243f13SShawn Guo host->res = r; 707e4243f13SShawn Guo host->dma_res = dmares; 708e4243f13SShawn Guo host->irq = irq_err; 709e4243f13SShawn Guo host->sdio_irq_en = 0; 710e4243f13SShawn Guo 711e4243f13SShawn Guo host->clk = clk_get(&pdev->dev, NULL); 712e4243f13SShawn Guo if (IS_ERR(host->clk)) { 713e4243f13SShawn Guo ret = PTR_ERR(host->clk); 714e4243f13SShawn Guo goto out_iounmap; 715e4243f13SShawn Guo } 716e4243f13SShawn Guo clk_enable(host->clk); 717e4243f13SShawn Guo 718e4243f13SShawn Guo mxs_mmc_reset(host); 719e4243f13SShawn Guo 720e4243f13SShawn Guo dma_cap_zero(mask); 721e4243f13SShawn Guo dma_cap_set(DMA_SLAVE, mask); 722e4243f13SShawn Guo host->dma_data.chan_irq = irq_dma; 723e4243f13SShawn Guo host->dmach = dma_request_channel(mask, mxs_mmc_dma_filter, host); 724e4243f13SShawn Guo if (!host->dmach) { 725e4243f13SShawn Guo dev_err(mmc_dev(host->mmc), 726e4243f13SShawn Guo "%s: failed to request dma\n", __func__); 727e4243f13SShawn Guo goto out_clk_put; 728e4243f13SShawn Guo } 729e4243f13SShawn Guo 730e4243f13SShawn Guo /* set mmc core parameters */ 731e4243f13SShawn Guo mmc->ops = &mxs_mmc_ops; 732e4243f13SShawn Guo mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 733e4243f13SShawn Guo MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL; 734e4243f13SShawn Guo 735e4243f13SShawn Guo pdata = mmc_dev(host->mmc)->platform_data; 736e4243f13SShawn Guo if (pdata) { 737e4243f13SShawn Guo if (pdata->flags & SLOTF_8_BIT_CAPABLE) 738e4243f13SShawn Guo mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA; 739e4243f13SShawn Guo if (pdata->flags & SLOTF_4_BIT_CAPABLE) 740e4243f13SShawn Guo mmc->caps |= MMC_CAP_4_BIT_DATA; 741e4243f13SShawn Guo } 742e4243f13SShawn Guo 743e4243f13SShawn Guo mmc->f_min = 400000; 744e4243f13SShawn Guo mmc->f_max = 288000000; 745e4243f13SShawn Guo mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 746e4243f13SShawn Guo 747e4243f13SShawn Guo mmc->max_segs = 52; 748e4243f13SShawn Guo mmc->max_blk_size = 1 << 0xf; 749e4243f13SShawn Guo mmc->max_blk_count = (ssp_is_old()) ? 0xff : 0xffffff; 750e4243f13SShawn Guo mmc->max_req_size = (ssp_is_old()) ? 0xffff : 0xffffffff; 751e4243f13SShawn Guo mmc->max_seg_size = dma_get_max_seg_size(host->dmach->device->dev); 752e4243f13SShawn Guo 753e4243f13SShawn Guo platform_set_drvdata(pdev, mmc); 754e4243f13SShawn Guo 755e4243f13SShawn Guo ret = request_irq(host->irq, mxs_mmc_irq_handler, 0, DRIVER_NAME, host); 756e4243f13SShawn Guo if (ret) 757e4243f13SShawn Guo goto out_free_dma; 758e4243f13SShawn Guo 759e4243f13SShawn Guo spin_lock_init(&host->lock); 760e4243f13SShawn Guo 761e4243f13SShawn Guo ret = mmc_add_host(mmc); 762e4243f13SShawn Guo if (ret) 763e4243f13SShawn Guo goto out_free_irq; 764e4243f13SShawn Guo 765e4243f13SShawn Guo dev_info(mmc_dev(host->mmc), "initialized\n"); 766e4243f13SShawn Guo 767e4243f13SShawn Guo return 0; 768e4243f13SShawn Guo 769e4243f13SShawn Guo out_free_irq: 770e4243f13SShawn Guo free_irq(host->irq, host); 771e4243f13SShawn Guo out_free_dma: 772e4243f13SShawn Guo if (host->dmach) 773e4243f13SShawn Guo dma_release_channel(host->dmach); 774e4243f13SShawn Guo out_clk_put: 775e4243f13SShawn Guo clk_disable(host->clk); 776e4243f13SShawn Guo clk_put(host->clk); 777e4243f13SShawn Guo out_iounmap: 778e4243f13SShawn Guo iounmap(host->base); 779e4243f13SShawn Guo out_mmc_free: 780e4243f13SShawn Guo mmc_free_host(mmc); 781e4243f13SShawn Guo out_release_mem: 782e4243f13SShawn Guo release_mem_region(iores->start, resource_size(iores)); 783e4243f13SShawn Guo return ret; 784e4243f13SShawn Guo } 785e4243f13SShawn Guo 786e4243f13SShawn Guo static int mxs_mmc_remove(struct platform_device *pdev) 787e4243f13SShawn Guo { 788e4243f13SShawn Guo struct mmc_host *mmc = platform_get_drvdata(pdev); 789e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 790e4243f13SShawn Guo struct resource *res = host->res; 791e4243f13SShawn Guo 792e4243f13SShawn Guo mmc_remove_host(mmc); 793e4243f13SShawn Guo 794e4243f13SShawn Guo free_irq(host->irq, host); 795e4243f13SShawn Guo 796e4243f13SShawn Guo platform_set_drvdata(pdev, NULL); 797e4243f13SShawn Guo 798e4243f13SShawn Guo if (host->dmach) 799e4243f13SShawn Guo dma_release_channel(host->dmach); 800e4243f13SShawn Guo 801e4243f13SShawn Guo clk_disable(host->clk); 802e4243f13SShawn Guo clk_put(host->clk); 803e4243f13SShawn Guo 804e4243f13SShawn Guo iounmap(host->base); 805e4243f13SShawn Guo 806e4243f13SShawn Guo mmc_free_host(mmc); 807e4243f13SShawn Guo 808e4243f13SShawn Guo release_mem_region(res->start, resource_size(res)); 809e4243f13SShawn Guo 810e4243f13SShawn Guo return 0; 811e4243f13SShawn Guo } 812e4243f13SShawn Guo 813e4243f13SShawn Guo #ifdef CONFIG_PM 814e4243f13SShawn Guo static int mxs_mmc_suspend(struct device *dev) 815e4243f13SShawn Guo { 816e4243f13SShawn Guo struct mmc_host *mmc = dev_get_drvdata(dev); 817e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 818e4243f13SShawn Guo int ret = 0; 819e4243f13SShawn Guo 820e4243f13SShawn Guo ret = mmc_suspend_host(mmc); 821e4243f13SShawn Guo 822e4243f13SShawn Guo clk_disable(host->clk); 823e4243f13SShawn Guo 824e4243f13SShawn Guo return ret; 825e4243f13SShawn Guo } 826e4243f13SShawn Guo 827e4243f13SShawn Guo static int mxs_mmc_resume(struct device *dev) 828e4243f13SShawn Guo { 829e4243f13SShawn Guo struct mmc_host *mmc = dev_get_drvdata(dev); 830e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc); 831e4243f13SShawn Guo int ret = 0; 832e4243f13SShawn Guo 833e4243f13SShawn Guo clk_enable(host->clk); 834e4243f13SShawn Guo 835e4243f13SShawn Guo ret = mmc_resume_host(mmc); 836e4243f13SShawn Guo 837e4243f13SShawn Guo return ret; 838e4243f13SShawn Guo } 839e4243f13SShawn Guo 840e4243f13SShawn Guo static const struct dev_pm_ops mxs_mmc_pm_ops = { 841e4243f13SShawn Guo .suspend = mxs_mmc_suspend, 842e4243f13SShawn Guo .resume = mxs_mmc_resume, 843e4243f13SShawn Guo }; 844e4243f13SShawn Guo #endif 845e4243f13SShawn Guo 846e4243f13SShawn Guo static struct platform_driver mxs_mmc_driver = { 847e4243f13SShawn Guo .probe = mxs_mmc_probe, 848e4243f13SShawn Guo .remove = mxs_mmc_remove, 849e4243f13SShawn Guo .driver = { 850e4243f13SShawn Guo .name = DRIVER_NAME, 851e4243f13SShawn Guo .owner = THIS_MODULE, 852e4243f13SShawn Guo #ifdef CONFIG_PM 853e4243f13SShawn Guo .pm = &mxs_mmc_pm_ops, 854e4243f13SShawn Guo #endif 855e4243f13SShawn Guo }, 856e4243f13SShawn Guo }; 857e4243f13SShawn Guo 858e4243f13SShawn Guo static int __init mxs_mmc_init(void) 859e4243f13SShawn Guo { 860e4243f13SShawn Guo return platform_driver_register(&mxs_mmc_driver); 861e4243f13SShawn Guo } 862e4243f13SShawn Guo 863e4243f13SShawn Guo static void __exit mxs_mmc_exit(void) 864e4243f13SShawn Guo { 865e4243f13SShawn Guo platform_driver_unregister(&mxs_mmc_driver); 866e4243f13SShawn Guo } 867e4243f13SShawn Guo 868e4243f13SShawn Guo module_init(mxs_mmc_init); 869e4243f13SShawn Guo module_exit(mxs_mmc_exit); 870e4243f13SShawn Guo 871e4243f13SShawn Guo MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral"); 872e4243f13SShawn Guo MODULE_AUTHOR("Freescale Semiconductor"); 873e4243f13SShawn Guo MODULE_LICENSE("GPL"); 874