116216333SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
2e4243f13SShawn Guo /*
3e4243f13SShawn Guo * Portions copyright (C) 2003 Russell King, PXA MMCI Driver
4e4243f13SShawn Guo * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
5e4243f13SShawn Guo *
6e4243f13SShawn Guo * Copyright 2008 Embedded Alley Solutions, Inc.
7e4243f13SShawn Guo * Copyright 2009-2011 Freescale Semiconductor, Inc.
8e4243f13SShawn Guo */
9e4243f13SShawn Guo
10e4243f13SShawn Guo #include <linux/kernel.h>
11e4243f13SShawn Guo #include <linux/init.h>
12e4243f13SShawn Guo #include <linux/ioport.h>
136de4d817SShawn Guo #include <linux/of.h>
14e4243f13SShawn Guo #include <linux/platform_device.h>
15e4243f13SShawn Guo #include <linux/delay.h>
16e4243f13SShawn Guo #include <linux/interrupt.h>
17e4243f13SShawn Guo #include <linux/dma-mapping.h>
18e4243f13SShawn Guo #include <linux/dmaengine.h>
192bb9f756SSascha Hauer #include <linux/dma/mxs-dma.h>
20e4243f13SShawn Guo #include <linux/highmem.h>
21e4243f13SShawn Guo #include <linux/clk.h>
22e4243f13SShawn Guo #include <linux/err.h>
23e4243f13SShawn Guo #include <linux/completion.h>
24e4243f13SShawn Guo #include <linux/mmc/host.h>
25e4243f13SShawn Guo #include <linux/mmc/mmc.h>
26e4243f13SShawn Guo #include <linux/mmc/sdio.h>
27abd37cccSSascha Hauer #include <linux/mmc/slot-gpio.h>
28e4243f13SShawn Guo #include <linux/regulator/consumer.h>
2988b47679SPaul Gortmaker #include <linux/module.h>
3070e60206SShawn Guo #include <linux/stmp_device.h>
318be3d3b2SMarek Vasut #include <linux/spi/mxs-spi.h>
32e4243f13SShawn Guo
33e4243f13SShawn Guo #define DRIVER_NAME "mxs-mmc"
34e4243f13SShawn Guo
35e4243f13SShawn Guo #define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \
36e4243f13SShawn Guo BM_SSP_CTRL1_RESP_ERR_IRQ | \
37e4243f13SShawn Guo BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \
38e4243f13SShawn Guo BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \
39e4243f13SShawn Guo BM_SSP_CTRL1_DATA_CRC_IRQ | \
40e4243f13SShawn Guo BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \
41e4243f13SShawn Guo BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \
42e4243f13SShawn Guo BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)
43e4243f13SShawn Guo
448be3d3b2SMarek Vasut /* card detect polling timeout */
458be3d3b2SMarek Vasut #define MXS_MMC_DETECT_TIMEOUT (HZ/2)
46ef9b4d39SShawn Guo
47e4243f13SShawn Guo struct mxs_mmc_host {
48829c1bf4SMarek Vasut struct mxs_ssp ssp;
49829c1bf4SMarek Vasut
50e4243f13SShawn Guo struct mmc_host *mmc;
51e4243f13SShawn Guo struct mmc_request *mrq;
52e4243f13SShawn Guo struct mmc_command *cmd;
53e4243f13SShawn Guo struct mmc_data *data;
54e4243f13SShawn Guo
55e4243f13SShawn Guo unsigned char bus_width;
56e4243f13SShawn Guo spinlock_t lock;
57e4243f13SShawn Guo int sdio_irq_en;
5891769986SDaniel Willmann bool broken_cd;
59e4243f13SShawn Guo };
60e4243f13SShawn Guo
mxs_mmc_get_cd(struct mmc_host * mmc)61e4243f13SShawn Guo static int mxs_mmc_get_cd(struct mmc_host *mmc)
62e4243f13SShawn Guo {
63e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc);
64829c1bf4SMarek Vasut struct mxs_ssp *ssp = &host->ssp;
65d1a1dfb2SSascha Hauer int present, ret;
66d1a1dfb2SSascha Hauer
6791769986SDaniel Willmann if (host->broken_cd)
6891769986SDaniel Willmann return -ENOSYS;
6991769986SDaniel Willmann
70d1a1dfb2SSascha Hauer ret = mmc_gpio_get_cd(mmc);
71d1a1dfb2SSascha Hauer if (ret >= 0)
72d1a1dfb2SSascha Hauer return ret;
73e4243f13SShawn Guo
746f726f49SRoman Peniaev present = mmc->caps & MMC_CAP_NEEDS_POLL ||
756f726f49SRoman Peniaev !(readl(ssp->base + HW_SSP_STATUS(ssp)) &
766c3331d3SSascha Hauer BM_SSP_STATUS_CARD_DETECT);
776c3331d3SSascha Hauer
786c3331d3SSascha Hauer if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH)
796c3331d3SSascha Hauer present = !present;
806c3331d3SSascha Hauer
816c3331d3SSascha Hauer return present;
82e4243f13SShawn Guo }
83e4243f13SShawn Guo
mxs_mmc_reset(struct mxs_mmc_host * host)8402c18c47SFabio Estevam static int mxs_mmc_reset(struct mxs_mmc_host *host)
85e4243f13SShawn Guo {
86829c1bf4SMarek Vasut struct mxs_ssp *ssp = &host->ssp;
87e4243f13SShawn Guo u32 ctrl0, ctrl1;
8802c18c47SFabio Estevam int ret;
89e4243f13SShawn Guo
9002c18c47SFabio Estevam ret = stmp_reset_block(ssp->base);
9102c18c47SFabio Estevam if (ret)
9202c18c47SFabio Estevam return ret;
93e4243f13SShawn Guo
94e4243f13SShawn Guo ctrl0 = BM_SSP_CTRL0_IGNORE_CRC;
95e4243f13SShawn Guo ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) |
96e4243f13SShawn Guo BF_SSP(0x7, CTRL1_WORD_LENGTH) |
97e4243f13SShawn Guo BM_SSP_CTRL1_DMA_ENABLE |
98e4243f13SShawn Guo BM_SSP_CTRL1_POLARITY |
99e4243f13SShawn Guo BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
100e4243f13SShawn Guo BM_SSP_CTRL1_DATA_CRC_IRQ_EN |
101e4243f13SShawn Guo BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
102e4243f13SShawn Guo BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
103e4243f13SShawn Guo BM_SSP_CTRL1_RESP_ERR_IRQ_EN;
104e4243f13SShawn Guo
105e4243f13SShawn Guo writel(BF_SSP(0xffff, TIMING_TIMEOUT) |
106e4243f13SShawn Guo BF_SSP(2, TIMING_CLOCK_DIVIDE) |
107e4243f13SShawn Guo BF_SSP(0, TIMING_CLOCK_RATE),
108829c1bf4SMarek Vasut ssp->base + HW_SSP_TIMING(ssp));
109e4243f13SShawn Guo
110e4243f13SShawn Guo if (host->sdio_irq_en) {
111e4243f13SShawn Guo ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
112e4243f13SShawn Guo ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN;
113e4243f13SShawn Guo }
114e4243f13SShawn Guo
115829c1bf4SMarek Vasut writel(ctrl0, ssp->base + HW_SSP_CTRL0);
116829c1bf4SMarek Vasut writel(ctrl1, ssp->base + HW_SSP_CTRL1(ssp));
11702c18c47SFabio Estevam return 0;
118e4243f13SShawn Guo }
119e4243f13SShawn Guo
120e4243f13SShawn Guo static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
121e4243f13SShawn Guo struct mmc_command *cmd);
122e4243f13SShawn Guo
mxs_mmc_request_done(struct mxs_mmc_host * host)123e4243f13SShawn Guo static void mxs_mmc_request_done(struct mxs_mmc_host *host)
124e4243f13SShawn Guo {
125e4243f13SShawn Guo struct mmc_command *cmd = host->cmd;
126e4243f13SShawn Guo struct mmc_data *data = host->data;
127e4243f13SShawn Guo struct mmc_request *mrq = host->mrq;
128829c1bf4SMarek Vasut struct mxs_ssp *ssp = &host->ssp;
129e4243f13SShawn Guo
130e4243f13SShawn Guo if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) {
131e4243f13SShawn Guo if (mmc_resp_type(cmd) & MMC_RSP_136) {
132829c1bf4SMarek Vasut cmd->resp[3] = readl(ssp->base + HW_SSP_SDRESP0(ssp));
133829c1bf4SMarek Vasut cmd->resp[2] = readl(ssp->base + HW_SSP_SDRESP1(ssp));
134829c1bf4SMarek Vasut cmd->resp[1] = readl(ssp->base + HW_SSP_SDRESP2(ssp));
135829c1bf4SMarek Vasut cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP3(ssp));
136e4243f13SShawn Guo } else {
137829c1bf4SMarek Vasut cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP0(ssp));
138e4243f13SShawn Guo }
139e4243f13SShawn Guo }
140e4243f13SShawn Guo
14173a85069SStefan Wahren if (cmd == mrq->sbc) {
14273a85069SStefan Wahren /* Finished CMD23, now send actual command. */
14373a85069SStefan Wahren mxs_mmc_start_cmd(host, mrq->cmd);
14473a85069SStefan Wahren return;
14573a85069SStefan Wahren } else if (data) {
146e4243f13SShawn Guo dma_unmap_sg(mmc_dev(host->mmc), data->sg,
14765defb9bSMarek Vasut data->sg_len, ssp->dma_dir);
148e4243f13SShawn Guo /*
149e4243f13SShawn Guo * If there was an error on any block, we mark all
150e4243f13SShawn Guo * data blocks as being in error.
151e4243f13SShawn Guo */
152e4243f13SShawn Guo if (!data->error)
153e4243f13SShawn Guo data->bytes_xfered = data->blocks * data->blksz;
154e4243f13SShawn Guo else
155e4243f13SShawn Guo data->bytes_xfered = 0;
156e4243f13SShawn Guo
157e4243f13SShawn Guo host->data = NULL;
15873a85069SStefan Wahren if (data->stop && (data->error || !mrq->sbc)) {
159e4243f13SShawn Guo mxs_mmc_start_cmd(host, mrq->stop);
160e4243f13SShawn Guo return;
161e4243f13SShawn Guo }
162e4243f13SShawn Guo }
163e4243f13SShawn Guo
164e4243f13SShawn Guo host->mrq = NULL;
165e4243f13SShawn Guo mmc_request_done(host->mmc, mrq);
166e4243f13SShawn Guo }
167e4243f13SShawn Guo
mxs_mmc_dma_irq_callback(void * param)168e4243f13SShawn Guo static void mxs_mmc_dma_irq_callback(void *param)
169e4243f13SShawn Guo {
170e4243f13SShawn Guo struct mxs_mmc_host *host = param;
171e4243f13SShawn Guo
172e4243f13SShawn Guo mxs_mmc_request_done(host);
173e4243f13SShawn Guo }
174e4243f13SShawn Guo
mxs_mmc_irq_handler(int irq,void * dev_id)175e4243f13SShawn Guo static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id)
176e4243f13SShawn Guo {
177e4243f13SShawn Guo struct mxs_mmc_host *host = dev_id;
178e4243f13SShawn Guo struct mmc_command *cmd = host->cmd;
179e4243f13SShawn Guo struct mmc_data *data = host->data;
180829c1bf4SMarek Vasut struct mxs_ssp *ssp = &host->ssp;
181e4243f13SShawn Guo u32 stat;
182e4243f13SShawn Guo
183e4243f13SShawn Guo spin_lock(&host->lock);
184e4243f13SShawn Guo
185829c1bf4SMarek Vasut stat = readl(ssp->base + HW_SSP_CTRL1(ssp));
186e4243f13SShawn Guo writel(stat & MXS_MMC_IRQ_BITS,
187829c1bf4SMarek Vasut ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR);
188e4243f13SShawn Guo
1891af36b2aSLauri Hintsala spin_unlock(&host->lock);
1901af36b2aSLauri Hintsala
191e4243f13SShawn Guo if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN))
192e4243f13SShawn Guo mmc_signal_sdio_irq(host->mmc);
193e4243f13SShawn Guo
194e4243f13SShawn Guo if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ)
195e4243f13SShawn Guo cmd->error = -ETIMEDOUT;
196e4243f13SShawn Guo else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ)
197e4243f13SShawn Guo cmd->error = -EIO;
198e4243f13SShawn Guo
199e4243f13SShawn Guo if (data) {
200e4243f13SShawn Guo if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ |
201e4243f13SShawn Guo BM_SSP_CTRL1_RECV_TIMEOUT_IRQ))
202e4243f13SShawn Guo data->error = -ETIMEDOUT;
203e4243f13SShawn Guo else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ)
204e4243f13SShawn Guo data->error = -EILSEQ;
205e4243f13SShawn Guo else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ |
206e4243f13SShawn Guo BM_SSP_CTRL1_FIFO_OVERRUN_IRQ))
207e4243f13SShawn Guo data->error = -EIO;
208e4243f13SShawn Guo }
209e4243f13SShawn Guo
210e4243f13SShawn Guo return IRQ_HANDLED;
211e4243f13SShawn Guo }
212e4243f13SShawn Guo
mxs_mmc_prep_dma(struct mxs_mmc_host * host,unsigned long flags)213e4243f13SShawn Guo static struct dma_async_tx_descriptor *mxs_mmc_prep_dma(
214921de864SHuang Shijie struct mxs_mmc_host *host, unsigned long flags)
215e4243f13SShawn Guo {
21665defb9bSMarek Vasut struct mxs_ssp *ssp = &host->ssp;
217e4243f13SShawn Guo struct dma_async_tx_descriptor *desc;
218e4243f13SShawn Guo struct mmc_data *data = host->data;
219e4243f13SShawn Guo struct scatterlist * sgl;
220e4243f13SShawn Guo unsigned int sg_len;
221e4243f13SShawn Guo
222e4243f13SShawn Guo if (data) {
223e4243f13SShawn Guo /* data */
224e4243f13SShawn Guo dma_map_sg(mmc_dev(host->mmc), data->sg,
22565defb9bSMarek Vasut data->sg_len, ssp->dma_dir);
226e4243f13SShawn Guo sgl = data->sg;
227e4243f13SShawn Guo sg_len = data->sg_len;
228e4243f13SShawn Guo } else {
229e4243f13SShawn Guo /* pio */
23065defb9bSMarek Vasut sgl = (struct scatterlist *) ssp->ssp_pio_words;
231e4243f13SShawn Guo sg_len = SSP_PIO_NUM;
232e4243f13SShawn Guo }
233e4243f13SShawn Guo
23465defb9bSMarek Vasut desc = dmaengine_prep_slave_sg(ssp->dmach,
23565defb9bSMarek Vasut sgl, sg_len, ssp->slave_dirn, flags);
236e4243f13SShawn Guo if (desc) {
237e4243f13SShawn Guo desc->callback = mxs_mmc_dma_irq_callback;
238e4243f13SShawn Guo desc->callback_param = host;
239e4243f13SShawn Guo } else {
240e4243f13SShawn Guo if (data)
241e4243f13SShawn Guo dma_unmap_sg(mmc_dev(host->mmc), data->sg,
24265defb9bSMarek Vasut data->sg_len, ssp->dma_dir);
243e4243f13SShawn Guo }
244e4243f13SShawn Guo
245e4243f13SShawn Guo return desc;
246e4243f13SShawn Guo }
247e4243f13SShawn Guo
mxs_mmc_bc(struct mxs_mmc_host * host)248e4243f13SShawn Guo static void mxs_mmc_bc(struct mxs_mmc_host *host)
249e4243f13SShawn Guo {
25065defb9bSMarek Vasut struct mxs_ssp *ssp = &host->ssp;
251e4243f13SShawn Guo struct mmc_command *cmd = host->cmd;
252e4243f13SShawn Guo struct dma_async_tx_descriptor *desc;
253e4243f13SShawn Guo u32 ctrl0, cmd0, cmd1;
254e4243f13SShawn Guo
255e4243f13SShawn Guo ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC;
256e4243f13SShawn Guo cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC;
257e4243f13SShawn Guo cmd1 = cmd->arg;
258e4243f13SShawn Guo
259e4243f13SShawn Guo if (host->sdio_irq_en) {
260e4243f13SShawn Guo ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
261e4243f13SShawn Guo cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
262e4243f13SShawn Guo }
263e4243f13SShawn Guo
26465defb9bSMarek Vasut ssp->ssp_pio_words[0] = ctrl0;
26565defb9bSMarek Vasut ssp->ssp_pio_words[1] = cmd0;
26665defb9bSMarek Vasut ssp->ssp_pio_words[2] = cmd1;
26765defb9bSMarek Vasut ssp->dma_dir = DMA_NONE;
26865defb9bSMarek Vasut ssp->slave_dirn = DMA_TRANS_NONE;
2692bb9f756SSascha Hauer desc = mxs_mmc_prep_dma(host, MXS_DMA_CTRL_WAIT4END);
270e4243f13SShawn Guo if (!desc)
271e4243f13SShawn Guo goto out;
272e4243f13SShawn Guo
273e4243f13SShawn Guo dmaengine_submit(desc);
27465defb9bSMarek Vasut dma_async_issue_pending(ssp->dmach);
275e4243f13SShawn Guo return;
276e4243f13SShawn Guo
277e4243f13SShawn Guo out:
278e4243f13SShawn Guo dev_warn(mmc_dev(host->mmc),
279e4243f13SShawn Guo "%s: failed to prep dma\n", __func__);
280e4243f13SShawn Guo }
281e4243f13SShawn Guo
mxs_mmc_ac(struct mxs_mmc_host * host)282e4243f13SShawn Guo static void mxs_mmc_ac(struct mxs_mmc_host *host)
283e4243f13SShawn Guo {
28465defb9bSMarek Vasut struct mxs_ssp *ssp = &host->ssp;
285e4243f13SShawn Guo struct mmc_command *cmd = host->cmd;
286e4243f13SShawn Guo struct dma_async_tx_descriptor *desc;
287e4243f13SShawn Guo u32 ignore_crc, get_resp, long_resp;
288e4243f13SShawn Guo u32 ctrl0, cmd0, cmd1;
289e4243f13SShawn Guo
290e4243f13SShawn Guo ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
291e4243f13SShawn Guo 0 : BM_SSP_CTRL0_IGNORE_CRC;
292e4243f13SShawn Guo get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
293e4243f13SShawn Guo BM_SSP_CTRL0_GET_RESP : 0;
294e4243f13SShawn Guo long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
295e4243f13SShawn Guo BM_SSP_CTRL0_LONG_RESP : 0;
296e4243f13SShawn Guo
297e4243f13SShawn Guo ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp;
298e4243f13SShawn Guo cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
299e4243f13SShawn Guo cmd1 = cmd->arg;
300e4243f13SShawn Guo
30101167c7bSStefan Wahren if (cmd->opcode == MMC_STOP_TRANSMISSION)
30201167c7bSStefan Wahren cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
30301167c7bSStefan Wahren
304e4243f13SShawn Guo if (host->sdio_irq_en) {
305e4243f13SShawn Guo ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
306e4243f13SShawn Guo cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
307e4243f13SShawn Guo }
308e4243f13SShawn Guo
30965defb9bSMarek Vasut ssp->ssp_pio_words[0] = ctrl0;
31065defb9bSMarek Vasut ssp->ssp_pio_words[1] = cmd0;
31165defb9bSMarek Vasut ssp->ssp_pio_words[2] = cmd1;
31265defb9bSMarek Vasut ssp->dma_dir = DMA_NONE;
31365defb9bSMarek Vasut ssp->slave_dirn = DMA_TRANS_NONE;
3142bb9f756SSascha Hauer desc = mxs_mmc_prep_dma(host, MXS_DMA_CTRL_WAIT4END);
315e4243f13SShawn Guo if (!desc)
316e4243f13SShawn Guo goto out;
317e4243f13SShawn Guo
318e4243f13SShawn Guo dmaengine_submit(desc);
31965defb9bSMarek Vasut dma_async_issue_pending(ssp->dmach);
320e4243f13SShawn Guo return;
321e4243f13SShawn Guo
322e4243f13SShawn Guo out:
323e4243f13SShawn Guo dev_warn(mmc_dev(host->mmc),
324e4243f13SShawn Guo "%s: failed to prep dma\n", __func__);
325e4243f13SShawn Guo }
326e4243f13SShawn Guo
mxs_ns_to_ssp_ticks(unsigned clock_rate,unsigned ns)327e4243f13SShawn Guo static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns)
328e4243f13SShawn Guo {
329e4243f13SShawn Guo const unsigned int ssp_timeout_mul = 4096;
330e4243f13SShawn Guo /*
331e4243f13SShawn Guo * Calculate ticks in ms since ns are large numbers
332e4243f13SShawn Guo * and might overflow
333e4243f13SShawn Guo */
334e4243f13SShawn Guo const unsigned int clock_per_ms = clock_rate / 1000;
335e4243f13SShawn Guo const unsigned int ms = ns / 1000;
336e4243f13SShawn Guo const unsigned int ticks = ms * clock_per_ms;
337e4243f13SShawn Guo const unsigned int ssp_ticks = ticks / ssp_timeout_mul;
338e4243f13SShawn Guo
339e4243f13SShawn Guo WARN_ON(ssp_ticks == 0);
340e4243f13SShawn Guo return ssp_ticks;
341e4243f13SShawn Guo }
342e4243f13SShawn Guo
mxs_mmc_adtc(struct mxs_mmc_host * host)343e4243f13SShawn Guo static void mxs_mmc_adtc(struct mxs_mmc_host *host)
344e4243f13SShawn Guo {
345e4243f13SShawn Guo struct mmc_command *cmd = host->cmd;
346e4243f13SShawn Guo struct mmc_data *data = cmd->data;
347e4243f13SShawn Guo struct dma_async_tx_descriptor *desc;
348e4243f13SShawn Guo struct scatterlist *sgl = data->sg, *sg;
349e4243f13SShawn Guo unsigned int sg_len = data->sg_len;
350fd63ac76SFabio Estevam unsigned int i;
351e4243f13SShawn Guo
352e4243f13SShawn Guo unsigned short dma_data_dir, timeout;
35305f5799cSVinod Koul enum dma_transfer_direction slave_dirn;
354e4243f13SShawn Guo unsigned int data_size = 0, log2_blksz;
355e4243f13SShawn Guo unsigned int blocks = data->blocks;
356e4243f13SShawn Guo
357829c1bf4SMarek Vasut struct mxs_ssp *ssp = &host->ssp;
358829c1bf4SMarek Vasut
359e4243f13SShawn Guo u32 ignore_crc, get_resp, long_resp, read;
360e4243f13SShawn Guo u32 ctrl0, cmd0, cmd1, val;
361e4243f13SShawn Guo
362e4243f13SShawn Guo ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
363e4243f13SShawn Guo 0 : BM_SSP_CTRL0_IGNORE_CRC;
364e4243f13SShawn Guo get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
365e4243f13SShawn Guo BM_SSP_CTRL0_GET_RESP : 0;
366e4243f13SShawn Guo long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
367e4243f13SShawn Guo BM_SSP_CTRL0_LONG_RESP : 0;
368e4243f13SShawn Guo
369e4243f13SShawn Guo if (data->flags & MMC_DATA_WRITE) {
370e4243f13SShawn Guo dma_data_dir = DMA_TO_DEVICE;
37105f5799cSVinod Koul slave_dirn = DMA_MEM_TO_DEV;
372e4243f13SShawn Guo read = 0;
373e4243f13SShawn Guo } else {
374e4243f13SShawn Guo dma_data_dir = DMA_FROM_DEVICE;
37505f5799cSVinod Koul slave_dirn = DMA_DEV_TO_MEM;
376e4243f13SShawn Guo read = BM_SSP_CTRL0_READ;
377e4243f13SShawn Guo }
378e4243f13SShawn Guo
379e4243f13SShawn Guo ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) |
380e4243f13SShawn Guo ignore_crc | get_resp | long_resp |
381e4243f13SShawn Guo BM_SSP_CTRL0_DATA_XFER | read |
382e4243f13SShawn Guo BM_SSP_CTRL0_WAIT_FOR_IRQ |
383e4243f13SShawn Guo BM_SSP_CTRL0_ENABLE;
384e4243f13SShawn Guo
385e4243f13SShawn Guo cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
386e4243f13SShawn Guo
387e4243f13SShawn Guo /* get logarithm to base 2 of block size for setting register */
388e4243f13SShawn Guo log2_blksz = ilog2(data->blksz);
389e4243f13SShawn Guo
390e4243f13SShawn Guo /*
391e4243f13SShawn Guo * take special care of the case that data size from data->sg
392e4243f13SShawn Guo * is not equal to blocks x blksz
393e4243f13SShawn Guo */
394e4243f13SShawn Guo for_each_sg(sgl, sg, sg_len, i)
395e4243f13SShawn Guo data_size += sg->length;
396e4243f13SShawn Guo
397e4243f13SShawn Guo if (data_size != data->blocks * data->blksz)
398e4243f13SShawn Guo blocks = 1;
399e4243f13SShawn Guo
400e4243f13SShawn Guo /* xfer count, block size and count need to be set differently */
401829c1bf4SMarek Vasut if (ssp_is_old(ssp)) {
402e4243f13SShawn Guo ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT);
403e4243f13SShawn Guo cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) |
404e4243f13SShawn Guo BF_SSP(blocks - 1, CMD0_BLOCK_COUNT);
405e4243f13SShawn Guo } else {
406829c1bf4SMarek Vasut writel(data_size, ssp->base + HW_SSP_XFER_SIZE);
407e4243f13SShawn Guo writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) |
408e4243f13SShawn Guo BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT),
409829c1bf4SMarek Vasut ssp->base + HW_SSP_BLOCK_SIZE);
410e4243f13SShawn Guo }
411e4243f13SShawn Guo
41201167c7bSStefan Wahren if (cmd->opcode == SD_IO_RW_EXTENDED)
413e4243f13SShawn Guo cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
414e4243f13SShawn Guo
415e4243f13SShawn Guo cmd1 = cmd->arg;
416e4243f13SShawn Guo
417e4243f13SShawn Guo if (host->sdio_irq_en) {
418e4243f13SShawn Guo ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
419e4243f13SShawn Guo cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
420e4243f13SShawn Guo }
421e4243f13SShawn Guo
422e4243f13SShawn Guo /* set the timeout count */
423829c1bf4SMarek Vasut timeout = mxs_ns_to_ssp_ticks(ssp->clk_rate, data->timeout_ns);
424829c1bf4SMarek Vasut val = readl(ssp->base + HW_SSP_TIMING(ssp));
425e4243f13SShawn Guo val &= ~(BM_SSP_TIMING_TIMEOUT);
426e4243f13SShawn Guo val |= BF_SSP(timeout, TIMING_TIMEOUT);
427829c1bf4SMarek Vasut writel(val, ssp->base + HW_SSP_TIMING(ssp));
428e4243f13SShawn Guo
429e4243f13SShawn Guo /* pio */
43065defb9bSMarek Vasut ssp->ssp_pio_words[0] = ctrl0;
43165defb9bSMarek Vasut ssp->ssp_pio_words[1] = cmd0;
43265defb9bSMarek Vasut ssp->ssp_pio_words[2] = cmd1;
43365defb9bSMarek Vasut ssp->dma_dir = DMA_NONE;
43465defb9bSMarek Vasut ssp->slave_dirn = DMA_TRANS_NONE;
435e4243f13SShawn Guo desc = mxs_mmc_prep_dma(host, 0);
436e4243f13SShawn Guo if (!desc)
437e4243f13SShawn Guo goto out;
438e4243f13SShawn Guo
439e4243f13SShawn Guo /* append data sg */
440e4243f13SShawn Guo WARN_ON(host->data != NULL);
441e4243f13SShawn Guo host->data = data;
44265defb9bSMarek Vasut ssp->dma_dir = dma_data_dir;
44365defb9bSMarek Vasut ssp->slave_dirn = slave_dirn;
4442bb9f756SSascha Hauer desc = mxs_mmc_prep_dma(host, DMA_PREP_INTERRUPT | MXS_DMA_CTRL_WAIT4END);
445e4243f13SShawn Guo if (!desc)
446e4243f13SShawn Guo goto out;
447e4243f13SShawn Guo
448e4243f13SShawn Guo dmaengine_submit(desc);
44965defb9bSMarek Vasut dma_async_issue_pending(ssp->dmach);
450e4243f13SShawn Guo return;
451e4243f13SShawn Guo out:
452e4243f13SShawn Guo dev_warn(mmc_dev(host->mmc),
453e4243f13SShawn Guo "%s: failed to prep dma\n", __func__);
454e4243f13SShawn Guo }
455e4243f13SShawn Guo
mxs_mmc_start_cmd(struct mxs_mmc_host * host,struct mmc_command * cmd)456e4243f13SShawn Guo static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
457e4243f13SShawn Guo struct mmc_command *cmd)
458e4243f13SShawn Guo {
459e4243f13SShawn Guo host->cmd = cmd;
460e4243f13SShawn Guo
461e4243f13SShawn Guo switch (mmc_cmd_type(cmd)) {
462e4243f13SShawn Guo case MMC_CMD_BC:
463e4243f13SShawn Guo mxs_mmc_bc(host);
464e4243f13SShawn Guo break;
465e4243f13SShawn Guo case MMC_CMD_BCR:
466e4243f13SShawn Guo mxs_mmc_ac(host);
467e4243f13SShawn Guo break;
468e4243f13SShawn Guo case MMC_CMD_AC:
469e4243f13SShawn Guo mxs_mmc_ac(host);
470e4243f13SShawn Guo break;
471e4243f13SShawn Guo case MMC_CMD_ADTC:
472e4243f13SShawn Guo mxs_mmc_adtc(host);
473e4243f13SShawn Guo break;
474e4243f13SShawn Guo default:
475e4243f13SShawn Guo dev_warn(mmc_dev(host->mmc),
476e4243f13SShawn Guo "%s: unknown MMC command\n", __func__);
477e4243f13SShawn Guo break;
478e4243f13SShawn Guo }
479e4243f13SShawn Guo }
480e4243f13SShawn Guo
mxs_mmc_request(struct mmc_host * mmc,struct mmc_request * mrq)481e4243f13SShawn Guo static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
482e4243f13SShawn Guo {
483e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc);
484e4243f13SShawn Guo
485e4243f13SShawn Guo WARN_ON(host->mrq != NULL);
486e4243f13SShawn Guo host->mrq = mrq;
48773a85069SStefan Wahren
48873a85069SStefan Wahren if (mrq->sbc)
48973a85069SStefan Wahren mxs_mmc_start_cmd(host, mrq->sbc);
49073a85069SStefan Wahren else
491e4243f13SShawn Guo mxs_mmc_start_cmd(host, mrq->cmd);
492e4243f13SShawn Guo }
493e4243f13SShawn Guo
mxs_mmc_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)494e4243f13SShawn Guo static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
495e4243f13SShawn Guo {
496e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc);
497e4243f13SShawn Guo
498e4243f13SShawn Guo if (ios->bus_width == MMC_BUS_WIDTH_8)
499e4243f13SShawn Guo host->bus_width = 2;
500e4243f13SShawn Guo else if (ios->bus_width == MMC_BUS_WIDTH_4)
501e4243f13SShawn Guo host->bus_width = 1;
502e4243f13SShawn Guo else
503e4243f13SShawn Guo host->bus_width = 0;
504e4243f13SShawn Guo
505e4243f13SShawn Guo if (ios->clock)
50613082398SMarek Vasut mxs_ssp_set_clk_rate(&host->ssp, ios->clock);
507e4243f13SShawn Guo }
508e4243f13SShawn Guo
mxs_mmc_enable_sdio_irq(struct mmc_host * mmc,int enable)509e4243f13SShawn Guo static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
510e4243f13SShawn Guo {
511e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc);
512829c1bf4SMarek Vasut struct mxs_ssp *ssp = &host->ssp;
513e4243f13SShawn Guo unsigned long flags;
514e4243f13SShawn Guo
515e4243f13SShawn Guo spin_lock_irqsave(&host->lock, flags);
516e4243f13SShawn Guo
517e4243f13SShawn Guo host->sdio_irq_en = enable;
518e4243f13SShawn Guo
519e4243f13SShawn Guo if (enable) {
520e4243f13SShawn Guo writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
521829c1bf4SMarek Vasut ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
522e4243f13SShawn Guo writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
5234c5bb2e4SMarek Vasut ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_SET);
524e4243f13SShawn Guo } else {
525e4243f13SShawn Guo writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
526829c1bf4SMarek Vasut ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
527e4243f13SShawn Guo writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
528829c1bf4SMarek Vasut ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR);
529e4243f13SShawn Guo }
530e4243f13SShawn Guo
531e4243f13SShawn Guo spin_unlock_irqrestore(&host->lock, flags);
532fc108d24SLauri Hintsala
533ac48f6cbSMark Brown if (enable && readl(ssp->base + HW_SSP_STATUS(ssp)) &
534fc108d24SLauri Hintsala BM_SSP_STATUS_SDIO_IRQ)
535fc108d24SLauri Hintsala mmc_signal_sdio_irq(host->mmc);
536fc108d24SLauri Hintsala
537e4243f13SShawn Guo }
538e4243f13SShawn Guo
539e4243f13SShawn Guo static const struct mmc_host_ops mxs_mmc_ops = {
540e4243f13SShawn Guo .request = mxs_mmc_request,
541abd37cccSSascha Hauer .get_ro = mmc_gpio_get_ro,
542e4243f13SShawn Guo .get_cd = mxs_mmc_get_cd,
543e4243f13SShawn Guo .set_ios = mxs_mmc_set_ios,
544e4243f13SShawn Guo .enable_sdio_irq = mxs_mmc_enable_sdio_irq,
545e4243f13SShawn Guo };
546e4243f13SShawn Guo
5476de4d817SShawn Guo static const struct of_device_id mxs_mmc_dt_ids[] = {
548600a991fSMarek Vasut { .compatible = "fsl,imx23-mmc", .data = (void *) IMX23_SSP, },
549600a991fSMarek Vasut { .compatible = "fsl,imx28-mmc", .data = (void *) IMX28_SSP, },
5506de4d817SShawn Guo { /* sentinel */ }
5516de4d817SShawn Guo };
5526de4d817SShawn Guo MODULE_DEVICE_TABLE(of, mxs_mmc_dt_ids);
5536de4d817SShawn Guo
mxs_mmc_regulator_disable(void * regulator)554ce5f6c2cSChristophe JAILLET static void mxs_mmc_regulator_disable(void *regulator)
555ce5f6c2cSChristophe JAILLET {
556ce5f6c2cSChristophe JAILLET regulator_disable(regulator);
557ce5f6c2cSChristophe JAILLET }
558ce5f6c2cSChristophe JAILLET
mxs_mmc_probe(struct platform_device * pdev)559e4243f13SShawn Guo static int mxs_mmc_probe(struct platform_device *pdev)
560e4243f13SShawn Guo {
56191769986SDaniel Willmann struct device_node *np = pdev->dev.of_node;
562e4243f13SShawn Guo struct mxs_mmc_host *host;
563e4243f13SShawn Guo struct mmc_host *mmc;
564d1a1dfb2SSascha Hauer int ret = 0, irq_err;
5654dc5a79fSShawn Guo struct regulator *reg_vmmc;
566829c1bf4SMarek Vasut struct mxs_ssp *ssp;
567e4243f13SShawn Guo
568e4243f13SShawn Guo irq_err = platform_get_irq(pdev, 0);
569c3cd5c07SFabio Estevam if (irq_err < 0)
5705654d900SFabio Estevam return irq_err;
571e4243f13SShawn Guo
572e4243f13SShawn Guo mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev);
573df06bfc7SShawn Guo if (!mmc)
574df06bfc7SShawn Guo return -ENOMEM;
575e4243f13SShawn Guo
576e4243f13SShawn Guo host = mmc_priv(mmc);
577829c1bf4SMarek Vasut ssp = &host->ssp;
578829c1bf4SMarek Vasut ssp->dev = &pdev->dev;
57959532dbbSAnson Huang ssp->base = devm_platform_ioremap_resource(pdev, 0);
580a3e2cd7fSThierry Reding if (IS_ERR(ssp->base)) {
581a3e2cd7fSThierry Reding ret = PTR_ERR(ssp->base);
582e4243f13SShawn Guo goto out_mmc_free;
583e4243f13SShawn Guo }
584e4243f13SShawn Guo
585d33b5b68SFabio Estevam ssp->devid = (enum mxs_ssp_id)of_device_get_match_data(&pdev->dev);
5866de4d817SShawn Guo
5876de4d817SShawn Guo host->mmc = mmc;
588e4243f13SShawn Guo host->sdio_irq_en = 0;
589e4243f13SShawn Guo
5904dc5a79fSShawn Guo reg_vmmc = devm_regulator_get(&pdev->dev, "vmmc");
5914dc5a79fSShawn Guo if (!IS_ERR(reg_vmmc)) {
5924dc5a79fSShawn Guo ret = regulator_enable(reg_vmmc);
5934dc5a79fSShawn Guo if (ret) {
5944dc5a79fSShawn Guo dev_err(&pdev->dev,
5954dc5a79fSShawn Guo "Failed to enable vmmc regulator: %d\n", ret);
5964dc5a79fSShawn Guo goto out_mmc_free;
5974dc5a79fSShawn Guo }
598ce5f6c2cSChristophe JAILLET
599ce5f6c2cSChristophe JAILLET ret = devm_add_action_or_reset(&pdev->dev, mxs_mmc_regulator_disable,
600ce5f6c2cSChristophe JAILLET reg_vmmc);
601ce5f6c2cSChristophe JAILLET if (ret)
602ce5f6c2cSChristophe JAILLET goto out_mmc_free;
6034dc5a79fSShawn Guo }
6044dc5a79fSShawn Guo
605a5adbffdSFabio Estevam ssp->clk = devm_clk_get(&pdev->dev, NULL);
606829c1bf4SMarek Vasut if (IS_ERR(ssp->clk)) {
607829c1bf4SMarek Vasut ret = PTR_ERR(ssp->clk);
608df06bfc7SShawn Guo goto out_mmc_free;
609e4243f13SShawn Guo }
610e34d467cSFabio Estevam ret = clk_prepare_enable(ssp->clk);
611e34d467cSFabio Estevam if (ret)
612e34d467cSFabio Estevam goto out_mmc_free;
613e4243f13SShawn Guo
61402c18c47SFabio Estevam ret = mxs_mmc_reset(host);
61502c18c47SFabio Estevam if (ret) {
61602c18c47SFabio Estevam dev_err(&pdev->dev, "Failed to reset mmc: %d\n", ret);
61702c18c47SFabio Estevam goto out_clk_disable;
61802c18c47SFabio Estevam }
619e4243f13SShawn Guo
620972a2dd6SPeter Ujfalusi ssp->dmach = dma_request_chan(&pdev->dev, "rx-tx");
621972a2dd6SPeter Ujfalusi if (IS_ERR(ssp->dmach)) {
622e4243f13SShawn Guo dev_err(mmc_dev(host->mmc),
623e4243f13SShawn Guo "%s: failed to request dma\n", __func__);
624972a2dd6SPeter Ujfalusi ret = PTR_ERR(ssp->dmach);
625a5adbffdSFabio Estevam goto out_clk_disable;
626e4243f13SShawn Guo }
627e4243f13SShawn Guo
628e4243f13SShawn Guo /* set mmc core parameters */
629e4243f13SShawn Guo mmc->ops = &mxs_mmc_ops;
630e4243f13SShawn Guo mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
6311be64c79SUlf Hansson MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL | MMC_CAP_CMD23;
632e4243f13SShawn Guo
63391769986SDaniel Willmann host->broken_cd = of_property_read_bool(np, "broken-cd");
63491769986SDaniel Willmann
635e4243f13SShawn Guo mmc->f_min = 400000;
636e4243f13SShawn Guo mmc->f_max = 288000000;
637d1a1dfb2SSascha Hauer
638d1a1dfb2SSascha Hauer ret = mmc_of_parse(mmc);
639d1a1dfb2SSascha Hauer if (ret)
6400bb7e560SChristophe JAILLET goto out_free_dma;
641d1a1dfb2SSascha Hauer
642e4243f13SShawn Guo mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
643e4243f13SShawn Guo
644e4243f13SShawn Guo mmc->max_segs = 52;
645e4243f13SShawn Guo mmc->max_blk_size = 1 << 0xf;
646829c1bf4SMarek Vasut mmc->max_blk_count = (ssp_is_old(ssp)) ? 0xff : 0xffffff;
647829c1bf4SMarek Vasut mmc->max_req_size = (ssp_is_old(ssp)) ? 0xffff : 0xffffffff;
64865defb9bSMarek Vasut mmc->max_seg_size = dma_get_max_seg_size(ssp->dmach->device->dev);
649e4243f13SShawn Guo
650e4243f13SShawn Guo platform_set_drvdata(pdev, mmc);
651e4243f13SShawn Guo
652f91346e8SFabio Estevam spin_lock_init(&host->lock);
653f91346e8SFabio Estevam
654df06bfc7SShawn Guo ret = devm_request_irq(&pdev->dev, irq_err, mxs_mmc_irq_handler, 0,
655cc87a358SFabio Estevam dev_name(&pdev->dev), host);
656e4243f13SShawn Guo if (ret)
657e4243f13SShawn Guo goto out_free_dma;
658e4243f13SShawn Guo
659e4243f13SShawn Guo ret = mmc_add_host(mmc);
660e4243f13SShawn Guo if (ret)
661df06bfc7SShawn Guo goto out_free_dma;
662e4243f13SShawn Guo
663e4243f13SShawn Guo dev_info(mmc_dev(host->mmc), "initialized\n");
664e4243f13SShawn Guo
665e4243f13SShawn Guo return 0;
666e4243f13SShawn Guo
667e4243f13SShawn Guo out_free_dma:
66865defb9bSMarek Vasut dma_release_channel(ssp->dmach);
669a5adbffdSFabio Estevam out_clk_disable:
670829c1bf4SMarek Vasut clk_disable_unprepare(ssp->clk);
671e4243f13SShawn Guo out_mmc_free:
672e4243f13SShawn Guo mmc_free_host(mmc);
673e4243f13SShawn Guo return ret;
674e4243f13SShawn Guo }
675e4243f13SShawn Guo
mxs_mmc_remove(struct platform_device * pdev)676*3f347f2cSYangtao Li static void mxs_mmc_remove(struct platform_device *pdev)
677e4243f13SShawn Guo {
678e4243f13SShawn Guo struct mmc_host *mmc = platform_get_drvdata(pdev);
679e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc);
680829c1bf4SMarek Vasut struct mxs_ssp *ssp = &host->ssp;
681e4243f13SShawn Guo
682e4243f13SShawn Guo mmc_remove_host(mmc);
683e4243f13SShawn Guo
68465defb9bSMarek Vasut if (ssp->dmach)
68565defb9bSMarek Vasut dma_release_channel(ssp->dmach);
686e4243f13SShawn Guo
687829c1bf4SMarek Vasut clk_disable_unprepare(ssp->clk);
688e4243f13SShawn Guo
689e4243f13SShawn Guo mmc_free_host(mmc);
690e4243f13SShawn Guo }
691e4243f13SShawn Guo
692d1355290SFabio Estevam #ifdef CONFIG_PM_SLEEP
mxs_mmc_suspend(struct device * dev)693e4243f13SShawn Guo static int mxs_mmc_suspend(struct device *dev)
694e4243f13SShawn Guo {
695e4243f13SShawn Guo struct mmc_host *mmc = dev_get_drvdata(dev);
696e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc);
697829c1bf4SMarek Vasut struct mxs_ssp *ssp = &host->ssp;
698e4243f13SShawn Guo
699829c1bf4SMarek Vasut clk_disable_unprepare(ssp->clk);
70068359079SUlf Hansson return 0;
701e4243f13SShawn Guo }
702e4243f13SShawn Guo
mxs_mmc_resume(struct device * dev)703e4243f13SShawn Guo static int mxs_mmc_resume(struct device *dev)
704e4243f13SShawn Guo {
705e4243f13SShawn Guo struct mmc_host *mmc = dev_get_drvdata(dev);
706e4243f13SShawn Guo struct mxs_mmc_host *host = mmc_priv(mmc);
707829c1bf4SMarek Vasut struct mxs_ssp *ssp = &host->ssp;
708e4243f13SShawn Guo
709e34d467cSFabio Estevam return clk_prepare_enable(ssp->clk);
710e4243f13SShawn Guo }
711e4243f13SShawn Guo #endif
712e4243f13SShawn Guo
713d1355290SFabio Estevam static SIMPLE_DEV_PM_OPS(mxs_mmc_pm_ops, mxs_mmc_suspend, mxs_mmc_resume);
714d1355290SFabio Estevam
715e4243f13SShawn Guo static struct platform_driver mxs_mmc_driver = {
716e4243f13SShawn Guo .probe = mxs_mmc_probe,
717*3f347f2cSYangtao Li .remove_new = mxs_mmc_remove,
718e4243f13SShawn Guo .driver = {
719e4243f13SShawn Guo .name = DRIVER_NAME,
72021b2cec6SDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS,
721e4243f13SShawn Guo .pm = &mxs_mmc_pm_ops,
722a3e545e9SMarek Vasut .of_match_table = mxs_mmc_dt_ids,
723e4243f13SShawn Guo },
724e4243f13SShawn Guo };
725e4243f13SShawn Guo
726d1f81a64SAxel Lin module_platform_driver(mxs_mmc_driver);
727e4243f13SShawn Guo
728e4243f13SShawn Guo MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral");
729e4243f13SShawn Guo MODULE_AUTHOR("Freescale Semiconductor");
730e4243f13SShawn Guo MODULE_LICENSE("GPL");
731e7be434aSFabio Estevam MODULE_ALIAS("platform:" DRIVER_NAME);
732