1 /* 2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver 3 * 4 * This is a driver for the SDHC controller found in Freescale MX2/MX3 5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c). 6 * Unlike the hardware found on MX1, this hardware just works and does 7 * not need all the quirks found in imxmmc.c, hence the separate driver. 8 * 9 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> 10 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com> 11 * 12 * derived from pxamci.c by Russell King 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 * 18 */ 19 20 #include <linux/module.h> 21 #include <linux/init.h> 22 #include <linux/ioport.h> 23 #include <linux/platform_device.h> 24 #include <linux/interrupt.h> 25 #include <linux/irq.h> 26 #include <linux/blkdev.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/mmc/host.h> 29 #include <linux/mmc/card.h> 30 #include <linux/delay.h> 31 #include <linux/clk.h> 32 #include <linux/io.h> 33 #include <linux/gpio.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/dmaengine.h> 36 #include <linux/types.h> 37 #include <linux/of.h> 38 #include <linux/of_device.h> 39 #include <linux/of_dma.h> 40 #include <linux/of_gpio.h> 41 #include <linux/mmc/slot-gpio.h> 42 43 #include <asm/dma.h> 44 #include <asm/irq.h> 45 #include <linux/platform_data/mmc-mxcmmc.h> 46 47 #include <linux/platform_data/dma-imx.h> 48 49 #define DRIVER_NAME "mxc-mmc" 50 #define MXCMCI_TIMEOUT_MS 10000 51 52 #define MMC_REG_STR_STP_CLK 0x00 53 #define MMC_REG_STATUS 0x04 54 #define MMC_REG_CLK_RATE 0x08 55 #define MMC_REG_CMD_DAT_CONT 0x0C 56 #define MMC_REG_RES_TO 0x10 57 #define MMC_REG_READ_TO 0x14 58 #define MMC_REG_BLK_LEN 0x18 59 #define MMC_REG_NOB 0x1C 60 #define MMC_REG_REV_NO 0x20 61 #define MMC_REG_INT_CNTR 0x24 62 #define MMC_REG_CMD 0x28 63 #define MMC_REG_ARG 0x2C 64 #define MMC_REG_RES_FIFO 0x34 65 #define MMC_REG_BUFFER_ACCESS 0x38 66 67 #define STR_STP_CLK_RESET (1 << 3) 68 #define STR_STP_CLK_START_CLK (1 << 1) 69 #define STR_STP_CLK_STOP_CLK (1 << 0) 70 71 #define STATUS_CARD_INSERTION (1 << 31) 72 #define STATUS_CARD_REMOVAL (1 << 30) 73 #define STATUS_YBUF_EMPTY (1 << 29) 74 #define STATUS_XBUF_EMPTY (1 << 28) 75 #define STATUS_YBUF_FULL (1 << 27) 76 #define STATUS_XBUF_FULL (1 << 26) 77 #define STATUS_BUF_UND_RUN (1 << 25) 78 #define STATUS_BUF_OVFL (1 << 24) 79 #define STATUS_SDIO_INT_ACTIVE (1 << 14) 80 #define STATUS_END_CMD_RESP (1 << 13) 81 #define STATUS_WRITE_OP_DONE (1 << 12) 82 #define STATUS_DATA_TRANS_DONE (1 << 11) 83 #define STATUS_READ_OP_DONE (1 << 11) 84 #define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10) 85 #define STATUS_CARD_BUS_CLK_RUN (1 << 8) 86 #define STATUS_BUF_READ_RDY (1 << 7) 87 #define STATUS_BUF_WRITE_RDY (1 << 6) 88 #define STATUS_RESP_CRC_ERR (1 << 5) 89 #define STATUS_CRC_READ_ERR (1 << 3) 90 #define STATUS_CRC_WRITE_ERR (1 << 2) 91 #define STATUS_TIME_OUT_RESP (1 << 1) 92 #define STATUS_TIME_OUT_READ (1 << 0) 93 #define STATUS_ERR_MASK 0x2f 94 95 #define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12) 96 #define CMD_DAT_CONT_STOP_READWAIT (1 << 11) 97 #define CMD_DAT_CONT_START_READWAIT (1 << 10) 98 #define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8) 99 #define CMD_DAT_CONT_INIT (1 << 7) 100 #define CMD_DAT_CONT_WRITE (1 << 4) 101 #define CMD_DAT_CONT_DATA_ENABLE (1 << 3) 102 #define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0) 103 #define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0) 104 #define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0) 105 106 #define INT_SDIO_INT_WKP_EN (1 << 18) 107 #define INT_CARD_INSERTION_WKP_EN (1 << 17) 108 #define INT_CARD_REMOVAL_WKP_EN (1 << 16) 109 #define INT_CARD_INSERTION_EN (1 << 15) 110 #define INT_CARD_REMOVAL_EN (1 << 14) 111 #define INT_SDIO_IRQ_EN (1 << 13) 112 #define INT_DAT0_EN (1 << 12) 113 #define INT_BUF_READ_EN (1 << 4) 114 #define INT_BUF_WRITE_EN (1 << 3) 115 #define INT_END_CMD_RES_EN (1 << 2) 116 #define INT_WRITE_OP_DONE_EN (1 << 1) 117 #define INT_READ_OP_EN (1 << 0) 118 119 enum mxcmci_type { 120 IMX21_MMC, 121 IMX31_MMC, 122 MPC512X_MMC, 123 }; 124 125 struct mxcmci_host { 126 struct mmc_host *mmc; 127 void __iomem *base; 128 dma_addr_t phys_base; 129 int detect_irq; 130 struct dma_chan *dma; 131 struct dma_async_tx_descriptor *desc; 132 int do_dma; 133 int default_irq_mask; 134 int use_sdio; 135 unsigned int power_mode; 136 struct imxmmc_platform_data *pdata; 137 138 struct mmc_request *req; 139 struct mmc_command *cmd; 140 struct mmc_data *data; 141 142 unsigned int datasize; 143 unsigned int dma_dir; 144 145 u16 rev_no; 146 unsigned int cmdat; 147 148 struct clk *clk_ipg; 149 struct clk *clk_per; 150 151 int clock; 152 153 struct work_struct datawork; 154 spinlock_t lock; 155 156 int burstlen; 157 int dmareq; 158 struct dma_slave_config dma_slave_config; 159 struct imx_dma_data dma_data; 160 161 struct timer_list watchdog; 162 enum mxcmci_type devtype; 163 }; 164 165 static const struct platform_device_id mxcmci_devtype[] = { 166 { 167 .name = "imx21-mmc", 168 .driver_data = IMX21_MMC, 169 }, { 170 .name = "imx31-mmc", 171 .driver_data = IMX31_MMC, 172 }, { 173 .name = "mpc512x-sdhc", 174 .driver_data = MPC512X_MMC, 175 }, { 176 /* sentinel */ 177 } 178 }; 179 MODULE_DEVICE_TABLE(platform, mxcmci_devtype); 180 181 static const struct of_device_id mxcmci_of_match[] = { 182 { 183 .compatible = "fsl,imx21-mmc", 184 .data = &mxcmci_devtype[IMX21_MMC], 185 }, { 186 .compatible = "fsl,imx31-mmc", 187 .data = &mxcmci_devtype[IMX31_MMC], 188 }, { 189 .compatible = "fsl,mpc5121-sdhc", 190 .data = &mxcmci_devtype[MPC512X_MMC], 191 }, { 192 /* sentinel */ 193 } 194 }; 195 MODULE_DEVICE_TABLE(of, mxcmci_of_match); 196 197 static inline int is_imx31_mmc(struct mxcmci_host *host) 198 { 199 return host->devtype == IMX31_MMC; 200 } 201 202 static inline int is_mpc512x_mmc(struct mxcmci_host *host) 203 { 204 return host->devtype == MPC512X_MMC; 205 } 206 207 static inline u32 mxcmci_readl(struct mxcmci_host *host, int reg) 208 { 209 if (IS_ENABLED(CONFIG_PPC_MPC512x)) 210 return ioread32be(host->base + reg); 211 else 212 return readl(host->base + reg); 213 } 214 215 static inline void mxcmci_writel(struct mxcmci_host *host, u32 val, int reg) 216 { 217 if (IS_ENABLED(CONFIG_PPC_MPC512x)) 218 iowrite32be(val, host->base + reg); 219 else 220 writel(val, host->base + reg); 221 } 222 223 static inline u16 mxcmci_readw(struct mxcmci_host *host, int reg) 224 { 225 if (IS_ENABLED(CONFIG_PPC_MPC512x)) 226 return ioread32be(host->base + reg); 227 else 228 return readw(host->base + reg); 229 } 230 231 static inline void mxcmci_writew(struct mxcmci_host *host, u16 val, int reg) 232 { 233 if (IS_ENABLED(CONFIG_PPC_MPC512x)) 234 iowrite32be(val, host->base + reg); 235 else 236 writew(val, host->base + reg); 237 } 238 239 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios); 240 241 static void mxcmci_set_power(struct mxcmci_host *host, unsigned int vdd) 242 { 243 if (!IS_ERR(host->mmc->supply.vmmc)) { 244 if (host->power_mode == MMC_POWER_UP) 245 mmc_regulator_set_ocr(host->mmc, 246 host->mmc->supply.vmmc, vdd); 247 else if (host->power_mode == MMC_POWER_OFF) 248 mmc_regulator_set_ocr(host->mmc, 249 host->mmc->supply.vmmc, 0); 250 } 251 252 if (host->pdata && host->pdata->setpower) 253 host->pdata->setpower(mmc_dev(host->mmc), vdd); 254 } 255 256 static inline int mxcmci_use_dma(struct mxcmci_host *host) 257 { 258 return host->do_dma; 259 } 260 261 static void mxcmci_softreset(struct mxcmci_host *host) 262 { 263 int i; 264 265 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n"); 266 267 /* reset sequence */ 268 mxcmci_writew(host, STR_STP_CLK_RESET, MMC_REG_STR_STP_CLK); 269 mxcmci_writew(host, STR_STP_CLK_RESET | STR_STP_CLK_START_CLK, 270 MMC_REG_STR_STP_CLK); 271 272 for (i = 0; i < 8; i++) 273 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK); 274 275 mxcmci_writew(host, 0xff, MMC_REG_RES_TO); 276 } 277 278 #if IS_ENABLED(CONFIG_PPC_MPC512x) 279 static inline void buffer_swap32(u32 *buf, int len) 280 { 281 int i; 282 283 for (i = 0; i < ((len + 3) / 4); i++) { 284 *buf = swab32(*buf); 285 buf++; 286 } 287 } 288 289 static void mxcmci_swap_buffers(struct mmc_data *data) 290 { 291 struct scatterlist *sg; 292 int i; 293 294 for_each_sg(data->sg, sg, data->sg_len, i) { 295 void *buf = kmap_atomic(sg_page(sg) + sg->offset; 296 buffer_swap32(buf, sg->length); 297 kunmap_atomic(buf); 298 } 299 #else 300 static inline void mxcmci_swap_buffers(struct mmc_data *data) {} 301 #endif 302 303 static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data) 304 { 305 unsigned int nob = data->blocks; 306 unsigned int blksz = data->blksz; 307 unsigned int datasize = nob * blksz; 308 struct scatterlist *sg; 309 enum dma_transfer_direction slave_dirn; 310 int i, nents; 311 312 host->data = data; 313 data->bytes_xfered = 0; 314 315 mxcmci_writew(host, nob, MMC_REG_NOB); 316 mxcmci_writew(host, blksz, MMC_REG_BLK_LEN); 317 host->datasize = datasize; 318 319 if (!mxcmci_use_dma(host)) 320 return 0; 321 322 for_each_sg(data->sg, sg, data->sg_len, i) { 323 if (sg->offset & 3 || sg->length & 3 || sg->length < 512) { 324 host->do_dma = 0; 325 return 0; 326 } 327 } 328 329 if (data->flags & MMC_DATA_READ) { 330 host->dma_dir = DMA_FROM_DEVICE; 331 slave_dirn = DMA_DEV_TO_MEM; 332 } else { 333 host->dma_dir = DMA_TO_DEVICE; 334 slave_dirn = DMA_MEM_TO_DEV; 335 336 mxcmci_swap_buffers(data); 337 } 338 339 nents = dma_map_sg(host->dma->device->dev, data->sg, 340 data->sg_len, host->dma_dir); 341 if (nents != data->sg_len) 342 return -EINVAL; 343 344 host->desc = dmaengine_prep_slave_sg(host->dma, 345 data->sg, data->sg_len, slave_dirn, 346 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 347 348 if (!host->desc) { 349 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len, 350 host->dma_dir); 351 host->do_dma = 0; 352 return 0; /* Fall back to PIO */ 353 } 354 wmb(); 355 356 dmaengine_submit(host->desc); 357 dma_async_issue_pending(host->dma); 358 359 mod_timer(&host->watchdog, jiffies + msecs_to_jiffies(MXCMCI_TIMEOUT_MS)); 360 361 return 0; 362 } 363 364 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat); 365 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat); 366 367 static void mxcmci_dma_callback(void *data) 368 { 369 struct mxcmci_host *host = data; 370 u32 stat; 371 372 del_timer(&host->watchdog); 373 374 stat = mxcmci_readl(host, MMC_REG_STATUS); 375 376 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat); 377 378 mxcmci_data_done(host, stat); 379 } 380 381 static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd, 382 unsigned int cmdat) 383 { 384 u32 int_cntr = host->default_irq_mask; 385 unsigned long flags; 386 387 WARN_ON(host->cmd != NULL); 388 host->cmd = cmd; 389 390 switch (mmc_resp_type(cmd)) { 391 case MMC_RSP_R1: /* short CRC, OPCODE */ 392 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */ 393 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC; 394 break; 395 case MMC_RSP_R2: /* long 136 bit + CRC */ 396 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT; 397 break; 398 case MMC_RSP_R3: /* short */ 399 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT; 400 break; 401 case MMC_RSP_NONE: 402 break; 403 default: 404 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n", 405 mmc_resp_type(cmd)); 406 cmd->error = -EINVAL; 407 return -EINVAL; 408 } 409 410 int_cntr = INT_END_CMD_RES_EN; 411 412 if (mxcmci_use_dma(host)) { 413 if (host->dma_dir == DMA_FROM_DEVICE) { 414 host->desc->callback = mxcmci_dma_callback; 415 host->desc->callback_param = host; 416 } else { 417 int_cntr |= INT_WRITE_OP_DONE_EN; 418 } 419 } 420 421 spin_lock_irqsave(&host->lock, flags); 422 if (host->use_sdio) 423 int_cntr |= INT_SDIO_IRQ_EN; 424 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR); 425 spin_unlock_irqrestore(&host->lock, flags); 426 427 mxcmci_writew(host, cmd->opcode, MMC_REG_CMD); 428 mxcmci_writel(host, cmd->arg, MMC_REG_ARG); 429 mxcmci_writew(host, cmdat, MMC_REG_CMD_DAT_CONT); 430 431 return 0; 432 } 433 434 static void mxcmci_finish_request(struct mxcmci_host *host, 435 struct mmc_request *req) 436 { 437 u32 int_cntr = host->default_irq_mask; 438 unsigned long flags; 439 440 spin_lock_irqsave(&host->lock, flags); 441 if (host->use_sdio) 442 int_cntr |= INT_SDIO_IRQ_EN; 443 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR); 444 spin_unlock_irqrestore(&host->lock, flags); 445 446 host->req = NULL; 447 host->cmd = NULL; 448 host->data = NULL; 449 450 mmc_request_done(host->mmc, req); 451 } 452 453 static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat) 454 { 455 struct mmc_data *data = host->data; 456 int data_error; 457 458 if (mxcmci_use_dma(host)) { 459 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len, 460 host->dma_dir); 461 mxcmci_swap_buffers(data); 462 } 463 464 if (stat & STATUS_ERR_MASK) { 465 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n", 466 stat); 467 if (stat & STATUS_CRC_READ_ERR) { 468 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__); 469 data->error = -EILSEQ; 470 } else if (stat & STATUS_CRC_WRITE_ERR) { 471 u32 err_code = (stat >> 9) & 0x3; 472 if (err_code == 2) { /* No CRC response */ 473 dev_err(mmc_dev(host->mmc), 474 "%s: No CRC -ETIMEDOUT\n", __func__); 475 data->error = -ETIMEDOUT; 476 } else { 477 dev_err(mmc_dev(host->mmc), 478 "%s: -EILSEQ\n", __func__); 479 data->error = -EILSEQ; 480 } 481 } else if (stat & STATUS_TIME_OUT_READ) { 482 dev_err(mmc_dev(host->mmc), 483 "%s: read -ETIMEDOUT\n", __func__); 484 data->error = -ETIMEDOUT; 485 } else { 486 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__); 487 data->error = -EIO; 488 } 489 } else { 490 data->bytes_xfered = host->datasize; 491 } 492 493 data_error = data->error; 494 495 host->data = NULL; 496 497 return data_error; 498 } 499 500 static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat) 501 { 502 struct mmc_command *cmd = host->cmd; 503 int i; 504 u32 a, b, c; 505 506 if (!cmd) 507 return; 508 509 if (stat & STATUS_TIME_OUT_RESP) { 510 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n"); 511 cmd->error = -ETIMEDOUT; 512 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) { 513 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n"); 514 cmd->error = -EILSEQ; 515 } 516 517 if (cmd->flags & MMC_RSP_PRESENT) { 518 if (cmd->flags & MMC_RSP_136) { 519 for (i = 0; i < 4; i++) { 520 a = mxcmci_readw(host, MMC_REG_RES_FIFO); 521 b = mxcmci_readw(host, MMC_REG_RES_FIFO); 522 cmd->resp[i] = a << 16 | b; 523 } 524 } else { 525 a = mxcmci_readw(host, MMC_REG_RES_FIFO); 526 b = mxcmci_readw(host, MMC_REG_RES_FIFO); 527 c = mxcmci_readw(host, MMC_REG_RES_FIFO); 528 cmd->resp[0] = a << 24 | b << 8 | c >> 8; 529 } 530 } 531 } 532 533 static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask) 534 { 535 u32 stat; 536 unsigned long timeout = jiffies + HZ; 537 538 do { 539 stat = mxcmci_readl(host, MMC_REG_STATUS); 540 if (stat & STATUS_ERR_MASK) 541 return stat; 542 if (time_after(jiffies, timeout)) { 543 mxcmci_softreset(host); 544 mxcmci_set_clk_rate(host, host->clock); 545 return STATUS_TIME_OUT_READ; 546 } 547 if (stat & mask) 548 return 0; 549 cpu_relax(); 550 } while (1); 551 } 552 553 static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes) 554 { 555 unsigned int stat; 556 u32 *buf = _buf; 557 558 while (bytes > 3) { 559 stat = mxcmci_poll_status(host, 560 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE); 561 if (stat) 562 return stat; 563 *buf++ = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS)); 564 bytes -= 4; 565 } 566 567 if (bytes) { 568 u8 *b = (u8 *)buf; 569 u32 tmp; 570 571 stat = mxcmci_poll_status(host, 572 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE); 573 if (stat) 574 return stat; 575 tmp = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS)); 576 memcpy(b, &tmp, bytes); 577 } 578 579 return 0; 580 } 581 582 static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes) 583 { 584 unsigned int stat; 585 u32 *buf = _buf; 586 587 while (bytes > 3) { 588 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 589 if (stat) 590 return stat; 591 mxcmci_writel(host, cpu_to_le32(*buf++), MMC_REG_BUFFER_ACCESS); 592 bytes -= 4; 593 } 594 595 if (bytes) { 596 u8 *b = (u8 *)buf; 597 u32 tmp; 598 599 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 600 if (stat) 601 return stat; 602 603 memcpy(&tmp, b, bytes); 604 mxcmci_writel(host, cpu_to_le32(tmp), MMC_REG_BUFFER_ACCESS); 605 } 606 607 return mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 608 } 609 610 static int mxcmci_transfer_data(struct mxcmci_host *host) 611 { 612 struct mmc_data *data = host->req->data; 613 struct scatterlist *sg; 614 void *buf; 615 int stat, i; 616 617 host->data = data; 618 host->datasize = 0; 619 620 if (data->flags & MMC_DATA_READ) { 621 for_each_sg(data->sg, sg, data->sg_len, i) { 622 buf = kmap_atomic(sg_page(sg) + sg->offset); 623 stat = mxcmci_pull(host, buf, sg->length); 624 kunmap(buf); 625 if (stat) 626 return stat; 627 host->datasize += sg->length; 628 } 629 } else { 630 for_each_sg(data->sg, sg, data->sg_len, i) { 631 buf = kmap_atomic(sg_page(sg) + sg->offset); 632 stat = mxcmci_push(host, buf, sg->length); 633 kunmap(buf); 634 if (stat) 635 return stat; 636 host->datasize += sg->length; 637 } 638 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE); 639 if (stat) 640 return stat; 641 } 642 return 0; 643 } 644 645 static void mxcmci_datawork(struct work_struct *work) 646 { 647 struct mxcmci_host *host = container_of(work, struct mxcmci_host, 648 datawork); 649 int datastat = mxcmci_transfer_data(host); 650 651 mxcmci_writel(host, STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE, 652 MMC_REG_STATUS); 653 mxcmci_finish_data(host, datastat); 654 655 if (host->req->stop) { 656 if (mxcmci_start_cmd(host, host->req->stop, 0)) { 657 mxcmci_finish_request(host, host->req); 658 return; 659 } 660 } else { 661 mxcmci_finish_request(host, host->req); 662 } 663 } 664 665 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat) 666 { 667 struct mmc_request *req; 668 int data_error; 669 unsigned long flags; 670 671 spin_lock_irqsave(&host->lock, flags); 672 673 if (!host->data) { 674 spin_unlock_irqrestore(&host->lock, flags); 675 return; 676 } 677 678 if (!host->req) { 679 spin_unlock_irqrestore(&host->lock, flags); 680 return; 681 } 682 683 req = host->req; 684 if (!req->stop) 685 host->req = NULL; /* we will handle finish req below */ 686 687 data_error = mxcmci_finish_data(host, stat); 688 689 spin_unlock_irqrestore(&host->lock, flags); 690 691 if (data_error) 692 return; 693 694 mxcmci_read_response(host, stat); 695 host->cmd = NULL; 696 697 if (req->stop) { 698 if (mxcmci_start_cmd(host, req->stop, 0)) { 699 mxcmci_finish_request(host, req); 700 return; 701 } 702 } else { 703 mxcmci_finish_request(host, req); 704 } 705 } 706 707 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat) 708 { 709 mxcmci_read_response(host, stat); 710 host->cmd = NULL; 711 712 if (!host->data && host->req) { 713 mxcmci_finish_request(host, host->req); 714 return; 715 } 716 717 /* For the DMA case the DMA engine handles the data transfer 718 * automatically. For non DMA we have to do it ourselves. 719 * Don't do it in interrupt context though. 720 */ 721 if (!mxcmci_use_dma(host) && host->data) 722 schedule_work(&host->datawork); 723 724 } 725 726 static irqreturn_t mxcmci_irq(int irq, void *devid) 727 { 728 struct mxcmci_host *host = devid; 729 unsigned long flags; 730 bool sdio_irq; 731 u32 stat; 732 733 stat = mxcmci_readl(host, MMC_REG_STATUS); 734 mxcmci_writel(host, 735 stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE | 736 STATUS_WRITE_OP_DONE), 737 MMC_REG_STATUS); 738 739 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat); 740 741 spin_lock_irqsave(&host->lock, flags); 742 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio; 743 spin_unlock_irqrestore(&host->lock, flags); 744 745 if (mxcmci_use_dma(host) && (stat & (STATUS_WRITE_OP_DONE))) 746 mxcmci_writel(host, STATUS_WRITE_OP_DONE, MMC_REG_STATUS); 747 748 if (sdio_irq) { 749 mxcmci_writel(host, STATUS_SDIO_INT_ACTIVE, MMC_REG_STATUS); 750 mmc_signal_sdio_irq(host->mmc); 751 } 752 753 if (stat & STATUS_END_CMD_RESP) 754 mxcmci_cmd_done(host, stat); 755 756 if (mxcmci_use_dma(host) && (stat & STATUS_WRITE_OP_DONE)) { 757 del_timer(&host->watchdog); 758 mxcmci_data_done(host, stat); 759 } 760 761 if (host->default_irq_mask && 762 (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL))) 763 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 764 765 return IRQ_HANDLED; 766 } 767 768 static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req) 769 { 770 struct mxcmci_host *host = mmc_priv(mmc); 771 unsigned int cmdat = host->cmdat; 772 int error; 773 774 WARN_ON(host->req != NULL); 775 776 host->req = req; 777 host->cmdat &= ~CMD_DAT_CONT_INIT; 778 779 if (host->dma) 780 host->do_dma = 1; 781 782 if (req->data) { 783 error = mxcmci_setup_data(host, req->data); 784 if (error) { 785 req->cmd->error = error; 786 goto out; 787 } 788 789 790 cmdat |= CMD_DAT_CONT_DATA_ENABLE; 791 792 if (req->data->flags & MMC_DATA_WRITE) 793 cmdat |= CMD_DAT_CONT_WRITE; 794 } 795 796 error = mxcmci_start_cmd(host, req->cmd, cmdat); 797 798 out: 799 if (error) 800 mxcmci_finish_request(host, req); 801 } 802 803 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios) 804 { 805 unsigned int divider; 806 int prescaler = 0; 807 unsigned int clk_in = clk_get_rate(host->clk_per); 808 809 while (prescaler <= 0x800) { 810 for (divider = 1; divider <= 0xF; divider++) { 811 int x; 812 813 x = (clk_in / (divider + 1)); 814 815 if (prescaler) 816 x /= (prescaler * 2); 817 818 if (x <= clk_ios) 819 break; 820 } 821 if (divider < 0x10) 822 break; 823 824 if (prescaler == 0) 825 prescaler = 1; 826 else 827 prescaler <<= 1; 828 } 829 830 mxcmci_writew(host, (prescaler << 4) | divider, MMC_REG_CLK_RATE); 831 832 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n", 833 prescaler, divider, clk_in, clk_ios); 834 } 835 836 static int mxcmci_setup_dma(struct mmc_host *mmc) 837 { 838 struct mxcmci_host *host = mmc_priv(mmc); 839 struct dma_slave_config *config = &host->dma_slave_config; 840 841 config->dst_addr = host->phys_base + MMC_REG_BUFFER_ACCESS; 842 config->src_addr = host->phys_base + MMC_REG_BUFFER_ACCESS; 843 config->dst_addr_width = 4; 844 config->src_addr_width = 4; 845 config->dst_maxburst = host->burstlen; 846 config->src_maxburst = host->burstlen; 847 config->device_fc = false; 848 849 return dmaengine_slave_config(host->dma, config); 850 } 851 852 static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 853 { 854 struct mxcmci_host *host = mmc_priv(mmc); 855 int burstlen, ret; 856 857 /* 858 * use burstlen of 64 (16 words) in 4 bit mode (--> reg value 0) 859 * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16) 860 */ 861 if (ios->bus_width == MMC_BUS_WIDTH_4) 862 burstlen = 16; 863 else 864 burstlen = 4; 865 866 if (mxcmci_use_dma(host) && burstlen != host->burstlen) { 867 host->burstlen = burstlen; 868 ret = mxcmci_setup_dma(mmc); 869 if (ret) { 870 dev_err(mmc_dev(host->mmc), 871 "failed to config DMA channel. Falling back to PIO\n"); 872 dma_release_channel(host->dma); 873 host->do_dma = 0; 874 host->dma = NULL; 875 } 876 } 877 878 if (ios->bus_width == MMC_BUS_WIDTH_4) 879 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4; 880 else 881 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4; 882 883 if (host->power_mode != ios->power_mode) { 884 host->power_mode = ios->power_mode; 885 mxcmci_set_power(host, ios->vdd); 886 887 if (ios->power_mode == MMC_POWER_ON) 888 host->cmdat |= CMD_DAT_CONT_INIT; 889 } 890 891 if (ios->clock) { 892 mxcmci_set_clk_rate(host, ios->clock); 893 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK); 894 } else { 895 mxcmci_writew(host, STR_STP_CLK_STOP_CLK, MMC_REG_STR_STP_CLK); 896 } 897 898 host->clock = ios->clock; 899 } 900 901 static irqreturn_t mxcmci_detect_irq(int irq, void *data) 902 { 903 struct mmc_host *mmc = data; 904 905 dev_dbg(mmc_dev(mmc), "%s\n", __func__); 906 907 mmc_detect_change(mmc, msecs_to_jiffies(250)); 908 return IRQ_HANDLED; 909 } 910 911 static int mxcmci_get_ro(struct mmc_host *mmc) 912 { 913 struct mxcmci_host *host = mmc_priv(mmc); 914 915 if (host->pdata && host->pdata->get_ro) 916 return !!host->pdata->get_ro(mmc_dev(mmc)); 917 /* 918 * If board doesn't support read only detection (no mmc_gpio 919 * context or gpio is invalid), then let the mmc core decide 920 * what to do. 921 */ 922 return mmc_gpio_get_ro(mmc); 923 } 924 925 static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable) 926 { 927 struct mxcmci_host *host = mmc_priv(mmc); 928 unsigned long flags; 929 u32 int_cntr; 930 931 spin_lock_irqsave(&host->lock, flags); 932 host->use_sdio = enable; 933 int_cntr = mxcmci_readl(host, MMC_REG_INT_CNTR); 934 935 if (enable) 936 int_cntr |= INT_SDIO_IRQ_EN; 937 else 938 int_cntr &= ~INT_SDIO_IRQ_EN; 939 940 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR); 941 spin_unlock_irqrestore(&host->lock, flags); 942 } 943 944 static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card) 945 { 946 struct mxcmci_host *mxcmci = mmc_priv(host); 947 948 /* 949 * MX3 SoCs have a silicon bug which corrupts CRC calculation of 950 * multi-block transfers when connected SDIO peripheral doesn't 951 * drive the BUSY line as required by the specs. 952 * One way to prevent this is to only allow 1-bit transfers. 953 */ 954 955 if (is_imx31_mmc(mxcmci) && card->type == MMC_TYPE_SDIO) 956 host->caps &= ~MMC_CAP_4_BIT_DATA; 957 else 958 host->caps |= MMC_CAP_4_BIT_DATA; 959 } 960 961 static bool filter(struct dma_chan *chan, void *param) 962 { 963 struct mxcmci_host *host = param; 964 965 if (!imx_dma_is_general_purpose(chan)) 966 return false; 967 968 chan->private = &host->dma_data; 969 970 return true; 971 } 972 973 static void mxcmci_watchdog(struct timer_list *t) 974 { 975 struct mxcmci_host *host = from_timer(host, t, watchdog); 976 struct mmc_request *req = host->req; 977 unsigned int stat = mxcmci_readl(host, MMC_REG_STATUS); 978 979 if (host->dma_dir == DMA_FROM_DEVICE) { 980 dmaengine_terminate_all(host->dma); 981 dev_err(mmc_dev(host->mmc), 982 "%s: read time out (status = 0x%08x)\n", 983 __func__, stat); 984 } else { 985 dev_err(mmc_dev(host->mmc), 986 "%s: write time out (status = 0x%08x)\n", 987 __func__, stat); 988 mxcmci_softreset(host); 989 } 990 991 /* Mark transfer as erroneus and inform the upper layers */ 992 993 if (host->data) 994 host->data->error = -ETIMEDOUT; 995 host->req = NULL; 996 host->cmd = NULL; 997 host->data = NULL; 998 mmc_request_done(host->mmc, req); 999 } 1000 1001 static const struct mmc_host_ops mxcmci_ops = { 1002 .request = mxcmci_request, 1003 .set_ios = mxcmci_set_ios, 1004 .get_ro = mxcmci_get_ro, 1005 .enable_sdio_irq = mxcmci_enable_sdio_irq, 1006 .init_card = mxcmci_init_card, 1007 }; 1008 1009 static int mxcmci_probe(struct platform_device *pdev) 1010 { 1011 struct mmc_host *mmc; 1012 struct mxcmci_host *host; 1013 struct resource *res; 1014 int ret = 0, irq; 1015 bool dat3_card_detect = false; 1016 dma_cap_mask_t mask; 1017 const struct of_device_id *of_id; 1018 struct imxmmc_platform_data *pdata = pdev->dev.platform_data; 1019 1020 pr_info("i.MX/MPC512x SDHC driver\n"); 1021 1022 of_id = of_match_device(mxcmci_of_match, &pdev->dev); 1023 1024 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1025 irq = platform_get_irq(pdev, 0); 1026 if (irq < 0) { 1027 dev_err(&pdev->dev, "failed to get IRQ: %d\n", irq); 1028 return irq; 1029 } 1030 1031 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); 1032 if (!mmc) 1033 return -ENOMEM; 1034 1035 host = mmc_priv(mmc); 1036 1037 host->base = devm_ioremap_resource(&pdev->dev, res); 1038 if (IS_ERR(host->base)) { 1039 ret = PTR_ERR(host->base); 1040 goto out_free; 1041 } 1042 1043 host->phys_base = res->start; 1044 1045 ret = mmc_of_parse(mmc); 1046 if (ret) 1047 goto out_free; 1048 mmc->ops = &mxcmci_ops; 1049 1050 /* For devicetree parsing, the bus width is read from devicetree */ 1051 if (pdata) 1052 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; 1053 else 1054 mmc->caps |= MMC_CAP_SDIO_IRQ; 1055 1056 /* MMC core transfer sizes tunable parameters */ 1057 mmc->max_blk_size = 2048; 1058 mmc->max_blk_count = 65535; 1059 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1060 mmc->max_seg_size = mmc->max_req_size; 1061 1062 if (of_id) { 1063 const struct platform_device_id *id_entry = of_id->data; 1064 host->devtype = id_entry->driver_data; 1065 } else { 1066 host->devtype = pdev->id_entry->driver_data; 1067 } 1068 1069 /* adjust max_segs after devtype detection */ 1070 if (!is_mpc512x_mmc(host)) 1071 mmc->max_segs = 64; 1072 1073 host->mmc = mmc; 1074 host->pdata = pdata; 1075 spin_lock_init(&host->lock); 1076 1077 if (pdata) 1078 dat3_card_detect = pdata->dat3_card_detect; 1079 else if (mmc_card_is_removable(mmc) 1080 && !of_property_read_bool(pdev->dev.of_node, "cd-gpios")) 1081 dat3_card_detect = true; 1082 1083 ret = mmc_regulator_get_supply(mmc); 1084 if (ret) 1085 goto out_free; 1086 1087 if (!mmc->ocr_avail) { 1088 if (pdata && pdata->ocr_avail) 1089 mmc->ocr_avail = pdata->ocr_avail; 1090 else 1091 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1092 } 1093 1094 if (dat3_card_detect) 1095 host->default_irq_mask = 1096 INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN; 1097 else 1098 host->default_irq_mask = 0; 1099 1100 host->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1101 if (IS_ERR(host->clk_ipg)) { 1102 ret = PTR_ERR(host->clk_ipg); 1103 goto out_free; 1104 } 1105 1106 host->clk_per = devm_clk_get(&pdev->dev, "per"); 1107 if (IS_ERR(host->clk_per)) { 1108 ret = PTR_ERR(host->clk_per); 1109 goto out_free; 1110 } 1111 1112 ret = clk_prepare_enable(host->clk_per); 1113 if (ret) 1114 goto out_free; 1115 1116 ret = clk_prepare_enable(host->clk_ipg); 1117 if (ret) 1118 goto out_clk_per_put; 1119 1120 mxcmci_softreset(host); 1121 1122 host->rev_no = mxcmci_readw(host, MMC_REG_REV_NO); 1123 if (host->rev_no != 0x400) { 1124 ret = -ENODEV; 1125 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n", 1126 host->rev_no); 1127 goto out_clk_put; 1128 } 1129 1130 mmc->f_min = clk_get_rate(host->clk_per) >> 16; 1131 mmc->f_max = clk_get_rate(host->clk_per) >> 1; 1132 1133 /* recommended in data sheet */ 1134 mxcmci_writew(host, 0x2db4, MMC_REG_READ_TO); 1135 1136 mxcmci_writel(host, host->default_irq_mask, MMC_REG_INT_CNTR); 1137 1138 if (!host->pdata) { 1139 host->dma = dma_request_slave_channel(&pdev->dev, "rx-tx"); 1140 } else { 1141 res = platform_get_resource(pdev, IORESOURCE_DMA, 0); 1142 if (res) { 1143 host->dmareq = res->start; 1144 host->dma_data.peripheral_type = IMX_DMATYPE_SDHC; 1145 host->dma_data.priority = DMA_PRIO_LOW; 1146 host->dma_data.dma_request = host->dmareq; 1147 dma_cap_zero(mask); 1148 dma_cap_set(DMA_SLAVE, mask); 1149 host->dma = dma_request_channel(mask, filter, host); 1150 } 1151 } 1152 if (host->dma) 1153 mmc->max_seg_size = dma_get_max_seg_size( 1154 host->dma->device->dev); 1155 else 1156 dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n"); 1157 1158 INIT_WORK(&host->datawork, mxcmci_datawork); 1159 1160 ret = devm_request_irq(&pdev->dev, irq, mxcmci_irq, 0, 1161 dev_name(&pdev->dev), host); 1162 if (ret) 1163 goto out_free_dma; 1164 1165 platform_set_drvdata(pdev, mmc); 1166 1167 if (host->pdata && host->pdata->init) { 1168 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq, 1169 host->mmc); 1170 if (ret) 1171 goto out_free_dma; 1172 } 1173 1174 timer_setup(&host->watchdog, mxcmci_watchdog, 0); 1175 1176 mmc_add_host(mmc); 1177 1178 return 0; 1179 1180 out_free_dma: 1181 if (host->dma) 1182 dma_release_channel(host->dma); 1183 1184 out_clk_put: 1185 clk_disable_unprepare(host->clk_ipg); 1186 out_clk_per_put: 1187 clk_disable_unprepare(host->clk_per); 1188 1189 out_free: 1190 mmc_free_host(mmc); 1191 1192 return ret; 1193 } 1194 1195 static int mxcmci_remove(struct platform_device *pdev) 1196 { 1197 struct mmc_host *mmc = platform_get_drvdata(pdev); 1198 struct mxcmci_host *host = mmc_priv(mmc); 1199 1200 mmc_remove_host(mmc); 1201 1202 if (host->pdata && host->pdata->exit) 1203 host->pdata->exit(&pdev->dev, mmc); 1204 1205 if (host->dma) 1206 dma_release_channel(host->dma); 1207 1208 clk_disable_unprepare(host->clk_per); 1209 clk_disable_unprepare(host->clk_ipg); 1210 1211 mmc_free_host(mmc); 1212 1213 return 0; 1214 } 1215 1216 static int __maybe_unused mxcmci_suspend(struct device *dev) 1217 { 1218 struct mmc_host *mmc = dev_get_drvdata(dev); 1219 struct mxcmci_host *host = mmc_priv(mmc); 1220 1221 clk_disable_unprepare(host->clk_per); 1222 clk_disable_unprepare(host->clk_ipg); 1223 return 0; 1224 } 1225 1226 static int __maybe_unused mxcmci_resume(struct device *dev) 1227 { 1228 struct mmc_host *mmc = dev_get_drvdata(dev); 1229 struct mxcmci_host *host = mmc_priv(mmc); 1230 int ret; 1231 1232 ret = clk_prepare_enable(host->clk_per); 1233 if (ret) 1234 return ret; 1235 1236 ret = clk_prepare_enable(host->clk_ipg); 1237 if (ret) 1238 clk_disable_unprepare(host->clk_per); 1239 1240 return ret; 1241 } 1242 1243 static SIMPLE_DEV_PM_OPS(mxcmci_pm_ops, mxcmci_suspend, mxcmci_resume); 1244 1245 static struct platform_driver mxcmci_driver = { 1246 .probe = mxcmci_probe, 1247 .remove = mxcmci_remove, 1248 .id_table = mxcmci_devtype, 1249 .driver = { 1250 .name = DRIVER_NAME, 1251 .pm = &mxcmci_pm_ops, 1252 .of_match_table = mxcmci_of_match, 1253 } 1254 }; 1255 1256 module_platform_driver(mxcmci_driver); 1257 1258 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver"); 1259 MODULE_AUTHOR("Sascha Hauer, Pengutronix"); 1260 MODULE_LICENSE("GPL"); 1261 MODULE_ALIAS("platform:mxc-mmc"); 1262