1 /* 2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver 3 * 4 * This is a driver for the SDHC controller found in Freescale MX2/MX3 5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c). 6 * Unlike the hardware found on MX1, this hardware just works and does 7 * not need all the quirks found in imxmmc.c, hence the separate driver. 8 * 9 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> 10 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com> 11 * 12 * derived from pxamci.c by Russell King 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 * 18 */ 19 20 #include <linux/module.h> 21 #include <linux/init.h> 22 #include <linux/ioport.h> 23 #include <linux/platform_device.h> 24 #include <linux/interrupt.h> 25 #include <linux/irq.h> 26 #include <linux/blkdev.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/mmc/host.h> 29 #include <linux/mmc/card.h> 30 #include <linux/delay.h> 31 #include <linux/clk.h> 32 #include <linux/io.h> 33 #include <linux/gpio.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/dmaengine.h> 36 #include <linux/types.h> 37 38 #include <asm/dma.h> 39 #include <asm/irq.h> 40 #include <asm/sizes.h> 41 #include <mach/mmc.h> 42 43 #include <mach/dma.h> 44 #include <mach/hardware.h> 45 46 #define DRIVER_NAME "mxc-mmc" 47 48 #define MMC_REG_STR_STP_CLK 0x00 49 #define MMC_REG_STATUS 0x04 50 #define MMC_REG_CLK_RATE 0x08 51 #define MMC_REG_CMD_DAT_CONT 0x0C 52 #define MMC_REG_RES_TO 0x10 53 #define MMC_REG_READ_TO 0x14 54 #define MMC_REG_BLK_LEN 0x18 55 #define MMC_REG_NOB 0x1C 56 #define MMC_REG_REV_NO 0x20 57 #define MMC_REG_INT_CNTR 0x24 58 #define MMC_REG_CMD 0x28 59 #define MMC_REG_ARG 0x2C 60 #define MMC_REG_RES_FIFO 0x34 61 #define MMC_REG_BUFFER_ACCESS 0x38 62 63 #define STR_STP_CLK_RESET (1 << 3) 64 #define STR_STP_CLK_START_CLK (1 << 1) 65 #define STR_STP_CLK_STOP_CLK (1 << 0) 66 67 #define STATUS_CARD_INSERTION (1 << 31) 68 #define STATUS_CARD_REMOVAL (1 << 30) 69 #define STATUS_YBUF_EMPTY (1 << 29) 70 #define STATUS_XBUF_EMPTY (1 << 28) 71 #define STATUS_YBUF_FULL (1 << 27) 72 #define STATUS_XBUF_FULL (1 << 26) 73 #define STATUS_BUF_UND_RUN (1 << 25) 74 #define STATUS_BUF_OVFL (1 << 24) 75 #define STATUS_SDIO_INT_ACTIVE (1 << 14) 76 #define STATUS_END_CMD_RESP (1 << 13) 77 #define STATUS_WRITE_OP_DONE (1 << 12) 78 #define STATUS_DATA_TRANS_DONE (1 << 11) 79 #define STATUS_READ_OP_DONE (1 << 11) 80 #define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10) 81 #define STATUS_CARD_BUS_CLK_RUN (1 << 8) 82 #define STATUS_BUF_READ_RDY (1 << 7) 83 #define STATUS_BUF_WRITE_RDY (1 << 6) 84 #define STATUS_RESP_CRC_ERR (1 << 5) 85 #define STATUS_CRC_READ_ERR (1 << 3) 86 #define STATUS_CRC_WRITE_ERR (1 << 2) 87 #define STATUS_TIME_OUT_RESP (1 << 1) 88 #define STATUS_TIME_OUT_READ (1 << 0) 89 #define STATUS_ERR_MASK 0x2f 90 91 #define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12) 92 #define CMD_DAT_CONT_STOP_READWAIT (1 << 11) 93 #define CMD_DAT_CONT_START_READWAIT (1 << 10) 94 #define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8) 95 #define CMD_DAT_CONT_INIT (1 << 7) 96 #define CMD_DAT_CONT_WRITE (1 << 4) 97 #define CMD_DAT_CONT_DATA_ENABLE (1 << 3) 98 #define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0) 99 #define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0) 100 #define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0) 101 102 #define INT_SDIO_INT_WKP_EN (1 << 18) 103 #define INT_CARD_INSERTION_WKP_EN (1 << 17) 104 #define INT_CARD_REMOVAL_WKP_EN (1 << 16) 105 #define INT_CARD_INSERTION_EN (1 << 15) 106 #define INT_CARD_REMOVAL_EN (1 << 14) 107 #define INT_SDIO_IRQ_EN (1 << 13) 108 #define INT_DAT0_EN (1 << 12) 109 #define INT_BUF_READ_EN (1 << 4) 110 #define INT_BUF_WRITE_EN (1 << 3) 111 #define INT_END_CMD_RES_EN (1 << 2) 112 #define INT_WRITE_OP_DONE_EN (1 << 1) 113 #define INT_READ_OP_EN (1 << 0) 114 115 struct mxcmci_host { 116 struct mmc_host *mmc; 117 struct resource *res; 118 void __iomem *base; 119 int irq; 120 int detect_irq; 121 struct dma_chan *dma; 122 struct dma_async_tx_descriptor *desc; 123 int do_dma; 124 int default_irq_mask; 125 int use_sdio; 126 unsigned int power_mode; 127 struct imxmmc_platform_data *pdata; 128 129 struct mmc_request *req; 130 struct mmc_command *cmd; 131 struct mmc_data *data; 132 133 unsigned int datasize; 134 unsigned int dma_dir; 135 136 u16 rev_no; 137 unsigned int cmdat; 138 139 struct clk *clk_ipg; 140 struct clk *clk_per; 141 142 int clock; 143 144 struct work_struct datawork; 145 spinlock_t lock; 146 147 struct regulator *vcc; 148 149 int burstlen; 150 int dmareq; 151 struct dma_slave_config dma_slave_config; 152 struct imx_dma_data dma_data; 153 }; 154 155 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios); 156 157 static inline void mxcmci_init_ocr(struct mxcmci_host *host) 158 { 159 host->vcc = regulator_get(mmc_dev(host->mmc), "vmmc"); 160 161 if (IS_ERR(host->vcc)) { 162 host->vcc = NULL; 163 } else { 164 host->mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vcc); 165 if (host->pdata && host->pdata->ocr_avail) 166 dev_warn(mmc_dev(host->mmc), 167 "pdata->ocr_avail will not be used\n"); 168 } 169 170 if (host->vcc == NULL) { 171 /* fall-back to platform data */ 172 if (host->pdata && host->pdata->ocr_avail) 173 host->mmc->ocr_avail = host->pdata->ocr_avail; 174 else 175 host->mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 176 } 177 } 178 179 static inline void mxcmci_set_power(struct mxcmci_host *host, 180 unsigned char power_mode, 181 unsigned int vdd) 182 { 183 if (host->vcc) { 184 if (power_mode == MMC_POWER_UP) 185 mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 186 else if (power_mode == MMC_POWER_OFF) 187 mmc_regulator_set_ocr(host->mmc, host->vcc, 0); 188 } 189 190 if (host->pdata && host->pdata->setpower) 191 host->pdata->setpower(mmc_dev(host->mmc), vdd); 192 } 193 194 static inline int mxcmci_use_dma(struct mxcmci_host *host) 195 { 196 return host->do_dma; 197 } 198 199 static void mxcmci_softreset(struct mxcmci_host *host) 200 { 201 int i; 202 203 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n"); 204 205 /* reset sequence */ 206 writew(STR_STP_CLK_RESET, host->base + MMC_REG_STR_STP_CLK); 207 writew(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK, 208 host->base + MMC_REG_STR_STP_CLK); 209 210 for (i = 0; i < 8; i++) 211 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK); 212 213 writew(0xff, host->base + MMC_REG_RES_TO); 214 } 215 static int mxcmci_setup_dma(struct mmc_host *mmc); 216 217 static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data) 218 { 219 unsigned int nob = data->blocks; 220 unsigned int blksz = data->blksz; 221 unsigned int datasize = nob * blksz; 222 struct scatterlist *sg; 223 enum dma_transfer_direction slave_dirn; 224 int i, nents; 225 226 if (data->flags & MMC_DATA_STREAM) 227 nob = 0xffff; 228 229 host->data = data; 230 data->bytes_xfered = 0; 231 232 writew(nob, host->base + MMC_REG_NOB); 233 writew(blksz, host->base + MMC_REG_BLK_LEN); 234 host->datasize = datasize; 235 236 if (!mxcmci_use_dma(host)) 237 return 0; 238 239 for_each_sg(data->sg, sg, data->sg_len, i) { 240 if (sg->offset & 3 || sg->length & 3) { 241 host->do_dma = 0; 242 return 0; 243 } 244 } 245 246 if (data->flags & MMC_DATA_READ) { 247 host->dma_dir = DMA_FROM_DEVICE; 248 slave_dirn = DMA_DEV_TO_MEM; 249 } else { 250 host->dma_dir = DMA_TO_DEVICE; 251 slave_dirn = DMA_MEM_TO_DEV; 252 } 253 254 nents = dma_map_sg(host->dma->device->dev, data->sg, 255 data->sg_len, host->dma_dir); 256 if (nents != data->sg_len) 257 return -EINVAL; 258 259 host->desc = dmaengine_prep_slave_sg(host->dma, 260 data->sg, data->sg_len, slave_dirn, 261 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 262 263 if (!host->desc) { 264 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len, 265 host->dma_dir); 266 host->do_dma = 0; 267 return 0; /* Fall back to PIO */ 268 } 269 wmb(); 270 271 dmaengine_submit(host->desc); 272 dma_async_issue_pending(host->dma); 273 274 return 0; 275 } 276 277 static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd, 278 unsigned int cmdat) 279 { 280 u32 int_cntr = host->default_irq_mask; 281 unsigned long flags; 282 283 WARN_ON(host->cmd != NULL); 284 host->cmd = cmd; 285 286 switch (mmc_resp_type(cmd)) { 287 case MMC_RSP_R1: /* short CRC, OPCODE */ 288 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */ 289 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC; 290 break; 291 case MMC_RSP_R2: /* long 136 bit + CRC */ 292 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT; 293 break; 294 case MMC_RSP_R3: /* short */ 295 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT; 296 break; 297 case MMC_RSP_NONE: 298 break; 299 default: 300 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n", 301 mmc_resp_type(cmd)); 302 cmd->error = -EINVAL; 303 return -EINVAL; 304 } 305 306 int_cntr = INT_END_CMD_RES_EN; 307 308 if (mxcmci_use_dma(host)) 309 int_cntr |= INT_READ_OP_EN | INT_WRITE_OP_DONE_EN; 310 311 spin_lock_irqsave(&host->lock, flags); 312 if (host->use_sdio) 313 int_cntr |= INT_SDIO_IRQ_EN; 314 writel(int_cntr, host->base + MMC_REG_INT_CNTR); 315 spin_unlock_irqrestore(&host->lock, flags); 316 317 writew(cmd->opcode, host->base + MMC_REG_CMD); 318 writel(cmd->arg, host->base + MMC_REG_ARG); 319 writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT); 320 321 return 0; 322 } 323 324 static void mxcmci_finish_request(struct mxcmci_host *host, 325 struct mmc_request *req) 326 { 327 u32 int_cntr = host->default_irq_mask; 328 unsigned long flags; 329 330 spin_lock_irqsave(&host->lock, flags); 331 if (host->use_sdio) 332 int_cntr |= INT_SDIO_IRQ_EN; 333 writel(int_cntr, host->base + MMC_REG_INT_CNTR); 334 spin_unlock_irqrestore(&host->lock, flags); 335 336 host->req = NULL; 337 host->cmd = NULL; 338 host->data = NULL; 339 340 mmc_request_done(host->mmc, req); 341 } 342 343 static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat) 344 { 345 struct mmc_data *data = host->data; 346 int data_error; 347 348 if (mxcmci_use_dma(host)) { 349 dmaengine_terminate_all(host->dma); 350 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len, 351 host->dma_dir); 352 } 353 354 if (stat & STATUS_ERR_MASK) { 355 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n", 356 stat); 357 if (stat & STATUS_CRC_READ_ERR) { 358 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__); 359 data->error = -EILSEQ; 360 } else if (stat & STATUS_CRC_WRITE_ERR) { 361 u32 err_code = (stat >> 9) & 0x3; 362 if (err_code == 2) { /* No CRC response */ 363 dev_err(mmc_dev(host->mmc), 364 "%s: No CRC -ETIMEDOUT\n", __func__); 365 data->error = -ETIMEDOUT; 366 } else { 367 dev_err(mmc_dev(host->mmc), 368 "%s: -EILSEQ\n", __func__); 369 data->error = -EILSEQ; 370 } 371 } else if (stat & STATUS_TIME_OUT_READ) { 372 dev_err(mmc_dev(host->mmc), 373 "%s: read -ETIMEDOUT\n", __func__); 374 data->error = -ETIMEDOUT; 375 } else { 376 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__); 377 data->error = -EIO; 378 } 379 } else { 380 data->bytes_xfered = host->datasize; 381 } 382 383 data_error = data->error; 384 385 host->data = NULL; 386 387 return data_error; 388 } 389 390 static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat) 391 { 392 struct mmc_command *cmd = host->cmd; 393 int i; 394 u32 a, b, c; 395 396 if (!cmd) 397 return; 398 399 if (stat & STATUS_TIME_OUT_RESP) { 400 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n"); 401 cmd->error = -ETIMEDOUT; 402 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) { 403 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n"); 404 cmd->error = -EILSEQ; 405 } 406 407 if (cmd->flags & MMC_RSP_PRESENT) { 408 if (cmd->flags & MMC_RSP_136) { 409 for (i = 0; i < 4; i++) { 410 a = readw(host->base + MMC_REG_RES_FIFO); 411 b = readw(host->base + MMC_REG_RES_FIFO); 412 cmd->resp[i] = a << 16 | b; 413 } 414 } else { 415 a = readw(host->base + MMC_REG_RES_FIFO); 416 b = readw(host->base + MMC_REG_RES_FIFO); 417 c = readw(host->base + MMC_REG_RES_FIFO); 418 cmd->resp[0] = a << 24 | b << 8 | c >> 8; 419 } 420 } 421 } 422 423 static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask) 424 { 425 u32 stat; 426 unsigned long timeout = jiffies + HZ; 427 428 do { 429 stat = readl(host->base + MMC_REG_STATUS); 430 if (stat & STATUS_ERR_MASK) 431 return stat; 432 if (time_after(jiffies, timeout)) { 433 mxcmci_softreset(host); 434 mxcmci_set_clk_rate(host, host->clock); 435 return STATUS_TIME_OUT_READ; 436 } 437 if (stat & mask) 438 return 0; 439 cpu_relax(); 440 } while (1); 441 } 442 443 static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes) 444 { 445 unsigned int stat; 446 u32 *buf = _buf; 447 448 while (bytes > 3) { 449 stat = mxcmci_poll_status(host, 450 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE); 451 if (stat) 452 return stat; 453 *buf++ = readl(host->base + MMC_REG_BUFFER_ACCESS); 454 bytes -= 4; 455 } 456 457 if (bytes) { 458 u8 *b = (u8 *)buf; 459 u32 tmp; 460 461 stat = mxcmci_poll_status(host, 462 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE); 463 if (stat) 464 return stat; 465 tmp = readl(host->base + MMC_REG_BUFFER_ACCESS); 466 memcpy(b, &tmp, bytes); 467 } 468 469 return 0; 470 } 471 472 static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes) 473 { 474 unsigned int stat; 475 u32 *buf = _buf; 476 477 while (bytes > 3) { 478 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 479 if (stat) 480 return stat; 481 writel(*buf++, host->base + MMC_REG_BUFFER_ACCESS); 482 bytes -= 4; 483 } 484 485 if (bytes) { 486 u8 *b = (u8 *)buf; 487 u32 tmp; 488 489 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 490 if (stat) 491 return stat; 492 493 memcpy(&tmp, b, bytes); 494 writel(tmp, host->base + MMC_REG_BUFFER_ACCESS); 495 } 496 497 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 498 if (stat) 499 return stat; 500 501 return 0; 502 } 503 504 static int mxcmci_transfer_data(struct mxcmci_host *host) 505 { 506 struct mmc_data *data = host->req->data; 507 struct scatterlist *sg; 508 int stat, i; 509 510 host->data = data; 511 host->datasize = 0; 512 513 if (data->flags & MMC_DATA_READ) { 514 for_each_sg(data->sg, sg, data->sg_len, i) { 515 stat = mxcmci_pull(host, sg_virt(sg), sg->length); 516 if (stat) 517 return stat; 518 host->datasize += sg->length; 519 } 520 } else { 521 for_each_sg(data->sg, sg, data->sg_len, i) { 522 stat = mxcmci_push(host, sg_virt(sg), sg->length); 523 if (stat) 524 return stat; 525 host->datasize += sg->length; 526 } 527 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE); 528 if (stat) 529 return stat; 530 } 531 return 0; 532 } 533 534 static void mxcmci_datawork(struct work_struct *work) 535 { 536 struct mxcmci_host *host = container_of(work, struct mxcmci_host, 537 datawork); 538 int datastat = mxcmci_transfer_data(host); 539 540 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE, 541 host->base + MMC_REG_STATUS); 542 mxcmci_finish_data(host, datastat); 543 544 if (host->req->stop) { 545 if (mxcmci_start_cmd(host, host->req->stop, 0)) { 546 mxcmci_finish_request(host, host->req); 547 return; 548 } 549 } else { 550 mxcmci_finish_request(host, host->req); 551 } 552 } 553 554 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat) 555 { 556 struct mmc_data *data = host->data; 557 int data_error; 558 559 if (!data) 560 return; 561 562 data_error = mxcmci_finish_data(host, stat); 563 564 mxcmci_read_response(host, stat); 565 host->cmd = NULL; 566 567 if (host->req->stop) { 568 if (mxcmci_start_cmd(host, host->req->stop, 0)) { 569 mxcmci_finish_request(host, host->req); 570 return; 571 } 572 } else { 573 mxcmci_finish_request(host, host->req); 574 } 575 } 576 577 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat) 578 { 579 mxcmci_read_response(host, stat); 580 host->cmd = NULL; 581 582 if (!host->data && host->req) { 583 mxcmci_finish_request(host, host->req); 584 return; 585 } 586 587 /* For the DMA case the DMA engine handles the data transfer 588 * automatically. For non DMA we have to do it ourselves. 589 * Don't do it in interrupt context though. 590 */ 591 if (!mxcmci_use_dma(host) && host->data) 592 schedule_work(&host->datawork); 593 594 } 595 596 static irqreturn_t mxcmci_irq(int irq, void *devid) 597 { 598 struct mxcmci_host *host = devid; 599 unsigned long flags; 600 bool sdio_irq; 601 u32 stat; 602 603 stat = readl(host->base + MMC_REG_STATUS); 604 writel(stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE | 605 STATUS_WRITE_OP_DONE), host->base + MMC_REG_STATUS); 606 607 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat); 608 609 spin_lock_irqsave(&host->lock, flags); 610 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio; 611 spin_unlock_irqrestore(&host->lock, flags); 612 613 if (mxcmci_use_dma(host) && 614 (stat & (STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE))) 615 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE, 616 host->base + MMC_REG_STATUS); 617 618 if (sdio_irq) { 619 writel(STATUS_SDIO_INT_ACTIVE, host->base + MMC_REG_STATUS); 620 mmc_signal_sdio_irq(host->mmc); 621 } 622 623 if (stat & STATUS_END_CMD_RESP) 624 mxcmci_cmd_done(host, stat); 625 626 if (mxcmci_use_dma(host) && 627 (stat & (STATUS_DATA_TRANS_DONE | STATUS_WRITE_OP_DONE))) 628 mxcmci_data_done(host, stat); 629 630 if (host->default_irq_mask && 631 (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL))) 632 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 633 634 return IRQ_HANDLED; 635 } 636 637 static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req) 638 { 639 struct mxcmci_host *host = mmc_priv(mmc); 640 unsigned int cmdat = host->cmdat; 641 int error; 642 643 WARN_ON(host->req != NULL); 644 645 host->req = req; 646 host->cmdat &= ~CMD_DAT_CONT_INIT; 647 648 if (host->dma) 649 host->do_dma = 1; 650 651 if (req->data) { 652 error = mxcmci_setup_data(host, req->data); 653 if (error) { 654 req->cmd->error = error; 655 goto out; 656 } 657 658 659 cmdat |= CMD_DAT_CONT_DATA_ENABLE; 660 661 if (req->data->flags & MMC_DATA_WRITE) 662 cmdat |= CMD_DAT_CONT_WRITE; 663 } 664 665 error = mxcmci_start_cmd(host, req->cmd, cmdat); 666 667 out: 668 if (error) 669 mxcmci_finish_request(host, req); 670 } 671 672 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios) 673 { 674 unsigned int divider; 675 int prescaler = 0; 676 unsigned int clk_in = clk_get_rate(host->clk_per); 677 678 while (prescaler <= 0x800) { 679 for (divider = 1; divider <= 0xF; divider++) { 680 int x; 681 682 x = (clk_in / (divider + 1)); 683 684 if (prescaler) 685 x /= (prescaler * 2); 686 687 if (x <= clk_ios) 688 break; 689 } 690 if (divider < 0x10) 691 break; 692 693 if (prescaler == 0) 694 prescaler = 1; 695 else 696 prescaler <<= 1; 697 } 698 699 writew((prescaler << 4) | divider, host->base + MMC_REG_CLK_RATE); 700 701 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n", 702 prescaler, divider, clk_in, clk_ios); 703 } 704 705 static int mxcmci_setup_dma(struct mmc_host *mmc) 706 { 707 struct mxcmci_host *host = mmc_priv(mmc); 708 struct dma_slave_config *config = &host->dma_slave_config; 709 710 config->dst_addr = host->res->start + MMC_REG_BUFFER_ACCESS; 711 config->src_addr = host->res->start + MMC_REG_BUFFER_ACCESS; 712 config->dst_addr_width = 4; 713 config->src_addr_width = 4; 714 config->dst_maxburst = host->burstlen; 715 config->src_maxburst = host->burstlen; 716 config->device_fc = false; 717 718 return dmaengine_slave_config(host->dma, config); 719 } 720 721 static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 722 { 723 struct mxcmci_host *host = mmc_priv(mmc); 724 int burstlen, ret; 725 726 /* 727 * use burstlen of 64 (16 words) in 4 bit mode (--> reg value 0) 728 * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16) 729 */ 730 if (ios->bus_width == MMC_BUS_WIDTH_4) 731 burstlen = 16; 732 else 733 burstlen = 4; 734 735 if (mxcmci_use_dma(host) && burstlen != host->burstlen) { 736 host->burstlen = burstlen; 737 ret = mxcmci_setup_dma(mmc); 738 if (ret) { 739 dev_err(mmc_dev(host->mmc), 740 "failed to config DMA channel. Falling back to PIO\n"); 741 dma_release_channel(host->dma); 742 host->do_dma = 0; 743 host->dma = NULL; 744 } 745 } 746 747 if (ios->bus_width == MMC_BUS_WIDTH_4) 748 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4; 749 else 750 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4; 751 752 if (host->power_mode != ios->power_mode) { 753 mxcmci_set_power(host, ios->power_mode, ios->vdd); 754 host->power_mode = ios->power_mode; 755 756 if (ios->power_mode == MMC_POWER_ON) 757 host->cmdat |= CMD_DAT_CONT_INIT; 758 } 759 760 if (ios->clock) { 761 mxcmci_set_clk_rate(host, ios->clock); 762 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK); 763 } else { 764 writew(STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK); 765 } 766 767 host->clock = ios->clock; 768 } 769 770 static irqreturn_t mxcmci_detect_irq(int irq, void *data) 771 { 772 struct mmc_host *mmc = data; 773 774 dev_dbg(mmc_dev(mmc), "%s\n", __func__); 775 776 mmc_detect_change(mmc, msecs_to_jiffies(250)); 777 return IRQ_HANDLED; 778 } 779 780 static int mxcmci_get_ro(struct mmc_host *mmc) 781 { 782 struct mxcmci_host *host = mmc_priv(mmc); 783 784 if (host->pdata && host->pdata->get_ro) 785 return !!host->pdata->get_ro(mmc_dev(mmc)); 786 /* 787 * Board doesn't support read only detection; let the mmc core 788 * decide what to do. 789 */ 790 return -ENOSYS; 791 } 792 793 static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable) 794 { 795 struct mxcmci_host *host = mmc_priv(mmc); 796 unsigned long flags; 797 u32 int_cntr; 798 799 spin_lock_irqsave(&host->lock, flags); 800 host->use_sdio = enable; 801 int_cntr = readl(host->base + MMC_REG_INT_CNTR); 802 803 if (enable) 804 int_cntr |= INT_SDIO_IRQ_EN; 805 else 806 int_cntr &= ~INT_SDIO_IRQ_EN; 807 808 writel(int_cntr, host->base + MMC_REG_INT_CNTR); 809 spin_unlock_irqrestore(&host->lock, flags); 810 } 811 812 static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card) 813 { 814 /* 815 * MX3 SoCs have a silicon bug which corrupts CRC calculation of 816 * multi-block transfers when connected SDIO peripheral doesn't 817 * drive the BUSY line as required by the specs. 818 * One way to prevent this is to only allow 1-bit transfers. 819 */ 820 821 if (cpu_is_mx3() && card->type == MMC_TYPE_SDIO) 822 host->caps &= ~MMC_CAP_4_BIT_DATA; 823 else 824 host->caps |= MMC_CAP_4_BIT_DATA; 825 } 826 827 static bool filter(struct dma_chan *chan, void *param) 828 { 829 struct mxcmci_host *host = param; 830 831 if (!imx_dma_is_general_purpose(chan)) 832 return false; 833 834 chan->private = &host->dma_data; 835 836 return true; 837 } 838 839 static const struct mmc_host_ops mxcmci_ops = { 840 .request = mxcmci_request, 841 .set_ios = mxcmci_set_ios, 842 .get_ro = mxcmci_get_ro, 843 .enable_sdio_irq = mxcmci_enable_sdio_irq, 844 .init_card = mxcmci_init_card, 845 }; 846 847 static int mxcmci_probe(struct platform_device *pdev) 848 { 849 struct mmc_host *mmc; 850 struct mxcmci_host *host = NULL; 851 struct resource *iores, *r; 852 int ret = 0, irq; 853 dma_cap_mask_t mask; 854 855 pr_info("i.MX SDHC driver\n"); 856 857 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 858 irq = platform_get_irq(pdev, 0); 859 if (!iores || irq < 0) 860 return -EINVAL; 861 862 r = request_mem_region(iores->start, resource_size(iores), pdev->name); 863 if (!r) 864 return -EBUSY; 865 866 mmc = mmc_alloc_host(sizeof(struct mxcmci_host), &pdev->dev); 867 if (!mmc) { 868 ret = -ENOMEM; 869 goto out_release_mem; 870 } 871 872 mmc->ops = &mxcmci_ops; 873 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; 874 875 /* MMC core transfer sizes tunable parameters */ 876 mmc->max_segs = 64; 877 mmc->max_blk_size = 2048; 878 mmc->max_blk_count = 65535; 879 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 880 mmc->max_seg_size = mmc->max_req_size; 881 882 host = mmc_priv(mmc); 883 host->base = ioremap(r->start, resource_size(r)); 884 if (!host->base) { 885 ret = -ENOMEM; 886 goto out_free; 887 } 888 889 host->mmc = mmc; 890 host->pdata = pdev->dev.platform_data; 891 spin_lock_init(&host->lock); 892 893 mxcmci_init_ocr(host); 894 895 if (host->pdata && host->pdata->dat3_card_detect) 896 host->default_irq_mask = 897 INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN; 898 else 899 host->default_irq_mask = 0; 900 901 host->res = r; 902 host->irq = irq; 903 904 host->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 905 if (IS_ERR(host->clk_ipg)) { 906 ret = PTR_ERR(host->clk_ipg); 907 goto out_iounmap; 908 } 909 910 host->clk_per = devm_clk_get(&pdev->dev, "per"); 911 if (IS_ERR(host->clk_per)) { 912 ret = PTR_ERR(host->clk_per); 913 goto out_iounmap; 914 } 915 916 clk_prepare_enable(host->clk_per); 917 clk_prepare_enable(host->clk_ipg); 918 919 mxcmci_softreset(host); 920 921 host->rev_no = readw(host->base + MMC_REG_REV_NO); 922 if (host->rev_no != 0x400) { 923 ret = -ENODEV; 924 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n", 925 host->rev_no); 926 goto out_clk_put; 927 } 928 929 mmc->f_min = clk_get_rate(host->clk_per) >> 16; 930 mmc->f_max = clk_get_rate(host->clk_per) >> 1; 931 932 /* recommended in data sheet */ 933 writew(0x2db4, host->base + MMC_REG_READ_TO); 934 935 writel(host->default_irq_mask, host->base + MMC_REG_INT_CNTR); 936 937 r = platform_get_resource(pdev, IORESOURCE_DMA, 0); 938 if (r) { 939 host->dmareq = r->start; 940 host->dma_data.peripheral_type = IMX_DMATYPE_SDHC; 941 host->dma_data.priority = DMA_PRIO_LOW; 942 host->dma_data.dma_request = host->dmareq; 943 dma_cap_zero(mask); 944 dma_cap_set(DMA_SLAVE, mask); 945 host->dma = dma_request_channel(mask, filter, host); 946 if (host->dma) 947 mmc->max_seg_size = dma_get_max_seg_size( 948 host->dma->device->dev); 949 } 950 951 if (!host->dma) 952 dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n"); 953 954 INIT_WORK(&host->datawork, mxcmci_datawork); 955 956 ret = request_irq(host->irq, mxcmci_irq, 0, DRIVER_NAME, host); 957 if (ret) 958 goto out_free_dma; 959 960 platform_set_drvdata(pdev, mmc); 961 962 if (host->pdata && host->pdata->init) { 963 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq, 964 host->mmc); 965 if (ret) 966 goto out_free_irq; 967 } 968 969 mmc_add_host(mmc); 970 971 return 0; 972 973 out_free_irq: 974 free_irq(host->irq, host); 975 out_free_dma: 976 if (host->dma) 977 dma_release_channel(host->dma); 978 out_clk_put: 979 clk_disable_unprepare(host->clk_per); 980 clk_disable_unprepare(host->clk_ipg); 981 out_iounmap: 982 iounmap(host->base); 983 out_free: 984 mmc_free_host(mmc); 985 out_release_mem: 986 release_mem_region(iores->start, resource_size(iores)); 987 return ret; 988 } 989 990 static int mxcmci_remove(struct platform_device *pdev) 991 { 992 struct mmc_host *mmc = platform_get_drvdata(pdev); 993 struct mxcmci_host *host = mmc_priv(mmc); 994 995 platform_set_drvdata(pdev, NULL); 996 997 mmc_remove_host(mmc); 998 999 if (host->vcc) 1000 regulator_put(host->vcc); 1001 1002 if (host->pdata && host->pdata->exit) 1003 host->pdata->exit(&pdev->dev, mmc); 1004 1005 free_irq(host->irq, host); 1006 iounmap(host->base); 1007 1008 if (host->dma) 1009 dma_release_channel(host->dma); 1010 1011 clk_disable_unprepare(host->clk_per); 1012 clk_disable_unprepare(host->clk_ipg); 1013 1014 release_mem_region(host->res->start, resource_size(host->res)); 1015 1016 mmc_free_host(mmc); 1017 1018 return 0; 1019 } 1020 1021 #ifdef CONFIG_PM 1022 static int mxcmci_suspend(struct device *dev) 1023 { 1024 struct mmc_host *mmc = dev_get_drvdata(dev); 1025 struct mxcmci_host *host = mmc_priv(mmc); 1026 int ret = 0; 1027 1028 if (mmc) 1029 ret = mmc_suspend_host(mmc); 1030 clk_disable_unprepare(host->clk_per); 1031 clk_disable_unprepare(host->clk_ipg); 1032 1033 return ret; 1034 } 1035 1036 static int mxcmci_resume(struct device *dev) 1037 { 1038 struct mmc_host *mmc = dev_get_drvdata(dev); 1039 struct mxcmci_host *host = mmc_priv(mmc); 1040 int ret = 0; 1041 1042 clk_prepare_enable(host->clk_per); 1043 clk_prepare_enable(host->clk_ipg); 1044 if (mmc) 1045 ret = mmc_resume_host(mmc); 1046 1047 return ret; 1048 } 1049 1050 static const struct dev_pm_ops mxcmci_pm_ops = { 1051 .suspend = mxcmci_suspend, 1052 .resume = mxcmci_resume, 1053 }; 1054 #endif 1055 1056 static struct platform_driver mxcmci_driver = { 1057 .probe = mxcmci_probe, 1058 .remove = mxcmci_remove, 1059 .driver = { 1060 .name = DRIVER_NAME, 1061 .owner = THIS_MODULE, 1062 #ifdef CONFIG_PM 1063 .pm = &mxcmci_pm_ops, 1064 #endif 1065 } 1066 }; 1067 1068 module_platform_driver(mxcmci_driver); 1069 1070 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver"); 1071 MODULE_AUTHOR("Sascha Hauer, Pengutronix"); 1072 MODULE_LICENSE("GPL"); 1073 MODULE_ALIAS("platform:imx-mmc"); 1074