1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver 4 * 5 * This is a driver for the SDHC controller found in Freescale MX2/MX3 6 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c). 7 * Unlike the hardware found on MX1, this hardware just works and does 8 * not need all the quirks found in imxmmc.c, hence the separate driver. 9 * 10 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> 11 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com> 12 * 13 * derived from pxamci.c by Russell King 14 */ 15 16 #include <linux/module.h> 17 #include <linux/init.h> 18 #include <linux/ioport.h> 19 #include <linux/platform_device.h> 20 #include <linux/highmem.h> 21 #include <linux/interrupt.h> 22 #include <linux/irq.h> 23 #include <linux/blkdev.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/mmc/host.h> 26 #include <linux/mmc/card.h> 27 #include <linux/delay.h> 28 #include <linux/clk.h> 29 #include <linux/io.h> 30 #include <linux/regulator/consumer.h> 31 #include <linux/dmaengine.h> 32 #include <linux/types.h> 33 #include <linux/of.h> 34 #include <linux/of_device.h> 35 #include <linux/of_dma.h> 36 #include <linux/mmc/slot-gpio.h> 37 38 #include <asm/dma.h> 39 #include <asm/irq.h> 40 #include <linux/platform_data/mmc-mxcmmc.h> 41 42 #include <linux/platform_data/dma-imx.h> 43 44 #define DRIVER_NAME "mxc-mmc" 45 #define MXCMCI_TIMEOUT_MS 10000 46 47 #define MMC_REG_STR_STP_CLK 0x00 48 #define MMC_REG_STATUS 0x04 49 #define MMC_REG_CLK_RATE 0x08 50 #define MMC_REG_CMD_DAT_CONT 0x0C 51 #define MMC_REG_RES_TO 0x10 52 #define MMC_REG_READ_TO 0x14 53 #define MMC_REG_BLK_LEN 0x18 54 #define MMC_REG_NOB 0x1C 55 #define MMC_REG_REV_NO 0x20 56 #define MMC_REG_INT_CNTR 0x24 57 #define MMC_REG_CMD 0x28 58 #define MMC_REG_ARG 0x2C 59 #define MMC_REG_RES_FIFO 0x34 60 #define MMC_REG_BUFFER_ACCESS 0x38 61 62 #define STR_STP_CLK_RESET (1 << 3) 63 #define STR_STP_CLK_START_CLK (1 << 1) 64 #define STR_STP_CLK_STOP_CLK (1 << 0) 65 66 #define STATUS_CARD_INSERTION (1 << 31) 67 #define STATUS_CARD_REMOVAL (1 << 30) 68 #define STATUS_YBUF_EMPTY (1 << 29) 69 #define STATUS_XBUF_EMPTY (1 << 28) 70 #define STATUS_YBUF_FULL (1 << 27) 71 #define STATUS_XBUF_FULL (1 << 26) 72 #define STATUS_BUF_UND_RUN (1 << 25) 73 #define STATUS_BUF_OVFL (1 << 24) 74 #define STATUS_SDIO_INT_ACTIVE (1 << 14) 75 #define STATUS_END_CMD_RESP (1 << 13) 76 #define STATUS_WRITE_OP_DONE (1 << 12) 77 #define STATUS_DATA_TRANS_DONE (1 << 11) 78 #define STATUS_READ_OP_DONE (1 << 11) 79 #define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10) 80 #define STATUS_CARD_BUS_CLK_RUN (1 << 8) 81 #define STATUS_BUF_READ_RDY (1 << 7) 82 #define STATUS_BUF_WRITE_RDY (1 << 6) 83 #define STATUS_RESP_CRC_ERR (1 << 5) 84 #define STATUS_CRC_READ_ERR (1 << 3) 85 #define STATUS_CRC_WRITE_ERR (1 << 2) 86 #define STATUS_TIME_OUT_RESP (1 << 1) 87 #define STATUS_TIME_OUT_READ (1 << 0) 88 #define STATUS_ERR_MASK 0x2f 89 90 #define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12) 91 #define CMD_DAT_CONT_STOP_READWAIT (1 << 11) 92 #define CMD_DAT_CONT_START_READWAIT (1 << 10) 93 #define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8) 94 #define CMD_DAT_CONT_INIT (1 << 7) 95 #define CMD_DAT_CONT_WRITE (1 << 4) 96 #define CMD_DAT_CONT_DATA_ENABLE (1 << 3) 97 #define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0) 98 #define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0) 99 #define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0) 100 101 #define INT_SDIO_INT_WKP_EN (1 << 18) 102 #define INT_CARD_INSERTION_WKP_EN (1 << 17) 103 #define INT_CARD_REMOVAL_WKP_EN (1 << 16) 104 #define INT_CARD_INSERTION_EN (1 << 15) 105 #define INT_CARD_REMOVAL_EN (1 << 14) 106 #define INT_SDIO_IRQ_EN (1 << 13) 107 #define INT_DAT0_EN (1 << 12) 108 #define INT_BUF_READ_EN (1 << 4) 109 #define INT_BUF_WRITE_EN (1 << 3) 110 #define INT_END_CMD_RES_EN (1 << 2) 111 #define INT_WRITE_OP_DONE_EN (1 << 1) 112 #define INT_READ_OP_EN (1 << 0) 113 114 enum mxcmci_type { 115 IMX21_MMC, 116 IMX31_MMC, 117 MPC512X_MMC, 118 }; 119 120 struct mxcmci_host { 121 struct mmc_host *mmc; 122 void __iomem *base; 123 dma_addr_t phys_base; 124 int detect_irq; 125 struct dma_chan *dma; 126 struct dma_async_tx_descriptor *desc; 127 int do_dma; 128 int default_irq_mask; 129 int use_sdio; 130 unsigned int power_mode; 131 struct imxmmc_platform_data *pdata; 132 133 struct mmc_request *req; 134 struct mmc_command *cmd; 135 struct mmc_data *data; 136 137 unsigned int datasize; 138 unsigned int dma_dir; 139 140 u16 rev_no; 141 unsigned int cmdat; 142 143 struct clk *clk_ipg; 144 struct clk *clk_per; 145 146 int clock; 147 148 struct work_struct datawork; 149 spinlock_t lock; 150 151 int burstlen; 152 int dmareq; 153 struct dma_slave_config dma_slave_config; 154 struct imx_dma_data dma_data; 155 156 struct timer_list watchdog; 157 enum mxcmci_type devtype; 158 }; 159 160 static const struct of_device_id mxcmci_of_match[] = { 161 { 162 .compatible = "fsl,imx21-mmc", 163 .data = (void *) IMX21_MMC, 164 }, { 165 .compatible = "fsl,imx31-mmc", 166 .data = (void *) IMX31_MMC, 167 }, { 168 .compatible = "fsl,mpc5121-sdhc", 169 .data = (void *) MPC512X_MMC, 170 }, { 171 /* sentinel */ 172 } 173 }; 174 MODULE_DEVICE_TABLE(of, mxcmci_of_match); 175 176 static inline int is_imx31_mmc(struct mxcmci_host *host) 177 { 178 return host->devtype == IMX31_MMC; 179 } 180 181 static inline int is_mpc512x_mmc(struct mxcmci_host *host) 182 { 183 return host->devtype == MPC512X_MMC; 184 } 185 186 static inline u32 mxcmci_readl(struct mxcmci_host *host, int reg) 187 { 188 if (IS_ENABLED(CONFIG_PPC_MPC512x)) 189 return ioread32be(host->base + reg); 190 else 191 return readl(host->base + reg); 192 } 193 194 static inline void mxcmci_writel(struct mxcmci_host *host, u32 val, int reg) 195 { 196 if (IS_ENABLED(CONFIG_PPC_MPC512x)) 197 iowrite32be(val, host->base + reg); 198 else 199 writel(val, host->base + reg); 200 } 201 202 static inline u16 mxcmci_readw(struct mxcmci_host *host, int reg) 203 { 204 if (IS_ENABLED(CONFIG_PPC_MPC512x)) 205 return ioread32be(host->base + reg); 206 else 207 return readw(host->base + reg); 208 } 209 210 static inline void mxcmci_writew(struct mxcmci_host *host, u16 val, int reg) 211 { 212 if (IS_ENABLED(CONFIG_PPC_MPC512x)) 213 iowrite32be(val, host->base + reg); 214 else 215 writew(val, host->base + reg); 216 } 217 218 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios); 219 220 static void mxcmci_set_power(struct mxcmci_host *host, unsigned int vdd) 221 { 222 if (!IS_ERR(host->mmc->supply.vmmc)) { 223 if (host->power_mode == MMC_POWER_UP) 224 mmc_regulator_set_ocr(host->mmc, 225 host->mmc->supply.vmmc, vdd); 226 else if (host->power_mode == MMC_POWER_OFF) 227 mmc_regulator_set_ocr(host->mmc, 228 host->mmc->supply.vmmc, 0); 229 } 230 231 if (host->pdata && host->pdata->setpower) 232 host->pdata->setpower(mmc_dev(host->mmc), vdd); 233 } 234 235 static inline int mxcmci_use_dma(struct mxcmci_host *host) 236 { 237 return host->do_dma; 238 } 239 240 static void mxcmci_softreset(struct mxcmci_host *host) 241 { 242 int i; 243 244 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n"); 245 246 /* reset sequence */ 247 mxcmci_writew(host, STR_STP_CLK_RESET, MMC_REG_STR_STP_CLK); 248 mxcmci_writew(host, STR_STP_CLK_RESET | STR_STP_CLK_START_CLK, 249 MMC_REG_STR_STP_CLK); 250 251 for (i = 0; i < 8; i++) 252 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK); 253 254 mxcmci_writew(host, 0xff, MMC_REG_RES_TO); 255 } 256 257 #if IS_ENABLED(CONFIG_PPC_MPC512x) 258 static inline void buffer_swap32(u32 *buf, int len) 259 { 260 int i; 261 262 for (i = 0; i < ((len + 3) / 4); i++) { 263 *buf = swab32(*buf); 264 buf++; 265 } 266 } 267 268 static void mxcmci_swap_buffers(struct mmc_data *data) 269 { 270 struct scatterlist *sg; 271 int i; 272 273 for_each_sg(data->sg, sg, data->sg_len, i) 274 buffer_swap32(sg_virt(sg), sg->length); 275 } 276 #else 277 static inline void mxcmci_swap_buffers(struct mmc_data *data) {} 278 #endif 279 280 static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data) 281 { 282 unsigned int nob = data->blocks; 283 unsigned int blksz = data->blksz; 284 unsigned int datasize = nob * blksz; 285 struct scatterlist *sg; 286 enum dma_transfer_direction slave_dirn; 287 int i, nents; 288 289 host->data = data; 290 data->bytes_xfered = 0; 291 292 mxcmci_writew(host, nob, MMC_REG_NOB); 293 mxcmci_writew(host, blksz, MMC_REG_BLK_LEN); 294 host->datasize = datasize; 295 296 if (!mxcmci_use_dma(host)) 297 return 0; 298 299 for_each_sg(data->sg, sg, data->sg_len, i) { 300 if (sg->offset & 3 || sg->length & 3 || sg->length < 512) { 301 host->do_dma = 0; 302 return 0; 303 } 304 } 305 306 if (data->flags & MMC_DATA_READ) { 307 host->dma_dir = DMA_FROM_DEVICE; 308 slave_dirn = DMA_DEV_TO_MEM; 309 } else { 310 host->dma_dir = DMA_TO_DEVICE; 311 slave_dirn = DMA_MEM_TO_DEV; 312 313 mxcmci_swap_buffers(data); 314 } 315 316 nents = dma_map_sg(host->dma->device->dev, data->sg, 317 data->sg_len, host->dma_dir); 318 if (nents != data->sg_len) 319 return -EINVAL; 320 321 host->desc = dmaengine_prep_slave_sg(host->dma, 322 data->sg, data->sg_len, slave_dirn, 323 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 324 325 if (!host->desc) { 326 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len, 327 host->dma_dir); 328 host->do_dma = 0; 329 return 0; /* Fall back to PIO */ 330 } 331 wmb(); 332 333 dmaengine_submit(host->desc); 334 dma_async_issue_pending(host->dma); 335 336 mod_timer(&host->watchdog, jiffies + msecs_to_jiffies(MXCMCI_TIMEOUT_MS)); 337 338 return 0; 339 } 340 341 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat); 342 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat); 343 344 static void mxcmci_dma_callback(void *data) 345 { 346 struct mxcmci_host *host = data; 347 u32 stat; 348 349 del_timer(&host->watchdog); 350 351 stat = mxcmci_readl(host, MMC_REG_STATUS); 352 353 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat); 354 355 mxcmci_data_done(host, stat); 356 } 357 358 static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd, 359 unsigned int cmdat) 360 { 361 u32 int_cntr = host->default_irq_mask; 362 unsigned long flags; 363 364 WARN_ON(host->cmd != NULL); 365 host->cmd = cmd; 366 367 switch (mmc_resp_type(cmd)) { 368 case MMC_RSP_R1: /* short CRC, OPCODE */ 369 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */ 370 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC; 371 break; 372 case MMC_RSP_R2: /* long 136 bit + CRC */ 373 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT; 374 break; 375 case MMC_RSP_R3: /* short */ 376 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT; 377 break; 378 case MMC_RSP_NONE: 379 break; 380 default: 381 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n", 382 mmc_resp_type(cmd)); 383 cmd->error = -EINVAL; 384 return -EINVAL; 385 } 386 387 int_cntr = INT_END_CMD_RES_EN; 388 389 if (mxcmci_use_dma(host)) { 390 if (host->dma_dir == DMA_FROM_DEVICE) { 391 host->desc->callback = mxcmci_dma_callback; 392 host->desc->callback_param = host; 393 } else { 394 int_cntr |= INT_WRITE_OP_DONE_EN; 395 } 396 } 397 398 spin_lock_irqsave(&host->lock, flags); 399 if (host->use_sdio) 400 int_cntr |= INT_SDIO_IRQ_EN; 401 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR); 402 spin_unlock_irqrestore(&host->lock, flags); 403 404 mxcmci_writew(host, cmd->opcode, MMC_REG_CMD); 405 mxcmci_writel(host, cmd->arg, MMC_REG_ARG); 406 mxcmci_writew(host, cmdat, MMC_REG_CMD_DAT_CONT); 407 408 return 0; 409 } 410 411 static void mxcmci_finish_request(struct mxcmci_host *host, 412 struct mmc_request *req) 413 { 414 u32 int_cntr = host->default_irq_mask; 415 unsigned long flags; 416 417 spin_lock_irqsave(&host->lock, flags); 418 if (host->use_sdio) 419 int_cntr |= INT_SDIO_IRQ_EN; 420 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR); 421 spin_unlock_irqrestore(&host->lock, flags); 422 423 host->req = NULL; 424 host->cmd = NULL; 425 host->data = NULL; 426 427 mmc_request_done(host->mmc, req); 428 } 429 430 static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat) 431 { 432 struct mmc_data *data = host->data; 433 int data_error; 434 435 if (mxcmci_use_dma(host)) { 436 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len, 437 host->dma_dir); 438 mxcmci_swap_buffers(data); 439 } 440 441 if (stat & STATUS_ERR_MASK) { 442 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n", 443 stat); 444 if (stat & STATUS_CRC_READ_ERR) { 445 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__); 446 data->error = -EILSEQ; 447 } else if (stat & STATUS_CRC_WRITE_ERR) { 448 u32 err_code = (stat >> 9) & 0x3; 449 if (err_code == 2) { /* No CRC response */ 450 dev_err(mmc_dev(host->mmc), 451 "%s: No CRC -ETIMEDOUT\n", __func__); 452 data->error = -ETIMEDOUT; 453 } else { 454 dev_err(mmc_dev(host->mmc), 455 "%s: -EILSEQ\n", __func__); 456 data->error = -EILSEQ; 457 } 458 } else if (stat & STATUS_TIME_OUT_READ) { 459 dev_err(mmc_dev(host->mmc), 460 "%s: read -ETIMEDOUT\n", __func__); 461 data->error = -ETIMEDOUT; 462 } else { 463 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__); 464 data->error = -EIO; 465 } 466 } else { 467 data->bytes_xfered = host->datasize; 468 } 469 470 data_error = data->error; 471 472 host->data = NULL; 473 474 return data_error; 475 } 476 477 static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat) 478 { 479 struct mmc_command *cmd = host->cmd; 480 int i; 481 u32 a, b, c; 482 483 if (!cmd) 484 return; 485 486 if (stat & STATUS_TIME_OUT_RESP) { 487 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n"); 488 cmd->error = -ETIMEDOUT; 489 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) { 490 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n"); 491 cmd->error = -EILSEQ; 492 } 493 494 if (cmd->flags & MMC_RSP_PRESENT) { 495 if (cmd->flags & MMC_RSP_136) { 496 for (i = 0; i < 4; i++) { 497 a = mxcmci_readw(host, MMC_REG_RES_FIFO); 498 b = mxcmci_readw(host, MMC_REG_RES_FIFO); 499 cmd->resp[i] = a << 16 | b; 500 } 501 } else { 502 a = mxcmci_readw(host, MMC_REG_RES_FIFO); 503 b = mxcmci_readw(host, MMC_REG_RES_FIFO); 504 c = mxcmci_readw(host, MMC_REG_RES_FIFO); 505 cmd->resp[0] = a << 24 | b << 8 | c >> 8; 506 } 507 } 508 } 509 510 static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask) 511 { 512 u32 stat; 513 unsigned long timeout = jiffies + HZ; 514 515 do { 516 stat = mxcmci_readl(host, MMC_REG_STATUS); 517 if (stat & STATUS_ERR_MASK) 518 return stat; 519 if (time_after(jiffies, timeout)) { 520 mxcmci_softreset(host); 521 mxcmci_set_clk_rate(host, host->clock); 522 return STATUS_TIME_OUT_READ; 523 } 524 if (stat & mask) 525 return 0; 526 cpu_relax(); 527 } while (1); 528 } 529 530 static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes) 531 { 532 unsigned int stat; 533 u32 *buf = _buf; 534 535 while (bytes > 3) { 536 stat = mxcmci_poll_status(host, 537 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE); 538 if (stat) 539 return stat; 540 *buf++ = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS)); 541 bytes -= 4; 542 } 543 544 if (bytes) { 545 u8 *b = (u8 *)buf; 546 u32 tmp; 547 548 stat = mxcmci_poll_status(host, 549 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE); 550 if (stat) 551 return stat; 552 tmp = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS)); 553 memcpy(b, &tmp, bytes); 554 } 555 556 return 0; 557 } 558 559 static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes) 560 { 561 unsigned int stat; 562 u32 *buf = _buf; 563 564 while (bytes > 3) { 565 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 566 if (stat) 567 return stat; 568 mxcmci_writel(host, cpu_to_le32(*buf++), MMC_REG_BUFFER_ACCESS); 569 bytes -= 4; 570 } 571 572 if (bytes) { 573 u8 *b = (u8 *)buf; 574 u32 tmp; 575 576 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 577 if (stat) 578 return stat; 579 580 memcpy(&tmp, b, bytes); 581 mxcmci_writel(host, cpu_to_le32(tmp), MMC_REG_BUFFER_ACCESS); 582 } 583 584 return mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 585 } 586 587 static int mxcmci_transfer_data(struct mxcmci_host *host) 588 { 589 struct mmc_data *data = host->req->data; 590 struct scatterlist *sg; 591 int stat, i; 592 593 host->data = data; 594 host->datasize = 0; 595 596 if (data->flags & MMC_DATA_READ) { 597 for_each_sg(data->sg, sg, data->sg_len, i) { 598 stat = mxcmci_pull(host, sg_virt(sg), sg->length); 599 if (stat) 600 return stat; 601 host->datasize += sg->length; 602 } 603 } else { 604 for_each_sg(data->sg, sg, data->sg_len, i) { 605 stat = mxcmci_push(host, sg_virt(sg), sg->length); 606 if (stat) 607 return stat; 608 host->datasize += sg->length; 609 } 610 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE); 611 if (stat) 612 return stat; 613 } 614 return 0; 615 } 616 617 static void mxcmci_datawork(struct work_struct *work) 618 { 619 struct mxcmci_host *host = container_of(work, struct mxcmci_host, 620 datawork); 621 int datastat = mxcmci_transfer_data(host); 622 623 mxcmci_writel(host, STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE, 624 MMC_REG_STATUS); 625 mxcmci_finish_data(host, datastat); 626 627 if (host->req->stop) { 628 if (mxcmci_start_cmd(host, host->req->stop, 0)) { 629 mxcmci_finish_request(host, host->req); 630 return; 631 } 632 } else { 633 mxcmci_finish_request(host, host->req); 634 } 635 } 636 637 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat) 638 { 639 struct mmc_request *req; 640 int data_error; 641 unsigned long flags; 642 643 spin_lock_irqsave(&host->lock, flags); 644 645 if (!host->data) { 646 spin_unlock_irqrestore(&host->lock, flags); 647 return; 648 } 649 650 if (!host->req) { 651 spin_unlock_irqrestore(&host->lock, flags); 652 return; 653 } 654 655 req = host->req; 656 if (!req->stop) 657 host->req = NULL; /* we will handle finish req below */ 658 659 data_error = mxcmci_finish_data(host, stat); 660 661 spin_unlock_irqrestore(&host->lock, flags); 662 663 if (data_error) 664 return; 665 666 mxcmci_read_response(host, stat); 667 host->cmd = NULL; 668 669 if (req->stop) { 670 if (mxcmci_start_cmd(host, req->stop, 0)) { 671 mxcmci_finish_request(host, req); 672 return; 673 } 674 } else { 675 mxcmci_finish_request(host, req); 676 } 677 } 678 679 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat) 680 { 681 mxcmci_read_response(host, stat); 682 host->cmd = NULL; 683 684 if (!host->data && host->req) { 685 mxcmci_finish_request(host, host->req); 686 return; 687 } 688 689 /* For the DMA case the DMA engine handles the data transfer 690 * automatically. For non DMA we have to do it ourselves. 691 * Don't do it in interrupt context though. 692 */ 693 if (!mxcmci_use_dma(host) && host->data) 694 schedule_work(&host->datawork); 695 696 } 697 698 static irqreturn_t mxcmci_irq(int irq, void *devid) 699 { 700 struct mxcmci_host *host = devid; 701 bool sdio_irq; 702 u32 stat; 703 704 stat = mxcmci_readl(host, MMC_REG_STATUS); 705 mxcmci_writel(host, 706 stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE | 707 STATUS_WRITE_OP_DONE), 708 MMC_REG_STATUS); 709 710 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat); 711 712 spin_lock(&host->lock); 713 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio; 714 spin_unlock(&host->lock); 715 716 if (mxcmci_use_dma(host) && (stat & (STATUS_WRITE_OP_DONE))) 717 mxcmci_writel(host, STATUS_WRITE_OP_DONE, MMC_REG_STATUS); 718 719 if (sdio_irq) { 720 mxcmci_writel(host, STATUS_SDIO_INT_ACTIVE, MMC_REG_STATUS); 721 mmc_signal_sdio_irq(host->mmc); 722 } 723 724 if (stat & STATUS_END_CMD_RESP) 725 mxcmci_cmd_done(host, stat); 726 727 if (mxcmci_use_dma(host) && (stat & STATUS_WRITE_OP_DONE)) { 728 del_timer(&host->watchdog); 729 mxcmci_data_done(host, stat); 730 } 731 732 if (host->default_irq_mask && 733 (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL))) 734 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 735 736 return IRQ_HANDLED; 737 } 738 739 static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req) 740 { 741 struct mxcmci_host *host = mmc_priv(mmc); 742 unsigned int cmdat = host->cmdat; 743 int error; 744 745 WARN_ON(host->req != NULL); 746 747 host->req = req; 748 host->cmdat &= ~CMD_DAT_CONT_INIT; 749 750 if (host->dma) 751 host->do_dma = 1; 752 753 if (req->data) { 754 error = mxcmci_setup_data(host, req->data); 755 if (error) { 756 req->cmd->error = error; 757 goto out; 758 } 759 760 761 cmdat |= CMD_DAT_CONT_DATA_ENABLE; 762 763 if (req->data->flags & MMC_DATA_WRITE) 764 cmdat |= CMD_DAT_CONT_WRITE; 765 } 766 767 error = mxcmci_start_cmd(host, req->cmd, cmdat); 768 769 out: 770 if (error) 771 mxcmci_finish_request(host, req); 772 } 773 774 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios) 775 { 776 unsigned int divider; 777 int prescaler = 0; 778 unsigned int clk_in = clk_get_rate(host->clk_per); 779 780 while (prescaler <= 0x800) { 781 for (divider = 1; divider <= 0xF; divider++) { 782 int x; 783 784 x = (clk_in / (divider + 1)); 785 786 if (prescaler) 787 x /= (prescaler * 2); 788 789 if (x <= clk_ios) 790 break; 791 } 792 if (divider < 0x10) 793 break; 794 795 if (prescaler == 0) 796 prescaler = 1; 797 else 798 prescaler <<= 1; 799 } 800 801 mxcmci_writew(host, (prescaler << 4) | divider, MMC_REG_CLK_RATE); 802 803 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n", 804 prescaler, divider, clk_in, clk_ios); 805 } 806 807 static int mxcmci_setup_dma(struct mmc_host *mmc) 808 { 809 struct mxcmci_host *host = mmc_priv(mmc); 810 struct dma_slave_config *config = &host->dma_slave_config; 811 812 config->dst_addr = host->phys_base + MMC_REG_BUFFER_ACCESS; 813 config->src_addr = host->phys_base + MMC_REG_BUFFER_ACCESS; 814 config->dst_addr_width = 4; 815 config->src_addr_width = 4; 816 config->dst_maxburst = host->burstlen; 817 config->src_maxburst = host->burstlen; 818 config->device_fc = false; 819 820 return dmaengine_slave_config(host->dma, config); 821 } 822 823 static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 824 { 825 struct mxcmci_host *host = mmc_priv(mmc); 826 int burstlen, ret; 827 828 /* 829 * use burstlen of 64 (16 words) in 4 bit mode (--> reg value 0) 830 * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16) 831 */ 832 if (ios->bus_width == MMC_BUS_WIDTH_4) 833 burstlen = 16; 834 else 835 burstlen = 4; 836 837 if (mxcmci_use_dma(host) && burstlen != host->burstlen) { 838 host->burstlen = burstlen; 839 ret = mxcmci_setup_dma(mmc); 840 if (ret) { 841 dev_err(mmc_dev(host->mmc), 842 "failed to config DMA channel. Falling back to PIO\n"); 843 dma_release_channel(host->dma); 844 host->do_dma = 0; 845 host->dma = NULL; 846 } 847 } 848 849 if (ios->bus_width == MMC_BUS_WIDTH_4) 850 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4; 851 else 852 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4; 853 854 if (host->power_mode != ios->power_mode) { 855 host->power_mode = ios->power_mode; 856 mxcmci_set_power(host, ios->vdd); 857 858 if (ios->power_mode == MMC_POWER_ON) 859 host->cmdat |= CMD_DAT_CONT_INIT; 860 } 861 862 if (ios->clock) { 863 mxcmci_set_clk_rate(host, ios->clock); 864 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK); 865 } else { 866 mxcmci_writew(host, STR_STP_CLK_STOP_CLK, MMC_REG_STR_STP_CLK); 867 } 868 869 host->clock = ios->clock; 870 } 871 872 static irqreturn_t mxcmci_detect_irq(int irq, void *data) 873 { 874 struct mmc_host *mmc = data; 875 876 dev_dbg(mmc_dev(mmc), "%s\n", __func__); 877 878 mmc_detect_change(mmc, msecs_to_jiffies(250)); 879 return IRQ_HANDLED; 880 } 881 882 static int mxcmci_get_ro(struct mmc_host *mmc) 883 { 884 struct mxcmci_host *host = mmc_priv(mmc); 885 886 if (host->pdata && host->pdata->get_ro) 887 return !!host->pdata->get_ro(mmc_dev(mmc)); 888 /* 889 * If board doesn't support read only detection (no mmc_gpio 890 * context or gpio is invalid), then let the mmc core decide 891 * what to do. 892 */ 893 return mmc_gpio_get_ro(mmc); 894 } 895 896 static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable) 897 { 898 struct mxcmci_host *host = mmc_priv(mmc); 899 unsigned long flags; 900 u32 int_cntr; 901 902 spin_lock_irqsave(&host->lock, flags); 903 host->use_sdio = enable; 904 int_cntr = mxcmci_readl(host, MMC_REG_INT_CNTR); 905 906 if (enable) 907 int_cntr |= INT_SDIO_IRQ_EN; 908 else 909 int_cntr &= ~INT_SDIO_IRQ_EN; 910 911 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR); 912 spin_unlock_irqrestore(&host->lock, flags); 913 } 914 915 static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card) 916 { 917 struct mxcmci_host *mxcmci = mmc_priv(host); 918 919 /* 920 * MX3 SoCs have a silicon bug which corrupts CRC calculation of 921 * multi-block transfers when connected SDIO peripheral doesn't 922 * drive the BUSY line as required by the specs. 923 * One way to prevent this is to only allow 1-bit transfers. 924 */ 925 926 if (is_imx31_mmc(mxcmci) && card->type == MMC_TYPE_SDIO) 927 host->caps &= ~MMC_CAP_4_BIT_DATA; 928 else 929 host->caps |= MMC_CAP_4_BIT_DATA; 930 } 931 932 static bool filter(struct dma_chan *chan, void *param) 933 { 934 struct mxcmci_host *host = param; 935 936 if (!imx_dma_is_general_purpose(chan)) 937 return false; 938 939 chan->private = &host->dma_data; 940 941 return true; 942 } 943 944 static void mxcmci_watchdog(struct timer_list *t) 945 { 946 struct mxcmci_host *host = from_timer(host, t, watchdog); 947 struct mmc_request *req = host->req; 948 unsigned int stat = mxcmci_readl(host, MMC_REG_STATUS); 949 950 if (host->dma_dir == DMA_FROM_DEVICE) { 951 dmaengine_terminate_all(host->dma); 952 dev_err(mmc_dev(host->mmc), 953 "%s: read time out (status = 0x%08x)\n", 954 __func__, stat); 955 } else { 956 dev_err(mmc_dev(host->mmc), 957 "%s: write time out (status = 0x%08x)\n", 958 __func__, stat); 959 mxcmci_softreset(host); 960 } 961 962 /* Mark transfer as erroneus and inform the upper layers */ 963 964 if (host->data) 965 host->data->error = -ETIMEDOUT; 966 host->req = NULL; 967 host->cmd = NULL; 968 host->data = NULL; 969 mmc_request_done(host->mmc, req); 970 } 971 972 static const struct mmc_host_ops mxcmci_ops = { 973 .request = mxcmci_request, 974 .set_ios = mxcmci_set_ios, 975 .get_ro = mxcmci_get_ro, 976 .enable_sdio_irq = mxcmci_enable_sdio_irq, 977 .init_card = mxcmci_init_card, 978 }; 979 980 static int mxcmci_probe(struct platform_device *pdev) 981 { 982 struct mmc_host *mmc; 983 struct mxcmci_host *host; 984 struct resource *res; 985 int ret = 0, irq; 986 bool dat3_card_detect = false; 987 dma_cap_mask_t mask; 988 struct imxmmc_platform_data *pdata = pdev->dev.platform_data; 989 990 pr_info("i.MX/MPC512x SDHC driver\n"); 991 992 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 993 irq = platform_get_irq(pdev, 0); 994 if (irq < 0) 995 return irq; 996 997 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); 998 if (!mmc) 999 return -ENOMEM; 1000 1001 host = mmc_priv(mmc); 1002 1003 host->base = devm_ioremap_resource(&pdev->dev, res); 1004 if (IS_ERR(host->base)) { 1005 ret = PTR_ERR(host->base); 1006 goto out_free; 1007 } 1008 1009 host->phys_base = res->start; 1010 1011 ret = mmc_of_parse(mmc); 1012 if (ret) 1013 goto out_free; 1014 mmc->ops = &mxcmci_ops; 1015 1016 /* For devicetree parsing, the bus width is read from devicetree */ 1017 if (pdata) 1018 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; 1019 else 1020 mmc->caps |= MMC_CAP_SDIO_IRQ; 1021 1022 /* MMC core transfer sizes tunable parameters */ 1023 mmc->max_blk_size = 2048; 1024 mmc->max_blk_count = 65535; 1025 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1026 mmc->max_seg_size = mmc->max_req_size; 1027 1028 host->devtype = (enum mxcmci_type)of_device_get_match_data(&pdev->dev); 1029 1030 /* adjust max_segs after devtype detection */ 1031 if (!is_mpc512x_mmc(host)) 1032 mmc->max_segs = 64; 1033 1034 host->mmc = mmc; 1035 host->pdata = pdata; 1036 spin_lock_init(&host->lock); 1037 1038 if (pdata) 1039 dat3_card_detect = pdata->dat3_card_detect; 1040 else if (mmc_card_is_removable(mmc) 1041 && !of_property_read_bool(pdev->dev.of_node, "cd-gpios")) 1042 dat3_card_detect = true; 1043 1044 ret = mmc_regulator_get_supply(mmc); 1045 if (ret) 1046 goto out_free; 1047 1048 if (!mmc->ocr_avail) { 1049 if (pdata && pdata->ocr_avail) 1050 mmc->ocr_avail = pdata->ocr_avail; 1051 else 1052 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1053 } 1054 1055 if (dat3_card_detect) 1056 host->default_irq_mask = 1057 INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN; 1058 else 1059 host->default_irq_mask = 0; 1060 1061 host->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1062 if (IS_ERR(host->clk_ipg)) { 1063 ret = PTR_ERR(host->clk_ipg); 1064 goto out_free; 1065 } 1066 1067 host->clk_per = devm_clk_get(&pdev->dev, "per"); 1068 if (IS_ERR(host->clk_per)) { 1069 ret = PTR_ERR(host->clk_per); 1070 goto out_free; 1071 } 1072 1073 ret = clk_prepare_enable(host->clk_per); 1074 if (ret) 1075 goto out_free; 1076 1077 ret = clk_prepare_enable(host->clk_ipg); 1078 if (ret) 1079 goto out_clk_per_put; 1080 1081 mxcmci_softreset(host); 1082 1083 host->rev_no = mxcmci_readw(host, MMC_REG_REV_NO); 1084 if (host->rev_no != 0x400) { 1085 ret = -ENODEV; 1086 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n", 1087 host->rev_no); 1088 goto out_clk_put; 1089 } 1090 1091 mmc->f_min = clk_get_rate(host->clk_per) >> 16; 1092 mmc->f_max = clk_get_rate(host->clk_per) >> 1; 1093 1094 /* recommended in data sheet */ 1095 mxcmci_writew(host, 0x2db4, MMC_REG_READ_TO); 1096 1097 mxcmci_writel(host, host->default_irq_mask, MMC_REG_INT_CNTR); 1098 1099 if (!host->pdata) { 1100 host->dma = dma_request_chan(&pdev->dev, "rx-tx"); 1101 if (IS_ERR(host->dma)) { 1102 if (PTR_ERR(host->dma) == -EPROBE_DEFER) { 1103 ret = -EPROBE_DEFER; 1104 goto out_clk_put; 1105 } 1106 1107 /* Ignore errors to fall back to PIO mode */ 1108 host->dma = NULL; 1109 } 1110 } else { 1111 res = platform_get_resource(pdev, IORESOURCE_DMA, 0); 1112 if (res) { 1113 host->dmareq = res->start; 1114 host->dma_data.peripheral_type = IMX_DMATYPE_SDHC; 1115 host->dma_data.priority = DMA_PRIO_LOW; 1116 host->dma_data.dma_request = host->dmareq; 1117 dma_cap_zero(mask); 1118 dma_cap_set(DMA_SLAVE, mask); 1119 host->dma = dma_request_channel(mask, filter, host); 1120 } 1121 } 1122 if (host->dma) 1123 mmc->max_seg_size = dma_get_max_seg_size( 1124 host->dma->device->dev); 1125 else 1126 dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n"); 1127 1128 INIT_WORK(&host->datawork, mxcmci_datawork); 1129 1130 ret = devm_request_irq(&pdev->dev, irq, mxcmci_irq, 0, 1131 dev_name(&pdev->dev), host); 1132 if (ret) 1133 goto out_free_dma; 1134 1135 platform_set_drvdata(pdev, mmc); 1136 1137 if (host->pdata && host->pdata->init) { 1138 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq, 1139 host->mmc); 1140 if (ret) 1141 goto out_free_dma; 1142 } 1143 1144 timer_setup(&host->watchdog, mxcmci_watchdog, 0); 1145 1146 mmc_add_host(mmc); 1147 1148 return 0; 1149 1150 out_free_dma: 1151 if (host->dma) 1152 dma_release_channel(host->dma); 1153 1154 out_clk_put: 1155 clk_disable_unprepare(host->clk_ipg); 1156 out_clk_per_put: 1157 clk_disable_unprepare(host->clk_per); 1158 1159 out_free: 1160 mmc_free_host(mmc); 1161 1162 return ret; 1163 } 1164 1165 static int mxcmci_remove(struct platform_device *pdev) 1166 { 1167 struct mmc_host *mmc = platform_get_drvdata(pdev); 1168 struct mxcmci_host *host = mmc_priv(mmc); 1169 1170 mmc_remove_host(mmc); 1171 1172 if (host->pdata && host->pdata->exit) 1173 host->pdata->exit(&pdev->dev, mmc); 1174 1175 if (host->dma) 1176 dma_release_channel(host->dma); 1177 1178 clk_disable_unprepare(host->clk_per); 1179 clk_disable_unprepare(host->clk_ipg); 1180 1181 mmc_free_host(mmc); 1182 1183 return 0; 1184 } 1185 1186 static int mxcmci_suspend(struct device *dev) 1187 { 1188 struct mmc_host *mmc = dev_get_drvdata(dev); 1189 struct mxcmci_host *host = mmc_priv(mmc); 1190 1191 clk_disable_unprepare(host->clk_per); 1192 clk_disable_unprepare(host->clk_ipg); 1193 return 0; 1194 } 1195 1196 static int mxcmci_resume(struct device *dev) 1197 { 1198 struct mmc_host *mmc = dev_get_drvdata(dev); 1199 struct mxcmci_host *host = mmc_priv(mmc); 1200 int ret; 1201 1202 ret = clk_prepare_enable(host->clk_per); 1203 if (ret) 1204 return ret; 1205 1206 ret = clk_prepare_enable(host->clk_ipg); 1207 if (ret) 1208 clk_disable_unprepare(host->clk_per); 1209 1210 return ret; 1211 } 1212 1213 static DEFINE_SIMPLE_DEV_PM_OPS(mxcmci_pm_ops, mxcmci_suspend, mxcmci_resume); 1214 1215 static struct platform_driver mxcmci_driver = { 1216 .probe = mxcmci_probe, 1217 .remove = mxcmci_remove, 1218 .driver = { 1219 .name = DRIVER_NAME, 1220 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1221 .pm = pm_sleep_ptr(&mxcmci_pm_ops), 1222 .of_match_table = mxcmci_of_match, 1223 } 1224 }; 1225 1226 module_platform_driver(mxcmci_driver); 1227 1228 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver"); 1229 MODULE_AUTHOR("Sascha Hauer, Pengutronix"); 1230 MODULE_LICENSE("GPL"); 1231 MODULE_ALIAS("platform:mxc-mmc"); 1232