1 /* 2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver 3 * 4 * This is a driver for the SDHC controller found in Freescale MX2/MX3 5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c). 6 * Unlike the hardware found on MX1, this hardware just works and does 7 * not need all the quirks found in imxmmc.c, hence the separate driver. 8 * 9 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> 10 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com> 11 * 12 * derived from pxamci.c by Russell King 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 * 18 */ 19 20 #include <linux/module.h> 21 #include <linux/init.h> 22 #include <linux/ioport.h> 23 #include <linux/platform_device.h> 24 #include <linux/interrupt.h> 25 #include <linux/irq.h> 26 #include <linux/blkdev.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/mmc/host.h> 29 #include <linux/mmc/card.h> 30 #include <linux/delay.h> 31 #include <linux/clk.h> 32 #include <linux/io.h> 33 #include <linux/gpio.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/dmaengine.h> 36 #include <linux/types.h> 37 38 #include <asm/dma.h> 39 #include <asm/irq.h> 40 #include <asm/sizes.h> 41 #include <mach/mmc.h> 42 43 #include <mach/dma.h> 44 #include <mach/hardware.h> 45 46 #define DRIVER_NAME "mxc-mmc" 47 48 #define MMC_REG_STR_STP_CLK 0x00 49 #define MMC_REG_STATUS 0x04 50 #define MMC_REG_CLK_RATE 0x08 51 #define MMC_REG_CMD_DAT_CONT 0x0C 52 #define MMC_REG_RES_TO 0x10 53 #define MMC_REG_READ_TO 0x14 54 #define MMC_REG_BLK_LEN 0x18 55 #define MMC_REG_NOB 0x1C 56 #define MMC_REG_REV_NO 0x20 57 #define MMC_REG_INT_CNTR 0x24 58 #define MMC_REG_CMD 0x28 59 #define MMC_REG_ARG 0x2C 60 #define MMC_REG_RES_FIFO 0x34 61 #define MMC_REG_BUFFER_ACCESS 0x38 62 63 #define STR_STP_CLK_RESET (1 << 3) 64 #define STR_STP_CLK_START_CLK (1 << 1) 65 #define STR_STP_CLK_STOP_CLK (1 << 0) 66 67 #define STATUS_CARD_INSERTION (1 << 31) 68 #define STATUS_CARD_REMOVAL (1 << 30) 69 #define STATUS_YBUF_EMPTY (1 << 29) 70 #define STATUS_XBUF_EMPTY (1 << 28) 71 #define STATUS_YBUF_FULL (1 << 27) 72 #define STATUS_XBUF_FULL (1 << 26) 73 #define STATUS_BUF_UND_RUN (1 << 25) 74 #define STATUS_BUF_OVFL (1 << 24) 75 #define STATUS_SDIO_INT_ACTIVE (1 << 14) 76 #define STATUS_END_CMD_RESP (1 << 13) 77 #define STATUS_WRITE_OP_DONE (1 << 12) 78 #define STATUS_DATA_TRANS_DONE (1 << 11) 79 #define STATUS_READ_OP_DONE (1 << 11) 80 #define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10) 81 #define STATUS_CARD_BUS_CLK_RUN (1 << 8) 82 #define STATUS_BUF_READ_RDY (1 << 7) 83 #define STATUS_BUF_WRITE_RDY (1 << 6) 84 #define STATUS_RESP_CRC_ERR (1 << 5) 85 #define STATUS_CRC_READ_ERR (1 << 3) 86 #define STATUS_CRC_WRITE_ERR (1 << 2) 87 #define STATUS_TIME_OUT_RESP (1 << 1) 88 #define STATUS_TIME_OUT_READ (1 << 0) 89 #define STATUS_ERR_MASK 0x2f 90 91 #define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12) 92 #define CMD_DAT_CONT_STOP_READWAIT (1 << 11) 93 #define CMD_DAT_CONT_START_READWAIT (1 << 10) 94 #define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8) 95 #define CMD_DAT_CONT_INIT (1 << 7) 96 #define CMD_DAT_CONT_WRITE (1 << 4) 97 #define CMD_DAT_CONT_DATA_ENABLE (1 << 3) 98 #define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0) 99 #define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0) 100 #define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0) 101 102 #define INT_SDIO_INT_WKP_EN (1 << 18) 103 #define INT_CARD_INSERTION_WKP_EN (1 << 17) 104 #define INT_CARD_REMOVAL_WKP_EN (1 << 16) 105 #define INT_CARD_INSERTION_EN (1 << 15) 106 #define INT_CARD_REMOVAL_EN (1 << 14) 107 #define INT_SDIO_IRQ_EN (1 << 13) 108 #define INT_DAT0_EN (1 << 12) 109 #define INT_BUF_READ_EN (1 << 4) 110 #define INT_BUF_WRITE_EN (1 << 3) 111 #define INT_END_CMD_RES_EN (1 << 2) 112 #define INT_WRITE_OP_DONE_EN (1 << 1) 113 #define INT_READ_OP_EN (1 << 0) 114 115 struct mxcmci_host { 116 struct mmc_host *mmc; 117 struct resource *res; 118 void __iomem *base; 119 int irq; 120 int detect_irq; 121 struct dma_chan *dma; 122 struct dma_async_tx_descriptor *desc; 123 int do_dma; 124 int default_irq_mask; 125 int use_sdio; 126 unsigned int power_mode; 127 struct imxmmc_platform_data *pdata; 128 129 struct mmc_request *req; 130 struct mmc_command *cmd; 131 struct mmc_data *data; 132 133 unsigned int datasize; 134 unsigned int dma_dir; 135 136 u16 rev_no; 137 unsigned int cmdat; 138 139 struct clk *clk; 140 141 int clock; 142 143 struct work_struct datawork; 144 spinlock_t lock; 145 146 struct regulator *vcc; 147 148 int burstlen; 149 int dmareq; 150 struct dma_slave_config dma_slave_config; 151 struct imx_dma_data dma_data; 152 }; 153 154 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios); 155 156 static inline void mxcmci_init_ocr(struct mxcmci_host *host) 157 { 158 host->vcc = regulator_get(mmc_dev(host->mmc), "vmmc"); 159 160 if (IS_ERR(host->vcc)) { 161 host->vcc = NULL; 162 } else { 163 host->mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vcc); 164 if (host->pdata && host->pdata->ocr_avail) 165 dev_warn(mmc_dev(host->mmc), 166 "pdata->ocr_avail will not be used\n"); 167 } 168 169 if (host->vcc == NULL) { 170 /* fall-back to platform data */ 171 if (host->pdata && host->pdata->ocr_avail) 172 host->mmc->ocr_avail = host->pdata->ocr_avail; 173 else 174 host->mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 175 } 176 } 177 178 static inline void mxcmci_set_power(struct mxcmci_host *host, 179 unsigned char power_mode, 180 unsigned int vdd) 181 { 182 if (host->vcc) { 183 if (power_mode == MMC_POWER_UP) 184 mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 185 else if (power_mode == MMC_POWER_OFF) 186 mmc_regulator_set_ocr(host->mmc, host->vcc, 0); 187 } 188 189 if (host->pdata && host->pdata->setpower) 190 host->pdata->setpower(mmc_dev(host->mmc), vdd); 191 } 192 193 static inline int mxcmci_use_dma(struct mxcmci_host *host) 194 { 195 return host->do_dma; 196 } 197 198 static void mxcmci_softreset(struct mxcmci_host *host) 199 { 200 int i; 201 202 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n"); 203 204 /* reset sequence */ 205 writew(STR_STP_CLK_RESET, host->base + MMC_REG_STR_STP_CLK); 206 writew(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK, 207 host->base + MMC_REG_STR_STP_CLK); 208 209 for (i = 0; i < 8; i++) 210 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK); 211 212 writew(0xff, host->base + MMC_REG_RES_TO); 213 } 214 static int mxcmci_setup_dma(struct mmc_host *mmc); 215 216 static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data) 217 { 218 unsigned int nob = data->blocks; 219 unsigned int blksz = data->blksz; 220 unsigned int datasize = nob * blksz; 221 struct scatterlist *sg; 222 enum dma_transfer_direction slave_dirn; 223 int i, nents; 224 225 if (data->flags & MMC_DATA_STREAM) 226 nob = 0xffff; 227 228 host->data = data; 229 data->bytes_xfered = 0; 230 231 writew(nob, host->base + MMC_REG_NOB); 232 writew(blksz, host->base + MMC_REG_BLK_LEN); 233 host->datasize = datasize; 234 235 if (!mxcmci_use_dma(host)) 236 return 0; 237 238 for_each_sg(data->sg, sg, data->sg_len, i) { 239 if (sg->offset & 3 || sg->length & 3) { 240 host->do_dma = 0; 241 return 0; 242 } 243 } 244 245 if (data->flags & MMC_DATA_READ) { 246 host->dma_dir = DMA_FROM_DEVICE; 247 slave_dirn = DMA_DEV_TO_MEM; 248 } else { 249 host->dma_dir = DMA_TO_DEVICE; 250 slave_dirn = DMA_MEM_TO_DEV; 251 } 252 253 nents = dma_map_sg(host->dma->device->dev, data->sg, 254 data->sg_len, host->dma_dir); 255 if (nents != data->sg_len) 256 return -EINVAL; 257 258 host->desc = dmaengine_prep_slave_sg(host->dma, 259 data->sg, data->sg_len, slave_dirn, 260 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 261 262 if (!host->desc) { 263 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len, 264 host->dma_dir); 265 host->do_dma = 0; 266 return 0; /* Fall back to PIO */ 267 } 268 wmb(); 269 270 dmaengine_submit(host->desc); 271 dma_async_issue_pending(host->dma); 272 273 return 0; 274 } 275 276 static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd, 277 unsigned int cmdat) 278 { 279 u32 int_cntr = host->default_irq_mask; 280 unsigned long flags; 281 282 WARN_ON(host->cmd != NULL); 283 host->cmd = cmd; 284 285 switch (mmc_resp_type(cmd)) { 286 case MMC_RSP_R1: /* short CRC, OPCODE */ 287 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */ 288 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC; 289 break; 290 case MMC_RSP_R2: /* long 136 bit + CRC */ 291 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT; 292 break; 293 case MMC_RSP_R3: /* short */ 294 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT; 295 break; 296 case MMC_RSP_NONE: 297 break; 298 default: 299 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n", 300 mmc_resp_type(cmd)); 301 cmd->error = -EINVAL; 302 return -EINVAL; 303 } 304 305 int_cntr = INT_END_CMD_RES_EN; 306 307 if (mxcmci_use_dma(host)) 308 int_cntr |= INT_READ_OP_EN | INT_WRITE_OP_DONE_EN; 309 310 spin_lock_irqsave(&host->lock, flags); 311 if (host->use_sdio) 312 int_cntr |= INT_SDIO_IRQ_EN; 313 writel(int_cntr, host->base + MMC_REG_INT_CNTR); 314 spin_unlock_irqrestore(&host->lock, flags); 315 316 writew(cmd->opcode, host->base + MMC_REG_CMD); 317 writel(cmd->arg, host->base + MMC_REG_ARG); 318 writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT); 319 320 return 0; 321 } 322 323 static void mxcmci_finish_request(struct mxcmci_host *host, 324 struct mmc_request *req) 325 { 326 u32 int_cntr = host->default_irq_mask; 327 unsigned long flags; 328 329 spin_lock_irqsave(&host->lock, flags); 330 if (host->use_sdio) 331 int_cntr |= INT_SDIO_IRQ_EN; 332 writel(int_cntr, host->base + MMC_REG_INT_CNTR); 333 spin_unlock_irqrestore(&host->lock, flags); 334 335 host->req = NULL; 336 host->cmd = NULL; 337 host->data = NULL; 338 339 mmc_request_done(host->mmc, req); 340 } 341 342 static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat) 343 { 344 struct mmc_data *data = host->data; 345 int data_error; 346 347 if (mxcmci_use_dma(host)) { 348 dmaengine_terminate_all(host->dma); 349 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len, 350 host->dma_dir); 351 } 352 353 if (stat & STATUS_ERR_MASK) { 354 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n", 355 stat); 356 if (stat & STATUS_CRC_READ_ERR) { 357 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__); 358 data->error = -EILSEQ; 359 } else if (stat & STATUS_CRC_WRITE_ERR) { 360 u32 err_code = (stat >> 9) & 0x3; 361 if (err_code == 2) { /* No CRC response */ 362 dev_err(mmc_dev(host->mmc), 363 "%s: No CRC -ETIMEDOUT\n", __func__); 364 data->error = -ETIMEDOUT; 365 } else { 366 dev_err(mmc_dev(host->mmc), 367 "%s: -EILSEQ\n", __func__); 368 data->error = -EILSEQ; 369 } 370 } else if (stat & STATUS_TIME_OUT_READ) { 371 dev_err(mmc_dev(host->mmc), 372 "%s: read -ETIMEDOUT\n", __func__); 373 data->error = -ETIMEDOUT; 374 } else { 375 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__); 376 data->error = -EIO; 377 } 378 } else { 379 data->bytes_xfered = host->datasize; 380 } 381 382 data_error = data->error; 383 384 host->data = NULL; 385 386 return data_error; 387 } 388 389 static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat) 390 { 391 struct mmc_command *cmd = host->cmd; 392 int i; 393 u32 a, b, c; 394 395 if (!cmd) 396 return; 397 398 if (stat & STATUS_TIME_OUT_RESP) { 399 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n"); 400 cmd->error = -ETIMEDOUT; 401 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) { 402 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n"); 403 cmd->error = -EILSEQ; 404 } 405 406 if (cmd->flags & MMC_RSP_PRESENT) { 407 if (cmd->flags & MMC_RSP_136) { 408 for (i = 0; i < 4; i++) { 409 a = readw(host->base + MMC_REG_RES_FIFO); 410 b = readw(host->base + MMC_REG_RES_FIFO); 411 cmd->resp[i] = a << 16 | b; 412 } 413 } else { 414 a = readw(host->base + MMC_REG_RES_FIFO); 415 b = readw(host->base + MMC_REG_RES_FIFO); 416 c = readw(host->base + MMC_REG_RES_FIFO); 417 cmd->resp[0] = a << 24 | b << 8 | c >> 8; 418 } 419 } 420 } 421 422 static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask) 423 { 424 u32 stat; 425 unsigned long timeout = jiffies + HZ; 426 427 do { 428 stat = readl(host->base + MMC_REG_STATUS); 429 if (stat & STATUS_ERR_MASK) 430 return stat; 431 if (time_after(jiffies, timeout)) { 432 mxcmci_softreset(host); 433 mxcmci_set_clk_rate(host, host->clock); 434 return STATUS_TIME_OUT_READ; 435 } 436 if (stat & mask) 437 return 0; 438 cpu_relax(); 439 } while (1); 440 } 441 442 static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes) 443 { 444 unsigned int stat; 445 u32 *buf = _buf; 446 447 while (bytes > 3) { 448 stat = mxcmci_poll_status(host, 449 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE); 450 if (stat) 451 return stat; 452 *buf++ = readl(host->base + MMC_REG_BUFFER_ACCESS); 453 bytes -= 4; 454 } 455 456 if (bytes) { 457 u8 *b = (u8 *)buf; 458 u32 tmp; 459 460 stat = mxcmci_poll_status(host, 461 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE); 462 if (stat) 463 return stat; 464 tmp = readl(host->base + MMC_REG_BUFFER_ACCESS); 465 memcpy(b, &tmp, bytes); 466 } 467 468 return 0; 469 } 470 471 static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes) 472 { 473 unsigned int stat; 474 u32 *buf = _buf; 475 476 while (bytes > 3) { 477 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 478 if (stat) 479 return stat; 480 writel(*buf++, host->base + MMC_REG_BUFFER_ACCESS); 481 bytes -= 4; 482 } 483 484 if (bytes) { 485 u8 *b = (u8 *)buf; 486 u32 tmp; 487 488 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 489 if (stat) 490 return stat; 491 492 memcpy(&tmp, b, bytes); 493 writel(tmp, host->base + MMC_REG_BUFFER_ACCESS); 494 } 495 496 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 497 if (stat) 498 return stat; 499 500 return 0; 501 } 502 503 static int mxcmci_transfer_data(struct mxcmci_host *host) 504 { 505 struct mmc_data *data = host->req->data; 506 struct scatterlist *sg; 507 int stat, i; 508 509 host->data = data; 510 host->datasize = 0; 511 512 if (data->flags & MMC_DATA_READ) { 513 for_each_sg(data->sg, sg, data->sg_len, i) { 514 stat = mxcmci_pull(host, sg_virt(sg), sg->length); 515 if (stat) 516 return stat; 517 host->datasize += sg->length; 518 } 519 } else { 520 for_each_sg(data->sg, sg, data->sg_len, i) { 521 stat = mxcmci_push(host, sg_virt(sg), sg->length); 522 if (stat) 523 return stat; 524 host->datasize += sg->length; 525 } 526 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE); 527 if (stat) 528 return stat; 529 } 530 return 0; 531 } 532 533 static void mxcmci_datawork(struct work_struct *work) 534 { 535 struct mxcmci_host *host = container_of(work, struct mxcmci_host, 536 datawork); 537 int datastat = mxcmci_transfer_data(host); 538 539 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE, 540 host->base + MMC_REG_STATUS); 541 mxcmci_finish_data(host, datastat); 542 543 if (host->req->stop) { 544 if (mxcmci_start_cmd(host, host->req->stop, 0)) { 545 mxcmci_finish_request(host, host->req); 546 return; 547 } 548 } else { 549 mxcmci_finish_request(host, host->req); 550 } 551 } 552 553 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat) 554 { 555 struct mmc_data *data = host->data; 556 int data_error; 557 558 if (!data) 559 return; 560 561 data_error = mxcmci_finish_data(host, stat); 562 563 mxcmci_read_response(host, stat); 564 host->cmd = NULL; 565 566 if (host->req->stop) { 567 if (mxcmci_start_cmd(host, host->req->stop, 0)) { 568 mxcmci_finish_request(host, host->req); 569 return; 570 } 571 } else { 572 mxcmci_finish_request(host, host->req); 573 } 574 } 575 576 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat) 577 { 578 mxcmci_read_response(host, stat); 579 host->cmd = NULL; 580 581 if (!host->data && host->req) { 582 mxcmci_finish_request(host, host->req); 583 return; 584 } 585 586 /* For the DMA case the DMA engine handles the data transfer 587 * automatically. For non DMA we have to do it ourselves. 588 * Don't do it in interrupt context though. 589 */ 590 if (!mxcmci_use_dma(host) && host->data) 591 schedule_work(&host->datawork); 592 593 } 594 595 static irqreturn_t mxcmci_irq(int irq, void *devid) 596 { 597 struct mxcmci_host *host = devid; 598 unsigned long flags; 599 bool sdio_irq; 600 u32 stat; 601 602 stat = readl(host->base + MMC_REG_STATUS); 603 writel(stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE | 604 STATUS_WRITE_OP_DONE), host->base + MMC_REG_STATUS); 605 606 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat); 607 608 spin_lock_irqsave(&host->lock, flags); 609 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio; 610 spin_unlock_irqrestore(&host->lock, flags); 611 612 if (mxcmci_use_dma(host) && 613 (stat & (STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE))) 614 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE, 615 host->base + MMC_REG_STATUS); 616 617 if (sdio_irq) { 618 writel(STATUS_SDIO_INT_ACTIVE, host->base + MMC_REG_STATUS); 619 mmc_signal_sdio_irq(host->mmc); 620 } 621 622 if (stat & STATUS_END_CMD_RESP) 623 mxcmci_cmd_done(host, stat); 624 625 if (mxcmci_use_dma(host) && 626 (stat & (STATUS_DATA_TRANS_DONE | STATUS_WRITE_OP_DONE))) 627 mxcmci_data_done(host, stat); 628 629 if (host->default_irq_mask && 630 (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL))) 631 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 632 633 return IRQ_HANDLED; 634 } 635 636 static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req) 637 { 638 struct mxcmci_host *host = mmc_priv(mmc); 639 unsigned int cmdat = host->cmdat; 640 int error; 641 642 WARN_ON(host->req != NULL); 643 644 host->req = req; 645 host->cmdat &= ~CMD_DAT_CONT_INIT; 646 647 if (host->dma) 648 host->do_dma = 1; 649 650 if (req->data) { 651 error = mxcmci_setup_data(host, req->data); 652 if (error) { 653 req->cmd->error = error; 654 goto out; 655 } 656 657 658 cmdat |= CMD_DAT_CONT_DATA_ENABLE; 659 660 if (req->data->flags & MMC_DATA_WRITE) 661 cmdat |= CMD_DAT_CONT_WRITE; 662 } 663 664 error = mxcmci_start_cmd(host, req->cmd, cmdat); 665 666 out: 667 if (error) 668 mxcmci_finish_request(host, req); 669 } 670 671 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios) 672 { 673 unsigned int divider; 674 int prescaler = 0; 675 unsigned int clk_in = clk_get_rate(host->clk); 676 677 while (prescaler <= 0x800) { 678 for (divider = 1; divider <= 0xF; divider++) { 679 int x; 680 681 x = (clk_in / (divider + 1)); 682 683 if (prescaler) 684 x /= (prescaler * 2); 685 686 if (x <= clk_ios) 687 break; 688 } 689 if (divider < 0x10) 690 break; 691 692 if (prescaler == 0) 693 prescaler = 1; 694 else 695 prescaler <<= 1; 696 } 697 698 writew((prescaler << 4) | divider, host->base + MMC_REG_CLK_RATE); 699 700 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n", 701 prescaler, divider, clk_in, clk_ios); 702 } 703 704 static int mxcmci_setup_dma(struct mmc_host *mmc) 705 { 706 struct mxcmci_host *host = mmc_priv(mmc); 707 struct dma_slave_config *config = &host->dma_slave_config; 708 709 config->dst_addr = host->res->start + MMC_REG_BUFFER_ACCESS; 710 config->src_addr = host->res->start + MMC_REG_BUFFER_ACCESS; 711 config->dst_addr_width = 4; 712 config->src_addr_width = 4; 713 config->dst_maxburst = host->burstlen; 714 config->src_maxburst = host->burstlen; 715 config->device_fc = false; 716 717 return dmaengine_slave_config(host->dma, config); 718 } 719 720 static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 721 { 722 struct mxcmci_host *host = mmc_priv(mmc); 723 int burstlen, ret; 724 725 /* 726 * use burstlen of 64 (16 words) in 4 bit mode (--> reg value 0) 727 * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16) 728 */ 729 if (ios->bus_width == MMC_BUS_WIDTH_4) 730 burstlen = 16; 731 else 732 burstlen = 4; 733 734 if (mxcmci_use_dma(host) && burstlen != host->burstlen) { 735 host->burstlen = burstlen; 736 ret = mxcmci_setup_dma(mmc); 737 if (ret) { 738 dev_err(mmc_dev(host->mmc), 739 "failed to config DMA channel. Falling back to PIO\n"); 740 dma_release_channel(host->dma); 741 host->do_dma = 0; 742 host->dma = NULL; 743 } 744 } 745 746 if (ios->bus_width == MMC_BUS_WIDTH_4) 747 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4; 748 else 749 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4; 750 751 if (host->power_mode != ios->power_mode) { 752 mxcmci_set_power(host, ios->power_mode, ios->vdd); 753 host->power_mode = ios->power_mode; 754 755 if (ios->power_mode == MMC_POWER_ON) 756 host->cmdat |= CMD_DAT_CONT_INIT; 757 } 758 759 if (ios->clock) { 760 mxcmci_set_clk_rate(host, ios->clock); 761 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK); 762 } else { 763 writew(STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK); 764 } 765 766 host->clock = ios->clock; 767 } 768 769 static irqreturn_t mxcmci_detect_irq(int irq, void *data) 770 { 771 struct mmc_host *mmc = data; 772 773 dev_dbg(mmc_dev(mmc), "%s\n", __func__); 774 775 mmc_detect_change(mmc, msecs_to_jiffies(250)); 776 return IRQ_HANDLED; 777 } 778 779 static int mxcmci_get_ro(struct mmc_host *mmc) 780 { 781 struct mxcmci_host *host = mmc_priv(mmc); 782 783 if (host->pdata && host->pdata->get_ro) 784 return !!host->pdata->get_ro(mmc_dev(mmc)); 785 /* 786 * Board doesn't support read only detection; let the mmc core 787 * decide what to do. 788 */ 789 return -ENOSYS; 790 } 791 792 static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable) 793 { 794 struct mxcmci_host *host = mmc_priv(mmc); 795 unsigned long flags; 796 u32 int_cntr; 797 798 spin_lock_irqsave(&host->lock, flags); 799 host->use_sdio = enable; 800 int_cntr = readl(host->base + MMC_REG_INT_CNTR); 801 802 if (enable) 803 int_cntr |= INT_SDIO_IRQ_EN; 804 else 805 int_cntr &= ~INT_SDIO_IRQ_EN; 806 807 writel(int_cntr, host->base + MMC_REG_INT_CNTR); 808 spin_unlock_irqrestore(&host->lock, flags); 809 } 810 811 static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card) 812 { 813 /* 814 * MX3 SoCs have a silicon bug which corrupts CRC calculation of 815 * multi-block transfers when connected SDIO peripheral doesn't 816 * drive the BUSY line as required by the specs. 817 * One way to prevent this is to only allow 1-bit transfers. 818 */ 819 820 if (cpu_is_mx3() && card->type == MMC_TYPE_SDIO) 821 host->caps &= ~MMC_CAP_4_BIT_DATA; 822 else 823 host->caps |= MMC_CAP_4_BIT_DATA; 824 } 825 826 static bool filter(struct dma_chan *chan, void *param) 827 { 828 struct mxcmci_host *host = param; 829 830 if (!imx_dma_is_general_purpose(chan)) 831 return false; 832 833 chan->private = &host->dma_data; 834 835 return true; 836 } 837 838 static const struct mmc_host_ops mxcmci_ops = { 839 .request = mxcmci_request, 840 .set_ios = mxcmci_set_ios, 841 .get_ro = mxcmci_get_ro, 842 .enable_sdio_irq = mxcmci_enable_sdio_irq, 843 .init_card = mxcmci_init_card, 844 }; 845 846 static int mxcmci_probe(struct platform_device *pdev) 847 { 848 struct mmc_host *mmc; 849 struct mxcmci_host *host = NULL; 850 struct resource *iores, *r; 851 int ret = 0, irq; 852 dma_cap_mask_t mask; 853 854 pr_info("i.MX SDHC driver\n"); 855 856 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 857 irq = platform_get_irq(pdev, 0); 858 if (!iores || irq < 0) 859 return -EINVAL; 860 861 r = request_mem_region(iores->start, resource_size(iores), pdev->name); 862 if (!r) 863 return -EBUSY; 864 865 mmc = mmc_alloc_host(sizeof(struct mxcmci_host), &pdev->dev); 866 if (!mmc) { 867 ret = -ENOMEM; 868 goto out_release_mem; 869 } 870 871 mmc->ops = &mxcmci_ops; 872 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; 873 874 /* MMC core transfer sizes tunable parameters */ 875 mmc->max_segs = 64; 876 mmc->max_blk_size = 2048; 877 mmc->max_blk_count = 65535; 878 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 879 mmc->max_seg_size = mmc->max_req_size; 880 881 host = mmc_priv(mmc); 882 host->base = ioremap(r->start, resource_size(r)); 883 if (!host->base) { 884 ret = -ENOMEM; 885 goto out_free; 886 } 887 888 host->mmc = mmc; 889 host->pdata = pdev->dev.platform_data; 890 spin_lock_init(&host->lock); 891 892 mxcmci_init_ocr(host); 893 894 if (host->pdata && host->pdata->dat3_card_detect) 895 host->default_irq_mask = 896 INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN; 897 else 898 host->default_irq_mask = 0; 899 900 host->res = r; 901 host->irq = irq; 902 903 host->clk = clk_get(&pdev->dev, NULL); 904 if (IS_ERR(host->clk)) { 905 ret = PTR_ERR(host->clk); 906 goto out_iounmap; 907 } 908 clk_enable(host->clk); 909 910 mxcmci_softreset(host); 911 912 host->rev_no = readw(host->base + MMC_REG_REV_NO); 913 if (host->rev_no != 0x400) { 914 ret = -ENODEV; 915 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n", 916 host->rev_no); 917 goto out_clk_put; 918 } 919 920 mmc->f_min = clk_get_rate(host->clk) >> 16; 921 mmc->f_max = clk_get_rate(host->clk) >> 1; 922 923 /* recommended in data sheet */ 924 writew(0x2db4, host->base + MMC_REG_READ_TO); 925 926 writel(host->default_irq_mask, host->base + MMC_REG_INT_CNTR); 927 928 r = platform_get_resource(pdev, IORESOURCE_DMA, 0); 929 if (r) { 930 host->dmareq = r->start; 931 host->dma_data.peripheral_type = IMX_DMATYPE_SDHC; 932 host->dma_data.priority = DMA_PRIO_LOW; 933 host->dma_data.dma_request = host->dmareq; 934 dma_cap_zero(mask); 935 dma_cap_set(DMA_SLAVE, mask); 936 host->dma = dma_request_channel(mask, filter, host); 937 if (host->dma) 938 mmc->max_seg_size = dma_get_max_seg_size( 939 host->dma->device->dev); 940 } 941 942 if (!host->dma) 943 dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n"); 944 945 INIT_WORK(&host->datawork, mxcmci_datawork); 946 947 ret = request_irq(host->irq, mxcmci_irq, 0, DRIVER_NAME, host); 948 if (ret) 949 goto out_free_dma; 950 951 platform_set_drvdata(pdev, mmc); 952 953 if (host->pdata && host->pdata->init) { 954 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq, 955 host->mmc); 956 if (ret) 957 goto out_free_irq; 958 } 959 960 mmc_add_host(mmc); 961 962 return 0; 963 964 out_free_irq: 965 free_irq(host->irq, host); 966 out_free_dma: 967 if (host->dma) 968 dma_release_channel(host->dma); 969 out_clk_put: 970 clk_disable(host->clk); 971 clk_put(host->clk); 972 out_iounmap: 973 iounmap(host->base); 974 out_free: 975 mmc_free_host(mmc); 976 out_release_mem: 977 release_mem_region(iores->start, resource_size(iores)); 978 return ret; 979 } 980 981 static int mxcmci_remove(struct platform_device *pdev) 982 { 983 struct mmc_host *mmc = platform_get_drvdata(pdev); 984 struct mxcmci_host *host = mmc_priv(mmc); 985 986 platform_set_drvdata(pdev, NULL); 987 988 mmc_remove_host(mmc); 989 990 if (host->vcc) 991 regulator_put(host->vcc); 992 993 if (host->pdata && host->pdata->exit) 994 host->pdata->exit(&pdev->dev, mmc); 995 996 free_irq(host->irq, host); 997 iounmap(host->base); 998 999 if (host->dma) 1000 dma_release_channel(host->dma); 1001 1002 clk_disable(host->clk); 1003 clk_put(host->clk); 1004 1005 release_mem_region(host->res->start, resource_size(host->res)); 1006 1007 mmc_free_host(mmc); 1008 1009 return 0; 1010 } 1011 1012 #ifdef CONFIG_PM 1013 static int mxcmci_suspend(struct device *dev) 1014 { 1015 struct mmc_host *mmc = dev_get_drvdata(dev); 1016 struct mxcmci_host *host = mmc_priv(mmc); 1017 int ret = 0; 1018 1019 if (mmc) 1020 ret = mmc_suspend_host(mmc); 1021 clk_disable(host->clk); 1022 1023 return ret; 1024 } 1025 1026 static int mxcmci_resume(struct device *dev) 1027 { 1028 struct mmc_host *mmc = dev_get_drvdata(dev); 1029 struct mxcmci_host *host = mmc_priv(mmc); 1030 int ret = 0; 1031 1032 clk_enable(host->clk); 1033 if (mmc) 1034 ret = mmc_resume_host(mmc); 1035 1036 return ret; 1037 } 1038 1039 static const struct dev_pm_ops mxcmci_pm_ops = { 1040 .suspend = mxcmci_suspend, 1041 .resume = mxcmci_resume, 1042 }; 1043 #endif 1044 1045 static struct platform_driver mxcmci_driver = { 1046 .probe = mxcmci_probe, 1047 .remove = mxcmci_remove, 1048 .driver = { 1049 .name = DRIVER_NAME, 1050 .owner = THIS_MODULE, 1051 #ifdef CONFIG_PM 1052 .pm = &mxcmci_pm_ops, 1053 #endif 1054 } 1055 }; 1056 1057 module_platform_driver(mxcmci_driver); 1058 1059 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver"); 1060 MODULE_AUTHOR("Sascha Hauer, Pengutronix"); 1061 MODULE_LICENSE("GPL"); 1062 MODULE_ALIAS("platform:imx-mmc"); 1063