1 /* 2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver 3 * 4 * This is a driver for the SDHC controller found in Freescale MX2/MX3 5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c). 6 * Unlike the hardware found on MX1, this hardware just works and does 7 * not need all the quirks found in imxmmc.c, hence the separate driver. 8 * 9 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> 10 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com> 11 * 12 * derived from pxamci.c by Russell King 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 * 18 */ 19 20 #include <linux/module.h> 21 #include <linux/init.h> 22 #include <linux/ioport.h> 23 #include <linux/platform_device.h> 24 #include <linux/interrupt.h> 25 #include <linux/irq.h> 26 #include <linux/blkdev.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/mmc/host.h> 29 #include <linux/mmc/card.h> 30 #include <linux/delay.h> 31 #include <linux/clk.h> 32 #include <linux/io.h> 33 #include <linux/gpio.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/dmaengine.h> 36 #include <linux/types.h> 37 38 #include <asm/dma.h> 39 #include <asm/irq.h> 40 #include <asm/sizes.h> 41 #include <linux/platform_data/mmc-mxcmmc.h> 42 43 #include <linux/platform_data/dma-imx.h> 44 #include <mach/hardware.h> 45 46 #define DRIVER_NAME "mxc-mmc" 47 #define MXCMCI_TIMEOUT_MS 10000 48 49 #define MMC_REG_STR_STP_CLK 0x00 50 #define MMC_REG_STATUS 0x04 51 #define MMC_REG_CLK_RATE 0x08 52 #define MMC_REG_CMD_DAT_CONT 0x0C 53 #define MMC_REG_RES_TO 0x10 54 #define MMC_REG_READ_TO 0x14 55 #define MMC_REG_BLK_LEN 0x18 56 #define MMC_REG_NOB 0x1C 57 #define MMC_REG_REV_NO 0x20 58 #define MMC_REG_INT_CNTR 0x24 59 #define MMC_REG_CMD 0x28 60 #define MMC_REG_ARG 0x2C 61 #define MMC_REG_RES_FIFO 0x34 62 #define MMC_REG_BUFFER_ACCESS 0x38 63 64 #define STR_STP_CLK_RESET (1 << 3) 65 #define STR_STP_CLK_START_CLK (1 << 1) 66 #define STR_STP_CLK_STOP_CLK (1 << 0) 67 68 #define STATUS_CARD_INSERTION (1 << 31) 69 #define STATUS_CARD_REMOVAL (1 << 30) 70 #define STATUS_YBUF_EMPTY (1 << 29) 71 #define STATUS_XBUF_EMPTY (1 << 28) 72 #define STATUS_YBUF_FULL (1 << 27) 73 #define STATUS_XBUF_FULL (1 << 26) 74 #define STATUS_BUF_UND_RUN (1 << 25) 75 #define STATUS_BUF_OVFL (1 << 24) 76 #define STATUS_SDIO_INT_ACTIVE (1 << 14) 77 #define STATUS_END_CMD_RESP (1 << 13) 78 #define STATUS_WRITE_OP_DONE (1 << 12) 79 #define STATUS_DATA_TRANS_DONE (1 << 11) 80 #define STATUS_READ_OP_DONE (1 << 11) 81 #define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10) 82 #define STATUS_CARD_BUS_CLK_RUN (1 << 8) 83 #define STATUS_BUF_READ_RDY (1 << 7) 84 #define STATUS_BUF_WRITE_RDY (1 << 6) 85 #define STATUS_RESP_CRC_ERR (1 << 5) 86 #define STATUS_CRC_READ_ERR (1 << 3) 87 #define STATUS_CRC_WRITE_ERR (1 << 2) 88 #define STATUS_TIME_OUT_RESP (1 << 1) 89 #define STATUS_TIME_OUT_READ (1 << 0) 90 #define STATUS_ERR_MASK 0x2f 91 92 #define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12) 93 #define CMD_DAT_CONT_STOP_READWAIT (1 << 11) 94 #define CMD_DAT_CONT_START_READWAIT (1 << 10) 95 #define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8) 96 #define CMD_DAT_CONT_INIT (1 << 7) 97 #define CMD_DAT_CONT_WRITE (1 << 4) 98 #define CMD_DAT_CONT_DATA_ENABLE (1 << 3) 99 #define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0) 100 #define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0) 101 #define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0) 102 103 #define INT_SDIO_INT_WKP_EN (1 << 18) 104 #define INT_CARD_INSERTION_WKP_EN (1 << 17) 105 #define INT_CARD_REMOVAL_WKP_EN (1 << 16) 106 #define INT_CARD_INSERTION_EN (1 << 15) 107 #define INT_CARD_REMOVAL_EN (1 << 14) 108 #define INT_SDIO_IRQ_EN (1 << 13) 109 #define INT_DAT0_EN (1 << 12) 110 #define INT_BUF_READ_EN (1 << 4) 111 #define INT_BUF_WRITE_EN (1 << 3) 112 #define INT_END_CMD_RES_EN (1 << 2) 113 #define INT_WRITE_OP_DONE_EN (1 << 1) 114 #define INT_READ_OP_EN (1 << 0) 115 116 struct mxcmci_host { 117 struct mmc_host *mmc; 118 struct resource *res; 119 void __iomem *base; 120 int irq; 121 int detect_irq; 122 struct dma_chan *dma; 123 struct dma_async_tx_descriptor *desc; 124 int do_dma; 125 int default_irq_mask; 126 int use_sdio; 127 unsigned int power_mode; 128 struct imxmmc_platform_data *pdata; 129 130 struct mmc_request *req; 131 struct mmc_command *cmd; 132 struct mmc_data *data; 133 134 unsigned int datasize; 135 unsigned int dma_dir; 136 137 u16 rev_no; 138 unsigned int cmdat; 139 140 struct clk *clk_ipg; 141 struct clk *clk_per; 142 143 int clock; 144 145 struct work_struct datawork; 146 spinlock_t lock; 147 148 struct regulator *vcc; 149 150 int burstlen; 151 int dmareq; 152 struct dma_slave_config dma_slave_config; 153 struct imx_dma_data dma_data; 154 155 struct timer_list watchdog; 156 }; 157 158 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios); 159 160 static inline void mxcmci_init_ocr(struct mxcmci_host *host) 161 { 162 host->vcc = regulator_get(mmc_dev(host->mmc), "vmmc"); 163 164 if (IS_ERR(host->vcc)) { 165 host->vcc = NULL; 166 } else { 167 host->mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vcc); 168 if (host->pdata && host->pdata->ocr_avail) 169 dev_warn(mmc_dev(host->mmc), 170 "pdata->ocr_avail will not be used\n"); 171 } 172 173 if (host->vcc == NULL) { 174 /* fall-back to platform data */ 175 if (host->pdata && host->pdata->ocr_avail) 176 host->mmc->ocr_avail = host->pdata->ocr_avail; 177 else 178 host->mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 179 } 180 } 181 182 static inline void mxcmci_set_power(struct mxcmci_host *host, 183 unsigned char power_mode, 184 unsigned int vdd) 185 { 186 if (host->vcc) { 187 if (power_mode == MMC_POWER_UP) 188 mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 189 else if (power_mode == MMC_POWER_OFF) 190 mmc_regulator_set_ocr(host->mmc, host->vcc, 0); 191 } 192 193 if (host->pdata && host->pdata->setpower) 194 host->pdata->setpower(mmc_dev(host->mmc), vdd); 195 } 196 197 static inline int mxcmci_use_dma(struct mxcmci_host *host) 198 { 199 return host->do_dma; 200 } 201 202 static void mxcmci_softreset(struct mxcmci_host *host) 203 { 204 int i; 205 206 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n"); 207 208 /* reset sequence */ 209 writew(STR_STP_CLK_RESET, host->base + MMC_REG_STR_STP_CLK); 210 writew(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK, 211 host->base + MMC_REG_STR_STP_CLK); 212 213 for (i = 0; i < 8; i++) 214 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK); 215 216 writew(0xff, host->base + MMC_REG_RES_TO); 217 } 218 static int mxcmci_setup_dma(struct mmc_host *mmc); 219 220 static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data) 221 { 222 unsigned int nob = data->blocks; 223 unsigned int blksz = data->blksz; 224 unsigned int datasize = nob * blksz; 225 struct scatterlist *sg; 226 enum dma_transfer_direction slave_dirn; 227 int i, nents; 228 229 if (data->flags & MMC_DATA_STREAM) 230 nob = 0xffff; 231 232 host->data = data; 233 data->bytes_xfered = 0; 234 235 writew(nob, host->base + MMC_REG_NOB); 236 writew(blksz, host->base + MMC_REG_BLK_LEN); 237 host->datasize = datasize; 238 239 if (!mxcmci_use_dma(host)) 240 return 0; 241 242 for_each_sg(data->sg, sg, data->sg_len, i) { 243 if (sg->offset & 3 || sg->length & 3) { 244 host->do_dma = 0; 245 return 0; 246 } 247 } 248 249 if (data->flags & MMC_DATA_READ) { 250 host->dma_dir = DMA_FROM_DEVICE; 251 slave_dirn = DMA_DEV_TO_MEM; 252 } else { 253 host->dma_dir = DMA_TO_DEVICE; 254 slave_dirn = DMA_MEM_TO_DEV; 255 } 256 257 nents = dma_map_sg(host->dma->device->dev, data->sg, 258 data->sg_len, host->dma_dir); 259 if (nents != data->sg_len) 260 return -EINVAL; 261 262 host->desc = dmaengine_prep_slave_sg(host->dma, 263 data->sg, data->sg_len, slave_dirn, 264 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 265 266 if (!host->desc) { 267 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len, 268 host->dma_dir); 269 host->do_dma = 0; 270 return 0; /* Fall back to PIO */ 271 } 272 wmb(); 273 274 dmaengine_submit(host->desc); 275 dma_async_issue_pending(host->dma); 276 277 mod_timer(&host->watchdog, jiffies + msecs_to_jiffies(MXCMCI_TIMEOUT_MS)); 278 279 return 0; 280 } 281 282 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat); 283 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat); 284 285 static void mxcmci_dma_callback(void *data) 286 { 287 struct mxcmci_host *host = data; 288 u32 stat; 289 290 del_timer(&host->watchdog); 291 292 stat = readl(host->base + MMC_REG_STATUS); 293 writel(stat & ~STATUS_DATA_TRANS_DONE, host->base + MMC_REG_STATUS); 294 295 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat); 296 297 if (stat & STATUS_READ_OP_DONE) 298 writel(STATUS_READ_OP_DONE, host->base + MMC_REG_STATUS); 299 300 mxcmci_data_done(host, stat); 301 } 302 303 static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd, 304 unsigned int cmdat) 305 { 306 u32 int_cntr = host->default_irq_mask; 307 unsigned long flags; 308 309 WARN_ON(host->cmd != NULL); 310 host->cmd = cmd; 311 312 switch (mmc_resp_type(cmd)) { 313 case MMC_RSP_R1: /* short CRC, OPCODE */ 314 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */ 315 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC; 316 break; 317 case MMC_RSP_R2: /* long 136 bit + CRC */ 318 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT; 319 break; 320 case MMC_RSP_R3: /* short */ 321 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT; 322 break; 323 case MMC_RSP_NONE: 324 break; 325 default: 326 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n", 327 mmc_resp_type(cmd)); 328 cmd->error = -EINVAL; 329 return -EINVAL; 330 } 331 332 int_cntr = INT_END_CMD_RES_EN; 333 334 if (mxcmci_use_dma(host)) { 335 if (host->dma_dir == DMA_FROM_DEVICE) { 336 host->desc->callback = mxcmci_dma_callback; 337 host->desc->callback_param = host; 338 } else { 339 int_cntr |= INT_WRITE_OP_DONE_EN; 340 } 341 } 342 343 spin_lock_irqsave(&host->lock, flags); 344 if (host->use_sdio) 345 int_cntr |= INT_SDIO_IRQ_EN; 346 writel(int_cntr, host->base + MMC_REG_INT_CNTR); 347 spin_unlock_irqrestore(&host->lock, flags); 348 349 writew(cmd->opcode, host->base + MMC_REG_CMD); 350 writel(cmd->arg, host->base + MMC_REG_ARG); 351 writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT); 352 353 return 0; 354 } 355 356 static void mxcmci_finish_request(struct mxcmci_host *host, 357 struct mmc_request *req) 358 { 359 u32 int_cntr = host->default_irq_mask; 360 unsigned long flags; 361 362 spin_lock_irqsave(&host->lock, flags); 363 if (host->use_sdio) 364 int_cntr |= INT_SDIO_IRQ_EN; 365 writel(int_cntr, host->base + MMC_REG_INT_CNTR); 366 spin_unlock_irqrestore(&host->lock, flags); 367 368 host->req = NULL; 369 host->cmd = NULL; 370 host->data = NULL; 371 372 mmc_request_done(host->mmc, req); 373 } 374 375 static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat) 376 { 377 struct mmc_data *data = host->data; 378 int data_error; 379 380 if (mxcmci_use_dma(host)) 381 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len, 382 host->dma_dir); 383 384 if (stat & STATUS_ERR_MASK) { 385 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n", 386 stat); 387 if (stat & STATUS_CRC_READ_ERR) { 388 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__); 389 data->error = -EILSEQ; 390 } else if (stat & STATUS_CRC_WRITE_ERR) { 391 u32 err_code = (stat >> 9) & 0x3; 392 if (err_code == 2) { /* No CRC response */ 393 dev_err(mmc_dev(host->mmc), 394 "%s: No CRC -ETIMEDOUT\n", __func__); 395 data->error = -ETIMEDOUT; 396 } else { 397 dev_err(mmc_dev(host->mmc), 398 "%s: -EILSEQ\n", __func__); 399 data->error = -EILSEQ; 400 } 401 } else if (stat & STATUS_TIME_OUT_READ) { 402 dev_err(mmc_dev(host->mmc), 403 "%s: read -ETIMEDOUT\n", __func__); 404 data->error = -ETIMEDOUT; 405 } else { 406 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__); 407 data->error = -EIO; 408 } 409 } else { 410 data->bytes_xfered = host->datasize; 411 } 412 413 data_error = data->error; 414 415 host->data = NULL; 416 417 return data_error; 418 } 419 420 static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat) 421 { 422 struct mmc_command *cmd = host->cmd; 423 int i; 424 u32 a, b, c; 425 426 if (!cmd) 427 return; 428 429 if (stat & STATUS_TIME_OUT_RESP) { 430 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n"); 431 cmd->error = -ETIMEDOUT; 432 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) { 433 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n"); 434 cmd->error = -EILSEQ; 435 } 436 437 if (cmd->flags & MMC_RSP_PRESENT) { 438 if (cmd->flags & MMC_RSP_136) { 439 for (i = 0; i < 4; i++) { 440 a = readw(host->base + MMC_REG_RES_FIFO); 441 b = readw(host->base + MMC_REG_RES_FIFO); 442 cmd->resp[i] = a << 16 | b; 443 } 444 } else { 445 a = readw(host->base + MMC_REG_RES_FIFO); 446 b = readw(host->base + MMC_REG_RES_FIFO); 447 c = readw(host->base + MMC_REG_RES_FIFO); 448 cmd->resp[0] = a << 24 | b << 8 | c >> 8; 449 } 450 } 451 } 452 453 static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask) 454 { 455 u32 stat; 456 unsigned long timeout = jiffies + HZ; 457 458 do { 459 stat = readl(host->base + MMC_REG_STATUS); 460 if (stat & STATUS_ERR_MASK) 461 return stat; 462 if (time_after(jiffies, timeout)) { 463 mxcmci_softreset(host); 464 mxcmci_set_clk_rate(host, host->clock); 465 return STATUS_TIME_OUT_READ; 466 } 467 if (stat & mask) 468 return 0; 469 cpu_relax(); 470 } while (1); 471 } 472 473 static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes) 474 { 475 unsigned int stat; 476 u32 *buf = _buf; 477 478 while (bytes > 3) { 479 stat = mxcmci_poll_status(host, 480 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE); 481 if (stat) 482 return stat; 483 *buf++ = readl(host->base + MMC_REG_BUFFER_ACCESS); 484 bytes -= 4; 485 } 486 487 if (bytes) { 488 u8 *b = (u8 *)buf; 489 u32 tmp; 490 491 stat = mxcmci_poll_status(host, 492 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE); 493 if (stat) 494 return stat; 495 tmp = readl(host->base + MMC_REG_BUFFER_ACCESS); 496 memcpy(b, &tmp, bytes); 497 } 498 499 return 0; 500 } 501 502 static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes) 503 { 504 unsigned int stat; 505 u32 *buf = _buf; 506 507 while (bytes > 3) { 508 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 509 if (stat) 510 return stat; 511 writel(*buf++, host->base + MMC_REG_BUFFER_ACCESS); 512 bytes -= 4; 513 } 514 515 if (bytes) { 516 u8 *b = (u8 *)buf; 517 u32 tmp; 518 519 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 520 if (stat) 521 return stat; 522 523 memcpy(&tmp, b, bytes); 524 writel(tmp, host->base + MMC_REG_BUFFER_ACCESS); 525 } 526 527 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 528 if (stat) 529 return stat; 530 531 return 0; 532 } 533 534 static int mxcmci_transfer_data(struct mxcmci_host *host) 535 { 536 struct mmc_data *data = host->req->data; 537 struct scatterlist *sg; 538 int stat, i; 539 540 host->data = data; 541 host->datasize = 0; 542 543 if (data->flags & MMC_DATA_READ) { 544 for_each_sg(data->sg, sg, data->sg_len, i) { 545 stat = mxcmci_pull(host, sg_virt(sg), sg->length); 546 if (stat) 547 return stat; 548 host->datasize += sg->length; 549 } 550 } else { 551 for_each_sg(data->sg, sg, data->sg_len, i) { 552 stat = mxcmci_push(host, sg_virt(sg), sg->length); 553 if (stat) 554 return stat; 555 host->datasize += sg->length; 556 } 557 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE); 558 if (stat) 559 return stat; 560 } 561 return 0; 562 } 563 564 static void mxcmci_datawork(struct work_struct *work) 565 { 566 struct mxcmci_host *host = container_of(work, struct mxcmci_host, 567 datawork); 568 int datastat = mxcmci_transfer_data(host); 569 570 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE, 571 host->base + MMC_REG_STATUS); 572 mxcmci_finish_data(host, datastat); 573 574 if (host->req->stop) { 575 if (mxcmci_start_cmd(host, host->req->stop, 0)) { 576 mxcmci_finish_request(host, host->req); 577 return; 578 } 579 } else { 580 mxcmci_finish_request(host, host->req); 581 } 582 } 583 584 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat) 585 { 586 struct mmc_data *data = host->data; 587 int data_error; 588 589 if (!data) 590 return; 591 592 data_error = mxcmci_finish_data(host, stat); 593 594 mxcmci_read_response(host, stat); 595 host->cmd = NULL; 596 597 if (host->req->stop) { 598 if (mxcmci_start_cmd(host, host->req->stop, 0)) { 599 mxcmci_finish_request(host, host->req); 600 return; 601 } 602 } else { 603 mxcmci_finish_request(host, host->req); 604 } 605 } 606 607 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat) 608 { 609 mxcmci_read_response(host, stat); 610 host->cmd = NULL; 611 612 if (!host->data && host->req) { 613 mxcmci_finish_request(host, host->req); 614 return; 615 } 616 617 /* For the DMA case the DMA engine handles the data transfer 618 * automatically. For non DMA we have to do it ourselves. 619 * Don't do it in interrupt context though. 620 */ 621 if (!mxcmci_use_dma(host) && host->data) 622 schedule_work(&host->datawork); 623 624 } 625 626 static irqreturn_t mxcmci_irq(int irq, void *devid) 627 { 628 struct mxcmci_host *host = devid; 629 unsigned long flags; 630 bool sdio_irq; 631 u32 stat; 632 633 stat = readl(host->base + MMC_REG_STATUS); 634 writel(stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE | 635 STATUS_WRITE_OP_DONE), host->base + MMC_REG_STATUS); 636 637 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat); 638 639 spin_lock_irqsave(&host->lock, flags); 640 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio; 641 spin_unlock_irqrestore(&host->lock, flags); 642 643 if (mxcmci_use_dma(host) && 644 (stat & (STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE))) 645 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE, 646 host->base + MMC_REG_STATUS); 647 648 if (sdio_irq) { 649 writel(STATUS_SDIO_INT_ACTIVE, host->base + MMC_REG_STATUS); 650 mmc_signal_sdio_irq(host->mmc); 651 } 652 653 if (stat & STATUS_END_CMD_RESP) 654 mxcmci_cmd_done(host, stat); 655 656 if (mxcmci_use_dma(host) && 657 (stat & (STATUS_DATA_TRANS_DONE | STATUS_WRITE_OP_DONE))) { 658 del_timer(&host->watchdog); 659 mxcmci_data_done(host, stat); 660 } 661 662 if (host->default_irq_mask && 663 (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL))) 664 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 665 666 return IRQ_HANDLED; 667 } 668 669 static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req) 670 { 671 struct mxcmci_host *host = mmc_priv(mmc); 672 unsigned int cmdat = host->cmdat; 673 int error; 674 675 WARN_ON(host->req != NULL); 676 677 host->req = req; 678 host->cmdat &= ~CMD_DAT_CONT_INIT; 679 680 if (host->dma) 681 host->do_dma = 1; 682 683 if (req->data) { 684 error = mxcmci_setup_data(host, req->data); 685 if (error) { 686 req->cmd->error = error; 687 goto out; 688 } 689 690 691 cmdat |= CMD_DAT_CONT_DATA_ENABLE; 692 693 if (req->data->flags & MMC_DATA_WRITE) 694 cmdat |= CMD_DAT_CONT_WRITE; 695 } 696 697 error = mxcmci_start_cmd(host, req->cmd, cmdat); 698 699 out: 700 if (error) 701 mxcmci_finish_request(host, req); 702 } 703 704 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios) 705 { 706 unsigned int divider; 707 int prescaler = 0; 708 unsigned int clk_in = clk_get_rate(host->clk_per); 709 710 while (prescaler <= 0x800) { 711 for (divider = 1; divider <= 0xF; divider++) { 712 int x; 713 714 x = (clk_in / (divider + 1)); 715 716 if (prescaler) 717 x /= (prescaler * 2); 718 719 if (x <= clk_ios) 720 break; 721 } 722 if (divider < 0x10) 723 break; 724 725 if (prescaler == 0) 726 prescaler = 1; 727 else 728 prescaler <<= 1; 729 } 730 731 writew((prescaler << 4) | divider, host->base + MMC_REG_CLK_RATE); 732 733 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n", 734 prescaler, divider, clk_in, clk_ios); 735 } 736 737 static int mxcmci_setup_dma(struct mmc_host *mmc) 738 { 739 struct mxcmci_host *host = mmc_priv(mmc); 740 struct dma_slave_config *config = &host->dma_slave_config; 741 742 config->dst_addr = host->res->start + MMC_REG_BUFFER_ACCESS; 743 config->src_addr = host->res->start + MMC_REG_BUFFER_ACCESS; 744 config->dst_addr_width = 4; 745 config->src_addr_width = 4; 746 config->dst_maxburst = host->burstlen; 747 config->src_maxburst = host->burstlen; 748 config->device_fc = false; 749 750 return dmaengine_slave_config(host->dma, config); 751 } 752 753 static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 754 { 755 struct mxcmci_host *host = mmc_priv(mmc); 756 int burstlen, ret; 757 758 /* 759 * use burstlen of 64 (16 words) in 4 bit mode (--> reg value 0) 760 * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16) 761 */ 762 if (ios->bus_width == MMC_BUS_WIDTH_4) 763 burstlen = 16; 764 else 765 burstlen = 4; 766 767 if (mxcmci_use_dma(host) && burstlen != host->burstlen) { 768 host->burstlen = burstlen; 769 ret = mxcmci_setup_dma(mmc); 770 if (ret) { 771 dev_err(mmc_dev(host->mmc), 772 "failed to config DMA channel. Falling back to PIO\n"); 773 dma_release_channel(host->dma); 774 host->do_dma = 0; 775 host->dma = NULL; 776 } 777 } 778 779 if (ios->bus_width == MMC_BUS_WIDTH_4) 780 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4; 781 else 782 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4; 783 784 if (host->power_mode != ios->power_mode) { 785 mxcmci_set_power(host, ios->power_mode, ios->vdd); 786 host->power_mode = ios->power_mode; 787 788 if (ios->power_mode == MMC_POWER_ON) 789 host->cmdat |= CMD_DAT_CONT_INIT; 790 } 791 792 if (ios->clock) { 793 mxcmci_set_clk_rate(host, ios->clock); 794 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK); 795 } else { 796 writew(STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK); 797 } 798 799 host->clock = ios->clock; 800 } 801 802 static irqreturn_t mxcmci_detect_irq(int irq, void *data) 803 { 804 struct mmc_host *mmc = data; 805 806 dev_dbg(mmc_dev(mmc), "%s\n", __func__); 807 808 mmc_detect_change(mmc, msecs_to_jiffies(250)); 809 return IRQ_HANDLED; 810 } 811 812 static int mxcmci_get_ro(struct mmc_host *mmc) 813 { 814 struct mxcmci_host *host = mmc_priv(mmc); 815 816 if (host->pdata && host->pdata->get_ro) 817 return !!host->pdata->get_ro(mmc_dev(mmc)); 818 /* 819 * Board doesn't support read only detection; let the mmc core 820 * decide what to do. 821 */ 822 return -ENOSYS; 823 } 824 825 static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable) 826 { 827 struct mxcmci_host *host = mmc_priv(mmc); 828 unsigned long flags; 829 u32 int_cntr; 830 831 spin_lock_irqsave(&host->lock, flags); 832 host->use_sdio = enable; 833 int_cntr = readl(host->base + MMC_REG_INT_CNTR); 834 835 if (enable) 836 int_cntr |= INT_SDIO_IRQ_EN; 837 else 838 int_cntr &= ~INT_SDIO_IRQ_EN; 839 840 writel(int_cntr, host->base + MMC_REG_INT_CNTR); 841 spin_unlock_irqrestore(&host->lock, flags); 842 } 843 844 static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card) 845 { 846 /* 847 * MX3 SoCs have a silicon bug which corrupts CRC calculation of 848 * multi-block transfers when connected SDIO peripheral doesn't 849 * drive the BUSY line as required by the specs. 850 * One way to prevent this is to only allow 1-bit transfers. 851 */ 852 853 if (cpu_is_mx3() && card->type == MMC_TYPE_SDIO) 854 host->caps &= ~MMC_CAP_4_BIT_DATA; 855 else 856 host->caps |= MMC_CAP_4_BIT_DATA; 857 } 858 859 static bool filter(struct dma_chan *chan, void *param) 860 { 861 struct mxcmci_host *host = param; 862 863 if (!imx_dma_is_general_purpose(chan)) 864 return false; 865 866 chan->private = &host->dma_data; 867 868 return true; 869 } 870 871 static void mxcmci_watchdog(unsigned long data) 872 { 873 struct mmc_host *mmc = (struct mmc_host *)data; 874 struct mxcmci_host *host = mmc_priv(mmc); 875 struct mmc_request *req = host->req; 876 unsigned int stat = readl(host->base + MMC_REG_STATUS); 877 878 if (host->dma_dir == DMA_FROM_DEVICE) { 879 dmaengine_terminate_all(host->dma); 880 dev_err(mmc_dev(host->mmc), 881 "%s: read time out (status = 0x%08x)\n", 882 __func__, stat); 883 } else { 884 dev_err(mmc_dev(host->mmc), 885 "%s: write time out (status = 0x%08x)\n", 886 __func__, stat); 887 mxcmci_softreset(host); 888 } 889 890 /* Mark transfer as erroneus and inform the upper layers */ 891 892 host->data->error = -ETIMEDOUT; 893 host->req = NULL; 894 host->cmd = NULL; 895 host->data = NULL; 896 mmc_request_done(host->mmc, req); 897 } 898 899 static const struct mmc_host_ops mxcmci_ops = { 900 .request = mxcmci_request, 901 .set_ios = mxcmci_set_ios, 902 .get_ro = mxcmci_get_ro, 903 .enable_sdio_irq = mxcmci_enable_sdio_irq, 904 .init_card = mxcmci_init_card, 905 }; 906 907 static int mxcmci_probe(struct platform_device *pdev) 908 { 909 struct mmc_host *mmc; 910 struct mxcmci_host *host = NULL; 911 struct resource *iores, *r; 912 int ret = 0, irq; 913 dma_cap_mask_t mask; 914 915 pr_info("i.MX SDHC driver\n"); 916 917 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 918 irq = platform_get_irq(pdev, 0); 919 if (!iores || irq < 0) 920 return -EINVAL; 921 922 r = request_mem_region(iores->start, resource_size(iores), pdev->name); 923 if (!r) 924 return -EBUSY; 925 926 mmc = mmc_alloc_host(sizeof(struct mxcmci_host), &pdev->dev); 927 if (!mmc) { 928 ret = -ENOMEM; 929 goto out_release_mem; 930 } 931 932 mmc->ops = &mxcmci_ops; 933 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; 934 935 /* MMC core transfer sizes tunable parameters */ 936 mmc->max_segs = 64; 937 mmc->max_blk_size = 2048; 938 mmc->max_blk_count = 65535; 939 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 940 mmc->max_seg_size = mmc->max_req_size; 941 942 host = mmc_priv(mmc); 943 host->base = ioremap(r->start, resource_size(r)); 944 if (!host->base) { 945 ret = -ENOMEM; 946 goto out_free; 947 } 948 949 host->mmc = mmc; 950 host->pdata = pdev->dev.platform_data; 951 spin_lock_init(&host->lock); 952 953 mxcmci_init_ocr(host); 954 955 if (host->pdata && host->pdata->dat3_card_detect) 956 host->default_irq_mask = 957 INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN; 958 else 959 host->default_irq_mask = 0; 960 961 host->res = r; 962 host->irq = irq; 963 964 host->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 965 if (IS_ERR(host->clk_ipg)) { 966 ret = PTR_ERR(host->clk_ipg); 967 goto out_iounmap; 968 } 969 970 host->clk_per = devm_clk_get(&pdev->dev, "per"); 971 if (IS_ERR(host->clk_per)) { 972 ret = PTR_ERR(host->clk_per); 973 goto out_iounmap; 974 } 975 976 clk_prepare_enable(host->clk_per); 977 clk_prepare_enable(host->clk_ipg); 978 979 mxcmci_softreset(host); 980 981 host->rev_no = readw(host->base + MMC_REG_REV_NO); 982 if (host->rev_no != 0x400) { 983 ret = -ENODEV; 984 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n", 985 host->rev_no); 986 goto out_clk_put; 987 } 988 989 mmc->f_min = clk_get_rate(host->clk_per) >> 16; 990 mmc->f_max = clk_get_rate(host->clk_per) >> 1; 991 992 /* recommended in data sheet */ 993 writew(0x2db4, host->base + MMC_REG_READ_TO); 994 995 writel(host->default_irq_mask, host->base + MMC_REG_INT_CNTR); 996 997 r = platform_get_resource(pdev, IORESOURCE_DMA, 0); 998 if (r) { 999 host->dmareq = r->start; 1000 host->dma_data.peripheral_type = IMX_DMATYPE_SDHC; 1001 host->dma_data.priority = DMA_PRIO_LOW; 1002 host->dma_data.dma_request = host->dmareq; 1003 dma_cap_zero(mask); 1004 dma_cap_set(DMA_SLAVE, mask); 1005 host->dma = dma_request_channel(mask, filter, host); 1006 if (host->dma) 1007 mmc->max_seg_size = dma_get_max_seg_size( 1008 host->dma->device->dev); 1009 } 1010 1011 if (!host->dma) 1012 dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n"); 1013 1014 INIT_WORK(&host->datawork, mxcmci_datawork); 1015 1016 ret = request_irq(host->irq, mxcmci_irq, 0, DRIVER_NAME, host); 1017 if (ret) 1018 goto out_free_dma; 1019 1020 platform_set_drvdata(pdev, mmc); 1021 1022 if (host->pdata && host->pdata->init) { 1023 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq, 1024 host->mmc); 1025 if (ret) 1026 goto out_free_irq; 1027 } 1028 1029 mmc_add_host(mmc); 1030 1031 init_timer(&host->watchdog); 1032 host->watchdog.function = &mxcmci_watchdog; 1033 host->watchdog.data = (unsigned long)mmc; 1034 1035 return 0; 1036 1037 out_free_irq: 1038 free_irq(host->irq, host); 1039 out_free_dma: 1040 if (host->dma) 1041 dma_release_channel(host->dma); 1042 out_clk_put: 1043 clk_disable_unprepare(host->clk_per); 1044 clk_disable_unprepare(host->clk_ipg); 1045 out_iounmap: 1046 iounmap(host->base); 1047 out_free: 1048 mmc_free_host(mmc); 1049 out_release_mem: 1050 release_mem_region(iores->start, resource_size(iores)); 1051 return ret; 1052 } 1053 1054 static int mxcmci_remove(struct platform_device *pdev) 1055 { 1056 struct mmc_host *mmc = platform_get_drvdata(pdev); 1057 struct mxcmci_host *host = mmc_priv(mmc); 1058 1059 platform_set_drvdata(pdev, NULL); 1060 1061 mmc_remove_host(mmc); 1062 1063 if (host->vcc) 1064 regulator_put(host->vcc); 1065 1066 if (host->pdata && host->pdata->exit) 1067 host->pdata->exit(&pdev->dev, mmc); 1068 1069 free_irq(host->irq, host); 1070 iounmap(host->base); 1071 1072 if (host->dma) 1073 dma_release_channel(host->dma); 1074 1075 clk_disable_unprepare(host->clk_per); 1076 clk_disable_unprepare(host->clk_ipg); 1077 1078 release_mem_region(host->res->start, resource_size(host->res)); 1079 1080 mmc_free_host(mmc); 1081 1082 return 0; 1083 } 1084 1085 #ifdef CONFIG_PM 1086 static int mxcmci_suspend(struct device *dev) 1087 { 1088 struct mmc_host *mmc = dev_get_drvdata(dev); 1089 struct mxcmci_host *host = mmc_priv(mmc); 1090 int ret = 0; 1091 1092 if (mmc) 1093 ret = mmc_suspend_host(mmc); 1094 clk_disable_unprepare(host->clk_per); 1095 clk_disable_unprepare(host->clk_ipg); 1096 1097 return ret; 1098 } 1099 1100 static int mxcmci_resume(struct device *dev) 1101 { 1102 struct mmc_host *mmc = dev_get_drvdata(dev); 1103 struct mxcmci_host *host = mmc_priv(mmc); 1104 int ret = 0; 1105 1106 clk_prepare_enable(host->clk_per); 1107 clk_prepare_enable(host->clk_ipg); 1108 if (mmc) 1109 ret = mmc_resume_host(mmc); 1110 1111 return ret; 1112 } 1113 1114 static const struct dev_pm_ops mxcmci_pm_ops = { 1115 .suspend = mxcmci_suspend, 1116 .resume = mxcmci_resume, 1117 }; 1118 #endif 1119 1120 static struct platform_driver mxcmci_driver = { 1121 .probe = mxcmci_probe, 1122 .remove = mxcmci_remove, 1123 .driver = { 1124 .name = DRIVER_NAME, 1125 .owner = THIS_MODULE, 1126 #ifdef CONFIG_PM 1127 .pm = &mxcmci_pm_ops, 1128 #endif 1129 } 1130 }; 1131 1132 module_platform_driver(mxcmci_driver); 1133 1134 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver"); 1135 MODULE_AUTHOR("Sascha Hauer, Pengutronix"); 1136 MODULE_LICENSE("GPL"); 1137 MODULE_ALIAS("platform:mxc-mmc"); 1138