1 /* 2 * Marvell MMC/SD/SDIO driver 3 * 4 * Authors: Maen Suleiman, Nicolas Pitre 5 * Copyright (C) 2008-2009 Marvell Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <linux/platform_device.h> 16 #include <linux/mbus.h> 17 #include <linux/delay.h> 18 #include <linux/interrupt.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/scatterlist.h> 21 #include <linux/irq.h> 22 #include <linux/clk.h> 23 #include <linux/of_irq.h> 24 #include <linux/mmc/host.h> 25 #include <linux/mmc/slot-gpio.h> 26 27 #include <asm/sizes.h> 28 #include <asm/unaligned.h> 29 30 #include "mvsdio.h" 31 32 #define DRIVER_NAME "mvsdio" 33 34 static int maxfreq; 35 static int nodma; 36 37 struct mvsd_host { 38 void __iomem *base; 39 struct mmc_request *mrq; 40 spinlock_t lock; 41 unsigned int xfer_mode; 42 unsigned int intr_en; 43 unsigned int ctrl; 44 unsigned int pio_size; 45 void *pio_ptr; 46 unsigned int sg_frags; 47 unsigned int ns_per_clk; 48 unsigned int clock; 49 unsigned int base_clock; 50 struct timer_list timer; 51 struct mmc_host *mmc; 52 struct device *dev; 53 struct clk *clk; 54 }; 55 56 #define mvsd_write(offs, val) writel(val, iobase + (offs)) 57 #define mvsd_read(offs) readl(iobase + (offs)) 58 59 static int mvsd_setup_data(struct mvsd_host *host, struct mmc_data *data) 60 { 61 void __iomem *iobase = host->base; 62 unsigned int tmout; 63 int tmout_index; 64 65 /* 66 * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE 67 * register is sometimes not set before a while when some 68 * "unusual" data block sizes are used (such as with the SWITCH 69 * command), even despite the fact that the XFER_DONE interrupt 70 * was raised. And if another data transfer starts before 71 * this bit comes to good sense (which eventually happens by 72 * itself) then the new transfer simply fails with a timeout. 73 */ 74 if (!(mvsd_read(MVSD_HW_STATE) & (1 << 13))) { 75 unsigned long t = jiffies + HZ; 76 unsigned int hw_state, count = 0; 77 do { 78 hw_state = mvsd_read(MVSD_HW_STATE); 79 if (time_after(jiffies, t)) { 80 dev_warn(host->dev, "FIFO_EMPTY bit missing\n"); 81 break; 82 } 83 count++; 84 } while (!(hw_state & (1 << 13))); 85 dev_dbg(host->dev, "*** wait for FIFO_EMPTY bit " 86 "(hw=0x%04x, count=%d, jiffies=%ld)\n", 87 hw_state, count, jiffies - (t - HZ)); 88 } 89 90 /* If timeout=0 then maximum timeout index is used. */ 91 tmout = DIV_ROUND_UP(data->timeout_ns, host->ns_per_clk); 92 tmout += data->timeout_clks; 93 tmout_index = fls(tmout - 1) - 12; 94 if (tmout_index < 0) 95 tmout_index = 0; 96 if (tmout_index > MVSD_HOST_CTRL_TMOUT_MAX) 97 tmout_index = MVSD_HOST_CTRL_TMOUT_MAX; 98 99 dev_dbg(host->dev, "data %s at 0x%08x: blocks=%d blksz=%d tmout=%u (%d)\n", 100 (data->flags & MMC_DATA_READ) ? "read" : "write", 101 (u32)sg_virt(data->sg), data->blocks, data->blksz, 102 tmout, tmout_index); 103 104 host->ctrl &= ~MVSD_HOST_CTRL_TMOUT_MASK; 105 host->ctrl |= MVSD_HOST_CTRL_TMOUT(tmout_index); 106 mvsd_write(MVSD_HOST_CTRL, host->ctrl); 107 mvsd_write(MVSD_BLK_COUNT, data->blocks); 108 mvsd_write(MVSD_BLK_SIZE, data->blksz); 109 110 if (nodma || (data->blksz | data->sg->offset) & 3 || 111 ((!(data->flags & MMC_DATA_READ) && data->sg->offset & 0x3f))) { 112 /* 113 * We cannot do DMA on a buffer which offset or size 114 * is not aligned on a 4-byte boundary. 115 * 116 * It also appears the host to card DMA can corrupt 117 * data when the buffer is not aligned on a 64 byte 118 * boundary. 119 */ 120 host->pio_size = data->blocks * data->blksz; 121 host->pio_ptr = sg_virt(data->sg); 122 if (!nodma) 123 dev_dbg(host->dev, "fallback to PIO for data at 0x%p size %d\n", 124 host->pio_ptr, host->pio_size); 125 return 1; 126 } else { 127 dma_addr_t phys_addr; 128 129 host->sg_frags = dma_map_sg(mmc_dev(host->mmc), 130 data->sg, data->sg_len, 131 mmc_get_dma_dir(data)); 132 phys_addr = sg_dma_address(data->sg); 133 mvsd_write(MVSD_SYS_ADDR_LOW, (u32)phys_addr & 0xffff); 134 mvsd_write(MVSD_SYS_ADDR_HI, (u32)phys_addr >> 16); 135 return 0; 136 } 137 } 138 139 static void mvsd_request(struct mmc_host *mmc, struct mmc_request *mrq) 140 { 141 struct mvsd_host *host = mmc_priv(mmc); 142 void __iomem *iobase = host->base; 143 struct mmc_command *cmd = mrq->cmd; 144 u32 cmdreg = 0, xfer = 0, intr = 0; 145 unsigned long flags; 146 unsigned int timeout; 147 148 BUG_ON(host->mrq != NULL); 149 host->mrq = mrq; 150 151 dev_dbg(host->dev, "cmd %d (hw state 0x%04x)\n", 152 cmd->opcode, mvsd_read(MVSD_HW_STATE)); 153 154 cmdreg = MVSD_CMD_INDEX(cmd->opcode); 155 156 if (cmd->flags & MMC_RSP_BUSY) 157 cmdreg |= MVSD_CMD_RSP_48BUSY; 158 else if (cmd->flags & MMC_RSP_136) 159 cmdreg |= MVSD_CMD_RSP_136; 160 else if (cmd->flags & MMC_RSP_PRESENT) 161 cmdreg |= MVSD_CMD_RSP_48; 162 else 163 cmdreg |= MVSD_CMD_RSP_NONE; 164 165 if (cmd->flags & MMC_RSP_CRC) 166 cmdreg |= MVSD_CMD_CHECK_CMDCRC; 167 168 if (cmd->flags & MMC_RSP_OPCODE) 169 cmdreg |= MVSD_CMD_INDX_CHECK; 170 171 if (cmd->flags & MMC_RSP_PRESENT) { 172 cmdreg |= MVSD_UNEXPECTED_RESP; 173 intr |= MVSD_NOR_UNEXP_RSP; 174 } 175 176 if (mrq->data) { 177 struct mmc_data *data = mrq->data; 178 int pio; 179 180 cmdreg |= MVSD_CMD_DATA_PRESENT | MVSD_CMD_CHECK_DATACRC16; 181 xfer |= MVSD_XFER_MODE_HW_WR_DATA_EN; 182 if (data->flags & MMC_DATA_READ) 183 xfer |= MVSD_XFER_MODE_TO_HOST; 184 185 pio = mvsd_setup_data(host, data); 186 if (pio) { 187 xfer |= MVSD_XFER_MODE_PIO; 188 /* PIO section of mvsd_irq has comments on those bits */ 189 if (data->flags & MMC_DATA_WRITE) 190 intr |= MVSD_NOR_TX_AVAIL; 191 else if (host->pio_size > 32) 192 intr |= MVSD_NOR_RX_FIFO_8W; 193 else 194 intr |= MVSD_NOR_RX_READY; 195 } 196 197 if (data->stop) { 198 struct mmc_command *stop = data->stop; 199 u32 cmd12reg = 0; 200 201 mvsd_write(MVSD_AUTOCMD12_ARG_LOW, stop->arg & 0xffff); 202 mvsd_write(MVSD_AUTOCMD12_ARG_HI, stop->arg >> 16); 203 204 if (stop->flags & MMC_RSP_BUSY) 205 cmd12reg |= MVSD_AUTOCMD12_BUSY; 206 if (stop->flags & MMC_RSP_OPCODE) 207 cmd12reg |= MVSD_AUTOCMD12_INDX_CHECK; 208 cmd12reg |= MVSD_AUTOCMD12_INDEX(stop->opcode); 209 mvsd_write(MVSD_AUTOCMD12_CMD, cmd12reg); 210 211 xfer |= MVSD_XFER_MODE_AUTO_CMD12; 212 intr |= MVSD_NOR_AUTOCMD12_DONE; 213 } else { 214 intr |= MVSD_NOR_XFER_DONE; 215 } 216 } else { 217 intr |= MVSD_NOR_CMD_DONE; 218 } 219 220 mvsd_write(MVSD_ARG_LOW, cmd->arg & 0xffff); 221 mvsd_write(MVSD_ARG_HI, cmd->arg >> 16); 222 223 spin_lock_irqsave(&host->lock, flags); 224 225 host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN; 226 host->xfer_mode |= xfer; 227 mvsd_write(MVSD_XFER_MODE, host->xfer_mode); 228 229 mvsd_write(MVSD_NOR_INTR_STATUS, ~MVSD_NOR_CARD_INT); 230 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff); 231 mvsd_write(MVSD_CMD, cmdreg); 232 233 host->intr_en &= MVSD_NOR_CARD_INT; 234 host->intr_en |= intr | MVSD_NOR_ERROR; 235 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); 236 mvsd_write(MVSD_ERR_INTR_EN, 0xffff); 237 238 timeout = cmd->busy_timeout ? cmd->busy_timeout : 5000; 239 mod_timer(&host->timer, jiffies + msecs_to_jiffies(timeout)); 240 241 spin_unlock_irqrestore(&host->lock, flags); 242 } 243 244 static u32 mvsd_finish_cmd(struct mvsd_host *host, struct mmc_command *cmd, 245 u32 err_status) 246 { 247 void __iomem *iobase = host->base; 248 249 if (cmd->flags & MMC_RSP_136) { 250 unsigned int response[8], i; 251 for (i = 0; i < 8; i++) 252 response[i] = mvsd_read(MVSD_RSP(i)); 253 cmd->resp[0] = ((response[0] & 0x03ff) << 22) | 254 ((response[1] & 0xffff) << 6) | 255 ((response[2] & 0xfc00) >> 10); 256 cmd->resp[1] = ((response[2] & 0x03ff) << 22) | 257 ((response[3] & 0xffff) << 6) | 258 ((response[4] & 0xfc00) >> 10); 259 cmd->resp[2] = ((response[4] & 0x03ff) << 22) | 260 ((response[5] & 0xffff) << 6) | 261 ((response[6] & 0xfc00) >> 10); 262 cmd->resp[3] = ((response[6] & 0x03ff) << 22) | 263 ((response[7] & 0x3fff) << 8); 264 } else if (cmd->flags & MMC_RSP_PRESENT) { 265 unsigned int response[3], i; 266 for (i = 0; i < 3; i++) 267 response[i] = mvsd_read(MVSD_RSP(i)); 268 cmd->resp[0] = ((response[2] & 0x003f) << (8 - 8)) | 269 ((response[1] & 0xffff) << (14 - 8)) | 270 ((response[0] & 0x03ff) << (30 - 8)); 271 cmd->resp[1] = ((response[0] & 0xfc00) >> 10); 272 cmd->resp[2] = 0; 273 cmd->resp[3] = 0; 274 } 275 276 if (err_status & MVSD_ERR_CMD_TIMEOUT) { 277 cmd->error = -ETIMEDOUT; 278 } else if (err_status & (MVSD_ERR_CMD_CRC | MVSD_ERR_CMD_ENDBIT | 279 MVSD_ERR_CMD_INDEX | MVSD_ERR_CMD_STARTBIT)) { 280 cmd->error = -EILSEQ; 281 } 282 err_status &= ~(MVSD_ERR_CMD_TIMEOUT | MVSD_ERR_CMD_CRC | 283 MVSD_ERR_CMD_ENDBIT | MVSD_ERR_CMD_INDEX | 284 MVSD_ERR_CMD_STARTBIT); 285 286 return err_status; 287 } 288 289 static u32 mvsd_finish_data(struct mvsd_host *host, struct mmc_data *data, 290 u32 err_status) 291 { 292 void __iomem *iobase = host->base; 293 294 if (host->pio_ptr) { 295 host->pio_ptr = NULL; 296 host->pio_size = 0; 297 } else { 298 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_frags, 299 mmc_get_dma_dir(data)); 300 } 301 302 if (err_status & MVSD_ERR_DATA_TIMEOUT) 303 data->error = -ETIMEDOUT; 304 else if (err_status & (MVSD_ERR_DATA_CRC | MVSD_ERR_DATA_ENDBIT)) 305 data->error = -EILSEQ; 306 else if (err_status & MVSD_ERR_XFER_SIZE) 307 data->error = -EBADE; 308 err_status &= ~(MVSD_ERR_DATA_TIMEOUT | MVSD_ERR_DATA_CRC | 309 MVSD_ERR_DATA_ENDBIT | MVSD_ERR_XFER_SIZE); 310 311 dev_dbg(host->dev, "data done: blocks_left=%d, bytes_left=%d\n", 312 mvsd_read(MVSD_CURR_BLK_LEFT), mvsd_read(MVSD_CURR_BYTE_LEFT)); 313 data->bytes_xfered = 314 (data->blocks - mvsd_read(MVSD_CURR_BLK_LEFT)) * data->blksz; 315 /* We can't be sure about the last block when errors are detected */ 316 if (data->bytes_xfered && data->error) 317 data->bytes_xfered -= data->blksz; 318 319 /* Handle Auto cmd 12 response */ 320 if (data->stop) { 321 unsigned int response[3], i; 322 for (i = 0; i < 3; i++) 323 response[i] = mvsd_read(MVSD_AUTO_RSP(i)); 324 data->stop->resp[0] = ((response[2] & 0x003f) << (8 - 8)) | 325 ((response[1] & 0xffff) << (14 - 8)) | 326 ((response[0] & 0x03ff) << (30 - 8)); 327 data->stop->resp[1] = ((response[0] & 0xfc00) >> 10); 328 data->stop->resp[2] = 0; 329 data->stop->resp[3] = 0; 330 331 if (err_status & MVSD_ERR_AUTOCMD12) { 332 u32 err_cmd12 = mvsd_read(MVSD_AUTOCMD12_ERR_STATUS); 333 dev_dbg(host->dev, "c12err 0x%04x\n", err_cmd12); 334 if (err_cmd12 & MVSD_AUTOCMD12_ERR_NOTEXE) 335 data->stop->error = -ENOEXEC; 336 else if (err_cmd12 & MVSD_AUTOCMD12_ERR_TIMEOUT) 337 data->stop->error = -ETIMEDOUT; 338 else if (err_cmd12) 339 data->stop->error = -EILSEQ; 340 err_status &= ~MVSD_ERR_AUTOCMD12; 341 } 342 } 343 344 return err_status; 345 } 346 347 static irqreturn_t mvsd_irq(int irq, void *dev) 348 { 349 struct mvsd_host *host = dev; 350 void __iomem *iobase = host->base; 351 u32 intr_status, intr_done_mask; 352 int irq_handled = 0; 353 354 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); 355 dev_dbg(host->dev, "intr 0x%04x intr_en 0x%04x hw_state 0x%04x\n", 356 intr_status, mvsd_read(MVSD_NOR_INTR_EN), 357 mvsd_read(MVSD_HW_STATE)); 358 359 /* 360 * It looks like, SDIO IP can issue one late, spurious irq 361 * although all irqs should be disabled. To work around this, 362 * bail out early, if we didn't expect any irqs to occur. 363 */ 364 if (!mvsd_read(MVSD_NOR_INTR_EN) && !mvsd_read(MVSD_ERR_INTR_EN)) { 365 dev_dbg(host->dev, "spurious irq detected intr 0x%04x intr_en 0x%04x erri 0x%04x erri_en 0x%04x\n", 366 mvsd_read(MVSD_NOR_INTR_STATUS), 367 mvsd_read(MVSD_NOR_INTR_EN), 368 mvsd_read(MVSD_ERR_INTR_STATUS), 369 mvsd_read(MVSD_ERR_INTR_EN)); 370 return IRQ_HANDLED; 371 } 372 373 spin_lock(&host->lock); 374 375 /* PIO handling, if needed. Messy business... */ 376 if (host->pio_size && 377 (intr_status & host->intr_en & 378 (MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W))) { 379 u16 *p = host->pio_ptr; 380 int s = host->pio_size; 381 while (s >= 32 && (intr_status & MVSD_NOR_RX_FIFO_8W)) { 382 readsw(iobase + MVSD_FIFO, p, 16); 383 p += 16; 384 s -= 32; 385 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); 386 } 387 /* 388 * Normally we'd use < 32 here, but the RX_FIFO_8W bit 389 * doesn't appear to assert when there is exactly 32 bytes 390 * (8 words) left to fetch in a transfer. 391 */ 392 if (s <= 32) { 393 while (s >= 4 && (intr_status & MVSD_NOR_RX_READY)) { 394 put_unaligned(mvsd_read(MVSD_FIFO), p++); 395 put_unaligned(mvsd_read(MVSD_FIFO), p++); 396 s -= 4; 397 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); 398 } 399 if (s && s < 4 && (intr_status & MVSD_NOR_RX_READY)) { 400 u16 val[2] = {0, 0}; 401 val[0] = mvsd_read(MVSD_FIFO); 402 val[1] = mvsd_read(MVSD_FIFO); 403 memcpy(p, ((void *)&val) + 4 - s, s); 404 s = 0; 405 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); 406 } 407 if (s == 0) { 408 host->intr_en &= 409 ~(MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W); 410 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); 411 } else if (host->intr_en & MVSD_NOR_RX_FIFO_8W) { 412 host->intr_en &= ~MVSD_NOR_RX_FIFO_8W; 413 host->intr_en |= MVSD_NOR_RX_READY; 414 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); 415 } 416 } 417 dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n", 418 s, intr_status, mvsd_read(MVSD_HW_STATE)); 419 host->pio_ptr = p; 420 host->pio_size = s; 421 irq_handled = 1; 422 } else if (host->pio_size && 423 (intr_status & host->intr_en & 424 (MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W))) { 425 u16 *p = host->pio_ptr; 426 int s = host->pio_size; 427 /* 428 * The TX_FIFO_8W bit is unreliable. When set, bursting 429 * 16 halfwords all at once in the FIFO drops data. Actually 430 * TX_AVAIL does go off after only one word is pushed even if 431 * TX_FIFO_8W remains set. 432 */ 433 while (s >= 4 && (intr_status & MVSD_NOR_TX_AVAIL)) { 434 mvsd_write(MVSD_FIFO, get_unaligned(p++)); 435 mvsd_write(MVSD_FIFO, get_unaligned(p++)); 436 s -= 4; 437 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); 438 } 439 if (s < 4) { 440 if (s && (intr_status & MVSD_NOR_TX_AVAIL)) { 441 u16 val[2] = {0, 0}; 442 memcpy(((void *)&val) + 4 - s, p, s); 443 mvsd_write(MVSD_FIFO, val[0]); 444 mvsd_write(MVSD_FIFO, val[1]); 445 s = 0; 446 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); 447 } 448 if (s == 0) { 449 host->intr_en &= 450 ~(MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W); 451 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); 452 } 453 } 454 dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n", 455 s, intr_status, mvsd_read(MVSD_HW_STATE)); 456 host->pio_ptr = p; 457 host->pio_size = s; 458 irq_handled = 1; 459 } 460 461 mvsd_write(MVSD_NOR_INTR_STATUS, intr_status); 462 463 intr_done_mask = MVSD_NOR_CARD_INT | MVSD_NOR_RX_READY | 464 MVSD_NOR_RX_FIFO_8W | MVSD_NOR_TX_FIFO_8W; 465 if (intr_status & host->intr_en & ~intr_done_mask) { 466 struct mmc_request *mrq = host->mrq; 467 struct mmc_command *cmd = mrq->cmd; 468 u32 err_status = 0; 469 470 del_timer(&host->timer); 471 host->mrq = NULL; 472 473 host->intr_en &= MVSD_NOR_CARD_INT; 474 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); 475 mvsd_write(MVSD_ERR_INTR_EN, 0); 476 477 spin_unlock(&host->lock); 478 479 if (intr_status & MVSD_NOR_UNEXP_RSP) { 480 cmd->error = -EPROTO; 481 } else if (intr_status & MVSD_NOR_ERROR) { 482 err_status = mvsd_read(MVSD_ERR_INTR_STATUS); 483 dev_dbg(host->dev, "err 0x%04x\n", err_status); 484 } 485 486 err_status = mvsd_finish_cmd(host, cmd, err_status); 487 if (mrq->data) 488 err_status = mvsd_finish_data(host, mrq->data, err_status); 489 if (err_status) { 490 dev_err(host->dev, "unhandled error status %#04x\n", 491 err_status); 492 cmd->error = -ENOMSG; 493 } 494 495 mmc_request_done(host->mmc, mrq); 496 irq_handled = 1; 497 } else 498 spin_unlock(&host->lock); 499 500 if (intr_status & MVSD_NOR_CARD_INT) { 501 mmc_signal_sdio_irq(host->mmc); 502 irq_handled = 1; 503 } 504 505 if (irq_handled) 506 return IRQ_HANDLED; 507 508 dev_err(host->dev, "unhandled interrupt status=0x%04x en=0x%04x pio=%d\n", 509 intr_status, host->intr_en, host->pio_size); 510 return IRQ_NONE; 511 } 512 513 static void mvsd_timeout_timer(struct timer_list *t) 514 { 515 struct mvsd_host *host = from_timer(host, t, timer); 516 void __iomem *iobase = host->base; 517 struct mmc_request *mrq; 518 unsigned long flags; 519 520 spin_lock_irqsave(&host->lock, flags); 521 mrq = host->mrq; 522 if (mrq) { 523 dev_err(host->dev, "Timeout waiting for hardware interrupt.\n"); 524 dev_err(host->dev, "hw_state=0x%04x, intr_status=0x%04x intr_en=0x%04x\n", 525 mvsd_read(MVSD_HW_STATE), 526 mvsd_read(MVSD_NOR_INTR_STATUS), 527 mvsd_read(MVSD_NOR_INTR_EN)); 528 529 host->mrq = NULL; 530 531 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW); 532 533 host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN; 534 mvsd_write(MVSD_XFER_MODE, host->xfer_mode); 535 536 host->intr_en &= MVSD_NOR_CARD_INT; 537 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); 538 mvsd_write(MVSD_ERR_INTR_EN, 0); 539 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff); 540 541 mrq->cmd->error = -ETIMEDOUT; 542 mvsd_finish_cmd(host, mrq->cmd, 0); 543 if (mrq->data) { 544 mrq->data->error = -ETIMEDOUT; 545 mvsd_finish_data(host, mrq->data, 0); 546 } 547 } 548 spin_unlock_irqrestore(&host->lock, flags); 549 550 if (mrq) 551 mmc_request_done(host->mmc, mrq); 552 } 553 554 static void mvsd_enable_sdio_irq(struct mmc_host *mmc, int enable) 555 { 556 struct mvsd_host *host = mmc_priv(mmc); 557 void __iomem *iobase = host->base; 558 unsigned long flags; 559 560 spin_lock_irqsave(&host->lock, flags); 561 if (enable) { 562 host->xfer_mode |= MVSD_XFER_MODE_INT_CHK_EN; 563 host->intr_en |= MVSD_NOR_CARD_INT; 564 } else { 565 host->xfer_mode &= ~MVSD_XFER_MODE_INT_CHK_EN; 566 host->intr_en &= ~MVSD_NOR_CARD_INT; 567 } 568 mvsd_write(MVSD_XFER_MODE, host->xfer_mode); 569 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); 570 spin_unlock_irqrestore(&host->lock, flags); 571 } 572 573 static void mvsd_power_up(struct mvsd_host *host) 574 { 575 void __iomem *iobase = host->base; 576 dev_dbg(host->dev, "power up\n"); 577 mvsd_write(MVSD_NOR_INTR_EN, 0); 578 mvsd_write(MVSD_ERR_INTR_EN, 0); 579 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW); 580 mvsd_write(MVSD_XFER_MODE, 0); 581 mvsd_write(MVSD_NOR_STATUS_EN, 0xffff); 582 mvsd_write(MVSD_ERR_STATUS_EN, 0xffff); 583 mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff); 584 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff); 585 } 586 587 static void mvsd_power_down(struct mvsd_host *host) 588 { 589 void __iomem *iobase = host->base; 590 dev_dbg(host->dev, "power down\n"); 591 mvsd_write(MVSD_NOR_INTR_EN, 0); 592 mvsd_write(MVSD_ERR_INTR_EN, 0); 593 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW); 594 mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK); 595 mvsd_write(MVSD_NOR_STATUS_EN, 0); 596 mvsd_write(MVSD_ERR_STATUS_EN, 0); 597 mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff); 598 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff); 599 } 600 601 static void mvsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 602 { 603 struct mvsd_host *host = mmc_priv(mmc); 604 void __iomem *iobase = host->base; 605 u32 ctrl_reg = 0; 606 607 if (ios->power_mode == MMC_POWER_UP) 608 mvsd_power_up(host); 609 610 if (ios->clock == 0) { 611 mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK); 612 mvsd_write(MVSD_CLK_DIV, MVSD_BASE_DIV_MAX); 613 host->clock = 0; 614 dev_dbg(host->dev, "clock off\n"); 615 } else if (ios->clock != host->clock) { 616 u32 m = DIV_ROUND_UP(host->base_clock, ios->clock) - 1; 617 if (m > MVSD_BASE_DIV_MAX) 618 m = MVSD_BASE_DIV_MAX; 619 mvsd_write(MVSD_CLK_DIV, m); 620 host->clock = ios->clock; 621 host->ns_per_clk = 1000000000 / (host->base_clock / (m+1)); 622 dev_dbg(host->dev, "clock=%d (%d), div=0x%04x\n", 623 ios->clock, host->base_clock / (m+1), m); 624 } 625 626 /* default transfer mode */ 627 ctrl_reg |= MVSD_HOST_CTRL_BIG_ENDIAN; 628 ctrl_reg &= ~MVSD_HOST_CTRL_LSB_FIRST; 629 630 /* default to maximum timeout */ 631 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_MASK; 632 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_EN; 633 634 if (ios->bus_mode == MMC_BUSMODE_PUSHPULL) 635 ctrl_reg |= MVSD_HOST_CTRL_PUSH_PULL_EN; 636 637 if (ios->bus_width == MMC_BUS_WIDTH_4) 638 ctrl_reg |= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS; 639 640 /* 641 * The HI_SPEED_EN bit is causing trouble with many (but not all) 642 * high speed SD, SDHC and SDIO cards. Not enabling that bit 643 * makes all cards work. So let's just ignore that bit for now 644 * and revisit this issue if problems for not enabling this bit 645 * are ever reported. 646 */ 647 #if 0 648 if (ios->timing == MMC_TIMING_MMC_HS || 649 ios->timing == MMC_TIMING_SD_HS) 650 ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN; 651 #endif 652 653 host->ctrl = ctrl_reg; 654 mvsd_write(MVSD_HOST_CTRL, ctrl_reg); 655 dev_dbg(host->dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg, 656 (ctrl_reg & MVSD_HOST_CTRL_PUSH_PULL_EN) ? 657 "push-pull" : "open-drain", 658 (ctrl_reg & MVSD_HOST_CTRL_DATA_WIDTH_4_BITS) ? 659 "4bit-width" : "1bit-width", 660 (ctrl_reg & MVSD_HOST_CTRL_HI_SPEED_EN) ? 661 "high-speed" : ""); 662 663 if (ios->power_mode == MMC_POWER_OFF) 664 mvsd_power_down(host); 665 } 666 667 static const struct mmc_host_ops mvsd_ops = { 668 .request = mvsd_request, 669 .get_ro = mmc_gpio_get_ro, 670 .set_ios = mvsd_set_ios, 671 .enable_sdio_irq = mvsd_enable_sdio_irq, 672 }; 673 674 static void 675 mv_conf_mbus_windows(struct mvsd_host *host, 676 const struct mbus_dram_target_info *dram) 677 { 678 void __iomem *iobase = host->base; 679 int i; 680 681 for (i = 0; i < 4; i++) { 682 writel(0, iobase + MVSD_WINDOW_CTRL(i)); 683 writel(0, iobase + MVSD_WINDOW_BASE(i)); 684 } 685 686 for (i = 0; i < dram->num_cs; i++) { 687 const struct mbus_dram_window *cs = dram->cs + i; 688 writel(((cs->size - 1) & 0xffff0000) | 689 (cs->mbus_attr << 8) | 690 (dram->mbus_dram_target_id << 4) | 1, 691 iobase + MVSD_WINDOW_CTRL(i)); 692 writel(cs->base, iobase + MVSD_WINDOW_BASE(i)); 693 } 694 } 695 696 static int mvsd_probe(struct platform_device *pdev) 697 { 698 struct device_node *np = pdev->dev.of_node; 699 struct mmc_host *mmc = NULL; 700 struct mvsd_host *host = NULL; 701 const struct mbus_dram_target_info *dram; 702 struct resource *r; 703 int ret, irq; 704 705 if (!np) { 706 dev_err(&pdev->dev, "no DT node\n"); 707 return -ENODEV; 708 } 709 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 710 irq = platform_get_irq(pdev, 0); 711 if (!r || irq < 0) 712 return -ENXIO; 713 714 mmc = mmc_alloc_host(sizeof(struct mvsd_host), &pdev->dev); 715 if (!mmc) { 716 ret = -ENOMEM; 717 goto out; 718 } 719 720 host = mmc_priv(mmc); 721 host->mmc = mmc; 722 host->dev = &pdev->dev; 723 724 /* 725 * Some non-DT platforms do not pass a clock, and the clock 726 * frequency is passed through platform_data. On DT platforms, 727 * a clock must always be passed, even if there is no gatable 728 * clock associated to the SDIO interface (it can simply be a 729 * fixed rate clock). 730 */ 731 host->clk = devm_clk_get(&pdev->dev, NULL); 732 if (IS_ERR(host->clk)) { 733 dev_err(&pdev->dev, "no clock associated\n"); 734 ret = -EINVAL; 735 goto out; 736 } 737 clk_prepare_enable(host->clk); 738 739 mmc->ops = &mvsd_ops; 740 741 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 742 743 mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX); 744 mmc->f_max = MVSD_CLOCKRATE_MAX; 745 746 mmc->max_blk_size = 2048; 747 mmc->max_blk_count = 65535; 748 749 mmc->max_segs = 1; 750 mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count; 751 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 752 753 host->base_clock = clk_get_rate(host->clk) / 2; 754 ret = mmc_of_parse(mmc); 755 if (ret < 0) 756 goto out; 757 if (maxfreq) 758 mmc->f_max = maxfreq; 759 760 mmc->caps |= MMC_CAP_ERASE; 761 762 spin_lock_init(&host->lock); 763 764 host->base = devm_ioremap_resource(&pdev->dev, r); 765 if (IS_ERR(host->base)) { 766 ret = PTR_ERR(host->base); 767 goto out; 768 } 769 770 /* (Re-)program MBUS remapping windows if we are asked to. */ 771 dram = mv_mbus_dram_info(); 772 if (dram) 773 mv_conf_mbus_windows(host, dram); 774 775 mvsd_power_down(host); 776 777 ret = devm_request_irq(&pdev->dev, irq, mvsd_irq, 0, DRIVER_NAME, host); 778 if (ret) { 779 dev_err(&pdev->dev, "cannot assign irq %d\n", irq); 780 goto out; 781 } 782 783 timer_setup(&host->timer, mvsd_timeout_timer, 0); 784 platform_set_drvdata(pdev, mmc); 785 ret = mmc_add_host(mmc); 786 if (ret) 787 goto out; 788 789 if (!(mmc->caps & MMC_CAP_NEEDS_POLL)) 790 dev_dbg(&pdev->dev, "using GPIO for card detection\n"); 791 else 792 dev_dbg(&pdev->dev, "lacking card detect (fall back to polling)\n"); 793 794 return 0; 795 796 out: 797 if (mmc) { 798 if (!IS_ERR(host->clk)) 799 clk_disable_unprepare(host->clk); 800 mmc_free_host(mmc); 801 } 802 803 return ret; 804 } 805 806 static int mvsd_remove(struct platform_device *pdev) 807 { 808 struct mmc_host *mmc = platform_get_drvdata(pdev); 809 810 struct mvsd_host *host = mmc_priv(mmc); 811 812 mmc_remove_host(mmc); 813 del_timer_sync(&host->timer); 814 mvsd_power_down(host); 815 816 if (!IS_ERR(host->clk)) 817 clk_disable_unprepare(host->clk); 818 mmc_free_host(mmc); 819 820 return 0; 821 } 822 823 static const struct of_device_id mvsdio_dt_ids[] = { 824 { .compatible = "marvell,orion-sdio" }, 825 { /* sentinel */ } 826 }; 827 MODULE_DEVICE_TABLE(of, mvsdio_dt_ids); 828 829 static struct platform_driver mvsd_driver = { 830 .probe = mvsd_probe, 831 .remove = mvsd_remove, 832 .driver = { 833 .name = DRIVER_NAME, 834 .of_match_table = mvsdio_dt_ids, 835 }, 836 }; 837 838 module_platform_driver(mvsd_driver); 839 840 /* maximum card clock frequency (default 50MHz) */ 841 module_param(maxfreq, int, 0); 842 843 /* force PIO transfers all the time */ 844 module_param(nodma, int, 0); 845 846 MODULE_AUTHOR("Maen Suleiman, Nicolas Pitre"); 847 MODULE_DESCRIPTION("Marvell MMC,SD,SDIO Host Controller driver"); 848 MODULE_LICENSE("GPL"); 849 MODULE_ALIAS("platform:mvsdio"); 850