1236caa7cSMaen Suleiman /* 2236caa7cSMaen Suleiman * Marvell MMC/SD/SDIO driver 3236caa7cSMaen Suleiman * 4236caa7cSMaen Suleiman * Authors: Maen Suleiman, Nicolas Pitre 5236caa7cSMaen Suleiman * Copyright (C) 2008-2009 Marvell Ltd. 6236caa7cSMaen Suleiman * 7236caa7cSMaen Suleiman * This program is free software; you can redistribute it and/or modify 8236caa7cSMaen Suleiman * it under the terms of the GNU General Public License version 2 as 9236caa7cSMaen Suleiman * published by the Free Software Foundation. 10236caa7cSMaen Suleiman */ 11236caa7cSMaen Suleiman 12236caa7cSMaen Suleiman #include <linux/module.h> 13236caa7cSMaen Suleiman #include <linux/init.h> 14236caa7cSMaen Suleiman #include <linux/io.h> 15236caa7cSMaen Suleiman #include <linux/platform_device.h> 16236caa7cSMaen Suleiman #include <linux/mbus.h> 17236caa7cSMaen Suleiman #include <linux/delay.h> 18236caa7cSMaen Suleiman #include <linux/interrupt.h> 19236caa7cSMaen Suleiman #include <linux/dma-mapping.h> 20236caa7cSMaen Suleiman #include <linux/scatterlist.h> 21236caa7cSMaen Suleiman #include <linux/irq.h> 22f4f7561eSAndrew Lunn #include <linux/clk.h> 23236caa7cSMaen Suleiman #include <linux/gpio.h> 24236caa7cSMaen Suleiman #include <linux/mmc/host.h> 25236caa7cSMaen Suleiman 26236caa7cSMaen Suleiman #include <asm/sizes.h> 27236caa7cSMaen Suleiman #include <asm/unaligned.h> 28236caa7cSMaen Suleiman #include <plat/mvsdio.h> 29236caa7cSMaen Suleiman 30236caa7cSMaen Suleiman #include "mvsdio.h" 31236caa7cSMaen Suleiman 32236caa7cSMaen Suleiman #define DRIVER_NAME "mvsdio" 33236caa7cSMaen Suleiman 34236caa7cSMaen Suleiman static int maxfreq = MVSD_CLOCKRATE_MAX; 35236caa7cSMaen Suleiman static int nodma; 36236caa7cSMaen Suleiman 37236caa7cSMaen Suleiman struct mvsd_host { 38236caa7cSMaen Suleiman void __iomem *base; 39236caa7cSMaen Suleiman struct mmc_request *mrq; 40236caa7cSMaen Suleiman spinlock_t lock; 41236caa7cSMaen Suleiman unsigned int xfer_mode; 42236caa7cSMaen Suleiman unsigned int intr_en; 43236caa7cSMaen Suleiman unsigned int ctrl; 44236caa7cSMaen Suleiman unsigned int pio_size; 45236caa7cSMaen Suleiman void *pio_ptr; 46236caa7cSMaen Suleiman unsigned int sg_frags; 47236caa7cSMaen Suleiman unsigned int ns_per_clk; 48236caa7cSMaen Suleiman unsigned int clock; 49236caa7cSMaen Suleiman unsigned int base_clock; 50236caa7cSMaen Suleiman struct timer_list timer; 51236caa7cSMaen Suleiman struct mmc_host *mmc; 52236caa7cSMaen Suleiman struct device *dev; 53236caa7cSMaen Suleiman struct resource *res; 54236caa7cSMaen Suleiman int irq; 55f4f7561eSAndrew Lunn struct clk *clk; 56236caa7cSMaen Suleiman int gpio_card_detect; 57236caa7cSMaen Suleiman int gpio_write_protect; 58236caa7cSMaen Suleiman }; 59236caa7cSMaen Suleiman 60236caa7cSMaen Suleiman #define mvsd_write(offs, val) writel(val, iobase + (offs)) 61236caa7cSMaen Suleiman #define mvsd_read(offs) readl(iobase + (offs)) 62236caa7cSMaen Suleiman 63236caa7cSMaen Suleiman static int mvsd_setup_data(struct mvsd_host *host, struct mmc_data *data) 64236caa7cSMaen Suleiman { 65236caa7cSMaen Suleiman void __iomem *iobase = host->base; 66236caa7cSMaen Suleiman unsigned int tmout; 67236caa7cSMaen Suleiman int tmout_index; 68236caa7cSMaen Suleiman 69a6d297f0SNicolas Pitre /* 70a6d297f0SNicolas Pitre * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE 71a6d297f0SNicolas Pitre * register is sometimes not set before a while when some 72a6d297f0SNicolas Pitre * "unusual" data block sizes are used (such as with the SWITCH 73a6d297f0SNicolas Pitre * command), even despite the fact that the XFER_DONE interrupt 74a6d297f0SNicolas Pitre * was raised. And if another data transfer starts before 75a6d297f0SNicolas Pitre * this bit comes to good sense (which eventually happens by 76a6d297f0SNicolas Pitre * itself) then the new transfer simply fails with a timeout. 77a6d297f0SNicolas Pitre */ 78a6d297f0SNicolas Pitre if (!(mvsd_read(MVSD_HW_STATE) & (1 << 13))) { 79a6d297f0SNicolas Pitre unsigned long t = jiffies + HZ; 80a6d297f0SNicolas Pitre unsigned int hw_state, count = 0; 81a6d297f0SNicolas Pitre do { 82a6d297f0SNicolas Pitre if (time_after(jiffies, t)) { 83a6d297f0SNicolas Pitre dev_warn(host->dev, "FIFO_EMPTY bit missing\n"); 84a6d297f0SNicolas Pitre break; 85a6d297f0SNicolas Pitre } 86a6d297f0SNicolas Pitre hw_state = mvsd_read(MVSD_HW_STATE); 87a6d297f0SNicolas Pitre count++; 88a6d297f0SNicolas Pitre } while (!(hw_state & (1 << 13))); 89a6d297f0SNicolas Pitre dev_dbg(host->dev, "*** wait for FIFO_EMPTY bit " 90a6d297f0SNicolas Pitre "(hw=0x%04x, count=%d, jiffies=%ld)\n", 91a6d297f0SNicolas Pitre hw_state, count, jiffies - (t - HZ)); 92a6d297f0SNicolas Pitre } 93a6d297f0SNicolas Pitre 94236caa7cSMaen Suleiman /* If timeout=0 then maximum timeout index is used. */ 95236caa7cSMaen Suleiman tmout = DIV_ROUND_UP(data->timeout_ns, host->ns_per_clk); 96236caa7cSMaen Suleiman tmout += data->timeout_clks; 97236caa7cSMaen Suleiman tmout_index = fls(tmout - 1) - 12; 98236caa7cSMaen Suleiman if (tmout_index < 0) 99236caa7cSMaen Suleiman tmout_index = 0; 100236caa7cSMaen Suleiman if (tmout_index > MVSD_HOST_CTRL_TMOUT_MAX) 101236caa7cSMaen Suleiman tmout_index = MVSD_HOST_CTRL_TMOUT_MAX; 102236caa7cSMaen Suleiman 103236caa7cSMaen Suleiman dev_dbg(host->dev, "data %s at 0x%08x: blocks=%d blksz=%d tmout=%u (%d)\n", 104236caa7cSMaen Suleiman (data->flags & MMC_DATA_READ) ? "read" : "write", 105236caa7cSMaen Suleiman (u32)sg_virt(data->sg), data->blocks, data->blksz, 106236caa7cSMaen Suleiman tmout, tmout_index); 107236caa7cSMaen Suleiman 108236caa7cSMaen Suleiman host->ctrl &= ~MVSD_HOST_CTRL_TMOUT_MASK; 109236caa7cSMaen Suleiman host->ctrl |= MVSD_HOST_CTRL_TMOUT(tmout_index); 110236caa7cSMaen Suleiman mvsd_write(MVSD_HOST_CTRL, host->ctrl); 111236caa7cSMaen Suleiman mvsd_write(MVSD_BLK_COUNT, data->blocks); 112236caa7cSMaen Suleiman mvsd_write(MVSD_BLK_SIZE, data->blksz); 113236caa7cSMaen Suleiman 114236caa7cSMaen Suleiman if (nodma || (data->blksz | data->sg->offset) & 3) { 115236caa7cSMaen Suleiman /* 116236caa7cSMaen Suleiman * We cannot do DMA on a buffer which offset or size 117236caa7cSMaen Suleiman * is not aligned on a 4-byte boundary. 118236caa7cSMaen Suleiman */ 119236caa7cSMaen Suleiman host->pio_size = data->blocks * data->blksz; 120236caa7cSMaen Suleiman host->pio_ptr = sg_virt(data->sg); 121236caa7cSMaen Suleiman if (!nodma) 122a3c76eb9SGirish K S pr_debug("%s: fallback to PIO for data " 123236caa7cSMaen Suleiman "at 0x%p size %d\n", 124236caa7cSMaen Suleiman mmc_hostname(host->mmc), 125236caa7cSMaen Suleiman host->pio_ptr, host->pio_size); 126236caa7cSMaen Suleiman return 1; 127236caa7cSMaen Suleiman } else { 128236caa7cSMaen Suleiman dma_addr_t phys_addr; 129236caa7cSMaen Suleiman int dma_dir = (data->flags & MMC_DATA_READ) ? 130236caa7cSMaen Suleiman DMA_FROM_DEVICE : DMA_TO_DEVICE; 131236caa7cSMaen Suleiman host->sg_frags = dma_map_sg(mmc_dev(host->mmc), data->sg, 132236caa7cSMaen Suleiman data->sg_len, dma_dir); 133236caa7cSMaen Suleiman phys_addr = sg_dma_address(data->sg); 134236caa7cSMaen Suleiman mvsd_write(MVSD_SYS_ADDR_LOW, (u32)phys_addr & 0xffff); 135236caa7cSMaen Suleiman mvsd_write(MVSD_SYS_ADDR_HI, (u32)phys_addr >> 16); 136236caa7cSMaen Suleiman return 0; 137236caa7cSMaen Suleiman } 138236caa7cSMaen Suleiman } 139236caa7cSMaen Suleiman 140236caa7cSMaen Suleiman static void mvsd_request(struct mmc_host *mmc, struct mmc_request *mrq) 141236caa7cSMaen Suleiman { 142236caa7cSMaen Suleiman struct mvsd_host *host = mmc_priv(mmc); 143236caa7cSMaen Suleiman void __iomem *iobase = host->base; 144236caa7cSMaen Suleiman struct mmc_command *cmd = mrq->cmd; 145236caa7cSMaen Suleiman u32 cmdreg = 0, xfer = 0, intr = 0; 146236caa7cSMaen Suleiman unsigned long flags; 147236caa7cSMaen Suleiman 148236caa7cSMaen Suleiman BUG_ON(host->mrq != NULL); 149236caa7cSMaen Suleiman host->mrq = mrq; 150236caa7cSMaen Suleiman 151236caa7cSMaen Suleiman dev_dbg(host->dev, "cmd %d (hw state 0x%04x)\n", 152236caa7cSMaen Suleiman cmd->opcode, mvsd_read(MVSD_HW_STATE)); 153236caa7cSMaen Suleiman 154236caa7cSMaen Suleiman cmdreg = MVSD_CMD_INDEX(cmd->opcode); 155236caa7cSMaen Suleiman 156236caa7cSMaen Suleiman if (cmd->flags & MMC_RSP_BUSY) 157236caa7cSMaen Suleiman cmdreg |= MVSD_CMD_RSP_48BUSY; 158236caa7cSMaen Suleiman else if (cmd->flags & MMC_RSP_136) 159236caa7cSMaen Suleiman cmdreg |= MVSD_CMD_RSP_136; 160236caa7cSMaen Suleiman else if (cmd->flags & MMC_RSP_PRESENT) 161236caa7cSMaen Suleiman cmdreg |= MVSD_CMD_RSP_48; 162236caa7cSMaen Suleiman else 163236caa7cSMaen Suleiman cmdreg |= MVSD_CMD_RSP_NONE; 164236caa7cSMaen Suleiman 165236caa7cSMaen Suleiman if (cmd->flags & MMC_RSP_CRC) 166236caa7cSMaen Suleiman cmdreg |= MVSD_CMD_CHECK_CMDCRC; 167236caa7cSMaen Suleiman 168236caa7cSMaen Suleiman if (cmd->flags & MMC_RSP_OPCODE) 169236caa7cSMaen Suleiman cmdreg |= MVSD_CMD_INDX_CHECK; 170236caa7cSMaen Suleiman 171236caa7cSMaen Suleiman if (cmd->flags & MMC_RSP_PRESENT) { 172236caa7cSMaen Suleiman cmdreg |= MVSD_UNEXPECTED_RESP; 173236caa7cSMaen Suleiman intr |= MVSD_NOR_UNEXP_RSP; 174236caa7cSMaen Suleiman } 175236caa7cSMaen Suleiman 176236caa7cSMaen Suleiman if (mrq->data) { 177236caa7cSMaen Suleiman struct mmc_data *data = mrq->data; 178236caa7cSMaen Suleiman int pio; 179236caa7cSMaen Suleiman 180236caa7cSMaen Suleiman cmdreg |= MVSD_CMD_DATA_PRESENT | MVSD_CMD_CHECK_DATACRC16; 181236caa7cSMaen Suleiman xfer |= MVSD_XFER_MODE_HW_WR_DATA_EN; 182236caa7cSMaen Suleiman if (data->flags & MMC_DATA_READ) 183236caa7cSMaen Suleiman xfer |= MVSD_XFER_MODE_TO_HOST; 184236caa7cSMaen Suleiman 185236caa7cSMaen Suleiman pio = mvsd_setup_data(host, data); 186236caa7cSMaen Suleiman if (pio) { 187236caa7cSMaen Suleiman xfer |= MVSD_XFER_MODE_PIO; 188236caa7cSMaen Suleiman /* PIO section of mvsd_irq has comments on those bits */ 189236caa7cSMaen Suleiman if (data->flags & MMC_DATA_WRITE) 190236caa7cSMaen Suleiman intr |= MVSD_NOR_TX_AVAIL; 191236caa7cSMaen Suleiman else if (host->pio_size > 32) 192236caa7cSMaen Suleiman intr |= MVSD_NOR_RX_FIFO_8W; 193236caa7cSMaen Suleiman else 194236caa7cSMaen Suleiman intr |= MVSD_NOR_RX_READY; 195236caa7cSMaen Suleiman } 196236caa7cSMaen Suleiman 197236caa7cSMaen Suleiman if (data->stop) { 198236caa7cSMaen Suleiman struct mmc_command *stop = data->stop; 199236caa7cSMaen Suleiman u32 cmd12reg = 0; 200236caa7cSMaen Suleiman 201236caa7cSMaen Suleiman mvsd_write(MVSD_AUTOCMD12_ARG_LOW, stop->arg & 0xffff); 202236caa7cSMaen Suleiman mvsd_write(MVSD_AUTOCMD12_ARG_HI, stop->arg >> 16); 203236caa7cSMaen Suleiman 204236caa7cSMaen Suleiman if (stop->flags & MMC_RSP_BUSY) 205236caa7cSMaen Suleiman cmd12reg |= MVSD_AUTOCMD12_BUSY; 206236caa7cSMaen Suleiman if (stop->flags & MMC_RSP_OPCODE) 207236caa7cSMaen Suleiman cmd12reg |= MVSD_AUTOCMD12_INDX_CHECK; 208236caa7cSMaen Suleiman cmd12reg |= MVSD_AUTOCMD12_INDEX(stop->opcode); 209236caa7cSMaen Suleiman mvsd_write(MVSD_AUTOCMD12_CMD, cmd12reg); 210236caa7cSMaen Suleiman 211236caa7cSMaen Suleiman xfer |= MVSD_XFER_MODE_AUTO_CMD12; 212236caa7cSMaen Suleiman intr |= MVSD_NOR_AUTOCMD12_DONE; 213236caa7cSMaen Suleiman } else { 214236caa7cSMaen Suleiman intr |= MVSD_NOR_XFER_DONE; 215236caa7cSMaen Suleiman } 216236caa7cSMaen Suleiman } else { 217236caa7cSMaen Suleiman intr |= MVSD_NOR_CMD_DONE; 218236caa7cSMaen Suleiman } 219236caa7cSMaen Suleiman 220236caa7cSMaen Suleiman mvsd_write(MVSD_ARG_LOW, cmd->arg & 0xffff); 221236caa7cSMaen Suleiman mvsd_write(MVSD_ARG_HI, cmd->arg >> 16); 222236caa7cSMaen Suleiman 223236caa7cSMaen Suleiman spin_lock_irqsave(&host->lock, flags); 224236caa7cSMaen Suleiman 225236caa7cSMaen Suleiman host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN; 226236caa7cSMaen Suleiman host->xfer_mode |= xfer; 227236caa7cSMaen Suleiman mvsd_write(MVSD_XFER_MODE, host->xfer_mode); 228236caa7cSMaen Suleiman 229236caa7cSMaen Suleiman mvsd_write(MVSD_NOR_INTR_STATUS, ~MVSD_NOR_CARD_INT); 230236caa7cSMaen Suleiman mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff); 231236caa7cSMaen Suleiman mvsd_write(MVSD_CMD, cmdreg); 232236caa7cSMaen Suleiman 233236caa7cSMaen Suleiman host->intr_en &= MVSD_NOR_CARD_INT; 234236caa7cSMaen Suleiman host->intr_en |= intr | MVSD_NOR_ERROR; 235236caa7cSMaen Suleiman mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); 236236caa7cSMaen Suleiman mvsd_write(MVSD_ERR_INTR_EN, 0xffff); 237236caa7cSMaen Suleiman 238236caa7cSMaen Suleiman mod_timer(&host->timer, jiffies + 5 * HZ); 239236caa7cSMaen Suleiman 240236caa7cSMaen Suleiman spin_unlock_irqrestore(&host->lock, flags); 241236caa7cSMaen Suleiman } 242236caa7cSMaen Suleiman 243236caa7cSMaen Suleiman static u32 mvsd_finish_cmd(struct mvsd_host *host, struct mmc_command *cmd, 244236caa7cSMaen Suleiman u32 err_status) 245236caa7cSMaen Suleiman { 246236caa7cSMaen Suleiman void __iomem *iobase = host->base; 247236caa7cSMaen Suleiman 248236caa7cSMaen Suleiman if (cmd->flags & MMC_RSP_136) { 249236caa7cSMaen Suleiman unsigned int response[8], i; 250236caa7cSMaen Suleiman for (i = 0; i < 8; i++) 251236caa7cSMaen Suleiman response[i] = mvsd_read(MVSD_RSP(i)); 252236caa7cSMaen Suleiman cmd->resp[0] = ((response[0] & 0x03ff) << 22) | 253236caa7cSMaen Suleiman ((response[1] & 0xffff) << 6) | 254236caa7cSMaen Suleiman ((response[2] & 0xfc00) >> 10); 255236caa7cSMaen Suleiman cmd->resp[1] = ((response[2] & 0x03ff) << 22) | 256236caa7cSMaen Suleiman ((response[3] & 0xffff) << 6) | 257236caa7cSMaen Suleiman ((response[4] & 0xfc00) >> 10); 258236caa7cSMaen Suleiman cmd->resp[2] = ((response[4] & 0x03ff) << 22) | 259236caa7cSMaen Suleiman ((response[5] & 0xffff) << 6) | 260236caa7cSMaen Suleiman ((response[6] & 0xfc00) >> 10); 261236caa7cSMaen Suleiman cmd->resp[3] = ((response[6] & 0x03ff) << 22) | 262236caa7cSMaen Suleiman ((response[7] & 0x3fff) << 8); 263236caa7cSMaen Suleiman } else if (cmd->flags & MMC_RSP_PRESENT) { 264236caa7cSMaen Suleiman unsigned int response[3], i; 265236caa7cSMaen Suleiman for (i = 0; i < 3; i++) 266236caa7cSMaen Suleiman response[i] = mvsd_read(MVSD_RSP(i)); 267236caa7cSMaen Suleiman cmd->resp[0] = ((response[2] & 0x003f) << (8 - 8)) | 268236caa7cSMaen Suleiman ((response[1] & 0xffff) << (14 - 8)) | 269236caa7cSMaen Suleiman ((response[0] & 0x03ff) << (30 - 8)); 270236caa7cSMaen Suleiman cmd->resp[1] = ((response[0] & 0xfc00) >> 10); 271236caa7cSMaen Suleiman cmd->resp[2] = 0; 272236caa7cSMaen Suleiman cmd->resp[3] = 0; 273236caa7cSMaen Suleiman } 274236caa7cSMaen Suleiman 275236caa7cSMaen Suleiman if (err_status & MVSD_ERR_CMD_TIMEOUT) { 276236caa7cSMaen Suleiman cmd->error = -ETIMEDOUT; 277236caa7cSMaen Suleiman } else if (err_status & (MVSD_ERR_CMD_CRC | MVSD_ERR_CMD_ENDBIT | 278236caa7cSMaen Suleiman MVSD_ERR_CMD_INDEX | MVSD_ERR_CMD_STARTBIT)) { 279236caa7cSMaen Suleiman cmd->error = -EILSEQ; 280236caa7cSMaen Suleiman } 281236caa7cSMaen Suleiman err_status &= ~(MVSD_ERR_CMD_TIMEOUT | MVSD_ERR_CMD_CRC | 282236caa7cSMaen Suleiman MVSD_ERR_CMD_ENDBIT | MVSD_ERR_CMD_INDEX | 283236caa7cSMaen Suleiman MVSD_ERR_CMD_STARTBIT); 284236caa7cSMaen Suleiman 285236caa7cSMaen Suleiman return err_status; 286236caa7cSMaen Suleiman } 287236caa7cSMaen Suleiman 288236caa7cSMaen Suleiman static u32 mvsd_finish_data(struct mvsd_host *host, struct mmc_data *data, 289236caa7cSMaen Suleiman u32 err_status) 290236caa7cSMaen Suleiman { 291236caa7cSMaen Suleiman void __iomem *iobase = host->base; 292236caa7cSMaen Suleiman 293236caa7cSMaen Suleiman if (host->pio_ptr) { 294236caa7cSMaen Suleiman host->pio_ptr = NULL; 295236caa7cSMaen Suleiman host->pio_size = 0; 296236caa7cSMaen Suleiman } else { 297236caa7cSMaen Suleiman dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_frags, 298236caa7cSMaen Suleiman (data->flags & MMC_DATA_READ) ? 299236caa7cSMaen Suleiman DMA_FROM_DEVICE : DMA_TO_DEVICE); 300236caa7cSMaen Suleiman } 301236caa7cSMaen Suleiman 302236caa7cSMaen Suleiman if (err_status & MVSD_ERR_DATA_TIMEOUT) 303236caa7cSMaen Suleiman data->error = -ETIMEDOUT; 304236caa7cSMaen Suleiman else if (err_status & (MVSD_ERR_DATA_CRC | MVSD_ERR_DATA_ENDBIT)) 305236caa7cSMaen Suleiman data->error = -EILSEQ; 306236caa7cSMaen Suleiman else if (err_status & MVSD_ERR_XFER_SIZE) 307236caa7cSMaen Suleiman data->error = -EBADE; 308236caa7cSMaen Suleiman err_status &= ~(MVSD_ERR_DATA_TIMEOUT | MVSD_ERR_DATA_CRC | 309236caa7cSMaen Suleiman MVSD_ERR_DATA_ENDBIT | MVSD_ERR_XFER_SIZE); 310236caa7cSMaen Suleiman 311236caa7cSMaen Suleiman dev_dbg(host->dev, "data done: blocks_left=%d, bytes_left=%d\n", 312236caa7cSMaen Suleiman mvsd_read(MVSD_CURR_BLK_LEFT), mvsd_read(MVSD_CURR_BYTE_LEFT)); 313236caa7cSMaen Suleiman data->bytes_xfered = 314236caa7cSMaen Suleiman (data->blocks - mvsd_read(MVSD_CURR_BLK_LEFT)) * data->blksz; 315236caa7cSMaen Suleiman /* We can't be sure about the last block when errors are detected */ 316236caa7cSMaen Suleiman if (data->bytes_xfered && data->error) 317236caa7cSMaen Suleiman data->bytes_xfered -= data->blksz; 318236caa7cSMaen Suleiman 319236caa7cSMaen Suleiman /* Handle Auto cmd 12 response */ 320236caa7cSMaen Suleiman if (data->stop) { 321236caa7cSMaen Suleiman unsigned int response[3], i; 322236caa7cSMaen Suleiman for (i = 0; i < 3; i++) 323236caa7cSMaen Suleiman response[i] = mvsd_read(MVSD_AUTO_RSP(i)); 324236caa7cSMaen Suleiman data->stop->resp[0] = ((response[2] & 0x003f) << (8 - 8)) | 325236caa7cSMaen Suleiman ((response[1] & 0xffff) << (14 - 8)) | 326236caa7cSMaen Suleiman ((response[0] & 0x03ff) << (30 - 8)); 327236caa7cSMaen Suleiman data->stop->resp[1] = ((response[0] & 0xfc00) >> 10); 328236caa7cSMaen Suleiman data->stop->resp[2] = 0; 329236caa7cSMaen Suleiman data->stop->resp[3] = 0; 330236caa7cSMaen Suleiman 331236caa7cSMaen Suleiman if (err_status & MVSD_ERR_AUTOCMD12) { 332236caa7cSMaen Suleiman u32 err_cmd12 = mvsd_read(MVSD_AUTOCMD12_ERR_STATUS); 333236caa7cSMaen Suleiman dev_dbg(host->dev, "c12err 0x%04x\n", err_cmd12); 334236caa7cSMaen Suleiman if (err_cmd12 & MVSD_AUTOCMD12_ERR_NOTEXE) 335236caa7cSMaen Suleiman data->stop->error = -ENOEXEC; 336236caa7cSMaen Suleiman else if (err_cmd12 & MVSD_AUTOCMD12_ERR_TIMEOUT) 337236caa7cSMaen Suleiman data->stop->error = -ETIMEDOUT; 338236caa7cSMaen Suleiman else if (err_cmd12) 339236caa7cSMaen Suleiman data->stop->error = -EILSEQ; 340236caa7cSMaen Suleiman err_status &= ~MVSD_ERR_AUTOCMD12; 341236caa7cSMaen Suleiman } 342236caa7cSMaen Suleiman } 343236caa7cSMaen Suleiman 344236caa7cSMaen Suleiman return err_status; 345236caa7cSMaen Suleiman } 346236caa7cSMaen Suleiman 347236caa7cSMaen Suleiman static irqreturn_t mvsd_irq(int irq, void *dev) 348236caa7cSMaen Suleiman { 349236caa7cSMaen Suleiman struct mvsd_host *host = dev; 350236caa7cSMaen Suleiman void __iomem *iobase = host->base; 351236caa7cSMaen Suleiman u32 intr_status, intr_done_mask; 352236caa7cSMaen Suleiman int irq_handled = 0; 353236caa7cSMaen Suleiman 354236caa7cSMaen Suleiman intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); 355236caa7cSMaen Suleiman dev_dbg(host->dev, "intr 0x%04x intr_en 0x%04x hw_state 0x%04x\n", 356236caa7cSMaen Suleiman intr_status, mvsd_read(MVSD_NOR_INTR_EN), 357236caa7cSMaen Suleiman mvsd_read(MVSD_HW_STATE)); 358236caa7cSMaen Suleiman 359236caa7cSMaen Suleiman spin_lock(&host->lock); 360236caa7cSMaen Suleiman 361236caa7cSMaen Suleiman /* PIO handling, if needed. Messy business... */ 362236caa7cSMaen Suleiman if (host->pio_size && 363236caa7cSMaen Suleiman (intr_status & host->intr_en & 364236caa7cSMaen Suleiman (MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W))) { 365236caa7cSMaen Suleiman u16 *p = host->pio_ptr; 366236caa7cSMaen Suleiman int s = host->pio_size; 367236caa7cSMaen Suleiman while (s >= 32 && (intr_status & MVSD_NOR_RX_FIFO_8W)) { 368236caa7cSMaen Suleiman readsw(iobase + MVSD_FIFO, p, 16); 369236caa7cSMaen Suleiman p += 16; 370236caa7cSMaen Suleiman s -= 32; 371236caa7cSMaen Suleiman intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); 372236caa7cSMaen Suleiman } 373236caa7cSMaen Suleiman /* 374236caa7cSMaen Suleiman * Normally we'd use < 32 here, but the RX_FIFO_8W bit 375236caa7cSMaen Suleiman * doesn't appear to assert when there is exactly 32 bytes 376236caa7cSMaen Suleiman * (8 words) left to fetch in a transfer. 377236caa7cSMaen Suleiman */ 378236caa7cSMaen Suleiman if (s <= 32) { 379236caa7cSMaen Suleiman while (s >= 4 && (intr_status & MVSD_NOR_RX_READY)) { 380236caa7cSMaen Suleiman put_unaligned(mvsd_read(MVSD_FIFO), p++); 381236caa7cSMaen Suleiman put_unaligned(mvsd_read(MVSD_FIFO), p++); 382236caa7cSMaen Suleiman s -= 4; 383236caa7cSMaen Suleiman intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); 384236caa7cSMaen Suleiman } 385236caa7cSMaen Suleiman if (s && s < 4 && (intr_status & MVSD_NOR_RX_READY)) { 386236caa7cSMaen Suleiman u16 val[2] = {0, 0}; 387236caa7cSMaen Suleiman val[0] = mvsd_read(MVSD_FIFO); 388236caa7cSMaen Suleiman val[1] = mvsd_read(MVSD_FIFO); 3896cdbf734SNicolas Pitre memcpy(p, ((void *)&val) + 4 - s, s); 390236caa7cSMaen Suleiman s = 0; 391236caa7cSMaen Suleiman intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); 392236caa7cSMaen Suleiman } 393236caa7cSMaen Suleiman if (s == 0) { 394236caa7cSMaen Suleiman host->intr_en &= 395236caa7cSMaen Suleiman ~(MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W); 396236caa7cSMaen Suleiman mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); 397236caa7cSMaen Suleiman } else if (host->intr_en & MVSD_NOR_RX_FIFO_8W) { 398236caa7cSMaen Suleiman host->intr_en &= ~MVSD_NOR_RX_FIFO_8W; 399236caa7cSMaen Suleiman host->intr_en |= MVSD_NOR_RX_READY; 400236caa7cSMaen Suleiman mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); 401236caa7cSMaen Suleiman } 402236caa7cSMaen Suleiman } 403236caa7cSMaen Suleiman dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n", 404236caa7cSMaen Suleiman s, intr_status, mvsd_read(MVSD_HW_STATE)); 405236caa7cSMaen Suleiman host->pio_ptr = p; 406236caa7cSMaen Suleiman host->pio_size = s; 407236caa7cSMaen Suleiman irq_handled = 1; 408236caa7cSMaen Suleiman } else if (host->pio_size && 409236caa7cSMaen Suleiman (intr_status & host->intr_en & 410236caa7cSMaen Suleiman (MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W))) { 411236caa7cSMaen Suleiman u16 *p = host->pio_ptr; 412236caa7cSMaen Suleiman int s = host->pio_size; 413236caa7cSMaen Suleiman /* 414236caa7cSMaen Suleiman * The TX_FIFO_8W bit is unreliable. When set, bursting 415236caa7cSMaen Suleiman * 16 halfwords all at once in the FIFO drops data. Actually 416236caa7cSMaen Suleiman * TX_AVAIL does go off after only one word is pushed even if 417236caa7cSMaen Suleiman * TX_FIFO_8W remains set. 418236caa7cSMaen Suleiman */ 419236caa7cSMaen Suleiman while (s >= 4 && (intr_status & MVSD_NOR_TX_AVAIL)) { 420236caa7cSMaen Suleiman mvsd_write(MVSD_FIFO, get_unaligned(p++)); 421236caa7cSMaen Suleiman mvsd_write(MVSD_FIFO, get_unaligned(p++)); 422236caa7cSMaen Suleiman s -= 4; 423236caa7cSMaen Suleiman intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); 424236caa7cSMaen Suleiman } 425236caa7cSMaen Suleiman if (s < 4) { 426236caa7cSMaen Suleiman if (s && (intr_status & MVSD_NOR_TX_AVAIL)) { 427236caa7cSMaen Suleiman u16 val[2] = {0, 0}; 4286cdbf734SNicolas Pitre memcpy(((void *)&val) + 4 - s, p, s); 429236caa7cSMaen Suleiman mvsd_write(MVSD_FIFO, val[0]); 430236caa7cSMaen Suleiman mvsd_write(MVSD_FIFO, val[1]); 431236caa7cSMaen Suleiman s = 0; 432236caa7cSMaen Suleiman intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); 433236caa7cSMaen Suleiman } 434236caa7cSMaen Suleiman if (s == 0) { 435236caa7cSMaen Suleiman host->intr_en &= 436236caa7cSMaen Suleiman ~(MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W); 437236caa7cSMaen Suleiman mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); 438236caa7cSMaen Suleiman } 439236caa7cSMaen Suleiman } 440236caa7cSMaen Suleiman dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n", 441236caa7cSMaen Suleiman s, intr_status, mvsd_read(MVSD_HW_STATE)); 442236caa7cSMaen Suleiman host->pio_ptr = p; 443236caa7cSMaen Suleiman host->pio_size = s; 444236caa7cSMaen Suleiman irq_handled = 1; 445236caa7cSMaen Suleiman } 446236caa7cSMaen Suleiman 447236caa7cSMaen Suleiman mvsd_write(MVSD_NOR_INTR_STATUS, intr_status); 448236caa7cSMaen Suleiman 449236caa7cSMaen Suleiman intr_done_mask = MVSD_NOR_CARD_INT | MVSD_NOR_RX_READY | 450236caa7cSMaen Suleiman MVSD_NOR_RX_FIFO_8W | MVSD_NOR_TX_FIFO_8W; 451236caa7cSMaen Suleiman if (intr_status & host->intr_en & ~intr_done_mask) { 452236caa7cSMaen Suleiman struct mmc_request *mrq = host->mrq; 453236caa7cSMaen Suleiman struct mmc_command *cmd = mrq->cmd; 454236caa7cSMaen Suleiman u32 err_status = 0; 455236caa7cSMaen Suleiman 456236caa7cSMaen Suleiman del_timer(&host->timer); 457236caa7cSMaen Suleiman host->mrq = NULL; 458236caa7cSMaen Suleiman 459236caa7cSMaen Suleiman host->intr_en &= MVSD_NOR_CARD_INT; 460236caa7cSMaen Suleiman mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); 461236caa7cSMaen Suleiman mvsd_write(MVSD_ERR_INTR_EN, 0); 462236caa7cSMaen Suleiman 463236caa7cSMaen Suleiman spin_unlock(&host->lock); 464236caa7cSMaen Suleiman 465236caa7cSMaen Suleiman if (intr_status & MVSD_NOR_UNEXP_RSP) { 466236caa7cSMaen Suleiman cmd->error = -EPROTO; 467236caa7cSMaen Suleiman } else if (intr_status & MVSD_NOR_ERROR) { 468236caa7cSMaen Suleiman err_status = mvsd_read(MVSD_ERR_INTR_STATUS); 469236caa7cSMaen Suleiman dev_dbg(host->dev, "err 0x%04x\n", err_status); 470236caa7cSMaen Suleiman } 471236caa7cSMaen Suleiman 472236caa7cSMaen Suleiman err_status = mvsd_finish_cmd(host, cmd, err_status); 473236caa7cSMaen Suleiman if (mrq->data) 474236caa7cSMaen Suleiman err_status = mvsd_finish_data(host, mrq->data, err_status); 475236caa7cSMaen Suleiman if (err_status) { 476a3c76eb9SGirish K S pr_err("%s: unhandled error status %#04x\n", 477236caa7cSMaen Suleiman mmc_hostname(host->mmc), err_status); 478236caa7cSMaen Suleiman cmd->error = -ENOMSG; 479236caa7cSMaen Suleiman } 480236caa7cSMaen Suleiman 481236caa7cSMaen Suleiman mmc_request_done(host->mmc, mrq); 482236caa7cSMaen Suleiman irq_handled = 1; 483236caa7cSMaen Suleiman } else 484236caa7cSMaen Suleiman spin_unlock(&host->lock); 485236caa7cSMaen Suleiman 486236caa7cSMaen Suleiman if (intr_status & MVSD_NOR_CARD_INT) { 487236caa7cSMaen Suleiman mmc_signal_sdio_irq(host->mmc); 488236caa7cSMaen Suleiman irq_handled = 1; 489236caa7cSMaen Suleiman } 490236caa7cSMaen Suleiman 491236caa7cSMaen Suleiman if (irq_handled) 492236caa7cSMaen Suleiman return IRQ_HANDLED; 493236caa7cSMaen Suleiman 494a3c76eb9SGirish K S pr_err("%s: unhandled interrupt status=0x%04x en=0x%04x " 495236caa7cSMaen Suleiman "pio=%d\n", mmc_hostname(host->mmc), intr_status, 496236caa7cSMaen Suleiman host->intr_en, host->pio_size); 497236caa7cSMaen Suleiman return IRQ_NONE; 498236caa7cSMaen Suleiman } 499236caa7cSMaen Suleiman 500236caa7cSMaen Suleiman static void mvsd_timeout_timer(unsigned long data) 501236caa7cSMaen Suleiman { 502236caa7cSMaen Suleiman struct mvsd_host *host = (struct mvsd_host *)data; 503236caa7cSMaen Suleiman void __iomem *iobase = host->base; 504236caa7cSMaen Suleiman struct mmc_request *mrq; 505236caa7cSMaen Suleiman unsigned long flags; 506236caa7cSMaen Suleiman 507236caa7cSMaen Suleiman spin_lock_irqsave(&host->lock, flags); 508236caa7cSMaen Suleiman mrq = host->mrq; 509236caa7cSMaen Suleiman if (mrq) { 510a3c76eb9SGirish K S pr_err("%s: Timeout waiting for hardware interrupt.\n", 511236caa7cSMaen Suleiman mmc_hostname(host->mmc)); 512a3c76eb9SGirish K S pr_err("%s: hw_state=0x%04x, intr_status=0x%04x " 513236caa7cSMaen Suleiman "intr_en=0x%04x\n", mmc_hostname(host->mmc), 514236caa7cSMaen Suleiman mvsd_read(MVSD_HW_STATE), 515236caa7cSMaen Suleiman mvsd_read(MVSD_NOR_INTR_STATUS), 516236caa7cSMaen Suleiman mvsd_read(MVSD_NOR_INTR_EN)); 517236caa7cSMaen Suleiman 518236caa7cSMaen Suleiman host->mrq = NULL; 519236caa7cSMaen Suleiman 520236caa7cSMaen Suleiman mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW); 521236caa7cSMaen Suleiman 522236caa7cSMaen Suleiman host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN; 523236caa7cSMaen Suleiman mvsd_write(MVSD_XFER_MODE, host->xfer_mode); 524236caa7cSMaen Suleiman 525236caa7cSMaen Suleiman host->intr_en &= MVSD_NOR_CARD_INT; 526236caa7cSMaen Suleiman mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); 527236caa7cSMaen Suleiman mvsd_write(MVSD_ERR_INTR_EN, 0); 528236caa7cSMaen Suleiman mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff); 529236caa7cSMaen Suleiman 530236caa7cSMaen Suleiman mrq->cmd->error = -ETIMEDOUT; 531236caa7cSMaen Suleiman mvsd_finish_cmd(host, mrq->cmd, 0); 532236caa7cSMaen Suleiman if (mrq->data) { 533236caa7cSMaen Suleiman mrq->data->error = -ETIMEDOUT; 534236caa7cSMaen Suleiman mvsd_finish_data(host, mrq->data, 0); 535236caa7cSMaen Suleiman } 536236caa7cSMaen Suleiman } 537236caa7cSMaen Suleiman spin_unlock_irqrestore(&host->lock, flags); 538236caa7cSMaen Suleiman 539236caa7cSMaen Suleiman if (mrq) 540236caa7cSMaen Suleiman mmc_request_done(host->mmc, mrq); 541236caa7cSMaen Suleiman } 542236caa7cSMaen Suleiman 543236caa7cSMaen Suleiman static irqreturn_t mvsd_card_detect_irq(int irq, void *dev) 544236caa7cSMaen Suleiman { 545236caa7cSMaen Suleiman struct mvsd_host *host = dev; 546236caa7cSMaen Suleiman mmc_detect_change(host->mmc, msecs_to_jiffies(100)); 547236caa7cSMaen Suleiman return IRQ_HANDLED; 548236caa7cSMaen Suleiman } 549236caa7cSMaen Suleiman 550236caa7cSMaen Suleiman static void mvsd_enable_sdio_irq(struct mmc_host *mmc, int enable) 551236caa7cSMaen Suleiman { 552236caa7cSMaen Suleiman struct mvsd_host *host = mmc_priv(mmc); 553236caa7cSMaen Suleiman void __iomem *iobase = host->base; 554236caa7cSMaen Suleiman unsigned long flags; 555236caa7cSMaen Suleiman 556236caa7cSMaen Suleiman spin_lock_irqsave(&host->lock, flags); 557236caa7cSMaen Suleiman if (enable) { 558236caa7cSMaen Suleiman host->xfer_mode |= MVSD_XFER_MODE_INT_CHK_EN; 559236caa7cSMaen Suleiman host->intr_en |= MVSD_NOR_CARD_INT; 560236caa7cSMaen Suleiman } else { 561236caa7cSMaen Suleiman host->xfer_mode &= ~MVSD_XFER_MODE_INT_CHK_EN; 562236caa7cSMaen Suleiman host->intr_en &= ~MVSD_NOR_CARD_INT; 563236caa7cSMaen Suleiman } 564236caa7cSMaen Suleiman mvsd_write(MVSD_XFER_MODE, host->xfer_mode); 565236caa7cSMaen Suleiman mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); 566236caa7cSMaen Suleiman spin_unlock_irqrestore(&host->lock, flags); 567236caa7cSMaen Suleiman } 568236caa7cSMaen Suleiman 569236caa7cSMaen Suleiman static int mvsd_get_ro(struct mmc_host *mmc) 570236caa7cSMaen Suleiman { 571236caa7cSMaen Suleiman struct mvsd_host *host = mmc_priv(mmc); 572236caa7cSMaen Suleiman 573236caa7cSMaen Suleiman if (host->gpio_write_protect) 574236caa7cSMaen Suleiman return gpio_get_value(host->gpio_write_protect); 575236caa7cSMaen Suleiman 576236caa7cSMaen Suleiman /* 577236caa7cSMaen Suleiman * Board doesn't support read only detection; let the mmc core 578236caa7cSMaen Suleiman * decide what to do. 579236caa7cSMaen Suleiman */ 580236caa7cSMaen Suleiman return -ENOSYS; 581236caa7cSMaen Suleiman } 582236caa7cSMaen Suleiman 583236caa7cSMaen Suleiman static void mvsd_power_up(struct mvsd_host *host) 584236caa7cSMaen Suleiman { 585236caa7cSMaen Suleiman void __iomem *iobase = host->base; 586236caa7cSMaen Suleiman dev_dbg(host->dev, "power up\n"); 587236caa7cSMaen Suleiman mvsd_write(MVSD_NOR_INTR_EN, 0); 588236caa7cSMaen Suleiman mvsd_write(MVSD_ERR_INTR_EN, 0); 589236caa7cSMaen Suleiman mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW); 590236caa7cSMaen Suleiman mvsd_write(MVSD_XFER_MODE, 0); 591236caa7cSMaen Suleiman mvsd_write(MVSD_NOR_STATUS_EN, 0xffff); 592236caa7cSMaen Suleiman mvsd_write(MVSD_ERR_STATUS_EN, 0xffff); 593236caa7cSMaen Suleiman mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff); 594236caa7cSMaen Suleiman mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff); 595236caa7cSMaen Suleiman } 596236caa7cSMaen Suleiman 597236caa7cSMaen Suleiman static void mvsd_power_down(struct mvsd_host *host) 598236caa7cSMaen Suleiman { 599236caa7cSMaen Suleiman void __iomem *iobase = host->base; 600236caa7cSMaen Suleiman dev_dbg(host->dev, "power down\n"); 601236caa7cSMaen Suleiman mvsd_write(MVSD_NOR_INTR_EN, 0); 602236caa7cSMaen Suleiman mvsd_write(MVSD_ERR_INTR_EN, 0); 603236caa7cSMaen Suleiman mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW); 604236caa7cSMaen Suleiman mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK); 605236caa7cSMaen Suleiman mvsd_write(MVSD_NOR_STATUS_EN, 0); 606236caa7cSMaen Suleiman mvsd_write(MVSD_ERR_STATUS_EN, 0); 607236caa7cSMaen Suleiman mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff); 608236caa7cSMaen Suleiman mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff); 609236caa7cSMaen Suleiman } 610236caa7cSMaen Suleiman 611236caa7cSMaen Suleiman static void mvsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 612236caa7cSMaen Suleiman { 613236caa7cSMaen Suleiman struct mvsd_host *host = mmc_priv(mmc); 614236caa7cSMaen Suleiman void __iomem *iobase = host->base; 615236caa7cSMaen Suleiman u32 ctrl_reg = 0; 616236caa7cSMaen Suleiman 617236caa7cSMaen Suleiman if (ios->power_mode == MMC_POWER_UP) 618236caa7cSMaen Suleiman mvsd_power_up(host); 619236caa7cSMaen Suleiman 620236caa7cSMaen Suleiman if (ios->clock == 0) { 621236caa7cSMaen Suleiman mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK); 622236caa7cSMaen Suleiman mvsd_write(MVSD_CLK_DIV, MVSD_BASE_DIV_MAX); 623236caa7cSMaen Suleiman host->clock = 0; 624236caa7cSMaen Suleiman dev_dbg(host->dev, "clock off\n"); 625236caa7cSMaen Suleiman } else if (ios->clock != host->clock) { 626236caa7cSMaen Suleiman u32 m = DIV_ROUND_UP(host->base_clock, ios->clock) - 1; 627236caa7cSMaen Suleiman if (m > MVSD_BASE_DIV_MAX) 628236caa7cSMaen Suleiman m = MVSD_BASE_DIV_MAX; 629236caa7cSMaen Suleiman mvsd_write(MVSD_CLK_DIV, m); 630236caa7cSMaen Suleiman host->clock = ios->clock; 631236caa7cSMaen Suleiman host->ns_per_clk = 1000000000 / (host->base_clock / (m+1)); 632236caa7cSMaen Suleiman dev_dbg(host->dev, "clock=%d (%d), div=0x%04x\n", 633236caa7cSMaen Suleiman ios->clock, host->base_clock / (m+1), m); 634236caa7cSMaen Suleiman } 635236caa7cSMaen Suleiman 636236caa7cSMaen Suleiman /* default transfer mode */ 637236caa7cSMaen Suleiman ctrl_reg |= MVSD_HOST_CTRL_BIG_ENDIAN; 638236caa7cSMaen Suleiman ctrl_reg &= ~MVSD_HOST_CTRL_LSB_FIRST; 639236caa7cSMaen Suleiman 640236caa7cSMaen Suleiman /* default to maximum timeout */ 641236caa7cSMaen Suleiman ctrl_reg |= MVSD_HOST_CTRL_TMOUT_MASK; 642236caa7cSMaen Suleiman ctrl_reg |= MVSD_HOST_CTRL_TMOUT_EN; 643236caa7cSMaen Suleiman 644236caa7cSMaen Suleiman if (ios->bus_mode == MMC_BUSMODE_PUSHPULL) 645236caa7cSMaen Suleiman ctrl_reg |= MVSD_HOST_CTRL_PUSH_PULL_EN; 646236caa7cSMaen Suleiman 647236caa7cSMaen Suleiman if (ios->bus_width == MMC_BUS_WIDTH_4) 648236caa7cSMaen Suleiman ctrl_reg |= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS; 649236caa7cSMaen Suleiman 6509ca6944cSNicolas Pitre /* 6519ca6944cSNicolas Pitre * The HI_SPEED_EN bit is causing trouble with many (but not all) 6529ca6944cSNicolas Pitre * high speed SD, SDHC and SDIO cards. Not enabling that bit 6539ca6944cSNicolas Pitre * makes all cards work. So let's just ignore that bit for now 6549ca6944cSNicolas Pitre * and revisit this issue if problems for not enabling this bit 6559ca6944cSNicolas Pitre * are ever reported. 6569ca6944cSNicolas Pitre */ 6579ca6944cSNicolas Pitre #if 0 658236caa7cSMaen Suleiman if (ios->timing == MMC_TIMING_MMC_HS || 659236caa7cSMaen Suleiman ios->timing == MMC_TIMING_SD_HS) 660236caa7cSMaen Suleiman ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN; 6619ca6944cSNicolas Pitre #endif 662236caa7cSMaen Suleiman 663236caa7cSMaen Suleiman host->ctrl = ctrl_reg; 664236caa7cSMaen Suleiman mvsd_write(MVSD_HOST_CTRL, ctrl_reg); 665236caa7cSMaen Suleiman dev_dbg(host->dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg, 666236caa7cSMaen Suleiman (ctrl_reg & MVSD_HOST_CTRL_PUSH_PULL_EN) ? 667236caa7cSMaen Suleiman "push-pull" : "open-drain", 668236caa7cSMaen Suleiman (ctrl_reg & MVSD_HOST_CTRL_DATA_WIDTH_4_BITS) ? 669236caa7cSMaen Suleiman "4bit-width" : "1bit-width", 670236caa7cSMaen Suleiman (ctrl_reg & MVSD_HOST_CTRL_HI_SPEED_EN) ? 671236caa7cSMaen Suleiman "high-speed" : ""); 672236caa7cSMaen Suleiman 673236caa7cSMaen Suleiman if (ios->power_mode == MMC_POWER_OFF) 674236caa7cSMaen Suleiman mvsd_power_down(host); 675236caa7cSMaen Suleiman } 676236caa7cSMaen Suleiman 677236caa7cSMaen Suleiman static const struct mmc_host_ops mvsd_ops = { 678236caa7cSMaen Suleiman .request = mvsd_request, 679236caa7cSMaen Suleiman .get_ro = mvsd_get_ro, 680236caa7cSMaen Suleiman .set_ios = mvsd_set_ios, 681236caa7cSMaen Suleiman .enable_sdio_irq = mvsd_enable_sdio_irq, 682236caa7cSMaen Suleiman }; 683236caa7cSMaen Suleiman 68463a9332bSAndrew Lunn static void __init 68563a9332bSAndrew Lunn mv_conf_mbus_windows(struct mvsd_host *host, 68663a9332bSAndrew Lunn const struct mbus_dram_target_info *dram) 687236caa7cSMaen Suleiman { 688236caa7cSMaen Suleiman void __iomem *iobase = host->base; 689236caa7cSMaen Suleiman int i; 690236caa7cSMaen Suleiman 691236caa7cSMaen Suleiman for (i = 0; i < 4; i++) { 692236caa7cSMaen Suleiman writel(0, iobase + MVSD_WINDOW_CTRL(i)); 693236caa7cSMaen Suleiman writel(0, iobase + MVSD_WINDOW_BASE(i)); 694236caa7cSMaen Suleiman } 695236caa7cSMaen Suleiman 696236caa7cSMaen Suleiman for (i = 0; i < dram->num_cs; i++) { 69763a9332bSAndrew Lunn const struct mbus_dram_window *cs = dram->cs + i; 698236caa7cSMaen Suleiman writel(((cs->size - 1) & 0xffff0000) | 699236caa7cSMaen Suleiman (cs->mbus_attr << 8) | 700236caa7cSMaen Suleiman (dram->mbus_dram_target_id << 4) | 1, 701236caa7cSMaen Suleiman iobase + MVSD_WINDOW_CTRL(i)); 702236caa7cSMaen Suleiman writel(cs->base, iobase + MVSD_WINDOW_BASE(i)); 703236caa7cSMaen Suleiman } 704236caa7cSMaen Suleiman } 705236caa7cSMaen Suleiman 706236caa7cSMaen Suleiman static int __init mvsd_probe(struct platform_device *pdev) 707236caa7cSMaen Suleiman { 708236caa7cSMaen Suleiman struct mmc_host *mmc = NULL; 709236caa7cSMaen Suleiman struct mvsd_host *host = NULL; 710236caa7cSMaen Suleiman const struct mvsdio_platform_data *mvsd_data; 71163a9332bSAndrew Lunn const struct mbus_dram_target_info *dram; 712236caa7cSMaen Suleiman struct resource *r; 713236caa7cSMaen Suleiman int ret, irq; 714236caa7cSMaen Suleiman 715236caa7cSMaen Suleiman r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 716236caa7cSMaen Suleiman irq = platform_get_irq(pdev, 0); 717236caa7cSMaen Suleiman mvsd_data = pdev->dev.platform_data; 718236caa7cSMaen Suleiman if (!r || irq < 0 || !mvsd_data) 719236caa7cSMaen Suleiman return -ENXIO; 720236caa7cSMaen Suleiman 721236caa7cSMaen Suleiman r = request_mem_region(r->start, SZ_1K, DRIVER_NAME); 722236caa7cSMaen Suleiman if (!r) 723236caa7cSMaen Suleiman return -EBUSY; 724236caa7cSMaen Suleiman 725236caa7cSMaen Suleiman mmc = mmc_alloc_host(sizeof(struct mvsd_host), &pdev->dev); 726236caa7cSMaen Suleiman if (!mmc) { 727236caa7cSMaen Suleiman ret = -ENOMEM; 728236caa7cSMaen Suleiman goto out; 729236caa7cSMaen Suleiman } 730236caa7cSMaen Suleiman 731236caa7cSMaen Suleiman host = mmc_priv(mmc); 732236caa7cSMaen Suleiman host->mmc = mmc; 733236caa7cSMaen Suleiman host->dev = &pdev->dev; 734236caa7cSMaen Suleiman host->res = r; 735236caa7cSMaen Suleiman host->base_clock = mvsd_data->clock / 2; 736236caa7cSMaen Suleiman 737236caa7cSMaen Suleiman mmc->ops = &mvsd_ops; 738236caa7cSMaen Suleiman 739236caa7cSMaen Suleiman mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 740236caa7cSMaen Suleiman mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ | 741236caa7cSMaen Suleiman MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; 742236caa7cSMaen Suleiman 743236caa7cSMaen Suleiman mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX); 744236caa7cSMaen Suleiman mmc->f_max = maxfreq; 745236caa7cSMaen Suleiman 746236caa7cSMaen Suleiman mmc->max_blk_size = 2048; 747236caa7cSMaen Suleiman mmc->max_blk_count = 65535; 748236caa7cSMaen Suleiman 749a36274e0SMartin K. Petersen mmc->max_segs = 1; 750236caa7cSMaen Suleiman mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count; 751236caa7cSMaen Suleiman mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 752236caa7cSMaen Suleiman 753236caa7cSMaen Suleiman spin_lock_init(&host->lock); 754236caa7cSMaen Suleiman 755236caa7cSMaen Suleiman host->base = ioremap(r->start, SZ_4K); 756236caa7cSMaen Suleiman if (!host->base) { 757236caa7cSMaen Suleiman ret = -ENOMEM; 758236caa7cSMaen Suleiman goto out; 759236caa7cSMaen Suleiman } 760236caa7cSMaen Suleiman 761236caa7cSMaen Suleiman /* (Re-)program MBUS remapping windows if we are asked to. */ 76263a9332bSAndrew Lunn dram = mv_mbus_dram_info(); 76363a9332bSAndrew Lunn if (dram) 76463a9332bSAndrew Lunn mv_conf_mbus_windows(host, dram); 765236caa7cSMaen Suleiman 766236caa7cSMaen Suleiman mvsd_power_down(host); 767236caa7cSMaen Suleiman 768236caa7cSMaen Suleiman ret = request_irq(irq, mvsd_irq, 0, DRIVER_NAME, host); 769236caa7cSMaen Suleiman if (ret) { 770a3c76eb9SGirish K S pr_err("%s: cannot assign irq %d\n", DRIVER_NAME, irq); 771236caa7cSMaen Suleiman goto out; 772236caa7cSMaen Suleiman } else 773236caa7cSMaen Suleiman host->irq = irq; 774236caa7cSMaen Suleiman 775f4f7561eSAndrew Lunn /* Not all platforms can gate the clock, so it is not 776f4f7561eSAndrew Lunn an error if the clock does not exists. */ 777f4f7561eSAndrew Lunn host->clk = clk_get(&pdev->dev, NULL); 778f4f7561eSAndrew Lunn if (!IS_ERR(host->clk)) { 779f4f7561eSAndrew Lunn clk_prepare_enable(host->clk); 780f4f7561eSAndrew Lunn } 781f4f7561eSAndrew Lunn 782236caa7cSMaen Suleiman if (mvsd_data->gpio_card_detect) { 783236caa7cSMaen Suleiman ret = gpio_request(mvsd_data->gpio_card_detect, 784236caa7cSMaen Suleiman DRIVER_NAME " cd"); 785236caa7cSMaen Suleiman if (ret == 0) { 786236caa7cSMaen Suleiman gpio_direction_input(mvsd_data->gpio_card_detect); 787236caa7cSMaen Suleiman irq = gpio_to_irq(mvsd_data->gpio_card_detect); 788236caa7cSMaen Suleiman ret = request_irq(irq, mvsd_card_detect_irq, 789236caa7cSMaen Suleiman IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING, 790236caa7cSMaen Suleiman DRIVER_NAME " cd", host); 791236caa7cSMaen Suleiman if (ret == 0) 792236caa7cSMaen Suleiman host->gpio_card_detect = 793236caa7cSMaen Suleiman mvsd_data->gpio_card_detect; 794236caa7cSMaen Suleiman else 795236caa7cSMaen Suleiman gpio_free(mvsd_data->gpio_card_detect); 796236caa7cSMaen Suleiman } 797236caa7cSMaen Suleiman } 798236caa7cSMaen Suleiman if (!host->gpio_card_detect) 799236caa7cSMaen Suleiman mmc->caps |= MMC_CAP_NEEDS_POLL; 800236caa7cSMaen Suleiman 801236caa7cSMaen Suleiman if (mvsd_data->gpio_write_protect) { 802236caa7cSMaen Suleiman ret = gpio_request(mvsd_data->gpio_write_protect, 803236caa7cSMaen Suleiman DRIVER_NAME " wp"); 804236caa7cSMaen Suleiman if (ret == 0) { 805236caa7cSMaen Suleiman gpio_direction_input(mvsd_data->gpio_write_protect); 806236caa7cSMaen Suleiman host->gpio_write_protect = 807236caa7cSMaen Suleiman mvsd_data->gpio_write_protect; 808236caa7cSMaen Suleiman } 809236caa7cSMaen Suleiman } 810236caa7cSMaen Suleiman 811236caa7cSMaen Suleiman setup_timer(&host->timer, mvsd_timeout_timer, (unsigned long)host); 812236caa7cSMaen Suleiman platform_set_drvdata(pdev, mmc); 813236caa7cSMaen Suleiman ret = mmc_add_host(mmc); 814236caa7cSMaen Suleiman if (ret) 815236caa7cSMaen Suleiman goto out; 816236caa7cSMaen Suleiman 817a3c76eb9SGirish K S pr_notice("%s: %s driver initialized, ", 818236caa7cSMaen Suleiman mmc_hostname(mmc), DRIVER_NAME); 819236caa7cSMaen Suleiman if (host->gpio_card_detect) 820236caa7cSMaen Suleiman printk("using GPIO %d for card detection\n", 821236caa7cSMaen Suleiman host->gpio_card_detect); 822236caa7cSMaen Suleiman else 823236caa7cSMaen Suleiman printk("lacking card detect (fall back to polling)\n"); 824236caa7cSMaen Suleiman return 0; 825236caa7cSMaen Suleiman 826236caa7cSMaen Suleiman out: 827236caa7cSMaen Suleiman if (host) { 828236caa7cSMaen Suleiman if (host->irq) 829236caa7cSMaen Suleiman free_irq(host->irq, host); 830236caa7cSMaen Suleiman if (host->gpio_card_detect) { 831236caa7cSMaen Suleiman free_irq(gpio_to_irq(host->gpio_card_detect), host); 832236caa7cSMaen Suleiman gpio_free(host->gpio_card_detect); 833236caa7cSMaen Suleiman } 834236caa7cSMaen Suleiman if (host->gpio_write_protect) 835236caa7cSMaen Suleiman gpio_free(host->gpio_write_protect); 836236caa7cSMaen Suleiman if (host->base) 837236caa7cSMaen Suleiman iounmap(host->base); 838236caa7cSMaen Suleiman } 839236caa7cSMaen Suleiman if (r) 840236caa7cSMaen Suleiman release_resource(r); 841236caa7cSMaen Suleiman if (mmc) 842236caa7cSMaen Suleiman mmc_free_host(mmc); 843236caa7cSMaen Suleiman 844236caa7cSMaen Suleiman return ret; 845236caa7cSMaen Suleiman } 846236caa7cSMaen Suleiman 847236caa7cSMaen Suleiman static int __exit mvsd_remove(struct platform_device *pdev) 848236caa7cSMaen Suleiman { 849236caa7cSMaen Suleiman struct mmc_host *mmc = platform_get_drvdata(pdev); 850236caa7cSMaen Suleiman 851236caa7cSMaen Suleiman if (mmc) { 852236caa7cSMaen Suleiman struct mvsd_host *host = mmc_priv(mmc); 853236caa7cSMaen Suleiman 854236caa7cSMaen Suleiman if (host->gpio_card_detect) { 855236caa7cSMaen Suleiman free_irq(gpio_to_irq(host->gpio_card_detect), host); 856236caa7cSMaen Suleiman gpio_free(host->gpio_card_detect); 857236caa7cSMaen Suleiman } 858236caa7cSMaen Suleiman mmc_remove_host(mmc); 859236caa7cSMaen Suleiman free_irq(host->irq, host); 860236caa7cSMaen Suleiman if (host->gpio_write_protect) 861236caa7cSMaen Suleiman gpio_free(host->gpio_write_protect); 862236caa7cSMaen Suleiman del_timer_sync(&host->timer); 863236caa7cSMaen Suleiman mvsd_power_down(host); 864236caa7cSMaen Suleiman iounmap(host->base); 865236caa7cSMaen Suleiman release_resource(host->res); 866f4f7561eSAndrew Lunn 867f4f7561eSAndrew Lunn if (!IS_ERR(host->clk)) { 868f4f7561eSAndrew Lunn clk_disable_unprepare(host->clk); 869f4f7561eSAndrew Lunn clk_put(host->clk); 870f4f7561eSAndrew Lunn } 871236caa7cSMaen Suleiman mmc_free_host(mmc); 872236caa7cSMaen Suleiman } 873236caa7cSMaen Suleiman platform_set_drvdata(pdev, NULL); 874236caa7cSMaen Suleiman return 0; 875236caa7cSMaen Suleiman } 876236caa7cSMaen Suleiman 877236caa7cSMaen Suleiman #ifdef CONFIG_PM 8782e058a6fSRabin Vincent static int mvsd_suspend(struct platform_device *dev, pm_message_t state) 879236caa7cSMaen Suleiman { 880236caa7cSMaen Suleiman struct mmc_host *mmc = platform_get_drvdata(dev); 881236caa7cSMaen Suleiman int ret = 0; 882236caa7cSMaen Suleiman 8832e058a6fSRabin Vincent if (mmc) 8841a13f8faSMatt Fleming ret = mmc_suspend_host(mmc); 885236caa7cSMaen Suleiman 886236caa7cSMaen Suleiman return ret; 887236caa7cSMaen Suleiman } 888236caa7cSMaen Suleiman 8892e058a6fSRabin Vincent static int mvsd_resume(struct platform_device *dev) 890236caa7cSMaen Suleiman { 8912e058a6fSRabin Vincent struct mmc_host *mmc = platform_get_drvdata(dev); 892236caa7cSMaen Suleiman int ret = 0; 893236caa7cSMaen Suleiman 8942e058a6fSRabin Vincent if (mmc) 895236caa7cSMaen Suleiman ret = mmc_resume_host(mmc); 896236caa7cSMaen Suleiman 897236caa7cSMaen Suleiman return ret; 898236caa7cSMaen Suleiman } 899236caa7cSMaen Suleiman #else 900236caa7cSMaen Suleiman #define mvsd_suspend NULL 901236caa7cSMaen Suleiman #define mvsd_resume NULL 902236caa7cSMaen Suleiman #endif 903236caa7cSMaen Suleiman 904236caa7cSMaen Suleiman static struct platform_driver mvsd_driver = { 905236caa7cSMaen Suleiman .remove = __exit_p(mvsd_remove), 906236caa7cSMaen Suleiman .suspend = mvsd_suspend, 907236caa7cSMaen Suleiman .resume = mvsd_resume, 908236caa7cSMaen Suleiman .driver = { 909236caa7cSMaen Suleiman .name = DRIVER_NAME, 910236caa7cSMaen Suleiman }, 911236caa7cSMaen Suleiman }; 912236caa7cSMaen Suleiman 913236caa7cSMaen Suleiman static int __init mvsd_init(void) 914236caa7cSMaen Suleiman { 915236caa7cSMaen Suleiman return platform_driver_probe(&mvsd_driver, mvsd_probe); 916236caa7cSMaen Suleiman } 917236caa7cSMaen Suleiman 918236caa7cSMaen Suleiman static void __exit mvsd_exit(void) 919236caa7cSMaen Suleiman { 920236caa7cSMaen Suleiman platform_driver_unregister(&mvsd_driver); 921236caa7cSMaen Suleiman } 922236caa7cSMaen Suleiman 923236caa7cSMaen Suleiman module_init(mvsd_init); 924236caa7cSMaen Suleiman module_exit(mvsd_exit); 925236caa7cSMaen Suleiman 926236caa7cSMaen Suleiman /* maximum card clock frequency (default 50MHz) */ 927236caa7cSMaen Suleiman module_param(maxfreq, int, 0); 928236caa7cSMaen Suleiman 929236caa7cSMaen Suleiman /* force PIO transfers all the time */ 930236caa7cSMaen Suleiman module_param(nodma, int, 0); 931236caa7cSMaen Suleiman 932236caa7cSMaen Suleiman MODULE_AUTHOR("Maen Suleiman, Nicolas Pitre"); 933236caa7cSMaen Suleiman MODULE_DESCRIPTION("Marvell MMC,SD,SDIO Host Controller driver"); 934236caa7cSMaen Suleiman MODULE_LICENSE("GPL"); 935703aacedSNicolas Pitre MODULE_ALIAS("platform:mvsdio"); 936