1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2015 MediaTek Inc. 4 * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 5 */ 6 7 #include <linux/module.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/ioport.h> 12 #include <linux/irq.h> 13 #include <linux/of_address.h> 14 #include <linux/of_device.h> 15 #include <linux/of_irq.h> 16 #include <linux/of_gpio.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/slab.h> 23 #include <linux/spinlock.h> 24 #include <linux/interrupt.h> 25 #include <linux/reset.h> 26 27 #include <linux/mmc/card.h> 28 #include <linux/mmc/core.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/mmc.h> 31 #include <linux/mmc/sd.h> 32 #include <linux/mmc/sdio.h> 33 #include <linux/mmc/slot-gpio.h> 34 35 #include "cqhci.h" 36 37 #define MAX_BD_NUM 1024 38 39 /*--------------------------------------------------------------------------*/ 40 /* Common Definition */ 41 /*--------------------------------------------------------------------------*/ 42 #define MSDC_BUS_1BITS 0x0 43 #define MSDC_BUS_4BITS 0x1 44 #define MSDC_BUS_8BITS 0x2 45 46 #define MSDC_BURST_64B 0x6 47 48 /*--------------------------------------------------------------------------*/ 49 /* Register Offset */ 50 /*--------------------------------------------------------------------------*/ 51 #define MSDC_CFG 0x0 52 #define MSDC_IOCON 0x04 53 #define MSDC_PS 0x08 54 #define MSDC_INT 0x0c 55 #define MSDC_INTEN 0x10 56 #define MSDC_FIFOCS 0x14 57 #define SDC_CFG 0x30 58 #define SDC_CMD 0x34 59 #define SDC_ARG 0x38 60 #define SDC_STS 0x3c 61 #define SDC_RESP0 0x40 62 #define SDC_RESP1 0x44 63 #define SDC_RESP2 0x48 64 #define SDC_RESP3 0x4c 65 #define SDC_BLK_NUM 0x50 66 #define SDC_ADV_CFG0 0x64 67 #define EMMC_IOCON 0x7c 68 #define SDC_ACMD_RESP 0x80 69 #define DMA_SA_H4BIT 0x8c 70 #define MSDC_DMA_SA 0x90 71 #define MSDC_DMA_CTRL 0x98 72 #define MSDC_DMA_CFG 0x9c 73 #define MSDC_PATCH_BIT 0xb0 74 #define MSDC_PATCH_BIT1 0xb4 75 #define MSDC_PATCH_BIT2 0xb8 76 #define MSDC_PAD_TUNE 0xec 77 #define MSDC_PAD_TUNE0 0xf0 78 #define PAD_DS_TUNE 0x188 79 #define PAD_CMD_TUNE 0x18c 80 #define EMMC50_CFG0 0x208 81 #define EMMC50_CFG3 0x220 82 #define SDC_FIFO_CFG 0x228 83 84 /*--------------------------------------------------------------------------*/ 85 /* Top Pad Register Offset */ 86 /*--------------------------------------------------------------------------*/ 87 #define EMMC_TOP_CONTROL 0x00 88 #define EMMC_TOP_CMD 0x04 89 #define EMMC50_PAD_DS_TUNE 0x0c 90 91 /*--------------------------------------------------------------------------*/ 92 /* Register Mask */ 93 /*--------------------------------------------------------------------------*/ 94 95 /* MSDC_CFG mask */ 96 #define MSDC_CFG_MODE (0x1 << 0) /* RW */ 97 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ 98 #define MSDC_CFG_RST (0x1 << 2) /* RW */ 99 #define MSDC_CFG_PIO (0x1 << 3) /* RW */ 100 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ 101 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ 102 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ 103 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ 104 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ 105 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ 106 #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */ 107 #define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */ 108 #define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */ 109 #define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */ 110 111 /* MSDC_IOCON mask */ 112 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ 113 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ 114 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ 115 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ 116 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ 117 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ 118 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ 119 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ 120 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ 121 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ 122 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ 123 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ 124 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ 125 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ 126 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ 127 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ 128 129 /* MSDC_PS mask */ 130 #define MSDC_PS_CDEN (0x1 << 0) /* RW */ 131 #define MSDC_PS_CDSTS (0x1 << 1) /* R */ 132 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ 133 #define MSDC_PS_DAT (0xff << 16) /* R */ 134 #define MSDC_PS_DATA1 (0x1 << 17) /* R */ 135 #define MSDC_PS_CMD (0x1 << 24) /* R */ 136 #define MSDC_PS_WP (0x1 << 31) /* R */ 137 138 /* MSDC_INT mask */ 139 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ 140 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ 141 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ 142 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ 143 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ 144 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ 145 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ 146 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ 147 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ 148 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ 149 #define MSDC_INT_CSTA (0x1 << 11) /* R */ 150 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ 151 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ 152 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ 153 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ 154 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ 155 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ 156 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ 157 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ 158 #define MSDC_INT_CMDQ (0x1 << 28) /* W1C */ 159 160 /* MSDC_INTEN mask */ 161 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ 162 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ 163 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ 164 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ 165 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ 166 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ 167 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ 168 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ 169 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ 170 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ 171 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ 172 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ 173 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ 174 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ 175 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ 176 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ 177 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ 178 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ 179 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ 180 181 /* MSDC_FIFOCS mask */ 182 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 183 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 184 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ 185 186 /* SDC_CFG mask */ 187 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ 188 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ 189 #define SDC_CFG_WRDTOC (0x1fff << 2) /* RW */ 190 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 191 #define SDC_CFG_SDIO (0x1 << 19) /* RW */ 192 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 193 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ 194 #define SDC_CFG_DTOC (0xff << 24) /* RW */ 195 196 /* SDC_STS mask */ 197 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ 198 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 199 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ 200 201 #define SDC_DAT1_IRQ_TRIGGER (0x1 << 19) /* RW */ 202 /* SDC_ADV_CFG0 mask */ 203 #define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */ 204 205 /* DMA_SA_H4BIT mask */ 206 #define DMA_ADDR_HIGH_4BIT (0xf << 0) /* RW */ 207 208 /* MSDC_DMA_CTRL mask */ 209 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ 210 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ 211 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ 212 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ 213 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ 214 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ 215 216 /* MSDC_DMA_CFG mask */ 217 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ 218 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ 219 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ 220 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ 221 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ 222 223 /* MSDC_PATCH_BIT mask */ 224 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ 225 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) 226 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) 227 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ 228 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ 229 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ 230 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ 231 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ 232 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ 233 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ 234 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ 235 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ 236 237 #define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */ 238 #define MSDC_PB1_BUSY_CHECK_SEL (0x1 << 7) /* RW */ 239 #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ 240 241 #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ 242 #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */ 243 #define MSDC_PB2_SUPPORT_64G (0x1 << 1) /* RW */ 244 #define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */ 245 #define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */ 246 #define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */ 247 248 #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */ 249 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */ 250 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */ 251 #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */ 252 #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */ 253 #define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */ 254 #define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */ 255 #define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */ 256 257 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */ 258 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */ 259 #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */ 260 261 #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */ 262 263 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */ 264 #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ 265 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ 266 267 #define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */ 268 269 #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */ 270 #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */ 271 272 /* EMMC_TOP_CONTROL mask */ 273 #define PAD_RXDLY_SEL (0x1 << 0) /* RW */ 274 #define DELAY_EN (0x1 << 1) /* RW */ 275 #define PAD_DAT_RD_RXDLY2 (0x1f << 2) /* RW */ 276 #define PAD_DAT_RD_RXDLY (0x1f << 7) /* RW */ 277 #define PAD_DAT_RD_RXDLY2_SEL (0x1 << 12) /* RW */ 278 #define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */ 279 #define DATA_K_VALUE_SEL (0x1 << 14) /* RW */ 280 #define SDC_RX_ENH_EN (0x1 << 15) /* TW */ 281 282 /* EMMC_TOP_CMD mask */ 283 #define PAD_CMD_RXDLY2 (0x1f << 0) /* RW */ 284 #define PAD_CMD_RXDLY (0x1f << 5) /* RW */ 285 #define PAD_CMD_RD_RXDLY2_SEL (0x1 << 10) /* RW */ 286 #define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */ 287 #define PAD_CMD_TX_DLY (0x1f << 12) /* RW */ 288 289 #define REQ_CMD_EIO (0x1 << 0) 290 #define REQ_CMD_TMO (0x1 << 1) 291 #define REQ_DAT_ERR (0x1 << 2) 292 #define REQ_STOP_EIO (0x1 << 3) 293 #define REQ_STOP_TMO (0x1 << 4) 294 #define REQ_CMD_BUSY (0x1 << 5) 295 296 #define MSDC_PREPARE_FLAG (0x1 << 0) 297 #define MSDC_ASYNC_FLAG (0x1 << 1) 298 #define MSDC_MMAP_FLAG (0x1 << 2) 299 300 #define MTK_MMC_AUTOSUSPEND_DELAY 50 301 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 302 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 303 304 #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */ 305 306 #define PAD_DELAY_MAX 32 /* PAD delay cells */ 307 /*--------------------------------------------------------------------------*/ 308 /* Descriptor Structure */ 309 /*--------------------------------------------------------------------------*/ 310 struct mt_gpdma_desc { 311 u32 gpd_info; 312 #define GPDMA_DESC_HWO (0x1 << 0) 313 #define GPDMA_DESC_BDP (0x1 << 1) 314 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 315 #define GPDMA_DESC_INT (0x1 << 16) 316 #define GPDMA_DESC_NEXT_H4 (0xf << 24) 317 #define GPDMA_DESC_PTR_H4 (0xf << 28) 318 u32 next; 319 u32 ptr; 320 u32 gpd_data_len; 321 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 322 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ 323 u32 arg; 324 u32 blknum; 325 u32 cmd; 326 }; 327 328 struct mt_bdma_desc { 329 u32 bd_info; 330 #define BDMA_DESC_EOL (0x1 << 0) 331 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 332 #define BDMA_DESC_BLKPAD (0x1 << 17) 333 #define BDMA_DESC_DWPAD (0x1 << 18) 334 #define BDMA_DESC_NEXT_H4 (0xf << 24) 335 #define BDMA_DESC_PTR_H4 (0xf << 28) 336 u32 next; 337 u32 ptr; 338 u32 bd_data_len; 339 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 340 #define BDMA_DESC_BUFLEN_EXT (0xffffff) /* bit0 ~ bit23 */ 341 }; 342 343 struct msdc_dma { 344 struct scatterlist *sg; /* I/O scatter list */ 345 struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 346 struct mt_bdma_desc *bd; /* pointer to bd array */ 347 dma_addr_t gpd_addr; /* the physical address of gpd array */ 348 dma_addr_t bd_addr; /* the physical address of bd array */ 349 }; 350 351 struct msdc_save_para { 352 u32 msdc_cfg; 353 u32 iocon; 354 u32 sdc_cfg; 355 u32 pad_tune; 356 u32 patch_bit0; 357 u32 patch_bit1; 358 u32 patch_bit2; 359 u32 pad_ds_tune; 360 u32 pad_cmd_tune; 361 u32 emmc50_cfg0; 362 u32 emmc50_cfg3; 363 u32 sdc_fifo_cfg; 364 u32 emmc_top_control; 365 u32 emmc_top_cmd; 366 u32 emmc50_pad_ds_tune; 367 }; 368 369 struct mtk_mmc_compatible { 370 u8 clk_div_bits; 371 bool recheck_sdio_irq; 372 bool hs400_tune; /* only used for MT8173 */ 373 u32 pad_tune_reg; 374 bool async_fifo; 375 bool data_tune; 376 bool busy_check; 377 bool stop_clk_fix; 378 bool enhance_rx; 379 bool support_64g; 380 bool use_internal_cd; 381 }; 382 383 struct msdc_tune_para { 384 u32 iocon; 385 u32 pad_tune; 386 u32 pad_cmd_tune; 387 u32 emmc_top_control; 388 u32 emmc_top_cmd; 389 }; 390 391 struct msdc_delay_phase { 392 u8 maxlen; 393 u8 start; 394 u8 final_phase; 395 }; 396 397 struct msdc_host { 398 struct device *dev; 399 const struct mtk_mmc_compatible *dev_comp; 400 struct mmc_host *mmc; /* mmc structure */ 401 int cmd_rsp; 402 403 spinlock_t lock; 404 struct mmc_request *mrq; 405 struct mmc_command *cmd; 406 struct mmc_data *data; 407 int error; 408 409 void __iomem *base; /* host base address */ 410 void __iomem *top_base; /* host top register base address */ 411 412 struct msdc_dma dma; /* dma channel */ 413 u64 dma_mask; 414 415 u32 timeout_ns; /* data timeout ns */ 416 u32 timeout_clks; /* data timeout clks */ 417 418 struct pinctrl *pinctrl; 419 struct pinctrl_state *pins_default; 420 struct pinctrl_state *pins_uhs; 421 struct delayed_work req_timeout; 422 int irq; /* host interrupt */ 423 struct reset_control *reset; 424 425 struct clk *src_clk; /* msdc source clock */ 426 struct clk *h_clk; /* msdc h_clk */ 427 struct clk *bus_clk; /* bus clock which used to access register */ 428 struct clk *src_clk_cg; /* msdc source clock control gate */ 429 u32 mclk; /* mmc subsystem clock frequency */ 430 u32 src_clk_freq; /* source clock frequency */ 431 unsigned char timing; 432 bool vqmmc_enabled; 433 u32 latch_ck; 434 u32 hs400_ds_delay; 435 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 436 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 437 bool hs400_cmd_resp_sel_rising; 438 /* cmd response sample selection for HS400 */ 439 bool hs400_mode; /* current eMMC will run at hs400 mode */ 440 bool internal_cd; /* Use internal card-detect logic */ 441 bool cqhci; /* support eMMC hw cmdq */ 442 struct msdc_save_para save_para; /* used when gate HCLK */ 443 struct msdc_tune_para def_tune_para; /* default tune setting */ 444 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 445 struct cqhci_host *cq_host; 446 }; 447 448 static const struct mtk_mmc_compatible mt8135_compat = { 449 .clk_div_bits = 8, 450 .recheck_sdio_irq = false, 451 .hs400_tune = false, 452 .pad_tune_reg = MSDC_PAD_TUNE, 453 .async_fifo = false, 454 .data_tune = false, 455 .busy_check = false, 456 .stop_clk_fix = false, 457 .enhance_rx = false, 458 .support_64g = false, 459 }; 460 461 static const struct mtk_mmc_compatible mt8173_compat = { 462 .clk_div_bits = 8, 463 .recheck_sdio_irq = true, 464 .hs400_tune = true, 465 .pad_tune_reg = MSDC_PAD_TUNE, 466 .async_fifo = false, 467 .data_tune = false, 468 .busy_check = false, 469 .stop_clk_fix = false, 470 .enhance_rx = false, 471 .support_64g = false, 472 }; 473 474 static const struct mtk_mmc_compatible mt8183_compat = { 475 .clk_div_bits = 12, 476 .recheck_sdio_irq = false, 477 .hs400_tune = false, 478 .pad_tune_reg = MSDC_PAD_TUNE0, 479 .async_fifo = true, 480 .data_tune = true, 481 .busy_check = true, 482 .stop_clk_fix = true, 483 .enhance_rx = true, 484 .support_64g = true, 485 }; 486 487 static const struct mtk_mmc_compatible mt2701_compat = { 488 .clk_div_bits = 12, 489 .recheck_sdio_irq = false, 490 .hs400_tune = false, 491 .pad_tune_reg = MSDC_PAD_TUNE0, 492 .async_fifo = true, 493 .data_tune = true, 494 .busy_check = false, 495 .stop_clk_fix = false, 496 .enhance_rx = false, 497 .support_64g = false, 498 }; 499 500 static const struct mtk_mmc_compatible mt2712_compat = { 501 .clk_div_bits = 12, 502 .recheck_sdio_irq = false, 503 .hs400_tune = false, 504 .pad_tune_reg = MSDC_PAD_TUNE0, 505 .async_fifo = true, 506 .data_tune = true, 507 .busy_check = true, 508 .stop_clk_fix = true, 509 .enhance_rx = true, 510 .support_64g = true, 511 }; 512 513 static const struct mtk_mmc_compatible mt7622_compat = { 514 .clk_div_bits = 12, 515 .recheck_sdio_irq = false, 516 .hs400_tune = false, 517 .pad_tune_reg = MSDC_PAD_TUNE0, 518 .async_fifo = true, 519 .data_tune = true, 520 .busy_check = true, 521 .stop_clk_fix = true, 522 .enhance_rx = true, 523 .support_64g = false, 524 }; 525 526 static const struct mtk_mmc_compatible mt8516_compat = { 527 .clk_div_bits = 12, 528 .recheck_sdio_irq = false, 529 .hs400_tune = false, 530 .pad_tune_reg = MSDC_PAD_TUNE0, 531 .async_fifo = true, 532 .data_tune = true, 533 .busy_check = true, 534 .stop_clk_fix = true, 535 }; 536 537 static const struct mtk_mmc_compatible mt7620_compat = { 538 .clk_div_bits = 8, 539 .recheck_sdio_irq = false, 540 .hs400_tune = false, 541 .pad_tune_reg = MSDC_PAD_TUNE, 542 .async_fifo = false, 543 .data_tune = false, 544 .busy_check = false, 545 .stop_clk_fix = false, 546 .enhance_rx = false, 547 .use_internal_cd = true, 548 }; 549 550 static const struct mtk_mmc_compatible mt6779_compat = { 551 .clk_div_bits = 12, 552 .hs400_tune = false, 553 .pad_tune_reg = MSDC_PAD_TUNE0, 554 .async_fifo = true, 555 .data_tune = true, 556 .busy_check = true, 557 .stop_clk_fix = true, 558 .enhance_rx = true, 559 .support_64g = true, 560 }; 561 562 static const struct of_device_id msdc_of_ids[] = { 563 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, 564 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, 565 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, 566 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, 567 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, 568 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, 569 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, 570 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, 571 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, 572 {} 573 }; 574 MODULE_DEVICE_TABLE(of, msdc_of_ids); 575 576 static void sdr_set_bits(void __iomem *reg, u32 bs) 577 { 578 u32 val = readl(reg); 579 580 val |= bs; 581 writel(val, reg); 582 } 583 584 static void sdr_clr_bits(void __iomem *reg, u32 bs) 585 { 586 u32 val = readl(reg); 587 588 val &= ~bs; 589 writel(val, reg); 590 } 591 592 static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 593 { 594 unsigned int tv = readl(reg); 595 596 tv &= ~field; 597 tv |= ((val) << (ffs((unsigned int)field) - 1)); 598 writel(tv, reg); 599 } 600 601 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 602 { 603 unsigned int tv = readl(reg); 604 605 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 606 } 607 608 static void msdc_reset_hw(struct msdc_host *host) 609 { 610 u32 val; 611 612 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 613 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) 614 cpu_relax(); 615 616 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 617 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) 618 cpu_relax(); 619 620 val = readl(host->base + MSDC_INT); 621 writel(val, host->base + MSDC_INT); 622 } 623 624 static void msdc_cmd_next(struct msdc_host *host, 625 struct mmc_request *mrq, struct mmc_command *cmd); 626 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb); 627 628 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 629 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 630 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 631 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 632 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 633 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 634 635 static u8 msdc_dma_calcs(u8 *buf, u32 len) 636 { 637 u32 i, sum = 0; 638 639 for (i = 0; i < len; i++) 640 sum += buf[i]; 641 return 0xff - (u8) sum; 642 } 643 644 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 645 struct mmc_data *data) 646 { 647 unsigned int j, dma_len; 648 dma_addr_t dma_address; 649 u32 dma_ctrl; 650 struct scatterlist *sg; 651 struct mt_gpdma_desc *gpd; 652 struct mt_bdma_desc *bd; 653 654 sg = data->sg; 655 656 gpd = dma->gpd; 657 bd = dma->bd; 658 659 /* modify gpd */ 660 gpd->gpd_info |= GPDMA_DESC_HWO; 661 gpd->gpd_info |= GPDMA_DESC_BDP; 662 /* need to clear first. use these bits to calc checksum */ 663 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 664 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 665 666 /* modify bd */ 667 for_each_sg(data->sg, sg, data->sg_count, j) { 668 dma_address = sg_dma_address(sg); 669 dma_len = sg_dma_len(sg); 670 671 /* init bd */ 672 bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 673 bd[j].bd_info &= ~BDMA_DESC_DWPAD; 674 bd[j].ptr = lower_32_bits(dma_address); 675 if (host->dev_comp->support_64g) { 676 bd[j].bd_info &= ~BDMA_DESC_PTR_H4; 677 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf) 678 << 28; 679 } 680 681 if (host->dev_comp->support_64g) { 682 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT; 683 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT); 684 } else { 685 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 686 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 687 } 688 689 if (j == data->sg_count - 1) /* the last bd */ 690 bd[j].bd_info |= BDMA_DESC_EOL; 691 else 692 bd[j].bd_info &= ~BDMA_DESC_EOL; 693 694 /* checksume need to clear first */ 695 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 696 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 697 } 698 699 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 700 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 701 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 702 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); 703 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 704 if (host->dev_comp->support_64g) 705 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, 706 upper_32_bits(dma->gpd_addr) & 0xf); 707 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); 708 } 709 710 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq) 711 { 712 struct mmc_data *data = mrq->data; 713 714 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 715 data->host_cookie |= MSDC_PREPARE_FLAG; 716 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 717 mmc_get_dma_dir(data)); 718 } 719 } 720 721 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) 722 { 723 struct mmc_data *data = mrq->data; 724 725 if (data->host_cookie & MSDC_ASYNC_FLAG) 726 return; 727 728 if (data->host_cookie & MSDC_PREPARE_FLAG) { 729 dma_unmap_sg(host->dev, data->sg, data->sg_len, 730 mmc_get_dma_dir(data)); 731 data->host_cookie &= ~MSDC_PREPARE_FLAG; 732 } 733 } 734 735 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) 736 { 737 u64 timeout, clk_ns; 738 u32 mode = 0; 739 740 if (host->mmc->actual_clock == 0) { 741 timeout = 0; 742 } else { 743 clk_ns = 1000000000ULL; 744 do_div(clk_ns, host->mmc->actual_clock); 745 timeout = ns + clk_ns - 1; 746 do_div(timeout, clk_ns); 747 timeout += clks; 748 /* in 1048576 sclk cycle unit */ 749 timeout = DIV_ROUND_UP(timeout, (0x1 << 20)); 750 if (host->dev_comp->clk_div_bits == 8) 751 sdr_get_field(host->base + MSDC_CFG, 752 MSDC_CFG_CKMOD, &mode); 753 else 754 sdr_get_field(host->base + MSDC_CFG, 755 MSDC_CFG_CKMOD_EXTRA, &mode); 756 /*DDR mode will double the clk cycles for data timeout */ 757 timeout = mode >= 2 ? timeout * 2 : timeout; 758 timeout = timeout > 1 ? timeout - 1 : 0; 759 } 760 return timeout; 761 } 762 763 /* clock control primitives */ 764 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) 765 { 766 u64 timeout; 767 768 host->timeout_ns = ns; 769 host->timeout_clks = clks; 770 771 timeout = msdc_timeout_cal(host, ns, clks); 772 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 773 (u32)(timeout > 255 ? 255 : timeout)); 774 } 775 776 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) 777 { 778 u64 timeout; 779 780 timeout = msdc_timeout_cal(host, ns, clks); 781 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, 782 (u32)(timeout > 8191 ? 8191 : timeout)); 783 } 784 785 static void msdc_gate_clock(struct msdc_host *host) 786 { 787 clk_disable_unprepare(host->src_clk_cg); 788 clk_disable_unprepare(host->src_clk); 789 clk_disable_unprepare(host->bus_clk); 790 clk_disable_unprepare(host->h_clk); 791 } 792 793 static void msdc_ungate_clock(struct msdc_host *host) 794 { 795 clk_prepare_enable(host->h_clk); 796 clk_prepare_enable(host->bus_clk); 797 clk_prepare_enable(host->src_clk); 798 clk_prepare_enable(host->src_clk_cg); 799 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 800 cpu_relax(); 801 } 802 803 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 804 { 805 u32 mode; 806 u32 flags; 807 u32 div; 808 u32 sclk; 809 u32 tune_reg = host->dev_comp->pad_tune_reg; 810 811 if (!hz) { 812 dev_dbg(host->dev, "set mclk to 0\n"); 813 host->mclk = 0; 814 host->mmc->actual_clock = 0; 815 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 816 return; 817 } 818 819 flags = readl(host->base + MSDC_INTEN); 820 sdr_clr_bits(host->base + MSDC_INTEN, flags); 821 if (host->dev_comp->clk_div_bits == 8) 822 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 823 else 824 sdr_clr_bits(host->base + MSDC_CFG, 825 MSDC_CFG_HS400_CK_MODE_EXTRA); 826 if (timing == MMC_TIMING_UHS_DDR50 || 827 timing == MMC_TIMING_MMC_DDR52 || 828 timing == MMC_TIMING_MMC_HS400) { 829 if (timing == MMC_TIMING_MMC_HS400) 830 mode = 0x3; 831 else 832 mode = 0x2; /* ddr mode and use divisor */ 833 834 if (hz >= (host->src_clk_freq >> 2)) { 835 div = 0; /* mean div = 1/4 */ 836 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 837 } else { 838 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 839 sclk = (host->src_clk_freq >> 2) / div; 840 div = (div >> 1); 841 } 842 843 if (timing == MMC_TIMING_MMC_HS400 && 844 hz >= (host->src_clk_freq >> 1)) { 845 if (host->dev_comp->clk_div_bits == 8) 846 sdr_set_bits(host->base + MSDC_CFG, 847 MSDC_CFG_HS400_CK_MODE); 848 else 849 sdr_set_bits(host->base + MSDC_CFG, 850 MSDC_CFG_HS400_CK_MODE_EXTRA); 851 sclk = host->src_clk_freq >> 1; 852 div = 0; /* div is ignore when bit18 is set */ 853 } 854 } else if (hz >= host->src_clk_freq) { 855 mode = 0x1; /* no divisor */ 856 div = 0; 857 sclk = host->src_clk_freq; 858 } else { 859 mode = 0x0; /* use divisor */ 860 if (hz >= (host->src_clk_freq >> 1)) { 861 div = 0; /* mean div = 1/2 */ 862 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 863 } else { 864 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 865 sclk = (host->src_clk_freq >> 2) / div; 866 } 867 } 868 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 869 /* 870 * As src_clk/HCLK use the same bit to gate/ungate, 871 * So if want to only gate src_clk, need gate its parent(mux). 872 */ 873 if (host->src_clk_cg) 874 clk_disable_unprepare(host->src_clk_cg); 875 else 876 clk_disable_unprepare(clk_get_parent(host->src_clk)); 877 if (host->dev_comp->clk_div_bits == 8) 878 sdr_set_field(host->base + MSDC_CFG, 879 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 880 (mode << 8) | div); 881 else 882 sdr_set_field(host->base + MSDC_CFG, 883 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, 884 (mode << 12) | div); 885 if (host->src_clk_cg) 886 clk_prepare_enable(host->src_clk_cg); 887 else 888 clk_prepare_enable(clk_get_parent(host->src_clk)); 889 890 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 891 cpu_relax(); 892 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 893 host->mmc->actual_clock = sclk; 894 host->mclk = hz; 895 host->timing = timing; 896 /* need because clk changed. */ 897 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 898 sdr_set_bits(host->base + MSDC_INTEN, flags); 899 900 /* 901 * mmc_select_hs400() will drop to 50Mhz and High speed mode, 902 * tune result of hs200/200Mhz is not suitable for 50Mhz 903 */ 904 if (host->mmc->actual_clock <= 52000000) { 905 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 906 if (host->top_base) { 907 writel(host->def_tune_para.emmc_top_control, 908 host->top_base + EMMC_TOP_CONTROL); 909 writel(host->def_tune_para.emmc_top_cmd, 910 host->top_base + EMMC_TOP_CMD); 911 } else { 912 writel(host->def_tune_para.pad_tune, 913 host->base + tune_reg); 914 } 915 } else { 916 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 917 writel(host->saved_tune_para.pad_cmd_tune, 918 host->base + PAD_CMD_TUNE); 919 if (host->top_base) { 920 writel(host->saved_tune_para.emmc_top_control, 921 host->top_base + EMMC_TOP_CONTROL); 922 writel(host->saved_tune_para.emmc_top_cmd, 923 host->top_base + EMMC_TOP_CMD); 924 } else { 925 writel(host->saved_tune_para.pad_tune, 926 host->base + tune_reg); 927 } 928 } 929 930 if (timing == MMC_TIMING_MMC_HS400 && 931 host->dev_comp->hs400_tune) 932 sdr_set_field(host->base + tune_reg, 933 MSDC_PAD_TUNE_CMDRRDLY, 934 host->hs400_cmd_int_delay); 935 dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->mmc->actual_clock, 936 timing); 937 } 938 939 static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 940 struct mmc_request *mrq, struct mmc_command *cmd) 941 { 942 u32 resp; 943 944 switch (mmc_resp_type(cmd)) { 945 /* Actually, R1, R5, R6, R7 are the same */ 946 case MMC_RSP_R1: 947 resp = 0x1; 948 break; 949 case MMC_RSP_R1B: 950 resp = 0x7; 951 break; 952 case MMC_RSP_R2: 953 resp = 0x2; 954 break; 955 case MMC_RSP_R3: 956 resp = 0x3; 957 break; 958 case MMC_RSP_NONE: 959 default: 960 resp = 0x0; 961 break; 962 } 963 964 return resp; 965 } 966 967 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 968 struct mmc_request *mrq, struct mmc_command *cmd) 969 { 970 /* rawcmd : 971 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 972 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 973 */ 974 u32 opcode = cmd->opcode; 975 u32 resp = msdc_cmd_find_resp(host, mrq, cmd); 976 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 977 978 host->cmd_rsp = resp; 979 980 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 981 opcode == MMC_STOP_TRANSMISSION) 982 rawcmd |= (0x1 << 14); 983 else if (opcode == SD_SWITCH_VOLTAGE) 984 rawcmd |= (0x1 << 30); 985 else if (opcode == SD_APP_SEND_SCR || 986 opcode == SD_APP_SEND_NUM_WR_BLKS || 987 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 988 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 989 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 990 rawcmd |= (0x1 << 11); 991 992 if (cmd->data) { 993 struct mmc_data *data = cmd->data; 994 995 if (mmc_op_multi(opcode)) { 996 if (mmc_card_mmc(host->mmc->card) && mrq->sbc && 997 !(mrq->sbc->arg & 0xFFFF0000)) 998 rawcmd |= 0x2 << 28; /* AutoCMD23 */ 999 } 1000 1001 rawcmd |= ((data->blksz & 0xFFF) << 16); 1002 if (data->flags & MMC_DATA_WRITE) 1003 rawcmd |= (0x1 << 13); 1004 if (data->blocks > 1) 1005 rawcmd |= (0x2 << 11); 1006 else 1007 rawcmd |= (0x1 << 11); 1008 /* Always use dma mode */ 1009 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 1010 1011 if (host->timeout_ns != data->timeout_ns || 1012 host->timeout_clks != data->timeout_clks) 1013 msdc_set_timeout(host, data->timeout_ns, 1014 data->timeout_clks); 1015 1016 writel(data->blocks, host->base + SDC_BLK_NUM); 1017 } 1018 return rawcmd; 1019 } 1020 1021 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, 1022 struct mmc_command *cmd, struct mmc_data *data) 1023 { 1024 bool read; 1025 1026 WARN_ON(host->data); 1027 host->data = data; 1028 read = data->flags & MMC_DATA_READ; 1029 1030 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1031 msdc_dma_setup(host, &host->dma, data); 1032 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 1033 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 1034 dev_dbg(host->dev, "DMA start\n"); 1035 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 1036 __func__, cmd->opcode, data->blocks, read); 1037 } 1038 1039 static int msdc_auto_cmd_done(struct msdc_host *host, int events, 1040 struct mmc_command *cmd) 1041 { 1042 u32 *rsp = cmd->resp; 1043 1044 rsp[0] = readl(host->base + SDC_ACMD_RESP); 1045 1046 if (events & MSDC_INT_ACMDRDY) { 1047 cmd->error = 0; 1048 } else { 1049 msdc_reset_hw(host); 1050 if (events & MSDC_INT_ACMDCRCERR) { 1051 cmd->error = -EILSEQ; 1052 host->error |= REQ_STOP_EIO; 1053 } else if (events & MSDC_INT_ACMDTMO) { 1054 cmd->error = -ETIMEDOUT; 1055 host->error |= REQ_STOP_TMO; 1056 } 1057 dev_err(host->dev, 1058 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 1059 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 1060 } 1061 return cmd->error; 1062 } 1063 1064 /* 1065 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost 1066 * 1067 * Host controller may lost interrupt in some special case. 1068 * Add SDIO irq recheck mechanism to make sure all interrupts 1069 * can be processed immediately 1070 */ 1071 static void msdc_recheck_sdio_irq(struct msdc_host *host) 1072 { 1073 u32 reg_int, reg_inten, reg_ps; 1074 1075 if (host->mmc->caps & MMC_CAP_SDIO_IRQ) { 1076 reg_inten = readl(host->base + MSDC_INTEN); 1077 if (reg_inten & MSDC_INTEN_SDIOIRQ) { 1078 reg_int = readl(host->base + MSDC_INT); 1079 reg_ps = readl(host->base + MSDC_PS); 1080 if (!(reg_int & MSDC_INT_SDIOIRQ || 1081 reg_ps & MSDC_PS_DATA1)) { 1082 __msdc_enable_sdio_irq(host, 0); 1083 sdio_signal_irq(host->mmc); 1084 } 1085 } 1086 } 1087 } 1088 1089 static void msdc_track_cmd_data(struct msdc_host *host, 1090 struct mmc_command *cmd, struct mmc_data *data) 1091 { 1092 if (host->error) 1093 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 1094 __func__, cmd->opcode, cmd->arg, host->error); 1095 } 1096 1097 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 1098 { 1099 unsigned long flags; 1100 bool ret; 1101 1102 ret = cancel_delayed_work(&host->req_timeout); 1103 if (!ret) { 1104 /* delay work already running */ 1105 return; 1106 } 1107 spin_lock_irqsave(&host->lock, flags); 1108 host->mrq = NULL; 1109 spin_unlock_irqrestore(&host->lock, flags); 1110 1111 msdc_track_cmd_data(host, mrq->cmd, mrq->data); 1112 if (mrq->data) 1113 msdc_unprepare_data(host, mrq); 1114 if (host->error) 1115 msdc_reset_hw(host); 1116 mmc_request_done(host->mmc, mrq); 1117 if (host->dev_comp->recheck_sdio_irq) 1118 msdc_recheck_sdio_irq(host); 1119 } 1120 1121 /* returns true if command is fully handled; returns false otherwise */ 1122 static bool msdc_cmd_done(struct msdc_host *host, int events, 1123 struct mmc_request *mrq, struct mmc_command *cmd) 1124 { 1125 bool done = false; 1126 bool sbc_error; 1127 unsigned long flags; 1128 u32 *rsp = cmd->resp; 1129 1130 if (mrq->sbc && cmd == mrq->cmd && 1131 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 1132 | MSDC_INT_ACMDTMO))) 1133 msdc_auto_cmd_done(host, events, mrq->sbc); 1134 1135 sbc_error = mrq->sbc && mrq->sbc->error; 1136 1137 if (!sbc_error && !(events & (MSDC_INT_CMDRDY 1138 | MSDC_INT_RSPCRCERR 1139 | MSDC_INT_CMDTMO))) 1140 return done; 1141 1142 spin_lock_irqsave(&host->lock, flags); 1143 done = !host->cmd; 1144 host->cmd = NULL; 1145 spin_unlock_irqrestore(&host->lock, flags); 1146 1147 if (done) 1148 return true; 1149 1150 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1151 1152 if (cmd->flags & MMC_RSP_PRESENT) { 1153 if (cmd->flags & MMC_RSP_136) { 1154 rsp[0] = readl(host->base + SDC_RESP3); 1155 rsp[1] = readl(host->base + SDC_RESP2); 1156 rsp[2] = readl(host->base + SDC_RESP1); 1157 rsp[3] = readl(host->base + SDC_RESP0); 1158 } else { 1159 rsp[0] = readl(host->base + SDC_RESP0); 1160 } 1161 } 1162 1163 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 1164 if (events & MSDC_INT_CMDTMO || 1165 (cmd->opcode != MMC_SEND_TUNING_BLOCK && 1166 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)) 1167 /* 1168 * should not clear fifo/interrupt as the tune data 1169 * may have alreay come when cmd19/cmd21 gets response 1170 * CRC error. 1171 */ 1172 msdc_reset_hw(host); 1173 if (events & MSDC_INT_RSPCRCERR) { 1174 cmd->error = -EILSEQ; 1175 host->error |= REQ_CMD_EIO; 1176 } else if (events & MSDC_INT_CMDTMO) { 1177 cmd->error = -ETIMEDOUT; 1178 host->error |= REQ_CMD_TMO; 1179 } 1180 } 1181 if (cmd->error) 1182 dev_dbg(host->dev, 1183 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 1184 __func__, cmd->opcode, cmd->arg, rsp[0], 1185 cmd->error); 1186 1187 msdc_cmd_next(host, mrq, cmd); 1188 return true; 1189 } 1190 1191 /* It is the core layer's responsibility to ensure card status 1192 * is correct before issue a request. but host design do below 1193 * checks recommended. 1194 */ 1195 static inline bool msdc_cmd_is_ready(struct msdc_host *host, 1196 struct mmc_request *mrq, struct mmc_command *cmd) 1197 { 1198 /* The max busy time we can endure is 20ms */ 1199 unsigned long tmo = jiffies + msecs_to_jiffies(20); 1200 1201 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && 1202 time_before(jiffies, tmo)) 1203 cpu_relax(); 1204 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { 1205 dev_err(host->dev, "CMD bus busy detected\n"); 1206 host->error |= REQ_CMD_BUSY; 1207 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1208 return false; 1209 } 1210 1211 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 1212 tmo = jiffies + msecs_to_jiffies(20); 1213 /* R1B or with data, should check SDCBUSY */ 1214 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && 1215 time_before(jiffies, tmo)) 1216 cpu_relax(); 1217 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { 1218 dev_err(host->dev, "Controller busy detected\n"); 1219 host->error |= REQ_CMD_BUSY; 1220 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1221 return false; 1222 } 1223 } 1224 return true; 1225 } 1226 1227 static void msdc_start_command(struct msdc_host *host, 1228 struct mmc_request *mrq, struct mmc_command *cmd) 1229 { 1230 u32 rawcmd; 1231 unsigned long flags; 1232 1233 WARN_ON(host->cmd); 1234 host->cmd = cmd; 1235 1236 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1237 if (!msdc_cmd_is_ready(host, mrq, cmd)) 1238 return; 1239 1240 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 1241 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 1242 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 1243 msdc_reset_hw(host); 1244 } 1245 1246 cmd->error = 0; 1247 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 1248 1249 spin_lock_irqsave(&host->lock, flags); 1250 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1251 spin_unlock_irqrestore(&host->lock, flags); 1252 1253 writel(cmd->arg, host->base + SDC_ARG); 1254 writel(rawcmd, host->base + SDC_CMD); 1255 } 1256 1257 static void msdc_cmd_next(struct msdc_host *host, 1258 struct mmc_request *mrq, struct mmc_command *cmd) 1259 { 1260 if ((cmd->error && 1261 !(cmd->error == -EILSEQ && 1262 (cmd->opcode == MMC_SEND_TUNING_BLOCK || 1263 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) || 1264 (mrq->sbc && mrq->sbc->error)) 1265 msdc_request_done(host, mrq); 1266 else if (cmd == mrq->sbc) 1267 msdc_start_command(host, mrq, mrq->cmd); 1268 else if (!cmd->data) 1269 msdc_request_done(host, mrq); 1270 else 1271 msdc_start_data(host, mrq, cmd, cmd->data); 1272 } 1273 1274 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 1275 { 1276 struct msdc_host *host = mmc_priv(mmc); 1277 1278 host->error = 0; 1279 WARN_ON(host->mrq); 1280 host->mrq = mrq; 1281 1282 if (mrq->data) 1283 msdc_prepare_data(host, mrq); 1284 1285 /* if SBC is required, we have HW option and SW option. 1286 * if HW option is enabled, and SBC does not have "special" flags, 1287 * use HW option, otherwise use SW option 1288 */ 1289 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 1290 (mrq->sbc->arg & 0xFFFF0000))) 1291 msdc_start_command(host, mrq, mrq->sbc); 1292 else 1293 msdc_start_command(host, mrq, mrq->cmd); 1294 } 1295 1296 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 1297 { 1298 struct msdc_host *host = mmc_priv(mmc); 1299 struct mmc_data *data = mrq->data; 1300 1301 if (!data) 1302 return; 1303 1304 msdc_prepare_data(host, mrq); 1305 data->host_cookie |= MSDC_ASYNC_FLAG; 1306 } 1307 1308 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1309 int err) 1310 { 1311 struct msdc_host *host = mmc_priv(mmc); 1312 struct mmc_data *data; 1313 1314 data = mrq->data; 1315 if (!data) 1316 return; 1317 if (data->host_cookie) { 1318 data->host_cookie &= ~MSDC_ASYNC_FLAG; 1319 msdc_unprepare_data(host, mrq); 1320 } 1321 } 1322 1323 static void msdc_data_xfer_next(struct msdc_host *host, 1324 struct mmc_request *mrq, struct mmc_data *data) 1325 { 1326 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 1327 !mrq->sbc) 1328 msdc_start_command(host, mrq, mrq->stop); 1329 else 1330 msdc_request_done(host, mrq); 1331 } 1332 1333 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 1334 struct mmc_request *mrq, struct mmc_data *data) 1335 { 1336 struct mmc_command *stop = data->stop; 1337 unsigned long flags; 1338 bool done; 1339 unsigned int check_data = events & 1340 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 1341 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 1342 | MSDC_INT_DMA_PROTECT); 1343 1344 spin_lock_irqsave(&host->lock, flags); 1345 done = !host->data; 1346 if (check_data) 1347 host->data = NULL; 1348 spin_unlock_irqrestore(&host->lock, flags); 1349 1350 if (done) 1351 return true; 1352 1353 if (check_data || (stop && stop->error)) { 1354 dev_dbg(host->dev, "DMA status: 0x%8X\n", 1355 readl(host->base + MSDC_DMA_CFG)); 1356 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1357 1); 1358 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) 1359 cpu_relax(); 1360 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 1361 dev_dbg(host->dev, "DMA stop\n"); 1362 1363 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 1364 data->bytes_xfered = data->blocks * data->blksz; 1365 } else { 1366 dev_dbg(host->dev, "interrupt events: %x\n", events); 1367 msdc_reset_hw(host); 1368 host->error |= REQ_DAT_ERR; 1369 data->bytes_xfered = 0; 1370 1371 if (events & MSDC_INT_DATTMO) 1372 data->error = -ETIMEDOUT; 1373 else if (events & MSDC_INT_DATCRCERR) 1374 data->error = -EILSEQ; 1375 1376 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 1377 __func__, mrq->cmd->opcode, data->blocks); 1378 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 1379 (int)data->error, data->bytes_xfered); 1380 } 1381 1382 msdc_data_xfer_next(host, mrq, data); 1383 done = true; 1384 } 1385 return done; 1386 } 1387 1388 static void msdc_set_buswidth(struct msdc_host *host, u32 width) 1389 { 1390 u32 val = readl(host->base + SDC_CFG); 1391 1392 val &= ~SDC_CFG_BUSWIDTH; 1393 1394 switch (width) { 1395 default: 1396 case MMC_BUS_WIDTH_1: 1397 val |= (MSDC_BUS_1BITS << 16); 1398 break; 1399 case MMC_BUS_WIDTH_4: 1400 val |= (MSDC_BUS_4BITS << 16); 1401 break; 1402 case MMC_BUS_WIDTH_8: 1403 val |= (MSDC_BUS_8BITS << 16); 1404 break; 1405 } 1406 1407 writel(val, host->base + SDC_CFG); 1408 dev_dbg(host->dev, "Bus Width = %d", width); 1409 } 1410 1411 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 1412 { 1413 struct msdc_host *host = mmc_priv(mmc); 1414 int ret; 1415 1416 if (!IS_ERR(mmc->supply.vqmmc)) { 1417 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1418 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 1419 dev_err(host->dev, "Unsupported signal voltage!\n"); 1420 return -EINVAL; 1421 } 1422 1423 ret = mmc_regulator_set_vqmmc(mmc, ios); 1424 if (ret < 0) { 1425 dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1426 ret, ios->signal_voltage); 1427 return ret; 1428 } 1429 1430 /* Apply different pinctrl settings for different signal voltage */ 1431 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 1432 pinctrl_select_state(host->pinctrl, host->pins_uhs); 1433 else 1434 pinctrl_select_state(host->pinctrl, host->pins_default); 1435 } 1436 return 0; 1437 } 1438 1439 static int msdc_card_busy(struct mmc_host *mmc) 1440 { 1441 struct msdc_host *host = mmc_priv(mmc); 1442 u32 status = readl(host->base + MSDC_PS); 1443 1444 /* only check if data0 is low */ 1445 return !(status & BIT(16)); 1446 } 1447 1448 static void msdc_request_timeout(struct work_struct *work) 1449 { 1450 struct msdc_host *host = container_of(work, struct msdc_host, 1451 req_timeout.work); 1452 1453 /* simulate HW timeout status */ 1454 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 1455 if (host->mrq) { 1456 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 1457 host->mrq, host->mrq->cmd->opcode); 1458 if (host->cmd) { 1459 dev_err(host->dev, "%s: aborting cmd=%d\n", 1460 __func__, host->cmd->opcode); 1461 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 1462 host->cmd); 1463 } else if (host->data) { 1464 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 1465 __func__, host->mrq->cmd->opcode, 1466 host->data->blocks); 1467 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 1468 host->data); 1469 } 1470 } 1471 } 1472 1473 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb) 1474 { 1475 if (enb) { 1476 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1477 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1478 if (host->dev_comp->recheck_sdio_irq) 1479 msdc_recheck_sdio_irq(host); 1480 } else { 1481 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1482 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1483 } 1484 } 1485 1486 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) 1487 { 1488 unsigned long flags; 1489 struct msdc_host *host = mmc_priv(mmc); 1490 1491 spin_lock_irqsave(&host->lock, flags); 1492 __msdc_enable_sdio_irq(host, enb); 1493 spin_unlock_irqrestore(&host->lock, flags); 1494 1495 if (enb) 1496 pm_runtime_get_noresume(host->dev); 1497 else 1498 pm_runtime_put_noidle(host->dev); 1499 } 1500 1501 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) 1502 { 1503 int cmd_err = 0, dat_err = 0; 1504 1505 if (intsts & MSDC_INT_RSPCRCERR) { 1506 cmd_err = -EILSEQ; 1507 dev_err(host->dev, "%s: CMD CRC ERR", __func__); 1508 } else if (intsts & MSDC_INT_CMDTMO) { 1509 cmd_err = -ETIMEDOUT; 1510 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); 1511 } 1512 1513 if (intsts & MSDC_INT_DATCRCERR) { 1514 dat_err = -EILSEQ; 1515 dev_err(host->dev, "%s: DATA CRC ERR", __func__); 1516 } else if (intsts & MSDC_INT_DATTMO) { 1517 dat_err = -ETIMEDOUT; 1518 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); 1519 } 1520 1521 if (cmd_err || dat_err) { 1522 dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", 1523 cmd_err, dat_err, intsts); 1524 } 1525 1526 return cqhci_irq(host->mmc, 0, cmd_err, dat_err); 1527 } 1528 1529 static irqreturn_t msdc_irq(int irq, void *dev_id) 1530 { 1531 struct msdc_host *host = (struct msdc_host *) dev_id; 1532 1533 while (true) { 1534 unsigned long flags; 1535 struct mmc_request *mrq; 1536 struct mmc_command *cmd; 1537 struct mmc_data *data; 1538 u32 events, event_mask; 1539 1540 spin_lock_irqsave(&host->lock, flags); 1541 events = readl(host->base + MSDC_INT); 1542 event_mask = readl(host->base + MSDC_INTEN); 1543 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1544 __msdc_enable_sdio_irq(host, 0); 1545 /* clear interrupts */ 1546 writel(events & event_mask, host->base + MSDC_INT); 1547 1548 mrq = host->mrq; 1549 cmd = host->cmd; 1550 data = host->data; 1551 spin_unlock_irqrestore(&host->lock, flags); 1552 1553 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1554 sdio_signal_irq(host->mmc); 1555 1556 if ((events & event_mask) & MSDC_INT_CDSC) { 1557 if (host->internal_cd) 1558 mmc_detect_change(host->mmc, msecs_to_jiffies(20)); 1559 events &= ~MSDC_INT_CDSC; 1560 } 1561 1562 if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) 1563 break; 1564 1565 if ((host->mmc->caps2 & MMC_CAP2_CQE) && 1566 (events & MSDC_INT_CMDQ)) { 1567 msdc_cmdq_irq(host, events); 1568 /* clear interrupts */ 1569 writel(events, host->base + MSDC_INT); 1570 return IRQ_HANDLED; 1571 } 1572 1573 if (!mrq) { 1574 dev_err(host->dev, 1575 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 1576 __func__, events, event_mask); 1577 WARN_ON(1); 1578 break; 1579 } 1580 1581 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 1582 1583 if (cmd) 1584 msdc_cmd_done(host, events, mrq, cmd); 1585 else if (data) 1586 msdc_data_xfer_done(host, events, mrq, data); 1587 } 1588 1589 return IRQ_HANDLED; 1590 } 1591 1592 static void msdc_init_hw(struct msdc_host *host) 1593 { 1594 u32 val; 1595 u32 tune_reg = host->dev_comp->pad_tune_reg; 1596 1597 if (host->reset) { 1598 reset_control_assert(host->reset); 1599 usleep_range(10, 50); 1600 reset_control_deassert(host->reset); 1601 } 1602 1603 /* Configure to MMC/SD mode, clock free running */ 1604 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 1605 1606 /* Reset */ 1607 msdc_reset_hw(host); 1608 1609 /* Disable and clear all interrupts */ 1610 writel(0, host->base + MSDC_INTEN); 1611 val = readl(host->base + MSDC_INT); 1612 writel(val, host->base + MSDC_INT); 1613 1614 /* Configure card detection */ 1615 if (host->internal_cd) { 1616 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, 1617 DEFAULT_DEBOUNCE); 1618 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1619 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1620 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1621 } else { 1622 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1623 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1624 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1625 } 1626 1627 if (host->top_base) { 1628 writel(0, host->top_base + EMMC_TOP_CONTROL); 1629 writel(0, host->top_base + EMMC_TOP_CMD); 1630 } else { 1631 writel(0, host->base + tune_reg); 1632 } 1633 writel(0, host->base + MSDC_IOCON); 1634 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 1635 writel(0x403c0046, host->base + MSDC_PATCH_BIT); 1636 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 1637 writel(0xffff4089, host->base + MSDC_PATCH_BIT1); 1638 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1639 1640 if (host->dev_comp->stop_clk_fix) { 1641 sdr_set_field(host->base + MSDC_PATCH_BIT1, 1642 MSDC_PATCH_BIT1_STOP_DLY, 3); 1643 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1644 SDC_FIFO_CFG_WRVALIDSEL); 1645 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1646 SDC_FIFO_CFG_RDVALIDSEL); 1647 } 1648 1649 if (host->dev_comp->busy_check) 1650 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7)); 1651 1652 if (host->dev_comp->async_fifo) { 1653 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1654 MSDC_PB2_RESPWAIT, 3); 1655 if (host->dev_comp->enhance_rx) { 1656 if (host->top_base) 1657 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1658 SDC_RX_ENH_EN); 1659 else 1660 sdr_set_bits(host->base + SDC_ADV_CFG0, 1661 SDC_RX_ENHANCE_EN); 1662 } else { 1663 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1664 MSDC_PB2_RESPSTSENSEL, 2); 1665 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1666 MSDC_PB2_CRCSTSENSEL, 2); 1667 } 1668 /* use async fifo, then no need tune internal delay */ 1669 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, 1670 MSDC_PATCH_BIT2_CFGRESP); 1671 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1672 MSDC_PATCH_BIT2_CFGCRCSTS); 1673 } 1674 1675 if (host->dev_comp->support_64g) 1676 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1677 MSDC_PB2_SUPPORT_64G); 1678 if (host->dev_comp->data_tune) { 1679 if (host->top_base) { 1680 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1681 PAD_DAT_RD_RXDLY_SEL); 1682 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, 1683 DATA_K_VALUE_SEL); 1684 sdr_set_bits(host->top_base + EMMC_TOP_CMD, 1685 PAD_CMD_RD_RXDLY_SEL); 1686 } else { 1687 sdr_set_bits(host->base + tune_reg, 1688 MSDC_PAD_TUNE_RD_SEL | 1689 MSDC_PAD_TUNE_CMD_SEL); 1690 } 1691 } else { 1692 /* choose clock tune */ 1693 if (host->top_base) 1694 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1695 PAD_RXDLY_SEL); 1696 else 1697 sdr_set_bits(host->base + tune_reg, 1698 MSDC_PAD_TUNE_RXDLYSEL); 1699 } 1700 1701 /* Configure to enable SDIO mode. 1702 * it's must otherwise sdio cmd5 failed 1703 */ 1704 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1705 1706 /* Config SDIO device detect interrupt function */ 1707 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1708 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 1709 1710 /* Configure to default data timeout */ 1711 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 1712 1713 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 1714 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1715 if (host->top_base) { 1716 host->def_tune_para.emmc_top_control = 1717 readl(host->top_base + EMMC_TOP_CONTROL); 1718 host->def_tune_para.emmc_top_cmd = 1719 readl(host->top_base + EMMC_TOP_CMD); 1720 host->saved_tune_para.emmc_top_control = 1721 readl(host->top_base + EMMC_TOP_CONTROL); 1722 host->saved_tune_para.emmc_top_cmd = 1723 readl(host->top_base + EMMC_TOP_CMD); 1724 } else { 1725 host->def_tune_para.pad_tune = readl(host->base + tune_reg); 1726 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 1727 } 1728 dev_dbg(host->dev, "init hardware done!"); 1729 } 1730 1731 static void msdc_deinit_hw(struct msdc_host *host) 1732 { 1733 u32 val; 1734 1735 if (host->internal_cd) { 1736 /* Disabled card-detect */ 1737 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1738 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1739 } 1740 1741 /* Disable and clear all interrupts */ 1742 writel(0, host->base + MSDC_INTEN); 1743 1744 val = readl(host->base + MSDC_INT); 1745 writel(val, host->base + MSDC_INT); 1746 } 1747 1748 /* init gpd and bd list in msdc_drv_probe */ 1749 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 1750 { 1751 struct mt_gpdma_desc *gpd = dma->gpd; 1752 struct mt_bdma_desc *bd = dma->bd; 1753 dma_addr_t dma_addr; 1754 int i; 1755 1756 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 1757 1758 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); 1759 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 1760 /* gpd->next is must set for desc DMA 1761 * That's why must alloc 2 gpd structure. 1762 */ 1763 gpd->next = lower_32_bits(dma_addr); 1764 if (host->dev_comp->support_64g) 1765 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1766 1767 dma_addr = dma->bd_addr; 1768 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ 1769 if (host->dev_comp->support_64g) 1770 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; 1771 1772 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 1773 for (i = 0; i < (MAX_BD_NUM - 1); i++) { 1774 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); 1775 bd[i].next = lower_32_bits(dma_addr); 1776 if (host->dev_comp->support_64g) 1777 bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1778 } 1779 } 1780 1781 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1782 { 1783 struct msdc_host *host = mmc_priv(mmc); 1784 int ret; 1785 1786 msdc_set_buswidth(host, ios->bus_width); 1787 1788 /* Suspend/Resume will do power off/on */ 1789 switch (ios->power_mode) { 1790 case MMC_POWER_UP: 1791 if (!IS_ERR(mmc->supply.vmmc)) { 1792 msdc_init_hw(host); 1793 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1794 ios->vdd); 1795 if (ret) { 1796 dev_err(host->dev, "Failed to set vmmc power!\n"); 1797 return; 1798 } 1799 } 1800 break; 1801 case MMC_POWER_ON: 1802 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1803 ret = regulator_enable(mmc->supply.vqmmc); 1804 if (ret) 1805 dev_err(host->dev, "Failed to set vqmmc power!\n"); 1806 else 1807 host->vqmmc_enabled = true; 1808 } 1809 break; 1810 case MMC_POWER_OFF: 1811 if (!IS_ERR(mmc->supply.vmmc)) 1812 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1813 1814 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1815 regulator_disable(mmc->supply.vqmmc); 1816 host->vqmmc_enabled = false; 1817 } 1818 break; 1819 default: 1820 break; 1821 } 1822 1823 if (host->mclk != ios->clock || host->timing != ios->timing) 1824 msdc_set_mclk(host, ios->timing, ios->clock); 1825 } 1826 1827 static u32 test_delay_bit(u32 delay, u32 bit) 1828 { 1829 bit %= PAD_DELAY_MAX; 1830 return delay & (1 << bit); 1831 } 1832 1833 static int get_delay_len(u32 delay, u32 start_bit) 1834 { 1835 int i; 1836 1837 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 1838 if (test_delay_bit(delay, start_bit + i) == 0) 1839 return i; 1840 } 1841 return PAD_DELAY_MAX - start_bit; 1842 } 1843 1844 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 1845 { 1846 int start = 0, len = 0; 1847 int start_final = 0, len_final = 0; 1848 u8 final_phase = 0xff; 1849 struct msdc_delay_phase delay_phase = { 0, }; 1850 1851 if (delay == 0) { 1852 dev_err(host->dev, "phase error: [map:%x]\n", delay); 1853 delay_phase.final_phase = final_phase; 1854 return delay_phase; 1855 } 1856 1857 while (start < PAD_DELAY_MAX) { 1858 len = get_delay_len(delay, start); 1859 if (len_final < len) { 1860 start_final = start; 1861 len_final = len; 1862 } 1863 start += len ? len : 1; 1864 if (len >= 12 && start_final < 4) 1865 break; 1866 } 1867 1868 /* The rule is that to find the smallest delay cell */ 1869 if (start_final == 0) 1870 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 1871 else 1872 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 1873 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 1874 delay, len_final, final_phase); 1875 1876 delay_phase.maxlen = len_final; 1877 delay_phase.start = start_final; 1878 delay_phase.final_phase = final_phase; 1879 return delay_phase; 1880 } 1881 1882 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) 1883 { 1884 u32 tune_reg = host->dev_comp->pad_tune_reg; 1885 1886 if (host->top_base) 1887 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, 1888 value); 1889 else 1890 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1891 value); 1892 } 1893 1894 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) 1895 { 1896 u32 tune_reg = host->dev_comp->pad_tune_reg; 1897 1898 if (host->top_base) 1899 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, 1900 PAD_DAT_RD_RXDLY, value); 1901 else 1902 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, 1903 value); 1904 } 1905 1906 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 1907 { 1908 struct msdc_host *host = mmc_priv(mmc); 1909 u32 rise_delay = 0, fall_delay = 0; 1910 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1911 struct msdc_delay_phase internal_delay_phase; 1912 u8 final_delay, final_maxlen; 1913 u32 internal_delay = 0; 1914 u32 tune_reg = host->dev_comp->pad_tune_reg; 1915 int cmd_err; 1916 int i, j; 1917 1918 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 1919 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 1920 sdr_set_field(host->base + tune_reg, 1921 MSDC_PAD_TUNE_CMDRRDLY, 1922 host->hs200_cmd_int_delay); 1923 1924 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1925 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1926 msdc_set_cmd_delay(host, i); 1927 /* 1928 * Using the same parameters, it may sometimes pass the test, 1929 * but sometimes it may fail. To make sure the parameters are 1930 * more stable, we test each set of parameters 3 times. 1931 */ 1932 for (j = 0; j < 3; j++) { 1933 mmc_send_tuning(mmc, opcode, &cmd_err); 1934 if (!cmd_err) { 1935 rise_delay |= (1 << i); 1936 } else { 1937 rise_delay &= ~(1 << i); 1938 break; 1939 } 1940 } 1941 } 1942 final_rise_delay = get_best_delay(host, rise_delay); 1943 /* if rising edge has enough margin, then do not scan falling edge */ 1944 if (final_rise_delay.maxlen >= 12 || 1945 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1946 goto skip_fall; 1947 1948 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1949 for (i = 0; i < PAD_DELAY_MAX; i++) { 1950 msdc_set_cmd_delay(host, i); 1951 /* 1952 * Using the same parameters, it may sometimes pass the test, 1953 * but sometimes it may fail. To make sure the parameters are 1954 * more stable, we test each set of parameters 3 times. 1955 */ 1956 for (j = 0; j < 3; j++) { 1957 mmc_send_tuning(mmc, opcode, &cmd_err); 1958 if (!cmd_err) { 1959 fall_delay |= (1 << i); 1960 } else { 1961 fall_delay &= ~(1 << i); 1962 break; 1963 } 1964 } 1965 } 1966 final_fall_delay = get_best_delay(host, fall_delay); 1967 1968 skip_fall: 1969 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1970 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 1971 final_maxlen = final_fall_delay.maxlen; 1972 if (final_maxlen == final_rise_delay.maxlen) { 1973 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1974 final_delay = final_rise_delay.final_phase; 1975 } else { 1976 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1977 final_delay = final_fall_delay.final_phase; 1978 } 1979 msdc_set_cmd_delay(host, final_delay); 1980 1981 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) 1982 goto skip_internal; 1983 1984 for (i = 0; i < PAD_DELAY_MAX; i++) { 1985 sdr_set_field(host->base + tune_reg, 1986 MSDC_PAD_TUNE_CMDRRDLY, i); 1987 mmc_send_tuning(mmc, opcode, &cmd_err); 1988 if (!cmd_err) 1989 internal_delay |= (1 << i); 1990 } 1991 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 1992 internal_delay_phase = get_best_delay(host, internal_delay); 1993 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 1994 internal_delay_phase.final_phase); 1995 skip_internal: 1996 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 1997 return final_delay == 0xff ? -EIO : 0; 1998 } 1999 2000 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 2001 { 2002 struct msdc_host *host = mmc_priv(mmc); 2003 u32 cmd_delay = 0; 2004 struct msdc_delay_phase final_cmd_delay = { 0,}; 2005 u8 final_delay; 2006 int cmd_err; 2007 int i, j; 2008 2009 /* select EMMC50 PAD CMD tune */ 2010 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 2011 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); 2012 2013 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 2014 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 2015 sdr_set_field(host->base + MSDC_PAD_TUNE, 2016 MSDC_PAD_TUNE_CMDRRDLY, 2017 host->hs200_cmd_int_delay); 2018 2019 if (host->hs400_cmd_resp_sel_rising) 2020 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2021 else 2022 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2023 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2024 sdr_set_field(host->base + PAD_CMD_TUNE, 2025 PAD_CMD_TUNE_RX_DLY3, i); 2026 /* 2027 * Using the same parameters, it may sometimes pass the test, 2028 * but sometimes it may fail. To make sure the parameters are 2029 * more stable, we test each set of parameters 3 times. 2030 */ 2031 for (j = 0; j < 3; j++) { 2032 mmc_send_tuning(mmc, opcode, &cmd_err); 2033 if (!cmd_err) { 2034 cmd_delay |= (1 << i); 2035 } else { 2036 cmd_delay &= ~(1 << i); 2037 break; 2038 } 2039 } 2040 } 2041 final_cmd_delay = get_best_delay(host, cmd_delay); 2042 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 2043 final_cmd_delay.final_phase); 2044 final_delay = final_cmd_delay.final_phase; 2045 2046 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 2047 return final_delay == 0xff ? -EIO : 0; 2048 } 2049 2050 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 2051 { 2052 struct msdc_host *host = mmc_priv(mmc); 2053 u32 rise_delay = 0, fall_delay = 0; 2054 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2055 u8 final_delay, final_maxlen; 2056 int i, ret; 2057 2058 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2059 host->latch_ck); 2060 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2061 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2062 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2063 msdc_set_data_delay(host, i); 2064 ret = mmc_send_tuning(mmc, opcode, NULL); 2065 if (!ret) 2066 rise_delay |= (1 << i); 2067 } 2068 final_rise_delay = get_best_delay(host, rise_delay); 2069 /* if rising edge has enough margin, then do not scan falling edge */ 2070 if (final_rise_delay.maxlen >= 12 || 2071 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2072 goto skip_fall; 2073 2074 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2075 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2076 for (i = 0; i < PAD_DELAY_MAX; i++) { 2077 msdc_set_data_delay(host, i); 2078 ret = mmc_send_tuning(mmc, opcode, NULL); 2079 if (!ret) 2080 fall_delay |= (1 << i); 2081 } 2082 final_fall_delay = get_best_delay(host, fall_delay); 2083 2084 skip_fall: 2085 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2086 if (final_maxlen == final_rise_delay.maxlen) { 2087 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2088 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2089 final_delay = final_rise_delay.final_phase; 2090 } else { 2091 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2092 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2093 final_delay = final_fall_delay.final_phase; 2094 } 2095 msdc_set_data_delay(host, final_delay); 2096 2097 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 2098 return final_delay == 0xff ? -EIO : 0; 2099 } 2100 2101 /* 2102 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune 2103 * together, which can save the tuning time. 2104 */ 2105 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode) 2106 { 2107 struct msdc_host *host = mmc_priv(mmc); 2108 u32 rise_delay = 0, fall_delay = 0; 2109 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2110 u8 final_delay, final_maxlen; 2111 int i, ret; 2112 2113 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2114 host->latch_ck); 2115 2116 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2117 sdr_clr_bits(host->base + MSDC_IOCON, 2118 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2119 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2120 msdc_set_cmd_delay(host, i); 2121 msdc_set_data_delay(host, i); 2122 ret = mmc_send_tuning(mmc, opcode, NULL); 2123 if (!ret) 2124 rise_delay |= (1 << i); 2125 } 2126 final_rise_delay = get_best_delay(host, rise_delay); 2127 /* if rising edge has enough margin, then do not scan falling edge */ 2128 if (final_rise_delay.maxlen >= 12 || 2129 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2130 goto skip_fall; 2131 2132 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2133 sdr_set_bits(host->base + MSDC_IOCON, 2134 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2135 for (i = 0; i < PAD_DELAY_MAX; i++) { 2136 msdc_set_cmd_delay(host, i); 2137 msdc_set_data_delay(host, i); 2138 ret = mmc_send_tuning(mmc, opcode, NULL); 2139 if (!ret) 2140 fall_delay |= (1 << i); 2141 } 2142 final_fall_delay = get_best_delay(host, fall_delay); 2143 2144 skip_fall: 2145 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2146 if (final_maxlen == final_rise_delay.maxlen) { 2147 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2148 sdr_clr_bits(host->base + MSDC_IOCON, 2149 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2150 final_delay = final_rise_delay.final_phase; 2151 } else { 2152 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2153 sdr_set_bits(host->base + MSDC_IOCON, 2154 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2155 final_delay = final_fall_delay.final_phase; 2156 } 2157 2158 msdc_set_cmd_delay(host, final_delay); 2159 msdc_set_data_delay(host, final_delay); 2160 2161 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); 2162 return final_delay == 0xff ? -EIO : 0; 2163 } 2164 2165 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 2166 { 2167 struct msdc_host *host = mmc_priv(mmc); 2168 int ret; 2169 u32 tune_reg = host->dev_comp->pad_tune_reg; 2170 2171 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { 2172 ret = msdc_tune_together(mmc, opcode); 2173 if (host->hs400_mode) { 2174 sdr_clr_bits(host->base + MSDC_IOCON, 2175 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2176 msdc_set_data_delay(host, 0); 2177 } 2178 goto tune_done; 2179 } 2180 if (host->hs400_mode && 2181 host->dev_comp->hs400_tune) 2182 ret = hs400_tune_response(mmc, opcode); 2183 else 2184 ret = msdc_tune_response(mmc, opcode); 2185 if (ret == -EIO) { 2186 dev_err(host->dev, "Tune response fail!\n"); 2187 return ret; 2188 } 2189 if (host->hs400_mode == false) { 2190 ret = msdc_tune_data(mmc, opcode); 2191 if (ret == -EIO) 2192 dev_err(host->dev, "Tune data fail!\n"); 2193 } 2194 2195 tune_done: 2196 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 2197 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 2198 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2199 if (host->top_base) { 2200 host->saved_tune_para.emmc_top_control = readl(host->top_base + 2201 EMMC_TOP_CONTROL); 2202 host->saved_tune_para.emmc_top_cmd = readl(host->top_base + 2203 EMMC_TOP_CMD); 2204 } 2205 return ret; 2206 } 2207 2208 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 2209 { 2210 struct msdc_host *host = mmc_priv(mmc); 2211 host->hs400_mode = true; 2212 2213 if (host->top_base) 2214 writel(host->hs400_ds_delay, 2215 host->top_base + EMMC50_PAD_DS_TUNE); 2216 else 2217 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 2218 /* hs400 mode must set it to 0 */ 2219 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); 2220 /* to improve read performance, set outstanding to 2 */ 2221 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); 2222 2223 return 0; 2224 } 2225 2226 static void msdc_hw_reset(struct mmc_host *mmc) 2227 { 2228 struct msdc_host *host = mmc_priv(mmc); 2229 2230 sdr_set_bits(host->base + EMMC_IOCON, 1); 2231 udelay(10); /* 10us is enough */ 2232 sdr_clr_bits(host->base + EMMC_IOCON, 1); 2233 } 2234 2235 static void msdc_ack_sdio_irq(struct mmc_host *mmc) 2236 { 2237 unsigned long flags; 2238 struct msdc_host *host = mmc_priv(mmc); 2239 2240 spin_lock_irqsave(&host->lock, flags); 2241 __msdc_enable_sdio_irq(host, 1); 2242 spin_unlock_irqrestore(&host->lock, flags); 2243 } 2244 2245 static int msdc_get_cd(struct mmc_host *mmc) 2246 { 2247 struct msdc_host *host = mmc_priv(mmc); 2248 int val; 2249 2250 if (mmc->caps & MMC_CAP_NONREMOVABLE) 2251 return 1; 2252 2253 if (!host->internal_cd) 2254 return mmc_gpio_get_cd(mmc); 2255 2256 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; 2257 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) 2258 return !!val; 2259 else 2260 return !val; 2261 } 2262 2263 static void msdc_cqe_enable(struct mmc_host *mmc) 2264 { 2265 struct msdc_host *host = mmc_priv(mmc); 2266 2267 /* enable cmdq irq */ 2268 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); 2269 /* enable busy check */ 2270 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 2271 /* default write data / busy timeout 20s */ 2272 msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); 2273 /* default read data timeout 1s */ 2274 msdc_set_timeout(host, 1000000000ULL, 0); 2275 } 2276 2277 static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) 2278 { 2279 struct msdc_host *host = mmc_priv(mmc); 2280 2281 /* disable cmdq irq */ 2282 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); 2283 /* disable busy check */ 2284 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 2285 2286 if (recovery) { 2287 sdr_set_field(host->base + MSDC_DMA_CTRL, 2288 MSDC_DMA_CTRL_STOP, 1); 2289 msdc_reset_hw(host); 2290 } 2291 } 2292 2293 static const struct mmc_host_ops mt_msdc_ops = { 2294 .post_req = msdc_post_req, 2295 .pre_req = msdc_pre_req, 2296 .request = msdc_ops_request, 2297 .set_ios = msdc_ops_set_ios, 2298 .get_ro = mmc_gpio_get_ro, 2299 .get_cd = msdc_get_cd, 2300 .enable_sdio_irq = msdc_enable_sdio_irq, 2301 .ack_sdio_irq = msdc_ack_sdio_irq, 2302 .start_signal_voltage_switch = msdc_ops_switch_volt, 2303 .card_busy = msdc_card_busy, 2304 .execute_tuning = msdc_execute_tuning, 2305 .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 2306 .hw_reset = msdc_hw_reset, 2307 }; 2308 2309 static const struct cqhci_host_ops msdc_cmdq_ops = { 2310 .enable = msdc_cqe_enable, 2311 .disable = msdc_cqe_disable, 2312 }; 2313 2314 static void msdc_of_property_parse(struct platform_device *pdev, 2315 struct msdc_host *host) 2316 { 2317 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", 2318 &host->latch_ck); 2319 2320 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 2321 &host->hs400_ds_delay); 2322 2323 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 2324 &host->hs200_cmd_int_delay); 2325 2326 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 2327 &host->hs400_cmd_int_delay); 2328 2329 if (of_property_read_bool(pdev->dev.of_node, 2330 "mediatek,hs400-cmd-resp-sel-rising")) 2331 host->hs400_cmd_resp_sel_rising = true; 2332 else 2333 host->hs400_cmd_resp_sel_rising = false; 2334 2335 if (of_property_read_bool(pdev->dev.of_node, 2336 "supports-cqe")) 2337 host->cqhci = true; 2338 else 2339 host->cqhci = false; 2340 } 2341 2342 static int msdc_drv_probe(struct platform_device *pdev) 2343 { 2344 struct mmc_host *mmc; 2345 struct msdc_host *host; 2346 struct resource *res; 2347 int ret; 2348 2349 if (!pdev->dev.of_node) { 2350 dev_err(&pdev->dev, "No DT found\n"); 2351 return -EINVAL; 2352 } 2353 2354 /* Allocate MMC host for this device */ 2355 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 2356 if (!mmc) 2357 return -ENOMEM; 2358 2359 host = mmc_priv(mmc); 2360 ret = mmc_of_parse(mmc); 2361 if (ret) 2362 goto host_free; 2363 2364 host->base = devm_platform_ioremap_resource(pdev, 0); 2365 if (IS_ERR(host->base)) { 2366 ret = PTR_ERR(host->base); 2367 goto host_free; 2368 } 2369 2370 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2371 if (res) { 2372 host->top_base = devm_ioremap_resource(&pdev->dev, res); 2373 if (IS_ERR(host->top_base)) 2374 host->top_base = NULL; 2375 } 2376 2377 ret = mmc_regulator_get_supply(mmc); 2378 if (ret) 2379 goto host_free; 2380 2381 host->src_clk = devm_clk_get(&pdev->dev, "source"); 2382 if (IS_ERR(host->src_clk)) { 2383 ret = PTR_ERR(host->src_clk); 2384 goto host_free; 2385 } 2386 2387 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 2388 if (IS_ERR(host->h_clk)) { 2389 ret = PTR_ERR(host->h_clk); 2390 goto host_free; 2391 } 2392 2393 host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); 2394 if (IS_ERR(host->bus_clk)) 2395 host->bus_clk = NULL; 2396 /*source clock control gate is optional clock*/ 2397 host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg"); 2398 if (IS_ERR(host->src_clk_cg)) 2399 host->src_clk_cg = NULL; 2400 2401 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 2402 "hrst"); 2403 if (IS_ERR(host->reset)) 2404 return PTR_ERR(host->reset); 2405 2406 host->irq = platform_get_irq(pdev, 0); 2407 if (host->irq < 0) { 2408 ret = -EINVAL; 2409 goto host_free; 2410 } 2411 2412 host->pinctrl = devm_pinctrl_get(&pdev->dev); 2413 if (IS_ERR(host->pinctrl)) { 2414 ret = PTR_ERR(host->pinctrl); 2415 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 2416 goto host_free; 2417 } 2418 2419 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 2420 if (IS_ERR(host->pins_default)) { 2421 ret = PTR_ERR(host->pins_default); 2422 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 2423 goto host_free; 2424 } 2425 2426 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 2427 if (IS_ERR(host->pins_uhs)) { 2428 ret = PTR_ERR(host->pins_uhs); 2429 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 2430 goto host_free; 2431 } 2432 2433 msdc_of_property_parse(pdev, host); 2434 2435 host->dev = &pdev->dev; 2436 host->dev_comp = of_device_get_match_data(&pdev->dev); 2437 host->mmc = mmc; 2438 host->src_clk_freq = clk_get_rate(host->src_clk); 2439 /* Set host parameters to mmc */ 2440 mmc->ops = &mt_msdc_ops; 2441 if (host->dev_comp->clk_div_bits == 8) 2442 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 2443 else 2444 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); 2445 2446 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && 2447 !mmc_can_gpio_cd(mmc) && 2448 host->dev_comp->use_internal_cd) { 2449 /* 2450 * Is removable but no GPIO declared, so 2451 * use internal functionality. 2452 */ 2453 host->internal_cd = true; 2454 } 2455 2456 if (mmc->caps & MMC_CAP_SDIO_IRQ) 2457 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2458 2459 mmc->caps |= MMC_CAP_CMD23; 2460 if (host->cqhci) 2461 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 2462 /* MMC core transfer sizes tunable parameters */ 2463 mmc->max_segs = MAX_BD_NUM; 2464 if (host->dev_comp->support_64g) 2465 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; 2466 else 2467 mmc->max_seg_size = BDMA_DESC_BUFLEN; 2468 mmc->max_blk_size = 2048; 2469 mmc->max_req_size = 512 * 1024; 2470 mmc->max_blk_count = mmc->max_req_size / 512; 2471 if (host->dev_comp->support_64g) 2472 host->dma_mask = DMA_BIT_MASK(36); 2473 else 2474 host->dma_mask = DMA_BIT_MASK(32); 2475 mmc_dev(mmc)->dma_mask = &host->dma_mask; 2476 2477 if (mmc->caps2 & MMC_CAP2_CQE) { 2478 host->cq_host = devm_kzalloc(host->mmc->parent, 2479 sizeof(*host->cq_host), 2480 GFP_KERNEL); 2481 if (!host->cq_host) { 2482 ret = -ENOMEM; 2483 goto host_free; 2484 } 2485 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 2486 host->cq_host->mmio = host->base + 0x800; 2487 host->cq_host->ops = &msdc_cmdq_ops; 2488 ret = cqhci_init(host->cq_host, mmc, true); 2489 if (ret) 2490 goto host_free; 2491 mmc->max_segs = 128; 2492 /* cqhci 16bit length */ 2493 /* 0 size, means 65536 so we don't have to -1 here */ 2494 mmc->max_seg_size = 64 * 1024; 2495 } 2496 2497 host->timeout_clks = 3 * 1048576; 2498 host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2499 2 * sizeof(struct mt_gpdma_desc), 2500 &host->dma.gpd_addr, GFP_KERNEL); 2501 host->dma.bd = dma_alloc_coherent(&pdev->dev, 2502 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2503 &host->dma.bd_addr, GFP_KERNEL); 2504 if (!host->dma.gpd || !host->dma.bd) { 2505 ret = -ENOMEM; 2506 goto release_mem; 2507 } 2508 msdc_init_gpd_bd(host, &host->dma); 2509 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 2510 spin_lock_init(&host->lock); 2511 2512 platform_set_drvdata(pdev, mmc); 2513 msdc_ungate_clock(host); 2514 msdc_init_hw(host); 2515 2516 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 2517 IRQF_TRIGGER_NONE, pdev->name, host); 2518 if (ret) 2519 goto release; 2520 2521 pm_runtime_set_active(host->dev); 2522 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 2523 pm_runtime_use_autosuspend(host->dev); 2524 pm_runtime_enable(host->dev); 2525 ret = mmc_add_host(mmc); 2526 2527 if (ret) 2528 goto end; 2529 2530 return 0; 2531 end: 2532 pm_runtime_disable(host->dev); 2533 release: 2534 platform_set_drvdata(pdev, NULL); 2535 msdc_deinit_hw(host); 2536 msdc_gate_clock(host); 2537 release_mem: 2538 if (host->dma.gpd) 2539 dma_free_coherent(&pdev->dev, 2540 2 * sizeof(struct mt_gpdma_desc), 2541 host->dma.gpd, host->dma.gpd_addr); 2542 if (host->dma.bd) 2543 dma_free_coherent(&pdev->dev, 2544 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2545 host->dma.bd, host->dma.bd_addr); 2546 host_free: 2547 mmc_free_host(mmc); 2548 2549 return ret; 2550 } 2551 2552 static int msdc_drv_remove(struct platform_device *pdev) 2553 { 2554 struct mmc_host *mmc; 2555 struct msdc_host *host; 2556 2557 mmc = platform_get_drvdata(pdev); 2558 host = mmc_priv(mmc); 2559 2560 pm_runtime_get_sync(host->dev); 2561 2562 platform_set_drvdata(pdev, NULL); 2563 mmc_remove_host(host->mmc); 2564 msdc_deinit_hw(host); 2565 msdc_gate_clock(host); 2566 2567 pm_runtime_disable(host->dev); 2568 pm_runtime_put_noidle(host->dev); 2569 dma_free_coherent(&pdev->dev, 2570 2 * sizeof(struct mt_gpdma_desc), 2571 host->dma.gpd, host->dma.gpd_addr); 2572 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2573 host->dma.bd, host->dma.bd_addr); 2574 2575 mmc_free_host(host->mmc); 2576 2577 return 0; 2578 } 2579 2580 #ifdef CONFIG_PM 2581 static void msdc_save_reg(struct msdc_host *host) 2582 { 2583 u32 tune_reg = host->dev_comp->pad_tune_reg; 2584 2585 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 2586 host->save_para.iocon = readl(host->base + MSDC_IOCON); 2587 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 2588 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 2589 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 2590 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); 2591 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 2592 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2593 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 2594 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); 2595 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); 2596 if (host->top_base) { 2597 host->save_para.emmc_top_control = 2598 readl(host->top_base + EMMC_TOP_CONTROL); 2599 host->save_para.emmc_top_cmd = 2600 readl(host->top_base + EMMC_TOP_CMD); 2601 host->save_para.emmc50_pad_ds_tune = 2602 readl(host->top_base + EMMC50_PAD_DS_TUNE); 2603 } else { 2604 host->save_para.pad_tune = readl(host->base + tune_reg); 2605 } 2606 } 2607 2608 static void msdc_restore_reg(struct msdc_host *host) 2609 { 2610 u32 tune_reg = host->dev_comp->pad_tune_reg; 2611 2612 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 2613 writel(host->save_para.iocon, host->base + MSDC_IOCON); 2614 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 2615 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 2616 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 2617 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); 2618 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 2619 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 2620 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 2621 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); 2622 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); 2623 if (host->top_base) { 2624 writel(host->save_para.emmc_top_control, 2625 host->top_base + EMMC_TOP_CONTROL); 2626 writel(host->save_para.emmc_top_cmd, 2627 host->top_base + EMMC_TOP_CMD); 2628 writel(host->save_para.emmc50_pad_ds_tune, 2629 host->top_base + EMMC50_PAD_DS_TUNE); 2630 } else { 2631 writel(host->save_para.pad_tune, host->base + tune_reg); 2632 } 2633 2634 if (sdio_irq_claimed(host->mmc)) 2635 __msdc_enable_sdio_irq(host, 1); 2636 } 2637 2638 static int msdc_runtime_suspend(struct device *dev) 2639 { 2640 struct mmc_host *mmc = dev_get_drvdata(dev); 2641 struct msdc_host *host = mmc_priv(mmc); 2642 2643 msdc_save_reg(host); 2644 msdc_gate_clock(host); 2645 return 0; 2646 } 2647 2648 static int msdc_runtime_resume(struct device *dev) 2649 { 2650 struct mmc_host *mmc = dev_get_drvdata(dev); 2651 struct msdc_host *host = mmc_priv(mmc); 2652 2653 msdc_ungate_clock(host); 2654 msdc_restore_reg(host); 2655 return 0; 2656 } 2657 #endif 2658 2659 static const struct dev_pm_ops msdc_dev_pm_ops = { 2660 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2661 pm_runtime_force_resume) 2662 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 2663 }; 2664 2665 static struct platform_driver mt_msdc_driver = { 2666 .probe = msdc_drv_probe, 2667 .remove = msdc_drv_remove, 2668 .driver = { 2669 .name = "mtk-msdc", 2670 .of_match_table = msdc_of_ids, 2671 .pm = &msdc_dev_pm_ops, 2672 }, 2673 }; 2674 2675 module_platform_driver(mt_msdc_driver); 2676 MODULE_LICENSE("GPL v2"); 2677 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 2678