1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2015, 2022 MediaTek Inc. 4 * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 5 */ 6 7 #include <linux/module.h> 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/iopoll.h> 13 #include <linux/ioport.h> 14 #include <linux/irq.h> 15 #include <linux/of_address.h> 16 #include <linux/of_device.h> 17 #include <linux/of_irq.h> 18 #include <linux/of_gpio.h> 19 #include <linux/pinctrl/consumer.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/pm_wakeirq.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/slab.h> 26 #include <linux/spinlock.h> 27 #include <linux/interrupt.h> 28 #include <linux/reset.h> 29 30 #include <linux/mmc/card.h> 31 #include <linux/mmc/core.h> 32 #include <linux/mmc/host.h> 33 #include <linux/mmc/mmc.h> 34 #include <linux/mmc/sd.h> 35 #include <linux/mmc/sdio.h> 36 #include <linux/mmc/slot-gpio.h> 37 38 #include "cqhci.h" 39 40 #define MAX_BD_NUM 1024 41 #define MSDC_NR_CLOCKS 3 42 43 /*--------------------------------------------------------------------------*/ 44 /* Common Definition */ 45 /*--------------------------------------------------------------------------*/ 46 #define MSDC_BUS_1BITS 0x0 47 #define MSDC_BUS_4BITS 0x1 48 #define MSDC_BUS_8BITS 0x2 49 50 #define MSDC_BURST_64B 0x6 51 52 /*--------------------------------------------------------------------------*/ 53 /* Register Offset */ 54 /*--------------------------------------------------------------------------*/ 55 #define MSDC_CFG 0x0 56 #define MSDC_IOCON 0x04 57 #define MSDC_PS 0x08 58 #define MSDC_INT 0x0c 59 #define MSDC_INTEN 0x10 60 #define MSDC_FIFOCS 0x14 61 #define SDC_CFG 0x30 62 #define SDC_CMD 0x34 63 #define SDC_ARG 0x38 64 #define SDC_STS 0x3c 65 #define SDC_RESP0 0x40 66 #define SDC_RESP1 0x44 67 #define SDC_RESP2 0x48 68 #define SDC_RESP3 0x4c 69 #define SDC_BLK_NUM 0x50 70 #define SDC_ADV_CFG0 0x64 71 #define EMMC_IOCON 0x7c 72 #define SDC_ACMD_RESP 0x80 73 #define DMA_SA_H4BIT 0x8c 74 #define MSDC_DMA_SA 0x90 75 #define MSDC_DMA_CTRL 0x98 76 #define MSDC_DMA_CFG 0x9c 77 #define MSDC_PATCH_BIT 0xb0 78 #define MSDC_PATCH_BIT1 0xb4 79 #define MSDC_PATCH_BIT2 0xb8 80 #define MSDC_PAD_TUNE 0xec 81 #define MSDC_PAD_TUNE0 0xf0 82 #define PAD_DS_TUNE 0x188 83 #define PAD_CMD_TUNE 0x18c 84 #define EMMC51_CFG0 0x204 85 #define EMMC50_CFG0 0x208 86 #define EMMC50_CFG1 0x20c 87 #define EMMC50_CFG3 0x220 88 #define SDC_FIFO_CFG 0x228 89 #define CQHCI_SETTING 0x7fc 90 91 /*--------------------------------------------------------------------------*/ 92 /* Top Pad Register Offset */ 93 /*--------------------------------------------------------------------------*/ 94 #define EMMC_TOP_CONTROL 0x00 95 #define EMMC_TOP_CMD 0x04 96 #define EMMC50_PAD_DS_TUNE 0x0c 97 98 /*--------------------------------------------------------------------------*/ 99 /* Register Mask */ 100 /*--------------------------------------------------------------------------*/ 101 102 /* MSDC_CFG mask */ 103 #define MSDC_CFG_MODE BIT(0) /* RW */ 104 #define MSDC_CFG_CKPDN BIT(1) /* RW */ 105 #define MSDC_CFG_RST BIT(2) /* RW */ 106 #define MSDC_CFG_PIO BIT(3) /* RW */ 107 #define MSDC_CFG_CKDRVEN BIT(4) /* RW */ 108 #define MSDC_CFG_BV18SDT BIT(5) /* RW */ 109 #define MSDC_CFG_BV18PSS BIT(6) /* R */ 110 #define MSDC_CFG_CKSTB BIT(7) /* R */ 111 #define MSDC_CFG_CKDIV GENMASK(15, 8) /* RW */ 112 #define MSDC_CFG_CKMOD GENMASK(17, 16) /* RW */ 113 #define MSDC_CFG_HS400_CK_MODE BIT(18) /* RW */ 114 #define MSDC_CFG_HS400_CK_MODE_EXTRA BIT(22) /* RW */ 115 #define MSDC_CFG_CKDIV_EXTRA GENMASK(19, 8) /* RW */ 116 #define MSDC_CFG_CKMOD_EXTRA GENMASK(21, 20) /* RW */ 117 118 /* MSDC_IOCON mask */ 119 #define MSDC_IOCON_SDR104CKS BIT(0) /* RW */ 120 #define MSDC_IOCON_RSPL BIT(1) /* RW */ 121 #define MSDC_IOCON_DSPL BIT(2) /* RW */ 122 #define MSDC_IOCON_DDLSEL BIT(3) /* RW */ 123 #define MSDC_IOCON_DDR50CKD BIT(4) /* RW */ 124 #define MSDC_IOCON_DSPLSEL BIT(5) /* RW */ 125 #define MSDC_IOCON_W_DSPL BIT(8) /* RW */ 126 #define MSDC_IOCON_D0SPL BIT(16) /* RW */ 127 #define MSDC_IOCON_D1SPL BIT(17) /* RW */ 128 #define MSDC_IOCON_D2SPL BIT(18) /* RW */ 129 #define MSDC_IOCON_D3SPL BIT(19) /* RW */ 130 #define MSDC_IOCON_D4SPL BIT(20) /* RW */ 131 #define MSDC_IOCON_D5SPL BIT(21) /* RW */ 132 #define MSDC_IOCON_D6SPL BIT(22) /* RW */ 133 #define MSDC_IOCON_D7SPL BIT(23) /* RW */ 134 #define MSDC_IOCON_RISCSZ GENMASK(25, 24) /* RW */ 135 136 /* MSDC_PS mask */ 137 #define MSDC_PS_CDEN BIT(0) /* RW */ 138 #define MSDC_PS_CDSTS BIT(1) /* R */ 139 #define MSDC_PS_CDDEBOUNCE GENMASK(15, 12) /* RW */ 140 #define MSDC_PS_DAT GENMASK(23, 16) /* R */ 141 #define MSDC_PS_DATA1 BIT(17) /* R */ 142 #define MSDC_PS_CMD BIT(24) /* R */ 143 #define MSDC_PS_WP BIT(31) /* R */ 144 145 /* MSDC_INT mask */ 146 #define MSDC_INT_MMCIRQ BIT(0) /* W1C */ 147 #define MSDC_INT_CDSC BIT(1) /* W1C */ 148 #define MSDC_INT_ACMDRDY BIT(3) /* W1C */ 149 #define MSDC_INT_ACMDTMO BIT(4) /* W1C */ 150 #define MSDC_INT_ACMDCRCERR BIT(5) /* W1C */ 151 #define MSDC_INT_DMAQ_EMPTY BIT(6) /* W1C */ 152 #define MSDC_INT_SDIOIRQ BIT(7) /* W1C */ 153 #define MSDC_INT_CMDRDY BIT(8) /* W1C */ 154 #define MSDC_INT_CMDTMO BIT(9) /* W1C */ 155 #define MSDC_INT_RSPCRCERR BIT(10) /* W1C */ 156 #define MSDC_INT_CSTA BIT(11) /* R */ 157 #define MSDC_INT_XFER_COMPL BIT(12) /* W1C */ 158 #define MSDC_INT_DXFER_DONE BIT(13) /* W1C */ 159 #define MSDC_INT_DATTMO BIT(14) /* W1C */ 160 #define MSDC_INT_DATCRCERR BIT(15) /* W1C */ 161 #define MSDC_INT_ACMD19_DONE BIT(16) /* W1C */ 162 #define MSDC_INT_DMA_BDCSERR BIT(17) /* W1C */ 163 #define MSDC_INT_DMA_GPDCSERR BIT(18) /* W1C */ 164 #define MSDC_INT_DMA_PROTECT BIT(19) /* W1C */ 165 #define MSDC_INT_CMDQ BIT(28) /* W1C */ 166 167 /* MSDC_INTEN mask */ 168 #define MSDC_INTEN_MMCIRQ BIT(0) /* RW */ 169 #define MSDC_INTEN_CDSC BIT(1) /* RW */ 170 #define MSDC_INTEN_ACMDRDY BIT(3) /* RW */ 171 #define MSDC_INTEN_ACMDTMO BIT(4) /* RW */ 172 #define MSDC_INTEN_ACMDCRCERR BIT(5) /* RW */ 173 #define MSDC_INTEN_DMAQ_EMPTY BIT(6) /* RW */ 174 #define MSDC_INTEN_SDIOIRQ BIT(7) /* RW */ 175 #define MSDC_INTEN_CMDRDY BIT(8) /* RW */ 176 #define MSDC_INTEN_CMDTMO BIT(9) /* RW */ 177 #define MSDC_INTEN_RSPCRCERR BIT(10) /* RW */ 178 #define MSDC_INTEN_CSTA BIT(11) /* RW */ 179 #define MSDC_INTEN_XFER_COMPL BIT(12) /* RW */ 180 #define MSDC_INTEN_DXFER_DONE BIT(13) /* RW */ 181 #define MSDC_INTEN_DATTMO BIT(14) /* RW */ 182 #define MSDC_INTEN_DATCRCERR BIT(15) /* RW */ 183 #define MSDC_INTEN_ACMD19_DONE BIT(16) /* RW */ 184 #define MSDC_INTEN_DMA_BDCSERR BIT(17) /* RW */ 185 #define MSDC_INTEN_DMA_GPDCSERR BIT(18) /* RW */ 186 #define MSDC_INTEN_DMA_PROTECT BIT(19) /* RW */ 187 188 /* MSDC_FIFOCS mask */ 189 #define MSDC_FIFOCS_RXCNT GENMASK(7, 0) /* R */ 190 #define MSDC_FIFOCS_TXCNT GENMASK(23, 16) /* R */ 191 #define MSDC_FIFOCS_CLR BIT(31) /* RW */ 192 193 /* SDC_CFG mask */ 194 #define SDC_CFG_SDIOINTWKUP BIT(0) /* RW */ 195 #define SDC_CFG_INSWKUP BIT(1) /* RW */ 196 #define SDC_CFG_WRDTOC GENMASK(14, 2) /* RW */ 197 #define SDC_CFG_BUSWIDTH GENMASK(17, 16) /* RW */ 198 #define SDC_CFG_SDIO BIT(19) /* RW */ 199 #define SDC_CFG_SDIOIDE BIT(20) /* RW */ 200 #define SDC_CFG_INTATGAP BIT(21) /* RW */ 201 #define SDC_CFG_DTOC GENMASK(31, 24) /* RW */ 202 203 /* SDC_STS mask */ 204 #define SDC_STS_SDCBUSY BIT(0) /* RW */ 205 #define SDC_STS_CMDBUSY BIT(1) /* RW */ 206 #define SDC_STS_SWR_COMPL BIT(31) /* RW */ 207 208 #define SDC_DAT1_IRQ_TRIGGER BIT(19) /* RW */ 209 /* SDC_ADV_CFG0 mask */ 210 #define SDC_RX_ENHANCE_EN BIT(20) /* RW */ 211 212 /* DMA_SA_H4BIT mask */ 213 #define DMA_ADDR_HIGH_4BIT GENMASK(3, 0) /* RW */ 214 215 /* MSDC_DMA_CTRL mask */ 216 #define MSDC_DMA_CTRL_START BIT(0) /* W */ 217 #define MSDC_DMA_CTRL_STOP BIT(1) /* W */ 218 #define MSDC_DMA_CTRL_RESUME BIT(2) /* W */ 219 #define MSDC_DMA_CTRL_MODE BIT(8) /* RW */ 220 #define MSDC_DMA_CTRL_LASTBUF BIT(10) /* RW */ 221 #define MSDC_DMA_CTRL_BRUSTSZ GENMASK(14, 12) /* RW */ 222 223 /* MSDC_DMA_CFG mask */ 224 #define MSDC_DMA_CFG_STS BIT(0) /* R */ 225 #define MSDC_DMA_CFG_DECSEN BIT(1) /* RW */ 226 #define MSDC_DMA_CFG_AHBHPROT2 BIT(9) /* RW */ 227 #define MSDC_DMA_CFG_ACTIVEEN BIT(13) /* RW */ 228 #define MSDC_DMA_CFG_CS12B16B BIT(16) /* RW */ 229 230 /* MSDC_PATCH_BIT mask */ 231 #define MSDC_PATCH_BIT_ODDSUPP BIT(1) /* RW */ 232 #define MSDC_INT_DAT_LATCH_CK_SEL GENMASK(9, 7) 233 #define MSDC_CKGEN_MSDC_DLY_SEL GENMASK(14, 10) 234 #define MSDC_PATCH_BIT_IODSSEL BIT(16) /* RW */ 235 #define MSDC_PATCH_BIT_IOINTSEL BIT(17) /* RW */ 236 #define MSDC_PATCH_BIT_BUSYDLY GENMASK(21, 18) /* RW */ 237 #define MSDC_PATCH_BIT_WDOD GENMASK(25, 22) /* RW */ 238 #define MSDC_PATCH_BIT_IDRTSEL BIT(26) /* RW */ 239 #define MSDC_PATCH_BIT_CMDFSEL BIT(27) /* RW */ 240 #define MSDC_PATCH_BIT_INTDLSEL BIT(28) /* RW */ 241 #define MSDC_PATCH_BIT_SPCPUSH BIT(29) /* RW */ 242 #define MSDC_PATCH_BIT_DECRCTMO BIT(30) /* RW */ 243 244 #define MSDC_PATCH_BIT1_CMDTA GENMASK(5, 3) /* RW */ 245 #define MSDC_PB1_BUSY_CHECK_SEL BIT(7) /* RW */ 246 #define MSDC_PATCH_BIT1_STOP_DLY GENMASK(11, 8) /* RW */ 247 248 #define MSDC_PATCH_BIT2_CFGRESP BIT(15) /* RW */ 249 #define MSDC_PATCH_BIT2_CFGCRCSTS BIT(28) /* RW */ 250 #define MSDC_PB2_SUPPORT_64G BIT(1) /* RW */ 251 #define MSDC_PB2_RESPWAIT GENMASK(3, 2) /* RW */ 252 #define MSDC_PB2_RESPSTSENSEL GENMASK(18, 16) /* RW */ 253 #define MSDC_PB2_CRCSTSENSEL GENMASK(31, 29) /* RW */ 254 255 #define MSDC_PAD_TUNE_DATWRDLY GENMASK(4, 0) /* RW */ 256 #define MSDC_PAD_TUNE_DATRRDLY GENMASK(12, 8) /* RW */ 257 #define MSDC_PAD_TUNE_CMDRDLY GENMASK(20, 16) /* RW */ 258 #define MSDC_PAD_TUNE_CMDRRDLY GENMASK(26, 22) /* RW */ 259 #define MSDC_PAD_TUNE_CLKTDLY GENMASK(31, 27) /* RW */ 260 #define MSDC_PAD_TUNE_RXDLYSEL BIT(15) /* RW */ 261 #define MSDC_PAD_TUNE_RD_SEL BIT(13) /* RW */ 262 #define MSDC_PAD_TUNE_CMD_SEL BIT(21) /* RW */ 263 264 #define PAD_DS_TUNE_DLY_SEL BIT(0) /* RW */ 265 #define PAD_DS_TUNE_DLY1 GENMASK(6, 2) /* RW */ 266 #define PAD_DS_TUNE_DLY2 GENMASK(11, 7) /* RW */ 267 #define PAD_DS_TUNE_DLY3 GENMASK(16, 12) /* RW */ 268 269 #define PAD_CMD_TUNE_RX_DLY3 GENMASK(5, 1) /* RW */ 270 271 /* EMMC51_CFG0 mask */ 272 #define CMDQ_RDAT_CNT GENMASK(21, 12) /* RW */ 273 274 #define EMMC50_CFG_PADCMD_LATCHCK BIT(0) /* RW */ 275 #define EMMC50_CFG_CRCSTS_EDGE BIT(3) /* RW */ 276 #define EMMC50_CFG_CFCSTS_SEL BIT(4) /* RW */ 277 #define EMMC50_CFG_CMD_RESP_SEL BIT(9) /* RW */ 278 279 /* EMMC50_CFG1 mask */ 280 #define EMMC50_CFG1_DS_CFG BIT(28) /* RW */ 281 282 #define EMMC50_CFG3_OUTS_WR GENMASK(4, 0) /* RW */ 283 284 #define SDC_FIFO_CFG_WRVALIDSEL BIT(24) /* RW */ 285 #define SDC_FIFO_CFG_RDVALIDSEL BIT(25) /* RW */ 286 287 /* CQHCI_SETTING */ 288 #define CQHCI_RD_CMD_WND_SEL BIT(14) /* RW */ 289 #define CQHCI_WR_CMD_WND_SEL BIT(15) /* RW */ 290 291 /* EMMC_TOP_CONTROL mask */ 292 #define PAD_RXDLY_SEL BIT(0) /* RW */ 293 #define DELAY_EN BIT(1) /* RW */ 294 #define PAD_DAT_RD_RXDLY2 GENMASK(6, 2) /* RW */ 295 #define PAD_DAT_RD_RXDLY GENMASK(11, 7) /* RW */ 296 #define PAD_DAT_RD_RXDLY2_SEL BIT(12) /* RW */ 297 #define PAD_DAT_RD_RXDLY_SEL BIT(13) /* RW */ 298 #define DATA_K_VALUE_SEL BIT(14) /* RW */ 299 #define SDC_RX_ENH_EN BIT(15) /* TW */ 300 301 /* EMMC_TOP_CMD mask */ 302 #define PAD_CMD_RXDLY2 GENMASK(4, 0) /* RW */ 303 #define PAD_CMD_RXDLY GENMASK(9, 5) /* RW */ 304 #define PAD_CMD_RD_RXDLY2_SEL BIT(10) /* RW */ 305 #define PAD_CMD_RD_RXDLY_SEL BIT(11) /* RW */ 306 #define PAD_CMD_TX_DLY GENMASK(16, 12) /* RW */ 307 308 /* EMMC50_PAD_DS_TUNE mask */ 309 #define PAD_DS_DLY_SEL BIT(16) /* RW */ 310 #define PAD_DS_DLY1 GENMASK(14, 10) /* RW */ 311 #define PAD_DS_DLY3 GENMASK(4, 0) /* RW */ 312 313 #define REQ_CMD_EIO BIT(0) 314 #define REQ_CMD_TMO BIT(1) 315 #define REQ_DAT_ERR BIT(2) 316 #define REQ_STOP_EIO BIT(3) 317 #define REQ_STOP_TMO BIT(4) 318 #define REQ_CMD_BUSY BIT(5) 319 320 #define MSDC_PREPARE_FLAG BIT(0) 321 #define MSDC_ASYNC_FLAG BIT(1) 322 #define MSDC_MMAP_FLAG BIT(2) 323 324 #define MTK_MMC_AUTOSUSPEND_DELAY 50 325 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 326 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 327 328 #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */ 329 330 #define PAD_DELAY_MAX 32 /* PAD delay cells */ 331 /*--------------------------------------------------------------------------*/ 332 /* Descriptor Structure */ 333 /*--------------------------------------------------------------------------*/ 334 struct mt_gpdma_desc { 335 u32 gpd_info; 336 #define GPDMA_DESC_HWO BIT(0) 337 #define GPDMA_DESC_BDP BIT(1) 338 #define GPDMA_DESC_CHECKSUM GENMASK(15, 8) 339 #define GPDMA_DESC_INT BIT(16) 340 #define GPDMA_DESC_NEXT_H4 GENMASK(27, 24) 341 #define GPDMA_DESC_PTR_H4 GENMASK(31, 28) 342 u32 next; 343 u32 ptr; 344 u32 gpd_data_len; 345 #define GPDMA_DESC_BUFLEN GENMASK(15, 0) 346 #define GPDMA_DESC_EXTLEN GENMASK(23, 16) 347 u32 arg; 348 u32 blknum; 349 u32 cmd; 350 }; 351 352 struct mt_bdma_desc { 353 u32 bd_info; 354 #define BDMA_DESC_EOL BIT(0) 355 #define BDMA_DESC_CHECKSUM GENMASK(15, 8) 356 #define BDMA_DESC_BLKPAD BIT(17) 357 #define BDMA_DESC_DWPAD BIT(18) 358 #define BDMA_DESC_NEXT_H4 GENMASK(27, 24) 359 #define BDMA_DESC_PTR_H4 GENMASK(31, 28) 360 u32 next; 361 u32 ptr; 362 u32 bd_data_len; 363 #define BDMA_DESC_BUFLEN GENMASK(15, 0) 364 #define BDMA_DESC_BUFLEN_EXT GENMASK(23, 0) 365 }; 366 367 struct msdc_dma { 368 struct scatterlist *sg; /* I/O scatter list */ 369 struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 370 struct mt_bdma_desc *bd; /* pointer to bd array */ 371 dma_addr_t gpd_addr; /* the physical address of gpd array */ 372 dma_addr_t bd_addr; /* the physical address of bd array */ 373 }; 374 375 struct msdc_save_para { 376 u32 msdc_cfg; 377 u32 iocon; 378 u32 sdc_cfg; 379 u32 pad_tune; 380 u32 patch_bit0; 381 u32 patch_bit1; 382 u32 patch_bit2; 383 u32 pad_ds_tune; 384 u32 pad_cmd_tune; 385 u32 emmc50_cfg0; 386 u32 emmc50_cfg3; 387 u32 sdc_fifo_cfg; 388 u32 emmc_top_control; 389 u32 emmc_top_cmd; 390 u32 emmc50_pad_ds_tune; 391 }; 392 393 struct mtk_mmc_compatible { 394 u8 clk_div_bits; 395 bool recheck_sdio_irq; 396 bool hs400_tune; /* only used for MT8173 */ 397 u32 pad_tune_reg; 398 bool async_fifo; 399 bool data_tune; 400 bool busy_check; 401 bool stop_clk_fix; 402 bool enhance_rx; 403 bool support_64g; 404 bool use_internal_cd; 405 }; 406 407 struct msdc_tune_para { 408 u32 iocon; 409 u32 pad_tune; 410 u32 pad_cmd_tune; 411 u32 emmc_top_control; 412 u32 emmc_top_cmd; 413 }; 414 415 struct msdc_delay_phase { 416 u8 maxlen; 417 u8 start; 418 u8 final_phase; 419 }; 420 421 struct msdc_host { 422 struct device *dev; 423 const struct mtk_mmc_compatible *dev_comp; 424 int cmd_rsp; 425 426 spinlock_t lock; 427 struct mmc_request *mrq; 428 struct mmc_command *cmd; 429 struct mmc_data *data; 430 int error; 431 432 void __iomem *base; /* host base address */ 433 void __iomem *top_base; /* host top register base address */ 434 435 struct msdc_dma dma; /* dma channel */ 436 u64 dma_mask; 437 438 u32 timeout_ns; /* data timeout ns */ 439 u32 timeout_clks; /* data timeout clks */ 440 441 struct pinctrl *pinctrl; 442 struct pinctrl_state *pins_default; 443 struct pinctrl_state *pins_uhs; 444 struct pinctrl_state *pins_eint; 445 struct delayed_work req_timeout; 446 int irq; /* host interrupt */ 447 int eint_irq; /* interrupt from sdio device for waking up system */ 448 struct reset_control *reset; 449 450 struct clk *src_clk; /* msdc source clock */ 451 struct clk *h_clk; /* msdc h_clk */ 452 struct clk *bus_clk; /* bus clock which used to access register */ 453 struct clk *src_clk_cg; /* msdc source clock control gate */ 454 struct clk *sys_clk_cg; /* msdc subsys clock control gate */ 455 struct clk *crypto_clk; /* msdc crypto clock control gate */ 456 struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS]; 457 u32 mclk; /* mmc subsystem clock frequency */ 458 u32 src_clk_freq; /* source clock frequency */ 459 unsigned char timing; 460 bool vqmmc_enabled; 461 u32 latch_ck; 462 u32 hs400_ds_delay; 463 u32 hs400_ds_dly3; 464 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 465 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 466 bool hs400_cmd_resp_sel_rising; 467 /* cmd response sample selection for HS400 */ 468 bool hs400_mode; /* current eMMC will run at hs400 mode */ 469 bool hs400_tuning; /* hs400 mode online tuning */ 470 bool internal_cd; /* Use internal card-detect logic */ 471 bool cqhci; /* support eMMC hw cmdq */ 472 struct msdc_save_para save_para; /* used when gate HCLK */ 473 struct msdc_tune_para def_tune_para; /* default tune setting */ 474 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 475 struct cqhci_host *cq_host; 476 u32 cq_ssc1_time; 477 }; 478 479 static const struct mtk_mmc_compatible mt2701_compat = { 480 .clk_div_bits = 12, 481 .recheck_sdio_irq = true, 482 .hs400_tune = false, 483 .pad_tune_reg = MSDC_PAD_TUNE0, 484 .async_fifo = true, 485 .data_tune = true, 486 .busy_check = false, 487 .stop_clk_fix = false, 488 .enhance_rx = false, 489 .support_64g = false, 490 }; 491 492 static const struct mtk_mmc_compatible mt2712_compat = { 493 .clk_div_bits = 12, 494 .recheck_sdio_irq = false, 495 .hs400_tune = false, 496 .pad_tune_reg = MSDC_PAD_TUNE0, 497 .async_fifo = true, 498 .data_tune = true, 499 .busy_check = true, 500 .stop_clk_fix = true, 501 .enhance_rx = true, 502 .support_64g = true, 503 }; 504 505 static const struct mtk_mmc_compatible mt6779_compat = { 506 .clk_div_bits = 12, 507 .recheck_sdio_irq = false, 508 .hs400_tune = false, 509 .pad_tune_reg = MSDC_PAD_TUNE0, 510 .async_fifo = true, 511 .data_tune = true, 512 .busy_check = true, 513 .stop_clk_fix = true, 514 .enhance_rx = true, 515 .support_64g = true, 516 }; 517 518 static const struct mtk_mmc_compatible mt6795_compat = { 519 .clk_div_bits = 8, 520 .recheck_sdio_irq = false, 521 .hs400_tune = true, 522 .pad_tune_reg = MSDC_PAD_TUNE, 523 .async_fifo = false, 524 .data_tune = false, 525 .busy_check = false, 526 .stop_clk_fix = false, 527 .enhance_rx = false, 528 .support_64g = false, 529 }; 530 531 static const struct mtk_mmc_compatible mt7620_compat = { 532 .clk_div_bits = 8, 533 .recheck_sdio_irq = true, 534 .hs400_tune = false, 535 .pad_tune_reg = MSDC_PAD_TUNE, 536 .async_fifo = false, 537 .data_tune = false, 538 .busy_check = false, 539 .stop_clk_fix = false, 540 .enhance_rx = false, 541 .use_internal_cd = true, 542 }; 543 544 static const struct mtk_mmc_compatible mt7622_compat = { 545 .clk_div_bits = 12, 546 .recheck_sdio_irq = true, 547 .hs400_tune = false, 548 .pad_tune_reg = MSDC_PAD_TUNE0, 549 .async_fifo = true, 550 .data_tune = true, 551 .busy_check = true, 552 .stop_clk_fix = true, 553 .enhance_rx = true, 554 .support_64g = false, 555 }; 556 557 static const struct mtk_mmc_compatible mt7986_compat = { 558 .clk_div_bits = 12, 559 .recheck_sdio_irq = true, 560 .hs400_tune = false, 561 .pad_tune_reg = MSDC_PAD_TUNE0, 562 .async_fifo = true, 563 .data_tune = true, 564 .busy_check = true, 565 .stop_clk_fix = true, 566 .enhance_rx = true, 567 .support_64g = true, 568 }; 569 570 static const struct mtk_mmc_compatible mt8135_compat = { 571 .clk_div_bits = 8, 572 .recheck_sdio_irq = true, 573 .hs400_tune = false, 574 .pad_tune_reg = MSDC_PAD_TUNE, 575 .async_fifo = false, 576 .data_tune = false, 577 .busy_check = false, 578 .stop_clk_fix = false, 579 .enhance_rx = false, 580 .support_64g = false, 581 }; 582 583 static const struct mtk_mmc_compatible mt8173_compat = { 584 .clk_div_bits = 8, 585 .recheck_sdio_irq = true, 586 .hs400_tune = true, 587 .pad_tune_reg = MSDC_PAD_TUNE, 588 .async_fifo = false, 589 .data_tune = false, 590 .busy_check = false, 591 .stop_clk_fix = false, 592 .enhance_rx = false, 593 .support_64g = false, 594 }; 595 596 static const struct mtk_mmc_compatible mt8183_compat = { 597 .clk_div_bits = 12, 598 .recheck_sdio_irq = false, 599 .hs400_tune = false, 600 .pad_tune_reg = MSDC_PAD_TUNE0, 601 .async_fifo = true, 602 .data_tune = true, 603 .busy_check = true, 604 .stop_clk_fix = true, 605 .enhance_rx = true, 606 .support_64g = true, 607 }; 608 609 static const struct mtk_mmc_compatible mt8516_compat = { 610 .clk_div_bits = 12, 611 .recheck_sdio_irq = true, 612 .hs400_tune = false, 613 .pad_tune_reg = MSDC_PAD_TUNE0, 614 .async_fifo = true, 615 .data_tune = true, 616 .busy_check = true, 617 .stop_clk_fix = true, 618 }; 619 620 static const struct of_device_id msdc_of_ids[] = { 621 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, 622 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, 623 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, 624 { .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat}, 625 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, 626 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, 627 { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat}, 628 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, 629 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, 630 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, 631 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, 632 633 {} 634 }; 635 MODULE_DEVICE_TABLE(of, msdc_of_ids); 636 637 static void sdr_set_bits(void __iomem *reg, u32 bs) 638 { 639 u32 val = readl(reg); 640 641 val |= bs; 642 writel(val, reg); 643 } 644 645 static void sdr_clr_bits(void __iomem *reg, u32 bs) 646 { 647 u32 val = readl(reg); 648 649 val &= ~bs; 650 writel(val, reg); 651 } 652 653 static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 654 { 655 unsigned int tv = readl(reg); 656 657 tv &= ~field; 658 tv |= ((val) << (ffs((unsigned int)field) - 1)); 659 writel(tv, reg); 660 } 661 662 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 663 { 664 unsigned int tv = readl(reg); 665 666 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 667 } 668 669 static void msdc_reset_hw(struct msdc_host *host) 670 { 671 u32 val; 672 673 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 674 readl_poll_timeout(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0); 675 676 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 677 readl_poll_timeout(host->base + MSDC_FIFOCS, val, 678 !(val & MSDC_FIFOCS_CLR), 0, 0); 679 680 val = readl(host->base + MSDC_INT); 681 writel(val, host->base + MSDC_INT); 682 } 683 684 static void msdc_cmd_next(struct msdc_host *host, 685 struct mmc_request *mrq, struct mmc_command *cmd); 686 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb); 687 688 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 689 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 690 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 691 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 692 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 693 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 694 695 static u8 msdc_dma_calcs(u8 *buf, u32 len) 696 { 697 u32 i, sum = 0; 698 699 for (i = 0; i < len; i++) 700 sum += buf[i]; 701 return 0xff - (u8) sum; 702 } 703 704 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 705 struct mmc_data *data) 706 { 707 unsigned int j, dma_len; 708 dma_addr_t dma_address; 709 u32 dma_ctrl; 710 struct scatterlist *sg; 711 struct mt_gpdma_desc *gpd; 712 struct mt_bdma_desc *bd; 713 714 sg = data->sg; 715 716 gpd = dma->gpd; 717 bd = dma->bd; 718 719 /* modify gpd */ 720 gpd->gpd_info |= GPDMA_DESC_HWO; 721 gpd->gpd_info |= GPDMA_DESC_BDP; 722 /* need to clear first. use these bits to calc checksum */ 723 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 724 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 725 726 /* modify bd */ 727 for_each_sg(data->sg, sg, data->sg_count, j) { 728 dma_address = sg_dma_address(sg); 729 dma_len = sg_dma_len(sg); 730 731 /* init bd */ 732 bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 733 bd[j].bd_info &= ~BDMA_DESC_DWPAD; 734 bd[j].ptr = lower_32_bits(dma_address); 735 if (host->dev_comp->support_64g) { 736 bd[j].bd_info &= ~BDMA_DESC_PTR_H4; 737 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf) 738 << 28; 739 } 740 741 if (host->dev_comp->support_64g) { 742 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT; 743 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT); 744 } else { 745 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 746 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 747 } 748 749 if (j == data->sg_count - 1) /* the last bd */ 750 bd[j].bd_info |= BDMA_DESC_EOL; 751 else 752 bd[j].bd_info &= ~BDMA_DESC_EOL; 753 754 /* checksum need to clear first */ 755 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 756 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 757 } 758 759 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 760 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 761 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 762 dma_ctrl |= (MSDC_BURST_64B << 12 | BIT(8)); 763 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 764 if (host->dev_comp->support_64g) 765 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, 766 upper_32_bits(dma->gpd_addr) & 0xf); 767 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); 768 } 769 770 static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data) 771 { 772 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 773 data->host_cookie |= MSDC_PREPARE_FLAG; 774 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 775 mmc_get_dma_dir(data)); 776 } 777 } 778 779 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data) 780 { 781 if (data->host_cookie & MSDC_ASYNC_FLAG) 782 return; 783 784 if (data->host_cookie & MSDC_PREPARE_FLAG) { 785 dma_unmap_sg(host->dev, data->sg, data->sg_len, 786 mmc_get_dma_dir(data)); 787 data->host_cookie &= ~MSDC_PREPARE_FLAG; 788 } 789 } 790 791 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) 792 { 793 struct mmc_host *mmc = mmc_from_priv(host); 794 u64 timeout, clk_ns; 795 u32 mode = 0; 796 797 if (mmc->actual_clock == 0) { 798 timeout = 0; 799 } else { 800 clk_ns = 1000000000ULL; 801 do_div(clk_ns, mmc->actual_clock); 802 timeout = ns + clk_ns - 1; 803 do_div(timeout, clk_ns); 804 timeout += clks; 805 /* in 1048576 sclk cycle unit */ 806 timeout = DIV_ROUND_UP(timeout, BIT(20)); 807 if (host->dev_comp->clk_div_bits == 8) 808 sdr_get_field(host->base + MSDC_CFG, 809 MSDC_CFG_CKMOD, &mode); 810 else 811 sdr_get_field(host->base + MSDC_CFG, 812 MSDC_CFG_CKMOD_EXTRA, &mode); 813 /*DDR mode will double the clk cycles for data timeout */ 814 timeout = mode >= 2 ? timeout * 2 : timeout; 815 timeout = timeout > 1 ? timeout - 1 : 0; 816 } 817 return timeout; 818 } 819 820 /* clock control primitives */ 821 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) 822 { 823 u64 timeout; 824 825 host->timeout_ns = ns; 826 host->timeout_clks = clks; 827 828 timeout = msdc_timeout_cal(host, ns, clks); 829 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 830 (u32)(timeout > 255 ? 255 : timeout)); 831 } 832 833 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) 834 { 835 u64 timeout; 836 837 timeout = msdc_timeout_cal(host, ns, clks); 838 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, 839 (u32)(timeout > 8191 ? 8191 : timeout)); 840 } 841 842 static void msdc_gate_clock(struct msdc_host *host) 843 { 844 clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); 845 clk_disable_unprepare(host->crypto_clk); 846 clk_disable_unprepare(host->src_clk_cg); 847 clk_disable_unprepare(host->src_clk); 848 clk_disable_unprepare(host->bus_clk); 849 clk_disable_unprepare(host->h_clk); 850 } 851 852 static int msdc_ungate_clock(struct msdc_host *host) 853 { 854 u32 val; 855 int ret; 856 857 clk_prepare_enable(host->h_clk); 858 clk_prepare_enable(host->bus_clk); 859 clk_prepare_enable(host->src_clk); 860 clk_prepare_enable(host->src_clk_cg); 861 clk_prepare_enable(host->crypto_clk); 862 ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); 863 if (ret) { 864 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); 865 return ret; 866 } 867 868 return readl_poll_timeout(host->base + MSDC_CFG, val, 869 (val & MSDC_CFG_CKSTB), 1, 20000); 870 } 871 872 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 873 { 874 struct mmc_host *mmc = mmc_from_priv(host); 875 u32 mode; 876 u32 flags; 877 u32 div; 878 u32 sclk; 879 u32 tune_reg = host->dev_comp->pad_tune_reg; 880 u32 val; 881 882 if (!hz) { 883 dev_dbg(host->dev, "set mclk to 0\n"); 884 host->mclk = 0; 885 mmc->actual_clock = 0; 886 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 887 return; 888 } 889 890 flags = readl(host->base + MSDC_INTEN); 891 sdr_clr_bits(host->base + MSDC_INTEN, flags); 892 if (host->dev_comp->clk_div_bits == 8) 893 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 894 else 895 sdr_clr_bits(host->base + MSDC_CFG, 896 MSDC_CFG_HS400_CK_MODE_EXTRA); 897 if (timing == MMC_TIMING_UHS_DDR50 || 898 timing == MMC_TIMING_MMC_DDR52 || 899 timing == MMC_TIMING_MMC_HS400) { 900 if (timing == MMC_TIMING_MMC_HS400) 901 mode = 0x3; 902 else 903 mode = 0x2; /* ddr mode and use divisor */ 904 905 if (hz >= (host->src_clk_freq >> 2)) { 906 div = 0; /* mean div = 1/4 */ 907 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 908 } else { 909 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 910 sclk = (host->src_clk_freq >> 2) / div; 911 div = (div >> 1); 912 } 913 914 if (timing == MMC_TIMING_MMC_HS400 && 915 hz >= (host->src_clk_freq >> 1)) { 916 if (host->dev_comp->clk_div_bits == 8) 917 sdr_set_bits(host->base + MSDC_CFG, 918 MSDC_CFG_HS400_CK_MODE); 919 else 920 sdr_set_bits(host->base + MSDC_CFG, 921 MSDC_CFG_HS400_CK_MODE_EXTRA); 922 sclk = host->src_clk_freq >> 1; 923 div = 0; /* div is ignore when bit18 is set */ 924 } 925 } else if (hz >= host->src_clk_freq) { 926 mode = 0x1; /* no divisor */ 927 div = 0; 928 sclk = host->src_clk_freq; 929 } else { 930 mode = 0x0; /* use divisor */ 931 if (hz >= (host->src_clk_freq >> 1)) { 932 div = 0; /* mean div = 1/2 */ 933 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 934 } else { 935 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 936 sclk = (host->src_clk_freq >> 2) / div; 937 } 938 } 939 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 940 941 clk_disable_unprepare(host->src_clk_cg); 942 if (host->dev_comp->clk_div_bits == 8) 943 sdr_set_field(host->base + MSDC_CFG, 944 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 945 (mode << 8) | div); 946 else 947 sdr_set_field(host->base + MSDC_CFG, 948 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, 949 (mode << 12) | div); 950 951 clk_prepare_enable(host->src_clk_cg); 952 readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0); 953 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 954 mmc->actual_clock = sclk; 955 host->mclk = hz; 956 host->timing = timing; 957 /* need because clk changed. */ 958 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 959 sdr_set_bits(host->base + MSDC_INTEN, flags); 960 961 /* 962 * mmc_select_hs400() will drop to 50Mhz and High speed mode, 963 * tune result of hs200/200Mhz is not suitable for 50Mhz 964 */ 965 if (mmc->actual_clock <= 52000000) { 966 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 967 if (host->top_base) { 968 writel(host->def_tune_para.emmc_top_control, 969 host->top_base + EMMC_TOP_CONTROL); 970 writel(host->def_tune_para.emmc_top_cmd, 971 host->top_base + EMMC_TOP_CMD); 972 } else { 973 writel(host->def_tune_para.pad_tune, 974 host->base + tune_reg); 975 } 976 } else { 977 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 978 writel(host->saved_tune_para.pad_cmd_tune, 979 host->base + PAD_CMD_TUNE); 980 if (host->top_base) { 981 writel(host->saved_tune_para.emmc_top_control, 982 host->top_base + EMMC_TOP_CONTROL); 983 writel(host->saved_tune_para.emmc_top_cmd, 984 host->top_base + EMMC_TOP_CMD); 985 } else { 986 writel(host->saved_tune_para.pad_tune, 987 host->base + tune_reg); 988 } 989 } 990 991 if (timing == MMC_TIMING_MMC_HS400 && 992 host->dev_comp->hs400_tune) 993 sdr_set_field(host->base + tune_reg, 994 MSDC_PAD_TUNE_CMDRRDLY, 995 host->hs400_cmd_int_delay); 996 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock, 997 timing); 998 } 999 1000 static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 1001 struct mmc_command *cmd) 1002 { 1003 u32 resp; 1004 1005 switch (mmc_resp_type(cmd)) { 1006 /* Actually, R1, R5, R6, R7 are the same */ 1007 case MMC_RSP_R1: 1008 resp = 0x1; 1009 break; 1010 case MMC_RSP_R1B: 1011 resp = 0x7; 1012 break; 1013 case MMC_RSP_R2: 1014 resp = 0x2; 1015 break; 1016 case MMC_RSP_R3: 1017 resp = 0x3; 1018 break; 1019 case MMC_RSP_NONE: 1020 default: 1021 resp = 0x0; 1022 break; 1023 } 1024 1025 return resp; 1026 } 1027 1028 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 1029 struct mmc_request *mrq, struct mmc_command *cmd) 1030 { 1031 struct mmc_host *mmc = mmc_from_priv(host); 1032 /* rawcmd : 1033 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 1034 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 1035 */ 1036 u32 opcode = cmd->opcode; 1037 u32 resp = msdc_cmd_find_resp(host, cmd); 1038 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 1039 1040 host->cmd_rsp = resp; 1041 1042 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 1043 opcode == MMC_STOP_TRANSMISSION) 1044 rawcmd |= BIT(14); 1045 else if (opcode == SD_SWITCH_VOLTAGE) 1046 rawcmd |= BIT(30); 1047 else if (opcode == SD_APP_SEND_SCR || 1048 opcode == SD_APP_SEND_NUM_WR_BLKS || 1049 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 1050 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 1051 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 1052 rawcmd |= BIT(11); 1053 1054 if (cmd->data) { 1055 struct mmc_data *data = cmd->data; 1056 1057 if (mmc_op_multi(opcode)) { 1058 if (mmc_card_mmc(mmc->card) && mrq->sbc && 1059 !(mrq->sbc->arg & 0xFFFF0000)) 1060 rawcmd |= BIT(29); /* AutoCMD23 */ 1061 } 1062 1063 rawcmd |= ((data->blksz & 0xFFF) << 16); 1064 if (data->flags & MMC_DATA_WRITE) 1065 rawcmd |= BIT(13); 1066 if (data->blocks > 1) 1067 rawcmd |= BIT(12); 1068 else 1069 rawcmd |= BIT(11); 1070 /* Always use dma mode */ 1071 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 1072 1073 if (host->timeout_ns != data->timeout_ns || 1074 host->timeout_clks != data->timeout_clks) 1075 msdc_set_timeout(host, data->timeout_ns, 1076 data->timeout_clks); 1077 1078 writel(data->blocks, host->base + SDC_BLK_NUM); 1079 } 1080 return rawcmd; 1081 } 1082 1083 static void msdc_start_data(struct msdc_host *host, struct mmc_command *cmd, 1084 struct mmc_data *data) 1085 { 1086 bool read; 1087 1088 WARN_ON(host->data); 1089 host->data = data; 1090 read = data->flags & MMC_DATA_READ; 1091 1092 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1093 msdc_dma_setup(host, &host->dma, data); 1094 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 1095 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 1096 dev_dbg(host->dev, "DMA start\n"); 1097 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 1098 __func__, cmd->opcode, data->blocks, read); 1099 } 1100 1101 static int msdc_auto_cmd_done(struct msdc_host *host, int events, 1102 struct mmc_command *cmd) 1103 { 1104 u32 *rsp = cmd->resp; 1105 1106 rsp[0] = readl(host->base + SDC_ACMD_RESP); 1107 1108 if (events & MSDC_INT_ACMDRDY) { 1109 cmd->error = 0; 1110 } else { 1111 msdc_reset_hw(host); 1112 if (events & MSDC_INT_ACMDCRCERR) { 1113 cmd->error = -EILSEQ; 1114 host->error |= REQ_STOP_EIO; 1115 } else if (events & MSDC_INT_ACMDTMO) { 1116 cmd->error = -ETIMEDOUT; 1117 host->error |= REQ_STOP_TMO; 1118 } 1119 dev_err(host->dev, 1120 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 1121 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 1122 } 1123 return cmd->error; 1124 } 1125 1126 /* 1127 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost 1128 * 1129 * Host controller may lost interrupt in some special case. 1130 * Add SDIO irq recheck mechanism to make sure all interrupts 1131 * can be processed immediately 1132 */ 1133 static void msdc_recheck_sdio_irq(struct msdc_host *host) 1134 { 1135 struct mmc_host *mmc = mmc_from_priv(host); 1136 u32 reg_int, reg_inten, reg_ps; 1137 1138 if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1139 reg_inten = readl(host->base + MSDC_INTEN); 1140 if (reg_inten & MSDC_INTEN_SDIOIRQ) { 1141 reg_int = readl(host->base + MSDC_INT); 1142 reg_ps = readl(host->base + MSDC_PS); 1143 if (!(reg_int & MSDC_INT_SDIOIRQ || 1144 reg_ps & MSDC_PS_DATA1)) { 1145 __msdc_enable_sdio_irq(host, 0); 1146 sdio_signal_irq(mmc); 1147 } 1148 } 1149 } 1150 } 1151 1152 static void msdc_track_cmd_data(struct msdc_host *host, struct mmc_command *cmd) 1153 { 1154 if (host->error) 1155 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 1156 __func__, cmd->opcode, cmd->arg, host->error); 1157 } 1158 1159 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 1160 { 1161 unsigned long flags; 1162 1163 /* 1164 * No need check the return value of cancel_delayed_work, as only ONE 1165 * path will go here! 1166 */ 1167 cancel_delayed_work(&host->req_timeout); 1168 1169 spin_lock_irqsave(&host->lock, flags); 1170 host->mrq = NULL; 1171 spin_unlock_irqrestore(&host->lock, flags); 1172 1173 msdc_track_cmd_data(host, mrq->cmd); 1174 if (mrq->data) 1175 msdc_unprepare_data(host, mrq->data); 1176 if (host->error) 1177 msdc_reset_hw(host); 1178 mmc_request_done(mmc_from_priv(host), mrq); 1179 if (host->dev_comp->recheck_sdio_irq) 1180 msdc_recheck_sdio_irq(host); 1181 } 1182 1183 /* returns true if command is fully handled; returns false otherwise */ 1184 static bool msdc_cmd_done(struct msdc_host *host, int events, 1185 struct mmc_request *mrq, struct mmc_command *cmd) 1186 { 1187 bool done = false; 1188 bool sbc_error; 1189 unsigned long flags; 1190 u32 *rsp; 1191 1192 if (mrq->sbc && cmd == mrq->cmd && 1193 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 1194 | MSDC_INT_ACMDTMO))) 1195 msdc_auto_cmd_done(host, events, mrq->sbc); 1196 1197 sbc_error = mrq->sbc && mrq->sbc->error; 1198 1199 if (!sbc_error && !(events & (MSDC_INT_CMDRDY 1200 | MSDC_INT_RSPCRCERR 1201 | MSDC_INT_CMDTMO))) 1202 return done; 1203 1204 spin_lock_irqsave(&host->lock, flags); 1205 done = !host->cmd; 1206 host->cmd = NULL; 1207 spin_unlock_irqrestore(&host->lock, flags); 1208 1209 if (done) 1210 return true; 1211 rsp = cmd->resp; 1212 1213 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1214 1215 if (cmd->flags & MMC_RSP_PRESENT) { 1216 if (cmd->flags & MMC_RSP_136) { 1217 rsp[0] = readl(host->base + SDC_RESP3); 1218 rsp[1] = readl(host->base + SDC_RESP2); 1219 rsp[2] = readl(host->base + SDC_RESP1); 1220 rsp[3] = readl(host->base + SDC_RESP0); 1221 } else { 1222 rsp[0] = readl(host->base + SDC_RESP0); 1223 } 1224 } 1225 1226 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 1227 if (events & MSDC_INT_CMDTMO || 1228 (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning)) 1229 /* 1230 * should not clear fifo/interrupt as the tune data 1231 * may have already come when cmd19/cmd21 gets response 1232 * CRC error. 1233 */ 1234 msdc_reset_hw(host); 1235 if (events & MSDC_INT_RSPCRCERR) { 1236 cmd->error = -EILSEQ; 1237 host->error |= REQ_CMD_EIO; 1238 } else if (events & MSDC_INT_CMDTMO) { 1239 cmd->error = -ETIMEDOUT; 1240 host->error |= REQ_CMD_TMO; 1241 } 1242 } 1243 if (cmd->error) 1244 dev_dbg(host->dev, 1245 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 1246 __func__, cmd->opcode, cmd->arg, rsp[0], 1247 cmd->error); 1248 1249 msdc_cmd_next(host, mrq, cmd); 1250 return true; 1251 } 1252 1253 /* It is the core layer's responsibility to ensure card status 1254 * is correct before issue a request. but host design do below 1255 * checks recommended. 1256 */ 1257 static inline bool msdc_cmd_is_ready(struct msdc_host *host, 1258 struct mmc_request *mrq, struct mmc_command *cmd) 1259 { 1260 u32 val; 1261 int ret; 1262 1263 /* The max busy time we can endure is 20ms */ 1264 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, 1265 !(val & SDC_STS_CMDBUSY), 1, 20000); 1266 if (ret) { 1267 dev_err(host->dev, "CMD bus busy detected\n"); 1268 host->error |= REQ_CMD_BUSY; 1269 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1270 return false; 1271 } 1272 1273 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 1274 /* R1B or with data, should check SDCBUSY */ 1275 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, 1276 !(val & SDC_STS_SDCBUSY), 1, 20000); 1277 if (ret) { 1278 dev_err(host->dev, "Controller busy detected\n"); 1279 host->error |= REQ_CMD_BUSY; 1280 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1281 return false; 1282 } 1283 } 1284 return true; 1285 } 1286 1287 static void msdc_start_command(struct msdc_host *host, 1288 struct mmc_request *mrq, struct mmc_command *cmd) 1289 { 1290 u32 rawcmd; 1291 unsigned long flags; 1292 1293 WARN_ON(host->cmd); 1294 host->cmd = cmd; 1295 1296 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1297 if (!msdc_cmd_is_ready(host, mrq, cmd)) 1298 return; 1299 1300 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 1301 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 1302 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 1303 msdc_reset_hw(host); 1304 } 1305 1306 cmd->error = 0; 1307 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 1308 1309 spin_lock_irqsave(&host->lock, flags); 1310 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1311 spin_unlock_irqrestore(&host->lock, flags); 1312 1313 writel(cmd->arg, host->base + SDC_ARG); 1314 writel(rawcmd, host->base + SDC_CMD); 1315 } 1316 1317 static void msdc_cmd_next(struct msdc_host *host, 1318 struct mmc_request *mrq, struct mmc_command *cmd) 1319 { 1320 if ((cmd->error && 1321 !(cmd->error == -EILSEQ && 1322 (mmc_op_tuning(cmd->opcode) || host->hs400_tuning))) || 1323 (mrq->sbc && mrq->sbc->error)) 1324 msdc_request_done(host, mrq); 1325 else if (cmd == mrq->sbc) 1326 msdc_start_command(host, mrq, mrq->cmd); 1327 else if (!cmd->data) 1328 msdc_request_done(host, mrq); 1329 else 1330 msdc_start_data(host, cmd, cmd->data); 1331 } 1332 1333 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 1334 { 1335 struct msdc_host *host = mmc_priv(mmc); 1336 1337 host->error = 0; 1338 WARN_ON(host->mrq); 1339 host->mrq = mrq; 1340 1341 if (mrq->data) 1342 msdc_prepare_data(host, mrq->data); 1343 1344 /* if SBC is required, we have HW option and SW option. 1345 * if HW option is enabled, and SBC does not have "special" flags, 1346 * use HW option, otherwise use SW option 1347 */ 1348 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 1349 (mrq->sbc->arg & 0xFFFF0000))) 1350 msdc_start_command(host, mrq, mrq->sbc); 1351 else 1352 msdc_start_command(host, mrq, mrq->cmd); 1353 } 1354 1355 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 1356 { 1357 struct msdc_host *host = mmc_priv(mmc); 1358 struct mmc_data *data = mrq->data; 1359 1360 if (!data) 1361 return; 1362 1363 msdc_prepare_data(host, data); 1364 data->host_cookie |= MSDC_ASYNC_FLAG; 1365 } 1366 1367 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1368 int err) 1369 { 1370 struct msdc_host *host = mmc_priv(mmc); 1371 struct mmc_data *data = mrq->data; 1372 1373 if (!data) 1374 return; 1375 1376 if (data->host_cookie) { 1377 data->host_cookie &= ~MSDC_ASYNC_FLAG; 1378 msdc_unprepare_data(host, data); 1379 } 1380 } 1381 1382 static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq) 1383 { 1384 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 1385 !mrq->sbc) 1386 msdc_start_command(host, mrq, mrq->stop); 1387 else 1388 msdc_request_done(host, mrq); 1389 } 1390 1391 static void msdc_data_xfer_done(struct msdc_host *host, u32 events, 1392 struct mmc_request *mrq, struct mmc_data *data) 1393 { 1394 struct mmc_command *stop; 1395 unsigned long flags; 1396 bool done; 1397 unsigned int check_data = events & 1398 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 1399 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 1400 | MSDC_INT_DMA_PROTECT); 1401 u32 val; 1402 int ret; 1403 1404 spin_lock_irqsave(&host->lock, flags); 1405 done = !host->data; 1406 if (check_data) 1407 host->data = NULL; 1408 spin_unlock_irqrestore(&host->lock, flags); 1409 1410 if (done) 1411 return; 1412 stop = data->stop; 1413 1414 if (check_data || (stop && stop->error)) { 1415 dev_dbg(host->dev, "DMA status: 0x%8X\n", 1416 readl(host->base + MSDC_DMA_CFG)); 1417 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1418 1); 1419 1420 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val, 1421 !(val & MSDC_DMA_CTRL_STOP), 1, 20000); 1422 if (ret) 1423 dev_dbg(host->dev, "DMA stop timed out\n"); 1424 1425 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val, 1426 !(val & MSDC_DMA_CFG_STS), 1, 20000); 1427 if (ret) 1428 dev_dbg(host->dev, "DMA inactive timed out\n"); 1429 1430 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 1431 dev_dbg(host->dev, "DMA stop\n"); 1432 1433 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 1434 data->bytes_xfered = data->blocks * data->blksz; 1435 } else { 1436 dev_dbg(host->dev, "interrupt events: %x\n", events); 1437 msdc_reset_hw(host); 1438 host->error |= REQ_DAT_ERR; 1439 data->bytes_xfered = 0; 1440 1441 if (events & MSDC_INT_DATTMO) 1442 data->error = -ETIMEDOUT; 1443 else if (events & MSDC_INT_DATCRCERR) 1444 data->error = -EILSEQ; 1445 1446 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 1447 __func__, mrq->cmd->opcode, data->blocks); 1448 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 1449 (int)data->error, data->bytes_xfered); 1450 } 1451 1452 msdc_data_xfer_next(host, mrq); 1453 } 1454 } 1455 1456 static void msdc_set_buswidth(struct msdc_host *host, u32 width) 1457 { 1458 u32 val = readl(host->base + SDC_CFG); 1459 1460 val &= ~SDC_CFG_BUSWIDTH; 1461 1462 switch (width) { 1463 default: 1464 case MMC_BUS_WIDTH_1: 1465 val |= (MSDC_BUS_1BITS << 16); 1466 break; 1467 case MMC_BUS_WIDTH_4: 1468 val |= (MSDC_BUS_4BITS << 16); 1469 break; 1470 case MMC_BUS_WIDTH_8: 1471 val |= (MSDC_BUS_8BITS << 16); 1472 break; 1473 } 1474 1475 writel(val, host->base + SDC_CFG); 1476 dev_dbg(host->dev, "Bus Width = %d", width); 1477 } 1478 1479 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 1480 { 1481 struct msdc_host *host = mmc_priv(mmc); 1482 int ret; 1483 1484 if (!IS_ERR(mmc->supply.vqmmc)) { 1485 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1486 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 1487 dev_err(host->dev, "Unsupported signal voltage!\n"); 1488 return -EINVAL; 1489 } 1490 1491 ret = mmc_regulator_set_vqmmc(mmc, ios); 1492 if (ret < 0) { 1493 dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1494 ret, ios->signal_voltage); 1495 return ret; 1496 } 1497 1498 /* Apply different pinctrl settings for different signal voltage */ 1499 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 1500 pinctrl_select_state(host->pinctrl, host->pins_uhs); 1501 else 1502 pinctrl_select_state(host->pinctrl, host->pins_default); 1503 } 1504 return 0; 1505 } 1506 1507 static int msdc_card_busy(struct mmc_host *mmc) 1508 { 1509 struct msdc_host *host = mmc_priv(mmc); 1510 u32 status = readl(host->base + MSDC_PS); 1511 1512 /* only check if data0 is low */ 1513 return !(status & BIT(16)); 1514 } 1515 1516 static void msdc_request_timeout(struct work_struct *work) 1517 { 1518 struct msdc_host *host = container_of(work, struct msdc_host, 1519 req_timeout.work); 1520 1521 /* simulate HW timeout status */ 1522 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 1523 if (host->mrq) { 1524 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 1525 host->mrq, host->mrq->cmd->opcode); 1526 if (host->cmd) { 1527 dev_err(host->dev, "%s: aborting cmd=%d\n", 1528 __func__, host->cmd->opcode); 1529 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 1530 host->cmd); 1531 } else if (host->data) { 1532 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 1533 __func__, host->mrq->cmd->opcode, 1534 host->data->blocks); 1535 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 1536 host->data); 1537 } 1538 } 1539 } 1540 1541 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb) 1542 { 1543 if (enb) { 1544 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1545 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1546 if (host->dev_comp->recheck_sdio_irq) 1547 msdc_recheck_sdio_irq(host); 1548 } else { 1549 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1550 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1551 } 1552 } 1553 1554 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) 1555 { 1556 struct msdc_host *host = mmc_priv(mmc); 1557 unsigned long flags; 1558 int ret; 1559 1560 spin_lock_irqsave(&host->lock, flags); 1561 __msdc_enable_sdio_irq(host, enb); 1562 spin_unlock_irqrestore(&host->lock, flags); 1563 1564 if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) { 1565 if (enb) { 1566 /* 1567 * In dev_pm_set_dedicated_wake_irq_reverse(), eint pin will be set to 1568 * GPIO mode. We need to restore it to SDIO DAT1 mode after that. 1569 * Since the current pinstate is pins_uhs, to ensure pinctrl select take 1570 * affect successfully, we change the pinstate to pins_eint firstly. 1571 */ 1572 pinctrl_select_state(host->pinctrl, host->pins_eint); 1573 ret = dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq); 1574 1575 if (ret) { 1576 dev_err(host->dev, "Failed to register SDIO wakeup irq!\n"); 1577 host->pins_eint = NULL; 1578 pm_runtime_get_noresume(host->dev); 1579 } else { 1580 dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq); 1581 } 1582 1583 pinctrl_select_state(host->pinctrl, host->pins_uhs); 1584 } else { 1585 dev_pm_clear_wake_irq(host->dev); 1586 } 1587 } else { 1588 if (enb) { 1589 /* Ensure host->pins_eint is NULL */ 1590 host->pins_eint = NULL; 1591 pm_runtime_get_noresume(host->dev); 1592 } else { 1593 pm_runtime_put_noidle(host->dev); 1594 } 1595 } 1596 } 1597 1598 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) 1599 { 1600 struct mmc_host *mmc = mmc_from_priv(host); 1601 int cmd_err = 0, dat_err = 0; 1602 1603 if (intsts & MSDC_INT_RSPCRCERR) { 1604 cmd_err = -EILSEQ; 1605 dev_err(host->dev, "%s: CMD CRC ERR", __func__); 1606 } else if (intsts & MSDC_INT_CMDTMO) { 1607 cmd_err = -ETIMEDOUT; 1608 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); 1609 } 1610 1611 if (intsts & MSDC_INT_DATCRCERR) { 1612 dat_err = -EILSEQ; 1613 dev_err(host->dev, "%s: DATA CRC ERR", __func__); 1614 } else if (intsts & MSDC_INT_DATTMO) { 1615 dat_err = -ETIMEDOUT; 1616 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); 1617 } 1618 1619 if (cmd_err || dat_err) { 1620 dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", 1621 cmd_err, dat_err, intsts); 1622 } 1623 1624 return cqhci_irq(mmc, 0, cmd_err, dat_err); 1625 } 1626 1627 static irqreturn_t msdc_irq(int irq, void *dev_id) 1628 { 1629 struct msdc_host *host = (struct msdc_host *) dev_id; 1630 struct mmc_host *mmc = mmc_from_priv(host); 1631 1632 while (true) { 1633 struct mmc_request *mrq; 1634 struct mmc_command *cmd; 1635 struct mmc_data *data; 1636 u32 events, event_mask; 1637 1638 spin_lock(&host->lock); 1639 events = readl(host->base + MSDC_INT); 1640 event_mask = readl(host->base + MSDC_INTEN); 1641 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1642 __msdc_enable_sdio_irq(host, 0); 1643 /* clear interrupts */ 1644 writel(events & event_mask, host->base + MSDC_INT); 1645 1646 mrq = host->mrq; 1647 cmd = host->cmd; 1648 data = host->data; 1649 spin_unlock(&host->lock); 1650 1651 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1652 sdio_signal_irq(mmc); 1653 1654 if ((events & event_mask) & MSDC_INT_CDSC) { 1655 if (host->internal_cd) 1656 mmc_detect_change(mmc, msecs_to_jiffies(20)); 1657 events &= ~MSDC_INT_CDSC; 1658 } 1659 1660 if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) 1661 break; 1662 1663 if ((mmc->caps2 & MMC_CAP2_CQE) && 1664 (events & MSDC_INT_CMDQ)) { 1665 msdc_cmdq_irq(host, events); 1666 /* clear interrupts */ 1667 writel(events, host->base + MSDC_INT); 1668 return IRQ_HANDLED; 1669 } 1670 1671 if (!mrq) { 1672 dev_err(host->dev, 1673 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 1674 __func__, events, event_mask); 1675 WARN_ON(1); 1676 break; 1677 } 1678 1679 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 1680 1681 if (cmd) 1682 msdc_cmd_done(host, events, mrq, cmd); 1683 else if (data) 1684 msdc_data_xfer_done(host, events, mrq, data); 1685 } 1686 1687 return IRQ_HANDLED; 1688 } 1689 1690 static void msdc_init_hw(struct msdc_host *host) 1691 { 1692 u32 val; 1693 u32 tune_reg = host->dev_comp->pad_tune_reg; 1694 struct mmc_host *mmc = mmc_from_priv(host); 1695 1696 if (host->reset) { 1697 reset_control_assert(host->reset); 1698 usleep_range(10, 50); 1699 reset_control_deassert(host->reset); 1700 } 1701 1702 /* Configure to MMC/SD mode, clock free running */ 1703 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 1704 1705 /* Reset */ 1706 msdc_reset_hw(host); 1707 1708 /* Disable and clear all interrupts */ 1709 writel(0, host->base + MSDC_INTEN); 1710 val = readl(host->base + MSDC_INT); 1711 writel(val, host->base + MSDC_INT); 1712 1713 /* Configure card detection */ 1714 if (host->internal_cd) { 1715 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, 1716 DEFAULT_DEBOUNCE); 1717 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1718 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1719 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1720 } else { 1721 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1722 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1723 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1724 } 1725 1726 if (host->top_base) { 1727 writel(0, host->top_base + EMMC_TOP_CONTROL); 1728 writel(0, host->top_base + EMMC_TOP_CMD); 1729 } else { 1730 writel(0, host->base + tune_reg); 1731 } 1732 writel(0, host->base + MSDC_IOCON); 1733 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 1734 writel(0x403c0046, host->base + MSDC_PATCH_BIT); 1735 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 1736 writel(0xffff4089, host->base + MSDC_PATCH_BIT1); 1737 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1738 1739 if (host->dev_comp->stop_clk_fix) { 1740 sdr_set_field(host->base + MSDC_PATCH_BIT1, 1741 MSDC_PATCH_BIT1_STOP_DLY, 3); 1742 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1743 SDC_FIFO_CFG_WRVALIDSEL); 1744 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1745 SDC_FIFO_CFG_RDVALIDSEL); 1746 } 1747 1748 if (host->dev_comp->busy_check) 1749 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7)); 1750 1751 if (host->dev_comp->async_fifo) { 1752 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1753 MSDC_PB2_RESPWAIT, 3); 1754 if (host->dev_comp->enhance_rx) { 1755 if (host->top_base) 1756 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1757 SDC_RX_ENH_EN); 1758 else 1759 sdr_set_bits(host->base + SDC_ADV_CFG0, 1760 SDC_RX_ENHANCE_EN); 1761 } else { 1762 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1763 MSDC_PB2_RESPSTSENSEL, 2); 1764 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1765 MSDC_PB2_CRCSTSENSEL, 2); 1766 } 1767 /* use async fifo, then no need tune internal delay */ 1768 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, 1769 MSDC_PATCH_BIT2_CFGRESP); 1770 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1771 MSDC_PATCH_BIT2_CFGCRCSTS); 1772 } 1773 1774 if (host->dev_comp->support_64g) 1775 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1776 MSDC_PB2_SUPPORT_64G); 1777 if (host->dev_comp->data_tune) { 1778 if (host->top_base) { 1779 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1780 PAD_DAT_RD_RXDLY_SEL); 1781 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, 1782 DATA_K_VALUE_SEL); 1783 sdr_set_bits(host->top_base + EMMC_TOP_CMD, 1784 PAD_CMD_RD_RXDLY_SEL); 1785 } else { 1786 sdr_set_bits(host->base + tune_reg, 1787 MSDC_PAD_TUNE_RD_SEL | 1788 MSDC_PAD_TUNE_CMD_SEL); 1789 } 1790 } else { 1791 /* choose clock tune */ 1792 if (host->top_base) 1793 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1794 PAD_RXDLY_SEL); 1795 else 1796 sdr_set_bits(host->base + tune_reg, 1797 MSDC_PAD_TUNE_RXDLYSEL); 1798 } 1799 1800 if (mmc->caps2 & MMC_CAP2_NO_SDIO) { 1801 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1802 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1803 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 1804 } else { 1805 /* Configure to enable SDIO mode, otherwise SDIO CMD5 fails */ 1806 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1807 1808 /* Config SDIO device detect interrupt function */ 1809 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1810 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 1811 } 1812 1813 /* Configure to default data timeout */ 1814 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 1815 1816 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 1817 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1818 if (host->top_base) { 1819 host->def_tune_para.emmc_top_control = 1820 readl(host->top_base + EMMC_TOP_CONTROL); 1821 host->def_tune_para.emmc_top_cmd = 1822 readl(host->top_base + EMMC_TOP_CMD); 1823 host->saved_tune_para.emmc_top_control = 1824 readl(host->top_base + EMMC_TOP_CONTROL); 1825 host->saved_tune_para.emmc_top_cmd = 1826 readl(host->top_base + EMMC_TOP_CMD); 1827 } else { 1828 host->def_tune_para.pad_tune = readl(host->base + tune_reg); 1829 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 1830 } 1831 dev_dbg(host->dev, "init hardware done!"); 1832 } 1833 1834 static void msdc_deinit_hw(struct msdc_host *host) 1835 { 1836 u32 val; 1837 1838 if (host->internal_cd) { 1839 /* Disabled card-detect */ 1840 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1841 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1842 } 1843 1844 /* Disable and clear all interrupts */ 1845 writel(0, host->base + MSDC_INTEN); 1846 1847 val = readl(host->base + MSDC_INT); 1848 writel(val, host->base + MSDC_INT); 1849 } 1850 1851 /* init gpd and bd list in msdc_drv_probe */ 1852 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 1853 { 1854 struct mt_gpdma_desc *gpd = dma->gpd; 1855 struct mt_bdma_desc *bd = dma->bd; 1856 dma_addr_t dma_addr; 1857 int i; 1858 1859 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 1860 1861 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); 1862 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 1863 /* gpd->next is must set for desc DMA 1864 * That's why must alloc 2 gpd structure. 1865 */ 1866 gpd->next = lower_32_bits(dma_addr); 1867 if (host->dev_comp->support_64g) 1868 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1869 1870 dma_addr = dma->bd_addr; 1871 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ 1872 if (host->dev_comp->support_64g) 1873 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; 1874 1875 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 1876 for (i = 0; i < (MAX_BD_NUM - 1); i++) { 1877 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); 1878 bd[i].next = lower_32_bits(dma_addr); 1879 if (host->dev_comp->support_64g) 1880 bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1881 } 1882 } 1883 1884 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1885 { 1886 struct msdc_host *host = mmc_priv(mmc); 1887 int ret; 1888 1889 msdc_set_buswidth(host, ios->bus_width); 1890 1891 /* Suspend/Resume will do power off/on */ 1892 switch (ios->power_mode) { 1893 case MMC_POWER_UP: 1894 if (!IS_ERR(mmc->supply.vmmc)) { 1895 msdc_init_hw(host); 1896 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1897 ios->vdd); 1898 if (ret) { 1899 dev_err(host->dev, "Failed to set vmmc power!\n"); 1900 return; 1901 } 1902 } 1903 break; 1904 case MMC_POWER_ON: 1905 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1906 ret = regulator_enable(mmc->supply.vqmmc); 1907 if (ret) 1908 dev_err(host->dev, "Failed to set vqmmc power!\n"); 1909 else 1910 host->vqmmc_enabled = true; 1911 } 1912 break; 1913 case MMC_POWER_OFF: 1914 if (!IS_ERR(mmc->supply.vmmc)) 1915 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1916 1917 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1918 regulator_disable(mmc->supply.vqmmc); 1919 host->vqmmc_enabled = false; 1920 } 1921 break; 1922 default: 1923 break; 1924 } 1925 1926 if (host->mclk != ios->clock || host->timing != ios->timing) 1927 msdc_set_mclk(host, ios->timing, ios->clock); 1928 } 1929 1930 static u32 test_delay_bit(u32 delay, u32 bit) 1931 { 1932 bit %= PAD_DELAY_MAX; 1933 return delay & BIT(bit); 1934 } 1935 1936 static int get_delay_len(u32 delay, u32 start_bit) 1937 { 1938 int i; 1939 1940 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 1941 if (test_delay_bit(delay, start_bit + i) == 0) 1942 return i; 1943 } 1944 return PAD_DELAY_MAX - start_bit; 1945 } 1946 1947 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 1948 { 1949 int start = 0, len = 0; 1950 int start_final = 0, len_final = 0; 1951 u8 final_phase = 0xff; 1952 struct msdc_delay_phase delay_phase = { 0, }; 1953 1954 if (delay == 0) { 1955 dev_err(host->dev, "phase error: [map:%x]\n", delay); 1956 delay_phase.final_phase = final_phase; 1957 return delay_phase; 1958 } 1959 1960 while (start < PAD_DELAY_MAX) { 1961 len = get_delay_len(delay, start); 1962 if (len_final < len) { 1963 start_final = start; 1964 len_final = len; 1965 } 1966 start += len ? len : 1; 1967 if (len >= 12 && start_final < 4) 1968 break; 1969 } 1970 1971 /* The rule is that to find the smallest delay cell */ 1972 if (start_final == 0) 1973 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 1974 else 1975 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 1976 dev_dbg(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 1977 delay, len_final, final_phase); 1978 1979 delay_phase.maxlen = len_final; 1980 delay_phase.start = start_final; 1981 delay_phase.final_phase = final_phase; 1982 return delay_phase; 1983 } 1984 1985 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) 1986 { 1987 u32 tune_reg = host->dev_comp->pad_tune_reg; 1988 1989 if (host->top_base) 1990 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, 1991 value); 1992 else 1993 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1994 value); 1995 } 1996 1997 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) 1998 { 1999 u32 tune_reg = host->dev_comp->pad_tune_reg; 2000 2001 if (host->top_base) 2002 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, 2003 PAD_DAT_RD_RXDLY, value); 2004 else 2005 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, 2006 value); 2007 } 2008 2009 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 2010 { 2011 struct msdc_host *host = mmc_priv(mmc); 2012 u32 rise_delay = 0, fall_delay = 0; 2013 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2014 struct msdc_delay_phase internal_delay_phase; 2015 u8 final_delay, final_maxlen; 2016 u32 internal_delay = 0; 2017 u32 tune_reg = host->dev_comp->pad_tune_reg; 2018 int cmd_err; 2019 int i, j; 2020 2021 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 2022 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 2023 sdr_set_field(host->base + tune_reg, 2024 MSDC_PAD_TUNE_CMDRRDLY, 2025 host->hs200_cmd_int_delay); 2026 2027 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2028 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2029 msdc_set_cmd_delay(host, i); 2030 /* 2031 * Using the same parameters, it may sometimes pass the test, 2032 * but sometimes it may fail. To make sure the parameters are 2033 * more stable, we test each set of parameters 3 times. 2034 */ 2035 for (j = 0; j < 3; j++) { 2036 mmc_send_tuning(mmc, opcode, &cmd_err); 2037 if (!cmd_err) { 2038 rise_delay |= BIT(i); 2039 } else { 2040 rise_delay &= ~BIT(i); 2041 break; 2042 } 2043 } 2044 } 2045 final_rise_delay = get_best_delay(host, rise_delay); 2046 /* if rising edge has enough margin, then do not scan falling edge */ 2047 if (final_rise_delay.maxlen >= 12 || 2048 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2049 goto skip_fall; 2050 2051 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2052 for (i = 0; i < PAD_DELAY_MAX; i++) { 2053 msdc_set_cmd_delay(host, i); 2054 /* 2055 * Using the same parameters, it may sometimes pass the test, 2056 * but sometimes it may fail. To make sure the parameters are 2057 * more stable, we test each set of parameters 3 times. 2058 */ 2059 for (j = 0; j < 3; j++) { 2060 mmc_send_tuning(mmc, opcode, &cmd_err); 2061 if (!cmd_err) { 2062 fall_delay |= BIT(i); 2063 } else { 2064 fall_delay &= ~BIT(i); 2065 break; 2066 } 2067 } 2068 } 2069 final_fall_delay = get_best_delay(host, fall_delay); 2070 2071 skip_fall: 2072 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2073 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 2074 final_maxlen = final_fall_delay.maxlen; 2075 if (final_maxlen == final_rise_delay.maxlen) { 2076 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2077 final_delay = final_rise_delay.final_phase; 2078 } else { 2079 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2080 final_delay = final_fall_delay.final_phase; 2081 } 2082 msdc_set_cmd_delay(host, final_delay); 2083 2084 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) 2085 goto skip_internal; 2086 2087 for (i = 0; i < PAD_DELAY_MAX; i++) { 2088 sdr_set_field(host->base + tune_reg, 2089 MSDC_PAD_TUNE_CMDRRDLY, i); 2090 mmc_send_tuning(mmc, opcode, &cmd_err); 2091 if (!cmd_err) 2092 internal_delay |= BIT(i); 2093 } 2094 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 2095 internal_delay_phase = get_best_delay(host, internal_delay); 2096 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 2097 internal_delay_phase.final_phase); 2098 skip_internal: 2099 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 2100 return final_delay == 0xff ? -EIO : 0; 2101 } 2102 2103 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 2104 { 2105 struct msdc_host *host = mmc_priv(mmc); 2106 u32 cmd_delay = 0; 2107 struct msdc_delay_phase final_cmd_delay = { 0,}; 2108 u8 final_delay; 2109 int cmd_err; 2110 int i, j; 2111 2112 /* select EMMC50 PAD CMD tune */ 2113 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 2114 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); 2115 2116 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 2117 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 2118 sdr_set_field(host->base + MSDC_PAD_TUNE, 2119 MSDC_PAD_TUNE_CMDRRDLY, 2120 host->hs200_cmd_int_delay); 2121 2122 if (host->hs400_cmd_resp_sel_rising) 2123 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2124 else 2125 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2126 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2127 sdr_set_field(host->base + PAD_CMD_TUNE, 2128 PAD_CMD_TUNE_RX_DLY3, i); 2129 /* 2130 * Using the same parameters, it may sometimes pass the test, 2131 * but sometimes it may fail. To make sure the parameters are 2132 * more stable, we test each set of parameters 3 times. 2133 */ 2134 for (j = 0; j < 3; j++) { 2135 mmc_send_tuning(mmc, opcode, &cmd_err); 2136 if (!cmd_err) { 2137 cmd_delay |= BIT(i); 2138 } else { 2139 cmd_delay &= ~BIT(i); 2140 break; 2141 } 2142 } 2143 } 2144 final_cmd_delay = get_best_delay(host, cmd_delay); 2145 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 2146 final_cmd_delay.final_phase); 2147 final_delay = final_cmd_delay.final_phase; 2148 2149 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 2150 return final_delay == 0xff ? -EIO : 0; 2151 } 2152 2153 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 2154 { 2155 struct msdc_host *host = mmc_priv(mmc); 2156 u32 rise_delay = 0, fall_delay = 0; 2157 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2158 u8 final_delay, final_maxlen; 2159 int i, ret; 2160 2161 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2162 host->latch_ck); 2163 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2164 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2165 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2166 msdc_set_data_delay(host, i); 2167 ret = mmc_send_tuning(mmc, opcode, NULL); 2168 if (!ret) 2169 rise_delay |= BIT(i); 2170 } 2171 final_rise_delay = get_best_delay(host, rise_delay); 2172 /* if rising edge has enough margin, then do not scan falling edge */ 2173 if (final_rise_delay.maxlen >= 12 || 2174 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2175 goto skip_fall; 2176 2177 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2178 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2179 for (i = 0; i < PAD_DELAY_MAX; i++) { 2180 msdc_set_data_delay(host, i); 2181 ret = mmc_send_tuning(mmc, opcode, NULL); 2182 if (!ret) 2183 fall_delay |= BIT(i); 2184 } 2185 final_fall_delay = get_best_delay(host, fall_delay); 2186 2187 skip_fall: 2188 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2189 if (final_maxlen == final_rise_delay.maxlen) { 2190 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2191 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2192 final_delay = final_rise_delay.final_phase; 2193 } else { 2194 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2195 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2196 final_delay = final_fall_delay.final_phase; 2197 } 2198 msdc_set_data_delay(host, final_delay); 2199 2200 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 2201 return final_delay == 0xff ? -EIO : 0; 2202 } 2203 2204 /* 2205 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune 2206 * together, which can save the tuning time. 2207 */ 2208 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode) 2209 { 2210 struct msdc_host *host = mmc_priv(mmc); 2211 u32 rise_delay = 0, fall_delay = 0; 2212 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2213 u8 final_delay, final_maxlen; 2214 int i, ret; 2215 2216 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2217 host->latch_ck); 2218 2219 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2220 sdr_clr_bits(host->base + MSDC_IOCON, 2221 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2222 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2223 msdc_set_cmd_delay(host, i); 2224 msdc_set_data_delay(host, i); 2225 ret = mmc_send_tuning(mmc, opcode, NULL); 2226 if (!ret) 2227 rise_delay |= BIT(i); 2228 } 2229 final_rise_delay = get_best_delay(host, rise_delay); 2230 /* if rising edge has enough margin, then do not scan falling edge */ 2231 if (final_rise_delay.maxlen >= 12 || 2232 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2233 goto skip_fall; 2234 2235 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2236 sdr_set_bits(host->base + MSDC_IOCON, 2237 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2238 for (i = 0; i < PAD_DELAY_MAX; i++) { 2239 msdc_set_cmd_delay(host, i); 2240 msdc_set_data_delay(host, i); 2241 ret = mmc_send_tuning(mmc, opcode, NULL); 2242 if (!ret) 2243 fall_delay |= BIT(i); 2244 } 2245 final_fall_delay = get_best_delay(host, fall_delay); 2246 2247 skip_fall: 2248 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2249 if (final_maxlen == final_rise_delay.maxlen) { 2250 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2251 sdr_clr_bits(host->base + MSDC_IOCON, 2252 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2253 final_delay = final_rise_delay.final_phase; 2254 } else { 2255 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2256 sdr_set_bits(host->base + MSDC_IOCON, 2257 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2258 final_delay = final_fall_delay.final_phase; 2259 } 2260 2261 msdc_set_cmd_delay(host, final_delay); 2262 msdc_set_data_delay(host, final_delay); 2263 2264 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); 2265 return final_delay == 0xff ? -EIO : 0; 2266 } 2267 2268 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 2269 { 2270 struct msdc_host *host = mmc_priv(mmc); 2271 int ret; 2272 u32 tune_reg = host->dev_comp->pad_tune_reg; 2273 2274 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { 2275 ret = msdc_tune_together(mmc, opcode); 2276 if (host->hs400_mode) { 2277 sdr_clr_bits(host->base + MSDC_IOCON, 2278 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2279 msdc_set_data_delay(host, 0); 2280 } 2281 goto tune_done; 2282 } 2283 if (host->hs400_mode && 2284 host->dev_comp->hs400_tune) 2285 ret = hs400_tune_response(mmc, opcode); 2286 else 2287 ret = msdc_tune_response(mmc, opcode); 2288 if (ret == -EIO) { 2289 dev_err(host->dev, "Tune response fail!\n"); 2290 return ret; 2291 } 2292 if (host->hs400_mode == false) { 2293 ret = msdc_tune_data(mmc, opcode); 2294 if (ret == -EIO) 2295 dev_err(host->dev, "Tune data fail!\n"); 2296 } 2297 2298 tune_done: 2299 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 2300 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 2301 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2302 if (host->top_base) { 2303 host->saved_tune_para.emmc_top_control = readl(host->top_base + 2304 EMMC_TOP_CONTROL); 2305 host->saved_tune_para.emmc_top_cmd = readl(host->top_base + 2306 EMMC_TOP_CMD); 2307 } 2308 return ret; 2309 } 2310 2311 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 2312 { 2313 struct msdc_host *host = mmc_priv(mmc); 2314 host->hs400_mode = true; 2315 2316 if (host->top_base) 2317 writel(host->hs400_ds_delay, 2318 host->top_base + EMMC50_PAD_DS_TUNE); 2319 else 2320 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 2321 /* hs400 mode must set it to 0 */ 2322 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); 2323 /* to improve read performance, set outstanding to 2 */ 2324 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); 2325 2326 return 0; 2327 } 2328 2329 static int msdc_execute_hs400_tuning(struct mmc_host *mmc, struct mmc_card *card) 2330 { 2331 struct msdc_host *host = mmc_priv(mmc); 2332 struct msdc_delay_phase dly1_delay; 2333 u32 val, result_dly1 = 0; 2334 u8 *ext_csd; 2335 int i, ret; 2336 2337 if (host->top_base) { 2338 sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE, 2339 PAD_DS_DLY_SEL); 2340 if (host->hs400_ds_dly3) 2341 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, 2342 PAD_DS_DLY3, host->hs400_ds_dly3); 2343 } else { 2344 sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL); 2345 if (host->hs400_ds_dly3) 2346 sdr_set_field(host->base + PAD_DS_TUNE, 2347 PAD_DS_TUNE_DLY3, host->hs400_ds_dly3); 2348 } 2349 2350 host->hs400_tuning = true; 2351 for (i = 0; i < PAD_DELAY_MAX; i++) { 2352 if (host->top_base) 2353 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, 2354 PAD_DS_DLY1, i); 2355 else 2356 sdr_set_field(host->base + PAD_DS_TUNE, 2357 PAD_DS_TUNE_DLY1, i); 2358 ret = mmc_get_ext_csd(card, &ext_csd); 2359 if (!ret) { 2360 result_dly1 |= BIT(i); 2361 kfree(ext_csd); 2362 } 2363 } 2364 host->hs400_tuning = false; 2365 2366 dly1_delay = get_best_delay(host, result_dly1); 2367 if (dly1_delay.maxlen == 0) { 2368 dev_err(host->dev, "Failed to get DLY1 delay!\n"); 2369 goto fail; 2370 } 2371 if (host->top_base) 2372 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, 2373 PAD_DS_DLY1, dly1_delay.final_phase); 2374 else 2375 sdr_set_field(host->base + PAD_DS_TUNE, 2376 PAD_DS_TUNE_DLY1, dly1_delay.final_phase); 2377 2378 if (host->top_base) 2379 val = readl(host->top_base + EMMC50_PAD_DS_TUNE); 2380 else 2381 val = readl(host->base + PAD_DS_TUNE); 2382 2383 dev_info(host->dev, "Final PAD_DS_TUNE: 0x%x\n", val); 2384 2385 return 0; 2386 2387 fail: 2388 dev_err(host->dev, "Failed to tuning DS pin delay!\n"); 2389 return -EIO; 2390 } 2391 2392 static void msdc_hw_reset(struct mmc_host *mmc) 2393 { 2394 struct msdc_host *host = mmc_priv(mmc); 2395 2396 sdr_set_bits(host->base + EMMC_IOCON, 1); 2397 udelay(10); /* 10us is enough */ 2398 sdr_clr_bits(host->base + EMMC_IOCON, 1); 2399 } 2400 2401 static void msdc_ack_sdio_irq(struct mmc_host *mmc) 2402 { 2403 unsigned long flags; 2404 struct msdc_host *host = mmc_priv(mmc); 2405 2406 spin_lock_irqsave(&host->lock, flags); 2407 __msdc_enable_sdio_irq(host, 1); 2408 spin_unlock_irqrestore(&host->lock, flags); 2409 } 2410 2411 static int msdc_get_cd(struct mmc_host *mmc) 2412 { 2413 struct msdc_host *host = mmc_priv(mmc); 2414 int val; 2415 2416 if (mmc->caps & MMC_CAP_NONREMOVABLE) 2417 return 1; 2418 2419 if (!host->internal_cd) 2420 return mmc_gpio_get_cd(mmc); 2421 2422 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; 2423 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) 2424 return !!val; 2425 else 2426 return !val; 2427 } 2428 2429 static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc, 2430 struct mmc_ios *ios) 2431 { 2432 struct msdc_host *host = mmc_priv(mmc); 2433 2434 if (ios->enhanced_strobe) { 2435 msdc_prepare_hs400_tuning(mmc, ios); 2436 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1); 2437 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1); 2438 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1); 2439 2440 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); 2441 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); 2442 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT); 2443 } else { 2444 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0); 2445 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0); 2446 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0); 2447 2448 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); 2449 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); 2450 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4); 2451 } 2452 } 2453 2454 static void msdc_cqe_cit_cal(struct msdc_host *host, u64 timer_ns) 2455 { 2456 struct mmc_host *mmc = mmc_from_priv(host); 2457 struct cqhci_host *cq_host = mmc->cqe_private; 2458 u8 itcfmul; 2459 u64 hclk_freq, value; 2460 2461 /* 2462 * On MediaTek SoCs the MSDC controller's CQE uses msdc_hclk as ITCFVAL 2463 * so we multiply/divide the HCLK frequency by ITCFMUL to calculate the 2464 * Send Status Command Idle Timer (CIT) value. 2465 */ 2466 hclk_freq = (u64)clk_get_rate(host->h_clk); 2467 itcfmul = CQHCI_ITCFMUL(cqhci_readl(cq_host, CQHCI_CAP)); 2468 switch (itcfmul) { 2469 case 0x0: 2470 do_div(hclk_freq, 1000); 2471 break; 2472 case 0x1: 2473 do_div(hclk_freq, 100); 2474 break; 2475 case 0x2: 2476 do_div(hclk_freq, 10); 2477 break; 2478 case 0x3: 2479 break; 2480 case 0x4: 2481 hclk_freq = hclk_freq * 10; 2482 break; 2483 default: 2484 host->cq_ssc1_time = 0x40; 2485 return; 2486 } 2487 2488 value = hclk_freq * timer_ns; 2489 do_div(value, 1000000000); 2490 host->cq_ssc1_time = value; 2491 } 2492 2493 static void msdc_cqe_enable(struct mmc_host *mmc) 2494 { 2495 struct msdc_host *host = mmc_priv(mmc); 2496 struct cqhci_host *cq_host = mmc->cqe_private; 2497 2498 /* enable cmdq irq */ 2499 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); 2500 /* enable busy check */ 2501 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 2502 /* default write data / busy timeout 20s */ 2503 msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); 2504 /* default read data timeout 1s */ 2505 msdc_set_timeout(host, 1000000000ULL, 0); 2506 2507 /* Set the send status command idle timer */ 2508 cqhci_writel(cq_host, host->cq_ssc1_time, CQHCI_SSC1); 2509 } 2510 2511 static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) 2512 { 2513 struct msdc_host *host = mmc_priv(mmc); 2514 unsigned int val = 0; 2515 2516 /* disable cmdq irq */ 2517 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); 2518 /* disable busy check */ 2519 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 2520 2521 val = readl(host->base + MSDC_INT); 2522 writel(val, host->base + MSDC_INT); 2523 2524 if (recovery) { 2525 sdr_set_field(host->base + MSDC_DMA_CTRL, 2526 MSDC_DMA_CTRL_STOP, 1); 2527 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val, 2528 !(val & MSDC_DMA_CTRL_STOP), 1, 3000))) 2529 return; 2530 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val, 2531 !(val & MSDC_DMA_CFG_STS), 1, 3000))) 2532 return; 2533 msdc_reset_hw(host); 2534 } 2535 } 2536 2537 static void msdc_cqe_pre_enable(struct mmc_host *mmc) 2538 { 2539 struct cqhci_host *cq_host = mmc->cqe_private; 2540 u32 reg; 2541 2542 reg = cqhci_readl(cq_host, CQHCI_CFG); 2543 reg |= CQHCI_ENABLE; 2544 cqhci_writel(cq_host, reg, CQHCI_CFG); 2545 } 2546 2547 static void msdc_cqe_post_disable(struct mmc_host *mmc) 2548 { 2549 struct cqhci_host *cq_host = mmc->cqe_private; 2550 u32 reg; 2551 2552 reg = cqhci_readl(cq_host, CQHCI_CFG); 2553 reg &= ~CQHCI_ENABLE; 2554 cqhci_writel(cq_host, reg, CQHCI_CFG); 2555 } 2556 2557 static const struct mmc_host_ops mt_msdc_ops = { 2558 .post_req = msdc_post_req, 2559 .pre_req = msdc_pre_req, 2560 .request = msdc_ops_request, 2561 .set_ios = msdc_ops_set_ios, 2562 .get_ro = mmc_gpio_get_ro, 2563 .get_cd = msdc_get_cd, 2564 .hs400_enhanced_strobe = msdc_hs400_enhanced_strobe, 2565 .enable_sdio_irq = msdc_enable_sdio_irq, 2566 .ack_sdio_irq = msdc_ack_sdio_irq, 2567 .start_signal_voltage_switch = msdc_ops_switch_volt, 2568 .card_busy = msdc_card_busy, 2569 .execute_tuning = msdc_execute_tuning, 2570 .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 2571 .execute_hs400_tuning = msdc_execute_hs400_tuning, 2572 .card_hw_reset = msdc_hw_reset, 2573 }; 2574 2575 static const struct cqhci_host_ops msdc_cmdq_ops = { 2576 .enable = msdc_cqe_enable, 2577 .disable = msdc_cqe_disable, 2578 .pre_enable = msdc_cqe_pre_enable, 2579 .post_disable = msdc_cqe_post_disable, 2580 }; 2581 2582 static void msdc_of_property_parse(struct platform_device *pdev, 2583 struct msdc_host *host) 2584 { 2585 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", 2586 &host->latch_ck); 2587 2588 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 2589 &host->hs400_ds_delay); 2590 2591 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3", 2592 &host->hs400_ds_dly3); 2593 2594 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 2595 &host->hs200_cmd_int_delay); 2596 2597 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 2598 &host->hs400_cmd_int_delay); 2599 2600 if (of_property_read_bool(pdev->dev.of_node, 2601 "mediatek,hs400-cmd-resp-sel-rising")) 2602 host->hs400_cmd_resp_sel_rising = true; 2603 else 2604 host->hs400_cmd_resp_sel_rising = false; 2605 2606 if (of_property_read_bool(pdev->dev.of_node, 2607 "supports-cqe")) 2608 host->cqhci = true; 2609 else 2610 host->cqhci = false; 2611 } 2612 2613 static int msdc_of_clock_parse(struct platform_device *pdev, 2614 struct msdc_host *host) 2615 { 2616 int ret; 2617 2618 host->src_clk = devm_clk_get(&pdev->dev, "source"); 2619 if (IS_ERR(host->src_clk)) 2620 return PTR_ERR(host->src_clk); 2621 2622 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 2623 if (IS_ERR(host->h_clk)) 2624 return PTR_ERR(host->h_clk); 2625 2626 host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk"); 2627 if (IS_ERR(host->bus_clk)) 2628 host->bus_clk = NULL; 2629 2630 /*source clock control gate is optional clock*/ 2631 host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg"); 2632 if (IS_ERR(host->src_clk_cg)) 2633 return PTR_ERR(host->src_clk_cg); 2634 2635 /* 2636 * Fallback for legacy device-trees: src_clk and HCLK use the same 2637 * bit to control gating but they are parented to a different mux, 2638 * hence if our intention is to gate only the source, required 2639 * during a clk mode switch to avoid hw hangs, we need to gate 2640 * its parent (specified as a different clock only on new DTs). 2641 */ 2642 if (!host->src_clk_cg) { 2643 host->src_clk_cg = clk_get_parent(host->src_clk); 2644 if (IS_ERR(host->src_clk_cg)) 2645 return PTR_ERR(host->src_clk_cg); 2646 } 2647 2648 /* If present, always enable for this clock gate */ 2649 host->sys_clk_cg = devm_clk_get_optional_enabled(&pdev->dev, "sys_cg"); 2650 if (IS_ERR(host->sys_clk_cg)) 2651 host->sys_clk_cg = NULL; 2652 2653 host->bulk_clks[0].id = "pclk_cg"; 2654 host->bulk_clks[1].id = "axi_cg"; 2655 host->bulk_clks[2].id = "ahb_cg"; 2656 ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS, 2657 host->bulk_clks); 2658 if (ret) { 2659 dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n"); 2660 return ret; 2661 } 2662 2663 return 0; 2664 } 2665 2666 static int msdc_drv_probe(struct platform_device *pdev) 2667 { 2668 struct mmc_host *mmc; 2669 struct msdc_host *host; 2670 struct resource *res; 2671 int ret; 2672 2673 if (!pdev->dev.of_node) { 2674 dev_err(&pdev->dev, "No DT found\n"); 2675 return -EINVAL; 2676 } 2677 2678 /* Allocate MMC host for this device */ 2679 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 2680 if (!mmc) 2681 return -ENOMEM; 2682 2683 host = mmc_priv(mmc); 2684 ret = mmc_of_parse(mmc); 2685 if (ret) 2686 goto host_free; 2687 2688 host->base = devm_platform_ioremap_resource(pdev, 0); 2689 if (IS_ERR(host->base)) { 2690 ret = PTR_ERR(host->base); 2691 goto host_free; 2692 } 2693 2694 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2695 if (res) { 2696 host->top_base = devm_ioremap_resource(&pdev->dev, res); 2697 if (IS_ERR(host->top_base)) 2698 host->top_base = NULL; 2699 } 2700 2701 ret = mmc_regulator_get_supply(mmc); 2702 if (ret) 2703 goto host_free; 2704 2705 ret = msdc_of_clock_parse(pdev, host); 2706 if (ret) 2707 goto host_free; 2708 2709 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 2710 "hrst"); 2711 if (IS_ERR(host->reset)) { 2712 ret = PTR_ERR(host->reset); 2713 goto host_free; 2714 } 2715 2716 /* only eMMC has crypto property */ 2717 if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) { 2718 host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto"); 2719 if (IS_ERR(host->crypto_clk)) 2720 host->crypto_clk = NULL; 2721 else 2722 mmc->caps2 |= MMC_CAP2_CRYPTO; 2723 } 2724 2725 host->irq = platform_get_irq(pdev, 0); 2726 if (host->irq < 0) { 2727 ret = -EINVAL; 2728 goto host_free; 2729 } 2730 2731 host->pinctrl = devm_pinctrl_get(&pdev->dev); 2732 if (IS_ERR(host->pinctrl)) { 2733 ret = PTR_ERR(host->pinctrl); 2734 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 2735 goto host_free; 2736 } 2737 2738 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 2739 if (IS_ERR(host->pins_default)) { 2740 ret = PTR_ERR(host->pins_default); 2741 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 2742 goto host_free; 2743 } 2744 2745 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 2746 if (IS_ERR(host->pins_uhs)) { 2747 ret = PTR_ERR(host->pins_uhs); 2748 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 2749 goto host_free; 2750 } 2751 2752 /* Support for SDIO eint irq ? */ 2753 if ((mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) && (mmc->pm_caps & MMC_PM_KEEP_POWER)) { 2754 host->eint_irq = platform_get_irq_byname_optional(pdev, "sdio_wakeup"); 2755 if (host->eint_irq > 0) { 2756 host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint"); 2757 if (IS_ERR(host->pins_eint)) { 2758 dev_err(&pdev->dev, "Cannot find pinctrl eint!\n"); 2759 host->pins_eint = NULL; 2760 } else { 2761 device_init_wakeup(&pdev->dev, true); 2762 } 2763 } 2764 } 2765 2766 msdc_of_property_parse(pdev, host); 2767 2768 host->dev = &pdev->dev; 2769 host->dev_comp = of_device_get_match_data(&pdev->dev); 2770 host->src_clk_freq = clk_get_rate(host->src_clk); 2771 /* Set host parameters to mmc */ 2772 mmc->ops = &mt_msdc_ops; 2773 if (host->dev_comp->clk_div_bits == 8) 2774 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 2775 else 2776 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); 2777 2778 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && 2779 !mmc_can_gpio_cd(mmc) && 2780 host->dev_comp->use_internal_cd) { 2781 /* 2782 * Is removable but no GPIO declared, so 2783 * use internal functionality. 2784 */ 2785 host->internal_cd = true; 2786 } 2787 2788 if (mmc->caps & MMC_CAP_SDIO_IRQ) 2789 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2790 2791 mmc->caps |= MMC_CAP_CMD23; 2792 if (host->cqhci) 2793 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 2794 /* MMC core transfer sizes tunable parameters */ 2795 mmc->max_segs = MAX_BD_NUM; 2796 if (host->dev_comp->support_64g) 2797 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; 2798 else 2799 mmc->max_seg_size = BDMA_DESC_BUFLEN; 2800 mmc->max_blk_size = 2048; 2801 mmc->max_req_size = 512 * 1024; 2802 mmc->max_blk_count = mmc->max_req_size / 512; 2803 if (host->dev_comp->support_64g) 2804 host->dma_mask = DMA_BIT_MASK(36); 2805 else 2806 host->dma_mask = DMA_BIT_MASK(32); 2807 mmc_dev(mmc)->dma_mask = &host->dma_mask; 2808 2809 host->timeout_clks = 3 * 1048576; 2810 host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2811 2 * sizeof(struct mt_gpdma_desc), 2812 &host->dma.gpd_addr, GFP_KERNEL); 2813 host->dma.bd = dma_alloc_coherent(&pdev->dev, 2814 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2815 &host->dma.bd_addr, GFP_KERNEL); 2816 if (!host->dma.gpd || !host->dma.bd) { 2817 ret = -ENOMEM; 2818 goto release_mem; 2819 } 2820 msdc_init_gpd_bd(host, &host->dma); 2821 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 2822 spin_lock_init(&host->lock); 2823 2824 platform_set_drvdata(pdev, mmc); 2825 ret = msdc_ungate_clock(host); 2826 if (ret) { 2827 dev_err(&pdev->dev, "Cannot ungate clocks!\n"); 2828 goto release_mem; 2829 } 2830 msdc_init_hw(host); 2831 2832 if (mmc->caps2 & MMC_CAP2_CQE) { 2833 host->cq_host = devm_kzalloc(mmc->parent, 2834 sizeof(*host->cq_host), 2835 GFP_KERNEL); 2836 if (!host->cq_host) { 2837 ret = -ENOMEM; 2838 goto host_free; 2839 } 2840 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 2841 host->cq_host->mmio = host->base + 0x800; 2842 host->cq_host->ops = &msdc_cmdq_ops; 2843 ret = cqhci_init(host->cq_host, mmc, true); 2844 if (ret) 2845 goto host_free; 2846 mmc->max_segs = 128; 2847 /* cqhci 16bit length */ 2848 /* 0 size, means 65536 so we don't have to -1 here */ 2849 mmc->max_seg_size = 64 * 1024; 2850 /* Reduce CIT to 0x40 that corresponds to 2.35us */ 2851 msdc_cqe_cit_cal(host, 2350); 2852 } 2853 2854 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 2855 IRQF_TRIGGER_NONE, pdev->name, host); 2856 if (ret) 2857 goto release; 2858 2859 pm_runtime_set_active(host->dev); 2860 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 2861 pm_runtime_use_autosuspend(host->dev); 2862 pm_runtime_enable(host->dev); 2863 ret = mmc_add_host(mmc); 2864 2865 if (ret) 2866 goto end; 2867 2868 return 0; 2869 end: 2870 pm_runtime_disable(host->dev); 2871 release: 2872 platform_set_drvdata(pdev, NULL); 2873 msdc_deinit_hw(host); 2874 msdc_gate_clock(host); 2875 release_mem: 2876 if (host->dma.gpd) 2877 dma_free_coherent(&pdev->dev, 2878 2 * sizeof(struct mt_gpdma_desc), 2879 host->dma.gpd, host->dma.gpd_addr); 2880 if (host->dma.bd) 2881 dma_free_coherent(&pdev->dev, 2882 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2883 host->dma.bd, host->dma.bd_addr); 2884 host_free: 2885 mmc_free_host(mmc); 2886 2887 return ret; 2888 } 2889 2890 static int msdc_drv_remove(struct platform_device *pdev) 2891 { 2892 struct mmc_host *mmc; 2893 struct msdc_host *host; 2894 2895 mmc = platform_get_drvdata(pdev); 2896 host = mmc_priv(mmc); 2897 2898 pm_runtime_get_sync(host->dev); 2899 2900 platform_set_drvdata(pdev, NULL); 2901 mmc_remove_host(mmc); 2902 msdc_deinit_hw(host); 2903 msdc_gate_clock(host); 2904 2905 pm_runtime_disable(host->dev); 2906 pm_runtime_put_noidle(host->dev); 2907 dma_free_coherent(&pdev->dev, 2908 2 * sizeof(struct mt_gpdma_desc), 2909 host->dma.gpd, host->dma.gpd_addr); 2910 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2911 host->dma.bd, host->dma.bd_addr); 2912 2913 mmc_free_host(mmc); 2914 2915 return 0; 2916 } 2917 2918 static void msdc_save_reg(struct msdc_host *host) 2919 { 2920 u32 tune_reg = host->dev_comp->pad_tune_reg; 2921 2922 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 2923 host->save_para.iocon = readl(host->base + MSDC_IOCON); 2924 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 2925 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 2926 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 2927 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); 2928 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 2929 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2930 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 2931 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); 2932 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); 2933 if (host->top_base) { 2934 host->save_para.emmc_top_control = 2935 readl(host->top_base + EMMC_TOP_CONTROL); 2936 host->save_para.emmc_top_cmd = 2937 readl(host->top_base + EMMC_TOP_CMD); 2938 host->save_para.emmc50_pad_ds_tune = 2939 readl(host->top_base + EMMC50_PAD_DS_TUNE); 2940 } else { 2941 host->save_para.pad_tune = readl(host->base + tune_reg); 2942 } 2943 } 2944 2945 static void msdc_restore_reg(struct msdc_host *host) 2946 { 2947 struct mmc_host *mmc = mmc_from_priv(host); 2948 u32 tune_reg = host->dev_comp->pad_tune_reg; 2949 2950 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 2951 writel(host->save_para.iocon, host->base + MSDC_IOCON); 2952 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 2953 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 2954 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 2955 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); 2956 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 2957 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 2958 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 2959 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); 2960 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); 2961 if (host->top_base) { 2962 writel(host->save_para.emmc_top_control, 2963 host->top_base + EMMC_TOP_CONTROL); 2964 writel(host->save_para.emmc_top_cmd, 2965 host->top_base + EMMC_TOP_CMD); 2966 writel(host->save_para.emmc50_pad_ds_tune, 2967 host->top_base + EMMC50_PAD_DS_TUNE); 2968 } else { 2969 writel(host->save_para.pad_tune, host->base + tune_reg); 2970 } 2971 2972 if (sdio_irq_claimed(mmc)) 2973 __msdc_enable_sdio_irq(host, 1); 2974 } 2975 2976 static int __maybe_unused msdc_runtime_suspend(struct device *dev) 2977 { 2978 struct mmc_host *mmc = dev_get_drvdata(dev); 2979 struct msdc_host *host = mmc_priv(mmc); 2980 2981 msdc_save_reg(host); 2982 2983 if (sdio_irq_claimed(mmc)) { 2984 if (host->pins_eint) { 2985 disable_irq(host->irq); 2986 pinctrl_select_state(host->pinctrl, host->pins_eint); 2987 } 2988 2989 __msdc_enable_sdio_irq(host, 0); 2990 } 2991 msdc_gate_clock(host); 2992 return 0; 2993 } 2994 2995 static int __maybe_unused msdc_runtime_resume(struct device *dev) 2996 { 2997 struct mmc_host *mmc = dev_get_drvdata(dev); 2998 struct msdc_host *host = mmc_priv(mmc); 2999 int ret; 3000 3001 ret = msdc_ungate_clock(host); 3002 if (ret) 3003 return ret; 3004 3005 msdc_restore_reg(host); 3006 3007 if (sdio_irq_claimed(mmc) && host->pins_eint) { 3008 pinctrl_select_state(host->pinctrl, host->pins_uhs); 3009 enable_irq(host->irq); 3010 } 3011 return 0; 3012 } 3013 3014 static int __maybe_unused msdc_suspend(struct device *dev) 3015 { 3016 struct mmc_host *mmc = dev_get_drvdata(dev); 3017 struct msdc_host *host = mmc_priv(mmc); 3018 int ret; 3019 u32 val; 3020 3021 if (mmc->caps2 & MMC_CAP2_CQE) { 3022 ret = cqhci_suspend(mmc); 3023 if (ret) 3024 return ret; 3025 val = readl(host->base + MSDC_INT); 3026 writel(val, host->base + MSDC_INT); 3027 } 3028 3029 /* 3030 * Bump up runtime PM usage counter otherwise dev->power.needs_force_resume will 3031 * not be marked as 1, pm_runtime_force_resume() will go out directly. 3032 */ 3033 if (sdio_irq_claimed(mmc) && host->pins_eint) 3034 pm_runtime_get_noresume(dev); 3035 3036 return pm_runtime_force_suspend(dev); 3037 } 3038 3039 static int __maybe_unused msdc_resume(struct device *dev) 3040 { 3041 struct mmc_host *mmc = dev_get_drvdata(dev); 3042 struct msdc_host *host = mmc_priv(mmc); 3043 3044 if (sdio_irq_claimed(mmc) && host->pins_eint) 3045 pm_runtime_put_noidle(dev); 3046 3047 return pm_runtime_force_resume(dev); 3048 } 3049 3050 static const struct dev_pm_ops msdc_dev_pm_ops = { 3051 SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume) 3052 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 3053 }; 3054 3055 static struct platform_driver mt_msdc_driver = { 3056 .probe = msdc_drv_probe, 3057 .remove = msdc_drv_remove, 3058 .driver = { 3059 .name = "mtk-msdc", 3060 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 3061 .of_match_table = msdc_of_ids, 3062 .pm = &msdc_dev_pm_ops, 3063 }, 3064 }; 3065 3066 module_platform_driver(mt_msdc_driver); 3067 MODULE_LICENSE("GPL v2"); 3068 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 3069