1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2015 MediaTek Inc. 4 * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 5 */ 6 7 #include <linux/module.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/ioport.h> 12 #include <linux/irq.h> 13 #include <linux/of_address.h> 14 #include <linux/of_device.h> 15 #include <linux/of_irq.h> 16 #include <linux/of_gpio.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/slab.h> 23 #include <linux/spinlock.h> 24 #include <linux/interrupt.h> 25 #include <linux/reset.h> 26 27 #include <linux/mmc/card.h> 28 #include <linux/mmc/core.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/mmc.h> 31 #include <linux/mmc/sd.h> 32 #include <linux/mmc/sdio.h> 33 #include <linux/mmc/slot-gpio.h> 34 35 #include "cqhci.h" 36 37 #define MAX_BD_NUM 1024 38 #define MSDC_NR_CLOCKS 3 39 40 /*--------------------------------------------------------------------------*/ 41 /* Common Definition */ 42 /*--------------------------------------------------------------------------*/ 43 #define MSDC_BUS_1BITS 0x0 44 #define MSDC_BUS_4BITS 0x1 45 #define MSDC_BUS_8BITS 0x2 46 47 #define MSDC_BURST_64B 0x6 48 49 /*--------------------------------------------------------------------------*/ 50 /* Register Offset */ 51 /*--------------------------------------------------------------------------*/ 52 #define MSDC_CFG 0x0 53 #define MSDC_IOCON 0x04 54 #define MSDC_PS 0x08 55 #define MSDC_INT 0x0c 56 #define MSDC_INTEN 0x10 57 #define MSDC_FIFOCS 0x14 58 #define SDC_CFG 0x30 59 #define SDC_CMD 0x34 60 #define SDC_ARG 0x38 61 #define SDC_STS 0x3c 62 #define SDC_RESP0 0x40 63 #define SDC_RESP1 0x44 64 #define SDC_RESP2 0x48 65 #define SDC_RESP3 0x4c 66 #define SDC_BLK_NUM 0x50 67 #define SDC_ADV_CFG0 0x64 68 #define EMMC_IOCON 0x7c 69 #define SDC_ACMD_RESP 0x80 70 #define DMA_SA_H4BIT 0x8c 71 #define MSDC_DMA_SA 0x90 72 #define MSDC_DMA_CTRL 0x98 73 #define MSDC_DMA_CFG 0x9c 74 #define MSDC_PATCH_BIT 0xb0 75 #define MSDC_PATCH_BIT1 0xb4 76 #define MSDC_PATCH_BIT2 0xb8 77 #define MSDC_PAD_TUNE 0xec 78 #define MSDC_PAD_TUNE0 0xf0 79 #define PAD_DS_TUNE 0x188 80 #define PAD_CMD_TUNE 0x18c 81 #define EMMC51_CFG0 0x204 82 #define EMMC50_CFG0 0x208 83 #define EMMC50_CFG1 0x20c 84 #define EMMC50_CFG3 0x220 85 #define SDC_FIFO_CFG 0x228 86 #define CQHCI_SETTING 0x7fc 87 88 /*--------------------------------------------------------------------------*/ 89 /* Top Pad Register Offset */ 90 /*--------------------------------------------------------------------------*/ 91 #define EMMC_TOP_CONTROL 0x00 92 #define EMMC_TOP_CMD 0x04 93 #define EMMC50_PAD_DS_TUNE 0x0c 94 95 /*--------------------------------------------------------------------------*/ 96 /* Register Mask */ 97 /*--------------------------------------------------------------------------*/ 98 99 /* MSDC_CFG mask */ 100 #define MSDC_CFG_MODE (0x1 << 0) /* RW */ 101 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ 102 #define MSDC_CFG_RST (0x1 << 2) /* RW */ 103 #define MSDC_CFG_PIO (0x1 << 3) /* RW */ 104 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ 105 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ 106 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ 107 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ 108 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ 109 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ 110 #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */ 111 #define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */ 112 #define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */ 113 #define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */ 114 115 /* MSDC_IOCON mask */ 116 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ 117 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ 118 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ 119 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ 120 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ 121 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ 122 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ 123 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ 124 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ 125 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ 126 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ 127 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ 128 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ 129 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ 130 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ 131 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ 132 133 /* MSDC_PS mask */ 134 #define MSDC_PS_CDEN (0x1 << 0) /* RW */ 135 #define MSDC_PS_CDSTS (0x1 << 1) /* R */ 136 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ 137 #define MSDC_PS_DAT (0xff << 16) /* R */ 138 #define MSDC_PS_DATA1 (0x1 << 17) /* R */ 139 #define MSDC_PS_CMD (0x1 << 24) /* R */ 140 #define MSDC_PS_WP (0x1 << 31) /* R */ 141 142 /* MSDC_INT mask */ 143 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ 144 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ 145 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ 146 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ 147 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ 148 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ 149 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ 150 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ 151 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ 152 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ 153 #define MSDC_INT_CSTA (0x1 << 11) /* R */ 154 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ 155 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ 156 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ 157 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ 158 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ 159 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ 160 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ 161 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ 162 #define MSDC_INT_CMDQ (0x1 << 28) /* W1C */ 163 164 /* MSDC_INTEN mask */ 165 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ 166 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ 167 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ 168 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ 169 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ 170 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ 171 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ 172 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ 173 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ 174 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ 175 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ 176 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ 177 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ 178 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ 179 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ 180 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ 181 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ 182 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ 183 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ 184 185 /* MSDC_FIFOCS mask */ 186 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 187 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 188 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ 189 190 /* SDC_CFG mask */ 191 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ 192 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ 193 #define SDC_CFG_WRDTOC (0x1fff << 2) /* RW */ 194 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 195 #define SDC_CFG_SDIO (0x1 << 19) /* RW */ 196 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 197 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ 198 #define SDC_CFG_DTOC (0xff << 24) /* RW */ 199 200 /* SDC_STS mask */ 201 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ 202 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 203 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ 204 205 #define SDC_DAT1_IRQ_TRIGGER (0x1 << 19) /* RW */ 206 /* SDC_ADV_CFG0 mask */ 207 #define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */ 208 209 /* DMA_SA_H4BIT mask */ 210 #define DMA_ADDR_HIGH_4BIT (0xf << 0) /* RW */ 211 212 /* MSDC_DMA_CTRL mask */ 213 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ 214 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ 215 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ 216 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ 217 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ 218 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ 219 220 /* MSDC_DMA_CFG mask */ 221 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ 222 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ 223 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ 224 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ 225 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ 226 227 /* MSDC_PATCH_BIT mask */ 228 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ 229 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) 230 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) 231 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ 232 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ 233 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ 234 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ 235 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ 236 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ 237 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ 238 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ 239 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ 240 241 #define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */ 242 #define MSDC_PB1_BUSY_CHECK_SEL (0x1 << 7) /* RW */ 243 #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ 244 245 #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ 246 #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */ 247 #define MSDC_PB2_SUPPORT_64G (0x1 << 1) /* RW */ 248 #define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */ 249 #define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */ 250 #define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */ 251 252 #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */ 253 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */ 254 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */ 255 #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */ 256 #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */ 257 #define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */ 258 #define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */ 259 #define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */ 260 261 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */ 262 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */ 263 #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */ 264 265 #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */ 266 267 /* EMMC51_CFG0 mask */ 268 #define CMDQ_RDAT_CNT (0x3ff << 12) /* RW */ 269 270 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */ 271 #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ 272 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ 273 #define EMMC50_CFG_CMD_RESP_SEL (0x1 << 9) /* RW */ 274 275 /* EMMC50_CFG1 mask */ 276 #define EMMC50_CFG1_DS_CFG (0x1 << 28) /* RW */ 277 278 #define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */ 279 280 #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */ 281 #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */ 282 283 /* CQHCI_SETTING */ 284 #define CQHCI_RD_CMD_WND_SEL (0x1 << 14) /* RW */ 285 #define CQHCI_WR_CMD_WND_SEL (0x1 << 15) /* RW */ 286 287 /* EMMC_TOP_CONTROL mask */ 288 #define PAD_RXDLY_SEL (0x1 << 0) /* RW */ 289 #define DELAY_EN (0x1 << 1) /* RW */ 290 #define PAD_DAT_RD_RXDLY2 (0x1f << 2) /* RW */ 291 #define PAD_DAT_RD_RXDLY (0x1f << 7) /* RW */ 292 #define PAD_DAT_RD_RXDLY2_SEL (0x1 << 12) /* RW */ 293 #define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */ 294 #define DATA_K_VALUE_SEL (0x1 << 14) /* RW */ 295 #define SDC_RX_ENH_EN (0x1 << 15) /* TW */ 296 297 /* EMMC_TOP_CMD mask */ 298 #define PAD_CMD_RXDLY2 (0x1f << 0) /* RW */ 299 #define PAD_CMD_RXDLY (0x1f << 5) /* RW */ 300 #define PAD_CMD_RD_RXDLY2_SEL (0x1 << 10) /* RW */ 301 #define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */ 302 #define PAD_CMD_TX_DLY (0x1f << 12) /* RW */ 303 304 #define REQ_CMD_EIO (0x1 << 0) 305 #define REQ_CMD_TMO (0x1 << 1) 306 #define REQ_DAT_ERR (0x1 << 2) 307 #define REQ_STOP_EIO (0x1 << 3) 308 #define REQ_STOP_TMO (0x1 << 4) 309 #define REQ_CMD_BUSY (0x1 << 5) 310 311 #define MSDC_PREPARE_FLAG (0x1 << 0) 312 #define MSDC_ASYNC_FLAG (0x1 << 1) 313 #define MSDC_MMAP_FLAG (0x1 << 2) 314 315 #define MTK_MMC_AUTOSUSPEND_DELAY 50 316 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 317 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 318 319 #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */ 320 321 #define PAD_DELAY_MAX 32 /* PAD delay cells */ 322 /*--------------------------------------------------------------------------*/ 323 /* Descriptor Structure */ 324 /*--------------------------------------------------------------------------*/ 325 struct mt_gpdma_desc { 326 u32 gpd_info; 327 #define GPDMA_DESC_HWO (0x1 << 0) 328 #define GPDMA_DESC_BDP (0x1 << 1) 329 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 330 #define GPDMA_DESC_INT (0x1 << 16) 331 #define GPDMA_DESC_NEXT_H4 (0xf << 24) 332 #define GPDMA_DESC_PTR_H4 (0xf << 28) 333 u32 next; 334 u32 ptr; 335 u32 gpd_data_len; 336 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 337 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ 338 u32 arg; 339 u32 blknum; 340 u32 cmd; 341 }; 342 343 struct mt_bdma_desc { 344 u32 bd_info; 345 #define BDMA_DESC_EOL (0x1 << 0) 346 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 347 #define BDMA_DESC_BLKPAD (0x1 << 17) 348 #define BDMA_DESC_DWPAD (0x1 << 18) 349 #define BDMA_DESC_NEXT_H4 (0xf << 24) 350 #define BDMA_DESC_PTR_H4 (0xf << 28) 351 u32 next; 352 u32 ptr; 353 u32 bd_data_len; 354 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 355 #define BDMA_DESC_BUFLEN_EXT (0xffffff) /* bit0 ~ bit23 */ 356 }; 357 358 struct msdc_dma { 359 struct scatterlist *sg; /* I/O scatter list */ 360 struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 361 struct mt_bdma_desc *bd; /* pointer to bd array */ 362 dma_addr_t gpd_addr; /* the physical address of gpd array */ 363 dma_addr_t bd_addr; /* the physical address of bd array */ 364 }; 365 366 struct msdc_save_para { 367 u32 msdc_cfg; 368 u32 iocon; 369 u32 sdc_cfg; 370 u32 pad_tune; 371 u32 patch_bit0; 372 u32 patch_bit1; 373 u32 patch_bit2; 374 u32 pad_ds_tune; 375 u32 pad_cmd_tune; 376 u32 emmc50_cfg0; 377 u32 emmc50_cfg3; 378 u32 sdc_fifo_cfg; 379 u32 emmc_top_control; 380 u32 emmc_top_cmd; 381 u32 emmc50_pad_ds_tune; 382 }; 383 384 struct mtk_mmc_compatible { 385 u8 clk_div_bits; 386 bool recheck_sdio_irq; 387 bool hs400_tune; /* only used for MT8173 */ 388 u32 pad_tune_reg; 389 bool async_fifo; 390 bool data_tune; 391 bool busy_check; 392 bool stop_clk_fix; 393 bool enhance_rx; 394 bool support_64g; 395 bool use_internal_cd; 396 }; 397 398 struct msdc_tune_para { 399 u32 iocon; 400 u32 pad_tune; 401 u32 pad_cmd_tune; 402 u32 emmc_top_control; 403 u32 emmc_top_cmd; 404 }; 405 406 struct msdc_delay_phase { 407 u8 maxlen; 408 u8 start; 409 u8 final_phase; 410 }; 411 412 struct msdc_host { 413 struct device *dev; 414 const struct mtk_mmc_compatible *dev_comp; 415 int cmd_rsp; 416 417 spinlock_t lock; 418 struct mmc_request *mrq; 419 struct mmc_command *cmd; 420 struct mmc_data *data; 421 int error; 422 423 void __iomem *base; /* host base address */ 424 void __iomem *top_base; /* host top register base address */ 425 426 struct msdc_dma dma; /* dma channel */ 427 u64 dma_mask; 428 429 u32 timeout_ns; /* data timeout ns */ 430 u32 timeout_clks; /* data timeout clks */ 431 432 struct pinctrl *pinctrl; 433 struct pinctrl_state *pins_default; 434 struct pinctrl_state *pins_uhs; 435 struct delayed_work req_timeout; 436 int irq; /* host interrupt */ 437 struct reset_control *reset; 438 439 struct clk *src_clk; /* msdc source clock */ 440 struct clk *h_clk; /* msdc h_clk */ 441 struct clk *bus_clk; /* bus clock which used to access register */ 442 struct clk *src_clk_cg; /* msdc source clock control gate */ 443 struct clk *sys_clk_cg; /* msdc subsys clock control gate */ 444 struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS]; 445 u32 mclk; /* mmc subsystem clock frequency */ 446 u32 src_clk_freq; /* source clock frequency */ 447 unsigned char timing; 448 bool vqmmc_enabled; 449 u32 latch_ck; 450 u32 hs400_ds_delay; 451 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 452 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 453 bool hs400_cmd_resp_sel_rising; 454 /* cmd response sample selection for HS400 */ 455 bool hs400_mode; /* current eMMC will run at hs400 mode */ 456 bool internal_cd; /* Use internal card-detect logic */ 457 bool cqhci; /* support eMMC hw cmdq */ 458 struct msdc_save_para save_para; /* used when gate HCLK */ 459 struct msdc_tune_para def_tune_para; /* default tune setting */ 460 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 461 struct cqhci_host *cq_host; 462 }; 463 464 static const struct mtk_mmc_compatible mt8135_compat = { 465 .clk_div_bits = 8, 466 .recheck_sdio_irq = true, 467 .hs400_tune = false, 468 .pad_tune_reg = MSDC_PAD_TUNE, 469 .async_fifo = false, 470 .data_tune = false, 471 .busy_check = false, 472 .stop_clk_fix = false, 473 .enhance_rx = false, 474 .support_64g = false, 475 }; 476 477 static const struct mtk_mmc_compatible mt8173_compat = { 478 .clk_div_bits = 8, 479 .recheck_sdio_irq = true, 480 .hs400_tune = true, 481 .pad_tune_reg = MSDC_PAD_TUNE, 482 .async_fifo = false, 483 .data_tune = false, 484 .busy_check = false, 485 .stop_clk_fix = false, 486 .enhance_rx = false, 487 .support_64g = false, 488 }; 489 490 static const struct mtk_mmc_compatible mt8183_compat = { 491 .clk_div_bits = 12, 492 .recheck_sdio_irq = false, 493 .hs400_tune = false, 494 .pad_tune_reg = MSDC_PAD_TUNE0, 495 .async_fifo = true, 496 .data_tune = true, 497 .busy_check = true, 498 .stop_clk_fix = true, 499 .enhance_rx = true, 500 .support_64g = true, 501 }; 502 503 static const struct mtk_mmc_compatible mt2701_compat = { 504 .clk_div_bits = 12, 505 .recheck_sdio_irq = true, 506 .hs400_tune = false, 507 .pad_tune_reg = MSDC_PAD_TUNE0, 508 .async_fifo = true, 509 .data_tune = true, 510 .busy_check = false, 511 .stop_clk_fix = false, 512 .enhance_rx = false, 513 .support_64g = false, 514 }; 515 516 static const struct mtk_mmc_compatible mt2712_compat = { 517 .clk_div_bits = 12, 518 .recheck_sdio_irq = false, 519 .hs400_tune = false, 520 .pad_tune_reg = MSDC_PAD_TUNE0, 521 .async_fifo = true, 522 .data_tune = true, 523 .busy_check = true, 524 .stop_clk_fix = true, 525 .enhance_rx = true, 526 .support_64g = true, 527 }; 528 529 static const struct mtk_mmc_compatible mt7622_compat = { 530 .clk_div_bits = 12, 531 .recheck_sdio_irq = true, 532 .hs400_tune = false, 533 .pad_tune_reg = MSDC_PAD_TUNE0, 534 .async_fifo = true, 535 .data_tune = true, 536 .busy_check = true, 537 .stop_clk_fix = true, 538 .enhance_rx = true, 539 .support_64g = false, 540 }; 541 542 static const struct mtk_mmc_compatible mt8516_compat = { 543 .clk_div_bits = 12, 544 .recheck_sdio_irq = true, 545 .hs400_tune = false, 546 .pad_tune_reg = MSDC_PAD_TUNE0, 547 .async_fifo = true, 548 .data_tune = true, 549 .busy_check = true, 550 .stop_clk_fix = true, 551 }; 552 553 static const struct mtk_mmc_compatible mt7620_compat = { 554 .clk_div_bits = 8, 555 .recheck_sdio_irq = true, 556 .hs400_tune = false, 557 .pad_tune_reg = MSDC_PAD_TUNE, 558 .async_fifo = false, 559 .data_tune = false, 560 .busy_check = false, 561 .stop_clk_fix = false, 562 .enhance_rx = false, 563 .use_internal_cd = true, 564 }; 565 566 static const struct mtk_mmc_compatible mt6779_compat = { 567 .clk_div_bits = 12, 568 .recheck_sdio_irq = false, 569 .hs400_tune = false, 570 .pad_tune_reg = MSDC_PAD_TUNE0, 571 .async_fifo = true, 572 .data_tune = true, 573 .busy_check = true, 574 .stop_clk_fix = true, 575 .enhance_rx = true, 576 .support_64g = true, 577 }; 578 579 static const struct of_device_id msdc_of_ids[] = { 580 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, 581 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, 582 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, 583 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, 584 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, 585 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, 586 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, 587 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, 588 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, 589 {} 590 }; 591 MODULE_DEVICE_TABLE(of, msdc_of_ids); 592 593 static void sdr_set_bits(void __iomem *reg, u32 bs) 594 { 595 u32 val = readl(reg); 596 597 val |= bs; 598 writel(val, reg); 599 } 600 601 static void sdr_clr_bits(void __iomem *reg, u32 bs) 602 { 603 u32 val = readl(reg); 604 605 val &= ~bs; 606 writel(val, reg); 607 } 608 609 static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 610 { 611 unsigned int tv = readl(reg); 612 613 tv &= ~field; 614 tv |= ((val) << (ffs((unsigned int)field) - 1)); 615 writel(tv, reg); 616 } 617 618 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 619 { 620 unsigned int tv = readl(reg); 621 622 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 623 } 624 625 static void msdc_reset_hw(struct msdc_host *host) 626 { 627 u32 val; 628 629 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 630 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) 631 cpu_relax(); 632 633 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 634 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) 635 cpu_relax(); 636 637 val = readl(host->base + MSDC_INT); 638 writel(val, host->base + MSDC_INT); 639 } 640 641 static void msdc_cmd_next(struct msdc_host *host, 642 struct mmc_request *mrq, struct mmc_command *cmd); 643 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb); 644 645 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 646 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 647 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 648 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 649 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 650 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 651 652 static u8 msdc_dma_calcs(u8 *buf, u32 len) 653 { 654 u32 i, sum = 0; 655 656 for (i = 0; i < len; i++) 657 sum += buf[i]; 658 return 0xff - (u8) sum; 659 } 660 661 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 662 struct mmc_data *data) 663 { 664 unsigned int j, dma_len; 665 dma_addr_t dma_address; 666 u32 dma_ctrl; 667 struct scatterlist *sg; 668 struct mt_gpdma_desc *gpd; 669 struct mt_bdma_desc *bd; 670 671 sg = data->sg; 672 673 gpd = dma->gpd; 674 bd = dma->bd; 675 676 /* modify gpd */ 677 gpd->gpd_info |= GPDMA_DESC_HWO; 678 gpd->gpd_info |= GPDMA_DESC_BDP; 679 /* need to clear first. use these bits to calc checksum */ 680 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 681 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 682 683 /* modify bd */ 684 for_each_sg(data->sg, sg, data->sg_count, j) { 685 dma_address = sg_dma_address(sg); 686 dma_len = sg_dma_len(sg); 687 688 /* init bd */ 689 bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 690 bd[j].bd_info &= ~BDMA_DESC_DWPAD; 691 bd[j].ptr = lower_32_bits(dma_address); 692 if (host->dev_comp->support_64g) { 693 bd[j].bd_info &= ~BDMA_DESC_PTR_H4; 694 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf) 695 << 28; 696 } 697 698 if (host->dev_comp->support_64g) { 699 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT; 700 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT); 701 } else { 702 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 703 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 704 } 705 706 if (j == data->sg_count - 1) /* the last bd */ 707 bd[j].bd_info |= BDMA_DESC_EOL; 708 else 709 bd[j].bd_info &= ~BDMA_DESC_EOL; 710 711 /* checksume need to clear first */ 712 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 713 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 714 } 715 716 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 717 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 718 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 719 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); 720 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 721 if (host->dev_comp->support_64g) 722 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, 723 upper_32_bits(dma->gpd_addr) & 0xf); 724 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); 725 } 726 727 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq) 728 { 729 struct mmc_data *data = mrq->data; 730 731 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 732 data->host_cookie |= MSDC_PREPARE_FLAG; 733 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 734 mmc_get_dma_dir(data)); 735 } 736 } 737 738 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) 739 { 740 struct mmc_data *data = mrq->data; 741 742 if (data->host_cookie & MSDC_ASYNC_FLAG) 743 return; 744 745 if (data->host_cookie & MSDC_PREPARE_FLAG) { 746 dma_unmap_sg(host->dev, data->sg, data->sg_len, 747 mmc_get_dma_dir(data)); 748 data->host_cookie &= ~MSDC_PREPARE_FLAG; 749 } 750 } 751 752 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) 753 { 754 struct mmc_host *mmc = mmc_from_priv(host); 755 u64 timeout, clk_ns; 756 u32 mode = 0; 757 758 if (mmc->actual_clock == 0) { 759 timeout = 0; 760 } else { 761 clk_ns = 1000000000ULL; 762 do_div(clk_ns, mmc->actual_clock); 763 timeout = ns + clk_ns - 1; 764 do_div(timeout, clk_ns); 765 timeout += clks; 766 /* in 1048576 sclk cycle unit */ 767 timeout = DIV_ROUND_UP(timeout, (0x1 << 20)); 768 if (host->dev_comp->clk_div_bits == 8) 769 sdr_get_field(host->base + MSDC_CFG, 770 MSDC_CFG_CKMOD, &mode); 771 else 772 sdr_get_field(host->base + MSDC_CFG, 773 MSDC_CFG_CKMOD_EXTRA, &mode); 774 /*DDR mode will double the clk cycles for data timeout */ 775 timeout = mode >= 2 ? timeout * 2 : timeout; 776 timeout = timeout > 1 ? timeout - 1 : 0; 777 } 778 return timeout; 779 } 780 781 /* clock control primitives */ 782 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) 783 { 784 u64 timeout; 785 786 host->timeout_ns = ns; 787 host->timeout_clks = clks; 788 789 timeout = msdc_timeout_cal(host, ns, clks); 790 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 791 (u32)(timeout > 255 ? 255 : timeout)); 792 } 793 794 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) 795 { 796 u64 timeout; 797 798 timeout = msdc_timeout_cal(host, ns, clks); 799 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, 800 (u32)(timeout > 8191 ? 8191 : timeout)); 801 } 802 803 static void msdc_gate_clock(struct msdc_host *host) 804 { 805 clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); 806 clk_disable_unprepare(host->src_clk_cg); 807 clk_disable_unprepare(host->src_clk); 808 clk_disable_unprepare(host->bus_clk); 809 clk_disable_unprepare(host->h_clk); 810 } 811 812 static void msdc_ungate_clock(struct msdc_host *host) 813 { 814 int ret; 815 816 clk_prepare_enable(host->h_clk); 817 clk_prepare_enable(host->bus_clk); 818 clk_prepare_enable(host->src_clk); 819 clk_prepare_enable(host->src_clk_cg); 820 ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); 821 if (ret) { 822 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); 823 return; 824 } 825 826 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 827 cpu_relax(); 828 } 829 830 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 831 { 832 struct mmc_host *mmc = mmc_from_priv(host); 833 u32 mode; 834 u32 flags; 835 u32 div; 836 u32 sclk; 837 u32 tune_reg = host->dev_comp->pad_tune_reg; 838 839 if (!hz) { 840 dev_dbg(host->dev, "set mclk to 0\n"); 841 host->mclk = 0; 842 mmc->actual_clock = 0; 843 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 844 return; 845 } 846 847 flags = readl(host->base + MSDC_INTEN); 848 sdr_clr_bits(host->base + MSDC_INTEN, flags); 849 if (host->dev_comp->clk_div_bits == 8) 850 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 851 else 852 sdr_clr_bits(host->base + MSDC_CFG, 853 MSDC_CFG_HS400_CK_MODE_EXTRA); 854 if (timing == MMC_TIMING_UHS_DDR50 || 855 timing == MMC_TIMING_MMC_DDR52 || 856 timing == MMC_TIMING_MMC_HS400) { 857 if (timing == MMC_TIMING_MMC_HS400) 858 mode = 0x3; 859 else 860 mode = 0x2; /* ddr mode and use divisor */ 861 862 if (hz >= (host->src_clk_freq >> 2)) { 863 div = 0; /* mean div = 1/4 */ 864 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 865 } else { 866 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 867 sclk = (host->src_clk_freq >> 2) / div; 868 div = (div >> 1); 869 } 870 871 if (timing == MMC_TIMING_MMC_HS400 && 872 hz >= (host->src_clk_freq >> 1)) { 873 if (host->dev_comp->clk_div_bits == 8) 874 sdr_set_bits(host->base + MSDC_CFG, 875 MSDC_CFG_HS400_CK_MODE); 876 else 877 sdr_set_bits(host->base + MSDC_CFG, 878 MSDC_CFG_HS400_CK_MODE_EXTRA); 879 sclk = host->src_clk_freq >> 1; 880 div = 0; /* div is ignore when bit18 is set */ 881 } 882 } else if (hz >= host->src_clk_freq) { 883 mode = 0x1; /* no divisor */ 884 div = 0; 885 sclk = host->src_clk_freq; 886 } else { 887 mode = 0x0; /* use divisor */ 888 if (hz >= (host->src_clk_freq >> 1)) { 889 div = 0; /* mean div = 1/2 */ 890 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 891 } else { 892 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 893 sclk = (host->src_clk_freq >> 2) / div; 894 } 895 } 896 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 897 /* 898 * As src_clk/HCLK use the same bit to gate/ungate, 899 * So if want to only gate src_clk, need gate its parent(mux). 900 */ 901 if (host->src_clk_cg) 902 clk_disable_unprepare(host->src_clk_cg); 903 else 904 clk_disable_unprepare(clk_get_parent(host->src_clk)); 905 if (host->dev_comp->clk_div_bits == 8) 906 sdr_set_field(host->base + MSDC_CFG, 907 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 908 (mode << 8) | div); 909 else 910 sdr_set_field(host->base + MSDC_CFG, 911 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, 912 (mode << 12) | div); 913 if (host->src_clk_cg) 914 clk_prepare_enable(host->src_clk_cg); 915 else 916 clk_prepare_enable(clk_get_parent(host->src_clk)); 917 918 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 919 cpu_relax(); 920 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 921 mmc->actual_clock = sclk; 922 host->mclk = hz; 923 host->timing = timing; 924 /* need because clk changed. */ 925 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 926 sdr_set_bits(host->base + MSDC_INTEN, flags); 927 928 /* 929 * mmc_select_hs400() will drop to 50Mhz and High speed mode, 930 * tune result of hs200/200Mhz is not suitable for 50Mhz 931 */ 932 if (mmc->actual_clock <= 52000000) { 933 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 934 if (host->top_base) { 935 writel(host->def_tune_para.emmc_top_control, 936 host->top_base + EMMC_TOP_CONTROL); 937 writel(host->def_tune_para.emmc_top_cmd, 938 host->top_base + EMMC_TOP_CMD); 939 } else { 940 writel(host->def_tune_para.pad_tune, 941 host->base + tune_reg); 942 } 943 } else { 944 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 945 writel(host->saved_tune_para.pad_cmd_tune, 946 host->base + PAD_CMD_TUNE); 947 if (host->top_base) { 948 writel(host->saved_tune_para.emmc_top_control, 949 host->top_base + EMMC_TOP_CONTROL); 950 writel(host->saved_tune_para.emmc_top_cmd, 951 host->top_base + EMMC_TOP_CMD); 952 } else { 953 writel(host->saved_tune_para.pad_tune, 954 host->base + tune_reg); 955 } 956 } 957 958 if (timing == MMC_TIMING_MMC_HS400 && 959 host->dev_comp->hs400_tune) 960 sdr_set_field(host->base + tune_reg, 961 MSDC_PAD_TUNE_CMDRRDLY, 962 host->hs400_cmd_int_delay); 963 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock, 964 timing); 965 } 966 967 static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 968 struct mmc_request *mrq, struct mmc_command *cmd) 969 { 970 u32 resp; 971 972 switch (mmc_resp_type(cmd)) { 973 /* Actually, R1, R5, R6, R7 are the same */ 974 case MMC_RSP_R1: 975 resp = 0x1; 976 break; 977 case MMC_RSP_R1B: 978 resp = 0x7; 979 break; 980 case MMC_RSP_R2: 981 resp = 0x2; 982 break; 983 case MMC_RSP_R3: 984 resp = 0x3; 985 break; 986 case MMC_RSP_NONE: 987 default: 988 resp = 0x0; 989 break; 990 } 991 992 return resp; 993 } 994 995 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 996 struct mmc_request *mrq, struct mmc_command *cmd) 997 { 998 struct mmc_host *mmc = mmc_from_priv(host); 999 /* rawcmd : 1000 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 1001 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 1002 */ 1003 u32 opcode = cmd->opcode; 1004 u32 resp = msdc_cmd_find_resp(host, mrq, cmd); 1005 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 1006 1007 host->cmd_rsp = resp; 1008 1009 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 1010 opcode == MMC_STOP_TRANSMISSION) 1011 rawcmd |= (0x1 << 14); 1012 else if (opcode == SD_SWITCH_VOLTAGE) 1013 rawcmd |= (0x1 << 30); 1014 else if (opcode == SD_APP_SEND_SCR || 1015 opcode == SD_APP_SEND_NUM_WR_BLKS || 1016 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 1017 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 1018 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 1019 rawcmd |= (0x1 << 11); 1020 1021 if (cmd->data) { 1022 struct mmc_data *data = cmd->data; 1023 1024 if (mmc_op_multi(opcode)) { 1025 if (mmc_card_mmc(mmc->card) && mrq->sbc && 1026 !(mrq->sbc->arg & 0xFFFF0000)) 1027 rawcmd |= 0x2 << 28; /* AutoCMD23 */ 1028 } 1029 1030 rawcmd |= ((data->blksz & 0xFFF) << 16); 1031 if (data->flags & MMC_DATA_WRITE) 1032 rawcmd |= (0x1 << 13); 1033 if (data->blocks > 1) 1034 rawcmd |= (0x2 << 11); 1035 else 1036 rawcmd |= (0x1 << 11); 1037 /* Always use dma mode */ 1038 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 1039 1040 if (host->timeout_ns != data->timeout_ns || 1041 host->timeout_clks != data->timeout_clks) 1042 msdc_set_timeout(host, data->timeout_ns, 1043 data->timeout_clks); 1044 1045 writel(data->blocks, host->base + SDC_BLK_NUM); 1046 } 1047 return rawcmd; 1048 } 1049 1050 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, 1051 struct mmc_command *cmd, struct mmc_data *data) 1052 { 1053 bool read; 1054 1055 WARN_ON(host->data); 1056 host->data = data; 1057 read = data->flags & MMC_DATA_READ; 1058 1059 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1060 msdc_dma_setup(host, &host->dma, data); 1061 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 1062 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 1063 dev_dbg(host->dev, "DMA start\n"); 1064 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 1065 __func__, cmd->opcode, data->blocks, read); 1066 } 1067 1068 static int msdc_auto_cmd_done(struct msdc_host *host, int events, 1069 struct mmc_command *cmd) 1070 { 1071 u32 *rsp = cmd->resp; 1072 1073 rsp[0] = readl(host->base + SDC_ACMD_RESP); 1074 1075 if (events & MSDC_INT_ACMDRDY) { 1076 cmd->error = 0; 1077 } else { 1078 msdc_reset_hw(host); 1079 if (events & MSDC_INT_ACMDCRCERR) { 1080 cmd->error = -EILSEQ; 1081 host->error |= REQ_STOP_EIO; 1082 } else if (events & MSDC_INT_ACMDTMO) { 1083 cmd->error = -ETIMEDOUT; 1084 host->error |= REQ_STOP_TMO; 1085 } 1086 dev_err(host->dev, 1087 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 1088 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 1089 } 1090 return cmd->error; 1091 } 1092 1093 /* 1094 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost 1095 * 1096 * Host controller may lost interrupt in some special case. 1097 * Add SDIO irq recheck mechanism to make sure all interrupts 1098 * can be processed immediately 1099 */ 1100 static void msdc_recheck_sdio_irq(struct msdc_host *host) 1101 { 1102 struct mmc_host *mmc = mmc_from_priv(host); 1103 u32 reg_int, reg_inten, reg_ps; 1104 1105 if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1106 reg_inten = readl(host->base + MSDC_INTEN); 1107 if (reg_inten & MSDC_INTEN_SDIOIRQ) { 1108 reg_int = readl(host->base + MSDC_INT); 1109 reg_ps = readl(host->base + MSDC_PS); 1110 if (!(reg_int & MSDC_INT_SDIOIRQ || 1111 reg_ps & MSDC_PS_DATA1)) { 1112 __msdc_enable_sdio_irq(host, 0); 1113 sdio_signal_irq(mmc); 1114 } 1115 } 1116 } 1117 } 1118 1119 static void msdc_track_cmd_data(struct msdc_host *host, 1120 struct mmc_command *cmd, struct mmc_data *data) 1121 { 1122 if (host->error) 1123 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 1124 __func__, cmd->opcode, cmd->arg, host->error); 1125 } 1126 1127 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 1128 { 1129 unsigned long flags; 1130 1131 /* 1132 * No need check the return value of cancel_delayed_work, as only ONE 1133 * path will go here! 1134 */ 1135 cancel_delayed_work(&host->req_timeout); 1136 1137 spin_lock_irqsave(&host->lock, flags); 1138 host->mrq = NULL; 1139 spin_unlock_irqrestore(&host->lock, flags); 1140 1141 msdc_track_cmd_data(host, mrq->cmd, mrq->data); 1142 if (mrq->data) 1143 msdc_unprepare_data(host, mrq); 1144 if (host->error) 1145 msdc_reset_hw(host); 1146 mmc_request_done(mmc_from_priv(host), mrq); 1147 if (host->dev_comp->recheck_sdio_irq) 1148 msdc_recheck_sdio_irq(host); 1149 } 1150 1151 /* returns true if command is fully handled; returns false otherwise */ 1152 static bool msdc_cmd_done(struct msdc_host *host, int events, 1153 struct mmc_request *mrq, struct mmc_command *cmd) 1154 { 1155 bool done = false; 1156 bool sbc_error; 1157 unsigned long flags; 1158 u32 *rsp; 1159 1160 if (mrq->sbc && cmd == mrq->cmd && 1161 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 1162 | MSDC_INT_ACMDTMO))) 1163 msdc_auto_cmd_done(host, events, mrq->sbc); 1164 1165 sbc_error = mrq->sbc && mrq->sbc->error; 1166 1167 if (!sbc_error && !(events & (MSDC_INT_CMDRDY 1168 | MSDC_INT_RSPCRCERR 1169 | MSDC_INT_CMDTMO))) 1170 return done; 1171 1172 spin_lock_irqsave(&host->lock, flags); 1173 done = !host->cmd; 1174 host->cmd = NULL; 1175 spin_unlock_irqrestore(&host->lock, flags); 1176 1177 if (done) 1178 return true; 1179 rsp = cmd->resp; 1180 1181 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1182 1183 if (cmd->flags & MMC_RSP_PRESENT) { 1184 if (cmd->flags & MMC_RSP_136) { 1185 rsp[0] = readl(host->base + SDC_RESP3); 1186 rsp[1] = readl(host->base + SDC_RESP2); 1187 rsp[2] = readl(host->base + SDC_RESP1); 1188 rsp[3] = readl(host->base + SDC_RESP0); 1189 } else { 1190 rsp[0] = readl(host->base + SDC_RESP0); 1191 } 1192 } 1193 1194 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 1195 if (events & MSDC_INT_CMDTMO || 1196 (cmd->opcode != MMC_SEND_TUNING_BLOCK && 1197 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)) 1198 /* 1199 * should not clear fifo/interrupt as the tune data 1200 * may have alreay come when cmd19/cmd21 gets response 1201 * CRC error. 1202 */ 1203 msdc_reset_hw(host); 1204 if (events & MSDC_INT_RSPCRCERR) { 1205 cmd->error = -EILSEQ; 1206 host->error |= REQ_CMD_EIO; 1207 } else if (events & MSDC_INT_CMDTMO) { 1208 cmd->error = -ETIMEDOUT; 1209 host->error |= REQ_CMD_TMO; 1210 } 1211 } 1212 if (cmd->error) 1213 dev_dbg(host->dev, 1214 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 1215 __func__, cmd->opcode, cmd->arg, rsp[0], 1216 cmd->error); 1217 1218 msdc_cmd_next(host, mrq, cmd); 1219 return true; 1220 } 1221 1222 /* It is the core layer's responsibility to ensure card status 1223 * is correct before issue a request. but host design do below 1224 * checks recommended. 1225 */ 1226 static inline bool msdc_cmd_is_ready(struct msdc_host *host, 1227 struct mmc_request *mrq, struct mmc_command *cmd) 1228 { 1229 /* The max busy time we can endure is 20ms */ 1230 unsigned long tmo = jiffies + msecs_to_jiffies(20); 1231 1232 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && 1233 time_before(jiffies, tmo)) 1234 cpu_relax(); 1235 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { 1236 dev_err(host->dev, "CMD bus busy detected\n"); 1237 host->error |= REQ_CMD_BUSY; 1238 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1239 return false; 1240 } 1241 1242 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 1243 tmo = jiffies + msecs_to_jiffies(20); 1244 /* R1B or with data, should check SDCBUSY */ 1245 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && 1246 time_before(jiffies, tmo)) 1247 cpu_relax(); 1248 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { 1249 dev_err(host->dev, "Controller busy detected\n"); 1250 host->error |= REQ_CMD_BUSY; 1251 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1252 return false; 1253 } 1254 } 1255 return true; 1256 } 1257 1258 static void msdc_start_command(struct msdc_host *host, 1259 struct mmc_request *mrq, struct mmc_command *cmd) 1260 { 1261 u32 rawcmd; 1262 unsigned long flags; 1263 1264 WARN_ON(host->cmd); 1265 host->cmd = cmd; 1266 1267 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1268 if (!msdc_cmd_is_ready(host, mrq, cmd)) 1269 return; 1270 1271 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 1272 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 1273 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 1274 msdc_reset_hw(host); 1275 } 1276 1277 cmd->error = 0; 1278 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 1279 1280 spin_lock_irqsave(&host->lock, flags); 1281 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1282 spin_unlock_irqrestore(&host->lock, flags); 1283 1284 writel(cmd->arg, host->base + SDC_ARG); 1285 writel(rawcmd, host->base + SDC_CMD); 1286 } 1287 1288 static void msdc_cmd_next(struct msdc_host *host, 1289 struct mmc_request *mrq, struct mmc_command *cmd) 1290 { 1291 if ((cmd->error && 1292 !(cmd->error == -EILSEQ && 1293 (cmd->opcode == MMC_SEND_TUNING_BLOCK || 1294 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) || 1295 (mrq->sbc && mrq->sbc->error)) 1296 msdc_request_done(host, mrq); 1297 else if (cmd == mrq->sbc) 1298 msdc_start_command(host, mrq, mrq->cmd); 1299 else if (!cmd->data) 1300 msdc_request_done(host, mrq); 1301 else 1302 msdc_start_data(host, mrq, cmd, cmd->data); 1303 } 1304 1305 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 1306 { 1307 struct msdc_host *host = mmc_priv(mmc); 1308 1309 host->error = 0; 1310 WARN_ON(host->mrq); 1311 host->mrq = mrq; 1312 1313 if (mrq->data) 1314 msdc_prepare_data(host, mrq); 1315 1316 /* if SBC is required, we have HW option and SW option. 1317 * if HW option is enabled, and SBC does not have "special" flags, 1318 * use HW option, otherwise use SW option 1319 */ 1320 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 1321 (mrq->sbc->arg & 0xFFFF0000))) 1322 msdc_start_command(host, mrq, mrq->sbc); 1323 else 1324 msdc_start_command(host, mrq, mrq->cmd); 1325 } 1326 1327 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 1328 { 1329 struct msdc_host *host = mmc_priv(mmc); 1330 struct mmc_data *data = mrq->data; 1331 1332 if (!data) 1333 return; 1334 1335 msdc_prepare_data(host, mrq); 1336 data->host_cookie |= MSDC_ASYNC_FLAG; 1337 } 1338 1339 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1340 int err) 1341 { 1342 struct msdc_host *host = mmc_priv(mmc); 1343 struct mmc_data *data; 1344 1345 data = mrq->data; 1346 if (!data) 1347 return; 1348 if (data->host_cookie) { 1349 data->host_cookie &= ~MSDC_ASYNC_FLAG; 1350 msdc_unprepare_data(host, mrq); 1351 } 1352 } 1353 1354 static void msdc_data_xfer_next(struct msdc_host *host, 1355 struct mmc_request *mrq, struct mmc_data *data) 1356 { 1357 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 1358 !mrq->sbc) 1359 msdc_start_command(host, mrq, mrq->stop); 1360 else 1361 msdc_request_done(host, mrq); 1362 } 1363 1364 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 1365 struct mmc_request *mrq, struct mmc_data *data) 1366 { 1367 struct mmc_command *stop; 1368 unsigned long flags; 1369 bool done; 1370 unsigned int check_data = events & 1371 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 1372 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 1373 | MSDC_INT_DMA_PROTECT); 1374 1375 spin_lock_irqsave(&host->lock, flags); 1376 done = !host->data; 1377 if (check_data) 1378 host->data = NULL; 1379 spin_unlock_irqrestore(&host->lock, flags); 1380 1381 if (done) 1382 return true; 1383 stop = data->stop; 1384 1385 if (check_data || (stop && stop->error)) { 1386 dev_dbg(host->dev, "DMA status: 0x%8X\n", 1387 readl(host->base + MSDC_DMA_CFG)); 1388 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1389 1); 1390 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) 1391 cpu_relax(); 1392 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 1393 dev_dbg(host->dev, "DMA stop\n"); 1394 1395 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 1396 data->bytes_xfered = data->blocks * data->blksz; 1397 } else { 1398 dev_dbg(host->dev, "interrupt events: %x\n", events); 1399 msdc_reset_hw(host); 1400 host->error |= REQ_DAT_ERR; 1401 data->bytes_xfered = 0; 1402 1403 if (events & MSDC_INT_DATTMO) 1404 data->error = -ETIMEDOUT; 1405 else if (events & MSDC_INT_DATCRCERR) 1406 data->error = -EILSEQ; 1407 1408 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 1409 __func__, mrq->cmd->opcode, data->blocks); 1410 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 1411 (int)data->error, data->bytes_xfered); 1412 } 1413 1414 msdc_data_xfer_next(host, mrq, data); 1415 done = true; 1416 } 1417 return done; 1418 } 1419 1420 static void msdc_set_buswidth(struct msdc_host *host, u32 width) 1421 { 1422 u32 val = readl(host->base + SDC_CFG); 1423 1424 val &= ~SDC_CFG_BUSWIDTH; 1425 1426 switch (width) { 1427 default: 1428 case MMC_BUS_WIDTH_1: 1429 val |= (MSDC_BUS_1BITS << 16); 1430 break; 1431 case MMC_BUS_WIDTH_4: 1432 val |= (MSDC_BUS_4BITS << 16); 1433 break; 1434 case MMC_BUS_WIDTH_8: 1435 val |= (MSDC_BUS_8BITS << 16); 1436 break; 1437 } 1438 1439 writel(val, host->base + SDC_CFG); 1440 dev_dbg(host->dev, "Bus Width = %d", width); 1441 } 1442 1443 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 1444 { 1445 struct msdc_host *host = mmc_priv(mmc); 1446 int ret; 1447 1448 if (!IS_ERR(mmc->supply.vqmmc)) { 1449 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1450 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 1451 dev_err(host->dev, "Unsupported signal voltage!\n"); 1452 return -EINVAL; 1453 } 1454 1455 ret = mmc_regulator_set_vqmmc(mmc, ios); 1456 if (ret < 0) { 1457 dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1458 ret, ios->signal_voltage); 1459 return ret; 1460 } 1461 1462 /* Apply different pinctrl settings for different signal voltage */ 1463 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 1464 pinctrl_select_state(host->pinctrl, host->pins_uhs); 1465 else 1466 pinctrl_select_state(host->pinctrl, host->pins_default); 1467 } 1468 return 0; 1469 } 1470 1471 static int msdc_card_busy(struct mmc_host *mmc) 1472 { 1473 struct msdc_host *host = mmc_priv(mmc); 1474 u32 status = readl(host->base + MSDC_PS); 1475 1476 /* only check if data0 is low */ 1477 return !(status & BIT(16)); 1478 } 1479 1480 static void msdc_request_timeout(struct work_struct *work) 1481 { 1482 struct msdc_host *host = container_of(work, struct msdc_host, 1483 req_timeout.work); 1484 1485 /* simulate HW timeout status */ 1486 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 1487 if (host->mrq) { 1488 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 1489 host->mrq, host->mrq->cmd->opcode); 1490 if (host->cmd) { 1491 dev_err(host->dev, "%s: aborting cmd=%d\n", 1492 __func__, host->cmd->opcode); 1493 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 1494 host->cmd); 1495 } else if (host->data) { 1496 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 1497 __func__, host->mrq->cmd->opcode, 1498 host->data->blocks); 1499 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 1500 host->data); 1501 } 1502 } 1503 } 1504 1505 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb) 1506 { 1507 if (enb) { 1508 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1509 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1510 if (host->dev_comp->recheck_sdio_irq) 1511 msdc_recheck_sdio_irq(host); 1512 } else { 1513 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1514 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1515 } 1516 } 1517 1518 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) 1519 { 1520 unsigned long flags; 1521 struct msdc_host *host = mmc_priv(mmc); 1522 1523 spin_lock_irqsave(&host->lock, flags); 1524 __msdc_enable_sdio_irq(host, enb); 1525 spin_unlock_irqrestore(&host->lock, flags); 1526 1527 if (enb) 1528 pm_runtime_get_noresume(host->dev); 1529 else 1530 pm_runtime_put_noidle(host->dev); 1531 } 1532 1533 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) 1534 { 1535 struct mmc_host *mmc = mmc_from_priv(host); 1536 int cmd_err = 0, dat_err = 0; 1537 1538 if (intsts & MSDC_INT_RSPCRCERR) { 1539 cmd_err = -EILSEQ; 1540 dev_err(host->dev, "%s: CMD CRC ERR", __func__); 1541 } else if (intsts & MSDC_INT_CMDTMO) { 1542 cmd_err = -ETIMEDOUT; 1543 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); 1544 } 1545 1546 if (intsts & MSDC_INT_DATCRCERR) { 1547 dat_err = -EILSEQ; 1548 dev_err(host->dev, "%s: DATA CRC ERR", __func__); 1549 } else if (intsts & MSDC_INT_DATTMO) { 1550 dat_err = -ETIMEDOUT; 1551 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); 1552 } 1553 1554 if (cmd_err || dat_err) { 1555 dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", 1556 cmd_err, dat_err, intsts); 1557 } 1558 1559 return cqhci_irq(mmc, 0, cmd_err, dat_err); 1560 } 1561 1562 static irqreturn_t msdc_irq(int irq, void *dev_id) 1563 { 1564 struct msdc_host *host = (struct msdc_host *) dev_id; 1565 struct mmc_host *mmc = mmc_from_priv(host); 1566 1567 while (true) { 1568 struct mmc_request *mrq; 1569 struct mmc_command *cmd; 1570 struct mmc_data *data; 1571 u32 events, event_mask; 1572 1573 spin_lock(&host->lock); 1574 events = readl(host->base + MSDC_INT); 1575 event_mask = readl(host->base + MSDC_INTEN); 1576 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1577 __msdc_enable_sdio_irq(host, 0); 1578 /* clear interrupts */ 1579 writel(events & event_mask, host->base + MSDC_INT); 1580 1581 mrq = host->mrq; 1582 cmd = host->cmd; 1583 data = host->data; 1584 spin_unlock(&host->lock); 1585 1586 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1587 sdio_signal_irq(mmc); 1588 1589 if ((events & event_mask) & MSDC_INT_CDSC) { 1590 if (host->internal_cd) 1591 mmc_detect_change(mmc, msecs_to_jiffies(20)); 1592 events &= ~MSDC_INT_CDSC; 1593 } 1594 1595 if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) 1596 break; 1597 1598 if ((mmc->caps2 & MMC_CAP2_CQE) && 1599 (events & MSDC_INT_CMDQ)) { 1600 msdc_cmdq_irq(host, events); 1601 /* clear interrupts */ 1602 writel(events, host->base + MSDC_INT); 1603 return IRQ_HANDLED; 1604 } 1605 1606 if (!mrq) { 1607 dev_err(host->dev, 1608 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 1609 __func__, events, event_mask); 1610 WARN_ON(1); 1611 break; 1612 } 1613 1614 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 1615 1616 if (cmd) 1617 msdc_cmd_done(host, events, mrq, cmd); 1618 else if (data) 1619 msdc_data_xfer_done(host, events, mrq, data); 1620 } 1621 1622 return IRQ_HANDLED; 1623 } 1624 1625 static void msdc_init_hw(struct msdc_host *host) 1626 { 1627 u32 val; 1628 u32 tune_reg = host->dev_comp->pad_tune_reg; 1629 1630 if (host->reset) { 1631 reset_control_assert(host->reset); 1632 usleep_range(10, 50); 1633 reset_control_deassert(host->reset); 1634 } 1635 1636 /* Configure to MMC/SD mode, clock free running */ 1637 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 1638 1639 /* Reset */ 1640 msdc_reset_hw(host); 1641 1642 /* Disable and clear all interrupts */ 1643 writel(0, host->base + MSDC_INTEN); 1644 val = readl(host->base + MSDC_INT); 1645 writel(val, host->base + MSDC_INT); 1646 1647 /* Configure card detection */ 1648 if (host->internal_cd) { 1649 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, 1650 DEFAULT_DEBOUNCE); 1651 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1652 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1653 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1654 } else { 1655 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1656 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1657 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1658 } 1659 1660 if (host->top_base) { 1661 writel(0, host->top_base + EMMC_TOP_CONTROL); 1662 writel(0, host->top_base + EMMC_TOP_CMD); 1663 } else { 1664 writel(0, host->base + tune_reg); 1665 } 1666 writel(0, host->base + MSDC_IOCON); 1667 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 1668 writel(0x403c0046, host->base + MSDC_PATCH_BIT); 1669 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 1670 writel(0xffff4089, host->base + MSDC_PATCH_BIT1); 1671 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1672 1673 if (host->dev_comp->stop_clk_fix) { 1674 sdr_set_field(host->base + MSDC_PATCH_BIT1, 1675 MSDC_PATCH_BIT1_STOP_DLY, 3); 1676 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1677 SDC_FIFO_CFG_WRVALIDSEL); 1678 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1679 SDC_FIFO_CFG_RDVALIDSEL); 1680 } 1681 1682 if (host->dev_comp->busy_check) 1683 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7)); 1684 1685 if (host->dev_comp->async_fifo) { 1686 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1687 MSDC_PB2_RESPWAIT, 3); 1688 if (host->dev_comp->enhance_rx) { 1689 if (host->top_base) 1690 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1691 SDC_RX_ENH_EN); 1692 else 1693 sdr_set_bits(host->base + SDC_ADV_CFG0, 1694 SDC_RX_ENHANCE_EN); 1695 } else { 1696 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1697 MSDC_PB2_RESPSTSENSEL, 2); 1698 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1699 MSDC_PB2_CRCSTSENSEL, 2); 1700 } 1701 /* use async fifo, then no need tune internal delay */ 1702 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, 1703 MSDC_PATCH_BIT2_CFGRESP); 1704 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1705 MSDC_PATCH_BIT2_CFGCRCSTS); 1706 } 1707 1708 if (host->dev_comp->support_64g) 1709 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1710 MSDC_PB2_SUPPORT_64G); 1711 if (host->dev_comp->data_tune) { 1712 if (host->top_base) { 1713 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1714 PAD_DAT_RD_RXDLY_SEL); 1715 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, 1716 DATA_K_VALUE_SEL); 1717 sdr_set_bits(host->top_base + EMMC_TOP_CMD, 1718 PAD_CMD_RD_RXDLY_SEL); 1719 } else { 1720 sdr_set_bits(host->base + tune_reg, 1721 MSDC_PAD_TUNE_RD_SEL | 1722 MSDC_PAD_TUNE_CMD_SEL); 1723 } 1724 } else { 1725 /* choose clock tune */ 1726 if (host->top_base) 1727 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1728 PAD_RXDLY_SEL); 1729 else 1730 sdr_set_bits(host->base + tune_reg, 1731 MSDC_PAD_TUNE_RXDLYSEL); 1732 } 1733 1734 /* Configure to enable SDIO mode. 1735 * it's must otherwise sdio cmd5 failed 1736 */ 1737 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1738 1739 /* Config SDIO device detect interrupt function */ 1740 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1741 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 1742 1743 /* Configure to default data timeout */ 1744 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 1745 1746 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 1747 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1748 if (host->top_base) { 1749 host->def_tune_para.emmc_top_control = 1750 readl(host->top_base + EMMC_TOP_CONTROL); 1751 host->def_tune_para.emmc_top_cmd = 1752 readl(host->top_base + EMMC_TOP_CMD); 1753 host->saved_tune_para.emmc_top_control = 1754 readl(host->top_base + EMMC_TOP_CONTROL); 1755 host->saved_tune_para.emmc_top_cmd = 1756 readl(host->top_base + EMMC_TOP_CMD); 1757 } else { 1758 host->def_tune_para.pad_tune = readl(host->base + tune_reg); 1759 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 1760 } 1761 dev_dbg(host->dev, "init hardware done!"); 1762 } 1763 1764 static void msdc_deinit_hw(struct msdc_host *host) 1765 { 1766 u32 val; 1767 1768 if (host->internal_cd) { 1769 /* Disabled card-detect */ 1770 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1771 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1772 } 1773 1774 /* Disable and clear all interrupts */ 1775 writel(0, host->base + MSDC_INTEN); 1776 1777 val = readl(host->base + MSDC_INT); 1778 writel(val, host->base + MSDC_INT); 1779 } 1780 1781 /* init gpd and bd list in msdc_drv_probe */ 1782 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 1783 { 1784 struct mt_gpdma_desc *gpd = dma->gpd; 1785 struct mt_bdma_desc *bd = dma->bd; 1786 dma_addr_t dma_addr; 1787 int i; 1788 1789 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 1790 1791 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); 1792 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 1793 /* gpd->next is must set for desc DMA 1794 * That's why must alloc 2 gpd structure. 1795 */ 1796 gpd->next = lower_32_bits(dma_addr); 1797 if (host->dev_comp->support_64g) 1798 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1799 1800 dma_addr = dma->bd_addr; 1801 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ 1802 if (host->dev_comp->support_64g) 1803 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; 1804 1805 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 1806 for (i = 0; i < (MAX_BD_NUM - 1); i++) { 1807 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); 1808 bd[i].next = lower_32_bits(dma_addr); 1809 if (host->dev_comp->support_64g) 1810 bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1811 } 1812 } 1813 1814 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1815 { 1816 struct msdc_host *host = mmc_priv(mmc); 1817 int ret; 1818 1819 msdc_set_buswidth(host, ios->bus_width); 1820 1821 /* Suspend/Resume will do power off/on */ 1822 switch (ios->power_mode) { 1823 case MMC_POWER_UP: 1824 if (!IS_ERR(mmc->supply.vmmc)) { 1825 msdc_init_hw(host); 1826 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1827 ios->vdd); 1828 if (ret) { 1829 dev_err(host->dev, "Failed to set vmmc power!\n"); 1830 return; 1831 } 1832 } 1833 break; 1834 case MMC_POWER_ON: 1835 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1836 ret = regulator_enable(mmc->supply.vqmmc); 1837 if (ret) 1838 dev_err(host->dev, "Failed to set vqmmc power!\n"); 1839 else 1840 host->vqmmc_enabled = true; 1841 } 1842 break; 1843 case MMC_POWER_OFF: 1844 if (!IS_ERR(mmc->supply.vmmc)) 1845 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1846 1847 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1848 regulator_disable(mmc->supply.vqmmc); 1849 host->vqmmc_enabled = false; 1850 } 1851 break; 1852 default: 1853 break; 1854 } 1855 1856 if (host->mclk != ios->clock || host->timing != ios->timing) 1857 msdc_set_mclk(host, ios->timing, ios->clock); 1858 } 1859 1860 static u32 test_delay_bit(u32 delay, u32 bit) 1861 { 1862 bit %= PAD_DELAY_MAX; 1863 return delay & (1 << bit); 1864 } 1865 1866 static int get_delay_len(u32 delay, u32 start_bit) 1867 { 1868 int i; 1869 1870 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 1871 if (test_delay_bit(delay, start_bit + i) == 0) 1872 return i; 1873 } 1874 return PAD_DELAY_MAX - start_bit; 1875 } 1876 1877 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 1878 { 1879 int start = 0, len = 0; 1880 int start_final = 0, len_final = 0; 1881 u8 final_phase = 0xff; 1882 struct msdc_delay_phase delay_phase = { 0, }; 1883 1884 if (delay == 0) { 1885 dev_err(host->dev, "phase error: [map:%x]\n", delay); 1886 delay_phase.final_phase = final_phase; 1887 return delay_phase; 1888 } 1889 1890 while (start < PAD_DELAY_MAX) { 1891 len = get_delay_len(delay, start); 1892 if (len_final < len) { 1893 start_final = start; 1894 len_final = len; 1895 } 1896 start += len ? len : 1; 1897 if (len >= 12 && start_final < 4) 1898 break; 1899 } 1900 1901 /* The rule is that to find the smallest delay cell */ 1902 if (start_final == 0) 1903 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 1904 else 1905 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 1906 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 1907 delay, len_final, final_phase); 1908 1909 delay_phase.maxlen = len_final; 1910 delay_phase.start = start_final; 1911 delay_phase.final_phase = final_phase; 1912 return delay_phase; 1913 } 1914 1915 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) 1916 { 1917 u32 tune_reg = host->dev_comp->pad_tune_reg; 1918 1919 if (host->top_base) 1920 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, 1921 value); 1922 else 1923 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1924 value); 1925 } 1926 1927 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) 1928 { 1929 u32 tune_reg = host->dev_comp->pad_tune_reg; 1930 1931 if (host->top_base) 1932 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, 1933 PAD_DAT_RD_RXDLY, value); 1934 else 1935 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, 1936 value); 1937 } 1938 1939 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 1940 { 1941 struct msdc_host *host = mmc_priv(mmc); 1942 u32 rise_delay = 0, fall_delay = 0; 1943 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1944 struct msdc_delay_phase internal_delay_phase; 1945 u8 final_delay, final_maxlen; 1946 u32 internal_delay = 0; 1947 u32 tune_reg = host->dev_comp->pad_tune_reg; 1948 int cmd_err; 1949 int i, j; 1950 1951 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 1952 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 1953 sdr_set_field(host->base + tune_reg, 1954 MSDC_PAD_TUNE_CMDRRDLY, 1955 host->hs200_cmd_int_delay); 1956 1957 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1958 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1959 msdc_set_cmd_delay(host, i); 1960 /* 1961 * Using the same parameters, it may sometimes pass the test, 1962 * but sometimes it may fail. To make sure the parameters are 1963 * more stable, we test each set of parameters 3 times. 1964 */ 1965 for (j = 0; j < 3; j++) { 1966 mmc_send_tuning(mmc, opcode, &cmd_err); 1967 if (!cmd_err) { 1968 rise_delay |= (1 << i); 1969 } else { 1970 rise_delay &= ~(1 << i); 1971 break; 1972 } 1973 } 1974 } 1975 final_rise_delay = get_best_delay(host, rise_delay); 1976 /* if rising edge has enough margin, then do not scan falling edge */ 1977 if (final_rise_delay.maxlen >= 12 || 1978 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1979 goto skip_fall; 1980 1981 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1982 for (i = 0; i < PAD_DELAY_MAX; i++) { 1983 msdc_set_cmd_delay(host, i); 1984 /* 1985 * Using the same parameters, it may sometimes pass the test, 1986 * but sometimes it may fail. To make sure the parameters are 1987 * more stable, we test each set of parameters 3 times. 1988 */ 1989 for (j = 0; j < 3; j++) { 1990 mmc_send_tuning(mmc, opcode, &cmd_err); 1991 if (!cmd_err) { 1992 fall_delay |= (1 << i); 1993 } else { 1994 fall_delay &= ~(1 << i); 1995 break; 1996 } 1997 } 1998 } 1999 final_fall_delay = get_best_delay(host, fall_delay); 2000 2001 skip_fall: 2002 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2003 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 2004 final_maxlen = final_fall_delay.maxlen; 2005 if (final_maxlen == final_rise_delay.maxlen) { 2006 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2007 final_delay = final_rise_delay.final_phase; 2008 } else { 2009 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2010 final_delay = final_fall_delay.final_phase; 2011 } 2012 msdc_set_cmd_delay(host, final_delay); 2013 2014 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) 2015 goto skip_internal; 2016 2017 for (i = 0; i < PAD_DELAY_MAX; i++) { 2018 sdr_set_field(host->base + tune_reg, 2019 MSDC_PAD_TUNE_CMDRRDLY, i); 2020 mmc_send_tuning(mmc, opcode, &cmd_err); 2021 if (!cmd_err) 2022 internal_delay |= (1 << i); 2023 } 2024 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 2025 internal_delay_phase = get_best_delay(host, internal_delay); 2026 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 2027 internal_delay_phase.final_phase); 2028 skip_internal: 2029 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 2030 return final_delay == 0xff ? -EIO : 0; 2031 } 2032 2033 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 2034 { 2035 struct msdc_host *host = mmc_priv(mmc); 2036 u32 cmd_delay = 0; 2037 struct msdc_delay_phase final_cmd_delay = { 0,}; 2038 u8 final_delay; 2039 int cmd_err; 2040 int i, j; 2041 2042 /* select EMMC50 PAD CMD tune */ 2043 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 2044 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); 2045 2046 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 2047 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 2048 sdr_set_field(host->base + MSDC_PAD_TUNE, 2049 MSDC_PAD_TUNE_CMDRRDLY, 2050 host->hs200_cmd_int_delay); 2051 2052 if (host->hs400_cmd_resp_sel_rising) 2053 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2054 else 2055 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2056 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2057 sdr_set_field(host->base + PAD_CMD_TUNE, 2058 PAD_CMD_TUNE_RX_DLY3, i); 2059 /* 2060 * Using the same parameters, it may sometimes pass the test, 2061 * but sometimes it may fail. To make sure the parameters are 2062 * more stable, we test each set of parameters 3 times. 2063 */ 2064 for (j = 0; j < 3; j++) { 2065 mmc_send_tuning(mmc, opcode, &cmd_err); 2066 if (!cmd_err) { 2067 cmd_delay |= (1 << i); 2068 } else { 2069 cmd_delay &= ~(1 << i); 2070 break; 2071 } 2072 } 2073 } 2074 final_cmd_delay = get_best_delay(host, cmd_delay); 2075 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 2076 final_cmd_delay.final_phase); 2077 final_delay = final_cmd_delay.final_phase; 2078 2079 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 2080 return final_delay == 0xff ? -EIO : 0; 2081 } 2082 2083 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 2084 { 2085 struct msdc_host *host = mmc_priv(mmc); 2086 u32 rise_delay = 0, fall_delay = 0; 2087 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2088 u8 final_delay, final_maxlen; 2089 int i, ret; 2090 2091 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2092 host->latch_ck); 2093 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2094 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2095 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2096 msdc_set_data_delay(host, i); 2097 ret = mmc_send_tuning(mmc, opcode, NULL); 2098 if (!ret) 2099 rise_delay |= (1 << i); 2100 } 2101 final_rise_delay = get_best_delay(host, rise_delay); 2102 /* if rising edge has enough margin, then do not scan falling edge */ 2103 if (final_rise_delay.maxlen >= 12 || 2104 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2105 goto skip_fall; 2106 2107 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2108 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2109 for (i = 0; i < PAD_DELAY_MAX; i++) { 2110 msdc_set_data_delay(host, i); 2111 ret = mmc_send_tuning(mmc, opcode, NULL); 2112 if (!ret) 2113 fall_delay |= (1 << i); 2114 } 2115 final_fall_delay = get_best_delay(host, fall_delay); 2116 2117 skip_fall: 2118 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2119 if (final_maxlen == final_rise_delay.maxlen) { 2120 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2121 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2122 final_delay = final_rise_delay.final_phase; 2123 } else { 2124 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2125 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2126 final_delay = final_fall_delay.final_phase; 2127 } 2128 msdc_set_data_delay(host, final_delay); 2129 2130 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 2131 return final_delay == 0xff ? -EIO : 0; 2132 } 2133 2134 /* 2135 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune 2136 * together, which can save the tuning time. 2137 */ 2138 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode) 2139 { 2140 struct msdc_host *host = mmc_priv(mmc); 2141 u32 rise_delay = 0, fall_delay = 0; 2142 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2143 u8 final_delay, final_maxlen; 2144 int i, ret; 2145 2146 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2147 host->latch_ck); 2148 2149 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2150 sdr_clr_bits(host->base + MSDC_IOCON, 2151 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2152 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2153 msdc_set_cmd_delay(host, i); 2154 msdc_set_data_delay(host, i); 2155 ret = mmc_send_tuning(mmc, opcode, NULL); 2156 if (!ret) 2157 rise_delay |= (1 << i); 2158 } 2159 final_rise_delay = get_best_delay(host, rise_delay); 2160 /* if rising edge has enough margin, then do not scan falling edge */ 2161 if (final_rise_delay.maxlen >= 12 || 2162 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2163 goto skip_fall; 2164 2165 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2166 sdr_set_bits(host->base + MSDC_IOCON, 2167 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2168 for (i = 0; i < PAD_DELAY_MAX; i++) { 2169 msdc_set_cmd_delay(host, i); 2170 msdc_set_data_delay(host, i); 2171 ret = mmc_send_tuning(mmc, opcode, NULL); 2172 if (!ret) 2173 fall_delay |= (1 << i); 2174 } 2175 final_fall_delay = get_best_delay(host, fall_delay); 2176 2177 skip_fall: 2178 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2179 if (final_maxlen == final_rise_delay.maxlen) { 2180 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2181 sdr_clr_bits(host->base + MSDC_IOCON, 2182 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2183 final_delay = final_rise_delay.final_phase; 2184 } else { 2185 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2186 sdr_set_bits(host->base + MSDC_IOCON, 2187 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2188 final_delay = final_fall_delay.final_phase; 2189 } 2190 2191 msdc_set_cmd_delay(host, final_delay); 2192 msdc_set_data_delay(host, final_delay); 2193 2194 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); 2195 return final_delay == 0xff ? -EIO : 0; 2196 } 2197 2198 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 2199 { 2200 struct msdc_host *host = mmc_priv(mmc); 2201 int ret; 2202 u32 tune_reg = host->dev_comp->pad_tune_reg; 2203 2204 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { 2205 ret = msdc_tune_together(mmc, opcode); 2206 if (host->hs400_mode) { 2207 sdr_clr_bits(host->base + MSDC_IOCON, 2208 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2209 msdc_set_data_delay(host, 0); 2210 } 2211 goto tune_done; 2212 } 2213 if (host->hs400_mode && 2214 host->dev_comp->hs400_tune) 2215 ret = hs400_tune_response(mmc, opcode); 2216 else 2217 ret = msdc_tune_response(mmc, opcode); 2218 if (ret == -EIO) { 2219 dev_err(host->dev, "Tune response fail!\n"); 2220 return ret; 2221 } 2222 if (host->hs400_mode == false) { 2223 ret = msdc_tune_data(mmc, opcode); 2224 if (ret == -EIO) 2225 dev_err(host->dev, "Tune data fail!\n"); 2226 } 2227 2228 tune_done: 2229 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 2230 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 2231 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2232 if (host->top_base) { 2233 host->saved_tune_para.emmc_top_control = readl(host->top_base + 2234 EMMC_TOP_CONTROL); 2235 host->saved_tune_para.emmc_top_cmd = readl(host->top_base + 2236 EMMC_TOP_CMD); 2237 } 2238 return ret; 2239 } 2240 2241 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 2242 { 2243 struct msdc_host *host = mmc_priv(mmc); 2244 host->hs400_mode = true; 2245 2246 if (host->top_base) 2247 writel(host->hs400_ds_delay, 2248 host->top_base + EMMC50_PAD_DS_TUNE); 2249 else 2250 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 2251 /* hs400 mode must set it to 0 */ 2252 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); 2253 /* to improve read performance, set outstanding to 2 */ 2254 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); 2255 2256 return 0; 2257 } 2258 2259 static void msdc_hw_reset(struct mmc_host *mmc) 2260 { 2261 struct msdc_host *host = mmc_priv(mmc); 2262 2263 sdr_set_bits(host->base + EMMC_IOCON, 1); 2264 udelay(10); /* 10us is enough */ 2265 sdr_clr_bits(host->base + EMMC_IOCON, 1); 2266 } 2267 2268 static void msdc_ack_sdio_irq(struct mmc_host *mmc) 2269 { 2270 unsigned long flags; 2271 struct msdc_host *host = mmc_priv(mmc); 2272 2273 spin_lock_irqsave(&host->lock, flags); 2274 __msdc_enable_sdio_irq(host, 1); 2275 spin_unlock_irqrestore(&host->lock, flags); 2276 } 2277 2278 static int msdc_get_cd(struct mmc_host *mmc) 2279 { 2280 struct msdc_host *host = mmc_priv(mmc); 2281 int val; 2282 2283 if (mmc->caps & MMC_CAP_NONREMOVABLE) 2284 return 1; 2285 2286 if (!host->internal_cd) 2287 return mmc_gpio_get_cd(mmc); 2288 2289 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; 2290 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) 2291 return !!val; 2292 else 2293 return !val; 2294 } 2295 2296 static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc, 2297 struct mmc_ios *ios) 2298 { 2299 struct msdc_host *host = mmc_priv(mmc); 2300 2301 if (ios->enhanced_strobe) { 2302 msdc_prepare_hs400_tuning(mmc, ios); 2303 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1); 2304 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1); 2305 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1); 2306 2307 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); 2308 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); 2309 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT); 2310 } else { 2311 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0); 2312 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0); 2313 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0); 2314 2315 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); 2316 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); 2317 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4); 2318 } 2319 } 2320 2321 static void msdc_cqe_enable(struct mmc_host *mmc) 2322 { 2323 struct msdc_host *host = mmc_priv(mmc); 2324 2325 /* enable cmdq irq */ 2326 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); 2327 /* enable busy check */ 2328 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 2329 /* default write data / busy timeout 20s */ 2330 msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); 2331 /* default read data timeout 1s */ 2332 msdc_set_timeout(host, 1000000000ULL, 0); 2333 } 2334 2335 static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) 2336 { 2337 struct msdc_host *host = mmc_priv(mmc); 2338 2339 /* disable cmdq irq */ 2340 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); 2341 /* disable busy check */ 2342 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 2343 2344 if (recovery) { 2345 sdr_set_field(host->base + MSDC_DMA_CTRL, 2346 MSDC_DMA_CTRL_STOP, 1); 2347 msdc_reset_hw(host); 2348 } 2349 } 2350 2351 static void msdc_cqe_pre_enable(struct mmc_host *mmc) 2352 { 2353 struct cqhci_host *cq_host = mmc->cqe_private; 2354 u32 reg; 2355 2356 reg = cqhci_readl(cq_host, CQHCI_CFG); 2357 reg |= CQHCI_ENABLE; 2358 cqhci_writel(cq_host, reg, CQHCI_CFG); 2359 } 2360 2361 static void msdc_cqe_post_disable(struct mmc_host *mmc) 2362 { 2363 struct cqhci_host *cq_host = mmc->cqe_private; 2364 u32 reg; 2365 2366 reg = cqhci_readl(cq_host, CQHCI_CFG); 2367 reg &= ~CQHCI_ENABLE; 2368 cqhci_writel(cq_host, reg, CQHCI_CFG); 2369 } 2370 2371 static const struct mmc_host_ops mt_msdc_ops = { 2372 .post_req = msdc_post_req, 2373 .pre_req = msdc_pre_req, 2374 .request = msdc_ops_request, 2375 .set_ios = msdc_ops_set_ios, 2376 .get_ro = mmc_gpio_get_ro, 2377 .get_cd = msdc_get_cd, 2378 .hs400_enhanced_strobe = msdc_hs400_enhanced_strobe, 2379 .enable_sdio_irq = msdc_enable_sdio_irq, 2380 .ack_sdio_irq = msdc_ack_sdio_irq, 2381 .start_signal_voltage_switch = msdc_ops_switch_volt, 2382 .card_busy = msdc_card_busy, 2383 .execute_tuning = msdc_execute_tuning, 2384 .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 2385 .hw_reset = msdc_hw_reset, 2386 }; 2387 2388 static const struct cqhci_host_ops msdc_cmdq_ops = { 2389 .enable = msdc_cqe_enable, 2390 .disable = msdc_cqe_disable, 2391 .pre_enable = msdc_cqe_pre_enable, 2392 .post_disable = msdc_cqe_post_disable, 2393 }; 2394 2395 static void msdc_of_property_parse(struct platform_device *pdev, 2396 struct msdc_host *host) 2397 { 2398 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", 2399 &host->latch_ck); 2400 2401 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 2402 &host->hs400_ds_delay); 2403 2404 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 2405 &host->hs200_cmd_int_delay); 2406 2407 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 2408 &host->hs400_cmd_int_delay); 2409 2410 if (of_property_read_bool(pdev->dev.of_node, 2411 "mediatek,hs400-cmd-resp-sel-rising")) 2412 host->hs400_cmd_resp_sel_rising = true; 2413 else 2414 host->hs400_cmd_resp_sel_rising = false; 2415 2416 if (of_property_read_bool(pdev->dev.of_node, 2417 "supports-cqe")) 2418 host->cqhci = true; 2419 else 2420 host->cqhci = false; 2421 } 2422 2423 static int msdc_of_clock_parse(struct platform_device *pdev, 2424 struct msdc_host *host) 2425 { 2426 int ret; 2427 2428 host->src_clk = devm_clk_get(&pdev->dev, "source"); 2429 if (IS_ERR(host->src_clk)) 2430 return PTR_ERR(host->src_clk); 2431 2432 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 2433 if (IS_ERR(host->h_clk)) 2434 return PTR_ERR(host->h_clk); 2435 2436 host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk"); 2437 if (IS_ERR(host->bus_clk)) 2438 host->bus_clk = NULL; 2439 2440 /*source clock control gate is optional clock*/ 2441 host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg"); 2442 if (IS_ERR(host->src_clk_cg)) 2443 host->src_clk_cg = NULL; 2444 2445 host->sys_clk_cg = devm_clk_get_optional(&pdev->dev, "sys_cg"); 2446 if (IS_ERR(host->sys_clk_cg)) 2447 host->sys_clk_cg = NULL; 2448 2449 /* If present, always enable for this clock gate */ 2450 clk_prepare_enable(host->sys_clk_cg); 2451 2452 host->bulk_clks[0].id = "pclk_cg"; 2453 host->bulk_clks[1].id = "axi_cg"; 2454 host->bulk_clks[2].id = "ahb_cg"; 2455 ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS, 2456 host->bulk_clks); 2457 if (ret) { 2458 dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n"); 2459 return ret; 2460 } 2461 2462 return 0; 2463 } 2464 2465 static int msdc_drv_probe(struct platform_device *pdev) 2466 { 2467 struct mmc_host *mmc; 2468 struct msdc_host *host; 2469 struct resource *res; 2470 int ret; 2471 2472 if (!pdev->dev.of_node) { 2473 dev_err(&pdev->dev, "No DT found\n"); 2474 return -EINVAL; 2475 } 2476 2477 /* Allocate MMC host for this device */ 2478 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 2479 if (!mmc) 2480 return -ENOMEM; 2481 2482 host = mmc_priv(mmc); 2483 ret = mmc_of_parse(mmc); 2484 if (ret) 2485 goto host_free; 2486 2487 host->base = devm_platform_ioremap_resource(pdev, 0); 2488 if (IS_ERR(host->base)) { 2489 ret = PTR_ERR(host->base); 2490 goto host_free; 2491 } 2492 2493 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2494 if (res) { 2495 host->top_base = devm_ioremap_resource(&pdev->dev, res); 2496 if (IS_ERR(host->top_base)) 2497 host->top_base = NULL; 2498 } 2499 2500 ret = mmc_regulator_get_supply(mmc); 2501 if (ret) 2502 goto host_free; 2503 2504 ret = msdc_of_clock_parse(pdev, host); 2505 if (ret) 2506 goto host_free; 2507 2508 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 2509 "hrst"); 2510 if (IS_ERR(host->reset)) { 2511 ret = PTR_ERR(host->reset); 2512 goto host_free; 2513 } 2514 2515 host->irq = platform_get_irq(pdev, 0); 2516 if (host->irq < 0) { 2517 ret = -EINVAL; 2518 goto host_free; 2519 } 2520 2521 host->pinctrl = devm_pinctrl_get(&pdev->dev); 2522 if (IS_ERR(host->pinctrl)) { 2523 ret = PTR_ERR(host->pinctrl); 2524 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 2525 goto host_free; 2526 } 2527 2528 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 2529 if (IS_ERR(host->pins_default)) { 2530 ret = PTR_ERR(host->pins_default); 2531 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 2532 goto host_free; 2533 } 2534 2535 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 2536 if (IS_ERR(host->pins_uhs)) { 2537 ret = PTR_ERR(host->pins_uhs); 2538 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 2539 goto host_free; 2540 } 2541 2542 msdc_of_property_parse(pdev, host); 2543 2544 host->dev = &pdev->dev; 2545 host->dev_comp = of_device_get_match_data(&pdev->dev); 2546 host->src_clk_freq = clk_get_rate(host->src_clk); 2547 /* Set host parameters to mmc */ 2548 mmc->ops = &mt_msdc_ops; 2549 if (host->dev_comp->clk_div_bits == 8) 2550 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 2551 else 2552 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); 2553 2554 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && 2555 !mmc_can_gpio_cd(mmc) && 2556 host->dev_comp->use_internal_cd) { 2557 /* 2558 * Is removable but no GPIO declared, so 2559 * use internal functionality. 2560 */ 2561 host->internal_cd = true; 2562 } 2563 2564 if (mmc->caps & MMC_CAP_SDIO_IRQ) 2565 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2566 2567 mmc->caps |= MMC_CAP_CMD23; 2568 if (host->cqhci) 2569 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 2570 /* MMC core transfer sizes tunable parameters */ 2571 mmc->max_segs = MAX_BD_NUM; 2572 if (host->dev_comp->support_64g) 2573 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; 2574 else 2575 mmc->max_seg_size = BDMA_DESC_BUFLEN; 2576 mmc->max_blk_size = 2048; 2577 mmc->max_req_size = 512 * 1024; 2578 mmc->max_blk_count = mmc->max_req_size / 512; 2579 if (host->dev_comp->support_64g) 2580 host->dma_mask = DMA_BIT_MASK(36); 2581 else 2582 host->dma_mask = DMA_BIT_MASK(32); 2583 mmc_dev(mmc)->dma_mask = &host->dma_mask; 2584 2585 if (mmc->caps2 & MMC_CAP2_CQE) { 2586 host->cq_host = devm_kzalloc(mmc->parent, 2587 sizeof(*host->cq_host), 2588 GFP_KERNEL); 2589 if (!host->cq_host) { 2590 ret = -ENOMEM; 2591 goto host_free; 2592 } 2593 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 2594 host->cq_host->mmio = host->base + 0x800; 2595 host->cq_host->ops = &msdc_cmdq_ops; 2596 ret = cqhci_init(host->cq_host, mmc, true); 2597 if (ret) 2598 goto host_free; 2599 mmc->max_segs = 128; 2600 /* cqhci 16bit length */ 2601 /* 0 size, means 65536 so we don't have to -1 here */ 2602 mmc->max_seg_size = 64 * 1024; 2603 } 2604 2605 host->timeout_clks = 3 * 1048576; 2606 host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2607 2 * sizeof(struct mt_gpdma_desc), 2608 &host->dma.gpd_addr, GFP_KERNEL); 2609 host->dma.bd = dma_alloc_coherent(&pdev->dev, 2610 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2611 &host->dma.bd_addr, GFP_KERNEL); 2612 if (!host->dma.gpd || !host->dma.bd) { 2613 ret = -ENOMEM; 2614 goto release_mem; 2615 } 2616 msdc_init_gpd_bd(host, &host->dma); 2617 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 2618 spin_lock_init(&host->lock); 2619 2620 platform_set_drvdata(pdev, mmc); 2621 msdc_ungate_clock(host); 2622 msdc_init_hw(host); 2623 2624 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 2625 IRQF_TRIGGER_NONE, pdev->name, host); 2626 if (ret) 2627 goto release; 2628 2629 pm_runtime_set_active(host->dev); 2630 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 2631 pm_runtime_use_autosuspend(host->dev); 2632 pm_runtime_enable(host->dev); 2633 ret = mmc_add_host(mmc); 2634 2635 if (ret) 2636 goto end; 2637 2638 return 0; 2639 end: 2640 pm_runtime_disable(host->dev); 2641 release: 2642 platform_set_drvdata(pdev, NULL); 2643 msdc_deinit_hw(host); 2644 msdc_gate_clock(host); 2645 release_mem: 2646 if (host->dma.gpd) 2647 dma_free_coherent(&pdev->dev, 2648 2 * sizeof(struct mt_gpdma_desc), 2649 host->dma.gpd, host->dma.gpd_addr); 2650 if (host->dma.bd) 2651 dma_free_coherent(&pdev->dev, 2652 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2653 host->dma.bd, host->dma.bd_addr); 2654 host_free: 2655 mmc_free_host(mmc); 2656 2657 return ret; 2658 } 2659 2660 static int msdc_drv_remove(struct platform_device *pdev) 2661 { 2662 struct mmc_host *mmc; 2663 struct msdc_host *host; 2664 2665 mmc = platform_get_drvdata(pdev); 2666 host = mmc_priv(mmc); 2667 2668 pm_runtime_get_sync(host->dev); 2669 2670 platform_set_drvdata(pdev, NULL); 2671 mmc_remove_host(mmc); 2672 msdc_deinit_hw(host); 2673 msdc_gate_clock(host); 2674 2675 pm_runtime_disable(host->dev); 2676 pm_runtime_put_noidle(host->dev); 2677 dma_free_coherent(&pdev->dev, 2678 2 * sizeof(struct mt_gpdma_desc), 2679 host->dma.gpd, host->dma.gpd_addr); 2680 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2681 host->dma.bd, host->dma.bd_addr); 2682 2683 mmc_free_host(mmc); 2684 2685 return 0; 2686 } 2687 2688 static void msdc_save_reg(struct msdc_host *host) 2689 { 2690 u32 tune_reg = host->dev_comp->pad_tune_reg; 2691 2692 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 2693 host->save_para.iocon = readl(host->base + MSDC_IOCON); 2694 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 2695 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 2696 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 2697 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); 2698 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 2699 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2700 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 2701 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); 2702 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); 2703 if (host->top_base) { 2704 host->save_para.emmc_top_control = 2705 readl(host->top_base + EMMC_TOP_CONTROL); 2706 host->save_para.emmc_top_cmd = 2707 readl(host->top_base + EMMC_TOP_CMD); 2708 host->save_para.emmc50_pad_ds_tune = 2709 readl(host->top_base + EMMC50_PAD_DS_TUNE); 2710 } else { 2711 host->save_para.pad_tune = readl(host->base + tune_reg); 2712 } 2713 } 2714 2715 static void msdc_restore_reg(struct msdc_host *host) 2716 { 2717 struct mmc_host *mmc = mmc_from_priv(host); 2718 u32 tune_reg = host->dev_comp->pad_tune_reg; 2719 2720 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 2721 writel(host->save_para.iocon, host->base + MSDC_IOCON); 2722 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 2723 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 2724 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 2725 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); 2726 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 2727 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 2728 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 2729 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); 2730 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); 2731 if (host->top_base) { 2732 writel(host->save_para.emmc_top_control, 2733 host->top_base + EMMC_TOP_CONTROL); 2734 writel(host->save_para.emmc_top_cmd, 2735 host->top_base + EMMC_TOP_CMD); 2736 writel(host->save_para.emmc50_pad_ds_tune, 2737 host->top_base + EMMC50_PAD_DS_TUNE); 2738 } else { 2739 writel(host->save_para.pad_tune, host->base + tune_reg); 2740 } 2741 2742 if (sdio_irq_claimed(mmc)) 2743 __msdc_enable_sdio_irq(host, 1); 2744 } 2745 2746 static int __maybe_unused msdc_runtime_suspend(struct device *dev) 2747 { 2748 struct mmc_host *mmc = dev_get_drvdata(dev); 2749 struct msdc_host *host = mmc_priv(mmc); 2750 2751 msdc_save_reg(host); 2752 msdc_gate_clock(host); 2753 return 0; 2754 } 2755 2756 static int __maybe_unused msdc_runtime_resume(struct device *dev) 2757 { 2758 struct mmc_host *mmc = dev_get_drvdata(dev); 2759 struct msdc_host *host = mmc_priv(mmc); 2760 2761 msdc_ungate_clock(host); 2762 msdc_restore_reg(host); 2763 return 0; 2764 } 2765 2766 static int __maybe_unused msdc_suspend(struct device *dev) 2767 { 2768 struct mmc_host *mmc = dev_get_drvdata(dev); 2769 int ret; 2770 2771 if (mmc->caps2 & MMC_CAP2_CQE) { 2772 ret = cqhci_suspend(mmc); 2773 if (ret) 2774 return ret; 2775 } 2776 2777 return pm_runtime_force_suspend(dev); 2778 } 2779 2780 static int __maybe_unused msdc_resume(struct device *dev) 2781 { 2782 return pm_runtime_force_resume(dev); 2783 } 2784 2785 static const struct dev_pm_ops msdc_dev_pm_ops = { 2786 SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume) 2787 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 2788 }; 2789 2790 static struct platform_driver mt_msdc_driver = { 2791 .probe = msdc_drv_probe, 2792 .remove = msdc_drv_remove, 2793 .driver = { 2794 .name = "mtk-msdc", 2795 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 2796 .of_match_table = msdc_of_ids, 2797 .pm = &msdc_dev_pm_ops, 2798 }, 2799 }; 2800 2801 module_platform_driver(mt_msdc_driver); 2802 MODULE_LICENSE("GPL v2"); 2803 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 2804