1 /* 2 * Copyright (c) 2014-2015 MediaTek Inc. 3 * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/ioport.h> 20 #include <linux/irq.h> 21 #include <linux/of_address.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_gpio.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/regulator/consumer.h> 29 #include <linux/spinlock.h> 30 31 #include <linux/mmc/card.h> 32 #include <linux/mmc/core.h> 33 #include <linux/mmc/host.h> 34 #include <linux/mmc/mmc.h> 35 #include <linux/mmc/sd.h> 36 #include <linux/mmc/sdio.h> 37 38 #define MAX_BD_NUM 1024 39 40 /*--------------------------------------------------------------------------*/ 41 /* Common Definition */ 42 /*--------------------------------------------------------------------------*/ 43 #define MSDC_BUS_1BITS 0x0 44 #define MSDC_BUS_4BITS 0x1 45 #define MSDC_BUS_8BITS 0x2 46 47 #define MSDC_BURST_64B 0x6 48 49 /*--------------------------------------------------------------------------*/ 50 /* Register Offset */ 51 /*--------------------------------------------------------------------------*/ 52 #define MSDC_CFG 0x0 53 #define MSDC_IOCON 0x04 54 #define MSDC_PS 0x08 55 #define MSDC_INT 0x0c 56 #define MSDC_INTEN 0x10 57 #define MSDC_FIFOCS 0x14 58 #define SDC_CFG 0x30 59 #define SDC_CMD 0x34 60 #define SDC_ARG 0x38 61 #define SDC_STS 0x3c 62 #define SDC_RESP0 0x40 63 #define SDC_RESP1 0x44 64 #define SDC_RESP2 0x48 65 #define SDC_RESP3 0x4c 66 #define SDC_BLK_NUM 0x50 67 #define SDC_ACMD_RESP 0x80 68 #define MSDC_DMA_SA 0x90 69 #define MSDC_DMA_CTRL 0x98 70 #define MSDC_DMA_CFG 0x9c 71 #define MSDC_PATCH_BIT 0xb0 72 #define MSDC_PATCH_BIT1 0xb4 73 #define MSDC_PAD_TUNE 0xec 74 75 /*--------------------------------------------------------------------------*/ 76 /* Register Mask */ 77 /*--------------------------------------------------------------------------*/ 78 79 /* MSDC_CFG mask */ 80 #define MSDC_CFG_MODE (0x1 << 0) /* RW */ 81 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ 82 #define MSDC_CFG_RST (0x1 << 2) /* RW */ 83 #define MSDC_CFG_PIO (0x1 << 3) /* RW */ 84 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ 85 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ 86 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ 87 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ 88 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ 89 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ 90 91 /* MSDC_IOCON mask */ 92 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ 93 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ 94 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ 95 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ 96 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ 97 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ 98 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ 99 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ 100 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ 101 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ 102 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ 103 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ 104 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ 105 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ 106 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ 107 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ 108 109 /* MSDC_PS mask */ 110 #define MSDC_PS_CDEN (0x1 << 0) /* RW */ 111 #define MSDC_PS_CDSTS (0x1 << 1) /* R */ 112 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ 113 #define MSDC_PS_DAT (0xff << 16) /* R */ 114 #define MSDC_PS_CMD (0x1 << 24) /* R */ 115 #define MSDC_PS_WP (0x1 << 31) /* R */ 116 117 /* MSDC_INT mask */ 118 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ 119 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ 120 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ 121 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ 122 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ 123 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ 124 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ 125 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ 126 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ 127 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ 128 #define MSDC_INT_CSTA (0x1 << 11) /* R */ 129 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ 130 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ 131 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ 132 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ 133 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ 134 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ 135 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ 136 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ 137 138 /* MSDC_INTEN mask */ 139 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ 140 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ 141 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ 142 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ 143 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ 144 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ 145 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ 146 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ 147 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ 148 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ 149 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ 150 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ 151 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ 152 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ 153 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ 154 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ 155 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ 156 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ 157 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ 158 159 /* MSDC_FIFOCS mask */ 160 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 161 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 162 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ 163 164 /* SDC_CFG mask */ 165 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ 166 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ 167 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 168 #define SDC_CFG_SDIO (0x1 << 19) /* RW */ 169 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 170 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ 171 #define SDC_CFG_DTOC (0xff << 24) /* RW */ 172 173 /* SDC_STS mask */ 174 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ 175 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 176 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ 177 178 /* MSDC_DMA_CTRL mask */ 179 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ 180 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ 181 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ 182 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ 183 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ 184 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ 185 186 /* MSDC_DMA_CFG mask */ 187 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ 188 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ 189 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ 190 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ 191 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ 192 193 /* MSDC_PATCH_BIT mask */ 194 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ 195 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) 196 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) 197 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ 198 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ 199 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ 200 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ 201 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ 202 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ 203 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ 204 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ 205 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ 206 207 #define REQ_CMD_EIO (0x1 << 0) 208 #define REQ_CMD_TMO (0x1 << 1) 209 #define REQ_DAT_ERR (0x1 << 2) 210 #define REQ_STOP_EIO (0x1 << 3) 211 #define REQ_STOP_TMO (0x1 << 4) 212 #define REQ_CMD_BUSY (0x1 << 5) 213 214 #define MSDC_PREPARE_FLAG (0x1 << 0) 215 #define MSDC_ASYNC_FLAG (0x1 << 1) 216 #define MSDC_MMAP_FLAG (0x1 << 2) 217 218 #define MTK_MMC_AUTOSUSPEND_DELAY 50 219 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 220 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 221 222 /*--------------------------------------------------------------------------*/ 223 /* Descriptor Structure */ 224 /*--------------------------------------------------------------------------*/ 225 struct mt_gpdma_desc { 226 u32 gpd_info; 227 #define GPDMA_DESC_HWO (0x1 << 0) 228 #define GPDMA_DESC_BDP (0x1 << 1) 229 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 230 #define GPDMA_DESC_INT (0x1 << 16) 231 u32 next; 232 u32 ptr; 233 u32 gpd_data_len; 234 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 235 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ 236 u32 arg; 237 u32 blknum; 238 u32 cmd; 239 }; 240 241 struct mt_bdma_desc { 242 u32 bd_info; 243 #define BDMA_DESC_EOL (0x1 << 0) 244 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 245 #define BDMA_DESC_BLKPAD (0x1 << 17) 246 #define BDMA_DESC_DWPAD (0x1 << 18) 247 u32 next; 248 u32 ptr; 249 u32 bd_data_len; 250 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 251 }; 252 253 struct msdc_dma { 254 struct scatterlist *sg; /* I/O scatter list */ 255 struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 256 struct mt_bdma_desc *bd; /* pointer to bd array */ 257 dma_addr_t gpd_addr; /* the physical address of gpd array */ 258 dma_addr_t bd_addr; /* the physical address of bd array */ 259 }; 260 261 struct msdc_save_para { 262 u32 msdc_cfg; 263 u32 iocon; 264 u32 sdc_cfg; 265 u32 pad_tune; 266 u32 patch_bit0; 267 u32 patch_bit1; 268 }; 269 270 struct msdc_host { 271 struct device *dev; 272 struct mmc_host *mmc; /* mmc structure */ 273 int cmd_rsp; 274 275 spinlock_t lock; 276 struct mmc_request *mrq; 277 struct mmc_command *cmd; 278 struct mmc_data *data; 279 int error; 280 281 void __iomem *base; /* host base address */ 282 283 struct msdc_dma dma; /* dma channel */ 284 u64 dma_mask; 285 286 u32 timeout_ns; /* data timeout ns */ 287 u32 timeout_clks; /* data timeout clks */ 288 289 struct pinctrl *pinctrl; 290 struct pinctrl_state *pins_default; 291 struct pinctrl_state *pins_uhs; 292 struct delayed_work req_timeout; 293 int irq; /* host interrupt */ 294 295 struct clk *src_clk; /* msdc source clock */ 296 struct clk *h_clk; /* msdc h_clk */ 297 u32 mclk; /* mmc subsystem clock frequency */ 298 u32 src_clk_freq; /* source clock frequency */ 299 u32 sclk; /* SD/MS bus clock frequency */ 300 bool ddr; 301 bool vqmmc_enabled; 302 struct msdc_save_para save_para; /* used when gate HCLK */ 303 }; 304 305 static void sdr_set_bits(void __iomem *reg, u32 bs) 306 { 307 u32 val = readl(reg); 308 309 val |= bs; 310 writel(val, reg); 311 } 312 313 static void sdr_clr_bits(void __iomem *reg, u32 bs) 314 { 315 u32 val = readl(reg); 316 317 val &= ~bs; 318 writel(val, reg); 319 } 320 321 static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 322 { 323 unsigned int tv = readl(reg); 324 325 tv &= ~field; 326 tv |= ((val) << (ffs((unsigned int)field) - 1)); 327 writel(tv, reg); 328 } 329 330 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 331 { 332 unsigned int tv = readl(reg); 333 334 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 335 } 336 337 static void msdc_reset_hw(struct msdc_host *host) 338 { 339 u32 val; 340 341 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 342 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) 343 cpu_relax(); 344 345 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 346 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) 347 cpu_relax(); 348 349 val = readl(host->base + MSDC_INT); 350 writel(val, host->base + MSDC_INT); 351 } 352 353 static void msdc_cmd_next(struct msdc_host *host, 354 struct mmc_request *mrq, struct mmc_command *cmd); 355 356 static u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 357 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 358 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 359 360 static u8 msdc_dma_calcs(u8 *buf, u32 len) 361 { 362 u32 i, sum = 0; 363 364 for (i = 0; i < len; i++) 365 sum += buf[i]; 366 return 0xff - (u8) sum; 367 } 368 369 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 370 struct mmc_data *data) 371 { 372 unsigned int j, dma_len; 373 dma_addr_t dma_address; 374 u32 dma_ctrl; 375 struct scatterlist *sg; 376 struct mt_gpdma_desc *gpd; 377 struct mt_bdma_desc *bd; 378 379 sg = data->sg; 380 381 gpd = dma->gpd; 382 bd = dma->bd; 383 384 /* modify gpd */ 385 gpd->gpd_info |= GPDMA_DESC_HWO; 386 gpd->gpd_info |= GPDMA_DESC_BDP; 387 /* need to clear first. use these bits to calc checksum */ 388 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 389 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 390 391 /* modify bd */ 392 for_each_sg(data->sg, sg, data->sg_count, j) { 393 dma_address = sg_dma_address(sg); 394 dma_len = sg_dma_len(sg); 395 396 /* init bd */ 397 bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 398 bd[j].bd_info &= ~BDMA_DESC_DWPAD; 399 bd[j].ptr = (u32)dma_address; 400 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 401 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 402 403 if (j == data->sg_count - 1) /* the last bd */ 404 bd[j].bd_info |= BDMA_DESC_EOL; 405 else 406 bd[j].bd_info &= ~BDMA_DESC_EOL; 407 408 /* checksume need to clear first */ 409 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 410 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 411 } 412 413 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 414 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 415 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 416 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); 417 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 418 writel((u32)dma->gpd_addr, host->base + MSDC_DMA_SA); 419 } 420 421 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq) 422 { 423 struct mmc_data *data = mrq->data; 424 425 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 426 bool read = (data->flags & MMC_DATA_READ) != 0; 427 428 data->host_cookie |= MSDC_PREPARE_FLAG; 429 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 430 read ? DMA_FROM_DEVICE : DMA_TO_DEVICE); 431 } 432 } 433 434 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) 435 { 436 struct mmc_data *data = mrq->data; 437 438 if (data->host_cookie & MSDC_ASYNC_FLAG) 439 return; 440 441 if (data->host_cookie & MSDC_PREPARE_FLAG) { 442 bool read = (data->flags & MMC_DATA_READ) != 0; 443 444 dma_unmap_sg(host->dev, data->sg, data->sg_len, 445 read ? DMA_FROM_DEVICE : DMA_TO_DEVICE); 446 data->host_cookie &= ~MSDC_PREPARE_FLAG; 447 } 448 } 449 450 /* clock control primitives */ 451 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) 452 { 453 u32 timeout, clk_ns; 454 u32 mode = 0; 455 456 host->timeout_ns = ns; 457 host->timeout_clks = clks; 458 if (host->sclk == 0) { 459 timeout = 0; 460 } else { 461 clk_ns = 1000000000UL / host->sclk; 462 timeout = (ns + clk_ns - 1) / clk_ns + clks; 463 /* in 1048576 sclk cycle unit */ 464 timeout = (timeout + (0x1 << 20) - 1) >> 20; 465 sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode); 466 /*DDR mode will double the clk cycles for data timeout */ 467 timeout = mode >= 2 ? timeout * 2 : timeout; 468 timeout = timeout > 1 ? timeout - 1 : 0; 469 timeout = timeout > 255 ? 255 : timeout; 470 } 471 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout); 472 } 473 474 static void msdc_gate_clock(struct msdc_host *host) 475 { 476 clk_disable_unprepare(host->src_clk); 477 clk_disable_unprepare(host->h_clk); 478 } 479 480 static void msdc_ungate_clock(struct msdc_host *host) 481 { 482 clk_prepare_enable(host->h_clk); 483 clk_prepare_enable(host->src_clk); 484 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 485 cpu_relax(); 486 } 487 488 static void msdc_set_mclk(struct msdc_host *host, int ddr, u32 hz) 489 { 490 u32 mode; 491 u32 flags; 492 u32 div; 493 u32 sclk; 494 495 if (!hz) { 496 dev_dbg(host->dev, "set mclk to 0\n"); 497 host->mclk = 0; 498 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 499 return; 500 } 501 502 flags = readl(host->base + MSDC_INTEN); 503 sdr_clr_bits(host->base + MSDC_INTEN, flags); 504 if (ddr) { /* may need to modify later */ 505 mode = 0x2; /* ddr mode and use divisor */ 506 if (hz >= (host->src_clk_freq >> 2)) { 507 div = 0; /* mean div = 1/4 */ 508 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 509 } else { 510 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 511 sclk = (host->src_clk_freq >> 2) / div; 512 div = (div >> 1); 513 } 514 } else if (hz >= host->src_clk_freq) { 515 mode = 0x1; /* no divisor */ 516 div = 0; 517 sclk = host->src_clk_freq; 518 } else { 519 mode = 0x0; /* use divisor */ 520 if (hz >= (host->src_clk_freq >> 1)) { 521 div = 0; /* mean div = 1/2 */ 522 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 523 } else { 524 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 525 sclk = (host->src_clk_freq >> 2) / div; 526 } 527 } 528 sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 529 (mode << 8) | (div % 0xff)); 530 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 531 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 532 cpu_relax(); 533 host->sclk = sclk; 534 host->mclk = hz; 535 host->ddr = ddr; 536 /* need because clk changed. */ 537 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 538 sdr_set_bits(host->base + MSDC_INTEN, flags); 539 540 dev_dbg(host->dev, "sclk: %d, ddr: %d\n", host->sclk, ddr); 541 } 542 543 static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 544 struct mmc_request *mrq, struct mmc_command *cmd) 545 { 546 u32 resp; 547 548 switch (mmc_resp_type(cmd)) { 549 /* Actually, R1, R5, R6, R7 are the same */ 550 case MMC_RSP_R1: 551 resp = 0x1; 552 break; 553 case MMC_RSP_R1B: 554 resp = 0x7; 555 break; 556 case MMC_RSP_R2: 557 resp = 0x2; 558 break; 559 case MMC_RSP_R3: 560 resp = 0x3; 561 break; 562 case MMC_RSP_NONE: 563 default: 564 resp = 0x0; 565 break; 566 } 567 568 return resp; 569 } 570 571 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 572 struct mmc_request *mrq, struct mmc_command *cmd) 573 { 574 /* rawcmd : 575 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 576 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 577 */ 578 u32 opcode = cmd->opcode; 579 u32 resp = msdc_cmd_find_resp(host, mrq, cmd); 580 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 581 582 host->cmd_rsp = resp; 583 584 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 585 opcode == MMC_STOP_TRANSMISSION) 586 rawcmd |= (0x1 << 14); 587 else if (opcode == SD_SWITCH_VOLTAGE) 588 rawcmd |= (0x1 << 30); 589 else if (opcode == SD_APP_SEND_SCR || 590 opcode == SD_APP_SEND_NUM_WR_BLKS || 591 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 592 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 593 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 594 rawcmd |= (0x1 << 11); 595 596 if (cmd->data) { 597 struct mmc_data *data = cmd->data; 598 599 if (mmc_op_multi(opcode)) { 600 if (mmc_card_mmc(host->mmc->card) && mrq->sbc && 601 !(mrq->sbc->arg & 0xFFFF0000)) 602 rawcmd |= 0x2 << 28; /* AutoCMD23 */ 603 } 604 605 rawcmd |= ((data->blksz & 0xFFF) << 16); 606 if (data->flags & MMC_DATA_WRITE) 607 rawcmd |= (0x1 << 13); 608 if (data->blocks > 1) 609 rawcmd |= (0x2 << 11); 610 else 611 rawcmd |= (0x1 << 11); 612 /* Always use dma mode */ 613 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 614 615 if (host->timeout_ns != data->timeout_ns || 616 host->timeout_clks != data->timeout_clks) 617 msdc_set_timeout(host, data->timeout_ns, 618 data->timeout_clks); 619 620 writel(data->blocks, host->base + SDC_BLK_NUM); 621 } 622 return rawcmd; 623 } 624 625 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, 626 struct mmc_command *cmd, struct mmc_data *data) 627 { 628 bool read; 629 630 WARN_ON(host->data); 631 host->data = data; 632 read = data->flags & MMC_DATA_READ; 633 634 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 635 msdc_dma_setup(host, &host->dma, data); 636 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 637 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 638 dev_dbg(host->dev, "DMA start\n"); 639 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 640 __func__, cmd->opcode, data->blocks, read); 641 } 642 643 static int msdc_auto_cmd_done(struct msdc_host *host, int events, 644 struct mmc_command *cmd) 645 { 646 u32 *rsp = cmd->resp; 647 648 rsp[0] = readl(host->base + SDC_ACMD_RESP); 649 650 if (events & MSDC_INT_ACMDRDY) { 651 cmd->error = 0; 652 } else { 653 msdc_reset_hw(host); 654 if (events & MSDC_INT_ACMDCRCERR) { 655 cmd->error = -EILSEQ; 656 host->error |= REQ_STOP_EIO; 657 } else if (events & MSDC_INT_ACMDTMO) { 658 cmd->error = -ETIMEDOUT; 659 host->error |= REQ_STOP_TMO; 660 } 661 dev_err(host->dev, 662 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 663 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 664 } 665 return cmd->error; 666 } 667 668 static void msdc_track_cmd_data(struct msdc_host *host, 669 struct mmc_command *cmd, struct mmc_data *data) 670 { 671 if (host->error) 672 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 673 __func__, cmd->opcode, cmd->arg, host->error); 674 } 675 676 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 677 { 678 unsigned long flags; 679 bool ret; 680 681 ret = cancel_delayed_work(&host->req_timeout); 682 if (!ret) { 683 /* delay work already running */ 684 return; 685 } 686 spin_lock_irqsave(&host->lock, flags); 687 host->mrq = NULL; 688 spin_unlock_irqrestore(&host->lock, flags); 689 690 msdc_track_cmd_data(host, mrq->cmd, mrq->data); 691 if (mrq->data) 692 msdc_unprepare_data(host, mrq); 693 mmc_request_done(host->mmc, mrq); 694 695 pm_runtime_mark_last_busy(host->dev); 696 pm_runtime_put_autosuspend(host->dev); 697 } 698 699 /* returns true if command is fully handled; returns false otherwise */ 700 static bool msdc_cmd_done(struct msdc_host *host, int events, 701 struct mmc_request *mrq, struct mmc_command *cmd) 702 { 703 bool done = false; 704 bool sbc_error; 705 unsigned long flags; 706 u32 *rsp = cmd->resp; 707 708 if (mrq->sbc && cmd == mrq->cmd && 709 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 710 | MSDC_INT_ACMDTMO))) 711 msdc_auto_cmd_done(host, events, mrq->sbc); 712 713 sbc_error = mrq->sbc && mrq->sbc->error; 714 715 if (!sbc_error && !(events & (MSDC_INT_CMDRDY 716 | MSDC_INT_RSPCRCERR 717 | MSDC_INT_CMDTMO))) 718 return done; 719 720 spin_lock_irqsave(&host->lock, flags); 721 done = !host->cmd; 722 host->cmd = NULL; 723 spin_unlock_irqrestore(&host->lock, flags); 724 725 if (done) 726 return true; 727 728 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CMDRDY | 729 MSDC_INTEN_RSPCRCERR | MSDC_INTEN_CMDTMO | 730 MSDC_INTEN_ACMDRDY | MSDC_INTEN_ACMDCRCERR | 731 MSDC_INTEN_ACMDTMO); 732 writel(cmd->arg, host->base + SDC_ARG); 733 734 if (cmd->flags & MMC_RSP_PRESENT) { 735 if (cmd->flags & MMC_RSP_136) { 736 rsp[0] = readl(host->base + SDC_RESP3); 737 rsp[1] = readl(host->base + SDC_RESP2); 738 rsp[2] = readl(host->base + SDC_RESP1); 739 rsp[3] = readl(host->base + SDC_RESP0); 740 } else { 741 rsp[0] = readl(host->base + SDC_RESP0); 742 } 743 } 744 745 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 746 msdc_reset_hw(host); 747 if (events & MSDC_INT_RSPCRCERR) { 748 cmd->error = -EILSEQ; 749 host->error |= REQ_CMD_EIO; 750 } else if (events & MSDC_INT_CMDTMO) { 751 cmd->error = -ETIMEDOUT; 752 host->error |= REQ_CMD_TMO; 753 } 754 } 755 if (cmd->error) 756 dev_dbg(host->dev, 757 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 758 __func__, cmd->opcode, cmd->arg, rsp[0], 759 cmd->error); 760 761 msdc_cmd_next(host, mrq, cmd); 762 return true; 763 } 764 765 /* It is the core layer's responsibility to ensure card status 766 * is correct before issue a request. but host design do below 767 * checks recommended. 768 */ 769 static inline bool msdc_cmd_is_ready(struct msdc_host *host, 770 struct mmc_request *mrq, struct mmc_command *cmd) 771 { 772 /* The max busy time we can endure is 20ms */ 773 unsigned long tmo = jiffies + msecs_to_jiffies(20); 774 775 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && 776 time_before(jiffies, tmo)) 777 cpu_relax(); 778 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { 779 dev_err(host->dev, "CMD bus busy detected\n"); 780 host->error |= REQ_CMD_BUSY; 781 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 782 return false; 783 } 784 785 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 786 tmo = jiffies + msecs_to_jiffies(20); 787 /* R1B or with data, should check SDCBUSY */ 788 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && 789 time_before(jiffies, tmo)) 790 cpu_relax(); 791 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { 792 dev_err(host->dev, "Controller busy detected\n"); 793 host->error |= REQ_CMD_BUSY; 794 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 795 return false; 796 } 797 } 798 return true; 799 } 800 801 static void msdc_start_command(struct msdc_host *host, 802 struct mmc_request *mrq, struct mmc_command *cmd) 803 { 804 u32 rawcmd; 805 806 WARN_ON(host->cmd); 807 host->cmd = cmd; 808 809 if (!msdc_cmd_is_ready(host, mrq, cmd)) 810 return; 811 812 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 813 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 814 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 815 msdc_reset_hw(host); 816 } 817 818 cmd->error = 0; 819 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 820 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 821 822 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CMDRDY | 823 MSDC_INTEN_RSPCRCERR | MSDC_INTEN_CMDTMO | 824 MSDC_INTEN_ACMDRDY | MSDC_INTEN_ACMDCRCERR | 825 MSDC_INTEN_ACMDTMO); 826 writel(cmd->arg, host->base + SDC_ARG); 827 writel(rawcmd, host->base + SDC_CMD); 828 } 829 830 static void msdc_cmd_next(struct msdc_host *host, 831 struct mmc_request *mrq, struct mmc_command *cmd) 832 { 833 if (cmd->error || (mrq->sbc && mrq->sbc->error)) 834 msdc_request_done(host, mrq); 835 else if (cmd == mrq->sbc) 836 msdc_start_command(host, mrq, mrq->cmd); 837 else if (!cmd->data) 838 msdc_request_done(host, mrq); 839 else 840 msdc_start_data(host, mrq, cmd, cmd->data); 841 } 842 843 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 844 { 845 struct msdc_host *host = mmc_priv(mmc); 846 847 host->error = 0; 848 WARN_ON(host->mrq); 849 host->mrq = mrq; 850 851 pm_runtime_get_sync(host->dev); 852 853 if (mrq->data) 854 msdc_prepare_data(host, mrq); 855 856 /* if SBC is required, we have HW option and SW option. 857 * if HW option is enabled, and SBC does not have "special" flags, 858 * use HW option, otherwise use SW option 859 */ 860 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 861 (mrq->sbc->arg & 0xFFFF0000))) 862 msdc_start_command(host, mrq, mrq->sbc); 863 else 864 msdc_start_command(host, mrq, mrq->cmd); 865 } 866 867 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 868 bool is_first_req) 869 { 870 struct msdc_host *host = mmc_priv(mmc); 871 struct mmc_data *data = mrq->data; 872 873 if (!data) 874 return; 875 876 msdc_prepare_data(host, mrq); 877 data->host_cookie |= MSDC_ASYNC_FLAG; 878 } 879 880 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 881 int err) 882 { 883 struct msdc_host *host = mmc_priv(mmc); 884 struct mmc_data *data; 885 886 data = mrq->data; 887 if (!data) 888 return; 889 if (data->host_cookie) { 890 data->host_cookie &= ~MSDC_ASYNC_FLAG; 891 msdc_unprepare_data(host, mrq); 892 } 893 } 894 895 static void msdc_data_xfer_next(struct msdc_host *host, 896 struct mmc_request *mrq, struct mmc_data *data) 897 { 898 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 899 (!data->bytes_xfered || !mrq->sbc)) 900 msdc_start_command(host, mrq, mrq->stop); 901 else 902 msdc_request_done(host, mrq); 903 } 904 905 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 906 struct mmc_request *mrq, struct mmc_data *data) 907 { 908 struct mmc_command *stop = data->stop; 909 unsigned long flags; 910 bool done; 911 unsigned int check_data = events & 912 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 913 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 914 | MSDC_INT_DMA_PROTECT); 915 916 spin_lock_irqsave(&host->lock, flags); 917 done = !host->data; 918 if (check_data) 919 host->data = NULL; 920 spin_unlock_irqrestore(&host->lock, flags); 921 922 if (done) 923 return true; 924 925 if (check_data || (stop && stop->error)) { 926 dev_dbg(host->dev, "DMA status: 0x%8X\n", 927 readl(host->base + MSDC_DMA_CFG)); 928 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 929 1); 930 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) 931 cpu_relax(); 932 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 933 dev_dbg(host->dev, "DMA stop\n"); 934 935 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 936 data->bytes_xfered = data->blocks * data->blksz; 937 } else { 938 dev_err(host->dev, "interrupt events: %x\n", events); 939 msdc_reset_hw(host); 940 host->error |= REQ_DAT_ERR; 941 data->bytes_xfered = 0; 942 943 if (events & MSDC_INT_DATTMO) 944 data->error = -ETIMEDOUT; 945 946 dev_err(host->dev, "%s: cmd=%d; blocks=%d", 947 __func__, mrq->cmd->opcode, data->blocks); 948 dev_err(host->dev, "data_error=%d xfer_size=%d\n", 949 (int)data->error, data->bytes_xfered); 950 } 951 952 msdc_data_xfer_next(host, mrq, data); 953 done = true; 954 } 955 return done; 956 } 957 958 static void msdc_set_buswidth(struct msdc_host *host, u32 width) 959 { 960 u32 val = readl(host->base + SDC_CFG); 961 962 val &= ~SDC_CFG_BUSWIDTH; 963 964 switch (width) { 965 default: 966 case MMC_BUS_WIDTH_1: 967 val |= (MSDC_BUS_1BITS << 16); 968 break; 969 case MMC_BUS_WIDTH_4: 970 val |= (MSDC_BUS_4BITS << 16); 971 break; 972 case MMC_BUS_WIDTH_8: 973 val |= (MSDC_BUS_8BITS << 16); 974 break; 975 } 976 977 writel(val, host->base + SDC_CFG); 978 dev_dbg(host->dev, "Bus Width = %d", width); 979 } 980 981 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 982 { 983 struct msdc_host *host = mmc_priv(mmc); 984 int min_uv, max_uv; 985 int ret = 0; 986 987 if (!IS_ERR(mmc->supply.vqmmc)) { 988 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 989 min_uv = 3300000; 990 max_uv = 3300000; 991 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 992 min_uv = 1800000; 993 max_uv = 1800000; 994 } else { 995 dev_err(host->dev, "Unsupported signal voltage!\n"); 996 return -EINVAL; 997 } 998 999 ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv); 1000 if (ret) { 1001 dev_err(host->dev, 1002 "Regulator set error %d: %d - %d\n", 1003 ret, min_uv, max_uv); 1004 } else { 1005 /* Apply different pinctrl settings for different signal voltage */ 1006 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 1007 pinctrl_select_state(host->pinctrl, host->pins_uhs); 1008 else 1009 pinctrl_select_state(host->pinctrl, host->pins_default); 1010 } 1011 } 1012 return ret; 1013 } 1014 1015 static int msdc_card_busy(struct mmc_host *mmc) 1016 { 1017 struct msdc_host *host = mmc_priv(mmc); 1018 u32 status = readl(host->base + MSDC_PS); 1019 1020 /* check if any pin between dat[0:3] is low */ 1021 if (((status >> 16) & 0xf) != 0xf) 1022 return 1; 1023 1024 return 0; 1025 } 1026 1027 static void msdc_request_timeout(struct work_struct *work) 1028 { 1029 struct msdc_host *host = container_of(work, struct msdc_host, 1030 req_timeout.work); 1031 1032 /* simulate HW timeout status */ 1033 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 1034 if (host->mrq) { 1035 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 1036 host->mrq, host->mrq->cmd->opcode); 1037 if (host->cmd) { 1038 dev_err(host->dev, "%s: aborting cmd=%d\n", 1039 __func__, host->cmd->opcode); 1040 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 1041 host->cmd); 1042 } else if (host->data) { 1043 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 1044 __func__, host->mrq->cmd->opcode, 1045 host->data->blocks); 1046 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 1047 host->data); 1048 } 1049 } 1050 } 1051 1052 static irqreturn_t msdc_irq(int irq, void *dev_id) 1053 { 1054 struct msdc_host *host = (struct msdc_host *) dev_id; 1055 1056 while (true) { 1057 unsigned long flags; 1058 struct mmc_request *mrq; 1059 struct mmc_command *cmd; 1060 struct mmc_data *data; 1061 u32 events, event_mask; 1062 1063 spin_lock_irqsave(&host->lock, flags); 1064 events = readl(host->base + MSDC_INT); 1065 event_mask = readl(host->base + MSDC_INTEN); 1066 /* clear interrupts */ 1067 writel(events & event_mask, host->base + MSDC_INT); 1068 1069 mrq = host->mrq; 1070 cmd = host->cmd; 1071 data = host->data; 1072 spin_unlock_irqrestore(&host->lock, flags); 1073 1074 if (!(events & event_mask)) 1075 break; 1076 1077 if (!mrq) { 1078 dev_err(host->dev, 1079 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 1080 __func__, events, event_mask); 1081 WARN_ON(1); 1082 break; 1083 } 1084 1085 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 1086 1087 if (cmd) 1088 msdc_cmd_done(host, events, mrq, cmd); 1089 else if (data) 1090 msdc_data_xfer_done(host, events, mrq, data); 1091 } 1092 1093 return IRQ_HANDLED; 1094 } 1095 1096 static void msdc_init_hw(struct msdc_host *host) 1097 { 1098 u32 val; 1099 1100 /* Configure to MMC/SD mode, clock free running */ 1101 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 1102 1103 /* Reset */ 1104 msdc_reset_hw(host); 1105 1106 /* Disable card detection */ 1107 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1108 1109 /* Disable and clear all interrupts */ 1110 writel(0, host->base + MSDC_INTEN); 1111 val = readl(host->base + MSDC_INT); 1112 writel(val, host->base + MSDC_INT); 1113 1114 writel(0, host->base + MSDC_PAD_TUNE); 1115 writel(0, host->base + MSDC_IOCON); 1116 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 1); 1117 writel(0x403c004f, host->base + MSDC_PATCH_BIT); 1118 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 1119 writel(0xffff0089, host->base + MSDC_PATCH_BIT1); 1120 /* Configure to enable SDIO mode. 1121 * it's must otherwise sdio cmd5 failed 1122 */ 1123 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1124 1125 /* disable detect SDIO device interrupt function */ 1126 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1127 1128 /* Configure to default data timeout */ 1129 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 1130 1131 dev_dbg(host->dev, "init hardware done!"); 1132 } 1133 1134 static void msdc_deinit_hw(struct msdc_host *host) 1135 { 1136 u32 val; 1137 /* Disable and clear all interrupts */ 1138 writel(0, host->base + MSDC_INTEN); 1139 1140 val = readl(host->base + MSDC_INT); 1141 writel(val, host->base + MSDC_INT); 1142 } 1143 1144 /* init gpd and bd list in msdc_drv_probe */ 1145 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 1146 { 1147 struct mt_gpdma_desc *gpd = dma->gpd; 1148 struct mt_bdma_desc *bd = dma->bd; 1149 int i; 1150 1151 memset(gpd, 0, sizeof(struct mt_gpdma_desc)); 1152 1153 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 1154 gpd->ptr = (u32)dma->bd_addr; /* physical address */ 1155 1156 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 1157 for (i = 0; i < (MAX_BD_NUM - 1); i++) 1158 bd[i].next = (u32)dma->bd_addr + sizeof(*bd) * (i + 1); 1159 } 1160 1161 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1162 { 1163 struct msdc_host *host = mmc_priv(mmc); 1164 int ret; 1165 u32 ddr = 0; 1166 1167 pm_runtime_get_sync(host->dev); 1168 1169 if (ios->timing == MMC_TIMING_UHS_DDR50 || 1170 ios->timing == MMC_TIMING_MMC_DDR52) 1171 ddr = 1; 1172 1173 msdc_set_buswidth(host, ios->bus_width); 1174 1175 /* Suspend/Resume will do power off/on */ 1176 switch (ios->power_mode) { 1177 case MMC_POWER_UP: 1178 if (!IS_ERR(mmc->supply.vmmc)) { 1179 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1180 ios->vdd); 1181 if (ret) { 1182 dev_err(host->dev, "Failed to set vmmc power!\n"); 1183 goto end; 1184 } 1185 } 1186 break; 1187 case MMC_POWER_ON: 1188 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1189 ret = regulator_enable(mmc->supply.vqmmc); 1190 if (ret) 1191 dev_err(host->dev, "Failed to set vqmmc power!\n"); 1192 else 1193 host->vqmmc_enabled = true; 1194 } 1195 break; 1196 case MMC_POWER_OFF: 1197 if (!IS_ERR(mmc->supply.vmmc)) 1198 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1199 1200 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1201 regulator_disable(mmc->supply.vqmmc); 1202 host->vqmmc_enabled = false; 1203 } 1204 break; 1205 default: 1206 break; 1207 } 1208 1209 if (host->mclk != ios->clock || host->ddr != ddr) 1210 msdc_set_mclk(host, ddr, ios->clock); 1211 1212 end: 1213 pm_runtime_mark_last_busy(host->dev); 1214 pm_runtime_put_autosuspend(host->dev); 1215 } 1216 1217 static struct mmc_host_ops mt_msdc_ops = { 1218 .post_req = msdc_post_req, 1219 .pre_req = msdc_pre_req, 1220 .request = msdc_ops_request, 1221 .set_ios = msdc_ops_set_ios, 1222 .start_signal_voltage_switch = msdc_ops_switch_volt, 1223 .card_busy = msdc_card_busy, 1224 }; 1225 1226 static int msdc_drv_probe(struct platform_device *pdev) 1227 { 1228 struct mmc_host *mmc; 1229 struct msdc_host *host; 1230 struct resource *res; 1231 int ret; 1232 1233 if (!pdev->dev.of_node) { 1234 dev_err(&pdev->dev, "No DT found\n"); 1235 return -EINVAL; 1236 } 1237 /* Allocate MMC host for this device */ 1238 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 1239 if (!mmc) 1240 return -ENOMEM; 1241 1242 host = mmc_priv(mmc); 1243 ret = mmc_of_parse(mmc); 1244 if (ret) 1245 goto host_free; 1246 1247 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1248 host->base = devm_ioremap_resource(&pdev->dev, res); 1249 if (IS_ERR(host->base)) { 1250 ret = PTR_ERR(host->base); 1251 goto host_free; 1252 } 1253 1254 ret = mmc_regulator_get_supply(mmc); 1255 if (ret == -EPROBE_DEFER) 1256 goto host_free; 1257 1258 host->src_clk = devm_clk_get(&pdev->dev, "source"); 1259 if (IS_ERR(host->src_clk)) { 1260 ret = PTR_ERR(host->src_clk); 1261 goto host_free; 1262 } 1263 1264 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 1265 if (IS_ERR(host->h_clk)) { 1266 ret = PTR_ERR(host->h_clk); 1267 goto host_free; 1268 } 1269 1270 host->irq = platform_get_irq(pdev, 0); 1271 if (host->irq < 0) { 1272 ret = -EINVAL; 1273 goto host_free; 1274 } 1275 1276 host->pinctrl = devm_pinctrl_get(&pdev->dev); 1277 if (IS_ERR(host->pinctrl)) { 1278 ret = PTR_ERR(host->pinctrl); 1279 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 1280 goto host_free; 1281 } 1282 1283 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 1284 if (IS_ERR(host->pins_default)) { 1285 ret = PTR_ERR(host->pins_default); 1286 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 1287 goto host_free; 1288 } 1289 1290 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 1291 if (IS_ERR(host->pins_uhs)) { 1292 ret = PTR_ERR(host->pins_uhs); 1293 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 1294 goto host_free; 1295 } 1296 1297 host->dev = &pdev->dev; 1298 host->mmc = mmc; 1299 host->src_clk_freq = clk_get_rate(host->src_clk); 1300 /* Set host parameters to mmc */ 1301 mmc->ops = &mt_msdc_ops; 1302 mmc->f_min = host->src_clk_freq / (4 * 255); 1303 1304 mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; 1305 /* MMC core transfer sizes tunable parameters */ 1306 mmc->max_segs = MAX_BD_NUM; 1307 mmc->max_seg_size = BDMA_DESC_BUFLEN; 1308 mmc->max_blk_size = 2048; 1309 mmc->max_req_size = 512 * 1024; 1310 mmc->max_blk_count = mmc->max_req_size / 512; 1311 host->dma_mask = DMA_BIT_MASK(32); 1312 mmc_dev(mmc)->dma_mask = &host->dma_mask; 1313 1314 host->timeout_clks = 3 * 1048576; 1315 host->dma.gpd = dma_alloc_coherent(&pdev->dev, 1316 sizeof(struct mt_gpdma_desc), 1317 &host->dma.gpd_addr, GFP_KERNEL); 1318 host->dma.bd = dma_alloc_coherent(&pdev->dev, 1319 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 1320 &host->dma.bd_addr, GFP_KERNEL); 1321 if (!host->dma.gpd || !host->dma.bd) { 1322 ret = -ENOMEM; 1323 goto release_mem; 1324 } 1325 msdc_init_gpd_bd(host, &host->dma); 1326 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 1327 spin_lock_init(&host->lock); 1328 1329 platform_set_drvdata(pdev, mmc); 1330 msdc_ungate_clock(host); 1331 msdc_init_hw(host); 1332 1333 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 1334 IRQF_TRIGGER_LOW | IRQF_ONESHOT, pdev->name, host); 1335 if (ret) 1336 goto release; 1337 1338 pm_runtime_set_active(host->dev); 1339 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 1340 pm_runtime_use_autosuspend(host->dev); 1341 pm_runtime_enable(host->dev); 1342 ret = mmc_add_host(mmc); 1343 1344 if (ret) 1345 goto end; 1346 1347 return 0; 1348 end: 1349 pm_runtime_disable(host->dev); 1350 release: 1351 platform_set_drvdata(pdev, NULL); 1352 msdc_deinit_hw(host); 1353 msdc_gate_clock(host); 1354 release_mem: 1355 if (host->dma.gpd) 1356 dma_free_coherent(&pdev->dev, 1357 sizeof(struct mt_gpdma_desc), 1358 host->dma.gpd, host->dma.gpd_addr); 1359 if (host->dma.bd) 1360 dma_free_coherent(&pdev->dev, 1361 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 1362 host->dma.bd, host->dma.bd_addr); 1363 host_free: 1364 mmc_free_host(mmc); 1365 1366 return ret; 1367 } 1368 1369 static int msdc_drv_remove(struct platform_device *pdev) 1370 { 1371 struct mmc_host *mmc; 1372 struct msdc_host *host; 1373 1374 mmc = platform_get_drvdata(pdev); 1375 host = mmc_priv(mmc); 1376 1377 pm_runtime_get_sync(host->dev); 1378 1379 platform_set_drvdata(pdev, NULL); 1380 mmc_remove_host(host->mmc); 1381 msdc_deinit_hw(host); 1382 msdc_gate_clock(host); 1383 1384 pm_runtime_disable(host->dev); 1385 pm_runtime_put_noidle(host->dev); 1386 dma_free_coherent(&pdev->dev, 1387 sizeof(struct mt_gpdma_desc), 1388 host->dma.gpd, host->dma.gpd_addr); 1389 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 1390 host->dma.bd, host->dma.bd_addr); 1391 1392 mmc_free_host(host->mmc); 1393 1394 return 0; 1395 } 1396 1397 #ifdef CONFIG_PM 1398 static void msdc_save_reg(struct msdc_host *host) 1399 { 1400 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 1401 host->save_para.iocon = readl(host->base + MSDC_IOCON); 1402 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 1403 host->save_para.pad_tune = readl(host->base + MSDC_PAD_TUNE); 1404 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 1405 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 1406 } 1407 1408 static void msdc_restore_reg(struct msdc_host *host) 1409 { 1410 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 1411 writel(host->save_para.iocon, host->base + MSDC_IOCON); 1412 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 1413 writel(host->save_para.pad_tune, host->base + MSDC_PAD_TUNE); 1414 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 1415 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 1416 } 1417 1418 static int msdc_runtime_suspend(struct device *dev) 1419 { 1420 struct mmc_host *mmc = dev_get_drvdata(dev); 1421 struct msdc_host *host = mmc_priv(mmc); 1422 1423 msdc_save_reg(host); 1424 msdc_gate_clock(host); 1425 return 0; 1426 } 1427 1428 static int msdc_runtime_resume(struct device *dev) 1429 { 1430 struct mmc_host *mmc = dev_get_drvdata(dev); 1431 struct msdc_host *host = mmc_priv(mmc); 1432 1433 msdc_ungate_clock(host); 1434 msdc_restore_reg(host); 1435 return 0; 1436 } 1437 #endif 1438 1439 static const struct dev_pm_ops msdc_dev_pm_ops = { 1440 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1441 pm_runtime_force_resume) 1442 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 1443 }; 1444 1445 static const struct of_device_id msdc_of_ids[] = { 1446 { .compatible = "mediatek,mt8135-mmc", }, 1447 {} 1448 }; 1449 1450 static struct platform_driver mt_msdc_driver = { 1451 .probe = msdc_drv_probe, 1452 .remove = msdc_drv_remove, 1453 .driver = { 1454 .name = "mtk-msdc", 1455 .of_match_table = msdc_of_ids, 1456 .pm = &msdc_dev_pm_ops, 1457 }, 1458 }; 1459 1460 module_platform_driver(mt_msdc_driver); 1461 MODULE_LICENSE("GPL v2"); 1462 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 1463