1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2015 MediaTek Inc. 4 * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 5 */ 6 7 #include <linux/module.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/ioport.h> 12 #include <linux/irq.h> 13 #include <linux/of_address.h> 14 #include <linux/of_device.h> 15 #include <linux/of_irq.h> 16 #include <linux/of_gpio.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/slab.h> 23 #include <linux/spinlock.h> 24 #include <linux/interrupt.h> 25 26 #include <linux/mmc/card.h> 27 #include <linux/mmc/core.h> 28 #include <linux/mmc/host.h> 29 #include <linux/mmc/mmc.h> 30 #include <linux/mmc/sd.h> 31 #include <linux/mmc/sdio.h> 32 #include <linux/mmc/slot-gpio.h> 33 34 #define MAX_BD_NUM 1024 35 36 /*--------------------------------------------------------------------------*/ 37 /* Common Definition */ 38 /*--------------------------------------------------------------------------*/ 39 #define MSDC_BUS_1BITS 0x0 40 #define MSDC_BUS_4BITS 0x1 41 #define MSDC_BUS_8BITS 0x2 42 43 #define MSDC_BURST_64B 0x6 44 45 /*--------------------------------------------------------------------------*/ 46 /* Register Offset */ 47 /*--------------------------------------------------------------------------*/ 48 #define MSDC_CFG 0x0 49 #define MSDC_IOCON 0x04 50 #define MSDC_PS 0x08 51 #define MSDC_INT 0x0c 52 #define MSDC_INTEN 0x10 53 #define MSDC_FIFOCS 0x14 54 #define SDC_CFG 0x30 55 #define SDC_CMD 0x34 56 #define SDC_ARG 0x38 57 #define SDC_STS 0x3c 58 #define SDC_RESP0 0x40 59 #define SDC_RESP1 0x44 60 #define SDC_RESP2 0x48 61 #define SDC_RESP3 0x4c 62 #define SDC_BLK_NUM 0x50 63 #define SDC_ADV_CFG0 0x64 64 #define EMMC_IOCON 0x7c 65 #define SDC_ACMD_RESP 0x80 66 #define DMA_SA_H4BIT 0x8c 67 #define MSDC_DMA_SA 0x90 68 #define MSDC_DMA_CTRL 0x98 69 #define MSDC_DMA_CFG 0x9c 70 #define MSDC_PATCH_BIT 0xb0 71 #define MSDC_PATCH_BIT1 0xb4 72 #define MSDC_PATCH_BIT2 0xb8 73 #define MSDC_PAD_TUNE 0xec 74 #define MSDC_PAD_TUNE0 0xf0 75 #define PAD_DS_TUNE 0x188 76 #define PAD_CMD_TUNE 0x18c 77 #define EMMC50_CFG0 0x208 78 #define EMMC50_CFG3 0x220 79 #define SDC_FIFO_CFG 0x228 80 81 /*--------------------------------------------------------------------------*/ 82 /* Top Pad Register Offset */ 83 /*--------------------------------------------------------------------------*/ 84 #define EMMC_TOP_CONTROL 0x00 85 #define EMMC_TOP_CMD 0x04 86 #define EMMC50_PAD_DS_TUNE 0x0c 87 88 /*--------------------------------------------------------------------------*/ 89 /* Register Mask */ 90 /*--------------------------------------------------------------------------*/ 91 92 /* MSDC_CFG mask */ 93 #define MSDC_CFG_MODE (0x1 << 0) /* RW */ 94 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ 95 #define MSDC_CFG_RST (0x1 << 2) /* RW */ 96 #define MSDC_CFG_PIO (0x1 << 3) /* RW */ 97 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ 98 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ 99 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ 100 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ 101 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ 102 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ 103 #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */ 104 #define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */ 105 #define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */ 106 #define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */ 107 108 /* MSDC_IOCON mask */ 109 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ 110 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ 111 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ 112 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ 113 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ 114 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ 115 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ 116 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ 117 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ 118 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ 119 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ 120 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ 121 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ 122 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ 123 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ 124 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ 125 126 /* MSDC_PS mask */ 127 #define MSDC_PS_CDEN (0x1 << 0) /* RW */ 128 #define MSDC_PS_CDSTS (0x1 << 1) /* R */ 129 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ 130 #define MSDC_PS_DAT (0xff << 16) /* R */ 131 #define MSDC_PS_CMD (0x1 << 24) /* R */ 132 #define MSDC_PS_WP (0x1 << 31) /* R */ 133 134 /* MSDC_INT mask */ 135 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ 136 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ 137 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ 138 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ 139 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ 140 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ 141 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ 142 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ 143 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ 144 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ 145 #define MSDC_INT_CSTA (0x1 << 11) /* R */ 146 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ 147 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ 148 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ 149 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ 150 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ 151 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ 152 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ 153 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ 154 155 /* MSDC_INTEN mask */ 156 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ 157 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ 158 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ 159 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ 160 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ 161 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ 162 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ 163 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ 164 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ 165 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ 166 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ 167 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ 168 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ 169 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ 170 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ 171 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ 172 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ 173 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ 174 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ 175 176 /* MSDC_FIFOCS mask */ 177 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 178 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 179 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ 180 181 /* SDC_CFG mask */ 182 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ 183 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ 184 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 185 #define SDC_CFG_SDIO (0x1 << 19) /* RW */ 186 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 187 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ 188 #define SDC_CFG_DTOC (0xff << 24) /* RW */ 189 190 /* SDC_STS mask */ 191 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ 192 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 193 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ 194 195 /* SDC_ADV_CFG0 mask */ 196 #define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */ 197 198 /* DMA_SA_H4BIT mask */ 199 #define DMA_ADDR_HIGH_4BIT (0xf << 0) /* RW */ 200 201 /* MSDC_DMA_CTRL mask */ 202 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ 203 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ 204 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ 205 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ 206 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ 207 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ 208 209 /* MSDC_DMA_CFG mask */ 210 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ 211 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ 212 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ 213 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ 214 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ 215 216 /* MSDC_PATCH_BIT mask */ 217 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ 218 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) 219 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) 220 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ 221 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ 222 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ 223 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ 224 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ 225 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ 226 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ 227 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ 228 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ 229 230 #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ 231 232 #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ 233 #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */ 234 #define MSDC_PB2_SUPPORT_64G (0x1 << 1) /* RW */ 235 #define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */ 236 #define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */ 237 #define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */ 238 239 #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */ 240 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */ 241 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */ 242 #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */ 243 #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */ 244 #define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */ 245 #define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */ 246 #define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */ 247 248 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */ 249 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */ 250 #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */ 251 252 #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */ 253 254 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */ 255 #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ 256 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ 257 258 #define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */ 259 260 #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */ 261 #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */ 262 263 /* EMMC_TOP_CONTROL mask */ 264 #define PAD_RXDLY_SEL (0x1 << 0) /* RW */ 265 #define DELAY_EN (0x1 << 1) /* RW */ 266 #define PAD_DAT_RD_RXDLY2 (0x1f << 2) /* RW */ 267 #define PAD_DAT_RD_RXDLY (0x1f << 7) /* RW */ 268 #define PAD_DAT_RD_RXDLY2_SEL (0x1 << 12) /* RW */ 269 #define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */ 270 #define DATA_K_VALUE_SEL (0x1 << 14) /* RW */ 271 #define SDC_RX_ENH_EN (0x1 << 15) /* TW */ 272 273 /* EMMC_TOP_CMD mask */ 274 #define PAD_CMD_RXDLY2 (0x1f << 0) /* RW */ 275 #define PAD_CMD_RXDLY (0x1f << 5) /* RW */ 276 #define PAD_CMD_RD_RXDLY2_SEL (0x1 << 10) /* RW */ 277 #define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */ 278 #define PAD_CMD_TX_DLY (0x1f << 12) /* RW */ 279 280 #define REQ_CMD_EIO (0x1 << 0) 281 #define REQ_CMD_TMO (0x1 << 1) 282 #define REQ_DAT_ERR (0x1 << 2) 283 #define REQ_STOP_EIO (0x1 << 3) 284 #define REQ_STOP_TMO (0x1 << 4) 285 #define REQ_CMD_BUSY (0x1 << 5) 286 287 #define MSDC_PREPARE_FLAG (0x1 << 0) 288 #define MSDC_ASYNC_FLAG (0x1 << 1) 289 #define MSDC_MMAP_FLAG (0x1 << 2) 290 291 #define MTK_MMC_AUTOSUSPEND_DELAY 50 292 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 293 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 294 295 #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */ 296 297 #define PAD_DELAY_MAX 32 /* PAD delay cells */ 298 /*--------------------------------------------------------------------------*/ 299 /* Descriptor Structure */ 300 /*--------------------------------------------------------------------------*/ 301 struct mt_gpdma_desc { 302 u32 gpd_info; 303 #define GPDMA_DESC_HWO (0x1 << 0) 304 #define GPDMA_DESC_BDP (0x1 << 1) 305 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 306 #define GPDMA_DESC_INT (0x1 << 16) 307 #define GPDMA_DESC_NEXT_H4 (0xf << 24) 308 #define GPDMA_DESC_PTR_H4 (0xf << 28) 309 u32 next; 310 u32 ptr; 311 u32 gpd_data_len; 312 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 313 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ 314 u32 arg; 315 u32 blknum; 316 u32 cmd; 317 }; 318 319 struct mt_bdma_desc { 320 u32 bd_info; 321 #define BDMA_DESC_EOL (0x1 << 0) 322 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 323 #define BDMA_DESC_BLKPAD (0x1 << 17) 324 #define BDMA_DESC_DWPAD (0x1 << 18) 325 #define BDMA_DESC_NEXT_H4 (0xf << 24) 326 #define BDMA_DESC_PTR_H4 (0xf << 28) 327 u32 next; 328 u32 ptr; 329 u32 bd_data_len; 330 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 331 }; 332 333 struct msdc_dma { 334 struct scatterlist *sg; /* I/O scatter list */ 335 struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 336 struct mt_bdma_desc *bd; /* pointer to bd array */ 337 dma_addr_t gpd_addr; /* the physical address of gpd array */ 338 dma_addr_t bd_addr; /* the physical address of bd array */ 339 }; 340 341 struct msdc_save_para { 342 u32 msdc_cfg; 343 u32 iocon; 344 u32 sdc_cfg; 345 u32 pad_tune; 346 u32 patch_bit0; 347 u32 patch_bit1; 348 u32 patch_bit2; 349 u32 pad_ds_tune; 350 u32 pad_cmd_tune; 351 u32 emmc50_cfg0; 352 u32 emmc50_cfg3; 353 u32 sdc_fifo_cfg; 354 u32 emmc_top_control; 355 u32 emmc_top_cmd; 356 u32 emmc50_pad_ds_tune; 357 }; 358 359 struct mtk_mmc_compatible { 360 u8 clk_div_bits; 361 bool hs400_tune; /* only used for MT8173 */ 362 u32 pad_tune_reg; 363 bool async_fifo; 364 bool data_tune; 365 bool busy_check; 366 bool stop_clk_fix; 367 bool enhance_rx; 368 bool support_64g; 369 bool use_internal_cd; 370 }; 371 372 struct msdc_tune_para { 373 u32 iocon; 374 u32 pad_tune; 375 u32 pad_cmd_tune; 376 u32 emmc_top_control; 377 u32 emmc_top_cmd; 378 }; 379 380 struct msdc_delay_phase { 381 u8 maxlen; 382 u8 start; 383 u8 final_phase; 384 }; 385 386 struct msdc_host { 387 struct device *dev; 388 const struct mtk_mmc_compatible *dev_comp; 389 struct mmc_host *mmc; /* mmc structure */ 390 int cmd_rsp; 391 392 spinlock_t lock; 393 struct mmc_request *mrq; 394 struct mmc_command *cmd; 395 struct mmc_data *data; 396 int error; 397 398 void __iomem *base; /* host base address */ 399 void __iomem *top_base; /* host top register base address */ 400 401 struct msdc_dma dma; /* dma channel */ 402 u64 dma_mask; 403 404 u32 timeout_ns; /* data timeout ns */ 405 u32 timeout_clks; /* data timeout clks */ 406 407 struct pinctrl *pinctrl; 408 struct pinctrl_state *pins_default; 409 struct pinctrl_state *pins_uhs; 410 struct delayed_work req_timeout; 411 int irq; /* host interrupt */ 412 413 struct clk *src_clk; /* msdc source clock */ 414 struct clk *h_clk; /* msdc h_clk */ 415 struct clk *bus_clk; /* bus clock which used to access register */ 416 struct clk *src_clk_cg; /* msdc source clock control gate */ 417 u32 mclk; /* mmc subsystem clock frequency */ 418 u32 src_clk_freq; /* source clock frequency */ 419 unsigned char timing; 420 bool vqmmc_enabled; 421 u32 latch_ck; 422 u32 hs400_ds_delay; 423 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 424 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 425 bool hs400_cmd_resp_sel_rising; 426 /* cmd response sample selection for HS400 */ 427 bool hs400_mode; /* current eMMC will run at hs400 mode */ 428 bool internal_cd; /* Use internal card-detect logic */ 429 struct msdc_save_para save_para; /* used when gate HCLK */ 430 struct msdc_tune_para def_tune_para; /* default tune setting */ 431 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 432 }; 433 434 static const struct mtk_mmc_compatible mt8135_compat = { 435 .clk_div_bits = 8, 436 .hs400_tune = false, 437 .pad_tune_reg = MSDC_PAD_TUNE, 438 .async_fifo = false, 439 .data_tune = false, 440 .busy_check = false, 441 .stop_clk_fix = false, 442 .enhance_rx = false, 443 .support_64g = false, 444 }; 445 446 static const struct mtk_mmc_compatible mt8173_compat = { 447 .clk_div_bits = 8, 448 .hs400_tune = true, 449 .pad_tune_reg = MSDC_PAD_TUNE, 450 .async_fifo = false, 451 .data_tune = false, 452 .busy_check = false, 453 .stop_clk_fix = false, 454 .enhance_rx = false, 455 .support_64g = false, 456 }; 457 458 static const struct mtk_mmc_compatible mt8183_compat = { 459 .clk_div_bits = 12, 460 .hs400_tune = false, 461 .pad_tune_reg = MSDC_PAD_TUNE0, 462 .async_fifo = true, 463 .data_tune = true, 464 .busy_check = true, 465 .stop_clk_fix = true, 466 .enhance_rx = true, 467 .support_64g = true, 468 }; 469 470 static const struct mtk_mmc_compatible mt2701_compat = { 471 .clk_div_bits = 12, 472 .hs400_tune = false, 473 .pad_tune_reg = MSDC_PAD_TUNE0, 474 .async_fifo = true, 475 .data_tune = true, 476 .busy_check = false, 477 .stop_clk_fix = false, 478 .enhance_rx = false, 479 .support_64g = false, 480 }; 481 482 static const struct mtk_mmc_compatible mt2712_compat = { 483 .clk_div_bits = 12, 484 .hs400_tune = false, 485 .pad_tune_reg = MSDC_PAD_TUNE0, 486 .async_fifo = true, 487 .data_tune = true, 488 .busy_check = true, 489 .stop_clk_fix = true, 490 .enhance_rx = true, 491 .support_64g = true, 492 }; 493 494 static const struct mtk_mmc_compatible mt7622_compat = { 495 .clk_div_bits = 12, 496 .hs400_tune = false, 497 .pad_tune_reg = MSDC_PAD_TUNE0, 498 .async_fifo = true, 499 .data_tune = true, 500 .busy_check = true, 501 .stop_clk_fix = true, 502 .enhance_rx = true, 503 .support_64g = false, 504 }; 505 506 static const struct mtk_mmc_compatible mt8516_compat = { 507 .clk_div_bits = 12, 508 .hs400_tune = false, 509 .pad_tune_reg = MSDC_PAD_TUNE0, 510 .async_fifo = true, 511 .data_tune = true, 512 .busy_check = true, 513 .stop_clk_fix = true, 514 }; 515 516 static const struct mtk_mmc_compatible mt7620_compat = { 517 .clk_div_bits = 8, 518 .hs400_tune = false, 519 .pad_tune_reg = MSDC_PAD_TUNE, 520 .async_fifo = false, 521 .data_tune = false, 522 .busy_check = false, 523 .stop_clk_fix = false, 524 .enhance_rx = false, 525 .use_internal_cd = true, 526 }; 527 528 static const struct of_device_id msdc_of_ids[] = { 529 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, 530 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, 531 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, 532 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, 533 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, 534 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, 535 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, 536 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, 537 {} 538 }; 539 MODULE_DEVICE_TABLE(of, msdc_of_ids); 540 541 static void sdr_set_bits(void __iomem *reg, u32 bs) 542 { 543 u32 val = readl(reg); 544 545 val |= bs; 546 writel(val, reg); 547 } 548 549 static void sdr_clr_bits(void __iomem *reg, u32 bs) 550 { 551 u32 val = readl(reg); 552 553 val &= ~bs; 554 writel(val, reg); 555 } 556 557 static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 558 { 559 unsigned int tv = readl(reg); 560 561 tv &= ~field; 562 tv |= ((val) << (ffs((unsigned int)field) - 1)); 563 writel(tv, reg); 564 } 565 566 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 567 { 568 unsigned int tv = readl(reg); 569 570 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 571 } 572 573 static void msdc_reset_hw(struct msdc_host *host) 574 { 575 u32 val; 576 577 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 578 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) 579 cpu_relax(); 580 581 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 582 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) 583 cpu_relax(); 584 585 val = readl(host->base + MSDC_INT); 586 writel(val, host->base + MSDC_INT); 587 } 588 589 static void msdc_cmd_next(struct msdc_host *host, 590 struct mmc_request *mrq, struct mmc_command *cmd); 591 592 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 593 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 594 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 595 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 596 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 597 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 598 599 static u8 msdc_dma_calcs(u8 *buf, u32 len) 600 { 601 u32 i, sum = 0; 602 603 for (i = 0; i < len; i++) 604 sum += buf[i]; 605 return 0xff - (u8) sum; 606 } 607 608 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 609 struct mmc_data *data) 610 { 611 unsigned int j, dma_len; 612 dma_addr_t dma_address; 613 u32 dma_ctrl; 614 struct scatterlist *sg; 615 struct mt_gpdma_desc *gpd; 616 struct mt_bdma_desc *bd; 617 618 sg = data->sg; 619 620 gpd = dma->gpd; 621 bd = dma->bd; 622 623 /* modify gpd */ 624 gpd->gpd_info |= GPDMA_DESC_HWO; 625 gpd->gpd_info |= GPDMA_DESC_BDP; 626 /* need to clear first. use these bits to calc checksum */ 627 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 628 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 629 630 /* modify bd */ 631 for_each_sg(data->sg, sg, data->sg_count, j) { 632 dma_address = sg_dma_address(sg); 633 dma_len = sg_dma_len(sg); 634 635 /* init bd */ 636 bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 637 bd[j].bd_info &= ~BDMA_DESC_DWPAD; 638 bd[j].ptr = lower_32_bits(dma_address); 639 if (host->dev_comp->support_64g) { 640 bd[j].bd_info &= ~BDMA_DESC_PTR_H4; 641 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf) 642 << 28; 643 } 644 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 645 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 646 647 if (j == data->sg_count - 1) /* the last bd */ 648 bd[j].bd_info |= BDMA_DESC_EOL; 649 else 650 bd[j].bd_info &= ~BDMA_DESC_EOL; 651 652 /* checksume need to clear first */ 653 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 654 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 655 } 656 657 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 658 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 659 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 660 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); 661 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 662 if (host->dev_comp->support_64g) 663 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, 664 upper_32_bits(dma->gpd_addr) & 0xf); 665 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); 666 } 667 668 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq) 669 { 670 struct mmc_data *data = mrq->data; 671 672 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 673 data->host_cookie |= MSDC_PREPARE_FLAG; 674 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 675 mmc_get_dma_dir(data)); 676 } 677 } 678 679 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) 680 { 681 struct mmc_data *data = mrq->data; 682 683 if (data->host_cookie & MSDC_ASYNC_FLAG) 684 return; 685 686 if (data->host_cookie & MSDC_PREPARE_FLAG) { 687 dma_unmap_sg(host->dev, data->sg, data->sg_len, 688 mmc_get_dma_dir(data)); 689 data->host_cookie &= ~MSDC_PREPARE_FLAG; 690 } 691 } 692 693 /* clock control primitives */ 694 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) 695 { 696 u32 timeout, clk_ns; 697 u32 mode = 0; 698 699 host->timeout_ns = ns; 700 host->timeout_clks = clks; 701 if (host->mmc->actual_clock == 0) { 702 timeout = 0; 703 } else { 704 clk_ns = 1000000000UL / host->mmc->actual_clock; 705 timeout = (ns + clk_ns - 1) / clk_ns + clks; 706 /* in 1048576 sclk cycle unit */ 707 timeout = (timeout + (0x1 << 20) - 1) >> 20; 708 if (host->dev_comp->clk_div_bits == 8) 709 sdr_get_field(host->base + MSDC_CFG, 710 MSDC_CFG_CKMOD, &mode); 711 else 712 sdr_get_field(host->base + MSDC_CFG, 713 MSDC_CFG_CKMOD_EXTRA, &mode); 714 /*DDR mode will double the clk cycles for data timeout */ 715 timeout = mode >= 2 ? timeout * 2 : timeout; 716 timeout = timeout > 1 ? timeout - 1 : 0; 717 timeout = timeout > 255 ? 255 : timeout; 718 } 719 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout); 720 } 721 722 static void msdc_gate_clock(struct msdc_host *host) 723 { 724 clk_disable_unprepare(host->src_clk_cg); 725 clk_disable_unprepare(host->src_clk); 726 clk_disable_unprepare(host->bus_clk); 727 clk_disable_unprepare(host->h_clk); 728 } 729 730 static void msdc_ungate_clock(struct msdc_host *host) 731 { 732 clk_prepare_enable(host->h_clk); 733 clk_prepare_enable(host->bus_clk); 734 clk_prepare_enable(host->src_clk); 735 clk_prepare_enable(host->src_clk_cg); 736 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 737 cpu_relax(); 738 } 739 740 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 741 { 742 u32 mode; 743 u32 flags; 744 u32 div; 745 u32 sclk; 746 u32 tune_reg = host->dev_comp->pad_tune_reg; 747 748 if (!hz) { 749 dev_dbg(host->dev, "set mclk to 0\n"); 750 host->mclk = 0; 751 host->mmc->actual_clock = 0; 752 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 753 return; 754 } 755 756 flags = readl(host->base + MSDC_INTEN); 757 sdr_clr_bits(host->base + MSDC_INTEN, flags); 758 if (host->dev_comp->clk_div_bits == 8) 759 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 760 else 761 sdr_clr_bits(host->base + MSDC_CFG, 762 MSDC_CFG_HS400_CK_MODE_EXTRA); 763 if (timing == MMC_TIMING_UHS_DDR50 || 764 timing == MMC_TIMING_MMC_DDR52 || 765 timing == MMC_TIMING_MMC_HS400) { 766 if (timing == MMC_TIMING_MMC_HS400) 767 mode = 0x3; 768 else 769 mode = 0x2; /* ddr mode and use divisor */ 770 771 if (hz >= (host->src_clk_freq >> 2)) { 772 div = 0; /* mean div = 1/4 */ 773 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 774 } else { 775 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 776 sclk = (host->src_clk_freq >> 2) / div; 777 div = (div >> 1); 778 } 779 780 if (timing == MMC_TIMING_MMC_HS400 && 781 hz >= (host->src_clk_freq >> 1)) { 782 if (host->dev_comp->clk_div_bits == 8) 783 sdr_set_bits(host->base + MSDC_CFG, 784 MSDC_CFG_HS400_CK_MODE); 785 else 786 sdr_set_bits(host->base + MSDC_CFG, 787 MSDC_CFG_HS400_CK_MODE_EXTRA); 788 sclk = host->src_clk_freq >> 1; 789 div = 0; /* div is ignore when bit18 is set */ 790 } 791 } else if (hz >= host->src_clk_freq) { 792 mode = 0x1; /* no divisor */ 793 div = 0; 794 sclk = host->src_clk_freq; 795 } else { 796 mode = 0x0; /* use divisor */ 797 if (hz >= (host->src_clk_freq >> 1)) { 798 div = 0; /* mean div = 1/2 */ 799 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 800 } else { 801 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 802 sclk = (host->src_clk_freq >> 2) / div; 803 } 804 } 805 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 806 /* 807 * As src_clk/HCLK use the same bit to gate/ungate, 808 * So if want to only gate src_clk, need gate its parent(mux). 809 */ 810 if (host->src_clk_cg) 811 clk_disable_unprepare(host->src_clk_cg); 812 else 813 clk_disable_unprepare(clk_get_parent(host->src_clk)); 814 if (host->dev_comp->clk_div_bits == 8) 815 sdr_set_field(host->base + MSDC_CFG, 816 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 817 (mode << 8) | div); 818 else 819 sdr_set_field(host->base + MSDC_CFG, 820 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, 821 (mode << 12) | div); 822 if (host->src_clk_cg) 823 clk_prepare_enable(host->src_clk_cg); 824 else 825 clk_prepare_enable(clk_get_parent(host->src_clk)); 826 827 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 828 cpu_relax(); 829 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 830 host->mmc->actual_clock = sclk; 831 host->mclk = hz; 832 host->timing = timing; 833 /* need because clk changed. */ 834 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 835 sdr_set_bits(host->base + MSDC_INTEN, flags); 836 837 /* 838 * mmc_select_hs400() will drop to 50Mhz and High speed mode, 839 * tune result of hs200/200Mhz is not suitable for 50Mhz 840 */ 841 if (host->mmc->actual_clock <= 52000000) { 842 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 843 if (host->top_base) { 844 writel(host->def_tune_para.emmc_top_control, 845 host->top_base + EMMC_TOP_CONTROL); 846 writel(host->def_tune_para.emmc_top_cmd, 847 host->top_base + EMMC_TOP_CMD); 848 } else { 849 writel(host->def_tune_para.pad_tune, 850 host->base + tune_reg); 851 } 852 } else { 853 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 854 writel(host->saved_tune_para.pad_cmd_tune, 855 host->base + PAD_CMD_TUNE); 856 if (host->top_base) { 857 writel(host->saved_tune_para.emmc_top_control, 858 host->top_base + EMMC_TOP_CONTROL); 859 writel(host->saved_tune_para.emmc_top_cmd, 860 host->top_base + EMMC_TOP_CMD); 861 } else { 862 writel(host->saved_tune_para.pad_tune, 863 host->base + tune_reg); 864 } 865 } 866 867 if (timing == MMC_TIMING_MMC_HS400 && 868 host->dev_comp->hs400_tune) 869 sdr_set_field(host->base + tune_reg, 870 MSDC_PAD_TUNE_CMDRRDLY, 871 host->hs400_cmd_int_delay); 872 dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->mmc->actual_clock, 873 timing); 874 } 875 876 static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 877 struct mmc_request *mrq, struct mmc_command *cmd) 878 { 879 u32 resp; 880 881 switch (mmc_resp_type(cmd)) { 882 /* Actually, R1, R5, R6, R7 are the same */ 883 case MMC_RSP_R1: 884 resp = 0x1; 885 break; 886 case MMC_RSP_R1B: 887 resp = 0x7; 888 break; 889 case MMC_RSP_R2: 890 resp = 0x2; 891 break; 892 case MMC_RSP_R3: 893 resp = 0x3; 894 break; 895 case MMC_RSP_NONE: 896 default: 897 resp = 0x0; 898 break; 899 } 900 901 return resp; 902 } 903 904 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 905 struct mmc_request *mrq, struct mmc_command *cmd) 906 { 907 /* rawcmd : 908 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 909 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 910 */ 911 u32 opcode = cmd->opcode; 912 u32 resp = msdc_cmd_find_resp(host, mrq, cmd); 913 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 914 915 host->cmd_rsp = resp; 916 917 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 918 opcode == MMC_STOP_TRANSMISSION) 919 rawcmd |= (0x1 << 14); 920 else if (opcode == SD_SWITCH_VOLTAGE) 921 rawcmd |= (0x1 << 30); 922 else if (opcode == SD_APP_SEND_SCR || 923 opcode == SD_APP_SEND_NUM_WR_BLKS || 924 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 925 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 926 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 927 rawcmd |= (0x1 << 11); 928 929 if (cmd->data) { 930 struct mmc_data *data = cmd->data; 931 932 if (mmc_op_multi(opcode)) { 933 if (mmc_card_mmc(host->mmc->card) && mrq->sbc && 934 !(mrq->sbc->arg & 0xFFFF0000)) 935 rawcmd |= 0x2 << 28; /* AutoCMD23 */ 936 } 937 938 rawcmd |= ((data->blksz & 0xFFF) << 16); 939 if (data->flags & MMC_DATA_WRITE) 940 rawcmd |= (0x1 << 13); 941 if (data->blocks > 1) 942 rawcmd |= (0x2 << 11); 943 else 944 rawcmd |= (0x1 << 11); 945 /* Always use dma mode */ 946 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 947 948 if (host->timeout_ns != data->timeout_ns || 949 host->timeout_clks != data->timeout_clks) 950 msdc_set_timeout(host, data->timeout_ns, 951 data->timeout_clks); 952 953 writel(data->blocks, host->base + SDC_BLK_NUM); 954 } 955 return rawcmd; 956 } 957 958 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, 959 struct mmc_command *cmd, struct mmc_data *data) 960 { 961 bool read; 962 963 WARN_ON(host->data); 964 host->data = data; 965 read = data->flags & MMC_DATA_READ; 966 967 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 968 msdc_dma_setup(host, &host->dma, data); 969 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 970 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 971 dev_dbg(host->dev, "DMA start\n"); 972 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 973 __func__, cmd->opcode, data->blocks, read); 974 } 975 976 static int msdc_auto_cmd_done(struct msdc_host *host, int events, 977 struct mmc_command *cmd) 978 { 979 u32 *rsp = cmd->resp; 980 981 rsp[0] = readl(host->base + SDC_ACMD_RESP); 982 983 if (events & MSDC_INT_ACMDRDY) { 984 cmd->error = 0; 985 } else { 986 msdc_reset_hw(host); 987 if (events & MSDC_INT_ACMDCRCERR) { 988 cmd->error = -EILSEQ; 989 host->error |= REQ_STOP_EIO; 990 } else if (events & MSDC_INT_ACMDTMO) { 991 cmd->error = -ETIMEDOUT; 992 host->error |= REQ_STOP_TMO; 993 } 994 dev_err(host->dev, 995 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 996 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 997 } 998 return cmd->error; 999 } 1000 1001 static void msdc_track_cmd_data(struct msdc_host *host, 1002 struct mmc_command *cmd, struct mmc_data *data) 1003 { 1004 if (host->error) 1005 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 1006 __func__, cmd->opcode, cmd->arg, host->error); 1007 } 1008 1009 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 1010 { 1011 unsigned long flags; 1012 bool ret; 1013 1014 ret = cancel_delayed_work(&host->req_timeout); 1015 if (!ret) { 1016 /* delay work already running */ 1017 return; 1018 } 1019 spin_lock_irqsave(&host->lock, flags); 1020 host->mrq = NULL; 1021 spin_unlock_irqrestore(&host->lock, flags); 1022 1023 msdc_track_cmd_data(host, mrq->cmd, mrq->data); 1024 if (mrq->data) 1025 msdc_unprepare_data(host, mrq); 1026 if (host->error) 1027 msdc_reset_hw(host); 1028 mmc_request_done(host->mmc, mrq); 1029 } 1030 1031 /* returns true if command is fully handled; returns false otherwise */ 1032 static bool msdc_cmd_done(struct msdc_host *host, int events, 1033 struct mmc_request *mrq, struct mmc_command *cmd) 1034 { 1035 bool done = false; 1036 bool sbc_error; 1037 unsigned long flags; 1038 u32 *rsp = cmd->resp; 1039 1040 if (mrq->sbc && cmd == mrq->cmd && 1041 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 1042 | MSDC_INT_ACMDTMO))) 1043 msdc_auto_cmd_done(host, events, mrq->sbc); 1044 1045 sbc_error = mrq->sbc && mrq->sbc->error; 1046 1047 if (!sbc_error && !(events & (MSDC_INT_CMDRDY 1048 | MSDC_INT_RSPCRCERR 1049 | MSDC_INT_CMDTMO))) 1050 return done; 1051 1052 spin_lock_irqsave(&host->lock, flags); 1053 done = !host->cmd; 1054 host->cmd = NULL; 1055 spin_unlock_irqrestore(&host->lock, flags); 1056 1057 if (done) 1058 return true; 1059 1060 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1061 1062 if (cmd->flags & MMC_RSP_PRESENT) { 1063 if (cmd->flags & MMC_RSP_136) { 1064 rsp[0] = readl(host->base + SDC_RESP3); 1065 rsp[1] = readl(host->base + SDC_RESP2); 1066 rsp[2] = readl(host->base + SDC_RESP1); 1067 rsp[3] = readl(host->base + SDC_RESP0); 1068 } else { 1069 rsp[0] = readl(host->base + SDC_RESP0); 1070 } 1071 } 1072 1073 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 1074 if (cmd->opcode != MMC_SEND_TUNING_BLOCK && 1075 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200) 1076 /* 1077 * should not clear fifo/interrupt as the tune data 1078 * may have alreay come. 1079 */ 1080 msdc_reset_hw(host); 1081 if (events & MSDC_INT_RSPCRCERR) { 1082 cmd->error = -EILSEQ; 1083 host->error |= REQ_CMD_EIO; 1084 } else if (events & MSDC_INT_CMDTMO) { 1085 cmd->error = -ETIMEDOUT; 1086 host->error |= REQ_CMD_TMO; 1087 } 1088 } 1089 if (cmd->error) 1090 dev_dbg(host->dev, 1091 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 1092 __func__, cmd->opcode, cmd->arg, rsp[0], 1093 cmd->error); 1094 1095 msdc_cmd_next(host, mrq, cmd); 1096 return true; 1097 } 1098 1099 /* It is the core layer's responsibility to ensure card status 1100 * is correct before issue a request. but host design do below 1101 * checks recommended. 1102 */ 1103 static inline bool msdc_cmd_is_ready(struct msdc_host *host, 1104 struct mmc_request *mrq, struct mmc_command *cmd) 1105 { 1106 /* The max busy time we can endure is 20ms */ 1107 unsigned long tmo = jiffies + msecs_to_jiffies(20); 1108 1109 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && 1110 time_before(jiffies, tmo)) 1111 cpu_relax(); 1112 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { 1113 dev_err(host->dev, "CMD bus busy detected\n"); 1114 host->error |= REQ_CMD_BUSY; 1115 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1116 return false; 1117 } 1118 1119 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 1120 tmo = jiffies + msecs_to_jiffies(20); 1121 /* R1B or with data, should check SDCBUSY */ 1122 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && 1123 time_before(jiffies, tmo)) 1124 cpu_relax(); 1125 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { 1126 dev_err(host->dev, "Controller busy detected\n"); 1127 host->error |= REQ_CMD_BUSY; 1128 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1129 return false; 1130 } 1131 } 1132 return true; 1133 } 1134 1135 static void msdc_start_command(struct msdc_host *host, 1136 struct mmc_request *mrq, struct mmc_command *cmd) 1137 { 1138 u32 rawcmd; 1139 unsigned long flags; 1140 1141 WARN_ON(host->cmd); 1142 host->cmd = cmd; 1143 1144 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1145 if (!msdc_cmd_is_ready(host, mrq, cmd)) 1146 return; 1147 1148 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 1149 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 1150 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 1151 msdc_reset_hw(host); 1152 } 1153 1154 cmd->error = 0; 1155 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 1156 1157 spin_lock_irqsave(&host->lock, flags); 1158 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1159 spin_unlock_irqrestore(&host->lock, flags); 1160 1161 writel(cmd->arg, host->base + SDC_ARG); 1162 writel(rawcmd, host->base + SDC_CMD); 1163 } 1164 1165 static void msdc_cmd_next(struct msdc_host *host, 1166 struct mmc_request *mrq, struct mmc_command *cmd) 1167 { 1168 if ((cmd->error && 1169 !(cmd->error == -EILSEQ && 1170 (cmd->opcode == MMC_SEND_TUNING_BLOCK || 1171 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) || 1172 (mrq->sbc && mrq->sbc->error)) 1173 msdc_request_done(host, mrq); 1174 else if (cmd == mrq->sbc) 1175 msdc_start_command(host, mrq, mrq->cmd); 1176 else if (!cmd->data) 1177 msdc_request_done(host, mrq); 1178 else 1179 msdc_start_data(host, mrq, cmd, cmd->data); 1180 } 1181 1182 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 1183 { 1184 struct msdc_host *host = mmc_priv(mmc); 1185 1186 host->error = 0; 1187 WARN_ON(host->mrq); 1188 host->mrq = mrq; 1189 1190 if (mrq->data) 1191 msdc_prepare_data(host, mrq); 1192 1193 /* if SBC is required, we have HW option and SW option. 1194 * if HW option is enabled, and SBC does not have "special" flags, 1195 * use HW option, otherwise use SW option 1196 */ 1197 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 1198 (mrq->sbc->arg & 0xFFFF0000))) 1199 msdc_start_command(host, mrq, mrq->sbc); 1200 else 1201 msdc_start_command(host, mrq, mrq->cmd); 1202 } 1203 1204 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 1205 { 1206 struct msdc_host *host = mmc_priv(mmc); 1207 struct mmc_data *data = mrq->data; 1208 1209 if (!data) 1210 return; 1211 1212 msdc_prepare_data(host, mrq); 1213 data->host_cookie |= MSDC_ASYNC_FLAG; 1214 } 1215 1216 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1217 int err) 1218 { 1219 struct msdc_host *host = mmc_priv(mmc); 1220 struct mmc_data *data; 1221 1222 data = mrq->data; 1223 if (!data) 1224 return; 1225 if (data->host_cookie) { 1226 data->host_cookie &= ~MSDC_ASYNC_FLAG; 1227 msdc_unprepare_data(host, mrq); 1228 } 1229 } 1230 1231 static void msdc_data_xfer_next(struct msdc_host *host, 1232 struct mmc_request *mrq, struct mmc_data *data) 1233 { 1234 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 1235 !mrq->sbc) 1236 msdc_start_command(host, mrq, mrq->stop); 1237 else 1238 msdc_request_done(host, mrq); 1239 } 1240 1241 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 1242 struct mmc_request *mrq, struct mmc_data *data) 1243 { 1244 struct mmc_command *stop = data->stop; 1245 unsigned long flags; 1246 bool done; 1247 unsigned int check_data = events & 1248 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 1249 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 1250 | MSDC_INT_DMA_PROTECT); 1251 1252 spin_lock_irqsave(&host->lock, flags); 1253 done = !host->data; 1254 if (check_data) 1255 host->data = NULL; 1256 spin_unlock_irqrestore(&host->lock, flags); 1257 1258 if (done) 1259 return true; 1260 1261 if (check_data || (stop && stop->error)) { 1262 dev_dbg(host->dev, "DMA status: 0x%8X\n", 1263 readl(host->base + MSDC_DMA_CFG)); 1264 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1265 1); 1266 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) 1267 cpu_relax(); 1268 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 1269 dev_dbg(host->dev, "DMA stop\n"); 1270 1271 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 1272 data->bytes_xfered = data->blocks * data->blksz; 1273 } else { 1274 dev_dbg(host->dev, "interrupt events: %x\n", events); 1275 msdc_reset_hw(host); 1276 host->error |= REQ_DAT_ERR; 1277 data->bytes_xfered = 0; 1278 1279 if (events & MSDC_INT_DATTMO) 1280 data->error = -ETIMEDOUT; 1281 else if (events & MSDC_INT_DATCRCERR) 1282 data->error = -EILSEQ; 1283 1284 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 1285 __func__, mrq->cmd->opcode, data->blocks); 1286 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 1287 (int)data->error, data->bytes_xfered); 1288 } 1289 1290 msdc_data_xfer_next(host, mrq, data); 1291 done = true; 1292 } 1293 return done; 1294 } 1295 1296 static void msdc_set_buswidth(struct msdc_host *host, u32 width) 1297 { 1298 u32 val = readl(host->base + SDC_CFG); 1299 1300 val &= ~SDC_CFG_BUSWIDTH; 1301 1302 switch (width) { 1303 default: 1304 case MMC_BUS_WIDTH_1: 1305 val |= (MSDC_BUS_1BITS << 16); 1306 break; 1307 case MMC_BUS_WIDTH_4: 1308 val |= (MSDC_BUS_4BITS << 16); 1309 break; 1310 case MMC_BUS_WIDTH_8: 1311 val |= (MSDC_BUS_8BITS << 16); 1312 break; 1313 } 1314 1315 writel(val, host->base + SDC_CFG); 1316 dev_dbg(host->dev, "Bus Width = %d", width); 1317 } 1318 1319 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 1320 { 1321 struct msdc_host *host = mmc_priv(mmc); 1322 int ret = 0; 1323 1324 if (!IS_ERR(mmc->supply.vqmmc)) { 1325 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1326 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 1327 dev_err(host->dev, "Unsupported signal voltage!\n"); 1328 return -EINVAL; 1329 } 1330 1331 ret = mmc_regulator_set_vqmmc(mmc, ios); 1332 if (ret) { 1333 dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1334 ret, ios->signal_voltage); 1335 } else { 1336 /* Apply different pinctrl settings for different signal voltage */ 1337 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 1338 pinctrl_select_state(host->pinctrl, host->pins_uhs); 1339 else 1340 pinctrl_select_state(host->pinctrl, host->pins_default); 1341 } 1342 } 1343 return ret; 1344 } 1345 1346 static int msdc_card_busy(struct mmc_host *mmc) 1347 { 1348 struct msdc_host *host = mmc_priv(mmc); 1349 u32 status = readl(host->base + MSDC_PS); 1350 1351 /* only check if data0 is low */ 1352 return !(status & BIT(16)); 1353 } 1354 1355 static void msdc_request_timeout(struct work_struct *work) 1356 { 1357 struct msdc_host *host = container_of(work, struct msdc_host, 1358 req_timeout.work); 1359 1360 /* simulate HW timeout status */ 1361 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 1362 if (host->mrq) { 1363 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 1364 host->mrq, host->mrq->cmd->opcode); 1365 if (host->cmd) { 1366 dev_err(host->dev, "%s: aborting cmd=%d\n", 1367 __func__, host->cmd->opcode); 1368 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 1369 host->cmd); 1370 } else if (host->data) { 1371 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 1372 __func__, host->mrq->cmd->opcode, 1373 host->data->blocks); 1374 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 1375 host->data); 1376 } 1377 } 1378 } 1379 1380 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb) 1381 { 1382 if (enb) { 1383 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1384 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1385 } else { 1386 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1387 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1388 } 1389 } 1390 1391 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) 1392 { 1393 unsigned long flags; 1394 struct msdc_host *host = mmc_priv(mmc); 1395 1396 spin_lock_irqsave(&host->lock, flags); 1397 __msdc_enable_sdio_irq(host, enb); 1398 spin_unlock_irqrestore(&host->lock, flags); 1399 1400 if (enb) 1401 pm_runtime_get_noresume(host->dev); 1402 else 1403 pm_runtime_put_noidle(host->dev); 1404 } 1405 1406 static irqreturn_t msdc_irq(int irq, void *dev_id) 1407 { 1408 struct msdc_host *host = (struct msdc_host *) dev_id; 1409 1410 while (true) { 1411 unsigned long flags; 1412 struct mmc_request *mrq; 1413 struct mmc_command *cmd; 1414 struct mmc_data *data; 1415 u32 events, event_mask; 1416 1417 spin_lock_irqsave(&host->lock, flags); 1418 events = readl(host->base + MSDC_INT); 1419 event_mask = readl(host->base + MSDC_INTEN); 1420 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1421 __msdc_enable_sdio_irq(host, 0); 1422 /* clear interrupts */ 1423 writel(events & event_mask, host->base + MSDC_INT); 1424 1425 mrq = host->mrq; 1426 cmd = host->cmd; 1427 data = host->data; 1428 spin_unlock_irqrestore(&host->lock, flags); 1429 1430 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1431 sdio_signal_irq(host->mmc); 1432 1433 if ((events & event_mask) & MSDC_INT_CDSC) { 1434 if (host->internal_cd) 1435 mmc_detect_change(host->mmc, msecs_to_jiffies(20)); 1436 events &= ~MSDC_INT_CDSC; 1437 } 1438 1439 if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) 1440 break; 1441 1442 if (!mrq) { 1443 dev_err(host->dev, 1444 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 1445 __func__, events, event_mask); 1446 WARN_ON(1); 1447 break; 1448 } 1449 1450 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 1451 1452 if (cmd) 1453 msdc_cmd_done(host, events, mrq, cmd); 1454 else if (data) 1455 msdc_data_xfer_done(host, events, mrq, data); 1456 } 1457 1458 return IRQ_HANDLED; 1459 } 1460 1461 static void msdc_init_hw(struct msdc_host *host) 1462 { 1463 u32 val; 1464 u32 tune_reg = host->dev_comp->pad_tune_reg; 1465 1466 /* Configure to MMC/SD mode, clock free running */ 1467 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 1468 1469 /* Reset */ 1470 msdc_reset_hw(host); 1471 1472 /* Disable and clear all interrupts */ 1473 writel(0, host->base + MSDC_INTEN); 1474 val = readl(host->base + MSDC_INT); 1475 writel(val, host->base + MSDC_INT); 1476 1477 /* Configure card detection */ 1478 if (host->internal_cd) { 1479 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, 1480 DEFAULT_DEBOUNCE); 1481 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1482 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1483 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1484 } else { 1485 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1486 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1487 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1488 } 1489 1490 if (host->top_base) { 1491 writel(0, host->top_base + EMMC_TOP_CONTROL); 1492 writel(0, host->top_base + EMMC_TOP_CMD); 1493 } else { 1494 writel(0, host->base + tune_reg); 1495 } 1496 writel(0, host->base + MSDC_IOCON); 1497 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 1498 writel(0x403c0046, host->base + MSDC_PATCH_BIT); 1499 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 1500 writel(0xffff4089, host->base + MSDC_PATCH_BIT1); 1501 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1502 1503 if (host->dev_comp->stop_clk_fix) { 1504 sdr_set_field(host->base + MSDC_PATCH_BIT1, 1505 MSDC_PATCH_BIT1_STOP_DLY, 3); 1506 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1507 SDC_FIFO_CFG_WRVALIDSEL); 1508 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1509 SDC_FIFO_CFG_RDVALIDSEL); 1510 } 1511 1512 if (host->dev_comp->busy_check) 1513 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7)); 1514 1515 if (host->dev_comp->async_fifo) { 1516 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1517 MSDC_PB2_RESPWAIT, 3); 1518 if (host->dev_comp->enhance_rx) { 1519 if (host->top_base) 1520 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1521 SDC_RX_ENH_EN); 1522 else 1523 sdr_set_bits(host->base + SDC_ADV_CFG0, 1524 SDC_RX_ENHANCE_EN); 1525 } else { 1526 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1527 MSDC_PB2_RESPSTSENSEL, 2); 1528 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1529 MSDC_PB2_CRCSTSENSEL, 2); 1530 } 1531 /* use async fifo, then no need tune internal delay */ 1532 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, 1533 MSDC_PATCH_BIT2_CFGRESP); 1534 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1535 MSDC_PATCH_BIT2_CFGCRCSTS); 1536 } 1537 1538 if (host->dev_comp->support_64g) 1539 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1540 MSDC_PB2_SUPPORT_64G); 1541 if (host->dev_comp->data_tune) { 1542 if (host->top_base) { 1543 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1544 PAD_DAT_RD_RXDLY_SEL); 1545 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, 1546 DATA_K_VALUE_SEL); 1547 sdr_set_bits(host->top_base + EMMC_TOP_CMD, 1548 PAD_CMD_RD_RXDLY_SEL); 1549 } else { 1550 sdr_set_bits(host->base + tune_reg, 1551 MSDC_PAD_TUNE_RD_SEL | 1552 MSDC_PAD_TUNE_CMD_SEL); 1553 } 1554 } else { 1555 /* choose clock tune */ 1556 if (host->top_base) 1557 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1558 PAD_RXDLY_SEL); 1559 else 1560 sdr_set_bits(host->base + tune_reg, 1561 MSDC_PAD_TUNE_RXDLYSEL); 1562 } 1563 1564 /* Configure to enable SDIO mode. 1565 * it's must otherwise sdio cmd5 failed 1566 */ 1567 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1568 1569 /* Config SDIO device detect interrupt function */ 1570 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1571 1572 /* Configure to default data timeout */ 1573 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 1574 1575 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 1576 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1577 if (host->top_base) { 1578 host->def_tune_para.emmc_top_control = 1579 readl(host->top_base + EMMC_TOP_CONTROL); 1580 host->def_tune_para.emmc_top_cmd = 1581 readl(host->top_base + EMMC_TOP_CMD); 1582 host->saved_tune_para.emmc_top_control = 1583 readl(host->top_base + EMMC_TOP_CONTROL); 1584 host->saved_tune_para.emmc_top_cmd = 1585 readl(host->top_base + EMMC_TOP_CMD); 1586 } else { 1587 host->def_tune_para.pad_tune = readl(host->base + tune_reg); 1588 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 1589 } 1590 dev_dbg(host->dev, "init hardware done!"); 1591 } 1592 1593 static void msdc_deinit_hw(struct msdc_host *host) 1594 { 1595 u32 val; 1596 1597 if (host->internal_cd) { 1598 /* Disabled card-detect */ 1599 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1600 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1601 } 1602 1603 /* Disable and clear all interrupts */ 1604 writel(0, host->base + MSDC_INTEN); 1605 1606 val = readl(host->base + MSDC_INT); 1607 writel(val, host->base + MSDC_INT); 1608 } 1609 1610 /* init gpd and bd list in msdc_drv_probe */ 1611 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 1612 { 1613 struct mt_gpdma_desc *gpd = dma->gpd; 1614 struct mt_bdma_desc *bd = dma->bd; 1615 dma_addr_t dma_addr; 1616 int i; 1617 1618 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 1619 1620 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); 1621 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 1622 /* gpd->next is must set for desc DMA 1623 * That's why must alloc 2 gpd structure. 1624 */ 1625 gpd->next = lower_32_bits(dma_addr); 1626 if (host->dev_comp->support_64g) 1627 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1628 1629 dma_addr = dma->bd_addr; 1630 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ 1631 if (host->dev_comp->support_64g) 1632 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; 1633 1634 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 1635 for (i = 0; i < (MAX_BD_NUM - 1); i++) { 1636 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); 1637 bd[i].next = lower_32_bits(dma_addr); 1638 if (host->dev_comp->support_64g) 1639 bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1640 } 1641 } 1642 1643 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1644 { 1645 struct msdc_host *host = mmc_priv(mmc); 1646 int ret; 1647 1648 msdc_set_buswidth(host, ios->bus_width); 1649 1650 /* Suspend/Resume will do power off/on */ 1651 switch (ios->power_mode) { 1652 case MMC_POWER_UP: 1653 if (!IS_ERR(mmc->supply.vmmc)) { 1654 msdc_init_hw(host); 1655 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1656 ios->vdd); 1657 if (ret) { 1658 dev_err(host->dev, "Failed to set vmmc power!\n"); 1659 return; 1660 } 1661 } 1662 break; 1663 case MMC_POWER_ON: 1664 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1665 ret = regulator_enable(mmc->supply.vqmmc); 1666 if (ret) 1667 dev_err(host->dev, "Failed to set vqmmc power!\n"); 1668 else 1669 host->vqmmc_enabled = true; 1670 } 1671 break; 1672 case MMC_POWER_OFF: 1673 if (!IS_ERR(mmc->supply.vmmc)) 1674 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1675 1676 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1677 regulator_disable(mmc->supply.vqmmc); 1678 host->vqmmc_enabled = false; 1679 } 1680 break; 1681 default: 1682 break; 1683 } 1684 1685 if (host->mclk != ios->clock || host->timing != ios->timing) 1686 msdc_set_mclk(host, ios->timing, ios->clock); 1687 } 1688 1689 static u32 test_delay_bit(u32 delay, u32 bit) 1690 { 1691 bit %= PAD_DELAY_MAX; 1692 return delay & (1 << bit); 1693 } 1694 1695 static int get_delay_len(u32 delay, u32 start_bit) 1696 { 1697 int i; 1698 1699 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 1700 if (test_delay_bit(delay, start_bit + i) == 0) 1701 return i; 1702 } 1703 return PAD_DELAY_MAX - start_bit; 1704 } 1705 1706 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 1707 { 1708 int start = 0, len = 0; 1709 int start_final = 0, len_final = 0; 1710 u8 final_phase = 0xff; 1711 struct msdc_delay_phase delay_phase = { 0, }; 1712 1713 if (delay == 0) { 1714 dev_err(host->dev, "phase error: [map:%x]\n", delay); 1715 delay_phase.final_phase = final_phase; 1716 return delay_phase; 1717 } 1718 1719 while (start < PAD_DELAY_MAX) { 1720 len = get_delay_len(delay, start); 1721 if (len_final < len) { 1722 start_final = start; 1723 len_final = len; 1724 } 1725 start += len ? len : 1; 1726 if (len >= 12 && start_final < 4) 1727 break; 1728 } 1729 1730 /* The rule is that to find the smallest delay cell */ 1731 if (start_final == 0) 1732 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 1733 else 1734 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 1735 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 1736 delay, len_final, final_phase); 1737 1738 delay_phase.maxlen = len_final; 1739 delay_phase.start = start_final; 1740 delay_phase.final_phase = final_phase; 1741 return delay_phase; 1742 } 1743 1744 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) 1745 { 1746 u32 tune_reg = host->dev_comp->pad_tune_reg; 1747 1748 if (host->top_base) 1749 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, 1750 value); 1751 else 1752 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1753 value); 1754 } 1755 1756 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) 1757 { 1758 u32 tune_reg = host->dev_comp->pad_tune_reg; 1759 1760 if (host->top_base) 1761 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, 1762 PAD_DAT_RD_RXDLY, value); 1763 else 1764 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, 1765 value); 1766 } 1767 1768 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 1769 { 1770 struct msdc_host *host = mmc_priv(mmc); 1771 u32 rise_delay = 0, fall_delay = 0; 1772 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1773 struct msdc_delay_phase internal_delay_phase; 1774 u8 final_delay, final_maxlen; 1775 u32 internal_delay = 0; 1776 u32 tune_reg = host->dev_comp->pad_tune_reg; 1777 int cmd_err; 1778 int i, j; 1779 1780 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 1781 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 1782 sdr_set_field(host->base + tune_reg, 1783 MSDC_PAD_TUNE_CMDRRDLY, 1784 host->hs200_cmd_int_delay); 1785 1786 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1787 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1788 msdc_set_cmd_delay(host, i); 1789 /* 1790 * Using the same parameters, it may sometimes pass the test, 1791 * but sometimes it may fail. To make sure the parameters are 1792 * more stable, we test each set of parameters 3 times. 1793 */ 1794 for (j = 0; j < 3; j++) { 1795 mmc_send_tuning(mmc, opcode, &cmd_err); 1796 if (!cmd_err) { 1797 rise_delay |= (1 << i); 1798 } else { 1799 rise_delay &= ~(1 << i); 1800 break; 1801 } 1802 } 1803 } 1804 final_rise_delay = get_best_delay(host, rise_delay); 1805 /* if rising edge has enough margin, then do not scan falling edge */ 1806 if (final_rise_delay.maxlen >= 12 || 1807 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1808 goto skip_fall; 1809 1810 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1811 for (i = 0; i < PAD_DELAY_MAX; i++) { 1812 msdc_set_cmd_delay(host, i); 1813 /* 1814 * Using the same parameters, it may sometimes pass the test, 1815 * but sometimes it may fail. To make sure the parameters are 1816 * more stable, we test each set of parameters 3 times. 1817 */ 1818 for (j = 0; j < 3; j++) { 1819 mmc_send_tuning(mmc, opcode, &cmd_err); 1820 if (!cmd_err) { 1821 fall_delay |= (1 << i); 1822 } else { 1823 fall_delay &= ~(1 << i); 1824 break; 1825 } 1826 } 1827 } 1828 final_fall_delay = get_best_delay(host, fall_delay); 1829 1830 skip_fall: 1831 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1832 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 1833 final_maxlen = final_fall_delay.maxlen; 1834 if (final_maxlen == final_rise_delay.maxlen) { 1835 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1836 final_delay = final_rise_delay.final_phase; 1837 } else { 1838 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1839 final_delay = final_fall_delay.final_phase; 1840 } 1841 msdc_set_cmd_delay(host, final_delay); 1842 1843 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) 1844 goto skip_internal; 1845 1846 for (i = 0; i < PAD_DELAY_MAX; i++) { 1847 sdr_set_field(host->base + tune_reg, 1848 MSDC_PAD_TUNE_CMDRRDLY, i); 1849 mmc_send_tuning(mmc, opcode, &cmd_err); 1850 if (!cmd_err) 1851 internal_delay |= (1 << i); 1852 } 1853 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 1854 internal_delay_phase = get_best_delay(host, internal_delay); 1855 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 1856 internal_delay_phase.final_phase); 1857 skip_internal: 1858 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 1859 return final_delay == 0xff ? -EIO : 0; 1860 } 1861 1862 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 1863 { 1864 struct msdc_host *host = mmc_priv(mmc); 1865 u32 cmd_delay = 0; 1866 struct msdc_delay_phase final_cmd_delay = { 0,}; 1867 u8 final_delay; 1868 int cmd_err; 1869 int i, j; 1870 1871 /* select EMMC50 PAD CMD tune */ 1872 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 1873 1874 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 1875 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 1876 sdr_set_field(host->base + MSDC_PAD_TUNE, 1877 MSDC_PAD_TUNE_CMDRRDLY, 1878 host->hs200_cmd_int_delay); 1879 1880 if (host->hs400_cmd_resp_sel_rising) 1881 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1882 else 1883 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1884 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1885 sdr_set_field(host->base + PAD_CMD_TUNE, 1886 PAD_CMD_TUNE_RX_DLY3, i); 1887 /* 1888 * Using the same parameters, it may sometimes pass the test, 1889 * but sometimes it may fail. To make sure the parameters are 1890 * more stable, we test each set of parameters 3 times. 1891 */ 1892 for (j = 0; j < 3; j++) { 1893 mmc_send_tuning(mmc, opcode, &cmd_err); 1894 if (!cmd_err) { 1895 cmd_delay |= (1 << i); 1896 } else { 1897 cmd_delay &= ~(1 << i); 1898 break; 1899 } 1900 } 1901 } 1902 final_cmd_delay = get_best_delay(host, cmd_delay); 1903 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 1904 final_cmd_delay.final_phase); 1905 final_delay = final_cmd_delay.final_phase; 1906 1907 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 1908 return final_delay == 0xff ? -EIO : 0; 1909 } 1910 1911 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 1912 { 1913 struct msdc_host *host = mmc_priv(mmc); 1914 u32 rise_delay = 0, fall_delay = 0; 1915 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1916 u8 final_delay, final_maxlen; 1917 int i, ret; 1918 1919 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 1920 host->latch_ck); 1921 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1922 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1923 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1924 msdc_set_data_delay(host, i); 1925 ret = mmc_send_tuning(mmc, opcode, NULL); 1926 if (!ret) 1927 rise_delay |= (1 << i); 1928 } 1929 final_rise_delay = get_best_delay(host, rise_delay); 1930 /* if rising edge has enough margin, then do not scan falling edge */ 1931 if (final_rise_delay.maxlen >= 12 || 1932 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1933 goto skip_fall; 1934 1935 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1936 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1937 for (i = 0; i < PAD_DELAY_MAX; i++) { 1938 msdc_set_data_delay(host, i); 1939 ret = mmc_send_tuning(mmc, opcode, NULL); 1940 if (!ret) 1941 fall_delay |= (1 << i); 1942 } 1943 final_fall_delay = get_best_delay(host, fall_delay); 1944 1945 skip_fall: 1946 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1947 if (final_maxlen == final_rise_delay.maxlen) { 1948 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1949 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1950 final_delay = final_rise_delay.final_phase; 1951 } else { 1952 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1953 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1954 final_delay = final_fall_delay.final_phase; 1955 } 1956 msdc_set_data_delay(host, final_delay); 1957 1958 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 1959 return final_delay == 0xff ? -EIO : 0; 1960 } 1961 1962 /* 1963 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune 1964 * together, which can save the tuning time. 1965 */ 1966 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode) 1967 { 1968 struct msdc_host *host = mmc_priv(mmc); 1969 u32 rise_delay = 0, fall_delay = 0; 1970 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1971 u8 final_delay, final_maxlen; 1972 int i, ret; 1973 1974 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 1975 host->latch_ck); 1976 1977 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1978 sdr_clr_bits(host->base + MSDC_IOCON, 1979 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 1980 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1981 msdc_set_cmd_delay(host, i); 1982 msdc_set_data_delay(host, i); 1983 ret = mmc_send_tuning(mmc, opcode, NULL); 1984 if (!ret) 1985 rise_delay |= (1 << i); 1986 } 1987 final_rise_delay = get_best_delay(host, rise_delay); 1988 /* if rising edge has enough margin, then do not scan falling edge */ 1989 if (final_rise_delay.maxlen >= 12 || 1990 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1991 goto skip_fall; 1992 1993 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1994 sdr_set_bits(host->base + MSDC_IOCON, 1995 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 1996 for (i = 0; i < PAD_DELAY_MAX; i++) { 1997 msdc_set_cmd_delay(host, i); 1998 msdc_set_data_delay(host, i); 1999 ret = mmc_send_tuning(mmc, opcode, NULL); 2000 if (!ret) 2001 fall_delay |= (1 << i); 2002 } 2003 final_fall_delay = get_best_delay(host, fall_delay); 2004 2005 skip_fall: 2006 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2007 if (final_maxlen == final_rise_delay.maxlen) { 2008 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2009 sdr_clr_bits(host->base + MSDC_IOCON, 2010 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2011 final_delay = final_rise_delay.final_phase; 2012 } else { 2013 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2014 sdr_set_bits(host->base + MSDC_IOCON, 2015 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2016 final_delay = final_fall_delay.final_phase; 2017 } 2018 2019 msdc_set_cmd_delay(host, final_delay); 2020 msdc_set_data_delay(host, final_delay); 2021 2022 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); 2023 return final_delay == 0xff ? -EIO : 0; 2024 } 2025 2026 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 2027 { 2028 struct msdc_host *host = mmc_priv(mmc); 2029 int ret; 2030 u32 tune_reg = host->dev_comp->pad_tune_reg; 2031 2032 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { 2033 ret = msdc_tune_together(mmc, opcode); 2034 if (host->hs400_mode) { 2035 sdr_clr_bits(host->base + MSDC_IOCON, 2036 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2037 msdc_set_data_delay(host, 0); 2038 } 2039 goto tune_done; 2040 } 2041 if (host->hs400_mode && 2042 host->dev_comp->hs400_tune) 2043 ret = hs400_tune_response(mmc, opcode); 2044 else 2045 ret = msdc_tune_response(mmc, opcode); 2046 if (ret == -EIO) { 2047 dev_err(host->dev, "Tune response fail!\n"); 2048 return ret; 2049 } 2050 if (host->hs400_mode == false) { 2051 ret = msdc_tune_data(mmc, opcode); 2052 if (ret == -EIO) 2053 dev_err(host->dev, "Tune data fail!\n"); 2054 } 2055 2056 tune_done: 2057 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 2058 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 2059 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2060 if (host->top_base) { 2061 host->saved_tune_para.emmc_top_control = readl(host->top_base + 2062 EMMC_TOP_CONTROL); 2063 host->saved_tune_para.emmc_top_cmd = readl(host->top_base + 2064 EMMC_TOP_CMD); 2065 } 2066 return ret; 2067 } 2068 2069 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 2070 { 2071 struct msdc_host *host = mmc_priv(mmc); 2072 host->hs400_mode = true; 2073 2074 if (host->top_base) 2075 writel(host->hs400_ds_delay, 2076 host->top_base + EMMC50_PAD_DS_TUNE); 2077 else 2078 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 2079 /* hs400 mode must set it to 0 */ 2080 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); 2081 /* to improve read performance, set outstanding to 2 */ 2082 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); 2083 2084 return 0; 2085 } 2086 2087 static void msdc_hw_reset(struct mmc_host *mmc) 2088 { 2089 struct msdc_host *host = mmc_priv(mmc); 2090 2091 sdr_set_bits(host->base + EMMC_IOCON, 1); 2092 udelay(10); /* 10us is enough */ 2093 sdr_clr_bits(host->base + EMMC_IOCON, 1); 2094 } 2095 2096 static void msdc_ack_sdio_irq(struct mmc_host *mmc) 2097 { 2098 unsigned long flags; 2099 struct msdc_host *host = mmc_priv(mmc); 2100 2101 spin_lock_irqsave(&host->lock, flags); 2102 __msdc_enable_sdio_irq(host, 1); 2103 spin_unlock_irqrestore(&host->lock, flags); 2104 } 2105 2106 static int msdc_get_cd(struct mmc_host *mmc) 2107 { 2108 struct msdc_host *host = mmc_priv(mmc); 2109 int val; 2110 2111 if (mmc->caps & MMC_CAP_NONREMOVABLE) 2112 return 1; 2113 2114 if (!host->internal_cd) 2115 return mmc_gpio_get_cd(mmc); 2116 2117 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; 2118 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) 2119 return !!val; 2120 else 2121 return !val; 2122 } 2123 2124 static const struct mmc_host_ops mt_msdc_ops = { 2125 .post_req = msdc_post_req, 2126 .pre_req = msdc_pre_req, 2127 .request = msdc_ops_request, 2128 .set_ios = msdc_ops_set_ios, 2129 .get_ro = mmc_gpio_get_ro, 2130 .get_cd = msdc_get_cd, 2131 .enable_sdio_irq = msdc_enable_sdio_irq, 2132 .ack_sdio_irq = msdc_ack_sdio_irq, 2133 .start_signal_voltage_switch = msdc_ops_switch_volt, 2134 .card_busy = msdc_card_busy, 2135 .execute_tuning = msdc_execute_tuning, 2136 .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 2137 .hw_reset = msdc_hw_reset, 2138 }; 2139 2140 static void msdc_of_property_parse(struct platform_device *pdev, 2141 struct msdc_host *host) 2142 { 2143 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", 2144 &host->latch_ck); 2145 2146 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 2147 &host->hs400_ds_delay); 2148 2149 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 2150 &host->hs200_cmd_int_delay); 2151 2152 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 2153 &host->hs400_cmd_int_delay); 2154 2155 if (of_property_read_bool(pdev->dev.of_node, 2156 "mediatek,hs400-cmd-resp-sel-rising")) 2157 host->hs400_cmd_resp_sel_rising = true; 2158 else 2159 host->hs400_cmd_resp_sel_rising = false; 2160 } 2161 2162 static int msdc_drv_probe(struct platform_device *pdev) 2163 { 2164 struct mmc_host *mmc; 2165 struct msdc_host *host; 2166 struct resource *res; 2167 int ret; 2168 2169 if (!pdev->dev.of_node) { 2170 dev_err(&pdev->dev, "No DT found\n"); 2171 return -EINVAL; 2172 } 2173 2174 /* Allocate MMC host for this device */ 2175 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 2176 if (!mmc) 2177 return -ENOMEM; 2178 2179 host = mmc_priv(mmc); 2180 ret = mmc_of_parse(mmc); 2181 if (ret) 2182 goto host_free; 2183 2184 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2185 host->base = devm_ioremap_resource(&pdev->dev, res); 2186 if (IS_ERR(host->base)) { 2187 ret = PTR_ERR(host->base); 2188 goto host_free; 2189 } 2190 2191 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2192 if (res) { 2193 host->top_base = devm_ioremap_resource(&pdev->dev, res); 2194 if (IS_ERR(host->top_base)) 2195 host->top_base = NULL; 2196 } 2197 2198 ret = mmc_regulator_get_supply(mmc); 2199 if (ret) 2200 goto host_free; 2201 2202 host->src_clk = devm_clk_get(&pdev->dev, "source"); 2203 if (IS_ERR(host->src_clk)) { 2204 ret = PTR_ERR(host->src_clk); 2205 goto host_free; 2206 } 2207 2208 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 2209 if (IS_ERR(host->h_clk)) { 2210 ret = PTR_ERR(host->h_clk); 2211 goto host_free; 2212 } 2213 2214 host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); 2215 if (IS_ERR(host->bus_clk)) 2216 host->bus_clk = NULL; 2217 /*source clock control gate is optional clock*/ 2218 host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg"); 2219 if (IS_ERR(host->src_clk_cg)) 2220 host->src_clk_cg = NULL; 2221 2222 host->irq = platform_get_irq(pdev, 0); 2223 if (host->irq < 0) { 2224 ret = -EINVAL; 2225 goto host_free; 2226 } 2227 2228 host->pinctrl = devm_pinctrl_get(&pdev->dev); 2229 if (IS_ERR(host->pinctrl)) { 2230 ret = PTR_ERR(host->pinctrl); 2231 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 2232 goto host_free; 2233 } 2234 2235 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 2236 if (IS_ERR(host->pins_default)) { 2237 ret = PTR_ERR(host->pins_default); 2238 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 2239 goto host_free; 2240 } 2241 2242 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 2243 if (IS_ERR(host->pins_uhs)) { 2244 ret = PTR_ERR(host->pins_uhs); 2245 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 2246 goto host_free; 2247 } 2248 2249 msdc_of_property_parse(pdev, host); 2250 2251 host->dev = &pdev->dev; 2252 host->dev_comp = of_device_get_match_data(&pdev->dev); 2253 host->mmc = mmc; 2254 host->src_clk_freq = clk_get_rate(host->src_clk); 2255 /* Set host parameters to mmc */ 2256 mmc->ops = &mt_msdc_ops; 2257 if (host->dev_comp->clk_div_bits == 8) 2258 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 2259 else 2260 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); 2261 2262 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && 2263 !mmc_can_gpio_cd(mmc) && 2264 host->dev_comp->use_internal_cd) { 2265 /* 2266 * Is removable but no GPIO declared, so 2267 * use internal functionality. 2268 */ 2269 host->internal_cd = true; 2270 } 2271 2272 if (mmc->caps & MMC_CAP_SDIO_IRQ) 2273 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2274 2275 mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; 2276 /* MMC core transfer sizes tunable parameters */ 2277 mmc->max_segs = MAX_BD_NUM; 2278 mmc->max_seg_size = BDMA_DESC_BUFLEN; 2279 mmc->max_blk_size = 2048; 2280 mmc->max_req_size = 512 * 1024; 2281 mmc->max_blk_count = mmc->max_req_size / 512; 2282 if (host->dev_comp->support_64g) 2283 host->dma_mask = DMA_BIT_MASK(36); 2284 else 2285 host->dma_mask = DMA_BIT_MASK(32); 2286 mmc_dev(mmc)->dma_mask = &host->dma_mask; 2287 2288 host->timeout_clks = 3 * 1048576; 2289 host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2290 2 * sizeof(struct mt_gpdma_desc), 2291 &host->dma.gpd_addr, GFP_KERNEL); 2292 host->dma.bd = dma_alloc_coherent(&pdev->dev, 2293 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2294 &host->dma.bd_addr, GFP_KERNEL); 2295 if (!host->dma.gpd || !host->dma.bd) { 2296 ret = -ENOMEM; 2297 goto release_mem; 2298 } 2299 msdc_init_gpd_bd(host, &host->dma); 2300 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 2301 spin_lock_init(&host->lock); 2302 2303 platform_set_drvdata(pdev, mmc); 2304 msdc_ungate_clock(host); 2305 msdc_init_hw(host); 2306 2307 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 2308 IRQF_TRIGGER_NONE, pdev->name, host); 2309 if (ret) 2310 goto release; 2311 2312 pm_runtime_set_active(host->dev); 2313 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 2314 pm_runtime_use_autosuspend(host->dev); 2315 pm_runtime_enable(host->dev); 2316 ret = mmc_add_host(mmc); 2317 2318 if (ret) 2319 goto end; 2320 2321 return 0; 2322 end: 2323 pm_runtime_disable(host->dev); 2324 release: 2325 platform_set_drvdata(pdev, NULL); 2326 msdc_deinit_hw(host); 2327 msdc_gate_clock(host); 2328 release_mem: 2329 if (host->dma.gpd) 2330 dma_free_coherent(&pdev->dev, 2331 2 * sizeof(struct mt_gpdma_desc), 2332 host->dma.gpd, host->dma.gpd_addr); 2333 if (host->dma.bd) 2334 dma_free_coherent(&pdev->dev, 2335 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2336 host->dma.bd, host->dma.bd_addr); 2337 host_free: 2338 mmc_free_host(mmc); 2339 2340 return ret; 2341 } 2342 2343 static int msdc_drv_remove(struct platform_device *pdev) 2344 { 2345 struct mmc_host *mmc; 2346 struct msdc_host *host; 2347 2348 mmc = platform_get_drvdata(pdev); 2349 host = mmc_priv(mmc); 2350 2351 pm_runtime_get_sync(host->dev); 2352 2353 platform_set_drvdata(pdev, NULL); 2354 mmc_remove_host(host->mmc); 2355 msdc_deinit_hw(host); 2356 msdc_gate_clock(host); 2357 2358 pm_runtime_disable(host->dev); 2359 pm_runtime_put_noidle(host->dev); 2360 dma_free_coherent(&pdev->dev, 2361 2 * sizeof(struct mt_gpdma_desc), 2362 host->dma.gpd, host->dma.gpd_addr); 2363 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2364 host->dma.bd, host->dma.bd_addr); 2365 2366 mmc_free_host(host->mmc); 2367 2368 return 0; 2369 } 2370 2371 #ifdef CONFIG_PM 2372 static void msdc_save_reg(struct msdc_host *host) 2373 { 2374 u32 tune_reg = host->dev_comp->pad_tune_reg; 2375 2376 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 2377 host->save_para.iocon = readl(host->base + MSDC_IOCON); 2378 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 2379 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 2380 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 2381 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); 2382 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 2383 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2384 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 2385 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); 2386 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); 2387 if (host->top_base) { 2388 host->save_para.emmc_top_control = 2389 readl(host->top_base + EMMC_TOP_CONTROL); 2390 host->save_para.emmc_top_cmd = 2391 readl(host->top_base + EMMC_TOP_CMD); 2392 host->save_para.emmc50_pad_ds_tune = 2393 readl(host->top_base + EMMC50_PAD_DS_TUNE); 2394 } else { 2395 host->save_para.pad_tune = readl(host->base + tune_reg); 2396 } 2397 } 2398 2399 static void msdc_restore_reg(struct msdc_host *host) 2400 { 2401 u32 tune_reg = host->dev_comp->pad_tune_reg; 2402 2403 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 2404 writel(host->save_para.iocon, host->base + MSDC_IOCON); 2405 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 2406 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 2407 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 2408 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); 2409 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 2410 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 2411 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 2412 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); 2413 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); 2414 if (host->top_base) { 2415 writel(host->save_para.emmc_top_control, 2416 host->top_base + EMMC_TOP_CONTROL); 2417 writel(host->save_para.emmc_top_cmd, 2418 host->top_base + EMMC_TOP_CMD); 2419 writel(host->save_para.emmc50_pad_ds_tune, 2420 host->top_base + EMMC50_PAD_DS_TUNE); 2421 } else { 2422 writel(host->save_para.pad_tune, host->base + tune_reg); 2423 } 2424 } 2425 2426 static int msdc_runtime_suspend(struct device *dev) 2427 { 2428 struct mmc_host *mmc = dev_get_drvdata(dev); 2429 struct msdc_host *host = mmc_priv(mmc); 2430 2431 msdc_save_reg(host); 2432 msdc_gate_clock(host); 2433 return 0; 2434 } 2435 2436 static int msdc_runtime_resume(struct device *dev) 2437 { 2438 struct mmc_host *mmc = dev_get_drvdata(dev); 2439 struct msdc_host *host = mmc_priv(mmc); 2440 2441 msdc_ungate_clock(host); 2442 msdc_restore_reg(host); 2443 return 0; 2444 } 2445 #endif 2446 2447 static const struct dev_pm_ops msdc_dev_pm_ops = { 2448 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2449 pm_runtime_force_resume) 2450 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 2451 }; 2452 2453 static struct platform_driver mt_msdc_driver = { 2454 .probe = msdc_drv_probe, 2455 .remove = msdc_drv_remove, 2456 .driver = { 2457 .name = "mtk-msdc", 2458 .of_match_table = msdc_of_ids, 2459 .pm = &msdc_dev_pm_ops, 2460 }, 2461 }; 2462 2463 module_platform_driver(mt_msdc_driver); 2464 MODULE_LICENSE("GPL v2"); 2465 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 2466