1 /* 2 * Copyright (c) 2014-2015 MediaTek Inc. 3 * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/ioport.h> 20 #include <linux/irq.h> 21 #include <linux/of_address.h> 22 #include <linux/of_device.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_gpio.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/regulator/consumer.h> 30 #include <linux/slab.h> 31 #include <linux/spinlock.h> 32 #include <linux/interrupt.h> 33 34 #include <linux/mmc/card.h> 35 #include <linux/mmc/core.h> 36 #include <linux/mmc/host.h> 37 #include <linux/mmc/mmc.h> 38 #include <linux/mmc/sd.h> 39 #include <linux/mmc/sdio.h> 40 #include <linux/mmc/slot-gpio.h> 41 42 #define MAX_BD_NUM 1024 43 44 /*--------------------------------------------------------------------------*/ 45 /* Common Definition */ 46 /*--------------------------------------------------------------------------*/ 47 #define MSDC_BUS_1BITS 0x0 48 #define MSDC_BUS_4BITS 0x1 49 #define MSDC_BUS_8BITS 0x2 50 51 #define MSDC_BURST_64B 0x6 52 53 /*--------------------------------------------------------------------------*/ 54 /* Register Offset */ 55 /*--------------------------------------------------------------------------*/ 56 #define MSDC_CFG 0x0 57 #define MSDC_IOCON 0x04 58 #define MSDC_PS 0x08 59 #define MSDC_INT 0x0c 60 #define MSDC_INTEN 0x10 61 #define MSDC_FIFOCS 0x14 62 #define SDC_CFG 0x30 63 #define SDC_CMD 0x34 64 #define SDC_ARG 0x38 65 #define SDC_STS 0x3c 66 #define SDC_RESP0 0x40 67 #define SDC_RESP1 0x44 68 #define SDC_RESP2 0x48 69 #define SDC_RESP3 0x4c 70 #define SDC_BLK_NUM 0x50 71 #define SDC_ADV_CFG0 0x64 72 #define EMMC_IOCON 0x7c 73 #define SDC_ACMD_RESP 0x80 74 #define DMA_SA_H4BIT 0x8c 75 #define MSDC_DMA_SA 0x90 76 #define MSDC_DMA_CTRL 0x98 77 #define MSDC_DMA_CFG 0x9c 78 #define MSDC_PATCH_BIT 0xb0 79 #define MSDC_PATCH_BIT1 0xb4 80 #define MSDC_PATCH_BIT2 0xb8 81 #define MSDC_PAD_TUNE 0xec 82 #define MSDC_PAD_TUNE0 0xf0 83 #define PAD_DS_TUNE 0x188 84 #define PAD_CMD_TUNE 0x18c 85 #define EMMC50_CFG0 0x208 86 #define EMMC50_CFG3 0x220 87 #define SDC_FIFO_CFG 0x228 88 89 /*--------------------------------------------------------------------------*/ 90 /* Top Pad Register Offset */ 91 /*--------------------------------------------------------------------------*/ 92 #define EMMC_TOP_CONTROL 0x00 93 #define EMMC_TOP_CMD 0x04 94 #define EMMC50_PAD_DS_TUNE 0x0c 95 96 /*--------------------------------------------------------------------------*/ 97 /* Register Mask */ 98 /*--------------------------------------------------------------------------*/ 99 100 /* MSDC_CFG mask */ 101 #define MSDC_CFG_MODE (0x1 << 0) /* RW */ 102 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ 103 #define MSDC_CFG_RST (0x1 << 2) /* RW */ 104 #define MSDC_CFG_PIO (0x1 << 3) /* RW */ 105 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ 106 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ 107 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ 108 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ 109 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ 110 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ 111 #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */ 112 #define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */ 113 #define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */ 114 #define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */ 115 116 /* MSDC_IOCON mask */ 117 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ 118 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ 119 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ 120 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ 121 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ 122 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ 123 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ 124 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ 125 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ 126 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ 127 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ 128 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ 129 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ 130 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ 131 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ 132 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ 133 134 /* MSDC_PS mask */ 135 #define MSDC_PS_CDEN (0x1 << 0) /* RW */ 136 #define MSDC_PS_CDSTS (0x1 << 1) /* R */ 137 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ 138 #define MSDC_PS_DAT (0xff << 16) /* R */ 139 #define MSDC_PS_CMD (0x1 << 24) /* R */ 140 #define MSDC_PS_WP (0x1 << 31) /* R */ 141 142 /* MSDC_INT mask */ 143 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ 144 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ 145 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ 146 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ 147 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ 148 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ 149 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ 150 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ 151 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ 152 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ 153 #define MSDC_INT_CSTA (0x1 << 11) /* R */ 154 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ 155 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ 156 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ 157 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ 158 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ 159 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ 160 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ 161 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ 162 163 /* MSDC_INTEN mask */ 164 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ 165 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ 166 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ 167 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ 168 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ 169 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ 170 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ 171 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ 172 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ 173 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ 174 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ 175 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ 176 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ 177 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ 178 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ 179 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ 180 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ 181 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ 182 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ 183 184 /* MSDC_FIFOCS mask */ 185 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 186 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 187 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ 188 189 /* SDC_CFG mask */ 190 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ 191 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ 192 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 193 #define SDC_CFG_SDIO (0x1 << 19) /* RW */ 194 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 195 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ 196 #define SDC_CFG_DTOC (0xff << 24) /* RW */ 197 198 /* SDC_STS mask */ 199 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ 200 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 201 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ 202 203 /* SDC_ADV_CFG0 mask */ 204 #define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */ 205 206 /* DMA_SA_H4BIT mask */ 207 #define DMA_ADDR_HIGH_4BIT (0xf << 0) /* RW */ 208 209 /* MSDC_DMA_CTRL mask */ 210 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ 211 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ 212 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ 213 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ 214 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ 215 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ 216 217 /* MSDC_DMA_CFG mask */ 218 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ 219 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ 220 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ 221 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ 222 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ 223 224 /* MSDC_PATCH_BIT mask */ 225 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ 226 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) 227 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) 228 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ 229 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ 230 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ 231 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ 232 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ 233 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ 234 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ 235 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ 236 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ 237 238 #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ 239 240 #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ 241 #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */ 242 #define MSDC_PB2_SUPPORT_64G (0x1 << 1) /* RW */ 243 #define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */ 244 #define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */ 245 #define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */ 246 247 #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */ 248 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */ 249 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */ 250 #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */ 251 #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */ 252 #define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */ 253 #define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */ 254 #define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */ 255 256 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */ 257 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */ 258 #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */ 259 260 #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */ 261 262 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */ 263 #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ 264 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ 265 266 #define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */ 267 268 #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */ 269 #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */ 270 271 /* EMMC_TOP_CONTROL mask */ 272 #define PAD_RXDLY_SEL (0x1 << 0) /* RW */ 273 #define DELAY_EN (0x1 << 1) /* RW */ 274 #define PAD_DAT_RD_RXDLY2 (0x1f << 2) /* RW */ 275 #define PAD_DAT_RD_RXDLY (0x1f << 7) /* RW */ 276 #define PAD_DAT_RD_RXDLY2_SEL (0x1 << 12) /* RW */ 277 #define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */ 278 #define DATA_K_VALUE_SEL (0x1 << 14) /* RW */ 279 #define SDC_RX_ENH_EN (0x1 << 15) /* TW */ 280 281 /* EMMC_TOP_CMD mask */ 282 #define PAD_CMD_RXDLY2 (0x1f << 0) /* RW */ 283 #define PAD_CMD_RXDLY (0x1f << 5) /* RW */ 284 #define PAD_CMD_RD_RXDLY2_SEL (0x1 << 10) /* RW */ 285 #define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */ 286 #define PAD_CMD_TX_DLY (0x1f << 12) /* RW */ 287 288 #define REQ_CMD_EIO (0x1 << 0) 289 #define REQ_CMD_TMO (0x1 << 1) 290 #define REQ_DAT_ERR (0x1 << 2) 291 #define REQ_STOP_EIO (0x1 << 3) 292 #define REQ_STOP_TMO (0x1 << 4) 293 #define REQ_CMD_BUSY (0x1 << 5) 294 295 #define MSDC_PREPARE_FLAG (0x1 << 0) 296 #define MSDC_ASYNC_FLAG (0x1 << 1) 297 #define MSDC_MMAP_FLAG (0x1 << 2) 298 299 #define MTK_MMC_AUTOSUSPEND_DELAY 50 300 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 301 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 302 303 #define PAD_DELAY_MAX 32 /* PAD delay cells */ 304 /*--------------------------------------------------------------------------*/ 305 /* Descriptor Structure */ 306 /*--------------------------------------------------------------------------*/ 307 struct mt_gpdma_desc { 308 u32 gpd_info; 309 #define GPDMA_DESC_HWO (0x1 << 0) 310 #define GPDMA_DESC_BDP (0x1 << 1) 311 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 312 #define GPDMA_DESC_INT (0x1 << 16) 313 #define GPDMA_DESC_NEXT_H4 (0xf << 24) 314 #define GPDMA_DESC_PTR_H4 (0xf << 28) 315 u32 next; 316 u32 ptr; 317 u32 gpd_data_len; 318 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 319 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ 320 u32 arg; 321 u32 blknum; 322 u32 cmd; 323 }; 324 325 struct mt_bdma_desc { 326 u32 bd_info; 327 #define BDMA_DESC_EOL (0x1 << 0) 328 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 329 #define BDMA_DESC_BLKPAD (0x1 << 17) 330 #define BDMA_DESC_DWPAD (0x1 << 18) 331 #define BDMA_DESC_NEXT_H4 (0xf << 24) 332 #define BDMA_DESC_PTR_H4 (0xf << 28) 333 u32 next; 334 u32 ptr; 335 u32 bd_data_len; 336 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 337 }; 338 339 struct msdc_dma { 340 struct scatterlist *sg; /* I/O scatter list */ 341 struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 342 struct mt_bdma_desc *bd; /* pointer to bd array */ 343 dma_addr_t gpd_addr; /* the physical address of gpd array */ 344 dma_addr_t bd_addr; /* the physical address of bd array */ 345 }; 346 347 struct msdc_save_para { 348 u32 msdc_cfg; 349 u32 iocon; 350 u32 sdc_cfg; 351 u32 pad_tune; 352 u32 patch_bit0; 353 u32 patch_bit1; 354 u32 patch_bit2; 355 u32 pad_ds_tune; 356 u32 pad_cmd_tune; 357 u32 emmc50_cfg0; 358 u32 emmc50_cfg3; 359 u32 sdc_fifo_cfg; 360 u32 emmc_top_control; 361 u32 emmc_top_cmd; 362 u32 emmc50_pad_ds_tune; 363 }; 364 365 struct mtk_mmc_compatible { 366 u8 clk_div_bits; 367 bool hs400_tune; /* only used for MT8173 */ 368 u32 pad_tune_reg; 369 bool async_fifo; 370 bool data_tune; 371 bool busy_check; 372 bool stop_clk_fix; 373 bool enhance_rx; 374 bool support_64g; 375 }; 376 377 struct msdc_tune_para { 378 u32 iocon; 379 u32 pad_tune; 380 u32 pad_cmd_tune; 381 u32 emmc_top_control; 382 u32 emmc_top_cmd; 383 }; 384 385 struct msdc_delay_phase { 386 u8 maxlen; 387 u8 start; 388 u8 final_phase; 389 }; 390 391 struct msdc_host { 392 struct device *dev; 393 const struct mtk_mmc_compatible *dev_comp; 394 struct mmc_host *mmc; /* mmc structure */ 395 int cmd_rsp; 396 397 spinlock_t lock; 398 struct mmc_request *mrq; 399 struct mmc_command *cmd; 400 struct mmc_data *data; 401 int error; 402 403 void __iomem *base; /* host base address */ 404 void __iomem *top_base; /* host top register base address */ 405 406 struct msdc_dma dma; /* dma channel */ 407 u64 dma_mask; 408 409 u32 timeout_ns; /* data timeout ns */ 410 u32 timeout_clks; /* data timeout clks */ 411 412 struct pinctrl *pinctrl; 413 struct pinctrl_state *pins_default; 414 struct pinctrl_state *pins_uhs; 415 struct delayed_work req_timeout; 416 int irq; /* host interrupt */ 417 418 struct clk *src_clk; /* msdc source clock */ 419 struct clk *h_clk; /* msdc h_clk */ 420 struct clk *bus_clk; /* bus clock which used to access register */ 421 struct clk *src_clk_cg; /* msdc source clock control gate */ 422 u32 mclk; /* mmc subsystem clock frequency */ 423 u32 src_clk_freq; /* source clock frequency */ 424 unsigned char timing; 425 bool vqmmc_enabled; 426 u32 latch_ck; 427 u32 hs400_ds_delay; 428 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 429 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 430 bool hs400_cmd_resp_sel_rising; 431 /* cmd response sample selection for HS400 */ 432 bool hs400_mode; /* current eMMC will run at hs400 mode */ 433 struct msdc_save_para save_para; /* used when gate HCLK */ 434 struct msdc_tune_para def_tune_para; /* default tune setting */ 435 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 436 }; 437 438 static const struct mtk_mmc_compatible mt8135_compat = { 439 .clk_div_bits = 8, 440 .hs400_tune = false, 441 .pad_tune_reg = MSDC_PAD_TUNE, 442 .async_fifo = false, 443 .data_tune = false, 444 .busy_check = false, 445 .stop_clk_fix = false, 446 .enhance_rx = false, 447 .support_64g = false, 448 }; 449 450 static const struct mtk_mmc_compatible mt8173_compat = { 451 .clk_div_bits = 8, 452 .hs400_tune = true, 453 .pad_tune_reg = MSDC_PAD_TUNE, 454 .async_fifo = false, 455 .data_tune = false, 456 .busy_check = false, 457 .stop_clk_fix = false, 458 .enhance_rx = false, 459 .support_64g = false, 460 }; 461 462 static const struct mtk_mmc_compatible mt8183_compat = { 463 .clk_div_bits = 12, 464 .hs400_tune = false, 465 .pad_tune_reg = MSDC_PAD_TUNE0, 466 .async_fifo = true, 467 .data_tune = true, 468 .busy_check = true, 469 .stop_clk_fix = true, 470 .enhance_rx = true, 471 .support_64g = true, 472 }; 473 474 static const struct mtk_mmc_compatible mt2701_compat = { 475 .clk_div_bits = 12, 476 .hs400_tune = false, 477 .pad_tune_reg = MSDC_PAD_TUNE0, 478 .async_fifo = true, 479 .data_tune = true, 480 .busy_check = false, 481 .stop_clk_fix = false, 482 .enhance_rx = false, 483 .support_64g = false, 484 }; 485 486 static const struct mtk_mmc_compatible mt2712_compat = { 487 .clk_div_bits = 12, 488 .hs400_tune = false, 489 .pad_tune_reg = MSDC_PAD_TUNE0, 490 .async_fifo = true, 491 .data_tune = true, 492 .busy_check = true, 493 .stop_clk_fix = true, 494 .enhance_rx = true, 495 .support_64g = true, 496 }; 497 498 static const struct mtk_mmc_compatible mt7622_compat = { 499 .clk_div_bits = 12, 500 .hs400_tune = false, 501 .pad_tune_reg = MSDC_PAD_TUNE0, 502 .async_fifo = true, 503 .data_tune = true, 504 .busy_check = true, 505 .stop_clk_fix = true, 506 .enhance_rx = true, 507 .support_64g = false, 508 }; 509 510 static const struct of_device_id msdc_of_ids[] = { 511 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, 512 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, 513 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, 514 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, 515 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, 516 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, 517 {} 518 }; 519 MODULE_DEVICE_TABLE(of, msdc_of_ids); 520 521 static void sdr_set_bits(void __iomem *reg, u32 bs) 522 { 523 u32 val = readl(reg); 524 525 val |= bs; 526 writel(val, reg); 527 } 528 529 static void sdr_clr_bits(void __iomem *reg, u32 bs) 530 { 531 u32 val = readl(reg); 532 533 val &= ~bs; 534 writel(val, reg); 535 } 536 537 static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 538 { 539 unsigned int tv = readl(reg); 540 541 tv &= ~field; 542 tv |= ((val) << (ffs((unsigned int)field) - 1)); 543 writel(tv, reg); 544 } 545 546 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 547 { 548 unsigned int tv = readl(reg); 549 550 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 551 } 552 553 static void msdc_reset_hw(struct msdc_host *host) 554 { 555 u32 val; 556 557 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 558 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) 559 cpu_relax(); 560 561 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 562 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) 563 cpu_relax(); 564 565 val = readl(host->base + MSDC_INT); 566 writel(val, host->base + MSDC_INT); 567 } 568 569 static void msdc_cmd_next(struct msdc_host *host, 570 struct mmc_request *mrq, struct mmc_command *cmd); 571 572 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 573 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 574 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 575 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 576 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 577 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 578 579 static u8 msdc_dma_calcs(u8 *buf, u32 len) 580 { 581 u32 i, sum = 0; 582 583 for (i = 0; i < len; i++) 584 sum += buf[i]; 585 return 0xff - (u8) sum; 586 } 587 588 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 589 struct mmc_data *data) 590 { 591 unsigned int j, dma_len; 592 dma_addr_t dma_address; 593 u32 dma_ctrl; 594 struct scatterlist *sg; 595 struct mt_gpdma_desc *gpd; 596 struct mt_bdma_desc *bd; 597 598 sg = data->sg; 599 600 gpd = dma->gpd; 601 bd = dma->bd; 602 603 /* modify gpd */ 604 gpd->gpd_info |= GPDMA_DESC_HWO; 605 gpd->gpd_info |= GPDMA_DESC_BDP; 606 /* need to clear first. use these bits to calc checksum */ 607 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 608 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 609 610 /* modify bd */ 611 for_each_sg(data->sg, sg, data->sg_count, j) { 612 dma_address = sg_dma_address(sg); 613 dma_len = sg_dma_len(sg); 614 615 /* init bd */ 616 bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 617 bd[j].bd_info &= ~BDMA_DESC_DWPAD; 618 bd[j].ptr = lower_32_bits(dma_address); 619 if (host->dev_comp->support_64g) { 620 bd[j].bd_info &= ~BDMA_DESC_PTR_H4; 621 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf) 622 << 28; 623 } 624 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 625 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 626 627 if (j == data->sg_count - 1) /* the last bd */ 628 bd[j].bd_info |= BDMA_DESC_EOL; 629 else 630 bd[j].bd_info &= ~BDMA_DESC_EOL; 631 632 /* checksume need to clear first */ 633 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 634 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 635 } 636 637 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 638 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 639 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 640 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); 641 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 642 if (host->dev_comp->support_64g) 643 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, 644 upper_32_bits(dma->gpd_addr) & 0xf); 645 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); 646 } 647 648 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq) 649 { 650 struct mmc_data *data = mrq->data; 651 652 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 653 data->host_cookie |= MSDC_PREPARE_FLAG; 654 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 655 mmc_get_dma_dir(data)); 656 } 657 } 658 659 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) 660 { 661 struct mmc_data *data = mrq->data; 662 663 if (data->host_cookie & MSDC_ASYNC_FLAG) 664 return; 665 666 if (data->host_cookie & MSDC_PREPARE_FLAG) { 667 dma_unmap_sg(host->dev, data->sg, data->sg_len, 668 mmc_get_dma_dir(data)); 669 data->host_cookie &= ~MSDC_PREPARE_FLAG; 670 } 671 } 672 673 /* clock control primitives */ 674 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) 675 { 676 u32 timeout, clk_ns; 677 u32 mode = 0; 678 679 host->timeout_ns = ns; 680 host->timeout_clks = clks; 681 if (host->mmc->actual_clock == 0) { 682 timeout = 0; 683 } else { 684 clk_ns = 1000000000UL / host->mmc->actual_clock; 685 timeout = (ns + clk_ns - 1) / clk_ns + clks; 686 /* in 1048576 sclk cycle unit */ 687 timeout = (timeout + (0x1 << 20) - 1) >> 20; 688 if (host->dev_comp->clk_div_bits == 8) 689 sdr_get_field(host->base + MSDC_CFG, 690 MSDC_CFG_CKMOD, &mode); 691 else 692 sdr_get_field(host->base + MSDC_CFG, 693 MSDC_CFG_CKMOD_EXTRA, &mode); 694 /*DDR mode will double the clk cycles for data timeout */ 695 timeout = mode >= 2 ? timeout * 2 : timeout; 696 timeout = timeout > 1 ? timeout - 1 : 0; 697 timeout = timeout > 255 ? 255 : timeout; 698 } 699 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout); 700 } 701 702 static void msdc_gate_clock(struct msdc_host *host) 703 { 704 clk_disable_unprepare(host->src_clk_cg); 705 clk_disable_unprepare(host->src_clk); 706 clk_disable_unprepare(host->bus_clk); 707 clk_disable_unprepare(host->h_clk); 708 } 709 710 static void msdc_ungate_clock(struct msdc_host *host) 711 { 712 clk_prepare_enable(host->h_clk); 713 clk_prepare_enable(host->bus_clk); 714 clk_prepare_enable(host->src_clk); 715 clk_prepare_enable(host->src_clk_cg); 716 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 717 cpu_relax(); 718 } 719 720 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 721 { 722 u32 mode; 723 u32 flags; 724 u32 div; 725 u32 sclk; 726 u32 tune_reg = host->dev_comp->pad_tune_reg; 727 728 if (!hz) { 729 dev_dbg(host->dev, "set mclk to 0\n"); 730 host->mclk = 0; 731 host->mmc->actual_clock = 0; 732 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 733 return; 734 } 735 736 flags = readl(host->base + MSDC_INTEN); 737 sdr_clr_bits(host->base + MSDC_INTEN, flags); 738 if (host->dev_comp->clk_div_bits == 8) 739 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 740 else 741 sdr_clr_bits(host->base + MSDC_CFG, 742 MSDC_CFG_HS400_CK_MODE_EXTRA); 743 if (timing == MMC_TIMING_UHS_DDR50 || 744 timing == MMC_TIMING_MMC_DDR52 || 745 timing == MMC_TIMING_MMC_HS400) { 746 if (timing == MMC_TIMING_MMC_HS400) 747 mode = 0x3; 748 else 749 mode = 0x2; /* ddr mode and use divisor */ 750 751 if (hz >= (host->src_clk_freq >> 2)) { 752 div = 0; /* mean div = 1/4 */ 753 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 754 } else { 755 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 756 sclk = (host->src_clk_freq >> 2) / div; 757 div = (div >> 1); 758 } 759 760 if (timing == MMC_TIMING_MMC_HS400 && 761 hz >= (host->src_clk_freq >> 1)) { 762 if (host->dev_comp->clk_div_bits == 8) 763 sdr_set_bits(host->base + MSDC_CFG, 764 MSDC_CFG_HS400_CK_MODE); 765 else 766 sdr_set_bits(host->base + MSDC_CFG, 767 MSDC_CFG_HS400_CK_MODE_EXTRA); 768 sclk = host->src_clk_freq >> 1; 769 div = 0; /* div is ignore when bit18 is set */ 770 } 771 } else if (hz >= host->src_clk_freq) { 772 mode = 0x1; /* no divisor */ 773 div = 0; 774 sclk = host->src_clk_freq; 775 } else { 776 mode = 0x0; /* use divisor */ 777 if (hz >= (host->src_clk_freq >> 1)) { 778 div = 0; /* mean div = 1/2 */ 779 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 780 } else { 781 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 782 sclk = (host->src_clk_freq >> 2) / div; 783 } 784 } 785 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 786 /* 787 * As src_clk/HCLK use the same bit to gate/ungate, 788 * So if want to only gate src_clk, need gate its parent(mux). 789 */ 790 if (host->src_clk_cg) 791 clk_disable_unprepare(host->src_clk_cg); 792 else 793 clk_disable_unprepare(clk_get_parent(host->src_clk)); 794 if (host->dev_comp->clk_div_bits == 8) 795 sdr_set_field(host->base + MSDC_CFG, 796 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 797 (mode << 8) | div); 798 else 799 sdr_set_field(host->base + MSDC_CFG, 800 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, 801 (mode << 12) | div); 802 if (host->src_clk_cg) 803 clk_prepare_enable(host->src_clk_cg); 804 else 805 clk_prepare_enable(clk_get_parent(host->src_clk)); 806 807 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 808 cpu_relax(); 809 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 810 host->mmc->actual_clock = sclk; 811 host->mclk = hz; 812 host->timing = timing; 813 /* need because clk changed. */ 814 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 815 sdr_set_bits(host->base + MSDC_INTEN, flags); 816 817 /* 818 * mmc_select_hs400() will drop to 50Mhz and High speed mode, 819 * tune result of hs200/200Mhz is not suitable for 50Mhz 820 */ 821 if (host->mmc->actual_clock <= 52000000) { 822 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 823 if (host->top_base) { 824 writel(host->def_tune_para.emmc_top_control, 825 host->top_base + EMMC_TOP_CONTROL); 826 writel(host->def_tune_para.emmc_top_cmd, 827 host->top_base + EMMC_TOP_CMD); 828 } else { 829 writel(host->def_tune_para.pad_tune, 830 host->base + tune_reg); 831 } 832 } else { 833 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 834 writel(host->saved_tune_para.pad_cmd_tune, 835 host->base + PAD_CMD_TUNE); 836 if (host->top_base) { 837 writel(host->saved_tune_para.emmc_top_control, 838 host->top_base + EMMC_TOP_CONTROL); 839 writel(host->saved_tune_para.emmc_top_cmd, 840 host->top_base + EMMC_TOP_CMD); 841 } else { 842 writel(host->saved_tune_para.pad_tune, 843 host->base + tune_reg); 844 } 845 } 846 847 if (timing == MMC_TIMING_MMC_HS400 && 848 host->dev_comp->hs400_tune) 849 sdr_set_field(host->base + tune_reg, 850 MSDC_PAD_TUNE_CMDRRDLY, 851 host->hs400_cmd_int_delay); 852 dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->mmc->actual_clock, 853 timing); 854 } 855 856 static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 857 struct mmc_request *mrq, struct mmc_command *cmd) 858 { 859 u32 resp; 860 861 switch (mmc_resp_type(cmd)) { 862 /* Actually, R1, R5, R6, R7 are the same */ 863 case MMC_RSP_R1: 864 resp = 0x1; 865 break; 866 case MMC_RSP_R1B: 867 resp = 0x7; 868 break; 869 case MMC_RSP_R2: 870 resp = 0x2; 871 break; 872 case MMC_RSP_R3: 873 resp = 0x3; 874 break; 875 case MMC_RSP_NONE: 876 default: 877 resp = 0x0; 878 break; 879 } 880 881 return resp; 882 } 883 884 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 885 struct mmc_request *mrq, struct mmc_command *cmd) 886 { 887 /* rawcmd : 888 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 889 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 890 */ 891 u32 opcode = cmd->opcode; 892 u32 resp = msdc_cmd_find_resp(host, mrq, cmd); 893 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 894 895 host->cmd_rsp = resp; 896 897 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 898 opcode == MMC_STOP_TRANSMISSION) 899 rawcmd |= (0x1 << 14); 900 else if (opcode == SD_SWITCH_VOLTAGE) 901 rawcmd |= (0x1 << 30); 902 else if (opcode == SD_APP_SEND_SCR || 903 opcode == SD_APP_SEND_NUM_WR_BLKS || 904 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 905 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 906 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 907 rawcmd |= (0x1 << 11); 908 909 if (cmd->data) { 910 struct mmc_data *data = cmd->data; 911 912 if (mmc_op_multi(opcode)) { 913 if (mmc_card_mmc(host->mmc->card) && mrq->sbc && 914 !(mrq->sbc->arg & 0xFFFF0000)) 915 rawcmd |= 0x2 << 28; /* AutoCMD23 */ 916 } 917 918 rawcmd |= ((data->blksz & 0xFFF) << 16); 919 if (data->flags & MMC_DATA_WRITE) 920 rawcmd |= (0x1 << 13); 921 if (data->blocks > 1) 922 rawcmd |= (0x2 << 11); 923 else 924 rawcmd |= (0x1 << 11); 925 /* Always use dma mode */ 926 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 927 928 if (host->timeout_ns != data->timeout_ns || 929 host->timeout_clks != data->timeout_clks) 930 msdc_set_timeout(host, data->timeout_ns, 931 data->timeout_clks); 932 933 writel(data->blocks, host->base + SDC_BLK_NUM); 934 } 935 return rawcmd; 936 } 937 938 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, 939 struct mmc_command *cmd, struct mmc_data *data) 940 { 941 bool read; 942 943 WARN_ON(host->data); 944 host->data = data; 945 read = data->flags & MMC_DATA_READ; 946 947 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 948 msdc_dma_setup(host, &host->dma, data); 949 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 950 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 951 dev_dbg(host->dev, "DMA start\n"); 952 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 953 __func__, cmd->opcode, data->blocks, read); 954 } 955 956 static int msdc_auto_cmd_done(struct msdc_host *host, int events, 957 struct mmc_command *cmd) 958 { 959 u32 *rsp = cmd->resp; 960 961 rsp[0] = readl(host->base + SDC_ACMD_RESP); 962 963 if (events & MSDC_INT_ACMDRDY) { 964 cmd->error = 0; 965 } else { 966 msdc_reset_hw(host); 967 if (events & MSDC_INT_ACMDCRCERR) { 968 cmd->error = -EILSEQ; 969 host->error |= REQ_STOP_EIO; 970 } else if (events & MSDC_INT_ACMDTMO) { 971 cmd->error = -ETIMEDOUT; 972 host->error |= REQ_STOP_TMO; 973 } 974 dev_err(host->dev, 975 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 976 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 977 } 978 return cmd->error; 979 } 980 981 static void msdc_track_cmd_data(struct msdc_host *host, 982 struct mmc_command *cmd, struct mmc_data *data) 983 { 984 if (host->error) 985 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 986 __func__, cmd->opcode, cmd->arg, host->error); 987 } 988 989 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 990 { 991 unsigned long flags; 992 bool ret; 993 994 ret = cancel_delayed_work(&host->req_timeout); 995 if (!ret) { 996 /* delay work already running */ 997 return; 998 } 999 spin_lock_irqsave(&host->lock, flags); 1000 host->mrq = NULL; 1001 spin_unlock_irqrestore(&host->lock, flags); 1002 1003 msdc_track_cmd_data(host, mrq->cmd, mrq->data); 1004 if (mrq->data) 1005 msdc_unprepare_data(host, mrq); 1006 mmc_request_done(host->mmc, mrq); 1007 } 1008 1009 /* returns true if command is fully handled; returns false otherwise */ 1010 static bool msdc_cmd_done(struct msdc_host *host, int events, 1011 struct mmc_request *mrq, struct mmc_command *cmd) 1012 { 1013 bool done = false; 1014 bool sbc_error; 1015 unsigned long flags; 1016 u32 *rsp = cmd->resp; 1017 1018 if (mrq->sbc && cmd == mrq->cmd && 1019 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 1020 | MSDC_INT_ACMDTMO))) 1021 msdc_auto_cmd_done(host, events, mrq->sbc); 1022 1023 sbc_error = mrq->sbc && mrq->sbc->error; 1024 1025 if (!sbc_error && !(events & (MSDC_INT_CMDRDY 1026 | MSDC_INT_RSPCRCERR 1027 | MSDC_INT_CMDTMO))) 1028 return done; 1029 1030 spin_lock_irqsave(&host->lock, flags); 1031 done = !host->cmd; 1032 host->cmd = NULL; 1033 spin_unlock_irqrestore(&host->lock, flags); 1034 1035 if (done) 1036 return true; 1037 1038 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1039 1040 if (cmd->flags & MMC_RSP_PRESENT) { 1041 if (cmd->flags & MMC_RSP_136) { 1042 rsp[0] = readl(host->base + SDC_RESP3); 1043 rsp[1] = readl(host->base + SDC_RESP2); 1044 rsp[2] = readl(host->base + SDC_RESP1); 1045 rsp[3] = readl(host->base + SDC_RESP0); 1046 } else { 1047 rsp[0] = readl(host->base + SDC_RESP0); 1048 } 1049 } 1050 1051 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 1052 if (cmd->opcode != MMC_SEND_TUNING_BLOCK && 1053 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200) 1054 /* 1055 * should not clear fifo/interrupt as the tune data 1056 * may have alreay come. 1057 */ 1058 msdc_reset_hw(host); 1059 if (events & MSDC_INT_RSPCRCERR) { 1060 cmd->error = -EILSEQ; 1061 host->error |= REQ_CMD_EIO; 1062 } else if (events & MSDC_INT_CMDTMO) { 1063 cmd->error = -ETIMEDOUT; 1064 host->error |= REQ_CMD_TMO; 1065 } 1066 } 1067 if (cmd->error) 1068 dev_dbg(host->dev, 1069 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 1070 __func__, cmd->opcode, cmd->arg, rsp[0], 1071 cmd->error); 1072 1073 msdc_cmd_next(host, mrq, cmd); 1074 return true; 1075 } 1076 1077 /* It is the core layer's responsibility to ensure card status 1078 * is correct before issue a request. but host design do below 1079 * checks recommended. 1080 */ 1081 static inline bool msdc_cmd_is_ready(struct msdc_host *host, 1082 struct mmc_request *mrq, struct mmc_command *cmd) 1083 { 1084 /* The max busy time we can endure is 20ms */ 1085 unsigned long tmo = jiffies + msecs_to_jiffies(20); 1086 1087 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && 1088 time_before(jiffies, tmo)) 1089 cpu_relax(); 1090 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { 1091 dev_err(host->dev, "CMD bus busy detected\n"); 1092 host->error |= REQ_CMD_BUSY; 1093 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1094 return false; 1095 } 1096 1097 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 1098 tmo = jiffies + msecs_to_jiffies(20); 1099 /* R1B or with data, should check SDCBUSY */ 1100 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && 1101 time_before(jiffies, tmo)) 1102 cpu_relax(); 1103 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { 1104 dev_err(host->dev, "Controller busy detected\n"); 1105 host->error |= REQ_CMD_BUSY; 1106 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1107 return false; 1108 } 1109 } 1110 return true; 1111 } 1112 1113 static void msdc_start_command(struct msdc_host *host, 1114 struct mmc_request *mrq, struct mmc_command *cmd) 1115 { 1116 u32 rawcmd; 1117 unsigned long flags; 1118 1119 WARN_ON(host->cmd); 1120 host->cmd = cmd; 1121 1122 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1123 if (!msdc_cmd_is_ready(host, mrq, cmd)) 1124 return; 1125 1126 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 1127 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 1128 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 1129 msdc_reset_hw(host); 1130 } 1131 1132 cmd->error = 0; 1133 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 1134 1135 spin_lock_irqsave(&host->lock, flags); 1136 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1137 spin_unlock_irqrestore(&host->lock, flags); 1138 1139 writel(cmd->arg, host->base + SDC_ARG); 1140 writel(rawcmd, host->base + SDC_CMD); 1141 } 1142 1143 static void msdc_cmd_next(struct msdc_host *host, 1144 struct mmc_request *mrq, struct mmc_command *cmd) 1145 { 1146 if ((cmd->error && 1147 !(cmd->error == -EILSEQ && 1148 (cmd->opcode == MMC_SEND_TUNING_BLOCK || 1149 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) || 1150 (mrq->sbc && mrq->sbc->error)) 1151 msdc_request_done(host, mrq); 1152 else if (cmd == mrq->sbc) 1153 msdc_start_command(host, mrq, mrq->cmd); 1154 else if (!cmd->data) 1155 msdc_request_done(host, mrq); 1156 else 1157 msdc_start_data(host, mrq, cmd, cmd->data); 1158 } 1159 1160 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 1161 { 1162 struct msdc_host *host = mmc_priv(mmc); 1163 1164 host->error = 0; 1165 WARN_ON(host->mrq); 1166 host->mrq = mrq; 1167 1168 if (mrq->data) 1169 msdc_prepare_data(host, mrq); 1170 1171 /* if SBC is required, we have HW option and SW option. 1172 * if HW option is enabled, and SBC does not have "special" flags, 1173 * use HW option, otherwise use SW option 1174 */ 1175 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 1176 (mrq->sbc->arg & 0xFFFF0000))) 1177 msdc_start_command(host, mrq, mrq->sbc); 1178 else 1179 msdc_start_command(host, mrq, mrq->cmd); 1180 } 1181 1182 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 1183 { 1184 struct msdc_host *host = mmc_priv(mmc); 1185 struct mmc_data *data = mrq->data; 1186 1187 if (!data) 1188 return; 1189 1190 msdc_prepare_data(host, mrq); 1191 data->host_cookie |= MSDC_ASYNC_FLAG; 1192 } 1193 1194 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1195 int err) 1196 { 1197 struct msdc_host *host = mmc_priv(mmc); 1198 struct mmc_data *data; 1199 1200 data = mrq->data; 1201 if (!data) 1202 return; 1203 if (data->host_cookie) { 1204 data->host_cookie &= ~MSDC_ASYNC_FLAG; 1205 msdc_unprepare_data(host, mrq); 1206 } 1207 } 1208 1209 static void msdc_data_xfer_next(struct msdc_host *host, 1210 struct mmc_request *mrq, struct mmc_data *data) 1211 { 1212 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 1213 !mrq->sbc) 1214 msdc_start_command(host, mrq, mrq->stop); 1215 else 1216 msdc_request_done(host, mrq); 1217 } 1218 1219 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 1220 struct mmc_request *mrq, struct mmc_data *data) 1221 { 1222 struct mmc_command *stop = data->stop; 1223 unsigned long flags; 1224 bool done; 1225 unsigned int check_data = events & 1226 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 1227 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 1228 | MSDC_INT_DMA_PROTECT); 1229 1230 spin_lock_irqsave(&host->lock, flags); 1231 done = !host->data; 1232 if (check_data) 1233 host->data = NULL; 1234 spin_unlock_irqrestore(&host->lock, flags); 1235 1236 if (done) 1237 return true; 1238 1239 if (check_data || (stop && stop->error)) { 1240 dev_dbg(host->dev, "DMA status: 0x%8X\n", 1241 readl(host->base + MSDC_DMA_CFG)); 1242 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1243 1); 1244 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) 1245 cpu_relax(); 1246 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 1247 dev_dbg(host->dev, "DMA stop\n"); 1248 1249 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 1250 data->bytes_xfered = data->blocks * data->blksz; 1251 } else { 1252 dev_dbg(host->dev, "interrupt events: %x\n", events); 1253 msdc_reset_hw(host); 1254 host->error |= REQ_DAT_ERR; 1255 data->bytes_xfered = 0; 1256 1257 if (events & MSDC_INT_DATTMO) 1258 data->error = -ETIMEDOUT; 1259 else if (events & MSDC_INT_DATCRCERR) 1260 data->error = -EILSEQ; 1261 1262 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 1263 __func__, mrq->cmd->opcode, data->blocks); 1264 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 1265 (int)data->error, data->bytes_xfered); 1266 } 1267 1268 msdc_data_xfer_next(host, mrq, data); 1269 done = true; 1270 } 1271 return done; 1272 } 1273 1274 static void msdc_set_buswidth(struct msdc_host *host, u32 width) 1275 { 1276 u32 val = readl(host->base + SDC_CFG); 1277 1278 val &= ~SDC_CFG_BUSWIDTH; 1279 1280 switch (width) { 1281 default: 1282 case MMC_BUS_WIDTH_1: 1283 val |= (MSDC_BUS_1BITS << 16); 1284 break; 1285 case MMC_BUS_WIDTH_4: 1286 val |= (MSDC_BUS_4BITS << 16); 1287 break; 1288 case MMC_BUS_WIDTH_8: 1289 val |= (MSDC_BUS_8BITS << 16); 1290 break; 1291 } 1292 1293 writel(val, host->base + SDC_CFG); 1294 dev_dbg(host->dev, "Bus Width = %d", width); 1295 } 1296 1297 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 1298 { 1299 struct msdc_host *host = mmc_priv(mmc); 1300 int ret = 0; 1301 1302 if (!IS_ERR(mmc->supply.vqmmc)) { 1303 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1304 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 1305 dev_err(host->dev, "Unsupported signal voltage!\n"); 1306 return -EINVAL; 1307 } 1308 1309 ret = mmc_regulator_set_vqmmc(mmc, ios); 1310 if (ret) { 1311 dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1312 ret, ios->signal_voltage); 1313 } else { 1314 /* Apply different pinctrl settings for different signal voltage */ 1315 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 1316 pinctrl_select_state(host->pinctrl, host->pins_uhs); 1317 else 1318 pinctrl_select_state(host->pinctrl, host->pins_default); 1319 } 1320 } 1321 return ret; 1322 } 1323 1324 static int msdc_card_busy(struct mmc_host *mmc) 1325 { 1326 struct msdc_host *host = mmc_priv(mmc); 1327 u32 status = readl(host->base + MSDC_PS); 1328 1329 /* only check if data0 is low */ 1330 return !(status & BIT(16)); 1331 } 1332 1333 static void msdc_request_timeout(struct work_struct *work) 1334 { 1335 struct msdc_host *host = container_of(work, struct msdc_host, 1336 req_timeout.work); 1337 1338 /* simulate HW timeout status */ 1339 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 1340 if (host->mrq) { 1341 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 1342 host->mrq, host->mrq->cmd->opcode); 1343 if (host->cmd) { 1344 dev_err(host->dev, "%s: aborting cmd=%d\n", 1345 __func__, host->cmd->opcode); 1346 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 1347 host->cmd); 1348 } else if (host->data) { 1349 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 1350 __func__, host->mrq->cmd->opcode, 1351 host->data->blocks); 1352 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 1353 host->data); 1354 } 1355 } 1356 } 1357 1358 static void __msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) 1359 { 1360 unsigned long flags; 1361 struct msdc_host *host = mmc_priv(mmc); 1362 1363 spin_lock_irqsave(&host->lock, flags); 1364 if (enb) 1365 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1366 else 1367 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1368 spin_unlock_irqrestore(&host->lock, flags); 1369 } 1370 1371 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) 1372 { 1373 struct msdc_host *host = mmc_priv(mmc); 1374 1375 __msdc_enable_sdio_irq(mmc, enb); 1376 1377 if (enb) 1378 pm_runtime_get_noresume(host->dev); 1379 else 1380 pm_runtime_put_noidle(host->dev); 1381 } 1382 1383 static irqreturn_t msdc_irq(int irq, void *dev_id) 1384 { 1385 struct msdc_host *host = (struct msdc_host *) dev_id; 1386 1387 while (true) { 1388 unsigned long flags; 1389 struct mmc_request *mrq; 1390 struct mmc_command *cmd; 1391 struct mmc_data *data; 1392 u32 events, event_mask; 1393 1394 spin_lock_irqsave(&host->lock, flags); 1395 events = readl(host->base + MSDC_INT); 1396 event_mask = readl(host->base + MSDC_INTEN); 1397 /* clear interrupts */ 1398 writel(events & event_mask, host->base + MSDC_INT); 1399 1400 mrq = host->mrq; 1401 cmd = host->cmd; 1402 data = host->data; 1403 spin_unlock_irqrestore(&host->lock, flags); 1404 1405 if ((events & event_mask) & MSDC_INT_SDIOIRQ) { 1406 __msdc_enable_sdio_irq(host->mmc, 0); 1407 sdio_signal_irq(host->mmc); 1408 } 1409 1410 if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) 1411 break; 1412 1413 if (!mrq) { 1414 dev_err(host->dev, 1415 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 1416 __func__, events, event_mask); 1417 WARN_ON(1); 1418 break; 1419 } 1420 1421 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 1422 1423 if (cmd) 1424 msdc_cmd_done(host, events, mrq, cmd); 1425 else if (data) 1426 msdc_data_xfer_done(host, events, mrq, data); 1427 } 1428 1429 return IRQ_HANDLED; 1430 } 1431 1432 static void msdc_init_hw(struct msdc_host *host) 1433 { 1434 u32 val; 1435 u32 tune_reg = host->dev_comp->pad_tune_reg; 1436 1437 /* Configure to MMC/SD mode, clock free running */ 1438 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 1439 1440 /* Reset */ 1441 msdc_reset_hw(host); 1442 1443 /* Disable card detection */ 1444 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1445 1446 /* Disable and clear all interrupts */ 1447 writel(0, host->base + MSDC_INTEN); 1448 val = readl(host->base + MSDC_INT); 1449 writel(val, host->base + MSDC_INT); 1450 1451 if (host->top_base) { 1452 writel(0, host->top_base + EMMC_TOP_CONTROL); 1453 writel(0, host->top_base + EMMC_TOP_CMD); 1454 } else { 1455 writel(0, host->base + tune_reg); 1456 } 1457 writel(0, host->base + MSDC_IOCON); 1458 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 1459 writel(0x403c0046, host->base + MSDC_PATCH_BIT); 1460 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 1461 writel(0xffff4089, host->base + MSDC_PATCH_BIT1); 1462 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1463 1464 if (host->dev_comp->stop_clk_fix) { 1465 sdr_set_field(host->base + MSDC_PATCH_BIT1, 1466 MSDC_PATCH_BIT1_STOP_DLY, 3); 1467 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1468 SDC_FIFO_CFG_WRVALIDSEL); 1469 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1470 SDC_FIFO_CFG_RDVALIDSEL); 1471 } 1472 1473 if (host->dev_comp->busy_check) 1474 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7)); 1475 1476 if (host->dev_comp->async_fifo) { 1477 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1478 MSDC_PB2_RESPWAIT, 3); 1479 if (host->dev_comp->enhance_rx) { 1480 if (host->top_base) 1481 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1482 SDC_RX_ENH_EN); 1483 else 1484 sdr_set_bits(host->base + SDC_ADV_CFG0, 1485 SDC_RX_ENHANCE_EN); 1486 } else { 1487 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1488 MSDC_PB2_RESPSTSENSEL, 2); 1489 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1490 MSDC_PB2_CRCSTSENSEL, 2); 1491 } 1492 /* use async fifo, then no need tune internal delay */ 1493 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, 1494 MSDC_PATCH_BIT2_CFGRESP); 1495 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1496 MSDC_PATCH_BIT2_CFGCRCSTS); 1497 } 1498 1499 if (host->dev_comp->support_64g) 1500 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1501 MSDC_PB2_SUPPORT_64G); 1502 if (host->dev_comp->data_tune) { 1503 if (host->top_base) { 1504 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1505 PAD_DAT_RD_RXDLY_SEL); 1506 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, 1507 DATA_K_VALUE_SEL); 1508 sdr_set_bits(host->top_base + EMMC_TOP_CMD, 1509 PAD_CMD_RD_RXDLY_SEL); 1510 } else { 1511 sdr_set_bits(host->base + tune_reg, 1512 MSDC_PAD_TUNE_RD_SEL | 1513 MSDC_PAD_TUNE_CMD_SEL); 1514 } 1515 } else { 1516 /* choose clock tune */ 1517 if (host->top_base) 1518 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1519 PAD_RXDLY_SEL); 1520 else 1521 sdr_set_bits(host->base + tune_reg, 1522 MSDC_PAD_TUNE_RXDLYSEL); 1523 } 1524 1525 /* Configure to enable SDIO mode. 1526 * it's must otherwise sdio cmd5 failed 1527 */ 1528 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1529 1530 /* Config SDIO device detect interrupt function */ 1531 if (host->mmc->caps & MMC_CAP_SDIO_IRQ) 1532 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1533 else 1534 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1535 1536 /* Configure to default data timeout */ 1537 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 1538 1539 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 1540 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1541 if (host->top_base) { 1542 host->def_tune_para.emmc_top_control = 1543 readl(host->top_base + EMMC_TOP_CONTROL); 1544 host->def_tune_para.emmc_top_cmd = 1545 readl(host->top_base + EMMC_TOP_CMD); 1546 host->saved_tune_para.emmc_top_control = 1547 readl(host->top_base + EMMC_TOP_CONTROL); 1548 host->saved_tune_para.emmc_top_cmd = 1549 readl(host->top_base + EMMC_TOP_CMD); 1550 } else { 1551 host->def_tune_para.pad_tune = readl(host->base + tune_reg); 1552 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 1553 } 1554 dev_dbg(host->dev, "init hardware done!"); 1555 } 1556 1557 static void msdc_deinit_hw(struct msdc_host *host) 1558 { 1559 u32 val; 1560 /* Disable and clear all interrupts */ 1561 writel(0, host->base + MSDC_INTEN); 1562 1563 val = readl(host->base + MSDC_INT); 1564 writel(val, host->base + MSDC_INT); 1565 } 1566 1567 /* init gpd and bd list in msdc_drv_probe */ 1568 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 1569 { 1570 struct mt_gpdma_desc *gpd = dma->gpd; 1571 struct mt_bdma_desc *bd = dma->bd; 1572 dma_addr_t dma_addr; 1573 int i; 1574 1575 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 1576 1577 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); 1578 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 1579 /* gpd->next is must set for desc DMA 1580 * That's why must alloc 2 gpd structure. 1581 */ 1582 gpd->next = lower_32_bits(dma_addr); 1583 if (host->dev_comp->support_64g) 1584 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1585 1586 dma_addr = dma->bd_addr; 1587 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ 1588 if (host->dev_comp->support_64g) 1589 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; 1590 1591 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 1592 for (i = 0; i < (MAX_BD_NUM - 1); i++) { 1593 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); 1594 bd[i].next = lower_32_bits(dma_addr); 1595 if (host->dev_comp->support_64g) 1596 bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1597 } 1598 } 1599 1600 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1601 { 1602 struct msdc_host *host = mmc_priv(mmc); 1603 int ret; 1604 1605 msdc_set_buswidth(host, ios->bus_width); 1606 1607 /* Suspend/Resume will do power off/on */ 1608 switch (ios->power_mode) { 1609 case MMC_POWER_UP: 1610 if (!IS_ERR(mmc->supply.vmmc)) { 1611 msdc_init_hw(host); 1612 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1613 ios->vdd); 1614 if (ret) { 1615 dev_err(host->dev, "Failed to set vmmc power!\n"); 1616 return; 1617 } 1618 } 1619 break; 1620 case MMC_POWER_ON: 1621 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1622 ret = regulator_enable(mmc->supply.vqmmc); 1623 if (ret) 1624 dev_err(host->dev, "Failed to set vqmmc power!\n"); 1625 else 1626 host->vqmmc_enabled = true; 1627 } 1628 break; 1629 case MMC_POWER_OFF: 1630 if (!IS_ERR(mmc->supply.vmmc)) 1631 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1632 1633 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1634 regulator_disable(mmc->supply.vqmmc); 1635 host->vqmmc_enabled = false; 1636 } 1637 break; 1638 default: 1639 break; 1640 } 1641 1642 if (host->mclk != ios->clock || host->timing != ios->timing) 1643 msdc_set_mclk(host, ios->timing, ios->clock); 1644 } 1645 1646 static u32 test_delay_bit(u32 delay, u32 bit) 1647 { 1648 bit %= PAD_DELAY_MAX; 1649 return delay & (1 << bit); 1650 } 1651 1652 static int get_delay_len(u32 delay, u32 start_bit) 1653 { 1654 int i; 1655 1656 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 1657 if (test_delay_bit(delay, start_bit + i) == 0) 1658 return i; 1659 } 1660 return PAD_DELAY_MAX - start_bit; 1661 } 1662 1663 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 1664 { 1665 int start = 0, len = 0; 1666 int start_final = 0, len_final = 0; 1667 u8 final_phase = 0xff; 1668 struct msdc_delay_phase delay_phase = { 0, }; 1669 1670 if (delay == 0) { 1671 dev_err(host->dev, "phase error: [map:%x]\n", delay); 1672 delay_phase.final_phase = final_phase; 1673 return delay_phase; 1674 } 1675 1676 while (start < PAD_DELAY_MAX) { 1677 len = get_delay_len(delay, start); 1678 if (len_final < len) { 1679 start_final = start; 1680 len_final = len; 1681 } 1682 start += len ? len : 1; 1683 if (len >= 12 && start_final < 4) 1684 break; 1685 } 1686 1687 /* The rule is that to find the smallest delay cell */ 1688 if (start_final == 0) 1689 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 1690 else 1691 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 1692 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 1693 delay, len_final, final_phase); 1694 1695 delay_phase.maxlen = len_final; 1696 delay_phase.start = start_final; 1697 delay_phase.final_phase = final_phase; 1698 return delay_phase; 1699 } 1700 1701 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) 1702 { 1703 u32 tune_reg = host->dev_comp->pad_tune_reg; 1704 1705 if (host->top_base) 1706 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, 1707 value); 1708 else 1709 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1710 value); 1711 } 1712 1713 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) 1714 { 1715 u32 tune_reg = host->dev_comp->pad_tune_reg; 1716 1717 if (host->top_base) 1718 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, 1719 PAD_DAT_RD_RXDLY, value); 1720 else 1721 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, 1722 value); 1723 } 1724 1725 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 1726 { 1727 struct msdc_host *host = mmc_priv(mmc); 1728 u32 rise_delay = 0, fall_delay = 0; 1729 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1730 struct msdc_delay_phase internal_delay_phase; 1731 u8 final_delay, final_maxlen; 1732 u32 internal_delay = 0; 1733 u32 tune_reg = host->dev_comp->pad_tune_reg; 1734 int cmd_err; 1735 int i, j; 1736 1737 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 1738 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 1739 sdr_set_field(host->base + tune_reg, 1740 MSDC_PAD_TUNE_CMDRRDLY, 1741 host->hs200_cmd_int_delay); 1742 1743 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1744 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1745 msdc_set_cmd_delay(host, i); 1746 /* 1747 * Using the same parameters, it may sometimes pass the test, 1748 * but sometimes it may fail. To make sure the parameters are 1749 * more stable, we test each set of parameters 3 times. 1750 */ 1751 for (j = 0; j < 3; j++) { 1752 mmc_send_tuning(mmc, opcode, &cmd_err); 1753 if (!cmd_err) { 1754 rise_delay |= (1 << i); 1755 } else { 1756 rise_delay &= ~(1 << i); 1757 break; 1758 } 1759 } 1760 } 1761 final_rise_delay = get_best_delay(host, rise_delay); 1762 /* if rising edge has enough margin, then do not scan falling edge */ 1763 if (final_rise_delay.maxlen >= 12 || 1764 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1765 goto skip_fall; 1766 1767 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1768 for (i = 0; i < PAD_DELAY_MAX; i++) { 1769 msdc_set_cmd_delay(host, i); 1770 /* 1771 * Using the same parameters, it may sometimes pass the test, 1772 * but sometimes it may fail. To make sure the parameters are 1773 * more stable, we test each set of parameters 3 times. 1774 */ 1775 for (j = 0; j < 3; j++) { 1776 mmc_send_tuning(mmc, opcode, &cmd_err); 1777 if (!cmd_err) { 1778 fall_delay |= (1 << i); 1779 } else { 1780 fall_delay &= ~(1 << i); 1781 break; 1782 } 1783 } 1784 } 1785 final_fall_delay = get_best_delay(host, fall_delay); 1786 1787 skip_fall: 1788 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1789 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 1790 final_maxlen = final_fall_delay.maxlen; 1791 if (final_maxlen == final_rise_delay.maxlen) { 1792 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1793 final_delay = final_rise_delay.final_phase; 1794 } else { 1795 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1796 final_delay = final_fall_delay.final_phase; 1797 } 1798 msdc_set_cmd_delay(host, final_delay); 1799 1800 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) 1801 goto skip_internal; 1802 1803 for (i = 0; i < PAD_DELAY_MAX; i++) { 1804 sdr_set_field(host->base + tune_reg, 1805 MSDC_PAD_TUNE_CMDRRDLY, i); 1806 mmc_send_tuning(mmc, opcode, &cmd_err); 1807 if (!cmd_err) 1808 internal_delay |= (1 << i); 1809 } 1810 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 1811 internal_delay_phase = get_best_delay(host, internal_delay); 1812 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 1813 internal_delay_phase.final_phase); 1814 skip_internal: 1815 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 1816 return final_delay == 0xff ? -EIO : 0; 1817 } 1818 1819 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 1820 { 1821 struct msdc_host *host = mmc_priv(mmc); 1822 u32 cmd_delay = 0; 1823 struct msdc_delay_phase final_cmd_delay = { 0,}; 1824 u8 final_delay; 1825 int cmd_err; 1826 int i, j; 1827 1828 /* select EMMC50 PAD CMD tune */ 1829 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 1830 1831 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 1832 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 1833 sdr_set_field(host->base + MSDC_PAD_TUNE, 1834 MSDC_PAD_TUNE_CMDRRDLY, 1835 host->hs200_cmd_int_delay); 1836 1837 if (host->hs400_cmd_resp_sel_rising) 1838 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1839 else 1840 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1841 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1842 sdr_set_field(host->base + PAD_CMD_TUNE, 1843 PAD_CMD_TUNE_RX_DLY3, i); 1844 /* 1845 * Using the same parameters, it may sometimes pass the test, 1846 * but sometimes it may fail. To make sure the parameters are 1847 * more stable, we test each set of parameters 3 times. 1848 */ 1849 for (j = 0; j < 3; j++) { 1850 mmc_send_tuning(mmc, opcode, &cmd_err); 1851 if (!cmd_err) { 1852 cmd_delay |= (1 << i); 1853 } else { 1854 cmd_delay &= ~(1 << i); 1855 break; 1856 } 1857 } 1858 } 1859 final_cmd_delay = get_best_delay(host, cmd_delay); 1860 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 1861 final_cmd_delay.final_phase); 1862 final_delay = final_cmd_delay.final_phase; 1863 1864 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 1865 return final_delay == 0xff ? -EIO : 0; 1866 } 1867 1868 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 1869 { 1870 struct msdc_host *host = mmc_priv(mmc); 1871 u32 rise_delay = 0, fall_delay = 0; 1872 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1873 u8 final_delay, final_maxlen; 1874 int i, ret; 1875 1876 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 1877 host->latch_ck); 1878 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1879 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1880 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1881 msdc_set_data_delay(host, i); 1882 ret = mmc_send_tuning(mmc, opcode, NULL); 1883 if (!ret) 1884 rise_delay |= (1 << i); 1885 } 1886 final_rise_delay = get_best_delay(host, rise_delay); 1887 /* if rising edge has enough margin, then do not scan falling edge */ 1888 if (final_rise_delay.maxlen >= 12 || 1889 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1890 goto skip_fall; 1891 1892 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1893 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1894 for (i = 0; i < PAD_DELAY_MAX; i++) { 1895 msdc_set_data_delay(host, i); 1896 ret = mmc_send_tuning(mmc, opcode, NULL); 1897 if (!ret) 1898 fall_delay |= (1 << i); 1899 } 1900 final_fall_delay = get_best_delay(host, fall_delay); 1901 1902 skip_fall: 1903 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1904 if (final_maxlen == final_rise_delay.maxlen) { 1905 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1906 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1907 final_delay = final_rise_delay.final_phase; 1908 } else { 1909 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1910 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1911 final_delay = final_fall_delay.final_phase; 1912 } 1913 msdc_set_data_delay(host, final_delay); 1914 1915 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 1916 return final_delay == 0xff ? -EIO : 0; 1917 } 1918 1919 /* 1920 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune 1921 * together, which can save the tuning time. 1922 */ 1923 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode) 1924 { 1925 struct msdc_host *host = mmc_priv(mmc); 1926 u32 rise_delay = 0, fall_delay = 0; 1927 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1928 u8 final_delay, final_maxlen; 1929 int i, ret; 1930 1931 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 1932 host->latch_ck); 1933 1934 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1935 sdr_clr_bits(host->base + MSDC_IOCON, 1936 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 1937 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1938 msdc_set_cmd_delay(host, i); 1939 msdc_set_data_delay(host, i); 1940 ret = mmc_send_tuning(mmc, opcode, NULL); 1941 if (!ret) 1942 rise_delay |= (1 << i); 1943 } 1944 final_rise_delay = get_best_delay(host, rise_delay); 1945 /* if rising edge has enough margin, then do not scan falling edge */ 1946 if (final_rise_delay.maxlen >= 12 || 1947 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1948 goto skip_fall; 1949 1950 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1951 sdr_set_bits(host->base + MSDC_IOCON, 1952 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 1953 for (i = 0; i < PAD_DELAY_MAX; i++) { 1954 msdc_set_cmd_delay(host, i); 1955 msdc_set_data_delay(host, i); 1956 ret = mmc_send_tuning(mmc, opcode, NULL); 1957 if (!ret) 1958 fall_delay |= (1 << i); 1959 } 1960 final_fall_delay = get_best_delay(host, fall_delay); 1961 1962 skip_fall: 1963 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1964 if (final_maxlen == final_rise_delay.maxlen) { 1965 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1966 sdr_clr_bits(host->base + MSDC_IOCON, 1967 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 1968 final_delay = final_rise_delay.final_phase; 1969 } else { 1970 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1971 sdr_set_bits(host->base + MSDC_IOCON, 1972 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 1973 final_delay = final_fall_delay.final_phase; 1974 } 1975 1976 msdc_set_cmd_delay(host, final_delay); 1977 msdc_set_data_delay(host, final_delay); 1978 1979 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); 1980 return final_delay == 0xff ? -EIO : 0; 1981 } 1982 1983 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1984 { 1985 struct msdc_host *host = mmc_priv(mmc); 1986 int ret; 1987 u32 tune_reg = host->dev_comp->pad_tune_reg; 1988 1989 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { 1990 ret = msdc_tune_together(mmc, opcode); 1991 if (host->hs400_mode) { 1992 sdr_clr_bits(host->base + MSDC_IOCON, 1993 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 1994 msdc_set_data_delay(host, 0); 1995 } 1996 goto tune_done; 1997 } 1998 if (host->hs400_mode && 1999 host->dev_comp->hs400_tune) 2000 ret = hs400_tune_response(mmc, opcode); 2001 else 2002 ret = msdc_tune_response(mmc, opcode); 2003 if (ret == -EIO) { 2004 dev_err(host->dev, "Tune response fail!\n"); 2005 return ret; 2006 } 2007 if (host->hs400_mode == false) { 2008 ret = msdc_tune_data(mmc, opcode); 2009 if (ret == -EIO) 2010 dev_err(host->dev, "Tune data fail!\n"); 2011 } 2012 2013 tune_done: 2014 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 2015 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 2016 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2017 if (host->top_base) { 2018 host->saved_tune_para.emmc_top_control = readl(host->top_base + 2019 EMMC_TOP_CONTROL); 2020 host->saved_tune_para.emmc_top_cmd = readl(host->top_base + 2021 EMMC_TOP_CMD); 2022 } 2023 return ret; 2024 } 2025 2026 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 2027 { 2028 struct msdc_host *host = mmc_priv(mmc); 2029 host->hs400_mode = true; 2030 2031 if (host->top_base) 2032 writel(host->hs400_ds_delay, 2033 host->top_base + EMMC50_PAD_DS_TUNE); 2034 else 2035 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 2036 /* hs400 mode must set it to 0 */ 2037 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); 2038 /* to improve read performance, set outstanding to 2 */ 2039 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); 2040 2041 return 0; 2042 } 2043 2044 static void msdc_hw_reset(struct mmc_host *mmc) 2045 { 2046 struct msdc_host *host = mmc_priv(mmc); 2047 2048 sdr_set_bits(host->base + EMMC_IOCON, 1); 2049 udelay(10); /* 10us is enough */ 2050 sdr_clr_bits(host->base + EMMC_IOCON, 1); 2051 } 2052 2053 static void msdc_ack_sdio_irq(struct mmc_host *mmc) 2054 { 2055 __msdc_enable_sdio_irq(mmc, 1); 2056 } 2057 2058 static const struct mmc_host_ops mt_msdc_ops = { 2059 .post_req = msdc_post_req, 2060 .pre_req = msdc_pre_req, 2061 .request = msdc_ops_request, 2062 .set_ios = msdc_ops_set_ios, 2063 .get_ro = mmc_gpio_get_ro, 2064 .get_cd = mmc_gpio_get_cd, 2065 .enable_sdio_irq = msdc_enable_sdio_irq, 2066 .ack_sdio_irq = msdc_ack_sdio_irq, 2067 .start_signal_voltage_switch = msdc_ops_switch_volt, 2068 .card_busy = msdc_card_busy, 2069 .execute_tuning = msdc_execute_tuning, 2070 .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 2071 .hw_reset = msdc_hw_reset, 2072 }; 2073 2074 static void msdc_of_property_parse(struct platform_device *pdev, 2075 struct msdc_host *host) 2076 { 2077 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", 2078 &host->latch_ck); 2079 2080 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 2081 &host->hs400_ds_delay); 2082 2083 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 2084 &host->hs200_cmd_int_delay); 2085 2086 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 2087 &host->hs400_cmd_int_delay); 2088 2089 if (of_property_read_bool(pdev->dev.of_node, 2090 "mediatek,hs400-cmd-resp-sel-rising")) 2091 host->hs400_cmd_resp_sel_rising = true; 2092 else 2093 host->hs400_cmd_resp_sel_rising = false; 2094 } 2095 2096 static int msdc_drv_probe(struct platform_device *pdev) 2097 { 2098 struct mmc_host *mmc; 2099 struct msdc_host *host; 2100 struct resource *res; 2101 int ret; 2102 2103 if (!pdev->dev.of_node) { 2104 dev_err(&pdev->dev, "No DT found\n"); 2105 return -EINVAL; 2106 } 2107 2108 /* Allocate MMC host for this device */ 2109 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 2110 if (!mmc) 2111 return -ENOMEM; 2112 2113 host = mmc_priv(mmc); 2114 ret = mmc_of_parse(mmc); 2115 if (ret) 2116 goto host_free; 2117 2118 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2119 host->base = devm_ioremap_resource(&pdev->dev, res); 2120 if (IS_ERR(host->base)) { 2121 ret = PTR_ERR(host->base); 2122 goto host_free; 2123 } 2124 2125 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2126 host->top_base = devm_ioremap_resource(&pdev->dev, res); 2127 if (IS_ERR(host->top_base)) 2128 host->top_base = NULL; 2129 2130 ret = mmc_regulator_get_supply(mmc); 2131 if (ret) 2132 goto host_free; 2133 2134 host->src_clk = devm_clk_get(&pdev->dev, "source"); 2135 if (IS_ERR(host->src_clk)) { 2136 ret = PTR_ERR(host->src_clk); 2137 goto host_free; 2138 } 2139 2140 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 2141 if (IS_ERR(host->h_clk)) { 2142 ret = PTR_ERR(host->h_clk); 2143 goto host_free; 2144 } 2145 2146 host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); 2147 if (IS_ERR(host->bus_clk)) 2148 host->bus_clk = NULL; 2149 /*source clock control gate is optional clock*/ 2150 host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg"); 2151 if (IS_ERR(host->src_clk_cg)) 2152 host->src_clk_cg = NULL; 2153 2154 host->irq = platform_get_irq(pdev, 0); 2155 if (host->irq < 0) { 2156 ret = -EINVAL; 2157 goto host_free; 2158 } 2159 2160 host->pinctrl = devm_pinctrl_get(&pdev->dev); 2161 if (IS_ERR(host->pinctrl)) { 2162 ret = PTR_ERR(host->pinctrl); 2163 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 2164 goto host_free; 2165 } 2166 2167 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 2168 if (IS_ERR(host->pins_default)) { 2169 ret = PTR_ERR(host->pins_default); 2170 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 2171 goto host_free; 2172 } 2173 2174 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 2175 if (IS_ERR(host->pins_uhs)) { 2176 ret = PTR_ERR(host->pins_uhs); 2177 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 2178 goto host_free; 2179 } 2180 2181 msdc_of_property_parse(pdev, host); 2182 2183 host->dev = &pdev->dev; 2184 host->dev_comp = of_device_get_match_data(&pdev->dev); 2185 host->mmc = mmc; 2186 host->src_clk_freq = clk_get_rate(host->src_clk); 2187 /* Set host parameters to mmc */ 2188 mmc->ops = &mt_msdc_ops; 2189 if (host->dev_comp->clk_div_bits == 8) 2190 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 2191 else 2192 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); 2193 2194 if (mmc->caps & MMC_CAP_SDIO_IRQ) 2195 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2196 2197 mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; 2198 /* MMC core transfer sizes tunable parameters */ 2199 mmc->max_segs = MAX_BD_NUM; 2200 mmc->max_seg_size = BDMA_DESC_BUFLEN; 2201 mmc->max_blk_size = 2048; 2202 mmc->max_req_size = 512 * 1024; 2203 mmc->max_blk_count = mmc->max_req_size / 512; 2204 if (host->dev_comp->support_64g) 2205 host->dma_mask = DMA_BIT_MASK(36); 2206 else 2207 host->dma_mask = DMA_BIT_MASK(32); 2208 mmc_dev(mmc)->dma_mask = &host->dma_mask; 2209 2210 host->timeout_clks = 3 * 1048576; 2211 host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2212 2 * sizeof(struct mt_gpdma_desc), 2213 &host->dma.gpd_addr, GFP_KERNEL); 2214 host->dma.bd = dma_alloc_coherent(&pdev->dev, 2215 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2216 &host->dma.bd_addr, GFP_KERNEL); 2217 if (!host->dma.gpd || !host->dma.bd) { 2218 ret = -ENOMEM; 2219 goto release_mem; 2220 } 2221 msdc_init_gpd_bd(host, &host->dma); 2222 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 2223 spin_lock_init(&host->lock); 2224 2225 platform_set_drvdata(pdev, mmc); 2226 msdc_ungate_clock(host); 2227 msdc_init_hw(host); 2228 2229 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 2230 IRQF_TRIGGER_LOW | IRQF_ONESHOT, pdev->name, host); 2231 if (ret) 2232 goto release; 2233 2234 pm_runtime_set_active(host->dev); 2235 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 2236 pm_runtime_use_autosuspend(host->dev); 2237 pm_runtime_enable(host->dev); 2238 ret = mmc_add_host(mmc); 2239 2240 if (ret) 2241 goto end; 2242 2243 return 0; 2244 end: 2245 pm_runtime_disable(host->dev); 2246 release: 2247 platform_set_drvdata(pdev, NULL); 2248 msdc_deinit_hw(host); 2249 msdc_gate_clock(host); 2250 release_mem: 2251 if (host->dma.gpd) 2252 dma_free_coherent(&pdev->dev, 2253 2 * sizeof(struct mt_gpdma_desc), 2254 host->dma.gpd, host->dma.gpd_addr); 2255 if (host->dma.bd) 2256 dma_free_coherent(&pdev->dev, 2257 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2258 host->dma.bd, host->dma.bd_addr); 2259 host_free: 2260 mmc_free_host(mmc); 2261 2262 return ret; 2263 } 2264 2265 static int msdc_drv_remove(struct platform_device *pdev) 2266 { 2267 struct mmc_host *mmc; 2268 struct msdc_host *host; 2269 2270 mmc = platform_get_drvdata(pdev); 2271 host = mmc_priv(mmc); 2272 2273 pm_runtime_get_sync(host->dev); 2274 2275 platform_set_drvdata(pdev, NULL); 2276 mmc_remove_host(host->mmc); 2277 msdc_deinit_hw(host); 2278 msdc_gate_clock(host); 2279 2280 pm_runtime_disable(host->dev); 2281 pm_runtime_put_noidle(host->dev); 2282 dma_free_coherent(&pdev->dev, 2283 2 * sizeof(struct mt_gpdma_desc), 2284 host->dma.gpd, host->dma.gpd_addr); 2285 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2286 host->dma.bd, host->dma.bd_addr); 2287 2288 mmc_free_host(host->mmc); 2289 2290 return 0; 2291 } 2292 2293 #ifdef CONFIG_PM 2294 static void msdc_save_reg(struct msdc_host *host) 2295 { 2296 u32 tune_reg = host->dev_comp->pad_tune_reg; 2297 2298 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 2299 host->save_para.iocon = readl(host->base + MSDC_IOCON); 2300 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 2301 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 2302 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 2303 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); 2304 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 2305 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2306 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 2307 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); 2308 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); 2309 if (host->top_base) { 2310 host->save_para.emmc_top_control = 2311 readl(host->top_base + EMMC_TOP_CONTROL); 2312 host->save_para.emmc_top_cmd = 2313 readl(host->top_base + EMMC_TOP_CMD); 2314 host->save_para.emmc50_pad_ds_tune = 2315 readl(host->top_base + EMMC50_PAD_DS_TUNE); 2316 } else { 2317 host->save_para.pad_tune = readl(host->base + tune_reg); 2318 } 2319 } 2320 2321 static void msdc_restore_reg(struct msdc_host *host) 2322 { 2323 u32 tune_reg = host->dev_comp->pad_tune_reg; 2324 2325 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 2326 writel(host->save_para.iocon, host->base + MSDC_IOCON); 2327 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 2328 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 2329 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 2330 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); 2331 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 2332 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 2333 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 2334 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); 2335 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); 2336 if (host->top_base) { 2337 writel(host->save_para.emmc_top_control, 2338 host->top_base + EMMC_TOP_CONTROL); 2339 writel(host->save_para.emmc_top_cmd, 2340 host->top_base + EMMC_TOP_CMD); 2341 writel(host->save_para.emmc50_pad_ds_tune, 2342 host->top_base + EMMC50_PAD_DS_TUNE); 2343 } else { 2344 writel(host->save_para.pad_tune, host->base + tune_reg); 2345 } 2346 } 2347 2348 static int msdc_runtime_suspend(struct device *dev) 2349 { 2350 struct mmc_host *mmc = dev_get_drvdata(dev); 2351 struct msdc_host *host = mmc_priv(mmc); 2352 2353 msdc_save_reg(host); 2354 msdc_gate_clock(host); 2355 return 0; 2356 } 2357 2358 static int msdc_runtime_resume(struct device *dev) 2359 { 2360 struct mmc_host *mmc = dev_get_drvdata(dev); 2361 struct msdc_host *host = mmc_priv(mmc); 2362 2363 msdc_ungate_clock(host); 2364 msdc_restore_reg(host); 2365 return 0; 2366 } 2367 #endif 2368 2369 static const struct dev_pm_ops msdc_dev_pm_ops = { 2370 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2371 pm_runtime_force_resume) 2372 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 2373 }; 2374 2375 static struct platform_driver mt_msdc_driver = { 2376 .probe = msdc_drv_probe, 2377 .remove = msdc_drv_remove, 2378 .driver = { 2379 .name = "mtk-msdc", 2380 .of_match_table = msdc_of_ids, 2381 .pm = &msdc_dev_pm_ops, 2382 }, 2383 }; 2384 2385 module_platform_driver(mt_msdc_driver); 2386 MODULE_LICENSE("GPL v2"); 2387 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 2388