1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2015, 2022 MediaTek Inc. 4 * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 5 */ 6 7 #include <linux/module.h> 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/iopoll.h> 13 #include <linux/ioport.h> 14 #include <linux/irq.h> 15 #include <linux/of_address.h> 16 #include <linux/of_device.h> 17 #include <linux/of_irq.h> 18 #include <linux/of_gpio.h> 19 #include <linux/pinctrl/consumer.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/pm_wakeirq.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/slab.h> 26 #include <linux/spinlock.h> 27 #include <linux/interrupt.h> 28 #include <linux/reset.h> 29 30 #include <linux/mmc/card.h> 31 #include <linux/mmc/core.h> 32 #include <linux/mmc/host.h> 33 #include <linux/mmc/mmc.h> 34 #include <linux/mmc/sd.h> 35 #include <linux/mmc/sdio.h> 36 #include <linux/mmc/slot-gpio.h> 37 38 #include "cqhci.h" 39 40 #define MAX_BD_NUM 1024 41 #define MSDC_NR_CLOCKS 3 42 43 /*--------------------------------------------------------------------------*/ 44 /* Common Definition */ 45 /*--------------------------------------------------------------------------*/ 46 #define MSDC_BUS_1BITS 0x0 47 #define MSDC_BUS_4BITS 0x1 48 #define MSDC_BUS_8BITS 0x2 49 50 #define MSDC_BURST_64B 0x6 51 52 /*--------------------------------------------------------------------------*/ 53 /* Register Offset */ 54 /*--------------------------------------------------------------------------*/ 55 #define MSDC_CFG 0x0 56 #define MSDC_IOCON 0x04 57 #define MSDC_PS 0x08 58 #define MSDC_INT 0x0c 59 #define MSDC_INTEN 0x10 60 #define MSDC_FIFOCS 0x14 61 #define SDC_CFG 0x30 62 #define SDC_CMD 0x34 63 #define SDC_ARG 0x38 64 #define SDC_STS 0x3c 65 #define SDC_RESP0 0x40 66 #define SDC_RESP1 0x44 67 #define SDC_RESP2 0x48 68 #define SDC_RESP3 0x4c 69 #define SDC_BLK_NUM 0x50 70 #define SDC_ADV_CFG0 0x64 71 #define EMMC_IOCON 0x7c 72 #define SDC_ACMD_RESP 0x80 73 #define DMA_SA_H4BIT 0x8c 74 #define MSDC_DMA_SA 0x90 75 #define MSDC_DMA_CTRL 0x98 76 #define MSDC_DMA_CFG 0x9c 77 #define MSDC_PATCH_BIT 0xb0 78 #define MSDC_PATCH_BIT1 0xb4 79 #define MSDC_PATCH_BIT2 0xb8 80 #define MSDC_PAD_TUNE 0xec 81 #define MSDC_PAD_TUNE0 0xf0 82 #define PAD_DS_TUNE 0x188 83 #define PAD_CMD_TUNE 0x18c 84 #define EMMC51_CFG0 0x204 85 #define EMMC50_CFG0 0x208 86 #define EMMC50_CFG1 0x20c 87 #define EMMC50_CFG3 0x220 88 #define SDC_FIFO_CFG 0x228 89 #define CQHCI_SETTING 0x7fc 90 91 /*--------------------------------------------------------------------------*/ 92 /* Top Pad Register Offset */ 93 /*--------------------------------------------------------------------------*/ 94 #define EMMC_TOP_CONTROL 0x00 95 #define EMMC_TOP_CMD 0x04 96 #define EMMC50_PAD_DS_TUNE 0x0c 97 98 /*--------------------------------------------------------------------------*/ 99 /* Register Mask */ 100 /*--------------------------------------------------------------------------*/ 101 102 /* MSDC_CFG mask */ 103 #define MSDC_CFG_MODE BIT(0) /* RW */ 104 #define MSDC_CFG_CKPDN BIT(1) /* RW */ 105 #define MSDC_CFG_RST BIT(2) /* RW */ 106 #define MSDC_CFG_PIO BIT(3) /* RW */ 107 #define MSDC_CFG_CKDRVEN BIT(4) /* RW */ 108 #define MSDC_CFG_BV18SDT BIT(5) /* RW */ 109 #define MSDC_CFG_BV18PSS BIT(6) /* R */ 110 #define MSDC_CFG_CKSTB BIT(7) /* R */ 111 #define MSDC_CFG_CKDIV GENMASK(15, 8) /* RW */ 112 #define MSDC_CFG_CKMOD GENMASK(17, 16) /* RW */ 113 #define MSDC_CFG_HS400_CK_MODE BIT(18) /* RW */ 114 #define MSDC_CFG_HS400_CK_MODE_EXTRA BIT(22) /* RW */ 115 #define MSDC_CFG_CKDIV_EXTRA GENMASK(19, 8) /* RW */ 116 #define MSDC_CFG_CKMOD_EXTRA GENMASK(21, 20) /* RW */ 117 118 /* MSDC_IOCON mask */ 119 #define MSDC_IOCON_SDR104CKS BIT(0) /* RW */ 120 #define MSDC_IOCON_RSPL BIT(1) /* RW */ 121 #define MSDC_IOCON_DSPL BIT(2) /* RW */ 122 #define MSDC_IOCON_DDLSEL BIT(3) /* RW */ 123 #define MSDC_IOCON_DDR50CKD BIT(4) /* RW */ 124 #define MSDC_IOCON_DSPLSEL BIT(5) /* RW */ 125 #define MSDC_IOCON_W_DSPL BIT(8) /* RW */ 126 #define MSDC_IOCON_D0SPL BIT(16) /* RW */ 127 #define MSDC_IOCON_D1SPL BIT(17) /* RW */ 128 #define MSDC_IOCON_D2SPL BIT(18) /* RW */ 129 #define MSDC_IOCON_D3SPL BIT(19) /* RW */ 130 #define MSDC_IOCON_D4SPL BIT(20) /* RW */ 131 #define MSDC_IOCON_D5SPL BIT(21) /* RW */ 132 #define MSDC_IOCON_D6SPL BIT(22) /* RW */ 133 #define MSDC_IOCON_D7SPL BIT(23) /* RW */ 134 #define MSDC_IOCON_RISCSZ GENMASK(25, 24) /* RW */ 135 136 /* MSDC_PS mask */ 137 #define MSDC_PS_CDEN BIT(0) /* RW */ 138 #define MSDC_PS_CDSTS BIT(1) /* R */ 139 #define MSDC_PS_CDDEBOUNCE GENMASK(15, 12) /* RW */ 140 #define MSDC_PS_DAT GENMASK(23, 16) /* R */ 141 #define MSDC_PS_DATA1 BIT(17) /* R */ 142 #define MSDC_PS_CMD BIT(24) /* R */ 143 #define MSDC_PS_WP BIT(31) /* R */ 144 145 /* MSDC_INT mask */ 146 #define MSDC_INT_MMCIRQ BIT(0) /* W1C */ 147 #define MSDC_INT_CDSC BIT(1) /* W1C */ 148 #define MSDC_INT_ACMDRDY BIT(3) /* W1C */ 149 #define MSDC_INT_ACMDTMO BIT(4) /* W1C */ 150 #define MSDC_INT_ACMDCRCERR BIT(5) /* W1C */ 151 #define MSDC_INT_DMAQ_EMPTY BIT(6) /* W1C */ 152 #define MSDC_INT_SDIOIRQ BIT(7) /* W1C */ 153 #define MSDC_INT_CMDRDY BIT(8) /* W1C */ 154 #define MSDC_INT_CMDTMO BIT(9) /* W1C */ 155 #define MSDC_INT_RSPCRCERR BIT(10) /* W1C */ 156 #define MSDC_INT_CSTA BIT(11) /* R */ 157 #define MSDC_INT_XFER_COMPL BIT(12) /* W1C */ 158 #define MSDC_INT_DXFER_DONE BIT(13) /* W1C */ 159 #define MSDC_INT_DATTMO BIT(14) /* W1C */ 160 #define MSDC_INT_DATCRCERR BIT(15) /* W1C */ 161 #define MSDC_INT_ACMD19_DONE BIT(16) /* W1C */ 162 #define MSDC_INT_DMA_BDCSERR BIT(17) /* W1C */ 163 #define MSDC_INT_DMA_GPDCSERR BIT(18) /* W1C */ 164 #define MSDC_INT_DMA_PROTECT BIT(19) /* W1C */ 165 #define MSDC_INT_CMDQ BIT(28) /* W1C */ 166 167 /* MSDC_INTEN mask */ 168 #define MSDC_INTEN_MMCIRQ BIT(0) /* RW */ 169 #define MSDC_INTEN_CDSC BIT(1) /* RW */ 170 #define MSDC_INTEN_ACMDRDY BIT(3) /* RW */ 171 #define MSDC_INTEN_ACMDTMO BIT(4) /* RW */ 172 #define MSDC_INTEN_ACMDCRCERR BIT(5) /* RW */ 173 #define MSDC_INTEN_DMAQ_EMPTY BIT(6) /* RW */ 174 #define MSDC_INTEN_SDIOIRQ BIT(7) /* RW */ 175 #define MSDC_INTEN_CMDRDY BIT(8) /* RW */ 176 #define MSDC_INTEN_CMDTMO BIT(9) /* RW */ 177 #define MSDC_INTEN_RSPCRCERR BIT(10) /* RW */ 178 #define MSDC_INTEN_CSTA BIT(11) /* RW */ 179 #define MSDC_INTEN_XFER_COMPL BIT(12) /* RW */ 180 #define MSDC_INTEN_DXFER_DONE BIT(13) /* RW */ 181 #define MSDC_INTEN_DATTMO BIT(14) /* RW */ 182 #define MSDC_INTEN_DATCRCERR BIT(15) /* RW */ 183 #define MSDC_INTEN_ACMD19_DONE BIT(16) /* RW */ 184 #define MSDC_INTEN_DMA_BDCSERR BIT(17) /* RW */ 185 #define MSDC_INTEN_DMA_GPDCSERR BIT(18) /* RW */ 186 #define MSDC_INTEN_DMA_PROTECT BIT(19) /* RW */ 187 188 /* MSDC_FIFOCS mask */ 189 #define MSDC_FIFOCS_RXCNT GENMASK(7, 0) /* R */ 190 #define MSDC_FIFOCS_TXCNT GENMASK(23, 16) /* R */ 191 #define MSDC_FIFOCS_CLR BIT(31) /* RW */ 192 193 /* SDC_CFG mask */ 194 #define SDC_CFG_SDIOINTWKUP BIT(0) /* RW */ 195 #define SDC_CFG_INSWKUP BIT(1) /* RW */ 196 #define SDC_CFG_WRDTOC GENMASK(14, 2) /* RW */ 197 #define SDC_CFG_BUSWIDTH GENMASK(17, 16) /* RW */ 198 #define SDC_CFG_SDIO BIT(19) /* RW */ 199 #define SDC_CFG_SDIOIDE BIT(20) /* RW */ 200 #define SDC_CFG_INTATGAP BIT(21) /* RW */ 201 #define SDC_CFG_DTOC GENMASK(31, 24) /* RW */ 202 203 /* SDC_STS mask */ 204 #define SDC_STS_SDCBUSY BIT(0) /* RW */ 205 #define SDC_STS_CMDBUSY BIT(1) /* RW */ 206 #define SDC_STS_SWR_COMPL BIT(31) /* RW */ 207 208 #define SDC_DAT1_IRQ_TRIGGER BIT(19) /* RW */ 209 /* SDC_ADV_CFG0 mask */ 210 #define SDC_RX_ENHANCE_EN BIT(20) /* RW */ 211 212 /* DMA_SA_H4BIT mask */ 213 #define DMA_ADDR_HIGH_4BIT GENMASK(3, 0) /* RW */ 214 215 /* MSDC_DMA_CTRL mask */ 216 #define MSDC_DMA_CTRL_START BIT(0) /* W */ 217 #define MSDC_DMA_CTRL_STOP BIT(1) /* W */ 218 #define MSDC_DMA_CTRL_RESUME BIT(2) /* W */ 219 #define MSDC_DMA_CTRL_MODE BIT(8) /* RW */ 220 #define MSDC_DMA_CTRL_LASTBUF BIT(10) /* RW */ 221 #define MSDC_DMA_CTRL_BRUSTSZ GENMASK(14, 12) /* RW */ 222 223 /* MSDC_DMA_CFG mask */ 224 #define MSDC_DMA_CFG_STS BIT(0) /* R */ 225 #define MSDC_DMA_CFG_DECSEN BIT(1) /* RW */ 226 #define MSDC_DMA_CFG_AHBHPROT2 BIT(9) /* RW */ 227 #define MSDC_DMA_CFG_ACTIVEEN BIT(13) /* RW */ 228 #define MSDC_DMA_CFG_CS12B16B BIT(16) /* RW */ 229 230 /* MSDC_PATCH_BIT mask */ 231 #define MSDC_PATCH_BIT_ODDSUPP BIT(1) /* RW */ 232 #define MSDC_INT_DAT_LATCH_CK_SEL GENMASK(9, 7) 233 #define MSDC_CKGEN_MSDC_DLY_SEL GENMASK(14, 10) 234 #define MSDC_PATCH_BIT_IODSSEL BIT(16) /* RW */ 235 #define MSDC_PATCH_BIT_IOINTSEL BIT(17) /* RW */ 236 #define MSDC_PATCH_BIT_BUSYDLY GENMASK(21, 18) /* RW */ 237 #define MSDC_PATCH_BIT_WDOD GENMASK(25, 22) /* RW */ 238 #define MSDC_PATCH_BIT_IDRTSEL BIT(26) /* RW */ 239 #define MSDC_PATCH_BIT_CMDFSEL BIT(27) /* RW */ 240 #define MSDC_PATCH_BIT_INTDLSEL BIT(28) /* RW */ 241 #define MSDC_PATCH_BIT_SPCPUSH BIT(29) /* RW */ 242 #define MSDC_PATCH_BIT_DECRCTMO BIT(30) /* RW */ 243 244 #define MSDC_PATCH_BIT1_CMDTA GENMASK(5, 3) /* RW */ 245 #define MSDC_PB1_BUSY_CHECK_SEL BIT(7) /* RW */ 246 #define MSDC_PATCH_BIT1_STOP_DLY GENMASK(11, 8) /* RW */ 247 248 #define MSDC_PATCH_BIT2_CFGRESP BIT(15) /* RW */ 249 #define MSDC_PATCH_BIT2_CFGCRCSTS BIT(28) /* RW */ 250 #define MSDC_PB2_SUPPORT_64G BIT(1) /* RW */ 251 #define MSDC_PB2_RESPWAIT GENMASK(3, 2) /* RW */ 252 #define MSDC_PB2_RESPSTSENSEL GENMASK(18, 16) /* RW */ 253 #define MSDC_PB2_CRCSTSENSEL GENMASK(31, 29) /* RW */ 254 255 #define MSDC_PAD_TUNE_DATWRDLY GENMASK(4, 0) /* RW */ 256 #define MSDC_PAD_TUNE_DATRRDLY GENMASK(12, 8) /* RW */ 257 #define MSDC_PAD_TUNE_CMDRDLY GENMASK(20, 16) /* RW */ 258 #define MSDC_PAD_TUNE_CMDRRDLY GENMASK(26, 22) /* RW */ 259 #define MSDC_PAD_TUNE_CLKTDLY GENMASK(31, 27) /* RW */ 260 #define MSDC_PAD_TUNE_RXDLYSEL BIT(15) /* RW */ 261 #define MSDC_PAD_TUNE_RD_SEL BIT(13) /* RW */ 262 #define MSDC_PAD_TUNE_CMD_SEL BIT(21) /* RW */ 263 264 #define PAD_DS_TUNE_DLY_SEL BIT(0) /* RW */ 265 #define PAD_DS_TUNE_DLY1 GENMASK(6, 2) /* RW */ 266 #define PAD_DS_TUNE_DLY2 GENMASK(11, 7) /* RW */ 267 #define PAD_DS_TUNE_DLY3 GENMASK(16, 12) /* RW */ 268 269 #define PAD_CMD_TUNE_RX_DLY3 GENMASK(5, 1) /* RW */ 270 271 /* EMMC51_CFG0 mask */ 272 #define CMDQ_RDAT_CNT GENMASK(21, 12) /* RW */ 273 274 #define EMMC50_CFG_PADCMD_LATCHCK BIT(0) /* RW */ 275 #define EMMC50_CFG_CRCSTS_EDGE BIT(3) /* RW */ 276 #define EMMC50_CFG_CFCSTS_SEL BIT(4) /* RW */ 277 #define EMMC50_CFG_CMD_RESP_SEL BIT(9) /* RW */ 278 279 /* EMMC50_CFG1 mask */ 280 #define EMMC50_CFG1_DS_CFG BIT(28) /* RW */ 281 282 #define EMMC50_CFG3_OUTS_WR GENMASK(4, 0) /* RW */ 283 284 #define SDC_FIFO_CFG_WRVALIDSEL BIT(24) /* RW */ 285 #define SDC_FIFO_CFG_RDVALIDSEL BIT(25) /* RW */ 286 287 /* CQHCI_SETTING */ 288 #define CQHCI_RD_CMD_WND_SEL BIT(14) /* RW */ 289 #define CQHCI_WR_CMD_WND_SEL BIT(15) /* RW */ 290 291 /* EMMC_TOP_CONTROL mask */ 292 #define PAD_RXDLY_SEL BIT(0) /* RW */ 293 #define DELAY_EN BIT(1) /* RW */ 294 #define PAD_DAT_RD_RXDLY2 GENMASK(6, 2) /* RW */ 295 #define PAD_DAT_RD_RXDLY GENMASK(11, 7) /* RW */ 296 #define PAD_DAT_RD_RXDLY2_SEL BIT(12) /* RW */ 297 #define PAD_DAT_RD_RXDLY_SEL BIT(13) /* RW */ 298 #define DATA_K_VALUE_SEL BIT(14) /* RW */ 299 #define SDC_RX_ENH_EN BIT(15) /* TW */ 300 301 /* EMMC_TOP_CMD mask */ 302 #define PAD_CMD_RXDLY2 GENMASK(4, 0) /* RW */ 303 #define PAD_CMD_RXDLY GENMASK(9, 5) /* RW */ 304 #define PAD_CMD_RD_RXDLY2_SEL BIT(10) /* RW */ 305 #define PAD_CMD_RD_RXDLY_SEL BIT(11) /* RW */ 306 #define PAD_CMD_TX_DLY GENMASK(16, 12) /* RW */ 307 308 /* EMMC50_PAD_DS_TUNE mask */ 309 #define PAD_DS_DLY_SEL BIT(16) /* RW */ 310 #define PAD_DS_DLY1 GENMASK(14, 10) /* RW */ 311 #define PAD_DS_DLY3 GENMASK(4, 0) /* RW */ 312 313 #define REQ_CMD_EIO BIT(0) 314 #define REQ_CMD_TMO BIT(1) 315 #define REQ_DAT_ERR BIT(2) 316 #define REQ_STOP_EIO BIT(3) 317 #define REQ_STOP_TMO BIT(4) 318 #define REQ_CMD_BUSY BIT(5) 319 320 #define MSDC_PREPARE_FLAG BIT(0) 321 #define MSDC_ASYNC_FLAG BIT(1) 322 #define MSDC_MMAP_FLAG BIT(2) 323 324 #define MTK_MMC_AUTOSUSPEND_DELAY 50 325 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 326 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 327 328 #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */ 329 330 #define PAD_DELAY_MAX 32 /* PAD delay cells */ 331 /*--------------------------------------------------------------------------*/ 332 /* Descriptor Structure */ 333 /*--------------------------------------------------------------------------*/ 334 struct mt_gpdma_desc { 335 u32 gpd_info; 336 #define GPDMA_DESC_HWO BIT(0) 337 #define GPDMA_DESC_BDP BIT(1) 338 #define GPDMA_DESC_CHECKSUM GENMASK(15, 8) 339 #define GPDMA_DESC_INT BIT(16) 340 #define GPDMA_DESC_NEXT_H4 GENMASK(27, 24) 341 #define GPDMA_DESC_PTR_H4 GENMASK(31, 28) 342 u32 next; 343 u32 ptr; 344 u32 gpd_data_len; 345 #define GPDMA_DESC_BUFLEN GENMASK(15, 0) 346 #define GPDMA_DESC_EXTLEN GENMASK(23, 16) 347 u32 arg; 348 u32 blknum; 349 u32 cmd; 350 }; 351 352 struct mt_bdma_desc { 353 u32 bd_info; 354 #define BDMA_DESC_EOL BIT(0) 355 #define BDMA_DESC_CHECKSUM GENMASK(15, 8) 356 #define BDMA_DESC_BLKPAD BIT(17) 357 #define BDMA_DESC_DWPAD BIT(18) 358 #define BDMA_DESC_NEXT_H4 GENMASK(27, 24) 359 #define BDMA_DESC_PTR_H4 GENMASK(31, 28) 360 u32 next; 361 u32 ptr; 362 u32 bd_data_len; 363 #define BDMA_DESC_BUFLEN GENMASK(15, 0) 364 #define BDMA_DESC_BUFLEN_EXT GENMASK(23, 0) 365 }; 366 367 struct msdc_dma { 368 struct scatterlist *sg; /* I/O scatter list */ 369 struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 370 struct mt_bdma_desc *bd; /* pointer to bd array */ 371 dma_addr_t gpd_addr; /* the physical address of gpd array */ 372 dma_addr_t bd_addr; /* the physical address of bd array */ 373 }; 374 375 struct msdc_save_para { 376 u32 msdc_cfg; 377 u32 iocon; 378 u32 sdc_cfg; 379 u32 pad_tune; 380 u32 patch_bit0; 381 u32 patch_bit1; 382 u32 patch_bit2; 383 u32 pad_ds_tune; 384 u32 pad_cmd_tune; 385 u32 emmc50_cfg0; 386 u32 emmc50_cfg3; 387 u32 sdc_fifo_cfg; 388 u32 emmc_top_control; 389 u32 emmc_top_cmd; 390 u32 emmc50_pad_ds_tune; 391 }; 392 393 struct mtk_mmc_compatible { 394 u8 clk_div_bits; 395 bool recheck_sdio_irq; 396 bool hs400_tune; /* only used for MT8173 */ 397 u32 pad_tune_reg; 398 bool async_fifo; 399 bool data_tune; 400 bool busy_check; 401 bool stop_clk_fix; 402 bool enhance_rx; 403 bool support_64g; 404 bool use_internal_cd; 405 }; 406 407 struct msdc_tune_para { 408 u32 iocon; 409 u32 pad_tune; 410 u32 pad_cmd_tune; 411 u32 emmc_top_control; 412 u32 emmc_top_cmd; 413 }; 414 415 struct msdc_delay_phase { 416 u8 maxlen; 417 u8 start; 418 u8 final_phase; 419 }; 420 421 struct msdc_host { 422 struct device *dev; 423 const struct mtk_mmc_compatible *dev_comp; 424 int cmd_rsp; 425 426 spinlock_t lock; 427 struct mmc_request *mrq; 428 struct mmc_command *cmd; 429 struct mmc_data *data; 430 int error; 431 432 void __iomem *base; /* host base address */ 433 void __iomem *top_base; /* host top register base address */ 434 435 struct msdc_dma dma; /* dma channel */ 436 u64 dma_mask; 437 438 u32 timeout_ns; /* data timeout ns */ 439 u32 timeout_clks; /* data timeout clks */ 440 441 struct pinctrl *pinctrl; 442 struct pinctrl_state *pins_default; 443 struct pinctrl_state *pins_uhs; 444 struct pinctrl_state *pins_eint; 445 struct delayed_work req_timeout; 446 int irq; /* host interrupt */ 447 int eint_irq; /* interrupt from sdio device for waking up system */ 448 struct reset_control *reset; 449 450 struct clk *src_clk; /* msdc source clock */ 451 struct clk *h_clk; /* msdc h_clk */ 452 struct clk *bus_clk; /* bus clock which used to access register */ 453 struct clk *src_clk_cg; /* msdc source clock control gate */ 454 struct clk *sys_clk_cg; /* msdc subsys clock control gate */ 455 struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS]; 456 u32 mclk; /* mmc subsystem clock frequency */ 457 u32 src_clk_freq; /* source clock frequency */ 458 unsigned char timing; 459 bool vqmmc_enabled; 460 u32 latch_ck; 461 u32 hs400_ds_delay; 462 u32 hs400_ds_dly3; 463 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 464 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 465 bool hs400_cmd_resp_sel_rising; 466 /* cmd response sample selection for HS400 */ 467 bool hs400_mode; /* current eMMC will run at hs400 mode */ 468 bool hs400_tuning; /* hs400 mode online tuning */ 469 bool internal_cd; /* Use internal card-detect logic */ 470 bool cqhci; /* support eMMC hw cmdq */ 471 struct msdc_save_para save_para; /* used when gate HCLK */ 472 struct msdc_tune_para def_tune_para; /* default tune setting */ 473 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 474 struct cqhci_host *cq_host; 475 }; 476 477 static const struct mtk_mmc_compatible mt2701_compat = { 478 .clk_div_bits = 12, 479 .recheck_sdio_irq = true, 480 .hs400_tune = false, 481 .pad_tune_reg = MSDC_PAD_TUNE0, 482 .async_fifo = true, 483 .data_tune = true, 484 .busy_check = false, 485 .stop_clk_fix = false, 486 .enhance_rx = false, 487 .support_64g = false, 488 }; 489 490 static const struct mtk_mmc_compatible mt2712_compat = { 491 .clk_div_bits = 12, 492 .recheck_sdio_irq = false, 493 .hs400_tune = false, 494 .pad_tune_reg = MSDC_PAD_TUNE0, 495 .async_fifo = true, 496 .data_tune = true, 497 .busy_check = true, 498 .stop_clk_fix = true, 499 .enhance_rx = true, 500 .support_64g = true, 501 }; 502 503 static const struct mtk_mmc_compatible mt6779_compat = { 504 .clk_div_bits = 12, 505 .recheck_sdio_irq = false, 506 .hs400_tune = false, 507 .pad_tune_reg = MSDC_PAD_TUNE0, 508 .async_fifo = true, 509 .data_tune = true, 510 .busy_check = true, 511 .stop_clk_fix = true, 512 .enhance_rx = true, 513 .support_64g = true, 514 }; 515 516 static const struct mtk_mmc_compatible mt6795_compat = { 517 .clk_div_bits = 8, 518 .recheck_sdio_irq = false, 519 .hs400_tune = true, 520 .pad_tune_reg = MSDC_PAD_TUNE, 521 .async_fifo = false, 522 .data_tune = false, 523 .busy_check = false, 524 .stop_clk_fix = false, 525 .enhance_rx = false, 526 .support_64g = false, 527 }; 528 529 static const struct mtk_mmc_compatible mt7620_compat = { 530 .clk_div_bits = 8, 531 .recheck_sdio_irq = true, 532 .hs400_tune = false, 533 .pad_tune_reg = MSDC_PAD_TUNE, 534 .async_fifo = false, 535 .data_tune = false, 536 .busy_check = false, 537 .stop_clk_fix = false, 538 .enhance_rx = false, 539 .use_internal_cd = true, 540 }; 541 542 static const struct mtk_mmc_compatible mt7622_compat = { 543 .clk_div_bits = 12, 544 .recheck_sdio_irq = true, 545 .hs400_tune = false, 546 .pad_tune_reg = MSDC_PAD_TUNE0, 547 .async_fifo = true, 548 .data_tune = true, 549 .busy_check = true, 550 .stop_clk_fix = true, 551 .enhance_rx = true, 552 .support_64g = false, 553 }; 554 555 static const struct mtk_mmc_compatible mt8135_compat = { 556 .clk_div_bits = 8, 557 .recheck_sdio_irq = true, 558 .hs400_tune = false, 559 .pad_tune_reg = MSDC_PAD_TUNE, 560 .async_fifo = false, 561 .data_tune = false, 562 .busy_check = false, 563 .stop_clk_fix = false, 564 .enhance_rx = false, 565 .support_64g = false, 566 }; 567 568 static const struct mtk_mmc_compatible mt8173_compat = { 569 .clk_div_bits = 8, 570 .recheck_sdio_irq = true, 571 .hs400_tune = true, 572 .pad_tune_reg = MSDC_PAD_TUNE, 573 .async_fifo = false, 574 .data_tune = false, 575 .busy_check = false, 576 .stop_clk_fix = false, 577 .enhance_rx = false, 578 .support_64g = false, 579 }; 580 581 static const struct mtk_mmc_compatible mt8183_compat = { 582 .clk_div_bits = 12, 583 .recheck_sdio_irq = false, 584 .hs400_tune = false, 585 .pad_tune_reg = MSDC_PAD_TUNE0, 586 .async_fifo = true, 587 .data_tune = true, 588 .busy_check = true, 589 .stop_clk_fix = true, 590 .enhance_rx = true, 591 .support_64g = true, 592 }; 593 594 static const struct mtk_mmc_compatible mt8516_compat = { 595 .clk_div_bits = 12, 596 .recheck_sdio_irq = true, 597 .hs400_tune = false, 598 .pad_tune_reg = MSDC_PAD_TUNE0, 599 .async_fifo = true, 600 .data_tune = true, 601 .busy_check = true, 602 .stop_clk_fix = true, 603 }; 604 605 static const struct of_device_id msdc_of_ids[] = { 606 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, 607 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, 608 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, 609 { .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat}, 610 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, 611 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, 612 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, 613 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, 614 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, 615 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, 616 617 {} 618 }; 619 MODULE_DEVICE_TABLE(of, msdc_of_ids); 620 621 static void sdr_set_bits(void __iomem *reg, u32 bs) 622 { 623 u32 val = readl(reg); 624 625 val |= bs; 626 writel(val, reg); 627 } 628 629 static void sdr_clr_bits(void __iomem *reg, u32 bs) 630 { 631 u32 val = readl(reg); 632 633 val &= ~bs; 634 writel(val, reg); 635 } 636 637 static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 638 { 639 unsigned int tv = readl(reg); 640 641 tv &= ~field; 642 tv |= ((val) << (ffs((unsigned int)field) - 1)); 643 writel(tv, reg); 644 } 645 646 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 647 { 648 unsigned int tv = readl(reg); 649 650 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 651 } 652 653 static void msdc_reset_hw(struct msdc_host *host) 654 { 655 u32 val; 656 657 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 658 readl_poll_timeout(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0); 659 660 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 661 readl_poll_timeout(host->base + MSDC_FIFOCS, val, 662 !(val & MSDC_FIFOCS_CLR), 0, 0); 663 664 val = readl(host->base + MSDC_INT); 665 writel(val, host->base + MSDC_INT); 666 } 667 668 static void msdc_cmd_next(struct msdc_host *host, 669 struct mmc_request *mrq, struct mmc_command *cmd); 670 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb); 671 672 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 673 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 674 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 675 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 676 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 677 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 678 679 static u8 msdc_dma_calcs(u8 *buf, u32 len) 680 { 681 u32 i, sum = 0; 682 683 for (i = 0; i < len; i++) 684 sum += buf[i]; 685 return 0xff - (u8) sum; 686 } 687 688 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 689 struct mmc_data *data) 690 { 691 unsigned int j, dma_len; 692 dma_addr_t dma_address; 693 u32 dma_ctrl; 694 struct scatterlist *sg; 695 struct mt_gpdma_desc *gpd; 696 struct mt_bdma_desc *bd; 697 698 sg = data->sg; 699 700 gpd = dma->gpd; 701 bd = dma->bd; 702 703 /* modify gpd */ 704 gpd->gpd_info |= GPDMA_DESC_HWO; 705 gpd->gpd_info |= GPDMA_DESC_BDP; 706 /* need to clear first. use these bits to calc checksum */ 707 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 708 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 709 710 /* modify bd */ 711 for_each_sg(data->sg, sg, data->sg_count, j) { 712 dma_address = sg_dma_address(sg); 713 dma_len = sg_dma_len(sg); 714 715 /* init bd */ 716 bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 717 bd[j].bd_info &= ~BDMA_DESC_DWPAD; 718 bd[j].ptr = lower_32_bits(dma_address); 719 if (host->dev_comp->support_64g) { 720 bd[j].bd_info &= ~BDMA_DESC_PTR_H4; 721 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf) 722 << 28; 723 } 724 725 if (host->dev_comp->support_64g) { 726 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT; 727 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT); 728 } else { 729 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 730 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 731 } 732 733 if (j == data->sg_count - 1) /* the last bd */ 734 bd[j].bd_info |= BDMA_DESC_EOL; 735 else 736 bd[j].bd_info &= ~BDMA_DESC_EOL; 737 738 /* checksume need to clear first */ 739 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 740 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 741 } 742 743 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 744 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 745 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 746 dma_ctrl |= (MSDC_BURST_64B << 12 | BIT(8)); 747 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 748 if (host->dev_comp->support_64g) 749 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, 750 upper_32_bits(dma->gpd_addr) & 0xf); 751 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); 752 } 753 754 static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data) 755 { 756 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 757 data->host_cookie |= MSDC_PREPARE_FLAG; 758 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 759 mmc_get_dma_dir(data)); 760 } 761 } 762 763 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data) 764 { 765 if (data->host_cookie & MSDC_ASYNC_FLAG) 766 return; 767 768 if (data->host_cookie & MSDC_PREPARE_FLAG) { 769 dma_unmap_sg(host->dev, data->sg, data->sg_len, 770 mmc_get_dma_dir(data)); 771 data->host_cookie &= ~MSDC_PREPARE_FLAG; 772 } 773 } 774 775 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) 776 { 777 struct mmc_host *mmc = mmc_from_priv(host); 778 u64 timeout, clk_ns; 779 u32 mode = 0; 780 781 if (mmc->actual_clock == 0) { 782 timeout = 0; 783 } else { 784 clk_ns = 1000000000ULL; 785 do_div(clk_ns, mmc->actual_clock); 786 timeout = ns + clk_ns - 1; 787 do_div(timeout, clk_ns); 788 timeout += clks; 789 /* in 1048576 sclk cycle unit */ 790 timeout = DIV_ROUND_UP(timeout, BIT(20)); 791 if (host->dev_comp->clk_div_bits == 8) 792 sdr_get_field(host->base + MSDC_CFG, 793 MSDC_CFG_CKMOD, &mode); 794 else 795 sdr_get_field(host->base + MSDC_CFG, 796 MSDC_CFG_CKMOD_EXTRA, &mode); 797 /*DDR mode will double the clk cycles for data timeout */ 798 timeout = mode >= 2 ? timeout * 2 : timeout; 799 timeout = timeout > 1 ? timeout - 1 : 0; 800 } 801 return timeout; 802 } 803 804 /* clock control primitives */ 805 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) 806 { 807 u64 timeout; 808 809 host->timeout_ns = ns; 810 host->timeout_clks = clks; 811 812 timeout = msdc_timeout_cal(host, ns, clks); 813 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 814 (u32)(timeout > 255 ? 255 : timeout)); 815 } 816 817 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) 818 { 819 u64 timeout; 820 821 timeout = msdc_timeout_cal(host, ns, clks); 822 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, 823 (u32)(timeout > 8191 ? 8191 : timeout)); 824 } 825 826 static void msdc_gate_clock(struct msdc_host *host) 827 { 828 clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); 829 clk_disable_unprepare(host->src_clk_cg); 830 clk_disable_unprepare(host->src_clk); 831 clk_disable_unprepare(host->bus_clk); 832 clk_disable_unprepare(host->h_clk); 833 } 834 835 static int msdc_ungate_clock(struct msdc_host *host) 836 { 837 u32 val; 838 int ret; 839 840 clk_prepare_enable(host->h_clk); 841 clk_prepare_enable(host->bus_clk); 842 clk_prepare_enable(host->src_clk); 843 clk_prepare_enable(host->src_clk_cg); 844 ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); 845 if (ret) { 846 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); 847 return ret; 848 } 849 850 return readl_poll_timeout(host->base + MSDC_CFG, val, 851 (val & MSDC_CFG_CKSTB), 1, 20000); 852 } 853 854 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 855 { 856 struct mmc_host *mmc = mmc_from_priv(host); 857 u32 mode; 858 u32 flags; 859 u32 div; 860 u32 sclk; 861 u32 tune_reg = host->dev_comp->pad_tune_reg; 862 u32 val; 863 864 if (!hz) { 865 dev_dbg(host->dev, "set mclk to 0\n"); 866 host->mclk = 0; 867 mmc->actual_clock = 0; 868 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 869 return; 870 } 871 872 flags = readl(host->base + MSDC_INTEN); 873 sdr_clr_bits(host->base + MSDC_INTEN, flags); 874 if (host->dev_comp->clk_div_bits == 8) 875 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 876 else 877 sdr_clr_bits(host->base + MSDC_CFG, 878 MSDC_CFG_HS400_CK_MODE_EXTRA); 879 if (timing == MMC_TIMING_UHS_DDR50 || 880 timing == MMC_TIMING_MMC_DDR52 || 881 timing == MMC_TIMING_MMC_HS400) { 882 if (timing == MMC_TIMING_MMC_HS400) 883 mode = 0x3; 884 else 885 mode = 0x2; /* ddr mode and use divisor */ 886 887 if (hz >= (host->src_clk_freq >> 2)) { 888 div = 0; /* mean div = 1/4 */ 889 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 890 } else { 891 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 892 sclk = (host->src_clk_freq >> 2) / div; 893 div = (div >> 1); 894 } 895 896 if (timing == MMC_TIMING_MMC_HS400 && 897 hz >= (host->src_clk_freq >> 1)) { 898 if (host->dev_comp->clk_div_bits == 8) 899 sdr_set_bits(host->base + MSDC_CFG, 900 MSDC_CFG_HS400_CK_MODE); 901 else 902 sdr_set_bits(host->base + MSDC_CFG, 903 MSDC_CFG_HS400_CK_MODE_EXTRA); 904 sclk = host->src_clk_freq >> 1; 905 div = 0; /* div is ignore when bit18 is set */ 906 } 907 } else if (hz >= host->src_clk_freq) { 908 mode = 0x1; /* no divisor */ 909 div = 0; 910 sclk = host->src_clk_freq; 911 } else { 912 mode = 0x0; /* use divisor */ 913 if (hz >= (host->src_clk_freq >> 1)) { 914 div = 0; /* mean div = 1/2 */ 915 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 916 } else { 917 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 918 sclk = (host->src_clk_freq >> 2) / div; 919 } 920 } 921 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 922 923 clk_disable_unprepare(host->src_clk_cg); 924 if (host->dev_comp->clk_div_bits == 8) 925 sdr_set_field(host->base + MSDC_CFG, 926 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 927 (mode << 8) | div); 928 else 929 sdr_set_field(host->base + MSDC_CFG, 930 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, 931 (mode << 12) | div); 932 933 clk_prepare_enable(host->src_clk_cg); 934 readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0); 935 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 936 mmc->actual_clock = sclk; 937 host->mclk = hz; 938 host->timing = timing; 939 /* need because clk changed. */ 940 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 941 sdr_set_bits(host->base + MSDC_INTEN, flags); 942 943 /* 944 * mmc_select_hs400() will drop to 50Mhz and High speed mode, 945 * tune result of hs200/200Mhz is not suitable for 50Mhz 946 */ 947 if (mmc->actual_clock <= 52000000) { 948 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 949 if (host->top_base) { 950 writel(host->def_tune_para.emmc_top_control, 951 host->top_base + EMMC_TOP_CONTROL); 952 writel(host->def_tune_para.emmc_top_cmd, 953 host->top_base + EMMC_TOP_CMD); 954 } else { 955 writel(host->def_tune_para.pad_tune, 956 host->base + tune_reg); 957 } 958 } else { 959 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 960 writel(host->saved_tune_para.pad_cmd_tune, 961 host->base + PAD_CMD_TUNE); 962 if (host->top_base) { 963 writel(host->saved_tune_para.emmc_top_control, 964 host->top_base + EMMC_TOP_CONTROL); 965 writel(host->saved_tune_para.emmc_top_cmd, 966 host->top_base + EMMC_TOP_CMD); 967 } else { 968 writel(host->saved_tune_para.pad_tune, 969 host->base + tune_reg); 970 } 971 } 972 973 if (timing == MMC_TIMING_MMC_HS400 && 974 host->dev_comp->hs400_tune) 975 sdr_set_field(host->base + tune_reg, 976 MSDC_PAD_TUNE_CMDRRDLY, 977 host->hs400_cmd_int_delay); 978 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock, 979 timing); 980 } 981 982 static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 983 struct mmc_command *cmd) 984 { 985 u32 resp; 986 987 switch (mmc_resp_type(cmd)) { 988 /* Actually, R1, R5, R6, R7 are the same */ 989 case MMC_RSP_R1: 990 resp = 0x1; 991 break; 992 case MMC_RSP_R1B: 993 resp = 0x7; 994 break; 995 case MMC_RSP_R2: 996 resp = 0x2; 997 break; 998 case MMC_RSP_R3: 999 resp = 0x3; 1000 break; 1001 case MMC_RSP_NONE: 1002 default: 1003 resp = 0x0; 1004 break; 1005 } 1006 1007 return resp; 1008 } 1009 1010 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 1011 struct mmc_request *mrq, struct mmc_command *cmd) 1012 { 1013 struct mmc_host *mmc = mmc_from_priv(host); 1014 /* rawcmd : 1015 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 1016 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 1017 */ 1018 u32 opcode = cmd->opcode; 1019 u32 resp = msdc_cmd_find_resp(host, cmd); 1020 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 1021 1022 host->cmd_rsp = resp; 1023 1024 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 1025 opcode == MMC_STOP_TRANSMISSION) 1026 rawcmd |= BIT(14); 1027 else if (opcode == SD_SWITCH_VOLTAGE) 1028 rawcmd |= BIT(30); 1029 else if (opcode == SD_APP_SEND_SCR || 1030 opcode == SD_APP_SEND_NUM_WR_BLKS || 1031 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 1032 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 1033 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 1034 rawcmd |= BIT(11); 1035 1036 if (cmd->data) { 1037 struct mmc_data *data = cmd->data; 1038 1039 if (mmc_op_multi(opcode)) { 1040 if (mmc_card_mmc(mmc->card) && mrq->sbc && 1041 !(mrq->sbc->arg & 0xFFFF0000)) 1042 rawcmd |= BIT(29); /* AutoCMD23 */ 1043 } 1044 1045 rawcmd |= ((data->blksz & 0xFFF) << 16); 1046 if (data->flags & MMC_DATA_WRITE) 1047 rawcmd |= BIT(13); 1048 if (data->blocks > 1) 1049 rawcmd |= BIT(12); 1050 else 1051 rawcmd |= BIT(11); 1052 /* Always use dma mode */ 1053 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 1054 1055 if (host->timeout_ns != data->timeout_ns || 1056 host->timeout_clks != data->timeout_clks) 1057 msdc_set_timeout(host, data->timeout_ns, 1058 data->timeout_clks); 1059 1060 writel(data->blocks, host->base + SDC_BLK_NUM); 1061 } 1062 return rawcmd; 1063 } 1064 1065 static void msdc_start_data(struct msdc_host *host, struct mmc_command *cmd, 1066 struct mmc_data *data) 1067 { 1068 bool read; 1069 1070 WARN_ON(host->data); 1071 host->data = data; 1072 read = data->flags & MMC_DATA_READ; 1073 1074 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1075 msdc_dma_setup(host, &host->dma, data); 1076 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 1077 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 1078 dev_dbg(host->dev, "DMA start\n"); 1079 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 1080 __func__, cmd->opcode, data->blocks, read); 1081 } 1082 1083 static int msdc_auto_cmd_done(struct msdc_host *host, int events, 1084 struct mmc_command *cmd) 1085 { 1086 u32 *rsp = cmd->resp; 1087 1088 rsp[0] = readl(host->base + SDC_ACMD_RESP); 1089 1090 if (events & MSDC_INT_ACMDRDY) { 1091 cmd->error = 0; 1092 } else { 1093 msdc_reset_hw(host); 1094 if (events & MSDC_INT_ACMDCRCERR) { 1095 cmd->error = -EILSEQ; 1096 host->error |= REQ_STOP_EIO; 1097 } else if (events & MSDC_INT_ACMDTMO) { 1098 cmd->error = -ETIMEDOUT; 1099 host->error |= REQ_STOP_TMO; 1100 } 1101 dev_err(host->dev, 1102 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 1103 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 1104 } 1105 return cmd->error; 1106 } 1107 1108 /* 1109 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost 1110 * 1111 * Host controller may lost interrupt in some special case. 1112 * Add SDIO irq recheck mechanism to make sure all interrupts 1113 * can be processed immediately 1114 */ 1115 static void msdc_recheck_sdio_irq(struct msdc_host *host) 1116 { 1117 struct mmc_host *mmc = mmc_from_priv(host); 1118 u32 reg_int, reg_inten, reg_ps; 1119 1120 if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1121 reg_inten = readl(host->base + MSDC_INTEN); 1122 if (reg_inten & MSDC_INTEN_SDIOIRQ) { 1123 reg_int = readl(host->base + MSDC_INT); 1124 reg_ps = readl(host->base + MSDC_PS); 1125 if (!(reg_int & MSDC_INT_SDIOIRQ || 1126 reg_ps & MSDC_PS_DATA1)) { 1127 __msdc_enable_sdio_irq(host, 0); 1128 sdio_signal_irq(mmc); 1129 } 1130 } 1131 } 1132 } 1133 1134 static void msdc_track_cmd_data(struct msdc_host *host, struct mmc_command *cmd) 1135 { 1136 if (host->error) 1137 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 1138 __func__, cmd->opcode, cmd->arg, host->error); 1139 } 1140 1141 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 1142 { 1143 unsigned long flags; 1144 1145 /* 1146 * No need check the return value of cancel_delayed_work, as only ONE 1147 * path will go here! 1148 */ 1149 cancel_delayed_work(&host->req_timeout); 1150 1151 spin_lock_irqsave(&host->lock, flags); 1152 host->mrq = NULL; 1153 spin_unlock_irqrestore(&host->lock, flags); 1154 1155 msdc_track_cmd_data(host, mrq->cmd); 1156 if (mrq->data) 1157 msdc_unprepare_data(host, mrq->data); 1158 if (host->error) 1159 msdc_reset_hw(host); 1160 mmc_request_done(mmc_from_priv(host), mrq); 1161 if (host->dev_comp->recheck_sdio_irq) 1162 msdc_recheck_sdio_irq(host); 1163 } 1164 1165 /* returns true if command is fully handled; returns false otherwise */ 1166 static bool msdc_cmd_done(struct msdc_host *host, int events, 1167 struct mmc_request *mrq, struct mmc_command *cmd) 1168 { 1169 bool done = false; 1170 bool sbc_error; 1171 unsigned long flags; 1172 u32 *rsp; 1173 1174 if (mrq->sbc && cmd == mrq->cmd && 1175 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 1176 | MSDC_INT_ACMDTMO))) 1177 msdc_auto_cmd_done(host, events, mrq->sbc); 1178 1179 sbc_error = mrq->sbc && mrq->sbc->error; 1180 1181 if (!sbc_error && !(events & (MSDC_INT_CMDRDY 1182 | MSDC_INT_RSPCRCERR 1183 | MSDC_INT_CMDTMO))) 1184 return done; 1185 1186 spin_lock_irqsave(&host->lock, flags); 1187 done = !host->cmd; 1188 host->cmd = NULL; 1189 spin_unlock_irqrestore(&host->lock, flags); 1190 1191 if (done) 1192 return true; 1193 rsp = cmd->resp; 1194 1195 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1196 1197 if (cmd->flags & MMC_RSP_PRESENT) { 1198 if (cmd->flags & MMC_RSP_136) { 1199 rsp[0] = readl(host->base + SDC_RESP3); 1200 rsp[1] = readl(host->base + SDC_RESP2); 1201 rsp[2] = readl(host->base + SDC_RESP1); 1202 rsp[3] = readl(host->base + SDC_RESP0); 1203 } else { 1204 rsp[0] = readl(host->base + SDC_RESP0); 1205 } 1206 } 1207 1208 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 1209 if (events & MSDC_INT_CMDTMO || 1210 (cmd->opcode != MMC_SEND_TUNING_BLOCK && 1211 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200 && 1212 !host->hs400_tuning)) 1213 /* 1214 * should not clear fifo/interrupt as the tune data 1215 * may have alreay come when cmd19/cmd21 gets response 1216 * CRC error. 1217 */ 1218 msdc_reset_hw(host); 1219 if (events & MSDC_INT_RSPCRCERR) { 1220 cmd->error = -EILSEQ; 1221 host->error |= REQ_CMD_EIO; 1222 } else if (events & MSDC_INT_CMDTMO) { 1223 cmd->error = -ETIMEDOUT; 1224 host->error |= REQ_CMD_TMO; 1225 } 1226 } 1227 if (cmd->error) 1228 dev_dbg(host->dev, 1229 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 1230 __func__, cmd->opcode, cmd->arg, rsp[0], 1231 cmd->error); 1232 1233 msdc_cmd_next(host, mrq, cmd); 1234 return true; 1235 } 1236 1237 /* It is the core layer's responsibility to ensure card status 1238 * is correct before issue a request. but host design do below 1239 * checks recommended. 1240 */ 1241 static inline bool msdc_cmd_is_ready(struct msdc_host *host, 1242 struct mmc_request *mrq, struct mmc_command *cmd) 1243 { 1244 u32 val; 1245 int ret; 1246 1247 /* The max busy time we can endure is 20ms */ 1248 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, 1249 !(val & SDC_STS_CMDBUSY), 1, 20000); 1250 if (ret) { 1251 dev_err(host->dev, "CMD bus busy detected\n"); 1252 host->error |= REQ_CMD_BUSY; 1253 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1254 return false; 1255 } 1256 1257 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 1258 /* R1B or with data, should check SDCBUSY */ 1259 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, 1260 !(val & SDC_STS_SDCBUSY), 1, 20000); 1261 if (ret) { 1262 dev_err(host->dev, "Controller busy detected\n"); 1263 host->error |= REQ_CMD_BUSY; 1264 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1265 return false; 1266 } 1267 } 1268 return true; 1269 } 1270 1271 static void msdc_start_command(struct msdc_host *host, 1272 struct mmc_request *mrq, struct mmc_command *cmd) 1273 { 1274 u32 rawcmd; 1275 unsigned long flags; 1276 1277 WARN_ON(host->cmd); 1278 host->cmd = cmd; 1279 1280 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1281 if (!msdc_cmd_is_ready(host, mrq, cmd)) 1282 return; 1283 1284 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 1285 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 1286 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 1287 msdc_reset_hw(host); 1288 } 1289 1290 cmd->error = 0; 1291 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 1292 1293 spin_lock_irqsave(&host->lock, flags); 1294 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1295 spin_unlock_irqrestore(&host->lock, flags); 1296 1297 writel(cmd->arg, host->base + SDC_ARG); 1298 writel(rawcmd, host->base + SDC_CMD); 1299 } 1300 1301 static void msdc_cmd_next(struct msdc_host *host, 1302 struct mmc_request *mrq, struct mmc_command *cmd) 1303 { 1304 if ((cmd->error && 1305 !(cmd->error == -EILSEQ && 1306 (cmd->opcode == MMC_SEND_TUNING_BLOCK || 1307 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200 || 1308 host->hs400_tuning))) || 1309 (mrq->sbc && mrq->sbc->error)) 1310 msdc_request_done(host, mrq); 1311 else if (cmd == mrq->sbc) 1312 msdc_start_command(host, mrq, mrq->cmd); 1313 else if (!cmd->data) 1314 msdc_request_done(host, mrq); 1315 else 1316 msdc_start_data(host, cmd, cmd->data); 1317 } 1318 1319 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 1320 { 1321 struct msdc_host *host = mmc_priv(mmc); 1322 1323 host->error = 0; 1324 WARN_ON(host->mrq); 1325 host->mrq = mrq; 1326 1327 if (mrq->data) 1328 msdc_prepare_data(host, mrq->data); 1329 1330 /* if SBC is required, we have HW option and SW option. 1331 * if HW option is enabled, and SBC does not have "special" flags, 1332 * use HW option, otherwise use SW option 1333 */ 1334 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 1335 (mrq->sbc->arg & 0xFFFF0000))) 1336 msdc_start_command(host, mrq, mrq->sbc); 1337 else 1338 msdc_start_command(host, mrq, mrq->cmd); 1339 } 1340 1341 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 1342 { 1343 struct msdc_host *host = mmc_priv(mmc); 1344 struct mmc_data *data = mrq->data; 1345 1346 if (!data) 1347 return; 1348 1349 msdc_prepare_data(host, data); 1350 data->host_cookie |= MSDC_ASYNC_FLAG; 1351 } 1352 1353 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1354 int err) 1355 { 1356 struct msdc_host *host = mmc_priv(mmc); 1357 struct mmc_data *data = mrq->data; 1358 1359 if (!data) 1360 return; 1361 1362 if (data->host_cookie) { 1363 data->host_cookie &= ~MSDC_ASYNC_FLAG; 1364 msdc_unprepare_data(host, data); 1365 } 1366 } 1367 1368 static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq) 1369 { 1370 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 1371 !mrq->sbc) 1372 msdc_start_command(host, mrq, mrq->stop); 1373 else 1374 msdc_request_done(host, mrq); 1375 } 1376 1377 static void msdc_data_xfer_done(struct msdc_host *host, u32 events, 1378 struct mmc_request *mrq, struct mmc_data *data) 1379 { 1380 struct mmc_command *stop; 1381 unsigned long flags; 1382 bool done; 1383 unsigned int check_data = events & 1384 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 1385 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 1386 | MSDC_INT_DMA_PROTECT); 1387 u32 val; 1388 int ret; 1389 1390 spin_lock_irqsave(&host->lock, flags); 1391 done = !host->data; 1392 if (check_data) 1393 host->data = NULL; 1394 spin_unlock_irqrestore(&host->lock, flags); 1395 1396 if (done) 1397 return; 1398 stop = data->stop; 1399 1400 if (check_data || (stop && stop->error)) { 1401 dev_dbg(host->dev, "DMA status: 0x%8X\n", 1402 readl(host->base + MSDC_DMA_CFG)); 1403 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1404 1); 1405 1406 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val, 1407 !(val & MSDC_DMA_CTRL_STOP), 1, 20000); 1408 if (ret) 1409 dev_dbg(host->dev, "DMA stop timed out\n"); 1410 1411 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val, 1412 !(val & MSDC_DMA_CFG_STS), 1, 20000); 1413 if (ret) 1414 dev_dbg(host->dev, "DMA inactive timed out\n"); 1415 1416 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 1417 dev_dbg(host->dev, "DMA stop\n"); 1418 1419 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 1420 data->bytes_xfered = data->blocks * data->blksz; 1421 } else { 1422 dev_dbg(host->dev, "interrupt events: %x\n", events); 1423 msdc_reset_hw(host); 1424 host->error |= REQ_DAT_ERR; 1425 data->bytes_xfered = 0; 1426 1427 if (events & MSDC_INT_DATTMO) 1428 data->error = -ETIMEDOUT; 1429 else if (events & MSDC_INT_DATCRCERR) 1430 data->error = -EILSEQ; 1431 1432 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 1433 __func__, mrq->cmd->opcode, data->blocks); 1434 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 1435 (int)data->error, data->bytes_xfered); 1436 } 1437 1438 msdc_data_xfer_next(host, mrq); 1439 } 1440 } 1441 1442 static void msdc_set_buswidth(struct msdc_host *host, u32 width) 1443 { 1444 u32 val = readl(host->base + SDC_CFG); 1445 1446 val &= ~SDC_CFG_BUSWIDTH; 1447 1448 switch (width) { 1449 default: 1450 case MMC_BUS_WIDTH_1: 1451 val |= (MSDC_BUS_1BITS << 16); 1452 break; 1453 case MMC_BUS_WIDTH_4: 1454 val |= (MSDC_BUS_4BITS << 16); 1455 break; 1456 case MMC_BUS_WIDTH_8: 1457 val |= (MSDC_BUS_8BITS << 16); 1458 break; 1459 } 1460 1461 writel(val, host->base + SDC_CFG); 1462 dev_dbg(host->dev, "Bus Width = %d", width); 1463 } 1464 1465 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 1466 { 1467 struct msdc_host *host = mmc_priv(mmc); 1468 int ret; 1469 1470 if (!IS_ERR(mmc->supply.vqmmc)) { 1471 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1472 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 1473 dev_err(host->dev, "Unsupported signal voltage!\n"); 1474 return -EINVAL; 1475 } 1476 1477 ret = mmc_regulator_set_vqmmc(mmc, ios); 1478 if (ret < 0) { 1479 dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1480 ret, ios->signal_voltage); 1481 return ret; 1482 } 1483 1484 /* Apply different pinctrl settings for different signal voltage */ 1485 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 1486 pinctrl_select_state(host->pinctrl, host->pins_uhs); 1487 else 1488 pinctrl_select_state(host->pinctrl, host->pins_default); 1489 } 1490 return 0; 1491 } 1492 1493 static int msdc_card_busy(struct mmc_host *mmc) 1494 { 1495 struct msdc_host *host = mmc_priv(mmc); 1496 u32 status = readl(host->base + MSDC_PS); 1497 1498 /* only check if data0 is low */ 1499 return !(status & BIT(16)); 1500 } 1501 1502 static void msdc_request_timeout(struct work_struct *work) 1503 { 1504 struct msdc_host *host = container_of(work, struct msdc_host, 1505 req_timeout.work); 1506 1507 /* simulate HW timeout status */ 1508 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 1509 if (host->mrq) { 1510 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 1511 host->mrq, host->mrq->cmd->opcode); 1512 if (host->cmd) { 1513 dev_err(host->dev, "%s: aborting cmd=%d\n", 1514 __func__, host->cmd->opcode); 1515 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 1516 host->cmd); 1517 } else if (host->data) { 1518 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 1519 __func__, host->mrq->cmd->opcode, 1520 host->data->blocks); 1521 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 1522 host->data); 1523 } 1524 } 1525 } 1526 1527 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb) 1528 { 1529 if (enb) { 1530 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1531 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1532 if (host->dev_comp->recheck_sdio_irq) 1533 msdc_recheck_sdio_irq(host); 1534 } else { 1535 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1536 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1537 } 1538 } 1539 1540 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) 1541 { 1542 struct msdc_host *host = mmc_priv(mmc); 1543 unsigned long flags; 1544 int ret; 1545 1546 spin_lock_irqsave(&host->lock, flags); 1547 __msdc_enable_sdio_irq(host, enb); 1548 spin_unlock_irqrestore(&host->lock, flags); 1549 1550 if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) { 1551 if (enb) { 1552 /* 1553 * In dev_pm_set_dedicated_wake_irq_reverse(), eint pin will be set to 1554 * GPIO mode. We need to restore it to SDIO DAT1 mode after that. 1555 * Since the current pinstate is pins_uhs, to ensure pinctrl select take 1556 * affect successfully, we change the pinstate to pins_eint firstly. 1557 */ 1558 pinctrl_select_state(host->pinctrl, host->pins_eint); 1559 ret = dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq); 1560 1561 if (ret) { 1562 dev_err(host->dev, "Failed to register SDIO wakeup irq!\n"); 1563 host->pins_eint = NULL; 1564 pm_runtime_get_noresume(host->dev); 1565 } else { 1566 dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq); 1567 } 1568 1569 pinctrl_select_state(host->pinctrl, host->pins_uhs); 1570 } else { 1571 dev_pm_clear_wake_irq(host->dev); 1572 } 1573 } else { 1574 if (enb) { 1575 /* Ensure host->pins_eint is NULL */ 1576 host->pins_eint = NULL; 1577 pm_runtime_get_noresume(host->dev); 1578 } else { 1579 pm_runtime_put_noidle(host->dev); 1580 } 1581 } 1582 } 1583 1584 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) 1585 { 1586 struct mmc_host *mmc = mmc_from_priv(host); 1587 int cmd_err = 0, dat_err = 0; 1588 1589 if (intsts & MSDC_INT_RSPCRCERR) { 1590 cmd_err = -EILSEQ; 1591 dev_err(host->dev, "%s: CMD CRC ERR", __func__); 1592 } else if (intsts & MSDC_INT_CMDTMO) { 1593 cmd_err = -ETIMEDOUT; 1594 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); 1595 } 1596 1597 if (intsts & MSDC_INT_DATCRCERR) { 1598 dat_err = -EILSEQ; 1599 dev_err(host->dev, "%s: DATA CRC ERR", __func__); 1600 } else if (intsts & MSDC_INT_DATTMO) { 1601 dat_err = -ETIMEDOUT; 1602 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); 1603 } 1604 1605 if (cmd_err || dat_err) { 1606 dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", 1607 cmd_err, dat_err, intsts); 1608 } 1609 1610 return cqhci_irq(mmc, 0, cmd_err, dat_err); 1611 } 1612 1613 static irqreturn_t msdc_irq(int irq, void *dev_id) 1614 { 1615 struct msdc_host *host = (struct msdc_host *) dev_id; 1616 struct mmc_host *mmc = mmc_from_priv(host); 1617 1618 while (true) { 1619 struct mmc_request *mrq; 1620 struct mmc_command *cmd; 1621 struct mmc_data *data; 1622 u32 events, event_mask; 1623 1624 spin_lock(&host->lock); 1625 events = readl(host->base + MSDC_INT); 1626 event_mask = readl(host->base + MSDC_INTEN); 1627 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1628 __msdc_enable_sdio_irq(host, 0); 1629 /* clear interrupts */ 1630 writel(events & event_mask, host->base + MSDC_INT); 1631 1632 mrq = host->mrq; 1633 cmd = host->cmd; 1634 data = host->data; 1635 spin_unlock(&host->lock); 1636 1637 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1638 sdio_signal_irq(mmc); 1639 1640 if ((events & event_mask) & MSDC_INT_CDSC) { 1641 if (host->internal_cd) 1642 mmc_detect_change(mmc, msecs_to_jiffies(20)); 1643 events &= ~MSDC_INT_CDSC; 1644 } 1645 1646 if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) 1647 break; 1648 1649 if ((mmc->caps2 & MMC_CAP2_CQE) && 1650 (events & MSDC_INT_CMDQ)) { 1651 msdc_cmdq_irq(host, events); 1652 /* clear interrupts */ 1653 writel(events, host->base + MSDC_INT); 1654 return IRQ_HANDLED; 1655 } 1656 1657 if (!mrq) { 1658 dev_err(host->dev, 1659 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 1660 __func__, events, event_mask); 1661 WARN_ON(1); 1662 break; 1663 } 1664 1665 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 1666 1667 if (cmd) 1668 msdc_cmd_done(host, events, mrq, cmd); 1669 else if (data) 1670 msdc_data_xfer_done(host, events, mrq, data); 1671 } 1672 1673 return IRQ_HANDLED; 1674 } 1675 1676 static void msdc_init_hw(struct msdc_host *host) 1677 { 1678 u32 val; 1679 u32 tune_reg = host->dev_comp->pad_tune_reg; 1680 struct mmc_host *mmc = mmc_from_priv(host); 1681 1682 if (host->reset) { 1683 reset_control_assert(host->reset); 1684 usleep_range(10, 50); 1685 reset_control_deassert(host->reset); 1686 } 1687 1688 /* Configure to MMC/SD mode, clock free running */ 1689 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 1690 1691 /* Reset */ 1692 msdc_reset_hw(host); 1693 1694 /* Disable and clear all interrupts */ 1695 writel(0, host->base + MSDC_INTEN); 1696 val = readl(host->base + MSDC_INT); 1697 writel(val, host->base + MSDC_INT); 1698 1699 /* Configure card detection */ 1700 if (host->internal_cd) { 1701 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, 1702 DEFAULT_DEBOUNCE); 1703 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1704 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1705 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1706 } else { 1707 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1708 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1709 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1710 } 1711 1712 if (host->top_base) { 1713 writel(0, host->top_base + EMMC_TOP_CONTROL); 1714 writel(0, host->top_base + EMMC_TOP_CMD); 1715 } else { 1716 writel(0, host->base + tune_reg); 1717 } 1718 writel(0, host->base + MSDC_IOCON); 1719 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 1720 writel(0x403c0046, host->base + MSDC_PATCH_BIT); 1721 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 1722 writel(0xffff4089, host->base + MSDC_PATCH_BIT1); 1723 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1724 1725 if (host->dev_comp->stop_clk_fix) { 1726 sdr_set_field(host->base + MSDC_PATCH_BIT1, 1727 MSDC_PATCH_BIT1_STOP_DLY, 3); 1728 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1729 SDC_FIFO_CFG_WRVALIDSEL); 1730 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1731 SDC_FIFO_CFG_RDVALIDSEL); 1732 } 1733 1734 if (host->dev_comp->busy_check) 1735 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7)); 1736 1737 if (host->dev_comp->async_fifo) { 1738 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1739 MSDC_PB2_RESPWAIT, 3); 1740 if (host->dev_comp->enhance_rx) { 1741 if (host->top_base) 1742 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1743 SDC_RX_ENH_EN); 1744 else 1745 sdr_set_bits(host->base + SDC_ADV_CFG0, 1746 SDC_RX_ENHANCE_EN); 1747 } else { 1748 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1749 MSDC_PB2_RESPSTSENSEL, 2); 1750 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1751 MSDC_PB2_CRCSTSENSEL, 2); 1752 } 1753 /* use async fifo, then no need tune internal delay */ 1754 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, 1755 MSDC_PATCH_BIT2_CFGRESP); 1756 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1757 MSDC_PATCH_BIT2_CFGCRCSTS); 1758 } 1759 1760 if (host->dev_comp->support_64g) 1761 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1762 MSDC_PB2_SUPPORT_64G); 1763 if (host->dev_comp->data_tune) { 1764 if (host->top_base) { 1765 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1766 PAD_DAT_RD_RXDLY_SEL); 1767 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, 1768 DATA_K_VALUE_SEL); 1769 sdr_set_bits(host->top_base + EMMC_TOP_CMD, 1770 PAD_CMD_RD_RXDLY_SEL); 1771 } else { 1772 sdr_set_bits(host->base + tune_reg, 1773 MSDC_PAD_TUNE_RD_SEL | 1774 MSDC_PAD_TUNE_CMD_SEL); 1775 } 1776 } else { 1777 /* choose clock tune */ 1778 if (host->top_base) 1779 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1780 PAD_RXDLY_SEL); 1781 else 1782 sdr_set_bits(host->base + tune_reg, 1783 MSDC_PAD_TUNE_RXDLYSEL); 1784 } 1785 1786 if (mmc->caps2 & MMC_CAP2_NO_SDIO) { 1787 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1788 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1789 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 1790 } else { 1791 /* Configure to enable SDIO mode, otherwise SDIO CMD5 fails */ 1792 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1793 1794 /* Config SDIO device detect interrupt function */ 1795 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1796 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 1797 } 1798 1799 /* Configure to default data timeout */ 1800 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 1801 1802 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 1803 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1804 if (host->top_base) { 1805 host->def_tune_para.emmc_top_control = 1806 readl(host->top_base + EMMC_TOP_CONTROL); 1807 host->def_tune_para.emmc_top_cmd = 1808 readl(host->top_base + EMMC_TOP_CMD); 1809 host->saved_tune_para.emmc_top_control = 1810 readl(host->top_base + EMMC_TOP_CONTROL); 1811 host->saved_tune_para.emmc_top_cmd = 1812 readl(host->top_base + EMMC_TOP_CMD); 1813 } else { 1814 host->def_tune_para.pad_tune = readl(host->base + tune_reg); 1815 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 1816 } 1817 dev_dbg(host->dev, "init hardware done!"); 1818 } 1819 1820 static void msdc_deinit_hw(struct msdc_host *host) 1821 { 1822 u32 val; 1823 1824 if (host->internal_cd) { 1825 /* Disabled card-detect */ 1826 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1827 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1828 } 1829 1830 /* Disable and clear all interrupts */ 1831 writel(0, host->base + MSDC_INTEN); 1832 1833 val = readl(host->base + MSDC_INT); 1834 writel(val, host->base + MSDC_INT); 1835 } 1836 1837 /* init gpd and bd list in msdc_drv_probe */ 1838 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 1839 { 1840 struct mt_gpdma_desc *gpd = dma->gpd; 1841 struct mt_bdma_desc *bd = dma->bd; 1842 dma_addr_t dma_addr; 1843 int i; 1844 1845 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 1846 1847 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); 1848 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 1849 /* gpd->next is must set for desc DMA 1850 * That's why must alloc 2 gpd structure. 1851 */ 1852 gpd->next = lower_32_bits(dma_addr); 1853 if (host->dev_comp->support_64g) 1854 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1855 1856 dma_addr = dma->bd_addr; 1857 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ 1858 if (host->dev_comp->support_64g) 1859 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; 1860 1861 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 1862 for (i = 0; i < (MAX_BD_NUM - 1); i++) { 1863 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); 1864 bd[i].next = lower_32_bits(dma_addr); 1865 if (host->dev_comp->support_64g) 1866 bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1867 } 1868 } 1869 1870 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1871 { 1872 struct msdc_host *host = mmc_priv(mmc); 1873 int ret; 1874 1875 msdc_set_buswidth(host, ios->bus_width); 1876 1877 /* Suspend/Resume will do power off/on */ 1878 switch (ios->power_mode) { 1879 case MMC_POWER_UP: 1880 if (!IS_ERR(mmc->supply.vmmc)) { 1881 msdc_init_hw(host); 1882 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1883 ios->vdd); 1884 if (ret) { 1885 dev_err(host->dev, "Failed to set vmmc power!\n"); 1886 return; 1887 } 1888 } 1889 break; 1890 case MMC_POWER_ON: 1891 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1892 ret = regulator_enable(mmc->supply.vqmmc); 1893 if (ret) 1894 dev_err(host->dev, "Failed to set vqmmc power!\n"); 1895 else 1896 host->vqmmc_enabled = true; 1897 } 1898 break; 1899 case MMC_POWER_OFF: 1900 if (!IS_ERR(mmc->supply.vmmc)) 1901 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1902 1903 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1904 regulator_disable(mmc->supply.vqmmc); 1905 host->vqmmc_enabled = false; 1906 } 1907 break; 1908 default: 1909 break; 1910 } 1911 1912 if (host->mclk != ios->clock || host->timing != ios->timing) 1913 msdc_set_mclk(host, ios->timing, ios->clock); 1914 } 1915 1916 static u32 test_delay_bit(u32 delay, u32 bit) 1917 { 1918 bit %= PAD_DELAY_MAX; 1919 return delay & BIT(bit); 1920 } 1921 1922 static int get_delay_len(u32 delay, u32 start_bit) 1923 { 1924 int i; 1925 1926 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 1927 if (test_delay_bit(delay, start_bit + i) == 0) 1928 return i; 1929 } 1930 return PAD_DELAY_MAX - start_bit; 1931 } 1932 1933 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 1934 { 1935 int start = 0, len = 0; 1936 int start_final = 0, len_final = 0; 1937 u8 final_phase = 0xff; 1938 struct msdc_delay_phase delay_phase = { 0, }; 1939 1940 if (delay == 0) { 1941 dev_err(host->dev, "phase error: [map:%x]\n", delay); 1942 delay_phase.final_phase = final_phase; 1943 return delay_phase; 1944 } 1945 1946 while (start < PAD_DELAY_MAX) { 1947 len = get_delay_len(delay, start); 1948 if (len_final < len) { 1949 start_final = start; 1950 len_final = len; 1951 } 1952 start += len ? len : 1; 1953 if (len >= 12 && start_final < 4) 1954 break; 1955 } 1956 1957 /* The rule is that to find the smallest delay cell */ 1958 if (start_final == 0) 1959 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 1960 else 1961 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 1962 dev_dbg(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 1963 delay, len_final, final_phase); 1964 1965 delay_phase.maxlen = len_final; 1966 delay_phase.start = start_final; 1967 delay_phase.final_phase = final_phase; 1968 return delay_phase; 1969 } 1970 1971 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) 1972 { 1973 u32 tune_reg = host->dev_comp->pad_tune_reg; 1974 1975 if (host->top_base) 1976 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, 1977 value); 1978 else 1979 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1980 value); 1981 } 1982 1983 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) 1984 { 1985 u32 tune_reg = host->dev_comp->pad_tune_reg; 1986 1987 if (host->top_base) 1988 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, 1989 PAD_DAT_RD_RXDLY, value); 1990 else 1991 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, 1992 value); 1993 } 1994 1995 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 1996 { 1997 struct msdc_host *host = mmc_priv(mmc); 1998 u32 rise_delay = 0, fall_delay = 0; 1999 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2000 struct msdc_delay_phase internal_delay_phase; 2001 u8 final_delay, final_maxlen; 2002 u32 internal_delay = 0; 2003 u32 tune_reg = host->dev_comp->pad_tune_reg; 2004 int cmd_err; 2005 int i, j; 2006 2007 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 2008 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 2009 sdr_set_field(host->base + tune_reg, 2010 MSDC_PAD_TUNE_CMDRRDLY, 2011 host->hs200_cmd_int_delay); 2012 2013 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2014 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2015 msdc_set_cmd_delay(host, i); 2016 /* 2017 * Using the same parameters, it may sometimes pass the test, 2018 * but sometimes it may fail. To make sure the parameters are 2019 * more stable, we test each set of parameters 3 times. 2020 */ 2021 for (j = 0; j < 3; j++) { 2022 mmc_send_tuning(mmc, opcode, &cmd_err); 2023 if (!cmd_err) { 2024 rise_delay |= BIT(i); 2025 } else { 2026 rise_delay &= ~BIT(i); 2027 break; 2028 } 2029 } 2030 } 2031 final_rise_delay = get_best_delay(host, rise_delay); 2032 /* if rising edge has enough margin, then do not scan falling edge */ 2033 if (final_rise_delay.maxlen >= 12 || 2034 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2035 goto skip_fall; 2036 2037 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2038 for (i = 0; i < PAD_DELAY_MAX; i++) { 2039 msdc_set_cmd_delay(host, i); 2040 /* 2041 * Using the same parameters, it may sometimes pass the test, 2042 * but sometimes it may fail. To make sure the parameters are 2043 * more stable, we test each set of parameters 3 times. 2044 */ 2045 for (j = 0; j < 3; j++) { 2046 mmc_send_tuning(mmc, opcode, &cmd_err); 2047 if (!cmd_err) { 2048 fall_delay |= BIT(i); 2049 } else { 2050 fall_delay &= ~BIT(i); 2051 break; 2052 } 2053 } 2054 } 2055 final_fall_delay = get_best_delay(host, fall_delay); 2056 2057 skip_fall: 2058 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2059 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 2060 final_maxlen = final_fall_delay.maxlen; 2061 if (final_maxlen == final_rise_delay.maxlen) { 2062 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2063 final_delay = final_rise_delay.final_phase; 2064 } else { 2065 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2066 final_delay = final_fall_delay.final_phase; 2067 } 2068 msdc_set_cmd_delay(host, final_delay); 2069 2070 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) 2071 goto skip_internal; 2072 2073 for (i = 0; i < PAD_DELAY_MAX; i++) { 2074 sdr_set_field(host->base + tune_reg, 2075 MSDC_PAD_TUNE_CMDRRDLY, i); 2076 mmc_send_tuning(mmc, opcode, &cmd_err); 2077 if (!cmd_err) 2078 internal_delay |= BIT(i); 2079 } 2080 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 2081 internal_delay_phase = get_best_delay(host, internal_delay); 2082 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 2083 internal_delay_phase.final_phase); 2084 skip_internal: 2085 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 2086 return final_delay == 0xff ? -EIO : 0; 2087 } 2088 2089 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 2090 { 2091 struct msdc_host *host = mmc_priv(mmc); 2092 u32 cmd_delay = 0; 2093 struct msdc_delay_phase final_cmd_delay = { 0,}; 2094 u8 final_delay; 2095 int cmd_err; 2096 int i, j; 2097 2098 /* select EMMC50 PAD CMD tune */ 2099 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 2100 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); 2101 2102 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 2103 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 2104 sdr_set_field(host->base + MSDC_PAD_TUNE, 2105 MSDC_PAD_TUNE_CMDRRDLY, 2106 host->hs200_cmd_int_delay); 2107 2108 if (host->hs400_cmd_resp_sel_rising) 2109 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2110 else 2111 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2112 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2113 sdr_set_field(host->base + PAD_CMD_TUNE, 2114 PAD_CMD_TUNE_RX_DLY3, i); 2115 /* 2116 * Using the same parameters, it may sometimes pass the test, 2117 * but sometimes it may fail. To make sure the parameters are 2118 * more stable, we test each set of parameters 3 times. 2119 */ 2120 for (j = 0; j < 3; j++) { 2121 mmc_send_tuning(mmc, opcode, &cmd_err); 2122 if (!cmd_err) { 2123 cmd_delay |= BIT(i); 2124 } else { 2125 cmd_delay &= ~BIT(i); 2126 break; 2127 } 2128 } 2129 } 2130 final_cmd_delay = get_best_delay(host, cmd_delay); 2131 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 2132 final_cmd_delay.final_phase); 2133 final_delay = final_cmd_delay.final_phase; 2134 2135 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 2136 return final_delay == 0xff ? -EIO : 0; 2137 } 2138 2139 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 2140 { 2141 struct msdc_host *host = mmc_priv(mmc); 2142 u32 rise_delay = 0, fall_delay = 0; 2143 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2144 u8 final_delay, final_maxlen; 2145 int i, ret; 2146 2147 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2148 host->latch_ck); 2149 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2150 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2151 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2152 msdc_set_data_delay(host, i); 2153 ret = mmc_send_tuning(mmc, opcode, NULL); 2154 if (!ret) 2155 rise_delay |= BIT(i); 2156 } 2157 final_rise_delay = get_best_delay(host, rise_delay); 2158 /* if rising edge has enough margin, then do not scan falling edge */ 2159 if (final_rise_delay.maxlen >= 12 || 2160 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2161 goto skip_fall; 2162 2163 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2164 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2165 for (i = 0; i < PAD_DELAY_MAX; i++) { 2166 msdc_set_data_delay(host, i); 2167 ret = mmc_send_tuning(mmc, opcode, NULL); 2168 if (!ret) 2169 fall_delay |= BIT(i); 2170 } 2171 final_fall_delay = get_best_delay(host, fall_delay); 2172 2173 skip_fall: 2174 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2175 if (final_maxlen == final_rise_delay.maxlen) { 2176 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2177 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2178 final_delay = final_rise_delay.final_phase; 2179 } else { 2180 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2181 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2182 final_delay = final_fall_delay.final_phase; 2183 } 2184 msdc_set_data_delay(host, final_delay); 2185 2186 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 2187 return final_delay == 0xff ? -EIO : 0; 2188 } 2189 2190 /* 2191 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune 2192 * together, which can save the tuning time. 2193 */ 2194 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode) 2195 { 2196 struct msdc_host *host = mmc_priv(mmc); 2197 u32 rise_delay = 0, fall_delay = 0; 2198 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2199 u8 final_delay, final_maxlen; 2200 int i, ret; 2201 2202 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2203 host->latch_ck); 2204 2205 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2206 sdr_clr_bits(host->base + MSDC_IOCON, 2207 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2208 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2209 msdc_set_cmd_delay(host, i); 2210 msdc_set_data_delay(host, i); 2211 ret = mmc_send_tuning(mmc, opcode, NULL); 2212 if (!ret) 2213 rise_delay |= BIT(i); 2214 } 2215 final_rise_delay = get_best_delay(host, rise_delay); 2216 /* if rising edge has enough margin, then do not scan falling edge */ 2217 if (final_rise_delay.maxlen >= 12 || 2218 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2219 goto skip_fall; 2220 2221 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2222 sdr_set_bits(host->base + MSDC_IOCON, 2223 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2224 for (i = 0; i < PAD_DELAY_MAX; i++) { 2225 msdc_set_cmd_delay(host, i); 2226 msdc_set_data_delay(host, i); 2227 ret = mmc_send_tuning(mmc, opcode, NULL); 2228 if (!ret) 2229 fall_delay |= BIT(i); 2230 } 2231 final_fall_delay = get_best_delay(host, fall_delay); 2232 2233 skip_fall: 2234 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2235 if (final_maxlen == final_rise_delay.maxlen) { 2236 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2237 sdr_clr_bits(host->base + MSDC_IOCON, 2238 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2239 final_delay = final_rise_delay.final_phase; 2240 } else { 2241 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2242 sdr_set_bits(host->base + MSDC_IOCON, 2243 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2244 final_delay = final_fall_delay.final_phase; 2245 } 2246 2247 msdc_set_cmd_delay(host, final_delay); 2248 msdc_set_data_delay(host, final_delay); 2249 2250 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); 2251 return final_delay == 0xff ? -EIO : 0; 2252 } 2253 2254 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 2255 { 2256 struct msdc_host *host = mmc_priv(mmc); 2257 int ret; 2258 u32 tune_reg = host->dev_comp->pad_tune_reg; 2259 2260 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { 2261 ret = msdc_tune_together(mmc, opcode); 2262 if (host->hs400_mode) { 2263 sdr_clr_bits(host->base + MSDC_IOCON, 2264 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2265 msdc_set_data_delay(host, 0); 2266 } 2267 goto tune_done; 2268 } 2269 if (host->hs400_mode && 2270 host->dev_comp->hs400_tune) 2271 ret = hs400_tune_response(mmc, opcode); 2272 else 2273 ret = msdc_tune_response(mmc, opcode); 2274 if (ret == -EIO) { 2275 dev_err(host->dev, "Tune response fail!\n"); 2276 return ret; 2277 } 2278 if (host->hs400_mode == false) { 2279 ret = msdc_tune_data(mmc, opcode); 2280 if (ret == -EIO) 2281 dev_err(host->dev, "Tune data fail!\n"); 2282 } 2283 2284 tune_done: 2285 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 2286 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 2287 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2288 if (host->top_base) { 2289 host->saved_tune_para.emmc_top_control = readl(host->top_base + 2290 EMMC_TOP_CONTROL); 2291 host->saved_tune_para.emmc_top_cmd = readl(host->top_base + 2292 EMMC_TOP_CMD); 2293 } 2294 return ret; 2295 } 2296 2297 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 2298 { 2299 struct msdc_host *host = mmc_priv(mmc); 2300 host->hs400_mode = true; 2301 2302 if (host->top_base) 2303 writel(host->hs400_ds_delay, 2304 host->top_base + EMMC50_PAD_DS_TUNE); 2305 else 2306 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 2307 /* hs400 mode must set it to 0 */ 2308 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); 2309 /* to improve read performance, set outstanding to 2 */ 2310 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); 2311 2312 return 0; 2313 } 2314 2315 static int msdc_execute_hs400_tuning(struct mmc_host *mmc, struct mmc_card *card) 2316 { 2317 struct msdc_host *host = mmc_priv(mmc); 2318 struct msdc_delay_phase dly1_delay; 2319 u32 val, result_dly1 = 0; 2320 u8 *ext_csd; 2321 int i, ret; 2322 2323 if (host->top_base) { 2324 sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE, 2325 PAD_DS_DLY_SEL); 2326 if (host->hs400_ds_dly3) 2327 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, 2328 PAD_DS_DLY3, host->hs400_ds_dly3); 2329 } else { 2330 sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL); 2331 if (host->hs400_ds_dly3) 2332 sdr_set_field(host->base + PAD_DS_TUNE, 2333 PAD_DS_TUNE_DLY3, host->hs400_ds_dly3); 2334 } 2335 2336 host->hs400_tuning = true; 2337 for (i = 0; i < PAD_DELAY_MAX; i++) { 2338 if (host->top_base) 2339 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, 2340 PAD_DS_DLY1, i); 2341 else 2342 sdr_set_field(host->base + PAD_DS_TUNE, 2343 PAD_DS_TUNE_DLY1, i); 2344 ret = mmc_get_ext_csd(card, &ext_csd); 2345 if (!ret) { 2346 result_dly1 |= BIT(i); 2347 kfree(ext_csd); 2348 } 2349 } 2350 host->hs400_tuning = false; 2351 2352 dly1_delay = get_best_delay(host, result_dly1); 2353 if (dly1_delay.maxlen == 0) { 2354 dev_err(host->dev, "Failed to get DLY1 delay!\n"); 2355 goto fail; 2356 } 2357 if (host->top_base) 2358 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, 2359 PAD_DS_DLY1, dly1_delay.final_phase); 2360 else 2361 sdr_set_field(host->base + PAD_DS_TUNE, 2362 PAD_DS_TUNE_DLY1, dly1_delay.final_phase); 2363 2364 if (host->top_base) 2365 val = readl(host->top_base + EMMC50_PAD_DS_TUNE); 2366 else 2367 val = readl(host->base + PAD_DS_TUNE); 2368 2369 dev_info(host->dev, "Final PAD_DS_TUNE: 0x%x\n", val); 2370 2371 return 0; 2372 2373 fail: 2374 dev_err(host->dev, "Failed to tuning DS pin delay!\n"); 2375 return -EIO; 2376 } 2377 2378 static void msdc_hw_reset(struct mmc_host *mmc) 2379 { 2380 struct msdc_host *host = mmc_priv(mmc); 2381 2382 sdr_set_bits(host->base + EMMC_IOCON, 1); 2383 udelay(10); /* 10us is enough */ 2384 sdr_clr_bits(host->base + EMMC_IOCON, 1); 2385 } 2386 2387 static void msdc_ack_sdio_irq(struct mmc_host *mmc) 2388 { 2389 unsigned long flags; 2390 struct msdc_host *host = mmc_priv(mmc); 2391 2392 spin_lock_irqsave(&host->lock, flags); 2393 __msdc_enable_sdio_irq(host, 1); 2394 spin_unlock_irqrestore(&host->lock, flags); 2395 } 2396 2397 static int msdc_get_cd(struct mmc_host *mmc) 2398 { 2399 struct msdc_host *host = mmc_priv(mmc); 2400 int val; 2401 2402 if (mmc->caps & MMC_CAP_NONREMOVABLE) 2403 return 1; 2404 2405 if (!host->internal_cd) 2406 return mmc_gpio_get_cd(mmc); 2407 2408 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; 2409 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) 2410 return !!val; 2411 else 2412 return !val; 2413 } 2414 2415 static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc, 2416 struct mmc_ios *ios) 2417 { 2418 struct msdc_host *host = mmc_priv(mmc); 2419 2420 if (ios->enhanced_strobe) { 2421 msdc_prepare_hs400_tuning(mmc, ios); 2422 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1); 2423 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1); 2424 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1); 2425 2426 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); 2427 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); 2428 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT); 2429 } else { 2430 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0); 2431 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0); 2432 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0); 2433 2434 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); 2435 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); 2436 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4); 2437 } 2438 } 2439 2440 static void msdc_cqe_enable(struct mmc_host *mmc) 2441 { 2442 struct msdc_host *host = mmc_priv(mmc); 2443 2444 /* enable cmdq irq */ 2445 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); 2446 /* enable busy check */ 2447 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 2448 /* default write data / busy timeout 20s */ 2449 msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); 2450 /* default read data timeout 1s */ 2451 msdc_set_timeout(host, 1000000000ULL, 0); 2452 } 2453 2454 static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) 2455 { 2456 struct msdc_host *host = mmc_priv(mmc); 2457 unsigned int val = 0; 2458 2459 /* disable cmdq irq */ 2460 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); 2461 /* disable busy check */ 2462 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 2463 2464 val = readl(host->base + MSDC_INT); 2465 writel(val, host->base + MSDC_INT); 2466 2467 if (recovery) { 2468 sdr_set_field(host->base + MSDC_DMA_CTRL, 2469 MSDC_DMA_CTRL_STOP, 1); 2470 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val, 2471 !(val & MSDC_DMA_CTRL_STOP), 1, 3000))) 2472 return; 2473 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val, 2474 !(val & MSDC_DMA_CFG_STS), 1, 3000))) 2475 return; 2476 msdc_reset_hw(host); 2477 } 2478 } 2479 2480 static void msdc_cqe_pre_enable(struct mmc_host *mmc) 2481 { 2482 struct cqhci_host *cq_host = mmc->cqe_private; 2483 u32 reg; 2484 2485 reg = cqhci_readl(cq_host, CQHCI_CFG); 2486 reg |= CQHCI_ENABLE; 2487 cqhci_writel(cq_host, reg, CQHCI_CFG); 2488 } 2489 2490 static void msdc_cqe_post_disable(struct mmc_host *mmc) 2491 { 2492 struct cqhci_host *cq_host = mmc->cqe_private; 2493 u32 reg; 2494 2495 reg = cqhci_readl(cq_host, CQHCI_CFG); 2496 reg &= ~CQHCI_ENABLE; 2497 cqhci_writel(cq_host, reg, CQHCI_CFG); 2498 } 2499 2500 static const struct mmc_host_ops mt_msdc_ops = { 2501 .post_req = msdc_post_req, 2502 .pre_req = msdc_pre_req, 2503 .request = msdc_ops_request, 2504 .set_ios = msdc_ops_set_ios, 2505 .get_ro = mmc_gpio_get_ro, 2506 .get_cd = msdc_get_cd, 2507 .hs400_enhanced_strobe = msdc_hs400_enhanced_strobe, 2508 .enable_sdio_irq = msdc_enable_sdio_irq, 2509 .ack_sdio_irq = msdc_ack_sdio_irq, 2510 .start_signal_voltage_switch = msdc_ops_switch_volt, 2511 .card_busy = msdc_card_busy, 2512 .execute_tuning = msdc_execute_tuning, 2513 .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 2514 .execute_hs400_tuning = msdc_execute_hs400_tuning, 2515 .card_hw_reset = msdc_hw_reset, 2516 }; 2517 2518 static const struct cqhci_host_ops msdc_cmdq_ops = { 2519 .enable = msdc_cqe_enable, 2520 .disable = msdc_cqe_disable, 2521 .pre_enable = msdc_cqe_pre_enable, 2522 .post_disable = msdc_cqe_post_disable, 2523 }; 2524 2525 static void msdc_of_property_parse(struct platform_device *pdev, 2526 struct msdc_host *host) 2527 { 2528 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", 2529 &host->latch_ck); 2530 2531 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 2532 &host->hs400_ds_delay); 2533 2534 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3", 2535 &host->hs400_ds_dly3); 2536 2537 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 2538 &host->hs200_cmd_int_delay); 2539 2540 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 2541 &host->hs400_cmd_int_delay); 2542 2543 if (of_property_read_bool(pdev->dev.of_node, 2544 "mediatek,hs400-cmd-resp-sel-rising")) 2545 host->hs400_cmd_resp_sel_rising = true; 2546 else 2547 host->hs400_cmd_resp_sel_rising = false; 2548 2549 if (of_property_read_bool(pdev->dev.of_node, 2550 "supports-cqe")) 2551 host->cqhci = true; 2552 else 2553 host->cqhci = false; 2554 } 2555 2556 static int msdc_of_clock_parse(struct platform_device *pdev, 2557 struct msdc_host *host) 2558 { 2559 int ret; 2560 2561 host->src_clk = devm_clk_get(&pdev->dev, "source"); 2562 if (IS_ERR(host->src_clk)) 2563 return PTR_ERR(host->src_clk); 2564 2565 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 2566 if (IS_ERR(host->h_clk)) 2567 return PTR_ERR(host->h_clk); 2568 2569 host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk"); 2570 if (IS_ERR(host->bus_clk)) 2571 host->bus_clk = NULL; 2572 2573 /*source clock control gate is optional clock*/ 2574 host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg"); 2575 if (IS_ERR(host->src_clk_cg)) 2576 return PTR_ERR(host->src_clk_cg); 2577 2578 /* 2579 * Fallback for legacy device-trees: src_clk and HCLK use the same 2580 * bit to control gating but they are parented to a different mux, 2581 * hence if our intention is to gate only the source, required 2582 * during a clk mode switch to avoid hw hangs, we need to gate 2583 * its parent (specified as a different clock only on new DTs). 2584 */ 2585 if (!host->src_clk_cg) { 2586 host->src_clk_cg = clk_get_parent(host->src_clk); 2587 if (IS_ERR(host->src_clk_cg)) 2588 return PTR_ERR(host->src_clk_cg); 2589 } 2590 2591 host->sys_clk_cg = devm_clk_get_optional(&pdev->dev, "sys_cg"); 2592 if (IS_ERR(host->sys_clk_cg)) 2593 host->sys_clk_cg = NULL; 2594 2595 /* If present, always enable for this clock gate */ 2596 clk_prepare_enable(host->sys_clk_cg); 2597 2598 host->bulk_clks[0].id = "pclk_cg"; 2599 host->bulk_clks[1].id = "axi_cg"; 2600 host->bulk_clks[2].id = "ahb_cg"; 2601 ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS, 2602 host->bulk_clks); 2603 if (ret) { 2604 dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n"); 2605 return ret; 2606 } 2607 2608 return 0; 2609 } 2610 2611 static int msdc_drv_probe(struct platform_device *pdev) 2612 { 2613 struct mmc_host *mmc; 2614 struct msdc_host *host; 2615 struct resource *res; 2616 int ret; 2617 2618 if (!pdev->dev.of_node) { 2619 dev_err(&pdev->dev, "No DT found\n"); 2620 return -EINVAL; 2621 } 2622 2623 /* Allocate MMC host for this device */ 2624 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 2625 if (!mmc) 2626 return -ENOMEM; 2627 2628 host = mmc_priv(mmc); 2629 ret = mmc_of_parse(mmc); 2630 if (ret) 2631 goto host_free; 2632 2633 host->base = devm_platform_ioremap_resource(pdev, 0); 2634 if (IS_ERR(host->base)) { 2635 ret = PTR_ERR(host->base); 2636 goto host_free; 2637 } 2638 2639 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2640 if (res) { 2641 host->top_base = devm_ioremap_resource(&pdev->dev, res); 2642 if (IS_ERR(host->top_base)) 2643 host->top_base = NULL; 2644 } 2645 2646 ret = mmc_regulator_get_supply(mmc); 2647 if (ret) 2648 goto host_free; 2649 2650 ret = msdc_of_clock_parse(pdev, host); 2651 if (ret) 2652 goto host_free; 2653 2654 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 2655 "hrst"); 2656 if (IS_ERR(host->reset)) { 2657 ret = PTR_ERR(host->reset); 2658 goto host_free; 2659 } 2660 2661 host->irq = platform_get_irq(pdev, 0); 2662 if (host->irq < 0) { 2663 ret = -EINVAL; 2664 goto host_free; 2665 } 2666 2667 host->pinctrl = devm_pinctrl_get(&pdev->dev); 2668 if (IS_ERR(host->pinctrl)) { 2669 ret = PTR_ERR(host->pinctrl); 2670 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 2671 goto host_free; 2672 } 2673 2674 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 2675 if (IS_ERR(host->pins_default)) { 2676 ret = PTR_ERR(host->pins_default); 2677 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 2678 goto host_free; 2679 } 2680 2681 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 2682 if (IS_ERR(host->pins_uhs)) { 2683 ret = PTR_ERR(host->pins_uhs); 2684 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 2685 goto host_free; 2686 } 2687 2688 /* Support for SDIO eint irq ? */ 2689 if ((mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) && (mmc->pm_caps & MMC_PM_KEEP_POWER)) { 2690 host->eint_irq = platform_get_irq_byname(pdev, "sdio_wakeup"); 2691 if (host->eint_irq > 0) { 2692 host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint"); 2693 if (IS_ERR(host->pins_eint)) { 2694 dev_err(&pdev->dev, "Cannot find pinctrl eint!\n"); 2695 host->pins_eint = NULL; 2696 } else { 2697 device_init_wakeup(&pdev->dev, true); 2698 } 2699 } 2700 } 2701 2702 msdc_of_property_parse(pdev, host); 2703 2704 host->dev = &pdev->dev; 2705 host->dev_comp = of_device_get_match_data(&pdev->dev); 2706 host->src_clk_freq = clk_get_rate(host->src_clk); 2707 /* Set host parameters to mmc */ 2708 mmc->ops = &mt_msdc_ops; 2709 if (host->dev_comp->clk_div_bits == 8) 2710 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 2711 else 2712 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); 2713 2714 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && 2715 !mmc_can_gpio_cd(mmc) && 2716 host->dev_comp->use_internal_cd) { 2717 /* 2718 * Is removable but no GPIO declared, so 2719 * use internal functionality. 2720 */ 2721 host->internal_cd = true; 2722 } 2723 2724 if (mmc->caps & MMC_CAP_SDIO_IRQ) 2725 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2726 2727 mmc->caps |= MMC_CAP_CMD23; 2728 if (host->cqhci) 2729 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 2730 /* MMC core transfer sizes tunable parameters */ 2731 mmc->max_segs = MAX_BD_NUM; 2732 if (host->dev_comp->support_64g) 2733 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; 2734 else 2735 mmc->max_seg_size = BDMA_DESC_BUFLEN; 2736 mmc->max_blk_size = 2048; 2737 mmc->max_req_size = 512 * 1024; 2738 mmc->max_blk_count = mmc->max_req_size / 512; 2739 if (host->dev_comp->support_64g) 2740 host->dma_mask = DMA_BIT_MASK(36); 2741 else 2742 host->dma_mask = DMA_BIT_MASK(32); 2743 mmc_dev(mmc)->dma_mask = &host->dma_mask; 2744 2745 host->timeout_clks = 3 * 1048576; 2746 host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2747 2 * sizeof(struct mt_gpdma_desc), 2748 &host->dma.gpd_addr, GFP_KERNEL); 2749 host->dma.bd = dma_alloc_coherent(&pdev->dev, 2750 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2751 &host->dma.bd_addr, GFP_KERNEL); 2752 if (!host->dma.gpd || !host->dma.bd) { 2753 ret = -ENOMEM; 2754 goto release_mem; 2755 } 2756 msdc_init_gpd_bd(host, &host->dma); 2757 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 2758 spin_lock_init(&host->lock); 2759 2760 platform_set_drvdata(pdev, mmc); 2761 ret = msdc_ungate_clock(host); 2762 if (ret) { 2763 dev_err(&pdev->dev, "Cannot ungate clocks!\n"); 2764 goto release_mem; 2765 } 2766 msdc_init_hw(host); 2767 2768 if (mmc->caps2 & MMC_CAP2_CQE) { 2769 host->cq_host = devm_kzalloc(mmc->parent, 2770 sizeof(*host->cq_host), 2771 GFP_KERNEL); 2772 if (!host->cq_host) { 2773 ret = -ENOMEM; 2774 goto host_free; 2775 } 2776 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 2777 host->cq_host->mmio = host->base + 0x800; 2778 host->cq_host->ops = &msdc_cmdq_ops; 2779 ret = cqhci_init(host->cq_host, mmc, true); 2780 if (ret) 2781 goto host_free; 2782 mmc->max_segs = 128; 2783 /* cqhci 16bit length */ 2784 /* 0 size, means 65536 so we don't have to -1 here */ 2785 mmc->max_seg_size = 64 * 1024; 2786 } 2787 2788 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 2789 IRQF_TRIGGER_NONE, pdev->name, host); 2790 if (ret) 2791 goto release; 2792 2793 pm_runtime_set_active(host->dev); 2794 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 2795 pm_runtime_use_autosuspend(host->dev); 2796 pm_runtime_enable(host->dev); 2797 ret = mmc_add_host(mmc); 2798 2799 if (ret) 2800 goto end; 2801 2802 return 0; 2803 end: 2804 pm_runtime_disable(host->dev); 2805 release: 2806 platform_set_drvdata(pdev, NULL); 2807 msdc_deinit_hw(host); 2808 msdc_gate_clock(host); 2809 release_mem: 2810 if (host->dma.gpd) 2811 dma_free_coherent(&pdev->dev, 2812 2 * sizeof(struct mt_gpdma_desc), 2813 host->dma.gpd, host->dma.gpd_addr); 2814 if (host->dma.bd) 2815 dma_free_coherent(&pdev->dev, 2816 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2817 host->dma.bd, host->dma.bd_addr); 2818 host_free: 2819 mmc_free_host(mmc); 2820 2821 return ret; 2822 } 2823 2824 static int msdc_drv_remove(struct platform_device *pdev) 2825 { 2826 struct mmc_host *mmc; 2827 struct msdc_host *host; 2828 2829 mmc = platform_get_drvdata(pdev); 2830 host = mmc_priv(mmc); 2831 2832 pm_runtime_get_sync(host->dev); 2833 2834 platform_set_drvdata(pdev, NULL); 2835 mmc_remove_host(mmc); 2836 msdc_deinit_hw(host); 2837 msdc_gate_clock(host); 2838 2839 pm_runtime_disable(host->dev); 2840 pm_runtime_put_noidle(host->dev); 2841 dma_free_coherent(&pdev->dev, 2842 2 * sizeof(struct mt_gpdma_desc), 2843 host->dma.gpd, host->dma.gpd_addr); 2844 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2845 host->dma.bd, host->dma.bd_addr); 2846 2847 mmc_free_host(mmc); 2848 2849 return 0; 2850 } 2851 2852 static void msdc_save_reg(struct msdc_host *host) 2853 { 2854 u32 tune_reg = host->dev_comp->pad_tune_reg; 2855 2856 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 2857 host->save_para.iocon = readl(host->base + MSDC_IOCON); 2858 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 2859 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 2860 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 2861 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); 2862 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 2863 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2864 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 2865 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); 2866 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); 2867 if (host->top_base) { 2868 host->save_para.emmc_top_control = 2869 readl(host->top_base + EMMC_TOP_CONTROL); 2870 host->save_para.emmc_top_cmd = 2871 readl(host->top_base + EMMC_TOP_CMD); 2872 host->save_para.emmc50_pad_ds_tune = 2873 readl(host->top_base + EMMC50_PAD_DS_TUNE); 2874 } else { 2875 host->save_para.pad_tune = readl(host->base + tune_reg); 2876 } 2877 } 2878 2879 static void msdc_restore_reg(struct msdc_host *host) 2880 { 2881 struct mmc_host *mmc = mmc_from_priv(host); 2882 u32 tune_reg = host->dev_comp->pad_tune_reg; 2883 2884 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 2885 writel(host->save_para.iocon, host->base + MSDC_IOCON); 2886 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 2887 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 2888 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 2889 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); 2890 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 2891 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 2892 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 2893 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); 2894 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); 2895 if (host->top_base) { 2896 writel(host->save_para.emmc_top_control, 2897 host->top_base + EMMC_TOP_CONTROL); 2898 writel(host->save_para.emmc_top_cmd, 2899 host->top_base + EMMC_TOP_CMD); 2900 writel(host->save_para.emmc50_pad_ds_tune, 2901 host->top_base + EMMC50_PAD_DS_TUNE); 2902 } else { 2903 writel(host->save_para.pad_tune, host->base + tune_reg); 2904 } 2905 2906 if (sdio_irq_claimed(mmc)) 2907 __msdc_enable_sdio_irq(host, 1); 2908 } 2909 2910 static int __maybe_unused msdc_runtime_suspend(struct device *dev) 2911 { 2912 struct mmc_host *mmc = dev_get_drvdata(dev); 2913 struct msdc_host *host = mmc_priv(mmc); 2914 2915 msdc_save_reg(host); 2916 2917 if (sdio_irq_claimed(mmc)) { 2918 if (host->pins_eint) { 2919 disable_irq(host->irq); 2920 pinctrl_select_state(host->pinctrl, host->pins_eint); 2921 } 2922 2923 __msdc_enable_sdio_irq(host, 0); 2924 } 2925 msdc_gate_clock(host); 2926 return 0; 2927 } 2928 2929 static int __maybe_unused msdc_runtime_resume(struct device *dev) 2930 { 2931 struct mmc_host *mmc = dev_get_drvdata(dev); 2932 struct msdc_host *host = mmc_priv(mmc); 2933 int ret; 2934 2935 ret = msdc_ungate_clock(host); 2936 if (ret) 2937 return ret; 2938 2939 msdc_restore_reg(host); 2940 2941 if (sdio_irq_claimed(mmc) && host->pins_eint) { 2942 pinctrl_select_state(host->pinctrl, host->pins_uhs); 2943 enable_irq(host->irq); 2944 } 2945 return 0; 2946 } 2947 2948 static int __maybe_unused msdc_suspend(struct device *dev) 2949 { 2950 struct mmc_host *mmc = dev_get_drvdata(dev); 2951 struct msdc_host *host = mmc_priv(mmc); 2952 int ret; 2953 u32 val; 2954 2955 if (mmc->caps2 & MMC_CAP2_CQE) { 2956 ret = cqhci_suspend(mmc); 2957 if (ret) 2958 return ret; 2959 val = readl(host->base + MSDC_INT); 2960 writel(val, host->base + MSDC_INT); 2961 } 2962 2963 /* 2964 * Bump up runtime PM usage counter otherwise dev->power.needs_force_resume will 2965 * not be marked as 1, pm_runtime_force_resume() will go out directly. 2966 */ 2967 if (sdio_irq_claimed(mmc) && host->pins_eint) 2968 pm_runtime_get_noresume(dev); 2969 2970 return pm_runtime_force_suspend(dev); 2971 } 2972 2973 static int __maybe_unused msdc_resume(struct device *dev) 2974 { 2975 struct mmc_host *mmc = dev_get_drvdata(dev); 2976 struct msdc_host *host = mmc_priv(mmc); 2977 2978 if (sdio_irq_claimed(mmc) && host->pins_eint) 2979 pm_runtime_put_noidle(dev); 2980 2981 return pm_runtime_force_resume(dev); 2982 } 2983 2984 static const struct dev_pm_ops msdc_dev_pm_ops = { 2985 SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume) 2986 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 2987 }; 2988 2989 static struct platform_driver mt_msdc_driver = { 2990 .probe = msdc_drv_probe, 2991 .remove = msdc_drv_remove, 2992 .driver = { 2993 .name = "mtk-msdc", 2994 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 2995 .of_match_table = msdc_of_ids, 2996 .pm = &msdc_dev_pm_ops, 2997 }, 2998 }; 2999 3000 module_platform_driver(mt_msdc_driver); 3001 MODULE_LICENSE("GPL v2"); 3002 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 3003