1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2015 MediaTek Inc. 4 * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 5 */ 6 7 #include <linux/module.h> 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/iopoll.h> 13 #include <linux/ioport.h> 14 #include <linux/irq.h> 15 #include <linux/of_address.h> 16 #include <linux/of_device.h> 17 #include <linux/of_irq.h> 18 #include <linux/of_gpio.h> 19 #include <linux/pinctrl/consumer.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/slab.h> 25 #include <linux/spinlock.h> 26 #include <linux/interrupt.h> 27 #include <linux/reset.h> 28 29 #include <linux/mmc/card.h> 30 #include <linux/mmc/core.h> 31 #include <linux/mmc/host.h> 32 #include <linux/mmc/mmc.h> 33 #include <linux/mmc/sd.h> 34 #include <linux/mmc/sdio.h> 35 #include <linux/mmc/slot-gpio.h> 36 37 #include "cqhci.h" 38 39 #define MAX_BD_NUM 1024 40 #define MSDC_NR_CLOCKS 3 41 42 /*--------------------------------------------------------------------------*/ 43 /* Common Definition */ 44 /*--------------------------------------------------------------------------*/ 45 #define MSDC_BUS_1BITS 0x0 46 #define MSDC_BUS_4BITS 0x1 47 #define MSDC_BUS_8BITS 0x2 48 49 #define MSDC_BURST_64B 0x6 50 51 /*--------------------------------------------------------------------------*/ 52 /* Register Offset */ 53 /*--------------------------------------------------------------------------*/ 54 #define MSDC_CFG 0x0 55 #define MSDC_IOCON 0x04 56 #define MSDC_PS 0x08 57 #define MSDC_INT 0x0c 58 #define MSDC_INTEN 0x10 59 #define MSDC_FIFOCS 0x14 60 #define SDC_CFG 0x30 61 #define SDC_CMD 0x34 62 #define SDC_ARG 0x38 63 #define SDC_STS 0x3c 64 #define SDC_RESP0 0x40 65 #define SDC_RESP1 0x44 66 #define SDC_RESP2 0x48 67 #define SDC_RESP3 0x4c 68 #define SDC_BLK_NUM 0x50 69 #define SDC_ADV_CFG0 0x64 70 #define EMMC_IOCON 0x7c 71 #define SDC_ACMD_RESP 0x80 72 #define DMA_SA_H4BIT 0x8c 73 #define MSDC_DMA_SA 0x90 74 #define MSDC_DMA_CTRL 0x98 75 #define MSDC_DMA_CFG 0x9c 76 #define MSDC_PATCH_BIT 0xb0 77 #define MSDC_PATCH_BIT1 0xb4 78 #define MSDC_PATCH_BIT2 0xb8 79 #define MSDC_PAD_TUNE 0xec 80 #define MSDC_PAD_TUNE0 0xf0 81 #define PAD_DS_TUNE 0x188 82 #define PAD_CMD_TUNE 0x18c 83 #define EMMC51_CFG0 0x204 84 #define EMMC50_CFG0 0x208 85 #define EMMC50_CFG1 0x20c 86 #define EMMC50_CFG3 0x220 87 #define SDC_FIFO_CFG 0x228 88 #define CQHCI_SETTING 0x7fc 89 90 /*--------------------------------------------------------------------------*/ 91 /* Top Pad Register Offset */ 92 /*--------------------------------------------------------------------------*/ 93 #define EMMC_TOP_CONTROL 0x00 94 #define EMMC_TOP_CMD 0x04 95 #define EMMC50_PAD_DS_TUNE 0x0c 96 97 /*--------------------------------------------------------------------------*/ 98 /* Register Mask */ 99 /*--------------------------------------------------------------------------*/ 100 101 /* MSDC_CFG mask */ 102 #define MSDC_CFG_MODE BIT(0) /* RW */ 103 #define MSDC_CFG_CKPDN BIT(1) /* RW */ 104 #define MSDC_CFG_RST BIT(2) /* RW */ 105 #define MSDC_CFG_PIO BIT(3) /* RW */ 106 #define MSDC_CFG_CKDRVEN BIT(4) /* RW */ 107 #define MSDC_CFG_BV18SDT BIT(5) /* RW */ 108 #define MSDC_CFG_BV18PSS BIT(6) /* R */ 109 #define MSDC_CFG_CKSTB BIT(7) /* R */ 110 #define MSDC_CFG_CKDIV GENMASK(15, 8) /* RW */ 111 #define MSDC_CFG_CKMOD GENMASK(17, 16) /* RW */ 112 #define MSDC_CFG_HS400_CK_MODE BIT(18) /* RW */ 113 #define MSDC_CFG_HS400_CK_MODE_EXTRA BIT(22) /* RW */ 114 #define MSDC_CFG_CKDIV_EXTRA GENMASK(19, 8) /* RW */ 115 #define MSDC_CFG_CKMOD_EXTRA GENMASK(21, 20) /* RW */ 116 117 /* MSDC_IOCON mask */ 118 #define MSDC_IOCON_SDR104CKS BIT(0) /* RW */ 119 #define MSDC_IOCON_RSPL BIT(1) /* RW */ 120 #define MSDC_IOCON_DSPL BIT(2) /* RW */ 121 #define MSDC_IOCON_DDLSEL BIT(3) /* RW */ 122 #define MSDC_IOCON_DDR50CKD BIT(4) /* RW */ 123 #define MSDC_IOCON_DSPLSEL BIT(5) /* RW */ 124 #define MSDC_IOCON_W_DSPL BIT(8) /* RW */ 125 #define MSDC_IOCON_D0SPL BIT(16) /* RW */ 126 #define MSDC_IOCON_D1SPL BIT(17) /* RW */ 127 #define MSDC_IOCON_D2SPL BIT(18) /* RW */ 128 #define MSDC_IOCON_D3SPL BIT(19) /* RW */ 129 #define MSDC_IOCON_D4SPL BIT(20) /* RW */ 130 #define MSDC_IOCON_D5SPL BIT(21) /* RW */ 131 #define MSDC_IOCON_D6SPL BIT(22) /* RW */ 132 #define MSDC_IOCON_D7SPL BIT(23) /* RW */ 133 #define MSDC_IOCON_RISCSZ GENMASK(25, 24) /* RW */ 134 135 /* MSDC_PS mask */ 136 #define MSDC_PS_CDEN BIT(0) /* RW */ 137 #define MSDC_PS_CDSTS BIT(1) /* R */ 138 #define MSDC_PS_CDDEBOUNCE GENMASK(15, 12) /* RW */ 139 #define MSDC_PS_DAT GENMASK(23, 16) /* R */ 140 #define MSDC_PS_DATA1 BIT(17) /* R */ 141 #define MSDC_PS_CMD BIT(24) /* R */ 142 #define MSDC_PS_WP BIT(31) /* R */ 143 144 /* MSDC_INT mask */ 145 #define MSDC_INT_MMCIRQ BIT(0) /* W1C */ 146 #define MSDC_INT_CDSC BIT(1) /* W1C */ 147 #define MSDC_INT_ACMDRDY BIT(3) /* W1C */ 148 #define MSDC_INT_ACMDTMO BIT(4) /* W1C */ 149 #define MSDC_INT_ACMDCRCERR BIT(5) /* W1C */ 150 #define MSDC_INT_DMAQ_EMPTY BIT(6) /* W1C */ 151 #define MSDC_INT_SDIOIRQ BIT(7) /* W1C */ 152 #define MSDC_INT_CMDRDY BIT(8) /* W1C */ 153 #define MSDC_INT_CMDTMO BIT(9) /* W1C */ 154 #define MSDC_INT_RSPCRCERR BIT(10) /* W1C */ 155 #define MSDC_INT_CSTA BIT(11) /* R */ 156 #define MSDC_INT_XFER_COMPL BIT(12) /* W1C */ 157 #define MSDC_INT_DXFER_DONE BIT(13) /* W1C */ 158 #define MSDC_INT_DATTMO BIT(14) /* W1C */ 159 #define MSDC_INT_DATCRCERR BIT(15) /* W1C */ 160 #define MSDC_INT_ACMD19_DONE BIT(16) /* W1C */ 161 #define MSDC_INT_DMA_BDCSERR BIT(17) /* W1C */ 162 #define MSDC_INT_DMA_GPDCSERR BIT(18) /* W1C */ 163 #define MSDC_INT_DMA_PROTECT BIT(19) /* W1C */ 164 #define MSDC_INT_CMDQ BIT(28) /* W1C */ 165 166 /* MSDC_INTEN mask */ 167 #define MSDC_INTEN_MMCIRQ BIT(0) /* RW */ 168 #define MSDC_INTEN_CDSC BIT(1) /* RW */ 169 #define MSDC_INTEN_ACMDRDY BIT(3) /* RW */ 170 #define MSDC_INTEN_ACMDTMO BIT(4) /* RW */ 171 #define MSDC_INTEN_ACMDCRCERR BIT(5) /* RW */ 172 #define MSDC_INTEN_DMAQ_EMPTY BIT(6) /* RW */ 173 #define MSDC_INTEN_SDIOIRQ BIT(7) /* RW */ 174 #define MSDC_INTEN_CMDRDY BIT(8) /* RW */ 175 #define MSDC_INTEN_CMDTMO BIT(9) /* RW */ 176 #define MSDC_INTEN_RSPCRCERR BIT(10) /* RW */ 177 #define MSDC_INTEN_CSTA BIT(11) /* RW */ 178 #define MSDC_INTEN_XFER_COMPL BIT(12) /* RW */ 179 #define MSDC_INTEN_DXFER_DONE BIT(13) /* RW */ 180 #define MSDC_INTEN_DATTMO BIT(14) /* RW */ 181 #define MSDC_INTEN_DATCRCERR BIT(15) /* RW */ 182 #define MSDC_INTEN_ACMD19_DONE BIT(16) /* RW */ 183 #define MSDC_INTEN_DMA_BDCSERR BIT(17) /* RW */ 184 #define MSDC_INTEN_DMA_GPDCSERR BIT(18) /* RW */ 185 #define MSDC_INTEN_DMA_PROTECT BIT(19) /* RW */ 186 187 /* MSDC_FIFOCS mask */ 188 #define MSDC_FIFOCS_RXCNT GENMASK(7, 0) /* R */ 189 #define MSDC_FIFOCS_TXCNT GENMASK(23, 16) /* R */ 190 #define MSDC_FIFOCS_CLR BIT(31) /* RW */ 191 192 /* SDC_CFG mask */ 193 #define SDC_CFG_SDIOINTWKUP BIT(0) /* RW */ 194 #define SDC_CFG_INSWKUP BIT(1) /* RW */ 195 #define SDC_CFG_WRDTOC GENMASK(14, 2) /* RW */ 196 #define SDC_CFG_BUSWIDTH GENMASK(17, 16) /* RW */ 197 #define SDC_CFG_SDIO BIT(19) /* RW */ 198 #define SDC_CFG_SDIOIDE BIT(20) /* RW */ 199 #define SDC_CFG_INTATGAP BIT(21) /* RW */ 200 #define SDC_CFG_DTOC GENMASK(31, 24) /* RW */ 201 202 /* SDC_STS mask */ 203 #define SDC_STS_SDCBUSY BIT(0) /* RW */ 204 #define SDC_STS_CMDBUSY BIT(1) /* RW */ 205 #define SDC_STS_SWR_COMPL BIT(31) /* RW */ 206 207 #define SDC_DAT1_IRQ_TRIGGER BIT(19) /* RW */ 208 /* SDC_ADV_CFG0 mask */ 209 #define SDC_RX_ENHANCE_EN BIT(20) /* RW */ 210 211 /* DMA_SA_H4BIT mask */ 212 #define DMA_ADDR_HIGH_4BIT GENMASK(3, 0) /* RW */ 213 214 /* MSDC_DMA_CTRL mask */ 215 #define MSDC_DMA_CTRL_START BIT(0) /* W */ 216 #define MSDC_DMA_CTRL_STOP BIT(1) /* W */ 217 #define MSDC_DMA_CTRL_RESUME BIT(2) /* W */ 218 #define MSDC_DMA_CTRL_MODE BIT(8) /* RW */ 219 #define MSDC_DMA_CTRL_LASTBUF BIT(10) /* RW */ 220 #define MSDC_DMA_CTRL_BRUSTSZ GENMASK(14, 12) /* RW */ 221 222 /* MSDC_DMA_CFG mask */ 223 #define MSDC_DMA_CFG_STS BIT(0) /* R */ 224 #define MSDC_DMA_CFG_DECSEN BIT(1) /* RW */ 225 #define MSDC_DMA_CFG_AHBHPROT2 BIT(9) /* RW */ 226 #define MSDC_DMA_CFG_ACTIVEEN BIT(13) /* RW */ 227 #define MSDC_DMA_CFG_CS12B16B BIT(16) /* RW */ 228 229 /* MSDC_PATCH_BIT mask */ 230 #define MSDC_PATCH_BIT_ODDSUPP BIT(1) /* RW */ 231 #define MSDC_INT_DAT_LATCH_CK_SEL GENMASK(9, 7) 232 #define MSDC_CKGEN_MSDC_DLY_SEL GENMASK(14, 10) 233 #define MSDC_PATCH_BIT_IODSSEL BIT(16) /* RW */ 234 #define MSDC_PATCH_BIT_IOINTSEL BIT(17) /* RW */ 235 #define MSDC_PATCH_BIT_BUSYDLY GENMASK(21, 18) /* RW */ 236 #define MSDC_PATCH_BIT_WDOD GENMASK(25, 22) /* RW */ 237 #define MSDC_PATCH_BIT_IDRTSEL BIT(26) /* RW */ 238 #define MSDC_PATCH_BIT_CMDFSEL BIT(27) /* RW */ 239 #define MSDC_PATCH_BIT_INTDLSEL BIT(28) /* RW */ 240 #define MSDC_PATCH_BIT_SPCPUSH BIT(29) /* RW */ 241 #define MSDC_PATCH_BIT_DECRCTMO BIT(30) /* RW */ 242 243 #define MSDC_PATCH_BIT1_CMDTA GENMASK(5, 3) /* RW */ 244 #define MSDC_PB1_BUSY_CHECK_SEL BIT(7) /* RW */ 245 #define MSDC_PATCH_BIT1_STOP_DLY GENMASK(11, 8) /* RW */ 246 247 #define MSDC_PATCH_BIT2_CFGRESP BIT(15) /* RW */ 248 #define MSDC_PATCH_BIT2_CFGCRCSTS BIT(28) /* RW */ 249 #define MSDC_PB2_SUPPORT_64G BIT(1) /* RW */ 250 #define MSDC_PB2_RESPWAIT GENMASK(3, 2) /* RW */ 251 #define MSDC_PB2_RESPSTSENSEL GENMASK(18, 16) /* RW */ 252 #define MSDC_PB2_CRCSTSENSEL GENMASK(31, 29) /* RW */ 253 254 #define MSDC_PAD_TUNE_DATWRDLY GENMASK(4, 0) /* RW */ 255 #define MSDC_PAD_TUNE_DATRRDLY GENMASK(12, 8) /* RW */ 256 #define MSDC_PAD_TUNE_CMDRDLY GENMASK(20, 16) /* RW */ 257 #define MSDC_PAD_TUNE_CMDRRDLY GENMASK(26, 22) /* RW */ 258 #define MSDC_PAD_TUNE_CLKTDLY GENMASK(31, 27) /* RW */ 259 #define MSDC_PAD_TUNE_RXDLYSEL BIT(15) /* RW */ 260 #define MSDC_PAD_TUNE_RD_SEL BIT(13) /* RW */ 261 #define MSDC_PAD_TUNE_CMD_SEL BIT(21) /* RW */ 262 263 #define PAD_DS_TUNE_DLY_SEL BIT(0) /* RW */ 264 #define PAD_DS_TUNE_DLY1 GENMASK(6, 2) /* RW */ 265 #define PAD_DS_TUNE_DLY2 GENMASK(11, 7) /* RW */ 266 #define PAD_DS_TUNE_DLY3 GENMASK(16, 12) /* RW */ 267 268 #define PAD_CMD_TUNE_RX_DLY3 GENMASK(5, 1) /* RW */ 269 270 /* EMMC51_CFG0 mask */ 271 #define CMDQ_RDAT_CNT GENMASK(21, 12) /* RW */ 272 273 #define EMMC50_CFG_PADCMD_LATCHCK BIT(0) /* RW */ 274 #define EMMC50_CFG_CRCSTS_EDGE BIT(3) /* RW */ 275 #define EMMC50_CFG_CFCSTS_SEL BIT(4) /* RW */ 276 #define EMMC50_CFG_CMD_RESP_SEL BIT(9) /* RW */ 277 278 /* EMMC50_CFG1 mask */ 279 #define EMMC50_CFG1_DS_CFG BIT(28) /* RW */ 280 281 #define EMMC50_CFG3_OUTS_WR GENMASK(4, 0) /* RW */ 282 283 #define SDC_FIFO_CFG_WRVALIDSEL BIT(24) /* RW */ 284 #define SDC_FIFO_CFG_RDVALIDSEL BIT(25) /* RW */ 285 286 /* CQHCI_SETTING */ 287 #define CQHCI_RD_CMD_WND_SEL BIT(14) /* RW */ 288 #define CQHCI_WR_CMD_WND_SEL BIT(15) /* RW */ 289 290 /* EMMC_TOP_CONTROL mask */ 291 #define PAD_RXDLY_SEL BIT(0) /* RW */ 292 #define DELAY_EN BIT(1) /* RW */ 293 #define PAD_DAT_RD_RXDLY2 GENMASK(6, 2) /* RW */ 294 #define PAD_DAT_RD_RXDLY GENMASK(11, 7) /* RW */ 295 #define PAD_DAT_RD_RXDLY2_SEL BIT(12) /* RW */ 296 #define PAD_DAT_RD_RXDLY_SEL BIT(13) /* RW */ 297 #define DATA_K_VALUE_SEL BIT(14) /* RW */ 298 #define SDC_RX_ENH_EN BIT(15) /* TW */ 299 300 /* EMMC_TOP_CMD mask */ 301 #define PAD_CMD_RXDLY2 GENMASK(4, 0) /* RW */ 302 #define PAD_CMD_RXDLY GENMASK(9, 5) /* RW */ 303 #define PAD_CMD_RD_RXDLY2_SEL BIT(10) /* RW */ 304 #define PAD_CMD_RD_RXDLY_SEL BIT(11) /* RW */ 305 #define PAD_CMD_TX_DLY GENMASK(16, 12) /* RW */ 306 307 /* EMMC50_PAD_DS_TUNE mask */ 308 #define PAD_DS_DLY_SEL BIT(16) /* RW */ 309 #define PAD_DS_DLY1 GENMASK(14, 10) /* RW */ 310 #define PAD_DS_DLY3 GENMASK(4, 0) /* RW */ 311 312 #define REQ_CMD_EIO BIT(0) 313 #define REQ_CMD_TMO BIT(1) 314 #define REQ_DAT_ERR BIT(2) 315 #define REQ_STOP_EIO BIT(3) 316 #define REQ_STOP_TMO BIT(4) 317 #define REQ_CMD_BUSY BIT(5) 318 319 #define MSDC_PREPARE_FLAG BIT(0) 320 #define MSDC_ASYNC_FLAG BIT(1) 321 #define MSDC_MMAP_FLAG BIT(2) 322 323 #define MTK_MMC_AUTOSUSPEND_DELAY 50 324 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 325 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 326 327 #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */ 328 329 #define PAD_DELAY_MAX 32 /* PAD delay cells */ 330 /*--------------------------------------------------------------------------*/ 331 /* Descriptor Structure */ 332 /*--------------------------------------------------------------------------*/ 333 struct mt_gpdma_desc { 334 u32 gpd_info; 335 #define GPDMA_DESC_HWO BIT(0) 336 #define GPDMA_DESC_BDP BIT(1) 337 #define GPDMA_DESC_CHECKSUM GENMASK(15, 8) 338 #define GPDMA_DESC_INT BIT(16) 339 #define GPDMA_DESC_NEXT_H4 GENMASK(27, 24) 340 #define GPDMA_DESC_PTR_H4 GENMASK(31, 28) 341 u32 next; 342 u32 ptr; 343 u32 gpd_data_len; 344 #define GPDMA_DESC_BUFLEN GENMASK(15, 0) 345 #define GPDMA_DESC_EXTLEN GENMASK(23, 16) 346 u32 arg; 347 u32 blknum; 348 u32 cmd; 349 }; 350 351 struct mt_bdma_desc { 352 u32 bd_info; 353 #define BDMA_DESC_EOL BIT(0) 354 #define BDMA_DESC_CHECKSUM GENMASK(15, 8) 355 #define BDMA_DESC_BLKPAD BIT(17) 356 #define BDMA_DESC_DWPAD BIT(18) 357 #define BDMA_DESC_NEXT_H4 GENMASK(27, 24) 358 #define BDMA_DESC_PTR_H4 GENMASK(31, 28) 359 u32 next; 360 u32 ptr; 361 u32 bd_data_len; 362 #define BDMA_DESC_BUFLEN GENMASK(15, 0) 363 #define BDMA_DESC_BUFLEN_EXT GENMASK(23, 0) 364 }; 365 366 struct msdc_dma { 367 struct scatterlist *sg; /* I/O scatter list */ 368 struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 369 struct mt_bdma_desc *bd; /* pointer to bd array */ 370 dma_addr_t gpd_addr; /* the physical address of gpd array */ 371 dma_addr_t bd_addr; /* the physical address of bd array */ 372 }; 373 374 struct msdc_save_para { 375 u32 msdc_cfg; 376 u32 iocon; 377 u32 sdc_cfg; 378 u32 pad_tune; 379 u32 patch_bit0; 380 u32 patch_bit1; 381 u32 patch_bit2; 382 u32 pad_ds_tune; 383 u32 pad_cmd_tune; 384 u32 emmc50_cfg0; 385 u32 emmc50_cfg3; 386 u32 sdc_fifo_cfg; 387 u32 emmc_top_control; 388 u32 emmc_top_cmd; 389 u32 emmc50_pad_ds_tune; 390 }; 391 392 struct mtk_mmc_compatible { 393 u8 clk_div_bits; 394 bool recheck_sdio_irq; 395 bool hs400_tune; /* only used for MT8173 */ 396 u32 pad_tune_reg; 397 bool async_fifo; 398 bool data_tune; 399 bool busy_check; 400 bool stop_clk_fix; 401 bool enhance_rx; 402 bool support_64g; 403 bool use_internal_cd; 404 }; 405 406 struct msdc_tune_para { 407 u32 iocon; 408 u32 pad_tune; 409 u32 pad_cmd_tune; 410 u32 emmc_top_control; 411 u32 emmc_top_cmd; 412 }; 413 414 struct msdc_delay_phase { 415 u8 maxlen; 416 u8 start; 417 u8 final_phase; 418 }; 419 420 struct msdc_host { 421 struct device *dev; 422 const struct mtk_mmc_compatible *dev_comp; 423 int cmd_rsp; 424 425 spinlock_t lock; 426 struct mmc_request *mrq; 427 struct mmc_command *cmd; 428 struct mmc_data *data; 429 int error; 430 431 void __iomem *base; /* host base address */ 432 void __iomem *top_base; /* host top register base address */ 433 434 struct msdc_dma dma; /* dma channel */ 435 u64 dma_mask; 436 437 u32 timeout_ns; /* data timeout ns */ 438 u32 timeout_clks; /* data timeout clks */ 439 440 struct pinctrl *pinctrl; 441 struct pinctrl_state *pins_default; 442 struct pinctrl_state *pins_uhs; 443 struct delayed_work req_timeout; 444 int irq; /* host interrupt */ 445 struct reset_control *reset; 446 447 struct clk *src_clk; /* msdc source clock */ 448 struct clk *h_clk; /* msdc h_clk */ 449 struct clk *bus_clk; /* bus clock which used to access register */ 450 struct clk *src_clk_cg; /* msdc source clock control gate */ 451 struct clk *sys_clk_cg; /* msdc subsys clock control gate */ 452 struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS]; 453 u32 mclk; /* mmc subsystem clock frequency */ 454 u32 src_clk_freq; /* source clock frequency */ 455 unsigned char timing; 456 bool vqmmc_enabled; 457 u32 latch_ck; 458 u32 hs400_ds_delay; 459 u32 hs400_ds_dly3; 460 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 461 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 462 bool hs400_cmd_resp_sel_rising; 463 /* cmd response sample selection for HS400 */ 464 bool hs400_mode; /* current eMMC will run at hs400 mode */ 465 bool hs400_tuning; /* hs400 mode online tuning */ 466 bool internal_cd; /* Use internal card-detect logic */ 467 bool cqhci; /* support eMMC hw cmdq */ 468 struct msdc_save_para save_para; /* used when gate HCLK */ 469 struct msdc_tune_para def_tune_para; /* default tune setting */ 470 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 471 struct cqhci_host *cq_host; 472 }; 473 474 static const struct mtk_mmc_compatible mt8135_compat = { 475 .clk_div_bits = 8, 476 .recheck_sdio_irq = true, 477 .hs400_tune = false, 478 .pad_tune_reg = MSDC_PAD_TUNE, 479 .async_fifo = false, 480 .data_tune = false, 481 .busy_check = false, 482 .stop_clk_fix = false, 483 .enhance_rx = false, 484 .support_64g = false, 485 }; 486 487 static const struct mtk_mmc_compatible mt8173_compat = { 488 .clk_div_bits = 8, 489 .recheck_sdio_irq = true, 490 .hs400_tune = true, 491 .pad_tune_reg = MSDC_PAD_TUNE, 492 .async_fifo = false, 493 .data_tune = false, 494 .busy_check = false, 495 .stop_clk_fix = false, 496 .enhance_rx = false, 497 .support_64g = false, 498 }; 499 500 static const struct mtk_mmc_compatible mt8183_compat = { 501 .clk_div_bits = 12, 502 .recheck_sdio_irq = false, 503 .hs400_tune = false, 504 .pad_tune_reg = MSDC_PAD_TUNE0, 505 .async_fifo = true, 506 .data_tune = true, 507 .busy_check = true, 508 .stop_clk_fix = true, 509 .enhance_rx = true, 510 .support_64g = true, 511 }; 512 513 static const struct mtk_mmc_compatible mt2701_compat = { 514 .clk_div_bits = 12, 515 .recheck_sdio_irq = true, 516 .hs400_tune = false, 517 .pad_tune_reg = MSDC_PAD_TUNE0, 518 .async_fifo = true, 519 .data_tune = true, 520 .busy_check = false, 521 .stop_clk_fix = false, 522 .enhance_rx = false, 523 .support_64g = false, 524 }; 525 526 static const struct mtk_mmc_compatible mt2712_compat = { 527 .clk_div_bits = 12, 528 .recheck_sdio_irq = false, 529 .hs400_tune = false, 530 .pad_tune_reg = MSDC_PAD_TUNE0, 531 .async_fifo = true, 532 .data_tune = true, 533 .busy_check = true, 534 .stop_clk_fix = true, 535 .enhance_rx = true, 536 .support_64g = true, 537 }; 538 539 static const struct mtk_mmc_compatible mt7622_compat = { 540 .clk_div_bits = 12, 541 .recheck_sdio_irq = true, 542 .hs400_tune = false, 543 .pad_tune_reg = MSDC_PAD_TUNE0, 544 .async_fifo = true, 545 .data_tune = true, 546 .busy_check = true, 547 .stop_clk_fix = true, 548 .enhance_rx = true, 549 .support_64g = false, 550 }; 551 552 static const struct mtk_mmc_compatible mt8516_compat = { 553 .clk_div_bits = 12, 554 .recheck_sdio_irq = true, 555 .hs400_tune = false, 556 .pad_tune_reg = MSDC_PAD_TUNE0, 557 .async_fifo = true, 558 .data_tune = true, 559 .busy_check = true, 560 .stop_clk_fix = true, 561 }; 562 563 static const struct mtk_mmc_compatible mt7620_compat = { 564 .clk_div_bits = 8, 565 .recheck_sdio_irq = true, 566 .hs400_tune = false, 567 .pad_tune_reg = MSDC_PAD_TUNE, 568 .async_fifo = false, 569 .data_tune = false, 570 .busy_check = false, 571 .stop_clk_fix = false, 572 .enhance_rx = false, 573 .use_internal_cd = true, 574 }; 575 576 static const struct mtk_mmc_compatible mt6779_compat = { 577 .clk_div_bits = 12, 578 .recheck_sdio_irq = false, 579 .hs400_tune = false, 580 .pad_tune_reg = MSDC_PAD_TUNE0, 581 .async_fifo = true, 582 .data_tune = true, 583 .busy_check = true, 584 .stop_clk_fix = true, 585 .enhance_rx = true, 586 .support_64g = true, 587 }; 588 589 static const struct of_device_id msdc_of_ids[] = { 590 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, 591 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, 592 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, 593 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, 594 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, 595 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, 596 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, 597 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, 598 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, 599 {} 600 }; 601 MODULE_DEVICE_TABLE(of, msdc_of_ids); 602 603 static void sdr_set_bits(void __iomem *reg, u32 bs) 604 { 605 u32 val = readl(reg); 606 607 val |= bs; 608 writel(val, reg); 609 } 610 611 static void sdr_clr_bits(void __iomem *reg, u32 bs) 612 { 613 u32 val = readl(reg); 614 615 val &= ~bs; 616 writel(val, reg); 617 } 618 619 static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 620 { 621 unsigned int tv = readl(reg); 622 623 tv &= ~field; 624 tv |= ((val) << (ffs((unsigned int)field) - 1)); 625 writel(tv, reg); 626 } 627 628 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 629 { 630 unsigned int tv = readl(reg); 631 632 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 633 } 634 635 static void msdc_reset_hw(struct msdc_host *host) 636 { 637 u32 val; 638 639 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 640 readl_poll_timeout(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0); 641 642 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 643 readl_poll_timeout(host->base + MSDC_FIFOCS, val, 644 !(val & MSDC_FIFOCS_CLR), 0, 0); 645 646 val = readl(host->base + MSDC_INT); 647 writel(val, host->base + MSDC_INT); 648 } 649 650 static void msdc_cmd_next(struct msdc_host *host, 651 struct mmc_request *mrq, struct mmc_command *cmd); 652 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb); 653 654 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 655 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 656 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 657 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 658 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 659 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 660 661 static u8 msdc_dma_calcs(u8 *buf, u32 len) 662 { 663 u32 i, sum = 0; 664 665 for (i = 0; i < len; i++) 666 sum += buf[i]; 667 return 0xff - (u8) sum; 668 } 669 670 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 671 struct mmc_data *data) 672 { 673 unsigned int j, dma_len; 674 dma_addr_t dma_address; 675 u32 dma_ctrl; 676 struct scatterlist *sg; 677 struct mt_gpdma_desc *gpd; 678 struct mt_bdma_desc *bd; 679 680 sg = data->sg; 681 682 gpd = dma->gpd; 683 bd = dma->bd; 684 685 /* modify gpd */ 686 gpd->gpd_info |= GPDMA_DESC_HWO; 687 gpd->gpd_info |= GPDMA_DESC_BDP; 688 /* need to clear first. use these bits to calc checksum */ 689 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 690 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 691 692 /* modify bd */ 693 for_each_sg(data->sg, sg, data->sg_count, j) { 694 dma_address = sg_dma_address(sg); 695 dma_len = sg_dma_len(sg); 696 697 /* init bd */ 698 bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 699 bd[j].bd_info &= ~BDMA_DESC_DWPAD; 700 bd[j].ptr = lower_32_bits(dma_address); 701 if (host->dev_comp->support_64g) { 702 bd[j].bd_info &= ~BDMA_DESC_PTR_H4; 703 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf) 704 << 28; 705 } 706 707 if (host->dev_comp->support_64g) { 708 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT; 709 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT); 710 } else { 711 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 712 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 713 } 714 715 if (j == data->sg_count - 1) /* the last bd */ 716 bd[j].bd_info |= BDMA_DESC_EOL; 717 else 718 bd[j].bd_info &= ~BDMA_DESC_EOL; 719 720 /* checksume need to clear first */ 721 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 722 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 723 } 724 725 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 726 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 727 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 728 dma_ctrl |= (MSDC_BURST_64B << 12 | BIT(8)); 729 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 730 if (host->dev_comp->support_64g) 731 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, 732 upper_32_bits(dma->gpd_addr) & 0xf); 733 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); 734 } 735 736 static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data) 737 { 738 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 739 data->host_cookie |= MSDC_PREPARE_FLAG; 740 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 741 mmc_get_dma_dir(data)); 742 } 743 } 744 745 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data) 746 { 747 if (data->host_cookie & MSDC_ASYNC_FLAG) 748 return; 749 750 if (data->host_cookie & MSDC_PREPARE_FLAG) { 751 dma_unmap_sg(host->dev, data->sg, data->sg_len, 752 mmc_get_dma_dir(data)); 753 data->host_cookie &= ~MSDC_PREPARE_FLAG; 754 } 755 } 756 757 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) 758 { 759 struct mmc_host *mmc = mmc_from_priv(host); 760 u64 timeout, clk_ns; 761 u32 mode = 0; 762 763 if (mmc->actual_clock == 0) { 764 timeout = 0; 765 } else { 766 clk_ns = 1000000000ULL; 767 do_div(clk_ns, mmc->actual_clock); 768 timeout = ns + clk_ns - 1; 769 do_div(timeout, clk_ns); 770 timeout += clks; 771 /* in 1048576 sclk cycle unit */ 772 timeout = DIV_ROUND_UP(timeout, BIT(20)); 773 if (host->dev_comp->clk_div_bits == 8) 774 sdr_get_field(host->base + MSDC_CFG, 775 MSDC_CFG_CKMOD, &mode); 776 else 777 sdr_get_field(host->base + MSDC_CFG, 778 MSDC_CFG_CKMOD_EXTRA, &mode); 779 /*DDR mode will double the clk cycles for data timeout */ 780 timeout = mode >= 2 ? timeout * 2 : timeout; 781 timeout = timeout > 1 ? timeout - 1 : 0; 782 } 783 return timeout; 784 } 785 786 /* clock control primitives */ 787 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) 788 { 789 u64 timeout; 790 791 host->timeout_ns = ns; 792 host->timeout_clks = clks; 793 794 timeout = msdc_timeout_cal(host, ns, clks); 795 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 796 (u32)(timeout > 255 ? 255 : timeout)); 797 } 798 799 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) 800 { 801 u64 timeout; 802 803 timeout = msdc_timeout_cal(host, ns, clks); 804 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, 805 (u32)(timeout > 8191 ? 8191 : timeout)); 806 } 807 808 static void msdc_gate_clock(struct msdc_host *host) 809 { 810 clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); 811 clk_disable_unprepare(host->src_clk_cg); 812 clk_disable_unprepare(host->src_clk); 813 clk_disable_unprepare(host->bus_clk); 814 clk_disable_unprepare(host->h_clk); 815 } 816 817 static int msdc_ungate_clock(struct msdc_host *host) 818 { 819 u32 val; 820 int ret; 821 822 clk_prepare_enable(host->h_clk); 823 clk_prepare_enable(host->bus_clk); 824 clk_prepare_enable(host->src_clk); 825 clk_prepare_enable(host->src_clk_cg); 826 ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); 827 if (ret) { 828 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); 829 return ret; 830 } 831 832 return readl_poll_timeout(host->base + MSDC_CFG, val, 833 (val & MSDC_CFG_CKSTB), 1, 20000); 834 } 835 836 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 837 { 838 struct mmc_host *mmc = mmc_from_priv(host); 839 u32 mode; 840 u32 flags; 841 u32 div; 842 u32 sclk; 843 u32 tune_reg = host->dev_comp->pad_tune_reg; 844 u32 val; 845 846 if (!hz) { 847 dev_dbg(host->dev, "set mclk to 0\n"); 848 host->mclk = 0; 849 mmc->actual_clock = 0; 850 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 851 return; 852 } 853 854 flags = readl(host->base + MSDC_INTEN); 855 sdr_clr_bits(host->base + MSDC_INTEN, flags); 856 if (host->dev_comp->clk_div_bits == 8) 857 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 858 else 859 sdr_clr_bits(host->base + MSDC_CFG, 860 MSDC_CFG_HS400_CK_MODE_EXTRA); 861 if (timing == MMC_TIMING_UHS_DDR50 || 862 timing == MMC_TIMING_MMC_DDR52 || 863 timing == MMC_TIMING_MMC_HS400) { 864 if (timing == MMC_TIMING_MMC_HS400) 865 mode = 0x3; 866 else 867 mode = 0x2; /* ddr mode and use divisor */ 868 869 if (hz >= (host->src_clk_freq >> 2)) { 870 div = 0; /* mean div = 1/4 */ 871 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 872 } else { 873 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 874 sclk = (host->src_clk_freq >> 2) / div; 875 div = (div >> 1); 876 } 877 878 if (timing == MMC_TIMING_MMC_HS400 && 879 hz >= (host->src_clk_freq >> 1)) { 880 if (host->dev_comp->clk_div_bits == 8) 881 sdr_set_bits(host->base + MSDC_CFG, 882 MSDC_CFG_HS400_CK_MODE); 883 else 884 sdr_set_bits(host->base + MSDC_CFG, 885 MSDC_CFG_HS400_CK_MODE_EXTRA); 886 sclk = host->src_clk_freq >> 1; 887 div = 0; /* div is ignore when bit18 is set */ 888 } 889 } else if (hz >= host->src_clk_freq) { 890 mode = 0x1; /* no divisor */ 891 div = 0; 892 sclk = host->src_clk_freq; 893 } else { 894 mode = 0x0; /* use divisor */ 895 if (hz >= (host->src_clk_freq >> 1)) { 896 div = 0; /* mean div = 1/2 */ 897 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 898 } else { 899 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 900 sclk = (host->src_clk_freq >> 2) / div; 901 } 902 } 903 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 904 905 clk_disable_unprepare(host->src_clk_cg); 906 if (host->dev_comp->clk_div_bits == 8) 907 sdr_set_field(host->base + MSDC_CFG, 908 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 909 (mode << 8) | div); 910 else 911 sdr_set_field(host->base + MSDC_CFG, 912 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, 913 (mode << 12) | div); 914 915 clk_prepare_enable(host->src_clk_cg); 916 readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0); 917 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 918 mmc->actual_clock = sclk; 919 host->mclk = hz; 920 host->timing = timing; 921 /* need because clk changed. */ 922 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 923 sdr_set_bits(host->base + MSDC_INTEN, flags); 924 925 /* 926 * mmc_select_hs400() will drop to 50Mhz and High speed mode, 927 * tune result of hs200/200Mhz is not suitable for 50Mhz 928 */ 929 if (mmc->actual_clock <= 52000000) { 930 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 931 if (host->top_base) { 932 writel(host->def_tune_para.emmc_top_control, 933 host->top_base + EMMC_TOP_CONTROL); 934 writel(host->def_tune_para.emmc_top_cmd, 935 host->top_base + EMMC_TOP_CMD); 936 } else { 937 writel(host->def_tune_para.pad_tune, 938 host->base + tune_reg); 939 } 940 } else { 941 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 942 writel(host->saved_tune_para.pad_cmd_tune, 943 host->base + PAD_CMD_TUNE); 944 if (host->top_base) { 945 writel(host->saved_tune_para.emmc_top_control, 946 host->top_base + EMMC_TOP_CONTROL); 947 writel(host->saved_tune_para.emmc_top_cmd, 948 host->top_base + EMMC_TOP_CMD); 949 } else { 950 writel(host->saved_tune_para.pad_tune, 951 host->base + tune_reg); 952 } 953 } 954 955 if (timing == MMC_TIMING_MMC_HS400 && 956 host->dev_comp->hs400_tune) 957 sdr_set_field(host->base + tune_reg, 958 MSDC_PAD_TUNE_CMDRRDLY, 959 host->hs400_cmd_int_delay); 960 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock, 961 timing); 962 } 963 964 static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 965 struct mmc_command *cmd) 966 { 967 u32 resp; 968 969 switch (mmc_resp_type(cmd)) { 970 /* Actually, R1, R5, R6, R7 are the same */ 971 case MMC_RSP_R1: 972 resp = 0x1; 973 break; 974 case MMC_RSP_R1B: 975 resp = 0x7; 976 break; 977 case MMC_RSP_R2: 978 resp = 0x2; 979 break; 980 case MMC_RSP_R3: 981 resp = 0x3; 982 break; 983 case MMC_RSP_NONE: 984 default: 985 resp = 0x0; 986 break; 987 } 988 989 return resp; 990 } 991 992 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 993 struct mmc_request *mrq, struct mmc_command *cmd) 994 { 995 struct mmc_host *mmc = mmc_from_priv(host); 996 /* rawcmd : 997 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 998 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 999 */ 1000 u32 opcode = cmd->opcode; 1001 u32 resp = msdc_cmd_find_resp(host, cmd); 1002 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 1003 1004 host->cmd_rsp = resp; 1005 1006 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 1007 opcode == MMC_STOP_TRANSMISSION) 1008 rawcmd |= BIT(14); 1009 else if (opcode == SD_SWITCH_VOLTAGE) 1010 rawcmd |= BIT(30); 1011 else if (opcode == SD_APP_SEND_SCR || 1012 opcode == SD_APP_SEND_NUM_WR_BLKS || 1013 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 1014 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 1015 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 1016 rawcmd |= BIT(11); 1017 1018 if (cmd->data) { 1019 struct mmc_data *data = cmd->data; 1020 1021 if (mmc_op_multi(opcode)) { 1022 if (mmc_card_mmc(mmc->card) && mrq->sbc && 1023 !(mrq->sbc->arg & 0xFFFF0000)) 1024 rawcmd |= BIT(29); /* AutoCMD23 */ 1025 } 1026 1027 rawcmd |= ((data->blksz & 0xFFF) << 16); 1028 if (data->flags & MMC_DATA_WRITE) 1029 rawcmd |= BIT(13); 1030 if (data->blocks > 1) 1031 rawcmd |= BIT(12); 1032 else 1033 rawcmd |= BIT(11); 1034 /* Always use dma mode */ 1035 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 1036 1037 if (host->timeout_ns != data->timeout_ns || 1038 host->timeout_clks != data->timeout_clks) 1039 msdc_set_timeout(host, data->timeout_ns, 1040 data->timeout_clks); 1041 1042 writel(data->blocks, host->base + SDC_BLK_NUM); 1043 } 1044 return rawcmd; 1045 } 1046 1047 static void msdc_start_data(struct msdc_host *host, struct mmc_command *cmd, 1048 struct mmc_data *data) 1049 { 1050 bool read; 1051 1052 WARN_ON(host->data); 1053 host->data = data; 1054 read = data->flags & MMC_DATA_READ; 1055 1056 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1057 msdc_dma_setup(host, &host->dma, data); 1058 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 1059 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 1060 dev_dbg(host->dev, "DMA start\n"); 1061 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 1062 __func__, cmd->opcode, data->blocks, read); 1063 } 1064 1065 static int msdc_auto_cmd_done(struct msdc_host *host, int events, 1066 struct mmc_command *cmd) 1067 { 1068 u32 *rsp = cmd->resp; 1069 1070 rsp[0] = readl(host->base + SDC_ACMD_RESP); 1071 1072 if (events & MSDC_INT_ACMDRDY) { 1073 cmd->error = 0; 1074 } else { 1075 msdc_reset_hw(host); 1076 if (events & MSDC_INT_ACMDCRCERR) { 1077 cmd->error = -EILSEQ; 1078 host->error |= REQ_STOP_EIO; 1079 } else if (events & MSDC_INT_ACMDTMO) { 1080 cmd->error = -ETIMEDOUT; 1081 host->error |= REQ_STOP_TMO; 1082 } 1083 dev_err(host->dev, 1084 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 1085 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 1086 } 1087 return cmd->error; 1088 } 1089 1090 /* 1091 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost 1092 * 1093 * Host controller may lost interrupt in some special case. 1094 * Add SDIO irq recheck mechanism to make sure all interrupts 1095 * can be processed immediately 1096 */ 1097 static void msdc_recheck_sdio_irq(struct msdc_host *host) 1098 { 1099 struct mmc_host *mmc = mmc_from_priv(host); 1100 u32 reg_int, reg_inten, reg_ps; 1101 1102 if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1103 reg_inten = readl(host->base + MSDC_INTEN); 1104 if (reg_inten & MSDC_INTEN_SDIOIRQ) { 1105 reg_int = readl(host->base + MSDC_INT); 1106 reg_ps = readl(host->base + MSDC_PS); 1107 if (!(reg_int & MSDC_INT_SDIOIRQ || 1108 reg_ps & MSDC_PS_DATA1)) { 1109 __msdc_enable_sdio_irq(host, 0); 1110 sdio_signal_irq(mmc); 1111 } 1112 } 1113 } 1114 } 1115 1116 static void msdc_track_cmd_data(struct msdc_host *host, struct mmc_command *cmd) 1117 { 1118 if (host->error) 1119 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 1120 __func__, cmd->opcode, cmd->arg, host->error); 1121 } 1122 1123 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 1124 { 1125 unsigned long flags; 1126 1127 /* 1128 * No need check the return value of cancel_delayed_work, as only ONE 1129 * path will go here! 1130 */ 1131 cancel_delayed_work(&host->req_timeout); 1132 1133 spin_lock_irqsave(&host->lock, flags); 1134 host->mrq = NULL; 1135 spin_unlock_irqrestore(&host->lock, flags); 1136 1137 msdc_track_cmd_data(host, mrq->cmd); 1138 if (mrq->data) 1139 msdc_unprepare_data(host, mrq->data); 1140 if (host->error) 1141 msdc_reset_hw(host); 1142 mmc_request_done(mmc_from_priv(host), mrq); 1143 if (host->dev_comp->recheck_sdio_irq) 1144 msdc_recheck_sdio_irq(host); 1145 } 1146 1147 /* returns true if command is fully handled; returns false otherwise */ 1148 static bool msdc_cmd_done(struct msdc_host *host, int events, 1149 struct mmc_request *mrq, struct mmc_command *cmd) 1150 { 1151 bool done = false; 1152 bool sbc_error; 1153 unsigned long flags; 1154 u32 *rsp; 1155 1156 if (mrq->sbc && cmd == mrq->cmd && 1157 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 1158 | MSDC_INT_ACMDTMO))) 1159 msdc_auto_cmd_done(host, events, mrq->sbc); 1160 1161 sbc_error = mrq->sbc && mrq->sbc->error; 1162 1163 if (!sbc_error && !(events & (MSDC_INT_CMDRDY 1164 | MSDC_INT_RSPCRCERR 1165 | MSDC_INT_CMDTMO))) 1166 return done; 1167 1168 spin_lock_irqsave(&host->lock, flags); 1169 done = !host->cmd; 1170 host->cmd = NULL; 1171 spin_unlock_irqrestore(&host->lock, flags); 1172 1173 if (done) 1174 return true; 1175 rsp = cmd->resp; 1176 1177 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1178 1179 if (cmd->flags & MMC_RSP_PRESENT) { 1180 if (cmd->flags & MMC_RSP_136) { 1181 rsp[0] = readl(host->base + SDC_RESP3); 1182 rsp[1] = readl(host->base + SDC_RESP2); 1183 rsp[2] = readl(host->base + SDC_RESP1); 1184 rsp[3] = readl(host->base + SDC_RESP0); 1185 } else { 1186 rsp[0] = readl(host->base + SDC_RESP0); 1187 } 1188 } 1189 1190 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 1191 if (events & MSDC_INT_CMDTMO || 1192 (cmd->opcode != MMC_SEND_TUNING_BLOCK && 1193 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200 && 1194 !host->hs400_tuning)) 1195 /* 1196 * should not clear fifo/interrupt as the tune data 1197 * may have alreay come when cmd19/cmd21 gets response 1198 * CRC error. 1199 */ 1200 msdc_reset_hw(host); 1201 if (events & MSDC_INT_RSPCRCERR) { 1202 cmd->error = -EILSEQ; 1203 host->error |= REQ_CMD_EIO; 1204 } else if (events & MSDC_INT_CMDTMO) { 1205 cmd->error = -ETIMEDOUT; 1206 host->error |= REQ_CMD_TMO; 1207 } 1208 } 1209 if (cmd->error) 1210 dev_dbg(host->dev, 1211 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 1212 __func__, cmd->opcode, cmd->arg, rsp[0], 1213 cmd->error); 1214 1215 msdc_cmd_next(host, mrq, cmd); 1216 return true; 1217 } 1218 1219 /* It is the core layer's responsibility to ensure card status 1220 * is correct before issue a request. but host design do below 1221 * checks recommended. 1222 */ 1223 static inline bool msdc_cmd_is_ready(struct msdc_host *host, 1224 struct mmc_request *mrq, struct mmc_command *cmd) 1225 { 1226 u32 val; 1227 int ret; 1228 1229 /* The max busy time we can endure is 20ms */ 1230 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, 1231 !(val & SDC_STS_CMDBUSY), 1, 20000); 1232 if (ret) { 1233 dev_err(host->dev, "CMD bus busy detected\n"); 1234 host->error |= REQ_CMD_BUSY; 1235 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1236 return false; 1237 } 1238 1239 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 1240 /* R1B or with data, should check SDCBUSY */ 1241 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, 1242 !(val & SDC_STS_SDCBUSY), 1, 20000); 1243 if (ret) { 1244 dev_err(host->dev, "Controller busy detected\n"); 1245 host->error |= REQ_CMD_BUSY; 1246 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1247 return false; 1248 } 1249 } 1250 return true; 1251 } 1252 1253 static void msdc_start_command(struct msdc_host *host, 1254 struct mmc_request *mrq, struct mmc_command *cmd) 1255 { 1256 u32 rawcmd; 1257 unsigned long flags; 1258 1259 WARN_ON(host->cmd); 1260 host->cmd = cmd; 1261 1262 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1263 if (!msdc_cmd_is_ready(host, mrq, cmd)) 1264 return; 1265 1266 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 1267 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 1268 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 1269 msdc_reset_hw(host); 1270 } 1271 1272 cmd->error = 0; 1273 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 1274 1275 spin_lock_irqsave(&host->lock, flags); 1276 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1277 spin_unlock_irqrestore(&host->lock, flags); 1278 1279 writel(cmd->arg, host->base + SDC_ARG); 1280 writel(rawcmd, host->base + SDC_CMD); 1281 } 1282 1283 static void msdc_cmd_next(struct msdc_host *host, 1284 struct mmc_request *mrq, struct mmc_command *cmd) 1285 { 1286 if ((cmd->error && 1287 !(cmd->error == -EILSEQ && 1288 (cmd->opcode == MMC_SEND_TUNING_BLOCK || 1289 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200 || 1290 host->hs400_tuning))) || 1291 (mrq->sbc && mrq->sbc->error)) 1292 msdc_request_done(host, mrq); 1293 else if (cmd == mrq->sbc) 1294 msdc_start_command(host, mrq, mrq->cmd); 1295 else if (!cmd->data) 1296 msdc_request_done(host, mrq); 1297 else 1298 msdc_start_data(host, cmd, cmd->data); 1299 } 1300 1301 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 1302 { 1303 struct msdc_host *host = mmc_priv(mmc); 1304 1305 host->error = 0; 1306 WARN_ON(host->mrq); 1307 host->mrq = mrq; 1308 1309 if (mrq->data) 1310 msdc_prepare_data(host, mrq->data); 1311 1312 /* if SBC is required, we have HW option and SW option. 1313 * if HW option is enabled, and SBC does not have "special" flags, 1314 * use HW option, otherwise use SW option 1315 */ 1316 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 1317 (mrq->sbc->arg & 0xFFFF0000))) 1318 msdc_start_command(host, mrq, mrq->sbc); 1319 else 1320 msdc_start_command(host, mrq, mrq->cmd); 1321 } 1322 1323 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 1324 { 1325 struct msdc_host *host = mmc_priv(mmc); 1326 struct mmc_data *data = mrq->data; 1327 1328 if (!data) 1329 return; 1330 1331 msdc_prepare_data(host, data); 1332 data->host_cookie |= MSDC_ASYNC_FLAG; 1333 } 1334 1335 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1336 int err) 1337 { 1338 struct msdc_host *host = mmc_priv(mmc); 1339 struct mmc_data *data = mrq->data; 1340 1341 if (!data) 1342 return; 1343 1344 if (data->host_cookie) { 1345 data->host_cookie &= ~MSDC_ASYNC_FLAG; 1346 msdc_unprepare_data(host, data); 1347 } 1348 } 1349 1350 static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq) 1351 { 1352 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 1353 !mrq->sbc) 1354 msdc_start_command(host, mrq, mrq->stop); 1355 else 1356 msdc_request_done(host, mrq); 1357 } 1358 1359 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 1360 struct mmc_request *mrq, struct mmc_data *data) 1361 { 1362 struct mmc_command *stop; 1363 unsigned long flags; 1364 bool done; 1365 unsigned int check_data = events & 1366 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 1367 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 1368 | MSDC_INT_DMA_PROTECT); 1369 u32 val; 1370 int ret; 1371 1372 spin_lock_irqsave(&host->lock, flags); 1373 done = !host->data; 1374 if (check_data) 1375 host->data = NULL; 1376 spin_unlock_irqrestore(&host->lock, flags); 1377 1378 if (done) 1379 return true; 1380 stop = data->stop; 1381 1382 if (check_data || (stop && stop->error)) { 1383 dev_dbg(host->dev, "DMA status: 0x%8X\n", 1384 readl(host->base + MSDC_DMA_CFG)); 1385 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1386 1); 1387 1388 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val, 1389 !(val & MSDC_DMA_CFG_STS), 1, 20000); 1390 if (ret) { 1391 dev_dbg(host->dev, "DMA stop timed out\n"); 1392 return false; 1393 } 1394 1395 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 1396 dev_dbg(host->dev, "DMA stop\n"); 1397 1398 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 1399 data->bytes_xfered = data->blocks * data->blksz; 1400 } else { 1401 dev_dbg(host->dev, "interrupt events: %x\n", events); 1402 msdc_reset_hw(host); 1403 host->error |= REQ_DAT_ERR; 1404 data->bytes_xfered = 0; 1405 1406 if (events & MSDC_INT_DATTMO) 1407 data->error = -ETIMEDOUT; 1408 else if (events & MSDC_INT_DATCRCERR) 1409 data->error = -EILSEQ; 1410 1411 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 1412 __func__, mrq->cmd->opcode, data->blocks); 1413 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 1414 (int)data->error, data->bytes_xfered); 1415 } 1416 1417 msdc_data_xfer_next(host, mrq); 1418 done = true; 1419 } 1420 return done; 1421 } 1422 1423 static void msdc_set_buswidth(struct msdc_host *host, u32 width) 1424 { 1425 u32 val = readl(host->base + SDC_CFG); 1426 1427 val &= ~SDC_CFG_BUSWIDTH; 1428 1429 switch (width) { 1430 default: 1431 case MMC_BUS_WIDTH_1: 1432 val |= (MSDC_BUS_1BITS << 16); 1433 break; 1434 case MMC_BUS_WIDTH_4: 1435 val |= (MSDC_BUS_4BITS << 16); 1436 break; 1437 case MMC_BUS_WIDTH_8: 1438 val |= (MSDC_BUS_8BITS << 16); 1439 break; 1440 } 1441 1442 writel(val, host->base + SDC_CFG); 1443 dev_dbg(host->dev, "Bus Width = %d", width); 1444 } 1445 1446 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 1447 { 1448 struct msdc_host *host = mmc_priv(mmc); 1449 int ret; 1450 1451 if (!IS_ERR(mmc->supply.vqmmc)) { 1452 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1453 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 1454 dev_err(host->dev, "Unsupported signal voltage!\n"); 1455 return -EINVAL; 1456 } 1457 1458 ret = mmc_regulator_set_vqmmc(mmc, ios); 1459 if (ret < 0) { 1460 dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1461 ret, ios->signal_voltage); 1462 return ret; 1463 } 1464 1465 /* Apply different pinctrl settings for different signal voltage */ 1466 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 1467 pinctrl_select_state(host->pinctrl, host->pins_uhs); 1468 else 1469 pinctrl_select_state(host->pinctrl, host->pins_default); 1470 } 1471 return 0; 1472 } 1473 1474 static int msdc_card_busy(struct mmc_host *mmc) 1475 { 1476 struct msdc_host *host = mmc_priv(mmc); 1477 u32 status = readl(host->base + MSDC_PS); 1478 1479 /* only check if data0 is low */ 1480 return !(status & BIT(16)); 1481 } 1482 1483 static void msdc_request_timeout(struct work_struct *work) 1484 { 1485 struct msdc_host *host = container_of(work, struct msdc_host, 1486 req_timeout.work); 1487 1488 /* simulate HW timeout status */ 1489 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 1490 if (host->mrq) { 1491 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 1492 host->mrq, host->mrq->cmd->opcode); 1493 if (host->cmd) { 1494 dev_err(host->dev, "%s: aborting cmd=%d\n", 1495 __func__, host->cmd->opcode); 1496 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 1497 host->cmd); 1498 } else if (host->data) { 1499 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 1500 __func__, host->mrq->cmd->opcode, 1501 host->data->blocks); 1502 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 1503 host->data); 1504 } 1505 } 1506 } 1507 1508 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb) 1509 { 1510 if (enb) { 1511 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1512 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1513 if (host->dev_comp->recheck_sdio_irq) 1514 msdc_recheck_sdio_irq(host); 1515 } else { 1516 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1517 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1518 } 1519 } 1520 1521 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) 1522 { 1523 unsigned long flags; 1524 struct msdc_host *host = mmc_priv(mmc); 1525 1526 spin_lock_irqsave(&host->lock, flags); 1527 __msdc_enable_sdio_irq(host, enb); 1528 spin_unlock_irqrestore(&host->lock, flags); 1529 1530 if (enb) 1531 pm_runtime_get_noresume(host->dev); 1532 else 1533 pm_runtime_put_noidle(host->dev); 1534 } 1535 1536 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) 1537 { 1538 struct mmc_host *mmc = mmc_from_priv(host); 1539 int cmd_err = 0, dat_err = 0; 1540 1541 if (intsts & MSDC_INT_RSPCRCERR) { 1542 cmd_err = -EILSEQ; 1543 dev_err(host->dev, "%s: CMD CRC ERR", __func__); 1544 } else if (intsts & MSDC_INT_CMDTMO) { 1545 cmd_err = -ETIMEDOUT; 1546 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); 1547 } 1548 1549 if (intsts & MSDC_INT_DATCRCERR) { 1550 dat_err = -EILSEQ; 1551 dev_err(host->dev, "%s: DATA CRC ERR", __func__); 1552 } else if (intsts & MSDC_INT_DATTMO) { 1553 dat_err = -ETIMEDOUT; 1554 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); 1555 } 1556 1557 if (cmd_err || dat_err) { 1558 dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", 1559 cmd_err, dat_err, intsts); 1560 } 1561 1562 return cqhci_irq(mmc, 0, cmd_err, dat_err); 1563 } 1564 1565 static irqreturn_t msdc_irq(int irq, void *dev_id) 1566 { 1567 struct msdc_host *host = (struct msdc_host *) dev_id; 1568 struct mmc_host *mmc = mmc_from_priv(host); 1569 1570 while (true) { 1571 struct mmc_request *mrq; 1572 struct mmc_command *cmd; 1573 struct mmc_data *data; 1574 u32 events, event_mask; 1575 1576 spin_lock(&host->lock); 1577 events = readl(host->base + MSDC_INT); 1578 event_mask = readl(host->base + MSDC_INTEN); 1579 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1580 __msdc_enable_sdio_irq(host, 0); 1581 /* clear interrupts */ 1582 writel(events & event_mask, host->base + MSDC_INT); 1583 1584 mrq = host->mrq; 1585 cmd = host->cmd; 1586 data = host->data; 1587 spin_unlock(&host->lock); 1588 1589 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1590 sdio_signal_irq(mmc); 1591 1592 if ((events & event_mask) & MSDC_INT_CDSC) { 1593 if (host->internal_cd) 1594 mmc_detect_change(mmc, msecs_to_jiffies(20)); 1595 events &= ~MSDC_INT_CDSC; 1596 } 1597 1598 if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) 1599 break; 1600 1601 if ((mmc->caps2 & MMC_CAP2_CQE) && 1602 (events & MSDC_INT_CMDQ)) { 1603 msdc_cmdq_irq(host, events); 1604 /* clear interrupts */ 1605 writel(events, host->base + MSDC_INT); 1606 return IRQ_HANDLED; 1607 } 1608 1609 if (!mrq) { 1610 dev_err(host->dev, 1611 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 1612 __func__, events, event_mask); 1613 WARN_ON(1); 1614 break; 1615 } 1616 1617 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 1618 1619 if (cmd) 1620 msdc_cmd_done(host, events, mrq, cmd); 1621 else if (data) 1622 msdc_data_xfer_done(host, events, mrq, data); 1623 } 1624 1625 return IRQ_HANDLED; 1626 } 1627 1628 static void msdc_init_hw(struct msdc_host *host) 1629 { 1630 u32 val; 1631 u32 tune_reg = host->dev_comp->pad_tune_reg; 1632 struct mmc_host *mmc = mmc_from_priv(host); 1633 1634 if (host->reset) { 1635 reset_control_assert(host->reset); 1636 usleep_range(10, 50); 1637 reset_control_deassert(host->reset); 1638 } 1639 1640 /* Configure to MMC/SD mode, clock free running */ 1641 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 1642 1643 /* Reset */ 1644 msdc_reset_hw(host); 1645 1646 /* Disable and clear all interrupts */ 1647 writel(0, host->base + MSDC_INTEN); 1648 val = readl(host->base + MSDC_INT); 1649 writel(val, host->base + MSDC_INT); 1650 1651 /* Configure card detection */ 1652 if (host->internal_cd) { 1653 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, 1654 DEFAULT_DEBOUNCE); 1655 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1656 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1657 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1658 } else { 1659 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1660 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1661 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1662 } 1663 1664 if (host->top_base) { 1665 writel(0, host->top_base + EMMC_TOP_CONTROL); 1666 writel(0, host->top_base + EMMC_TOP_CMD); 1667 } else { 1668 writel(0, host->base + tune_reg); 1669 } 1670 writel(0, host->base + MSDC_IOCON); 1671 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 1672 writel(0x403c0046, host->base + MSDC_PATCH_BIT); 1673 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 1674 writel(0xffff4089, host->base + MSDC_PATCH_BIT1); 1675 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1676 1677 if (host->dev_comp->stop_clk_fix) { 1678 sdr_set_field(host->base + MSDC_PATCH_BIT1, 1679 MSDC_PATCH_BIT1_STOP_DLY, 3); 1680 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1681 SDC_FIFO_CFG_WRVALIDSEL); 1682 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1683 SDC_FIFO_CFG_RDVALIDSEL); 1684 } 1685 1686 if (host->dev_comp->busy_check) 1687 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7)); 1688 1689 if (host->dev_comp->async_fifo) { 1690 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1691 MSDC_PB2_RESPWAIT, 3); 1692 if (host->dev_comp->enhance_rx) { 1693 if (host->top_base) 1694 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1695 SDC_RX_ENH_EN); 1696 else 1697 sdr_set_bits(host->base + SDC_ADV_CFG0, 1698 SDC_RX_ENHANCE_EN); 1699 } else { 1700 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1701 MSDC_PB2_RESPSTSENSEL, 2); 1702 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1703 MSDC_PB2_CRCSTSENSEL, 2); 1704 } 1705 /* use async fifo, then no need tune internal delay */ 1706 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, 1707 MSDC_PATCH_BIT2_CFGRESP); 1708 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1709 MSDC_PATCH_BIT2_CFGCRCSTS); 1710 } 1711 1712 if (host->dev_comp->support_64g) 1713 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1714 MSDC_PB2_SUPPORT_64G); 1715 if (host->dev_comp->data_tune) { 1716 if (host->top_base) { 1717 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1718 PAD_DAT_RD_RXDLY_SEL); 1719 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, 1720 DATA_K_VALUE_SEL); 1721 sdr_set_bits(host->top_base + EMMC_TOP_CMD, 1722 PAD_CMD_RD_RXDLY_SEL); 1723 } else { 1724 sdr_set_bits(host->base + tune_reg, 1725 MSDC_PAD_TUNE_RD_SEL | 1726 MSDC_PAD_TUNE_CMD_SEL); 1727 } 1728 } else { 1729 /* choose clock tune */ 1730 if (host->top_base) 1731 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1732 PAD_RXDLY_SEL); 1733 else 1734 sdr_set_bits(host->base + tune_reg, 1735 MSDC_PAD_TUNE_RXDLYSEL); 1736 } 1737 1738 if (mmc->caps2 & MMC_CAP2_NO_SDIO) { 1739 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1740 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1741 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 1742 } else { 1743 /* Configure to enable SDIO mode, otherwise SDIO CMD5 fails */ 1744 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1745 1746 /* Config SDIO device detect interrupt function */ 1747 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1748 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 1749 } 1750 1751 /* Configure to default data timeout */ 1752 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 1753 1754 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 1755 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1756 if (host->top_base) { 1757 host->def_tune_para.emmc_top_control = 1758 readl(host->top_base + EMMC_TOP_CONTROL); 1759 host->def_tune_para.emmc_top_cmd = 1760 readl(host->top_base + EMMC_TOP_CMD); 1761 host->saved_tune_para.emmc_top_control = 1762 readl(host->top_base + EMMC_TOP_CONTROL); 1763 host->saved_tune_para.emmc_top_cmd = 1764 readl(host->top_base + EMMC_TOP_CMD); 1765 } else { 1766 host->def_tune_para.pad_tune = readl(host->base + tune_reg); 1767 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 1768 } 1769 dev_dbg(host->dev, "init hardware done!"); 1770 } 1771 1772 static void msdc_deinit_hw(struct msdc_host *host) 1773 { 1774 u32 val; 1775 1776 if (host->internal_cd) { 1777 /* Disabled card-detect */ 1778 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1779 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1780 } 1781 1782 /* Disable and clear all interrupts */ 1783 writel(0, host->base + MSDC_INTEN); 1784 1785 val = readl(host->base + MSDC_INT); 1786 writel(val, host->base + MSDC_INT); 1787 } 1788 1789 /* init gpd and bd list in msdc_drv_probe */ 1790 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 1791 { 1792 struct mt_gpdma_desc *gpd = dma->gpd; 1793 struct mt_bdma_desc *bd = dma->bd; 1794 dma_addr_t dma_addr; 1795 int i; 1796 1797 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 1798 1799 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); 1800 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 1801 /* gpd->next is must set for desc DMA 1802 * That's why must alloc 2 gpd structure. 1803 */ 1804 gpd->next = lower_32_bits(dma_addr); 1805 if (host->dev_comp->support_64g) 1806 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1807 1808 dma_addr = dma->bd_addr; 1809 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ 1810 if (host->dev_comp->support_64g) 1811 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; 1812 1813 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 1814 for (i = 0; i < (MAX_BD_NUM - 1); i++) { 1815 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); 1816 bd[i].next = lower_32_bits(dma_addr); 1817 if (host->dev_comp->support_64g) 1818 bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1819 } 1820 } 1821 1822 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1823 { 1824 struct msdc_host *host = mmc_priv(mmc); 1825 int ret; 1826 1827 msdc_set_buswidth(host, ios->bus_width); 1828 1829 /* Suspend/Resume will do power off/on */ 1830 switch (ios->power_mode) { 1831 case MMC_POWER_UP: 1832 if (!IS_ERR(mmc->supply.vmmc)) { 1833 msdc_init_hw(host); 1834 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1835 ios->vdd); 1836 if (ret) { 1837 dev_err(host->dev, "Failed to set vmmc power!\n"); 1838 return; 1839 } 1840 } 1841 break; 1842 case MMC_POWER_ON: 1843 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1844 ret = regulator_enable(mmc->supply.vqmmc); 1845 if (ret) 1846 dev_err(host->dev, "Failed to set vqmmc power!\n"); 1847 else 1848 host->vqmmc_enabled = true; 1849 } 1850 break; 1851 case MMC_POWER_OFF: 1852 if (!IS_ERR(mmc->supply.vmmc)) 1853 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1854 1855 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1856 regulator_disable(mmc->supply.vqmmc); 1857 host->vqmmc_enabled = false; 1858 } 1859 break; 1860 default: 1861 break; 1862 } 1863 1864 if (host->mclk != ios->clock || host->timing != ios->timing) 1865 msdc_set_mclk(host, ios->timing, ios->clock); 1866 } 1867 1868 static u32 test_delay_bit(u32 delay, u32 bit) 1869 { 1870 bit %= PAD_DELAY_MAX; 1871 return delay & BIT(bit); 1872 } 1873 1874 static int get_delay_len(u32 delay, u32 start_bit) 1875 { 1876 int i; 1877 1878 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 1879 if (test_delay_bit(delay, start_bit + i) == 0) 1880 return i; 1881 } 1882 return PAD_DELAY_MAX - start_bit; 1883 } 1884 1885 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 1886 { 1887 int start = 0, len = 0; 1888 int start_final = 0, len_final = 0; 1889 u8 final_phase = 0xff; 1890 struct msdc_delay_phase delay_phase = { 0, }; 1891 1892 if (delay == 0) { 1893 dev_err(host->dev, "phase error: [map:%x]\n", delay); 1894 delay_phase.final_phase = final_phase; 1895 return delay_phase; 1896 } 1897 1898 while (start < PAD_DELAY_MAX) { 1899 len = get_delay_len(delay, start); 1900 if (len_final < len) { 1901 start_final = start; 1902 len_final = len; 1903 } 1904 start += len ? len : 1; 1905 if (len >= 12 && start_final < 4) 1906 break; 1907 } 1908 1909 /* The rule is that to find the smallest delay cell */ 1910 if (start_final == 0) 1911 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 1912 else 1913 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 1914 dev_dbg(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 1915 delay, len_final, final_phase); 1916 1917 delay_phase.maxlen = len_final; 1918 delay_phase.start = start_final; 1919 delay_phase.final_phase = final_phase; 1920 return delay_phase; 1921 } 1922 1923 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) 1924 { 1925 u32 tune_reg = host->dev_comp->pad_tune_reg; 1926 1927 if (host->top_base) 1928 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, 1929 value); 1930 else 1931 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1932 value); 1933 } 1934 1935 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) 1936 { 1937 u32 tune_reg = host->dev_comp->pad_tune_reg; 1938 1939 if (host->top_base) 1940 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, 1941 PAD_DAT_RD_RXDLY, value); 1942 else 1943 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, 1944 value); 1945 } 1946 1947 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 1948 { 1949 struct msdc_host *host = mmc_priv(mmc); 1950 u32 rise_delay = 0, fall_delay = 0; 1951 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1952 struct msdc_delay_phase internal_delay_phase; 1953 u8 final_delay, final_maxlen; 1954 u32 internal_delay = 0; 1955 u32 tune_reg = host->dev_comp->pad_tune_reg; 1956 int cmd_err; 1957 int i, j; 1958 1959 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 1960 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 1961 sdr_set_field(host->base + tune_reg, 1962 MSDC_PAD_TUNE_CMDRRDLY, 1963 host->hs200_cmd_int_delay); 1964 1965 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1966 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1967 msdc_set_cmd_delay(host, i); 1968 /* 1969 * Using the same parameters, it may sometimes pass the test, 1970 * but sometimes it may fail. To make sure the parameters are 1971 * more stable, we test each set of parameters 3 times. 1972 */ 1973 for (j = 0; j < 3; j++) { 1974 mmc_send_tuning(mmc, opcode, &cmd_err); 1975 if (!cmd_err) { 1976 rise_delay |= BIT(i); 1977 } else { 1978 rise_delay &= ~BIT(i); 1979 break; 1980 } 1981 } 1982 } 1983 final_rise_delay = get_best_delay(host, rise_delay); 1984 /* if rising edge has enough margin, then do not scan falling edge */ 1985 if (final_rise_delay.maxlen >= 12 || 1986 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1987 goto skip_fall; 1988 1989 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1990 for (i = 0; i < PAD_DELAY_MAX; i++) { 1991 msdc_set_cmd_delay(host, i); 1992 /* 1993 * Using the same parameters, it may sometimes pass the test, 1994 * but sometimes it may fail. To make sure the parameters are 1995 * more stable, we test each set of parameters 3 times. 1996 */ 1997 for (j = 0; j < 3; j++) { 1998 mmc_send_tuning(mmc, opcode, &cmd_err); 1999 if (!cmd_err) { 2000 fall_delay |= BIT(i); 2001 } else { 2002 fall_delay &= ~BIT(i); 2003 break; 2004 } 2005 } 2006 } 2007 final_fall_delay = get_best_delay(host, fall_delay); 2008 2009 skip_fall: 2010 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2011 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 2012 final_maxlen = final_fall_delay.maxlen; 2013 if (final_maxlen == final_rise_delay.maxlen) { 2014 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2015 final_delay = final_rise_delay.final_phase; 2016 } else { 2017 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2018 final_delay = final_fall_delay.final_phase; 2019 } 2020 msdc_set_cmd_delay(host, final_delay); 2021 2022 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) 2023 goto skip_internal; 2024 2025 for (i = 0; i < PAD_DELAY_MAX; i++) { 2026 sdr_set_field(host->base + tune_reg, 2027 MSDC_PAD_TUNE_CMDRRDLY, i); 2028 mmc_send_tuning(mmc, opcode, &cmd_err); 2029 if (!cmd_err) 2030 internal_delay |= BIT(i); 2031 } 2032 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 2033 internal_delay_phase = get_best_delay(host, internal_delay); 2034 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 2035 internal_delay_phase.final_phase); 2036 skip_internal: 2037 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 2038 return final_delay == 0xff ? -EIO : 0; 2039 } 2040 2041 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 2042 { 2043 struct msdc_host *host = mmc_priv(mmc); 2044 u32 cmd_delay = 0; 2045 struct msdc_delay_phase final_cmd_delay = { 0,}; 2046 u8 final_delay; 2047 int cmd_err; 2048 int i, j; 2049 2050 /* select EMMC50 PAD CMD tune */ 2051 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 2052 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); 2053 2054 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 2055 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 2056 sdr_set_field(host->base + MSDC_PAD_TUNE, 2057 MSDC_PAD_TUNE_CMDRRDLY, 2058 host->hs200_cmd_int_delay); 2059 2060 if (host->hs400_cmd_resp_sel_rising) 2061 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2062 else 2063 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2064 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2065 sdr_set_field(host->base + PAD_CMD_TUNE, 2066 PAD_CMD_TUNE_RX_DLY3, i); 2067 /* 2068 * Using the same parameters, it may sometimes pass the test, 2069 * but sometimes it may fail. To make sure the parameters are 2070 * more stable, we test each set of parameters 3 times. 2071 */ 2072 for (j = 0; j < 3; j++) { 2073 mmc_send_tuning(mmc, opcode, &cmd_err); 2074 if (!cmd_err) { 2075 cmd_delay |= BIT(i); 2076 } else { 2077 cmd_delay &= ~BIT(i); 2078 break; 2079 } 2080 } 2081 } 2082 final_cmd_delay = get_best_delay(host, cmd_delay); 2083 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 2084 final_cmd_delay.final_phase); 2085 final_delay = final_cmd_delay.final_phase; 2086 2087 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 2088 return final_delay == 0xff ? -EIO : 0; 2089 } 2090 2091 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 2092 { 2093 struct msdc_host *host = mmc_priv(mmc); 2094 u32 rise_delay = 0, fall_delay = 0; 2095 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2096 u8 final_delay, final_maxlen; 2097 int i, ret; 2098 2099 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2100 host->latch_ck); 2101 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2102 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2103 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2104 msdc_set_data_delay(host, i); 2105 ret = mmc_send_tuning(mmc, opcode, NULL); 2106 if (!ret) 2107 rise_delay |= BIT(i); 2108 } 2109 final_rise_delay = get_best_delay(host, rise_delay); 2110 /* if rising edge has enough margin, then do not scan falling edge */ 2111 if (final_rise_delay.maxlen >= 12 || 2112 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2113 goto skip_fall; 2114 2115 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2116 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2117 for (i = 0; i < PAD_DELAY_MAX; i++) { 2118 msdc_set_data_delay(host, i); 2119 ret = mmc_send_tuning(mmc, opcode, NULL); 2120 if (!ret) 2121 fall_delay |= BIT(i); 2122 } 2123 final_fall_delay = get_best_delay(host, fall_delay); 2124 2125 skip_fall: 2126 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2127 if (final_maxlen == final_rise_delay.maxlen) { 2128 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2129 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2130 final_delay = final_rise_delay.final_phase; 2131 } else { 2132 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2133 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2134 final_delay = final_fall_delay.final_phase; 2135 } 2136 msdc_set_data_delay(host, final_delay); 2137 2138 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 2139 return final_delay == 0xff ? -EIO : 0; 2140 } 2141 2142 /* 2143 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune 2144 * together, which can save the tuning time. 2145 */ 2146 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode) 2147 { 2148 struct msdc_host *host = mmc_priv(mmc); 2149 u32 rise_delay = 0, fall_delay = 0; 2150 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2151 u8 final_delay, final_maxlen; 2152 int i, ret; 2153 2154 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2155 host->latch_ck); 2156 2157 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2158 sdr_clr_bits(host->base + MSDC_IOCON, 2159 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2160 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2161 msdc_set_cmd_delay(host, i); 2162 msdc_set_data_delay(host, i); 2163 ret = mmc_send_tuning(mmc, opcode, NULL); 2164 if (!ret) 2165 rise_delay |= BIT(i); 2166 } 2167 final_rise_delay = get_best_delay(host, rise_delay); 2168 /* if rising edge has enough margin, then do not scan falling edge */ 2169 if (final_rise_delay.maxlen >= 12 || 2170 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2171 goto skip_fall; 2172 2173 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2174 sdr_set_bits(host->base + MSDC_IOCON, 2175 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2176 for (i = 0; i < PAD_DELAY_MAX; i++) { 2177 msdc_set_cmd_delay(host, i); 2178 msdc_set_data_delay(host, i); 2179 ret = mmc_send_tuning(mmc, opcode, NULL); 2180 if (!ret) 2181 fall_delay |= BIT(i); 2182 } 2183 final_fall_delay = get_best_delay(host, fall_delay); 2184 2185 skip_fall: 2186 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2187 if (final_maxlen == final_rise_delay.maxlen) { 2188 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2189 sdr_clr_bits(host->base + MSDC_IOCON, 2190 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2191 final_delay = final_rise_delay.final_phase; 2192 } else { 2193 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2194 sdr_set_bits(host->base + MSDC_IOCON, 2195 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2196 final_delay = final_fall_delay.final_phase; 2197 } 2198 2199 msdc_set_cmd_delay(host, final_delay); 2200 msdc_set_data_delay(host, final_delay); 2201 2202 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); 2203 return final_delay == 0xff ? -EIO : 0; 2204 } 2205 2206 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 2207 { 2208 struct msdc_host *host = mmc_priv(mmc); 2209 int ret; 2210 u32 tune_reg = host->dev_comp->pad_tune_reg; 2211 2212 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { 2213 ret = msdc_tune_together(mmc, opcode); 2214 if (host->hs400_mode) { 2215 sdr_clr_bits(host->base + MSDC_IOCON, 2216 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2217 msdc_set_data_delay(host, 0); 2218 } 2219 goto tune_done; 2220 } 2221 if (host->hs400_mode && 2222 host->dev_comp->hs400_tune) 2223 ret = hs400_tune_response(mmc, opcode); 2224 else 2225 ret = msdc_tune_response(mmc, opcode); 2226 if (ret == -EIO) { 2227 dev_err(host->dev, "Tune response fail!\n"); 2228 return ret; 2229 } 2230 if (host->hs400_mode == false) { 2231 ret = msdc_tune_data(mmc, opcode); 2232 if (ret == -EIO) 2233 dev_err(host->dev, "Tune data fail!\n"); 2234 } 2235 2236 tune_done: 2237 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 2238 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 2239 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2240 if (host->top_base) { 2241 host->saved_tune_para.emmc_top_control = readl(host->top_base + 2242 EMMC_TOP_CONTROL); 2243 host->saved_tune_para.emmc_top_cmd = readl(host->top_base + 2244 EMMC_TOP_CMD); 2245 } 2246 return ret; 2247 } 2248 2249 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 2250 { 2251 struct msdc_host *host = mmc_priv(mmc); 2252 host->hs400_mode = true; 2253 2254 if (host->top_base) 2255 writel(host->hs400_ds_delay, 2256 host->top_base + EMMC50_PAD_DS_TUNE); 2257 else 2258 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 2259 /* hs400 mode must set it to 0 */ 2260 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); 2261 /* to improve read performance, set outstanding to 2 */ 2262 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); 2263 2264 return 0; 2265 } 2266 2267 static int msdc_execute_hs400_tuning(struct mmc_host *mmc, struct mmc_card *card) 2268 { 2269 struct msdc_host *host = mmc_priv(mmc); 2270 struct msdc_delay_phase dly1_delay; 2271 u32 val, result_dly1 = 0; 2272 u8 *ext_csd; 2273 int i, ret; 2274 2275 if (host->top_base) { 2276 sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE, 2277 PAD_DS_DLY_SEL); 2278 if (host->hs400_ds_dly3) 2279 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, 2280 PAD_DS_DLY3, host->hs400_ds_dly3); 2281 } else { 2282 sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL); 2283 if (host->hs400_ds_dly3) 2284 sdr_set_field(host->base + PAD_DS_TUNE, 2285 PAD_DS_TUNE_DLY3, host->hs400_ds_dly3); 2286 } 2287 2288 host->hs400_tuning = true; 2289 for (i = 0; i < PAD_DELAY_MAX; i++) { 2290 if (host->top_base) 2291 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, 2292 PAD_DS_DLY1, i); 2293 else 2294 sdr_set_field(host->base + PAD_DS_TUNE, 2295 PAD_DS_TUNE_DLY1, i); 2296 ret = mmc_get_ext_csd(card, &ext_csd); 2297 if (!ret) { 2298 result_dly1 |= BIT(i); 2299 kfree(ext_csd); 2300 } 2301 } 2302 host->hs400_tuning = false; 2303 2304 dly1_delay = get_best_delay(host, result_dly1); 2305 if (dly1_delay.maxlen == 0) { 2306 dev_err(host->dev, "Failed to get DLY1 delay!\n"); 2307 goto fail; 2308 } 2309 if (host->top_base) 2310 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, 2311 PAD_DS_DLY1, dly1_delay.final_phase); 2312 else 2313 sdr_set_field(host->base + PAD_DS_TUNE, 2314 PAD_DS_TUNE_DLY1, dly1_delay.final_phase); 2315 2316 if (host->top_base) 2317 val = readl(host->top_base + EMMC50_PAD_DS_TUNE); 2318 else 2319 val = readl(host->base + PAD_DS_TUNE); 2320 2321 dev_info(host->dev, "Fianl PAD_DS_TUNE: 0x%x\n", val); 2322 2323 return 0; 2324 2325 fail: 2326 dev_err(host->dev, "Failed to tuning DS pin delay!\n"); 2327 return -EIO; 2328 } 2329 2330 static void msdc_hw_reset(struct mmc_host *mmc) 2331 { 2332 struct msdc_host *host = mmc_priv(mmc); 2333 2334 sdr_set_bits(host->base + EMMC_IOCON, 1); 2335 udelay(10); /* 10us is enough */ 2336 sdr_clr_bits(host->base + EMMC_IOCON, 1); 2337 } 2338 2339 static void msdc_ack_sdio_irq(struct mmc_host *mmc) 2340 { 2341 unsigned long flags; 2342 struct msdc_host *host = mmc_priv(mmc); 2343 2344 spin_lock_irqsave(&host->lock, flags); 2345 __msdc_enable_sdio_irq(host, 1); 2346 spin_unlock_irqrestore(&host->lock, flags); 2347 } 2348 2349 static int msdc_get_cd(struct mmc_host *mmc) 2350 { 2351 struct msdc_host *host = mmc_priv(mmc); 2352 int val; 2353 2354 if (mmc->caps & MMC_CAP_NONREMOVABLE) 2355 return 1; 2356 2357 if (!host->internal_cd) 2358 return mmc_gpio_get_cd(mmc); 2359 2360 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; 2361 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) 2362 return !!val; 2363 else 2364 return !val; 2365 } 2366 2367 static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc, 2368 struct mmc_ios *ios) 2369 { 2370 struct msdc_host *host = mmc_priv(mmc); 2371 2372 if (ios->enhanced_strobe) { 2373 msdc_prepare_hs400_tuning(mmc, ios); 2374 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1); 2375 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1); 2376 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1); 2377 2378 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); 2379 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); 2380 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT); 2381 } else { 2382 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0); 2383 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0); 2384 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0); 2385 2386 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); 2387 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); 2388 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4); 2389 } 2390 } 2391 2392 static void msdc_cqe_enable(struct mmc_host *mmc) 2393 { 2394 struct msdc_host *host = mmc_priv(mmc); 2395 2396 /* enable cmdq irq */ 2397 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); 2398 /* enable busy check */ 2399 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 2400 /* default write data / busy timeout 20s */ 2401 msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); 2402 /* default read data timeout 1s */ 2403 msdc_set_timeout(host, 1000000000ULL, 0); 2404 } 2405 2406 static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) 2407 { 2408 struct msdc_host *host = mmc_priv(mmc); 2409 unsigned int val = 0; 2410 2411 /* disable cmdq irq */ 2412 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); 2413 /* disable busy check */ 2414 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 2415 2416 if (recovery) { 2417 sdr_set_field(host->base + MSDC_DMA_CTRL, 2418 MSDC_DMA_CTRL_STOP, 1); 2419 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val, 2420 !(val & MSDC_DMA_CFG_STS), 1, 3000))) 2421 return; 2422 msdc_reset_hw(host); 2423 } 2424 } 2425 2426 static void msdc_cqe_pre_enable(struct mmc_host *mmc) 2427 { 2428 struct cqhci_host *cq_host = mmc->cqe_private; 2429 u32 reg; 2430 2431 reg = cqhci_readl(cq_host, CQHCI_CFG); 2432 reg |= CQHCI_ENABLE; 2433 cqhci_writel(cq_host, reg, CQHCI_CFG); 2434 } 2435 2436 static void msdc_cqe_post_disable(struct mmc_host *mmc) 2437 { 2438 struct cqhci_host *cq_host = mmc->cqe_private; 2439 u32 reg; 2440 2441 reg = cqhci_readl(cq_host, CQHCI_CFG); 2442 reg &= ~CQHCI_ENABLE; 2443 cqhci_writel(cq_host, reg, CQHCI_CFG); 2444 } 2445 2446 static const struct mmc_host_ops mt_msdc_ops = { 2447 .post_req = msdc_post_req, 2448 .pre_req = msdc_pre_req, 2449 .request = msdc_ops_request, 2450 .set_ios = msdc_ops_set_ios, 2451 .get_ro = mmc_gpio_get_ro, 2452 .get_cd = msdc_get_cd, 2453 .hs400_enhanced_strobe = msdc_hs400_enhanced_strobe, 2454 .enable_sdio_irq = msdc_enable_sdio_irq, 2455 .ack_sdio_irq = msdc_ack_sdio_irq, 2456 .start_signal_voltage_switch = msdc_ops_switch_volt, 2457 .card_busy = msdc_card_busy, 2458 .execute_tuning = msdc_execute_tuning, 2459 .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 2460 .execute_hs400_tuning = msdc_execute_hs400_tuning, 2461 .card_hw_reset = msdc_hw_reset, 2462 }; 2463 2464 static const struct cqhci_host_ops msdc_cmdq_ops = { 2465 .enable = msdc_cqe_enable, 2466 .disable = msdc_cqe_disable, 2467 .pre_enable = msdc_cqe_pre_enable, 2468 .post_disable = msdc_cqe_post_disable, 2469 }; 2470 2471 static void msdc_of_property_parse(struct platform_device *pdev, 2472 struct msdc_host *host) 2473 { 2474 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", 2475 &host->latch_ck); 2476 2477 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 2478 &host->hs400_ds_delay); 2479 2480 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3", 2481 &host->hs400_ds_dly3); 2482 2483 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 2484 &host->hs200_cmd_int_delay); 2485 2486 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 2487 &host->hs400_cmd_int_delay); 2488 2489 if (of_property_read_bool(pdev->dev.of_node, 2490 "mediatek,hs400-cmd-resp-sel-rising")) 2491 host->hs400_cmd_resp_sel_rising = true; 2492 else 2493 host->hs400_cmd_resp_sel_rising = false; 2494 2495 if (of_property_read_bool(pdev->dev.of_node, 2496 "supports-cqe")) 2497 host->cqhci = true; 2498 else 2499 host->cqhci = false; 2500 } 2501 2502 static int msdc_of_clock_parse(struct platform_device *pdev, 2503 struct msdc_host *host) 2504 { 2505 int ret; 2506 2507 host->src_clk = devm_clk_get(&pdev->dev, "source"); 2508 if (IS_ERR(host->src_clk)) 2509 return PTR_ERR(host->src_clk); 2510 2511 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 2512 if (IS_ERR(host->h_clk)) 2513 return PTR_ERR(host->h_clk); 2514 2515 host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk"); 2516 if (IS_ERR(host->bus_clk)) 2517 host->bus_clk = NULL; 2518 2519 /*source clock control gate is optional clock*/ 2520 host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg"); 2521 if (IS_ERR(host->src_clk_cg)) 2522 return PTR_ERR(host->src_clk_cg); 2523 2524 /* 2525 * Fallback for legacy device-trees: src_clk and HCLK use the same 2526 * bit to control gating but they are parented to a different mux, 2527 * hence if our intention is to gate only the source, required 2528 * during a clk mode switch to avoid hw hangs, we need to gate 2529 * its parent (specified as a different clock only on new DTs). 2530 */ 2531 if (!host->src_clk_cg) { 2532 host->src_clk_cg = clk_get_parent(host->src_clk); 2533 if (IS_ERR(host->src_clk_cg)) 2534 return PTR_ERR(host->src_clk_cg); 2535 } 2536 2537 host->sys_clk_cg = devm_clk_get_optional(&pdev->dev, "sys_cg"); 2538 if (IS_ERR(host->sys_clk_cg)) 2539 host->sys_clk_cg = NULL; 2540 2541 /* If present, always enable for this clock gate */ 2542 clk_prepare_enable(host->sys_clk_cg); 2543 2544 host->bulk_clks[0].id = "pclk_cg"; 2545 host->bulk_clks[1].id = "axi_cg"; 2546 host->bulk_clks[2].id = "ahb_cg"; 2547 ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS, 2548 host->bulk_clks); 2549 if (ret) { 2550 dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n"); 2551 return ret; 2552 } 2553 2554 return 0; 2555 } 2556 2557 static int msdc_drv_probe(struct platform_device *pdev) 2558 { 2559 struct mmc_host *mmc; 2560 struct msdc_host *host; 2561 struct resource *res; 2562 int ret; 2563 2564 if (!pdev->dev.of_node) { 2565 dev_err(&pdev->dev, "No DT found\n"); 2566 return -EINVAL; 2567 } 2568 2569 /* Allocate MMC host for this device */ 2570 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 2571 if (!mmc) 2572 return -ENOMEM; 2573 2574 host = mmc_priv(mmc); 2575 ret = mmc_of_parse(mmc); 2576 if (ret) 2577 goto host_free; 2578 2579 host->base = devm_platform_ioremap_resource(pdev, 0); 2580 if (IS_ERR(host->base)) { 2581 ret = PTR_ERR(host->base); 2582 goto host_free; 2583 } 2584 2585 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2586 if (res) { 2587 host->top_base = devm_ioremap_resource(&pdev->dev, res); 2588 if (IS_ERR(host->top_base)) 2589 host->top_base = NULL; 2590 } 2591 2592 ret = mmc_regulator_get_supply(mmc); 2593 if (ret) 2594 goto host_free; 2595 2596 ret = msdc_of_clock_parse(pdev, host); 2597 if (ret) 2598 goto host_free; 2599 2600 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 2601 "hrst"); 2602 if (IS_ERR(host->reset)) { 2603 ret = PTR_ERR(host->reset); 2604 goto host_free; 2605 } 2606 2607 host->irq = platform_get_irq(pdev, 0); 2608 if (host->irq < 0) { 2609 ret = -EINVAL; 2610 goto host_free; 2611 } 2612 2613 host->pinctrl = devm_pinctrl_get(&pdev->dev); 2614 if (IS_ERR(host->pinctrl)) { 2615 ret = PTR_ERR(host->pinctrl); 2616 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 2617 goto host_free; 2618 } 2619 2620 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 2621 if (IS_ERR(host->pins_default)) { 2622 ret = PTR_ERR(host->pins_default); 2623 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 2624 goto host_free; 2625 } 2626 2627 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 2628 if (IS_ERR(host->pins_uhs)) { 2629 ret = PTR_ERR(host->pins_uhs); 2630 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 2631 goto host_free; 2632 } 2633 2634 msdc_of_property_parse(pdev, host); 2635 2636 host->dev = &pdev->dev; 2637 host->dev_comp = of_device_get_match_data(&pdev->dev); 2638 host->src_clk_freq = clk_get_rate(host->src_clk); 2639 /* Set host parameters to mmc */ 2640 mmc->ops = &mt_msdc_ops; 2641 if (host->dev_comp->clk_div_bits == 8) 2642 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 2643 else 2644 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); 2645 2646 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && 2647 !mmc_can_gpio_cd(mmc) && 2648 host->dev_comp->use_internal_cd) { 2649 /* 2650 * Is removable but no GPIO declared, so 2651 * use internal functionality. 2652 */ 2653 host->internal_cd = true; 2654 } 2655 2656 if (mmc->caps & MMC_CAP_SDIO_IRQ) 2657 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2658 2659 mmc->caps |= MMC_CAP_CMD23; 2660 if (host->cqhci) 2661 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 2662 /* MMC core transfer sizes tunable parameters */ 2663 mmc->max_segs = MAX_BD_NUM; 2664 if (host->dev_comp->support_64g) 2665 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; 2666 else 2667 mmc->max_seg_size = BDMA_DESC_BUFLEN; 2668 mmc->max_blk_size = 2048; 2669 mmc->max_req_size = 512 * 1024; 2670 mmc->max_blk_count = mmc->max_req_size / 512; 2671 if (host->dev_comp->support_64g) 2672 host->dma_mask = DMA_BIT_MASK(36); 2673 else 2674 host->dma_mask = DMA_BIT_MASK(32); 2675 mmc_dev(mmc)->dma_mask = &host->dma_mask; 2676 2677 host->timeout_clks = 3 * 1048576; 2678 host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2679 2 * sizeof(struct mt_gpdma_desc), 2680 &host->dma.gpd_addr, GFP_KERNEL); 2681 host->dma.bd = dma_alloc_coherent(&pdev->dev, 2682 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2683 &host->dma.bd_addr, GFP_KERNEL); 2684 if (!host->dma.gpd || !host->dma.bd) { 2685 ret = -ENOMEM; 2686 goto release_mem; 2687 } 2688 msdc_init_gpd_bd(host, &host->dma); 2689 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 2690 spin_lock_init(&host->lock); 2691 2692 platform_set_drvdata(pdev, mmc); 2693 ret = msdc_ungate_clock(host); 2694 if (ret) { 2695 dev_err(&pdev->dev, "Cannot ungate clocks!\n"); 2696 goto release_mem; 2697 } 2698 msdc_init_hw(host); 2699 2700 if (mmc->caps2 & MMC_CAP2_CQE) { 2701 host->cq_host = devm_kzalloc(mmc->parent, 2702 sizeof(*host->cq_host), 2703 GFP_KERNEL); 2704 if (!host->cq_host) { 2705 ret = -ENOMEM; 2706 goto host_free; 2707 } 2708 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 2709 host->cq_host->mmio = host->base + 0x800; 2710 host->cq_host->ops = &msdc_cmdq_ops; 2711 ret = cqhci_init(host->cq_host, mmc, true); 2712 if (ret) 2713 goto host_free; 2714 mmc->max_segs = 128; 2715 /* cqhci 16bit length */ 2716 /* 0 size, means 65536 so we don't have to -1 here */ 2717 mmc->max_seg_size = 64 * 1024; 2718 } 2719 2720 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 2721 IRQF_TRIGGER_NONE, pdev->name, host); 2722 if (ret) 2723 goto release; 2724 2725 pm_runtime_set_active(host->dev); 2726 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 2727 pm_runtime_use_autosuspend(host->dev); 2728 pm_runtime_enable(host->dev); 2729 ret = mmc_add_host(mmc); 2730 2731 if (ret) 2732 goto end; 2733 2734 return 0; 2735 end: 2736 pm_runtime_disable(host->dev); 2737 release: 2738 platform_set_drvdata(pdev, NULL); 2739 msdc_deinit_hw(host); 2740 msdc_gate_clock(host); 2741 release_mem: 2742 if (host->dma.gpd) 2743 dma_free_coherent(&pdev->dev, 2744 2 * sizeof(struct mt_gpdma_desc), 2745 host->dma.gpd, host->dma.gpd_addr); 2746 if (host->dma.bd) 2747 dma_free_coherent(&pdev->dev, 2748 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2749 host->dma.bd, host->dma.bd_addr); 2750 host_free: 2751 mmc_free_host(mmc); 2752 2753 return ret; 2754 } 2755 2756 static int msdc_drv_remove(struct platform_device *pdev) 2757 { 2758 struct mmc_host *mmc; 2759 struct msdc_host *host; 2760 2761 mmc = platform_get_drvdata(pdev); 2762 host = mmc_priv(mmc); 2763 2764 pm_runtime_get_sync(host->dev); 2765 2766 platform_set_drvdata(pdev, NULL); 2767 mmc_remove_host(mmc); 2768 msdc_deinit_hw(host); 2769 msdc_gate_clock(host); 2770 2771 pm_runtime_disable(host->dev); 2772 pm_runtime_put_noidle(host->dev); 2773 dma_free_coherent(&pdev->dev, 2774 2 * sizeof(struct mt_gpdma_desc), 2775 host->dma.gpd, host->dma.gpd_addr); 2776 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2777 host->dma.bd, host->dma.bd_addr); 2778 2779 mmc_free_host(mmc); 2780 2781 return 0; 2782 } 2783 2784 static void msdc_save_reg(struct msdc_host *host) 2785 { 2786 u32 tune_reg = host->dev_comp->pad_tune_reg; 2787 2788 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 2789 host->save_para.iocon = readl(host->base + MSDC_IOCON); 2790 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 2791 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 2792 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 2793 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); 2794 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 2795 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2796 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 2797 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); 2798 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); 2799 if (host->top_base) { 2800 host->save_para.emmc_top_control = 2801 readl(host->top_base + EMMC_TOP_CONTROL); 2802 host->save_para.emmc_top_cmd = 2803 readl(host->top_base + EMMC_TOP_CMD); 2804 host->save_para.emmc50_pad_ds_tune = 2805 readl(host->top_base + EMMC50_PAD_DS_TUNE); 2806 } else { 2807 host->save_para.pad_tune = readl(host->base + tune_reg); 2808 } 2809 } 2810 2811 static void msdc_restore_reg(struct msdc_host *host) 2812 { 2813 struct mmc_host *mmc = mmc_from_priv(host); 2814 u32 tune_reg = host->dev_comp->pad_tune_reg; 2815 2816 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 2817 writel(host->save_para.iocon, host->base + MSDC_IOCON); 2818 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 2819 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 2820 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 2821 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); 2822 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 2823 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 2824 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 2825 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); 2826 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); 2827 if (host->top_base) { 2828 writel(host->save_para.emmc_top_control, 2829 host->top_base + EMMC_TOP_CONTROL); 2830 writel(host->save_para.emmc_top_cmd, 2831 host->top_base + EMMC_TOP_CMD); 2832 writel(host->save_para.emmc50_pad_ds_tune, 2833 host->top_base + EMMC50_PAD_DS_TUNE); 2834 } else { 2835 writel(host->save_para.pad_tune, host->base + tune_reg); 2836 } 2837 2838 if (sdio_irq_claimed(mmc)) 2839 __msdc_enable_sdio_irq(host, 1); 2840 } 2841 2842 static int __maybe_unused msdc_runtime_suspend(struct device *dev) 2843 { 2844 struct mmc_host *mmc = dev_get_drvdata(dev); 2845 struct msdc_host *host = mmc_priv(mmc); 2846 2847 msdc_save_reg(host); 2848 msdc_gate_clock(host); 2849 return 0; 2850 } 2851 2852 static int __maybe_unused msdc_runtime_resume(struct device *dev) 2853 { 2854 struct mmc_host *mmc = dev_get_drvdata(dev); 2855 struct msdc_host *host = mmc_priv(mmc); 2856 int ret; 2857 2858 ret = msdc_ungate_clock(host); 2859 if (ret) 2860 return ret; 2861 2862 msdc_restore_reg(host); 2863 return 0; 2864 } 2865 2866 static int __maybe_unused msdc_suspend(struct device *dev) 2867 { 2868 struct mmc_host *mmc = dev_get_drvdata(dev); 2869 int ret; 2870 2871 if (mmc->caps2 & MMC_CAP2_CQE) { 2872 ret = cqhci_suspend(mmc); 2873 if (ret) 2874 return ret; 2875 } 2876 2877 return pm_runtime_force_suspend(dev); 2878 } 2879 2880 static int __maybe_unused msdc_resume(struct device *dev) 2881 { 2882 return pm_runtime_force_resume(dev); 2883 } 2884 2885 static const struct dev_pm_ops msdc_dev_pm_ops = { 2886 SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume) 2887 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 2888 }; 2889 2890 static struct platform_driver mt_msdc_driver = { 2891 .probe = msdc_drv_probe, 2892 .remove = msdc_drv_remove, 2893 .driver = { 2894 .name = "mtk-msdc", 2895 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 2896 .of_match_table = msdc_of_ids, 2897 .pm = &msdc_dev_pm_ops, 2898 }, 2899 }; 2900 2901 module_platform_driver(mt_msdc_driver); 2902 MODULE_LICENSE("GPL v2"); 2903 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 2904