1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2015, 2022 MediaTek Inc. 4 * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 5 */ 6 7 #include <linux/module.h> 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/iopoll.h> 13 #include <linux/ioport.h> 14 #include <linux/irq.h> 15 #include <linux/of_address.h> 16 #include <linux/of_device.h> 17 #include <linux/of_irq.h> 18 #include <linux/of_gpio.h> 19 #include <linux/pinctrl/consumer.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/pm_wakeirq.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/slab.h> 26 #include <linux/spinlock.h> 27 #include <linux/interrupt.h> 28 #include <linux/reset.h> 29 30 #include <linux/mmc/card.h> 31 #include <linux/mmc/core.h> 32 #include <linux/mmc/host.h> 33 #include <linux/mmc/mmc.h> 34 #include <linux/mmc/sd.h> 35 #include <linux/mmc/sdio.h> 36 #include <linux/mmc/slot-gpio.h> 37 38 #include "cqhci.h" 39 40 #define MAX_BD_NUM 1024 41 #define MSDC_NR_CLOCKS 3 42 43 /*--------------------------------------------------------------------------*/ 44 /* Common Definition */ 45 /*--------------------------------------------------------------------------*/ 46 #define MSDC_BUS_1BITS 0x0 47 #define MSDC_BUS_4BITS 0x1 48 #define MSDC_BUS_8BITS 0x2 49 50 #define MSDC_BURST_64B 0x6 51 52 /*--------------------------------------------------------------------------*/ 53 /* Register Offset */ 54 /*--------------------------------------------------------------------------*/ 55 #define MSDC_CFG 0x0 56 #define MSDC_IOCON 0x04 57 #define MSDC_PS 0x08 58 #define MSDC_INT 0x0c 59 #define MSDC_INTEN 0x10 60 #define MSDC_FIFOCS 0x14 61 #define SDC_CFG 0x30 62 #define SDC_CMD 0x34 63 #define SDC_ARG 0x38 64 #define SDC_STS 0x3c 65 #define SDC_RESP0 0x40 66 #define SDC_RESP1 0x44 67 #define SDC_RESP2 0x48 68 #define SDC_RESP3 0x4c 69 #define SDC_BLK_NUM 0x50 70 #define SDC_ADV_CFG0 0x64 71 #define EMMC_IOCON 0x7c 72 #define SDC_ACMD_RESP 0x80 73 #define DMA_SA_H4BIT 0x8c 74 #define MSDC_DMA_SA 0x90 75 #define MSDC_DMA_CTRL 0x98 76 #define MSDC_DMA_CFG 0x9c 77 #define MSDC_PATCH_BIT 0xb0 78 #define MSDC_PATCH_BIT1 0xb4 79 #define MSDC_PATCH_BIT2 0xb8 80 #define MSDC_PAD_TUNE 0xec 81 #define MSDC_PAD_TUNE0 0xf0 82 #define PAD_DS_TUNE 0x188 83 #define PAD_CMD_TUNE 0x18c 84 #define EMMC51_CFG0 0x204 85 #define EMMC50_CFG0 0x208 86 #define EMMC50_CFG1 0x20c 87 #define EMMC50_CFG3 0x220 88 #define SDC_FIFO_CFG 0x228 89 #define CQHCI_SETTING 0x7fc 90 91 /*--------------------------------------------------------------------------*/ 92 /* Top Pad Register Offset */ 93 /*--------------------------------------------------------------------------*/ 94 #define EMMC_TOP_CONTROL 0x00 95 #define EMMC_TOP_CMD 0x04 96 #define EMMC50_PAD_DS_TUNE 0x0c 97 98 /*--------------------------------------------------------------------------*/ 99 /* Register Mask */ 100 /*--------------------------------------------------------------------------*/ 101 102 /* MSDC_CFG mask */ 103 #define MSDC_CFG_MODE BIT(0) /* RW */ 104 #define MSDC_CFG_CKPDN BIT(1) /* RW */ 105 #define MSDC_CFG_RST BIT(2) /* RW */ 106 #define MSDC_CFG_PIO BIT(3) /* RW */ 107 #define MSDC_CFG_CKDRVEN BIT(4) /* RW */ 108 #define MSDC_CFG_BV18SDT BIT(5) /* RW */ 109 #define MSDC_CFG_BV18PSS BIT(6) /* R */ 110 #define MSDC_CFG_CKSTB BIT(7) /* R */ 111 #define MSDC_CFG_CKDIV GENMASK(15, 8) /* RW */ 112 #define MSDC_CFG_CKMOD GENMASK(17, 16) /* RW */ 113 #define MSDC_CFG_HS400_CK_MODE BIT(18) /* RW */ 114 #define MSDC_CFG_HS400_CK_MODE_EXTRA BIT(22) /* RW */ 115 #define MSDC_CFG_CKDIV_EXTRA GENMASK(19, 8) /* RW */ 116 #define MSDC_CFG_CKMOD_EXTRA GENMASK(21, 20) /* RW */ 117 118 /* MSDC_IOCON mask */ 119 #define MSDC_IOCON_SDR104CKS BIT(0) /* RW */ 120 #define MSDC_IOCON_RSPL BIT(1) /* RW */ 121 #define MSDC_IOCON_DSPL BIT(2) /* RW */ 122 #define MSDC_IOCON_DDLSEL BIT(3) /* RW */ 123 #define MSDC_IOCON_DDR50CKD BIT(4) /* RW */ 124 #define MSDC_IOCON_DSPLSEL BIT(5) /* RW */ 125 #define MSDC_IOCON_W_DSPL BIT(8) /* RW */ 126 #define MSDC_IOCON_D0SPL BIT(16) /* RW */ 127 #define MSDC_IOCON_D1SPL BIT(17) /* RW */ 128 #define MSDC_IOCON_D2SPL BIT(18) /* RW */ 129 #define MSDC_IOCON_D3SPL BIT(19) /* RW */ 130 #define MSDC_IOCON_D4SPL BIT(20) /* RW */ 131 #define MSDC_IOCON_D5SPL BIT(21) /* RW */ 132 #define MSDC_IOCON_D6SPL BIT(22) /* RW */ 133 #define MSDC_IOCON_D7SPL BIT(23) /* RW */ 134 #define MSDC_IOCON_RISCSZ GENMASK(25, 24) /* RW */ 135 136 /* MSDC_PS mask */ 137 #define MSDC_PS_CDEN BIT(0) /* RW */ 138 #define MSDC_PS_CDSTS BIT(1) /* R */ 139 #define MSDC_PS_CDDEBOUNCE GENMASK(15, 12) /* RW */ 140 #define MSDC_PS_DAT GENMASK(23, 16) /* R */ 141 #define MSDC_PS_DATA1 BIT(17) /* R */ 142 #define MSDC_PS_CMD BIT(24) /* R */ 143 #define MSDC_PS_WP BIT(31) /* R */ 144 145 /* MSDC_INT mask */ 146 #define MSDC_INT_MMCIRQ BIT(0) /* W1C */ 147 #define MSDC_INT_CDSC BIT(1) /* W1C */ 148 #define MSDC_INT_ACMDRDY BIT(3) /* W1C */ 149 #define MSDC_INT_ACMDTMO BIT(4) /* W1C */ 150 #define MSDC_INT_ACMDCRCERR BIT(5) /* W1C */ 151 #define MSDC_INT_DMAQ_EMPTY BIT(6) /* W1C */ 152 #define MSDC_INT_SDIOIRQ BIT(7) /* W1C */ 153 #define MSDC_INT_CMDRDY BIT(8) /* W1C */ 154 #define MSDC_INT_CMDTMO BIT(9) /* W1C */ 155 #define MSDC_INT_RSPCRCERR BIT(10) /* W1C */ 156 #define MSDC_INT_CSTA BIT(11) /* R */ 157 #define MSDC_INT_XFER_COMPL BIT(12) /* W1C */ 158 #define MSDC_INT_DXFER_DONE BIT(13) /* W1C */ 159 #define MSDC_INT_DATTMO BIT(14) /* W1C */ 160 #define MSDC_INT_DATCRCERR BIT(15) /* W1C */ 161 #define MSDC_INT_ACMD19_DONE BIT(16) /* W1C */ 162 #define MSDC_INT_DMA_BDCSERR BIT(17) /* W1C */ 163 #define MSDC_INT_DMA_GPDCSERR BIT(18) /* W1C */ 164 #define MSDC_INT_DMA_PROTECT BIT(19) /* W1C */ 165 #define MSDC_INT_CMDQ BIT(28) /* W1C */ 166 167 /* MSDC_INTEN mask */ 168 #define MSDC_INTEN_MMCIRQ BIT(0) /* RW */ 169 #define MSDC_INTEN_CDSC BIT(1) /* RW */ 170 #define MSDC_INTEN_ACMDRDY BIT(3) /* RW */ 171 #define MSDC_INTEN_ACMDTMO BIT(4) /* RW */ 172 #define MSDC_INTEN_ACMDCRCERR BIT(5) /* RW */ 173 #define MSDC_INTEN_DMAQ_EMPTY BIT(6) /* RW */ 174 #define MSDC_INTEN_SDIOIRQ BIT(7) /* RW */ 175 #define MSDC_INTEN_CMDRDY BIT(8) /* RW */ 176 #define MSDC_INTEN_CMDTMO BIT(9) /* RW */ 177 #define MSDC_INTEN_RSPCRCERR BIT(10) /* RW */ 178 #define MSDC_INTEN_CSTA BIT(11) /* RW */ 179 #define MSDC_INTEN_XFER_COMPL BIT(12) /* RW */ 180 #define MSDC_INTEN_DXFER_DONE BIT(13) /* RW */ 181 #define MSDC_INTEN_DATTMO BIT(14) /* RW */ 182 #define MSDC_INTEN_DATCRCERR BIT(15) /* RW */ 183 #define MSDC_INTEN_ACMD19_DONE BIT(16) /* RW */ 184 #define MSDC_INTEN_DMA_BDCSERR BIT(17) /* RW */ 185 #define MSDC_INTEN_DMA_GPDCSERR BIT(18) /* RW */ 186 #define MSDC_INTEN_DMA_PROTECT BIT(19) /* RW */ 187 188 /* MSDC_FIFOCS mask */ 189 #define MSDC_FIFOCS_RXCNT GENMASK(7, 0) /* R */ 190 #define MSDC_FIFOCS_TXCNT GENMASK(23, 16) /* R */ 191 #define MSDC_FIFOCS_CLR BIT(31) /* RW */ 192 193 /* SDC_CFG mask */ 194 #define SDC_CFG_SDIOINTWKUP BIT(0) /* RW */ 195 #define SDC_CFG_INSWKUP BIT(1) /* RW */ 196 #define SDC_CFG_WRDTOC GENMASK(14, 2) /* RW */ 197 #define SDC_CFG_BUSWIDTH GENMASK(17, 16) /* RW */ 198 #define SDC_CFG_SDIO BIT(19) /* RW */ 199 #define SDC_CFG_SDIOIDE BIT(20) /* RW */ 200 #define SDC_CFG_INTATGAP BIT(21) /* RW */ 201 #define SDC_CFG_DTOC GENMASK(31, 24) /* RW */ 202 203 /* SDC_STS mask */ 204 #define SDC_STS_SDCBUSY BIT(0) /* RW */ 205 #define SDC_STS_CMDBUSY BIT(1) /* RW */ 206 #define SDC_STS_SWR_COMPL BIT(31) /* RW */ 207 208 #define SDC_DAT1_IRQ_TRIGGER BIT(19) /* RW */ 209 /* SDC_ADV_CFG0 mask */ 210 #define SDC_RX_ENHANCE_EN BIT(20) /* RW */ 211 212 /* DMA_SA_H4BIT mask */ 213 #define DMA_ADDR_HIGH_4BIT GENMASK(3, 0) /* RW */ 214 215 /* MSDC_DMA_CTRL mask */ 216 #define MSDC_DMA_CTRL_START BIT(0) /* W */ 217 #define MSDC_DMA_CTRL_STOP BIT(1) /* W */ 218 #define MSDC_DMA_CTRL_RESUME BIT(2) /* W */ 219 #define MSDC_DMA_CTRL_MODE BIT(8) /* RW */ 220 #define MSDC_DMA_CTRL_LASTBUF BIT(10) /* RW */ 221 #define MSDC_DMA_CTRL_BRUSTSZ GENMASK(14, 12) /* RW */ 222 223 /* MSDC_DMA_CFG mask */ 224 #define MSDC_DMA_CFG_STS BIT(0) /* R */ 225 #define MSDC_DMA_CFG_DECSEN BIT(1) /* RW */ 226 #define MSDC_DMA_CFG_AHBHPROT2 BIT(9) /* RW */ 227 #define MSDC_DMA_CFG_ACTIVEEN BIT(13) /* RW */ 228 #define MSDC_DMA_CFG_CS12B16B BIT(16) /* RW */ 229 230 /* MSDC_PATCH_BIT mask */ 231 #define MSDC_PATCH_BIT_ODDSUPP BIT(1) /* RW */ 232 #define MSDC_INT_DAT_LATCH_CK_SEL GENMASK(9, 7) 233 #define MSDC_CKGEN_MSDC_DLY_SEL GENMASK(14, 10) 234 #define MSDC_PATCH_BIT_IODSSEL BIT(16) /* RW */ 235 #define MSDC_PATCH_BIT_IOINTSEL BIT(17) /* RW */ 236 #define MSDC_PATCH_BIT_BUSYDLY GENMASK(21, 18) /* RW */ 237 #define MSDC_PATCH_BIT_WDOD GENMASK(25, 22) /* RW */ 238 #define MSDC_PATCH_BIT_IDRTSEL BIT(26) /* RW */ 239 #define MSDC_PATCH_BIT_CMDFSEL BIT(27) /* RW */ 240 #define MSDC_PATCH_BIT_INTDLSEL BIT(28) /* RW */ 241 #define MSDC_PATCH_BIT_SPCPUSH BIT(29) /* RW */ 242 #define MSDC_PATCH_BIT_DECRCTMO BIT(30) /* RW */ 243 244 #define MSDC_PATCH_BIT1_CMDTA GENMASK(5, 3) /* RW */ 245 #define MSDC_PB1_BUSY_CHECK_SEL BIT(7) /* RW */ 246 #define MSDC_PATCH_BIT1_STOP_DLY GENMASK(11, 8) /* RW */ 247 248 #define MSDC_PATCH_BIT2_CFGRESP BIT(15) /* RW */ 249 #define MSDC_PATCH_BIT2_CFGCRCSTS BIT(28) /* RW */ 250 #define MSDC_PB2_SUPPORT_64G BIT(1) /* RW */ 251 #define MSDC_PB2_RESPWAIT GENMASK(3, 2) /* RW */ 252 #define MSDC_PB2_RESPSTSENSEL GENMASK(18, 16) /* RW */ 253 #define MSDC_PB2_CRCSTSENSEL GENMASK(31, 29) /* RW */ 254 255 #define MSDC_PAD_TUNE_DATWRDLY GENMASK(4, 0) /* RW */ 256 #define MSDC_PAD_TUNE_DATRRDLY GENMASK(12, 8) /* RW */ 257 #define MSDC_PAD_TUNE_CMDRDLY GENMASK(20, 16) /* RW */ 258 #define MSDC_PAD_TUNE_CMDRRDLY GENMASK(26, 22) /* RW */ 259 #define MSDC_PAD_TUNE_CLKTDLY GENMASK(31, 27) /* RW */ 260 #define MSDC_PAD_TUNE_RXDLYSEL BIT(15) /* RW */ 261 #define MSDC_PAD_TUNE_RD_SEL BIT(13) /* RW */ 262 #define MSDC_PAD_TUNE_CMD_SEL BIT(21) /* RW */ 263 264 #define PAD_DS_TUNE_DLY_SEL BIT(0) /* RW */ 265 #define PAD_DS_TUNE_DLY1 GENMASK(6, 2) /* RW */ 266 #define PAD_DS_TUNE_DLY2 GENMASK(11, 7) /* RW */ 267 #define PAD_DS_TUNE_DLY3 GENMASK(16, 12) /* RW */ 268 269 #define PAD_CMD_TUNE_RX_DLY3 GENMASK(5, 1) /* RW */ 270 271 /* EMMC51_CFG0 mask */ 272 #define CMDQ_RDAT_CNT GENMASK(21, 12) /* RW */ 273 274 #define EMMC50_CFG_PADCMD_LATCHCK BIT(0) /* RW */ 275 #define EMMC50_CFG_CRCSTS_EDGE BIT(3) /* RW */ 276 #define EMMC50_CFG_CFCSTS_SEL BIT(4) /* RW */ 277 #define EMMC50_CFG_CMD_RESP_SEL BIT(9) /* RW */ 278 279 /* EMMC50_CFG1 mask */ 280 #define EMMC50_CFG1_DS_CFG BIT(28) /* RW */ 281 282 #define EMMC50_CFG3_OUTS_WR GENMASK(4, 0) /* RW */ 283 284 #define SDC_FIFO_CFG_WRVALIDSEL BIT(24) /* RW */ 285 #define SDC_FIFO_CFG_RDVALIDSEL BIT(25) /* RW */ 286 287 /* CQHCI_SETTING */ 288 #define CQHCI_RD_CMD_WND_SEL BIT(14) /* RW */ 289 #define CQHCI_WR_CMD_WND_SEL BIT(15) /* RW */ 290 291 /* EMMC_TOP_CONTROL mask */ 292 #define PAD_RXDLY_SEL BIT(0) /* RW */ 293 #define DELAY_EN BIT(1) /* RW */ 294 #define PAD_DAT_RD_RXDLY2 GENMASK(6, 2) /* RW */ 295 #define PAD_DAT_RD_RXDLY GENMASK(11, 7) /* RW */ 296 #define PAD_DAT_RD_RXDLY2_SEL BIT(12) /* RW */ 297 #define PAD_DAT_RD_RXDLY_SEL BIT(13) /* RW */ 298 #define DATA_K_VALUE_SEL BIT(14) /* RW */ 299 #define SDC_RX_ENH_EN BIT(15) /* TW */ 300 301 /* EMMC_TOP_CMD mask */ 302 #define PAD_CMD_RXDLY2 GENMASK(4, 0) /* RW */ 303 #define PAD_CMD_RXDLY GENMASK(9, 5) /* RW */ 304 #define PAD_CMD_RD_RXDLY2_SEL BIT(10) /* RW */ 305 #define PAD_CMD_RD_RXDLY_SEL BIT(11) /* RW */ 306 #define PAD_CMD_TX_DLY GENMASK(16, 12) /* RW */ 307 308 /* EMMC50_PAD_DS_TUNE mask */ 309 #define PAD_DS_DLY_SEL BIT(16) /* RW */ 310 #define PAD_DS_DLY1 GENMASK(14, 10) /* RW */ 311 #define PAD_DS_DLY3 GENMASK(4, 0) /* RW */ 312 313 #define REQ_CMD_EIO BIT(0) 314 #define REQ_CMD_TMO BIT(1) 315 #define REQ_DAT_ERR BIT(2) 316 #define REQ_STOP_EIO BIT(3) 317 #define REQ_STOP_TMO BIT(4) 318 #define REQ_CMD_BUSY BIT(5) 319 320 #define MSDC_PREPARE_FLAG BIT(0) 321 #define MSDC_ASYNC_FLAG BIT(1) 322 #define MSDC_MMAP_FLAG BIT(2) 323 324 #define MTK_MMC_AUTOSUSPEND_DELAY 50 325 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 326 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 327 328 #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */ 329 330 #define PAD_DELAY_MAX 32 /* PAD delay cells */ 331 /*--------------------------------------------------------------------------*/ 332 /* Descriptor Structure */ 333 /*--------------------------------------------------------------------------*/ 334 struct mt_gpdma_desc { 335 u32 gpd_info; 336 #define GPDMA_DESC_HWO BIT(0) 337 #define GPDMA_DESC_BDP BIT(1) 338 #define GPDMA_DESC_CHECKSUM GENMASK(15, 8) 339 #define GPDMA_DESC_INT BIT(16) 340 #define GPDMA_DESC_NEXT_H4 GENMASK(27, 24) 341 #define GPDMA_DESC_PTR_H4 GENMASK(31, 28) 342 u32 next; 343 u32 ptr; 344 u32 gpd_data_len; 345 #define GPDMA_DESC_BUFLEN GENMASK(15, 0) 346 #define GPDMA_DESC_EXTLEN GENMASK(23, 16) 347 u32 arg; 348 u32 blknum; 349 u32 cmd; 350 }; 351 352 struct mt_bdma_desc { 353 u32 bd_info; 354 #define BDMA_DESC_EOL BIT(0) 355 #define BDMA_DESC_CHECKSUM GENMASK(15, 8) 356 #define BDMA_DESC_BLKPAD BIT(17) 357 #define BDMA_DESC_DWPAD BIT(18) 358 #define BDMA_DESC_NEXT_H4 GENMASK(27, 24) 359 #define BDMA_DESC_PTR_H4 GENMASK(31, 28) 360 u32 next; 361 u32 ptr; 362 u32 bd_data_len; 363 #define BDMA_DESC_BUFLEN GENMASK(15, 0) 364 #define BDMA_DESC_BUFLEN_EXT GENMASK(23, 0) 365 }; 366 367 struct msdc_dma { 368 struct scatterlist *sg; /* I/O scatter list */ 369 struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 370 struct mt_bdma_desc *bd; /* pointer to bd array */ 371 dma_addr_t gpd_addr; /* the physical address of gpd array */ 372 dma_addr_t bd_addr; /* the physical address of bd array */ 373 }; 374 375 struct msdc_save_para { 376 u32 msdc_cfg; 377 u32 iocon; 378 u32 sdc_cfg; 379 u32 pad_tune; 380 u32 patch_bit0; 381 u32 patch_bit1; 382 u32 patch_bit2; 383 u32 pad_ds_tune; 384 u32 pad_cmd_tune; 385 u32 emmc50_cfg0; 386 u32 emmc50_cfg3; 387 u32 sdc_fifo_cfg; 388 u32 emmc_top_control; 389 u32 emmc_top_cmd; 390 u32 emmc50_pad_ds_tune; 391 }; 392 393 struct mtk_mmc_compatible { 394 u8 clk_div_bits; 395 bool recheck_sdio_irq; 396 bool hs400_tune; /* only used for MT8173 */ 397 u32 pad_tune_reg; 398 bool async_fifo; 399 bool data_tune; 400 bool busy_check; 401 bool stop_clk_fix; 402 bool enhance_rx; 403 bool support_64g; 404 bool use_internal_cd; 405 }; 406 407 struct msdc_tune_para { 408 u32 iocon; 409 u32 pad_tune; 410 u32 pad_cmd_tune; 411 u32 emmc_top_control; 412 u32 emmc_top_cmd; 413 }; 414 415 struct msdc_delay_phase { 416 u8 maxlen; 417 u8 start; 418 u8 final_phase; 419 }; 420 421 struct msdc_host { 422 struct device *dev; 423 const struct mtk_mmc_compatible *dev_comp; 424 int cmd_rsp; 425 426 spinlock_t lock; 427 struct mmc_request *mrq; 428 struct mmc_command *cmd; 429 struct mmc_data *data; 430 int error; 431 432 void __iomem *base; /* host base address */ 433 void __iomem *top_base; /* host top register base address */ 434 435 struct msdc_dma dma; /* dma channel */ 436 u64 dma_mask; 437 438 u32 timeout_ns; /* data timeout ns */ 439 u32 timeout_clks; /* data timeout clks */ 440 441 struct pinctrl *pinctrl; 442 struct pinctrl_state *pins_default; 443 struct pinctrl_state *pins_uhs; 444 struct pinctrl_state *pins_eint; 445 struct delayed_work req_timeout; 446 int irq; /* host interrupt */ 447 int eint_irq; /* interrupt from sdio device for waking up system */ 448 struct reset_control *reset; 449 450 struct clk *src_clk; /* msdc source clock */ 451 struct clk *h_clk; /* msdc h_clk */ 452 struct clk *bus_clk; /* bus clock which used to access register */ 453 struct clk *src_clk_cg; /* msdc source clock control gate */ 454 struct clk *sys_clk_cg; /* msdc subsys clock control gate */ 455 struct clk *crypto_clk; /* msdc crypto clock control gate */ 456 struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS]; 457 u32 mclk; /* mmc subsystem clock frequency */ 458 u32 src_clk_freq; /* source clock frequency */ 459 unsigned char timing; 460 bool vqmmc_enabled; 461 u32 latch_ck; 462 u32 hs400_ds_delay; 463 u32 hs400_ds_dly3; 464 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 465 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 466 bool hs400_cmd_resp_sel_rising; 467 /* cmd response sample selection for HS400 */ 468 bool hs400_mode; /* current eMMC will run at hs400 mode */ 469 bool hs400_tuning; /* hs400 mode online tuning */ 470 bool internal_cd; /* Use internal card-detect logic */ 471 bool cqhci; /* support eMMC hw cmdq */ 472 struct msdc_save_para save_para; /* used when gate HCLK */ 473 struct msdc_tune_para def_tune_para; /* default tune setting */ 474 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 475 struct cqhci_host *cq_host; 476 }; 477 478 static const struct mtk_mmc_compatible mt2701_compat = { 479 .clk_div_bits = 12, 480 .recheck_sdio_irq = true, 481 .hs400_tune = false, 482 .pad_tune_reg = MSDC_PAD_TUNE0, 483 .async_fifo = true, 484 .data_tune = true, 485 .busy_check = false, 486 .stop_clk_fix = false, 487 .enhance_rx = false, 488 .support_64g = false, 489 }; 490 491 static const struct mtk_mmc_compatible mt2712_compat = { 492 .clk_div_bits = 12, 493 .recheck_sdio_irq = false, 494 .hs400_tune = false, 495 .pad_tune_reg = MSDC_PAD_TUNE0, 496 .async_fifo = true, 497 .data_tune = true, 498 .busy_check = true, 499 .stop_clk_fix = true, 500 .enhance_rx = true, 501 .support_64g = true, 502 }; 503 504 static const struct mtk_mmc_compatible mt6779_compat = { 505 .clk_div_bits = 12, 506 .recheck_sdio_irq = false, 507 .hs400_tune = false, 508 .pad_tune_reg = MSDC_PAD_TUNE0, 509 .async_fifo = true, 510 .data_tune = true, 511 .busy_check = true, 512 .stop_clk_fix = true, 513 .enhance_rx = true, 514 .support_64g = true, 515 }; 516 517 static const struct mtk_mmc_compatible mt6795_compat = { 518 .clk_div_bits = 8, 519 .recheck_sdio_irq = false, 520 .hs400_tune = true, 521 .pad_tune_reg = MSDC_PAD_TUNE, 522 .async_fifo = false, 523 .data_tune = false, 524 .busy_check = false, 525 .stop_clk_fix = false, 526 .enhance_rx = false, 527 .support_64g = false, 528 }; 529 530 static const struct mtk_mmc_compatible mt7620_compat = { 531 .clk_div_bits = 8, 532 .recheck_sdio_irq = true, 533 .hs400_tune = false, 534 .pad_tune_reg = MSDC_PAD_TUNE, 535 .async_fifo = false, 536 .data_tune = false, 537 .busy_check = false, 538 .stop_clk_fix = false, 539 .enhance_rx = false, 540 .use_internal_cd = true, 541 }; 542 543 static const struct mtk_mmc_compatible mt7622_compat = { 544 .clk_div_bits = 12, 545 .recheck_sdio_irq = true, 546 .hs400_tune = false, 547 .pad_tune_reg = MSDC_PAD_TUNE0, 548 .async_fifo = true, 549 .data_tune = true, 550 .busy_check = true, 551 .stop_clk_fix = true, 552 .enhance_rx = true, 553 .support_64g = false, 554 }; 555 556 static const struct mtk_mmc_compatible mt7986_compat = { 557 .clk_div_bits = 12, 558 .recheck_sdio_irq = true, 559 .hs400_tune = false, 560 .pad_tune_reg = MSDC_PAD_TUNE0, 561 .async_fifo = true, 562 .data_tune = true, 563 .busy_check = true, 564 .stop_clk_fix = true, 565 .enhance_rx = true, 566 .support_64g = true, 567 }; 568 569 static const struct mtk_mmc_compatible mt8135_compat = { 570 .clk_div_bits = 8, 571 .recheck_sdio_irq = true, 572 .hs400_tune = false, 573 .pad_tune_reg = MSDC_PAD_TUNE, 574 .async_fifo = false, 575 .data_tune = false, 576 .busy_check = false, 577 .stop_clk_fix = false, 578 .enhance_rx = false, 579 .support_64g = false, 580 }; 581 582 static const struct mtk_mmc_compatible mt8173_compat = { 583 .clk_div_bits = 8, 584 .recheck_sdio_irq = true, 585 .hs400_tune = true, 586 .pad_tune_reg = MSDC_PAD_TUNE, 587 .async_fifo = false, 588 .data_tune = false, 589 .busy_check = false, 590 .stop_clk_fix = false, 591 .enhance_rx = false, 592 .support_64g = false, 593 }; 594 595 static const struct mtk_mmc_compatible mt8183_compat = { 596 .clk_div_bits = 12, 597 .recheck_sdio_irq = false, 598 .hs400_tune = false, 599 .pad_tune_reg = MSDC_PAD_TUNE0, 600 .async_fifo = true, 601 .data_tune = true, 602 .busy_check = true, 603 .stop_clk_fix = true, 604 .enhance_rx = true, 605 .support_64g = true, 606 }; 607 608 static const struct mtk_mmc_compatible mt8516_compat = { 609 .clk_div_bits = 12, 610 .recheck_sdio_irq = true, 611 .hs400_tune = false, 612 .pad_tune_reg = MSDC_PAD_TUNE0, 613 .async_fifo = true, 614 .data_tune = true, 615 .busy_check = true, 616 .stop_clk_fix = true, 617 }; 618 619 static const struct of_device_id msdc_of_ids[] = { 620 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, 621 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, 622 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, 623 { .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat}, 624 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, 625 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, 626 { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat}, 627 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, 628 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, 629 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, 630 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, 631 632 {} 633 }; 634 MODULE_DEVICE_TABLE(of, msdc_of_ids); 635 636 static void sdr_set_bits(void __iomem *reg, u32 bs) 637 { 638 u32 val = readl(reg); 639 640 val |= bs; 641 writel(val, reg); 642 } 643 644 static void sdr_clr_bits(void __iomem *reg, u32 bs) 645 { 646 u32 val = readl(reg); 647 648 val &= ~bs; 649 writel(val, reg); 650 } 651 652 static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 653 { 654 unsigned int tv = readl(reg); 655 656 tv &= ~field; 657 tv |= ((val) << (ffs((unsigned int)field) - 1)); 658 writel(tv, reg); 659 } 660 661 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 662 { 663 unsigned int tv = readl(reg); 664 665 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 666 } 667 668 static void msdc_reset_hw(struct msdc_host *host) 669 { 670 u32 val; 671 672 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 673 readl_poll_timeout(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0); 674 675 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 676 readl_poll_timeout(host->base + MSDC_FIFOCS, val, 677 !(val & MSDC_FIFOCS_CLR), 0, 0); 678 679 val = readl(host->base + MSDC_INT); 680 writel(val, host->base + MSDC_INT); 681 } 682 683 static void msdc_cmd_next(struct msdc_host *host, 684 struct mmc_request *mrq, struct mmc_command *cmd); 685 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb); 686 687 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 688 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 689 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 690 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 691 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 692 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 693 694 static u8 msdc_dma_calcs(u8 *buf, u32 len) 695 { 696 u32 i, sum = 0; 697 698 for (i = 0; i < len; i++) 699 sum += buf[i]; 700 return 0xff - (u8) sum; 701 } 702 703 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 704 struct mmc_data *data) 705 { 706 unsigned int j, dma_len; 707 dma_addr_t dma_address; 708 u32 dma_ctrl; 709 struct scatterlist *sg; 710 struct mt_gpdma_desc *gpd; 711 struct mt_bdma_desc *bd; 712 713 sg = data->sg; 714 715 gpd = dma->gpd; 716 bd = dma->bd; 717 718 /* modify gpd */ 719 gpd->gpd_info |= GPDMA_DESC_HWO; 720 gpd->gpd_info |= GPDMA_DESC_BDP; 721 /* need to clear first. use these bits to calc checksum */ 722 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 723 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 724 725 /* modify bd */ 726 for_each_sg(data->sg, sg, data->sg_count, j) { 727 dma_address = sg_dma_address(sg); 728 dma_len = sg_dma_len(sg); 729 730 /* init bd */ 731 bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 732 bd[j].bd_info &= ~BDMA_DESC_DWPAD; 733 bd[j].ptr = lower_32_bits(dma_address); 734 if (host->dev_comp->support_64g) { 735 bd[j].bd_info &= ~BDMA_DESC_PTR_H4; 736 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf) 737 << 28; 738 } 739 740 if (host->dev_comp->support_64g) { 741 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT; 742 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT); 743 } else { 744 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 745 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 746 } 747 748 if (j == data->sg_count - 1) /* the last bd */ 749 bd[j].bd_info |= BDMA_DESC_EOL; 750 else 751 bd[j].bd_info &= ~BDMA_DESC_EOL; 752 753 /* checksume need to clear first */ 754 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 755 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 756 } 757 758 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 759 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 760 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 761 dma_ctrl |= (MSDC_BURST_64B << 12 | BIT(8)); 762 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 763 if (host->dev_comp->support_64g) 764 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, 765 upper_32_bits(dma->gpd_addr) & 0xf); 766 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); 767 } 768 769 static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data) 770 { 771 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 772 data->host_cookie |= MSDC_PREPARE_FLAG; 773 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 774 mmc_get_dma_dir(data)); 775 } 776 } 777 778 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data) 779 { 780 if (data->host_cookie & MSDC_ASYNC_FLAG) 781 return; 782 783 if (data->host_cookie & MSDC_PREPARE_FLAG) { 784 dma_unmap_sg(host->dev, data->sg, data->sg_len, 785 mmc_get_dma_dir(data)); 786 data->host_cookie &= ~MSDC_PREPARE_FLAG; 787 } 788 } 789 790 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) 791 { 792 struct mmc_host *mmc = mmc_from_priv(host); 793 u64 timeout, clk_ns; 794 u32 mode = 0; 795 796 if (mmc->actual_clock == 0) { 797 timeout = 0; 798 } else { 799 clk_ns = 1000000000ULL; 800 do_div(clk_ns, mmc->actual_clock); 801 timeout = ns + clk_ns - 1; 802 do_div(timeout, clk_ns); 803 timeout += clks; 804 /* in 1048576 sclk cycle unit */ 805 timeout = DIV_ROUND_UP(timeout, BIT(20)); 806 if (host->dev_comp->clk_div_bits == 8) 807 sdr_get_field(host->base + MSDC_CFG, 808 MSDC_CFG_CKMOD, &mode); 809 else 810 sdr_get_field(host->base + MSDC_CFG, 811 MSDC_CFG_CKMOD_EXTRA, &mode); 812 /*DDR mode will double the clk cycles for data timeout */ 813 timeout = mode >= 2 ? timeout * 2 : timeout; 814 timeout = timeout > 1 ? timeout - 1 : 0; 815 } 816 return timeout; 817 } 818 819 /* clock control primitives */ 820 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) 821 { 822 u64 timeout; 823 824 host->timeout_ns = ns; 825 host->timeout_clks = clks; 826 827 timeout = msdc_timeout_cal(host, ns, clks); 828 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 829 (u32)(timeout > 255 ? 255 : timeout)); 830 } 831 832 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) 833 { 834 u64 timeout; 835 836 timeout = msdc_timeout_cal(host, ns, clks); 837 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, 838 (u32)(timeout > 8191 ? 8191 : timeout)); 839 } 840 841 static void msdc_gate_clock(struct msdc_host *host) 842 { 843 clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); 844 clk_disable_unprepare(host->crypto_clk); 845 clk_disable_unprepare(host->src_clk_cg); 846 clk_disable_unprepare(host->src_clk); 847 clk_disable_unprepare(host->bus_clk); 848 clk_disable_unprepare(host->h_clk); 849 } 850 851 static int msdc_ungate_clock(struct msdc_host *host) 852 { 853 u32 val; 854 int ret; 855 856 clk_prepare_enable(host->h_clk); 857 clk_prepare_enable(host->bus_clk); 858 clk_prepare_enable(host->src_clk); 859 clk_prepare_enable(host->src_clk_cg); 860 clk_prepare_enable(host->crypto_clk); 861 ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); 862 if (ret) { 863 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); 864 return ret; 865 } 866 867 return readl_poll_timeout(host->base + MSDC_CFG, val, 868 (val & MSDC_CFG_CKSTB), 1, 20000); 869 } 870 871 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 872 { 873 struct mmc_host *mmc = mmc_from_priv(host); 874 u32 mode; 875 u32 flags; 876 u32 div; 877 u32 sclk; 878 u32 tune_reg = host->dev_comp->pad_tune_reg; 879 u32 val; 880 881 if (!hz) { 882 dev_dbg(host->dev, "set mclk to 0\n"); 883 host->mclk = 0; 884 mmc->actual_clock = 0; 885 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 886 return; 887 } 888 889 flags = readl(host->base + MSDC_INTEN); 890 sdr_clr_bits(host->base + MSDC_INTEN, flags); 891 if (host->dev_comp->clk_div_bits == 8) 892 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 893 else 894 sdr_clr_bits(host->base + MSDC_CFG, 895 MSDC_CFG_HS400_CK_MODE_EXTRA); 896 if (timing == MMC_TIMING_UHS_DDR50 || 897 timing == MMC_TIMING_MMC_DDR52 || 898 timing == MMC_TIMING_MMC_HS400) { 899 if (timing == MMC_TIMING_MMC_HS400) 900 mode = 0x3; 901 else 902 mode = 0x2; /* ddr mode and use divisor */ 903 904 if (hz >= (host->src_clk_freq >> 2)) { 905 div = 0; /* mean div = 1/4 */ 906 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 907 } else { 908 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 909 sclk = (host->src_clk_freq >> 2) / div; 910 div = (div >> 1); 911 } 912 913 if (timing == MMC_TIMING_MMC_HS400 && 914 hz >= (host->src_clk_freq >> 1)) { 915 if (host->dev_comp->clk_div_bits == 8) 916 sdr_set_bits(host->base + MSDC_CFG, 917 MSDC_CFG_HS400_CK_MODE); 918 else 919 sdr_set_bits(host->base + MSDC_CFG, 920 MSDC_CFG_HS400_CK_MODE_EXTRA); 921 sclk = host->src_clk_freq >> 1; 922 div = 0; /* div is ignore when bit18 is set */ 923 } 924 } else if (hz >= host->src_clk_freq) { 925 mode = 0x1; /* no divisor */ 926 div = 0; 927 sclk = host->src_clk_freq; 928 } else { 929 mode = 0x0; /* use divisor */ 930 if (hz >= (host->src_clk_freq >> 1)) { 931 div = 0; /* mean div = 1/2 */ 932 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 933 } else { 934 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 935 sclk = (host->src_clk_freq >> 2) / div; 936 } 937 } 938 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 939 940 clk_disable_unprepare(host->src_clk_cg); 941 if (host->dev_comp->clk_div_bits == 8) 942 sdr_set_field(host->base + MSDC_CFG, 943 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 944 (mode << 8) | div); 945 else 946 sdr_set_field(host->base + MSDC_CFG, 947 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, 948 (mode << 12) | div); 949 950 clk_prepare_enable(host->src_clk_cg); 951 readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0); 952 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 953 mmc->actual_clock = sclk; 954 host->mclk = hz; 955 host->timing = timing; 956 /* need because clk changed. */ 957 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 958 sdr_set_bits(host->base + MSDC_INTEN, flags); 959 960 /* 961 * mmc_select_hs400() will drop to 50Mhz and High speed mode, 962 * tune result of hs200/200Mhz is not suitable for 50Mhz 963 */ 964 if (mmc->actual_clock <= 52000000) { 965 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 966 if (host->top_base) { 967 writel(host->def_tune_para.emmc_top_control, 968 host->top_base + EMMC_TOP_CONTROL); 969 writel(host->def_tune_para.emmc_top_cmd, 970 host->top_base + EMMC_TOP_CMD); 971 } else { 972 writel(host->def_tune_para.pad_tune, 973 host->base + tune_reg); 974 } 975 } else { 976 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 977 writel(host->saved_tune_para.pad_cmd_tune, 978 host->base + PAD_CMD_TUNE); 979 if (host->top_base) { 980 writel(host->saved_tune_para.emmc_top_control, 981 host->top_base + EMMC_TOP_CONTROL); 982 writel(host->saved_tune_para.emmc_top_cmd, 983 host->top_base + EMMC_TOP_CMD); 984 } else { 985 writel(host->saved_tune_para.pad_tune, 986 host->base + tune_reg); 987 } 988 } 989 990 if (timing == MMC_TIMING_MMC_HS400 && 991 host->dev_comp->hs400_tune) 992 sdr_set_field(host->base + tune_reg, 993 MSDC_PAD_TUNE_CMDRRDLY, 994 host->hs400_cmd_int_delay); 995 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock, 996 timing); 997 } 998 999 static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 1000 struct mmc_command *cmd) 1001 { 1002 u32 resp; 1003 1004 switch (mmc_resp_type(cmd)) { 1005 /* Actually, R1, R5, R6, R7 are the same */ 1006 case MMC_RSP_R1: 1007 resp = 0x1; 1008 break; 1009 case MMC_RSP_R1B: 1010 resp = 0x7; 1011 break; 1012 case MMC_RSP_R2: 1013 resp = 0x2; 1014 break; 1015 case MMC_RSP_R3: 1016 resp = 0x3; 1017 break; 1018 case MMC_RSP_NONE: 1019 default: 1020 resp = 0x0; 1021 break; 1022 } 1023 1024 return resp; 1025 } 1026 1027 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 1028 struct mmc_request *mrq, struct mmc_command *cmd) 1029 { 1030 struct mmc_host *mmc = mmc_from_priv(host); 1031 /* rawcmd : 1032 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 1033 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 1034 */ 1035 u32 opcode = cmd->opcode; 1036 u32 resp = msdc_cmd_find_resp(host, cmd); 1037 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 1038 1039 host->cmd_rsp = resp; 1040 1041 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 1042 opcode == MMC_STOP_TRANSMISSION) 1043 rawcmd |= BIT(14); 1044 else if (opcode == SD_SWITCH_VOLTAGE) 1045 rawcmd |= BIT(30); 1046 else if (opcode == SD_APP_SEND_SCR || 1047 opcode == SD_APP_SEND_NUM_WR_BLKS || 1048 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 1049 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 1050 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 1051 rawcmd |= BIT(11); 1052 1053 if (cmd->data) { 1054 struct mmc_data *data = cmd->data; 1055 1056 if (mmc_op_multi(opcode)) { 1057 if (mmc_card_mmc(mmc->card) && mrq->sbc && 1058 !(mrq->sbc->arg & 0xFFFF0000)) 1059 rawcmd |= BIT(29); /* AutoCMD23 */ 1060 } 1061 1062 rawcmd |= ((data->blksz & 0xFFF) << 16); 1063 if (data->flags & MMC_DATA_WRITE) 1064 rawcmd |= BIT(13); 1065 if (data->blocks > 1) 1066 rawcmd |= BIT(12); 1067 else 1068 rawcmd |= BIT(11); 1069 /* Always use dma mode */ 1070 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 1071 1072 if (host->timeout_ns != data->timeout_ns || 1073 host->timeout_clks != data->timeout_clks) 1074 msdc_set_timeout(host, data->timeout_ns, 1075 data->timeout_clks); 1076 1077 writel(data->blocks, host->base + SDC_BLK_NUM); 1078 } 1079 return rawcmd; 1080 } 1081 1082 static void msdc_start_data(struct msdc_host *host, struct mmc_command *cmd, 1083 struct mmc_data *data) 1084 { 1085 bool read; 1086 1087 WARN_ON(host->data); 1088 host->data = data; 1089 read = data->flags & MMC_DATA_READ; 1090 1091 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1092 msdc_dma_setup(host, &host->dma, data); 1093 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 1094 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 1095 dev_dbg(host->dev, "DMA start\n"); 1096 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 1097 __func__, cmd->opcode, data->blocks, read); 1098 } 1099 1100 static int msdc_auto_cmd_done(struct msdc_host *host, int events, 1101 struct mmc_command *cmd) 1102 { 1103 u32 *rsp = cmd->resp; 1104 1105 rsp[0] = readl(host->base + SDC_ACMD_RESP); 1106 1107 if (events & MSDC_INT_ACMDRDY) { 1108 cmd->error = 0; 1109 } else { 1110 msdc_reset_hw(host); 1111 if (events & MSDC_INT_ACMDCRCERR) { 1112 cmd->error = -EILSEQ; 1113 host->error |= REQ_STOP_EIO; 1114 } else if (events & MSDC_INT_ACMDTMO) { 1115 cmd->error = -ETIMEDOUT; 1116 host->error |= REQ_STOP_TMO; 1117 } 1118 dev_err(host->dev, 1119 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 1120 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 1121 } 1122 return cmd->error; 1123 } 1124 1125 /* 1126 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost 1127 * 1128 * Host controller may lost interrupt in some special case. 1129 * Add SDIO irq recheck mechanism to make sure all interrupts 1130 * can be processed immediately 1131 */ 1132 static void msdc_recheck_sdio_irq(struct msdc_host *host) 1133 { 1134 struct mmc_host *mmc = mmc_from_priv(host); 1135 u32 reg_int, reg_inten, reg_ps; 1136 1137 if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1138 reg_inten = readl(host->base + MSDC_INTEN); 1139 if (reg_inten & MSDC_INTEN_SDIOIRQ) { 1140 reg_int = readl(host->base + MSDC_INT); 1141 reg_ps = readl(host->base + MSDC_PS); 1142 if (!(reg_int & MSDC_INT_SDIOIRQ || 1143 reg_ps & MSDC_PS_DATA1)) { 1144 __msdc_enable_sdio_irq(host, 0); 1145 sdio_signal_irq(mmc); 1146 } 1147 } 1148 } 1149 } 1150 1151 static void msdc_track_cmd_data(struct msdc_host *host, struct mmc_command *cmd) 1152 { 1153 if (host->error) 1154 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 1155 __func__, cmd->opcode, cmd->arg, host->error); 1156 } 1157 1158 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 1159 { 1160 unsigned long flags; 1161 1162 /* 1163 * No need check the return value of cancel_delayed_work, as only ONE 1164 * path will go here! 1165 */ 1166 cancel_delayed_work(&host->req_timeout); 1167 1168 spin_lock_irqsave(&host->lock, flags); 1169 host->mrq = NULL; 1170 spin_unlock_irqrestore(&host->lock, flags); 1171 1172 msdc_track_cmd_data(host, mrq->cmd); 1173 if (mrq->data) 1174 msdc_unprepare_data(host, mrq->data); 1175 if (host->error) 1176 msdc_reset_hw(host); 1177 mmc_request_done(mmc_from_priv(host), mrq); 1178 if (host->dev_comp->recheck_sdio_irq) 1179 msdc_recheck_sdio_irq(host); 1180 } 1181 1182 /* returns true if command is fully handled; returns false otherwise */ 1183 static bool msdc_cmd_done(struct msdc_host *host, int events, 1184 struct mmc_request *mrq, struct mmc_command *cmd) 1185 { 1186 bool done = false; 1187 bool sbc_error; 1188 unsigned long flags; 1189 u32 *rsp; 1190 1191 if (mrq->sbc && cmd == mrq->cmd && 1192 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 1193 | MSDC_INT_ACMDTMO))) 1194 msdc_auto_cmd_done(host, events, mrq->sbc); 1195 1196 sbc_error = mrq->sbc && mrq->sbc->error; 1197 1198 if (!sbc_error && !(events & (MSDC_INT_CMDRDY 1199 | MSDC_INT_RSPCRCERR 1200 | MSDC_INT_CMDTMO))) 1201 return done; 1202 1203 spin_lock_irqsave(&host->lock, flags); 1204 done = !host->cmd; 1205 host->cmd = NULL; 1206 spin_unlock_irqrestore(&host->lock, flags); 1207 1208 if (done) 1209 return true; 1210 rsp = cmd->resp; 1211 1212 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1213 1214 if (cmd->flags & MMC_RSP_PRESENT) { 1215 if (cmd->flags & MMC_RSP_136) { 1216 rsp[0] = readl(host->base + SDC_RESP3); 1217 rsp[1] = readl(host->base + SDC_RESP2); 1218 rsp[2] = readl(host->base + SDC_RESP1); 1219 rsp[3] = readl(host->base + SDC_RESP0); 1220 } else { 1221 rsp[0] = readl(host->base + SDC_RESP0); 1222 } 1223 } 1224 1225 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 1226 if (events & MSDC_INT_CMDTMO || 1227 (cmd->opcode != MMC_SEND_TUNING_BLOCK && 1228 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200 && 1229 !host->hs400_tuning)) 1230 /* 1231 * should not clear fifo/interrupt as the tune data 1232 * may have alreay come when cmd19/cmd21 gets response 1233 * CRC error. 1234 */ 1235 msdc_reset_hw(host); 1236 if (events & MSDC_INT_RSPCRCERR) { 1237 cmd->error = -EILSEQ; 1238 host->error |= REQ_CMD_EIO; 1239 } else if (events & MSDC_INT_CMDTMO) { 1240 cmd->error = -ETIMEDOUT; 1241 host->error |= REQ_CMD_TMO; 1242 } 1243 } 1244 if (cmd->error) 1245 dev_dbg(host->dev, 1246 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 1247 __func__, cmd->opcode, cmd->arg, rsp[0], 1248 cmd->error); 1249 1250 msdc_cmd_next(host, mrq, cmd); 1251 return true; 1252 } 1253 1254 /* It is the core layer's responsibility to ensure card status 1255 * is correct before issue a request. but host design do below 1256 * checks recommended. 1257 */ 1258 static inline bool msdc_cmd_is_ready(struct msdc_host *host, 1259 struct mmc_request *mrq, struct mmc_command *cmd) 1260 { 1261 u32 val; 1262 int ret; 1263 1264 /* The max busy time we can endure is 20ms */ 1265 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, 1266 !(val & SDC_STS_CMDBUSY), 1, 20000); 1267 if (ret) { 1268 dev_err(host->dev, "CMD bus busy detected\n"); 1269 host->error |= REQ_CMD_BUSY; 1270 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1271 return false; 1272 } 1273 1274 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 1275 /* R1B or with data, should check SDCBUSY */ 1276 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, 1277 !(val & SDC_STS_SDCBUSY), 1, 20000); 1278 if (ret) { 1279 dev_err(host->dev, "Controller busy detected\n"); 1280 host->error |= REQ_CMD_BUSY; 1281 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1282 return false; 1283 } 1284 } 1285 return true; 1286 } 1287 1288 static void msdc_start_command(struct msdc_host *host, 1289 struct mmc_request *mrq, struct mmc_command *cmd) 1290 { 1291 u32 rawcmd; 1292 unsigned long flags; 1293 1294 WARN_ON(host->cmd); 1295 host->cmd = cmd; 1296 1297 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1298 if (!msdc_cmd_is_ready(host, mrq, cmd)) 1299 return; 1300 1301 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 1302 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 1303 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 1304 msdc_reset_hw(host); 1305 } 1306 1307 cmd->error = 0; 1308 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 1309 1310 spin_lock_irqsave(&host->lock, flags); 1311 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1312 spin_unlock_irqrestore(&host->lock, flags); 1313 1314 writel(cmd->arg, host->base + SDC_ARG); 1315 writel(rawcmd, host->base + SDC_CMD); 1316 } 1317 1318 static void msdc_cmd_next(struct msdc_host *host, 1319 struct mmc_request *mrq, struct mmc_command *cmd) 1320 { 1321 if ((cmd->error && 1322 !(cmd->error == -EILSEQ && 1323 (cmd->opcode == MMC_SEND_TUNING_BLOCK || 1324 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200 || 1325 host->hs400_tuning))) || 1326 (mrq->sbc && mrq->sbc->error)) 1327 msdc_request_done(host, mrq); 1328 else if (cmd == mrq->sbc) 1329 msdc_start_command(host, mrq, mrq->cmd); 1330 else if (!cmd->data) 1331 msdc_request_done(host, mrq); 1332 else 1333 msdc_start_data(host, cmd, cmd->data); 1334 } 1335 1336 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 1337 { 1338 struct msdc_host *host = mmc_priv(mmc); 1339 1340 host->error = 0; 1341 WARN_ON(host->mrq); 1342 host->mrq = mrq; 1343 1344 if (mrq->data) 1345 msdc_prepare_data(host, mrq->data); 1346 1347 /* if SBC is required, we have HW option and SW option. 1348 * if HW option is enabled, and SBC does not have "special" flags, 1349 * use HW option, otherwise use SW option 1350 */ 1351 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 1352 (mrq->sbc->arg & 0xFFFF0000))) 1353 msdc_start_command(host, mrq, mrq->sbc); 1354 else 1355 msdc_start_command(host, mrq, mrq->cmd); 1356 } 1357 1358 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 1359 { 1360 struct msdc_host *host = mmc_priv(mmc); 1361 struct mmc_data *data = mrq->data; 1362 1363 if (!data) 1364 return; 1365 1366 msdc_prepare_data(host, data); 1367 data->host_cookie |= MSDC_ASYNC_FLAG; 1368 } 1369 1370 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1371 int err) 1372 { 1373 struct msdc_host *host = mmc_priv(mmc); 1374 struct mmc_data *data = mrq->data; 1375 1376 if (!data) 1377 return; 1378 1379 if (data->host_cookie) { 1380 data->host_cookie &= ~MSDC_ASYNC_FLAG; 1381 msdc_unprepare_data(host, data); 1382 } 1383 } 1384 1385 static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq) 1386 { 1387 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 1388 !mrq->sbc) 1389 msdc_start_command(host, mrq, mrq->stop); 1390 else 1391 msdc_request_done(host, mrq); 1392 } 1393 1394 static void msdc_data_xfer_done(struct msdc_host *host, u32 events, 1395 struct mmc_request *mrq, struct mmc_data *data) 1396 { 1397 struct mmc_command *stop; 1398 unsigned long flags; 1399 bool done; 1400 unsigned int check_data = events & 1401 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 1402 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 1403 | MSDC_INT_DMA_PROTECT); 1404 u32 val; 1405 int ret; 1406 1407 spin_lock_irqsave(&host->lock, flags); 1408 done = !host->data; 1409 if (check_data) 1410 host->data = NULL; 1411 spin_unlock_irqrestore(&host->lock, flags); 1412 1413 if (done) 1414 return; 1415 stop = data->stop; 1416 1417 if (check_data || (stop && stop->error)) { 1418 dev_dbg(host->dev, "DMA status: 0x%8X\n", 1419 readl(host->base + MSDC_DMA_CFG)); 1420 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1421 1); 1422 1423 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val, 1424 !(val & MSDC_DMA_CTRL_STOP), 1, 20000); 1425 if (ret) 1426 dev_dbg(host->dev, "DMA stop timed out\n"); 1427 1428 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val, 1429 !(val & MSDC_DMA_CFG_STS), 1, 20000); 1430 if (ret) 1431 dev_dbg(host->dev, "DMA inactive timed out\n"); 1432 1433 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 1434 dev_dbg(host->dev, "DMA stop\n"); 1435 1436 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 1437 data->bytes_xfered = data->blocks * data->blksz; 1438 } else { 1439 dev_dbg(host->dev, "interrupt events: %x\n", events); 1440 msdc_reset_hw(host); 1441 host->error |= REQ_DAT_ERR; 1442 data->bytes_xfered = 0; 1443 1444 if (events & MSDC_INT_DATTMO) 1445 data->error = -ETIMEDOUT; 1446 else if (events & MSDC_INT_DATCRCERR) 1447 data->error = -EILSEQ; 1448 1449 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 1450 __func__, mrq->cmd->opcode, data->blocks); 1451 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 1452 (int)data->error, data->bytes_xfered); 1453 } 1454 1455 msdc_data_xfer_next(host, mrq); 1456 } 1457 } 1458 1459 static void msdc_set_buswidth(struct msdc_host *host, u32 width) 1460 { 1461 u32 val = readl(host->base + SDC_CFG); 1462 1463 val &= ~SDC_CFG_BUSWIDTH; 1464 1465 switch (width) { 1466 default: 1467 case MMC_BUS_WIDTH_1: 1468 val |= (MSDC_BUS_1BITS << 16); 1469 break; 1470 case MMC_BUS_WIDTH_4: 1471 val |= (MSDC_BUS_4BITS << 16); 1472 break; 1473 case MMC_BUS_WIDTH_8: 1474 val |= (MSDC_BUS_8BITS << 16); 1475 break; 1476 } 1477 1478 writel(val, host->base + SDC_CFG); 1479 dev_dbg(host->dev, "Bus Width = %d", width); 1480 } 1481 1482 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 1483 { 1484 struct msdc_host *host = mmc_priv(mmc); 1485 int ret; 1486 1487 if (!IS_ERR(mmc->supply.vqmmc)) { 1488 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1489 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 1490 dev_err(host->dev, "Unsupported signal voltage!\n"); 1491 return -EINVAL; 1492 } 1493 1494 ret = mmc_regulator_set_vqmmc(mmc, ios); 1495 if (ret < 0) { 1496 dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1497 ret, ios->signal_voltage); 1498 return ret; 1499 } 1500 1501 /* Apply different pinctrl settings for different signal voltage */ 1502 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 1503 pinctrl_select_state(host->pinctrl, host->pins_uhs); 1504 else 1505 pinctrl_select_state(host->pinctrl, host->pins_default); 1506 } 1507 return 0; 1508 } 1509 1510 static int msdc_card_busy(struct mmc_host *mmc) 1511 { 1512 struct msdc_host *host = mmc_priv(mmc); 1513 u32 status = readl(host->base + MSDC_PS); 1514 1515 /* only check if data0 is low */ 1516 return !(status & BIT(16)); 1517 } 1518 1519 static void msdc_request_timeout(struct work_struct *work) 1520 { 1521 struct msdc_host *host = container_of(work, struct msdc_host, 1522 req_timeout.work); 1523 1524 /* simulate HW timeout status */ 1525 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 1526 if (host->mrq) { 1527 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 1528 host->mrq, host->mrq->cmd->opcode); 1529 if (host->cmd) { 1530 dev_err(host->dev, "%s: aborting cmd=%d\n", 1531 __func__, host->cmd->opcode); 1532 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 1533 host->cmd); 1534 } else if (host->data) { 1535 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 1536 __func__, host->mrq->cmd->opcode, 1537 host->data->blocks); 1538 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 1539 host->data); 1540 } 1541 } 1542 } 1543 1544 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb) 1545 { 1546 if (enb) { 1547 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1548 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1549 if (host->dev_comp->recheck_sdio_irq) 1550 msdc_recheck_sdio_irq(host); 1551 } else { 1552 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1553 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1554 } 1555 } 1556 1557 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) 1558 { 1559 struct msdc_host *host = mmc_priv(mmc); 1560 unsigned long flags; 1561 int ret; 1562 1563 spin_lock_irqsave(&host->lock, flags); 1564 __msdc_enable_sdio_irq(host, enb); 1565 spin_unlock_irqrestore(&host->lock, flags); 1566 1567 if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) { 1568 if (enb) { 1569 /* 1570 * In dev_pm_set_dedicated_wake_irq_reverse(), eint pin will be set to 1571 * GPIO mode. We need to restore it to SDIO DAT1 mode after that. 1572 * Since the current pinstate is pins_uhs, to ensure pinctrl select take 1573 * affect successfully, we change the pinstate to pins_eint firstly. 1574 */ 1575 pinctrl_select_state(host->pinctrl, host->pins_eint); 1576 ret = dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq); 1577 1578 if (ret) { 1579 dev_err(host->dev, "Failed to register SDIO wakeup irq!\n"); 1580 host->pins_eint = NULL; 1581 pm_runtime_get_noresume(host->dev); 1582 } else { 1583 dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq); 1584 } 1585 1586 pinctrl_select_state(host->pinctrl, host->pins_uhs); 1587 } else { 1588 dev_pm_clear_wake_irq(host->dev); 1589 } 1590 } else { 1591 if (enb) { 1592 /* Ensure host->pins_eint is NULL */ 1593 host->pins_eint = NULL; 1594 pm_runtime_get_noresume(host->dev); 1595 } else { 1596 pm_runtime_put_noidle(host->dev); 1597 } 1598 } 1599 } 1600 1601 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) 1602 { 1603 struct mmc_host *mmc = mmc_from_priv(host); 1604 int cmd_err = 0, dat_err = 0; 1605 1606 if (intsts & MSDC_INT_RSPCRCERR) { 1607 cmd_err = -EILSEQ; 1608 dev_err(host->dev, "%s: CMD CRC ERR", __func__); 1609 } else if (intsts & MSDC_INT_CMDTMO) { 1610 cmd_err = -ETIMEDOUT; 1611 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); 1612 } 1613 1614 if (intsts & MSDC_INT_DATCRCERR) { 1615 dat_err = -EILSEQ; 1616 dev_err(host->dev, "%s: DATA CRC ERR", __func__); 1617 } else if (intsts & MSDC_INT_DATTMO) { 1618 dat_err = -ETIMEDOUT; 1619 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); 1620 } 1621 1622 if (cmd_err || dat_err) { 1623 dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", 1624 cmd_err, dat_err, intsts); 1625 } 1626 1627 return cqhci_irq(mmc, 0, cmd_err, dat_err); 1628 } 1629 1630 static irqreturn_t msdc_irq(int irq, void *dev_id) 1631 { 1632 struct msdc_host *host = (struct msdc_host *) dev_id; 1633 struct mmc_host *mmc = mmc_from_priv(host); 1634 1635 while (true) { 1636 struct mmc_request *mrq; 1637 struct mmc_command *cmd; 1638 struct mmc_data *data; 1639 u32 events, event_mask; 1640 1641 spin_lock(&host->lock); 1642 events = readl(host->base + MSDC_INT); 1643 event_mask = readl(host->base + MSDC_INTEN); 1644 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1645 __msdc_enable_sdio_irq(host, 0); 1646 /* clear interrupts */ 1647 writel(events & event_mask, host->base + MSDC_INT); 1648 1649 mrq = host->mrq; 1650 cmd = host->cmd; 1651 data = host->data; 1652 spin_unlock(&host->lock); 1653 1654 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1655 sdio_signal_irq(mmc); 1656 1657 if ((events & event_mask) & MSDC_INT_CDSC) { 1658 if (host->internal_cd) 1659 mmc_detect_change(mmc, msecs_to_jiffies(20)); 1660 events &= ~MSDC_INT_CDSC; 1661 } 1662 1663 if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) 1664 break; 1665 1666 if ((mmc->caps2 & MMC_CAP2_CQE) && 1667 (events & MSDC_INT_CMDQ)) { 1668 msdc_cmdq_irq(host, events); 1669 /* clear interrupts */ 1670 writel(events, host->base + MSDC_INT); 1671 return IRQ_HANDLED; 1672 } 1673 1674 if (!mrq) { 1675 dev_err(host->dev, 1676 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 1677 __func__, events, event_mask); 1678 WARN_ON(1); 1679 break; 1680 } 1681 1682 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 1683 1684 if (cmd) 1685 msdc_cmd_done(host, events, mrq, cmd); 1686 else if (data) 1687 msdc_data_xfer_done(host, events, mrq, data); 1688 } 1689 1690 return IRQ_HANDLED; 1691 } 1692 1693 static void msdc_init_hw(struct msdc_host *host) 1694 { 1695 u32 val; 1696 u32 tune_reg = host->dev_comp->pad_tune_reg; 1697 struct mmc_host *mmc = mmc_from_priv(host); 1698 1699 if (host->reset) { 1700 reset_control_assert(host->reset); 1701 usleep_range(10, 50); 1702 reset_control_deassert(host->reset); 1703 } 1704 1705 /* Configure to MMC/SD mode, clock free running */ 1706 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 1707 1708 /* Reset */ 1709 msdc_reset_hw(host); 1710 1711 /* Disable and clear all interrupts */ 1712 writel(0, host->base + MSDC_INTEN); 1713 val = readl(host->base + MSDC_INT); 1714 writel(val, host->base + MSDC_INT); 1715 1716 /* Configure card detection */ 1717 if (host->internal_cd) { 1718 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, 1719 DEFAULT_DEBOUNCE); 1720 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1721 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1722 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1723 } else { 1724 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1725 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1726 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1727 } 1728 1729 if (host->top_base) { 1730 writel(0, host->top_base + EMMC_TOP_CONTROL); 1731 writel(0, host->top_base + EMMC_TOP_CMD); 1732 } else { 1733 writel(0, host->base + tune_reg); 1734 } 1735 writel(0, host->base + MSDC_IOCON); 1736 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 1737 writel(0x403c0046, host->base + MSDC_PATCH_BIT); 1738 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 1739 writel(0xffff4089, host->base + MSDC_PATCH_BIT1); 1740 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1741 1742 if (host->dev_comp->stop_clk_fix) { 1743 sdr_set_field(host->base + MSDC_PATCH_BIT1, 1744 MSDC_PATCH_BIT1_STOP_DLY, 3); 1745 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1746 SDC_FIFO_CFG_WRVALIDSEL); 1747 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1748 SDC_FIFO_CFG_RDVALIDSEL); 1749 } 1750 1751 if (host->dev_comp->busy_check) 1752 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7)); 1753 1754 if (host->dev_comp->async_fifo) { 1755 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1756 MSDC_PB2_RESPWAIT, 3); 1757 if (host->dev_comp->enhance_rx) { 1758 if (host->top_base) 1759 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1760 SDC_RX_ENH_EN); 1761 else 1762 sdr_set_bits(host->base + SDC_ADV_CFG0, 1763 SDC_RX_ENHANCE_EN); 1764 } else { 1765 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1766 MSDC_PB2_RESPSTSENSEL, 2); 1767 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1768 MSDC_PB2_CRCSTSENSEL, 2); 1769 } 1770 /* use async fifo, then no need tune internal delay */ 1771 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, 1772 MSDC_PATCH_BIT2_CFGRESP); 1773 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1774 MSDC_PATCH_BIT2_CFGCRCSTS); 1775 } 1776 1777 if (host->dev_comp->support_64g) 1778 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1779 MSDC_PB2_SUPPORT_64G); 1780 if (host->dev_comp->data_tune) { 1781 if (host->top_base) { 1782 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1783 PAD_DAT_RD_RXDLY_SEL); 1784 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, 1785 DATA_K_VALUE_SEL); 1786 sdr_set_bits(host->top_base + EMMC_TOP_CMD, 1787 PAD_CMD_RD_RXDLY_SEL); 1788 } else { 1789 sdr_set_bits(host->base + tune_reg, 1790 MSDC_PAD_TUNE_RD_SEL | 1791 MSDC_PAD_TUNE_CMD_SEL); 1792 } 1793 } else { 1794 /* choose clock tune */ 1795 if (host->top_base) 1796 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1797 PAD_RXDLY_SEL); 1798 else 1799 sdr_set_bits(host->base + tune_reg, 1800 MSDC_PAD_TUNE_RXDLYSEL); 1801 } 1802 1803 if (mmc->caps2 & MMC_CAP2_NO_SDIO) { 1804 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1805 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1806 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 1807 } else { 1808 /* Configure to enable SDIO mode, otherwise SDIO CMD5 fails */ 1809 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1810 1811 /* Config SDIO device detect interrupt function */ 1812 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1813 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 1814 } 1815 1816 /* Configure to default data timeout */ 1817 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 1818 1819 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 1820 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1821 if (host->top_base) { 1822 host->def_tune_para.emmc_top_control = 1823 readl(host->top_base + EMMC_TOP_CONTROL); 1824 host->def_tune_para.emmc_top_cmd = 1825 readl(host->top_base + EMMC_TOP_CMD); 1826 host->saved_tune_para.emmc_top_control = 1827 readl(host->top_base + EMMC_TOP_CONTROL); 1828 host->saved_tune_para.emmc_top_cmd = 1829 readl(host->top_base + EMMC_TOP_CMD); 1830 } else { 1831 host->def_tune_para.pad_tune = readl(host->base + tune_reg); 1832 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 1833 } 1834 dev_dbg(host->dev, "init hardware done!"); 1835 } 1836 1837 static void msdc_deinit_hw(struct msdc_host *host) 1838 { 1839 u32 val; 1840 1841 if (host->internal_cd) { 1842 /* Disabled card-detect */ 1843 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1844 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1845 } 1846 1847 /* Disable and clear all interrupts */ 1848 writel(0, host->base + MSDC_INTEN); 1849 1850 val = readl(host->base + MSDC_INT); 1851 writel(val, host->base + MSDC_INT); 1852 } 1853 1854 /* init gpd and bd list in msdc_drv_probe */ 1855 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 1856 { 1857 struct mt_gpdma_desc *gpd = dma->gpd; 1858 struct mt_bdma_desc *bd = dma->bd; 1859 dma_addr_t dma_addr; 1860 int i; 1861 1862 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 1863 1864 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); 1865 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 1866 /* gpd->next is must set for desc DMA 1867 * That's why must alloc 2 gpd structure. 1868 */ 1869 gpd->next = lower_32_bits(dma_addr); 1870 if (host->dev_comp->support_64g) 1871 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1872 1873 dma_addr = dma->bd_addr; 1874 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ 1875 if (host->dev_comp->support_64g) 1876 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; 1877 1878 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 1879 for (i = 0; i < (MAX_BD_NUM - 1); i++) { 1880 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); 1881 bd[i].next = lower_32_bits(dma_addr); 1882 if (host->dev_comp->support_64g) 1883 bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1884 } 1885 } 1886 1887 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1888 { 1889 struct msdc_host *host = mmc_priv(mmc); 1890 int ret; 1891 1892 msdc_set_buswidth(host, ios->bus_width); 1893 1894 /* Suspend/Resume will do power off/on */ 1895 switch (ios->power_mode) { 1896 case MMC_POWER_UP: 1897 if (!IS_ERR(mmc->supply.vmmc)) { 1898 msdc_init_hw(host); 1899 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1900 ios->vdd); 1901 if (ret) { 1902 dev_err(host->dev, "Failed to set vmmc power!\n"); 1903 return; 1904 } 1905 } 1906 break; 1907 case MMC_POWER_ON: 1908 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1909 ret = regulator_enable(mmc->supply.vqmmc); 1910 if (ret) 1911 dev_err(host->dev, "Failed to set vqmmc power!\n"); 1912 else 1913 host->vqmmc_enabled = true; 1914 } 1915 break; 1916 case MMC_POWER_OFF: 1917 if (!IS_ERR(mmc->supply.vmmc)) 1918 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1919 1920 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1921 regulator_disable(mmc->supply.vqmmc); 1922 host->vqmmc_enabled = false; 1923 } 1924 break; 1925 default: 1926 break; 1927 } 1928 1929 if (host->mclk != ios->clock || host->timing != ios->timing) 1930 msdc_set_mclk(host, ios->timing, ios->clock); 1931 } 1932 1933 static u32 test_delay_bit(u32 delay, u32 bit) 1934 { 1935 bit %= PAD_DELAY_MAX; 1936 return delay & BIT(bit); 1937 } 1938 1939 static int get_delay_len(u32 delay, u32 start_bit) 1940 { 1941 int i; 1942 1943 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 1944 if (test_delay_bit(delay, start_bit + i) == 0) 1945 return i; 1946 } 1947 return PAD_DELAY_MAX - start_bit; 1948 } 1949 1950 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 1951 { 1952 int start = 0, len = 0; 1953 int start_final = 0, len_final = 0; 1954 u8 final_phase = 0xff; 1955 struct msdc_delay_phase delay_phase = { 0, }; 1956 1957 if (delay == 0) { 1958 dev_err(host->dev, "phase error: [map:%x]\n", delay); 1959 delay_phase.final_phase = final_phase; 1960 return delay_phase; 1961 } 1962 1963 while (start < PAD_DELAY_MAX) { 1964 len = get_delay_len(delay, start); 1965 if (len_final < len) { 1966 start_final = start; 1967 len_final = len; 1968 } 1969 start += len ? len : 1; 1970 if (len >= 12 && start_final < 4) 1971 break; 1972 } 1973 1974 /* The rule is that to find the smallest delay cell */ 1975 if (start_final == 0) 1976 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 1977 else 1978 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 1979 dev_dbg(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 1980 delay, len_final, final_phase); 1981 1982 delay_phase.maxlen = len_final; 1983 delay_phase.start = start_final; 1984 delay_phase.final_phase = final_phase; 1985 return delay_phase; 1986 } 1987 1988 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) 1989 { 1990 u32 tune_reg = host->dev_comp->pad_tune_reg; 1991 1992 if (host->top_base) 1993 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, 1994 value); 1995 else 1996 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1997 value); 1998 } 1999 2000 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) 2001 { 2002 u32 tune_reg = host->dev_comp->pad_tune_reg; 2003 2004 if (host->top_base) 2005 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, 2006 PAD_DAT_RD_RXDLY, value); 2007 else 2008 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, 2009 value); 2010 } 2011 2012 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 2013 { 2014 struct msdc_host *host = mmc_priv(mmc); 2015 u32 rise_delay = 0, fall_delay = 0; 2016 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2017 struct msdc_delay_phase internal_delay_phase; 2018 u8 final_delay, final_maxlen; 2019 u32 internal_delay = 0; 2020 u32 tune_reg = host->dev_comp->pad_tune_reg; 2021 int cmd_err; 2022 int i, j; 2023 2024 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 2025 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 2026 sdr_set_field(host->base + tune_reg, 2027 MSDC_PAD_TUNE_CMDRRDLY, 2028 host->hs200_cmd_int_delay); 2029 2030 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2031 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2032 msdc_set_cmd_delay(host, i); 2033 /* 2034 * Using the same parameters, it may sometimes pass the test, 2035 * but sometimes it may fail. To make sure the parameters are 2036 * more stable, we test each set of parameters 3 times. 2037 */ 2038 for (j = 0; j < 3; j++) { 2039 mmc_send_tuning(mmc, opcode, &cmd_err); 2040 if (!cmd_err) { 2041 rise_delay |= BIT(i); 2042 } else { 2043 rise_delay &= ~BIT(i); 2044 break; 2045 } 2046 } 2047 } 2048 final_rise_delay = get_best_delay(host, rise_delay); 2049 /* if rising edge has enough margin, then do not scan falling edge */ 2050 if (final_rise_delay.maxlen >= 12 || 2051 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2052 goto skip_fall; 2053 2054 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2055 for (i = 0; i < PAD_DELAY_MAX; i++) { 2056 msdc_set_cmd_delay(host, i); 2057 /* 2058 * Using the same parameters, it may sometimes pass the test, 2059 * but sometimes it may fail. To make sure the parameters are 2060 * more stable, we test each set of parameters 3 times. 2061 */ 2062 for (j = 0; j < 3; j++) { 2063 mmc_send_tuning(mmc, opcode, &cmd_err); 2064 if (!cmd_err) { 2065 fall_delay |= BIT(i); 2066 } else { 2067 fall_delay &= ~BIT(i); 2068 break; 2069 } 2070 } 2071 } 2072 final_fall_delay = get_best_delay(host, fall_delay); 2073 2074 skip_fall: 2075 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2076 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 2077 final_maxlen = final_fall_delay.maxlen; 2078 if (final_maxlen == final_rise_delay.maxlen) { 2079 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2080 final_delay = final_rise_delay.final_phase; 2081 } else { 2082 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2083 final_delay = final_fall_delay.final_phase; 2084 } 2085 msdc_set_cmd_delay(host, final_delay); 2086 2087 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) 2088 goto skip_internal; 2089 2090 for (i = 0; i < PAD_DELAY_MAX; i++) { 2091 sdr_set_field(host->base + tune_reg, 2092 MSDC_PAD_TUNE_CMDRRDLY, i); 2093 mmc_send_tuning(mmc, opcode, &cmd_err); 2094 if (!cmd_err) 2095 internal_delay |= BIT(i); 2096 } 2097 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 2098 internal_delay_phase = get_best_delay(host, internal_delay); 2099 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 2100 internal_delay_phase.final_phase); 2101 skip_internal: 2102 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 2103 return final_delay == 0xff ? -EIO : 0; 2104 } 2105 2106 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 2107 { 2108 struct msdc_host *host = mmc_priv(mmc); 2109 u32 cmd_delay = 0; 2110 struct msdc_delay_phase final_cmd_delay = { 0,}; 2111 u8 final_delay; 2112 int cmd_err; 2113 int i, j; 2114 2115 /* select EMMC50 PAD CMD tune */ 2116 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 2117 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); 2118 2119 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 2120 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 2121 sdr_set_field(host->base + MSDC_PAD_TUNE, 2122 MSDC_PAD_TUNE_CMDRRDLY, 2123 host->hs200_cmd_int_delay); 2124 2125 if (host->hs400_cmd_resp_sel_rising) 2126 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2127 else 2128 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2129 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2130 sdr_set_field(host->base + PAD_CMD_TUNE, 2131 PAD_CMD_TUNE_RX_DLY3, i); 2132 /* 2133 * Using the same parameters, it may sometimes pass the test, 2134 * but sometimes it may fail. To make sure the parameters are 2135 * more stable, we test each set of parameters 3 times. 2136 */ 2137 for (j = 0; j < 3; j++) { 2138 mmc_send_tuning(mmc, opcode, &cmd_err); 2139 if (!cmd_err) { 2140 cmd_delay |= BIT(i); 2141 } else { 2142 cmd_delay &= ~BIT(i); 2143 break; 2144 } 2145 } 2146 } 2147 final_cmd_delay = get_best_delay(host, cmd_delay); 2148 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 2149 final_cmd_delay.final_phase); 2150 final_delay = final_cmd_delay.final_phase; 2151 2152 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 2153 return final_delay == 0xff ? -EIO : 0; 2154 } 2155 2156 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 2157 { 2158 struct msdc_host *host = mmc_priv(mmc); 2159 u32 rise_delay = 0, fall_delay = 0; 2160 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2161 u8 final_delay, final_maxlen; 2162 int i, ret; 2163 2164 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2165 host->latch_ck); 2166 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2167 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2168 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2169 msdc_set_data_delay(host, i); 2170 ret = mmc_send_tuning(mmc, opcode, NULL); 2171 if (!ret) 2172 rise_delay |= BIT(i); 2173 } 2174 final_rise_delay = get_best_delay(host, rise_delay); 2175 /* if rising edge has enough margin, then do not scan falling edge */ 2176 if (final_rise_delay.maxlen >= 12 || 2177 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2178 goto skip_fall; 2179 2180 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2181 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2182 for (i = 0; i < PAD_DELAY_MAX; i++) { 2183 msdc_set_data_delay(host, i); 2184 ret = mmc_send_tuning(mmc, opcode, NULL); 2185 if (!ret) 2186 fall_delay |= BIT(i); 2187 } 2188 final_fall_delay = get_best_delay(host, fall_delay); 2189 2190 skip_fall: 2191 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2192 if (final_maxlen == final_rise_delay.maxlen) { 2193 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2194 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2195 final_delay = final_rise_delay.final_phase; 2196 } else { 2197 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2198 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2199 final_delay = final_fall_delay.final_phase; 2200 } 2201 msdc_set_data_delay(host, final_delay); 2202 2203 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 2204 return final_delay == 0xff ? -EIO : 0; 2205 } 2206 2207 /* 2208 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune 2209 * together, which can save the tuning time. 2210 */ 2211 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode) 2212 { 2213 struct msdc_host *host = mmc_priv(mmc); 2214 u32 rise_delay = 0, fall_delay = 0; 2215 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2216 u8 final_delay, final_maxlen; 2217 int i, ret; 2218 2219 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2220 host->latch_ck); 2221 2222 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2223 sdr_clr_bits(host->base + MSDC_IOCON, 2224 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2225 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2226 msdc_set_cmd_delay(host, i); 2227 msdc_set_data_delay(host, i); 2228 ret = mmc_send_tuning(mmc, opcode, NULL); 2229 if (!ret) 2230 rise_delay |= BIT(i); 2231 } 2232 final_rise_delay = get_best_delay(host, rise_delay); 2233 /* if rising edge has enough margin, then do not scan falling edge */ 2234 if (final_rise_delay.maxlen >= 12 || 2235 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2236 goto skip_fall; 2237 2238 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2239 sdr_set_bits(host->base + MSDC_IOCON, 2240 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2241 for (i = 0; i < PAD_DELAY_MAX; i++) { 2242 msdc_set_cmd_delay(host, i); 2243 msdc_set_data_delay(host, i); 2244 ret = mmc_send_tuning(mmc, opcode, NULL); 2245 if (!ret) 2246 fall_delay |= BIT(i); 2247 } 2248 final_fall_delay = get_best_delay(host, fall_delay); 2249 2250 skip_fall: 2251 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2252 if (final_maxlen == final_rise_delay.maxlen) { 2253 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2254 sdr_clr_bits(host->base + MSDC_IOCON, 2255 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2256 final_delay = final_rise_delay.final_phase; 2257 } else { 2258 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2259 sdr_set_bits(host->base + MSDC_IOCON, 2260 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2261 final_delay = final_fall_delay.final_phase; 2262 } 2263 2264 msdc_set_cmd_delay(host, final_delay); 2265 msdc_set_data_delay(host, final_delay); 2266 2267 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); 2268 return final_delay == 0xff ? -EIO : 0; 2269 } 2270 2271 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 2272 { 2273 struct msdc_host *host = mmc_priv(mmc); 2274 int ret; 2275 u32 tune_reg = host->dev_comp->pad_tune_reg; 2276 2277 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { 2278 ret = msdc_tune_together(mmc, opcode); 2279 if (host->hs400_mode) { 2280 sdr_clr_bits(host->base + MSDC_IOCON, 2281 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2282 msdc_set_data_delay(host, 0); 2283 } 2284 goto tune_done; 2285 } 2286 if (host->hs400_mode && 2287 host->dev_comp->hs400_tune) 2288 ret = hs400_tune_response(mmc, opcode); 2289 else 2290 ret = msdc_tune_response(mmc, opcode); 2291 if (ret == -EIO) { 2292 dev_err(host->dev, "Tune response fail!\n"); 2293 return ret; 2294 } 2295 if (host->hs400_mode == false) { 2296 ret = msdc_tune_data(mmc, opcode); 2297 if (ret == -EIO) 2298 dev_err(host->dev, "Tune data fail!\n"); 2299 } 2300 2301 tune_done: 2302 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 2303 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 2304 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2305 if (host->top_base) { 2306 host->saved_tune_para.emmc_top_control = readl(host->top_base + 2307 EMMC_TOP_CONTROL); 2308 host->saved_tune_para.emmc_top_cmd = readl(host->top_base + 2309 EMMC_TOP_CMD); 2310 } 2311 return ret; 2312 } 2313 2314 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 2315 { 2316 struct msdc_host *host = mmc_priv(mmc); 2317 host->hs400_mode = true; 2318 2319 if (host->top_base) 2320 writel(host->hs400_ds_delay, 2321 host->top_base + EMMC50_PAD_DS_TUNE); 2322 else 2323 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 2324 /* hs400 mode must set it to 0 */ 2325 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); 2326 /* to improve read performance, set outstanding to 2 */ 2327 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); 2328 2329 return 0; 2330 } 2331 2332 static int msdc_execute_hs400_tuning(struct mmc_host *mmc, struct mmc_card *card) 2333 { 2334 struct msdc_host *host = mmc_priv(mmc); 2335 struct msdc_delay_phase dly1_delay; 2336 u32 val, result_dly1 = 0; 2337 u8 *ext_csd; 2338 int i, ret; 2339 2340 if (host->top_base) { 2341 sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE, 2342 PAD_DS_DLY_SEL); 2343 if (host->hs400_ds_dly3) 2344 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, 2345 PAD_DS_DLY3, host->hs400_ds_dly3); 2346 } else { 2347 sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL); 2348 if (host->hs400_ds_dly3) 2349 sdr_set_field(host->base + PAD_DS_TUNE, 2350 PAD_DS_TUNE_DLY3, host->hs400_ds_dly3); 2351 } 2352 2353 host->hs400_tuning = true; 2354 for (i = 0; i < PAD_DELAY_MAX; i++) { 2355 if (host->top_base) 2356 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, 2357 PAD_DS_DLY1, i); 2358 else 2359 sdr_set_field(host->base + PAD_DS_TUNE, 2360 PAD_DS_TUNE_DLY1, i); 2361 ret = mmc_get_ext_csd(card, &ext_csd); 2362 if (!ret) { 2363 result_dly1 |= BIT(i); 2364 kfree(ext_csd); 2365 } 2366 } 2367 host->hs400_tuning = false; 2368 2369 dly1_delay = get_best_delay(host, result_dly1); 2370 if (dly1_delay.maxlen == 0) { 2371 dev_err(host->dev, "Failed to get DLY1 delay!\n"); 2372 goto fail; 2373 } 2374 if (host->top_base) 2375 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, 2376 PAD_DS_DLY1, dly1_delay.final_phase); 2377 else 2378 sdr_set_field(host->base + PAD_DS_TUNE, 2379 PAD_DS_TUNE_DLY1, dly1_delay.final_phase); 2380 2381 if (host->top_base) 2382 val = readl(host->top_base + EMMC50_PAD_DS_TUNE); 2383 else 2384 val = readl(host->base + PAD_DS_TUNE); 2385 2386 dev_info(host->dev, "Final PAD_DS_TUNE: 0x%x\n", val); 2387 2388 return 0; 2389 2390 fail: 2391 dev_err(host->dev, "Failed to tuning DS pin delay!\n"); 2392 return -EIO; 2393 } 2394 2395 static void msdc_hw_reset(struct mmc_host *mmc) 2396 { 2397 struct msdc_host *host = mmc_priv(mmc); 2398 2399 sdr_set_bits(host->base + EMMC_IOCON, 1); 2400 udelay(10); /* 10us is enough */ 2401 sdr_clr_bits(host->base + EMMC_IOCON, 1); 2402 } 2403 2404 static void msdc_ack_sdio_irq(struct mmc_host *mmc) 2405 { 2406 unsigned long flags; 2407 struct msdc_host *host = mmc_priv(mmc); 2408 2409 spin_lock_irqsave(&host->lock, flags); 2410 __msdc_enable_sdio_irq(host, 1); 2411 spin_unlock_irqrestore(&host->lock, flags); 2412 } 2413 2414 static int msdc_get_cd(struct mmc_host *mmc) 2415 { 2416 struct msdc_host *host = mmc_priv(mmc); 2417 int val; 2418 2419 if (mmc->caps & MMC_CAP_NONREMOVABLE) 2420 return 1; 2421 2422 if (!host->internal_cd) 2423 return mmc_gpio_get_cd(mmc); 2424 2425 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; 2426 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) 2427 return !!val; 2428 else 2429 return !val; 2430 } 2431 2432 static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc, 2433 struct mmc_ios *ios) 2434 { 2435 struct msdc_host *host = mmc_priv(mmc); 2436 2437 if (ios->enhanced_strobe) { 2438 msdc_prepare_hs400_tuning(mmc, ios); 2439 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1); 2440 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1); 2441 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1); 2442 2443 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); 2444 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); 2445 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT); 2446 } else { 2447 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0); 2448 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0); 2449 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0); 2450 2451 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); 2452 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); 2453 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4); 2454 } 2455 } 2456 2457 static void msdc_cqe_enable(struct mmc_host *mmc) 2458 { 2459 struct msdc_host *host = mmc_priv(mmc); 2460 2461 /* enable cmdq irq */ 2462 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); 2463 /* enable busy check */ 2464 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 2465 /* default write data / busy timeout 20s */ 2466 msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); 2467 /* default read data timeout 1s */ 2468 msdc_set_timeout(host, 1000000000ULL, 0); 2469 } 2470 2471 static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) 2472 { 2473 struct msdc_host *host = mmc_priv(mmc); 2474 unsigned int val = 0; 2475 2476 /* disable cmdq irq */ 2477 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); 2478 /* disable busy check */ 2479 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 2480 2481 val = readl(host->base + MSDC_INT); 2482 writel(val, host->base + MSDC_INT); 2483 2484 if (recovery) { 2485 sdr_set_field(host->base + MSDC_DMA_CTRL, 2486 MSDC_DMA_CTRL_STOP, 1); 2487 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val, 2488 !(val & MSDC_DMA_CTRL_STOP), 1, 3000))) 2489 return; 2490 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val, 2491 !(val & MSDC_DMA_CFG_STS), 1, 3000))) 2492 return; 2493 msdc_reset_hw(host); 2494 } 2495 } 2496 2497 static void msdc_cqe_pre_enable(struct mmc_host *mmc) 2498 { 2499 struct cqhci_host *cq_host = mmc->cqe_private; 2500 u32 reg; 2501 2502 reg = cqhci_readl(cq_host, CQHCI_CFG); 2503 reg |= CQHCI_ENABLE; 2504 cqhci_writel(cq_host, reg, CQHCI_CFG); 2505 } 2506 2507 static void msdc_cqe_post_disable(struct mmc_host *mmc) 2508 { 2509 struct cqhci_host *cq_host = mmc->cqe_private; 2510 u32 reg; 2511 2512 reg = cqhci_readl(cq_host, CQHCI_CFG); 2513 reg &= ~CQHCI_ENABLE; 2514 cqhci_writel(cq_host, reg, CQHCI_CFG); 2515 } 2516 2517 static const struct mmc_host_ops mt_msdc_ops = { 2518 .post_req = msdc_post_req, 2519 .pre_req = msdc_pre_req, 2520 .request = msdc_ops_request, 2521 .set_ios = msdc_ops_set_ios, 2522 .get_ro = mmc_gpio_get_ro, 2523 .get_cd = msdc_get_cd, 2524 .hs400_enhanced_strobe = msdc_hs400_enhanced_strobe, 2525 .enable_sdio_irq = msdc_enable_sdio_irq, 2526 .ack_sdio_irq = msdc_ack_sdio_irq, 2527 .start_signal_voltage_switch = msdc_ops_switch_volt, 2528 .card_busy = msdc_card_busy, 2529 .execute_tuning = msdc_execute_tuning, 2530 .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 2531 .execute_hs400_tuning = msdc_execute_hs400_tuning, 2532 .card_hw_reset = msdc_hw_reset, 2533 }; 2534 2535 static const struct cqhci_host_ops msdc_cmdq_ops = { 2536 .enable = msdc_cqe_enable, 2537 .disable = msdc_cqe_disable, 2538 .pre_enable = msdc_cqe_pre_enable, 2539 .post_disable = msdc_cqe_post_disable, 2540 }; 2541 2542 static void msdc_of_property_parse(struct platform_device *pdev, 2543 struct msdc_host *host) 2544 { 2545 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", 2546 &host->latch_ck); 2547 2548 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 2549 &host->hs400_ds_delay); 2550 2551 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3", 2552 &host->hs400_ds_dly3); 2553 2554 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 2555 &host->hs200_cmd_int_delay); 2556 2557 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 2558 &host->hs400_cmd_int_delay); 2559 2560 if (of_property_read_bool(pdev->dev.of_node, 2561 "mediatek,hs400-cmd-resp-sel-rising")) 2562 host->hs400_cmd_resp_sel_rising = true; 2563 else 2564 host->hs400_cmd_resp_sel_rising = false; 2565 2566 if (of_property_read_bool(pdev->dev.of_node, 2567 "supports-cqe")) 2568 host->cqhci = true; 2569 else 2570 host->cqhci = false; 2571 } 2572 2573 static int msdc_of_clock_parse(struct platform_device *pdev, 2574 struct msdc_host *host) 2575 { 2576 int ret; 2577 2578 host->src_clk = devm_clk_get(&pdev->dev, "source"); 2579 if (IS_ERR(host->src_clk)) 2580 return PTR_ERR(host->src_clk); 2581 2582 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 2583 if (IS_ERR(host->h_clk)) 2584 return PTR_ERR(host->h_clk); 2585 2586 host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk"); 2587 if (IS_ERR(host->bus_clk)) 2588 host->bus_clk = NULL; 2589 2590 /*source clock control gate is optional clock*/ 2591 host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg"); 2592 if (IS_ERR(host->src_clk_cg)) 2593 return PTR_ERR(host->src_clk_cg); 2594 2595 /* 2596 * Fallback for legacy device-trees: src_clk and HCLK use the same 2597 * bit to control gating but they are parented to a different mux, 2598 * hence if our intention is to gate only the source, required 2599 * during a clk mode switch to avoid hw hangs, we need to gate 2600 * its parent (specified as a different clock only on new DTs). 2601 */ 2602 if (!host->src_clk_cg) { 2603 host->src_clk_cg = clk_get_parent(host->src_clk); 2604 if (IS_ERR(host->src_clk_cg)) 2605 return PTR_ERR(host->src_clk_cg); 2606 } 2607 2608 /* If present, always enable for this clock gate */ 2609 host->sys_clk_cg = devm_clk_get_optional_enabled(&pdev->dev, "sys_cg"); 2610 if (IS_ERR(host->sys_clk_cg)) 2611 host->sys_clk_cg = NULL; 2612 2613 host->bulk_clks[0].id = "pclk_cg"; 2614 host->bulk_clks[1].id = "axi_cg"; 2615 host->bulk_clks[2].id = "ahb_cg"; 2616 ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS, 2617 host->bulk_clks); 2618 if (ret) { 2619 dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n"); 2620 return ret; 2621 } 2622 2623 return 0; 2624 } 2625 2626 static int msdc_drv_probe(struct platform_device *pdev) 2627 { 2628 struct mmc_host *mmc; 2629 struct msdc_host *host; 2630 struct resource *res; 2631 int ret; 2632 2633 if (!pdev->dev.of_node) { 2634 dev_err(&pdev->dev, "No DT found\n"); 2635 return -EINVAL; 2636 } 2637 2638 /* Allocate MMC host for this device */ 2639 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 2640 if (!mmc) 2641 return -ENOMEM; 2642 2643 host = mmc_priv(mmc); 2644 ret = mmc_of_parse(mmc); 2645 if (ret) 2646 goto host_free; 2647 2648 host->base = devm_platform_ioremap_resource(pdev, 0); 2649 if (IS_ERR(host->base)) { 2650 ret = PTR_ERR(host->base); 2651 goto host_free; 2652 } 2653 2654 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2655 if (res) { 2656 host->top_base = devm_ioremap_resource(&pdev->dev, res); 2657 if (IS_ERR(host->top_base)) 2658 host->top_base = NULL; 2659 } 2660 2661 ret = mmc_regulator_get_supply(mmc); 2662 if (ret) 2663 goto host_free; 2664 2665 ret = msdc_of_clock_parse(pdev, host); 2666 if (ret) 2667 goto host_free; 2668 2669 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 2670 "hrst"); 2671 if (IS_ERR(host->reset)) { 2672 ret = PTR_ERR(host->reset); 2673 goto host_free; 2674 } 2675 2676 /* only eMMC has crypto property */ 2677 if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) { 2678 host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto"); 2679 if (IS_ERR(host->crypto_clk)) 2680 host->crypto_clk = NULL; 2681 else 2682 mmc->caps2 |= MMC_CAP2_CRYPTO; 2683 } 2684 2685 host->irq = platform_get_irq(pdev, 0); 2686 if (host->irq < 0) { 2687 ret = -EINVAL; 2688 goto host_free; 2689 } 2690 2691 host->pinctrl = devm_pinctrl_get(&pdev->dev); 2692 if (IS_ERR(host->pinctrl)) { 2693 ret = PTR_ERR(host->pinctrl); 2694 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 2695 goto host_free; 2696 } 2697 2698 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 2699 if (IS_ERR(host->pins_default)) { 2700 ret = PTR_ERR(host->pins_default); 2701 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 2702 goto host_free; 2703 } 2704 2705 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 2706 if (IS_ERR(host->pins_uhs)) { 2707 ret = PTR_ERR(host->pins_uhs); 2708 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 2709 goto host_free; 2710 } 2711 2712 /* Support for SDIO eint irq ? */ 2713 if ((mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) && (mmc->pm_caps & MMC_PM_KEEP_POWER)) { 2714 host->eint_irq = platform_get_irq_byname(pdev, "sdio_wakeup"); 2715 if (host->eint_irq > 0) { 2716 host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint"); 2717 if (IS_ERR(host->pins_eint)) { 2718 dev_err(&pdev->dev, "Cannot find pinctrl eint!\n"); 2719 host->pins_eint = NULL; 2720 } else { 2721 device_init_wakeup(&pdev->dev, true); 2722 } 2723 } 2724 } 2725 2726 msdc_of_property_parse(pdev, host); 2727 2728 host->dev = &pdev->dev; 2729 host->dev_comp = of_device_get_match_data(&pdev->dev); 2730 host->src_clk_freq = clk_get_rate(host->src_clk); 2731 /* Set host parameters to mmc */ 2732 mmc->ops = &mt_msdc_ops; 2733 if (host->dev_comp->clk_div_bits == 8) 2734 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 2735 else 2736 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); 2737 2738 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && 2739 !mmc_can_gpio_cd(mmc) && 2740 host->dev_comp->use_internal_cd) { 2741 /* 2742 * Is removable but no GPIO declared, so 2743 * use internal functionality. 2744 */ 2745 host->internal_cd = true; 2746 } 2747 2748 if (mmc->caps & MMC_CAP_SDIO_IRQ) 2749 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2750 2751 mmc->caps |= MMC_CAP_CMD23; 2752 if (host->cqhci) 2753 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 2754 /* MMC core transfer sizes tunable parameters */ 2755 mmc->max_segs = MAX_BD_NUM; 2756 if (host->dev_comp->support_64g) 2757 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; 2758 else 2759 mmc->max_seg_size = BDMA_DESC_BUFLEN; 2760 mmc->max_blk_size = 2048; 2761 mmc->max_req_size = 512 * 1024; 2762 mmc->max_blk_count = mmc->max_req_size / 512; 2763 if (host->dev_comp->support_64g) 2764 host->dma_mask = DMA_BIT_MASK(36); 2765 else 2766 host->dma_mask = DMA_BIT_MASK(32); 2767 mmc_dev(mmc)->dma_mask = &host->dma_mask; 2768 2769 host->timeout_clks = 3 * 1048576; 2770 host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2771 2 * sizeof(struct mt_gpdma_desc), 2772 &host->dma.gpd_addr, GFP_KERNEL); 2773 host->dma.bd = dma_alloc_coherent(&pdev->dev, 2774 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2775 &host->dma.bd_addr, GFP_KERNEL); 2776 if (!host->dma.gpd || !host->dma.bd) { 2777 ret = -ENOMEM; 2778 goto release_mem; 2779 } 2780 msdc_init_gpd_bd(host, &host->dma); 2781 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 2782 spin_lock_init(&host->lock); 2783 2784 platform_set_drvdata(pdev, mmc); 2785 ret = msdc_ungate_clock(host); 2786 if (ret) { 2787 dev_err(&pdev->dev, "Cannot ungate clocks!\n"); 2788 goto release_mem; 2789 } 2790 msdc_init_hw(host); 2791 2792 if (mmc->caps2 & MMC_CAP2_CQE) { 2793 host->cq_host = devm_kzalloc(mmc->parent, 2794 sizeof(*host->cq_host), 2795 GFP_KERNEL); 2796 if (!host->cq_host) { 2797 ret = -ENOMEM; 2798 goto host_free; 2799 } 2800 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 2801 host->cq_host->mmio = host->base + 0x800; 2802 host->cq_host->ops = &msdc_cmdq_ops; 2803 ret = cqhci_init(host->cq_host, mmc, true); 2804 if (ret) 2805 goto host_free; 2806 mmc->max_segs = 128; 2807 /* cqhci 16bit length */ 2808 /* 0 size, means 65536 so we don't have to -1 here */ 2809 mmc->max_seg_size = 64 * 1024; 2810 } 2811 2812 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 2813 IRQF_TRIGGER_NONE, pdev->name, host); 2814 if (ret) 2815 goto release; 2816 2817 pm_runtime_set_active(host->dev); 2818 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 2819 pm_runtime_use_autosuspend(host->dev); 2820 pm_runtime_enable(host->dev); 2821 ret = mmc_add_host(mmc); 2822 2823 if (ret) 2824 goto end; 2825 2826 return 0; 2827 end: 2828 pm_runtime_disable(host->dev); 2829 release: 2830 platform_set_drvdata(pdev, NULL); 2831 msdc_deinit_hw(host); 2832 msdc_gate_clock(host); 2833 release_mem: 2834 if (host->dma.gpd) 2835 dma_free_coherent(&pdev->dev, 2836 2 * sizeof(struct mt_gpdma_desc), 2837 host->dma.gpd, host->dma.gpd_addr); 2838 if (host->dma.bd) 2839 dma_free_coherent(&pdev->dev, 2840 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2841 host->dma.bd, host->dma.bd_addr); 2842 host_free: 2843 mmc_free_host(mmc); 2844 2845 return ret; 2846 } 2847 2848 static int msdc_drv_remove(struct platform_device *pdev) 2849 { 2850 struct mmc_host *mmc; 2851 struct msdc_host *host; 2852 2853 mmc = platform_get_drvdata(pdev); 2854 host = mmc_priv(mmc); 2855 2856 pm_runtime_get_sync(host->dev); 2857 2858 platform_set_drvdata(pdev, NULL); 2859 mmc_remove_host(mmc); 2860 msdc_deinit_hw(host); 2861 msdc_gate_clock(host); 2862 2863 pm_runtime_disable(host->dev); 2864 pm_runtime_put_noidle(host->dev); 2865 dma_free_coherent(&pdev->dev, 2866 2 * sizeof(struct mt_gpdma_desc), 2867 host->dma.gpd, host->dma.gpd_addr); 2868 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2869 host->dma.bd, host->dma.bd_addr); 2870 2871 mmc_free_host(mmc); 2872 2873 return 0; 2874 } 2875 2876 static void msdc_save_reg(struct msdc_host *host) 2877 { 2878 u32 tune_reg = host->dev_comp->pad_tune_reg; 2879 2880 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 2881 host->save_para.iocon = readl(host->base + MSDC_IOCON); 2882 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 2883 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 2884 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 2885 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); 2886 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 2887 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2888 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 2889 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); 2890 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); 2891 if (host->top_base) { 2892 host->save_para.emmc_top_control = 2893 readl(host->top_base + EMMC_TOP_CONTROL); 2894 host->save_para.emmc_top_cmd = 2895 readl(host->top_base + EMMC_TOP_CMD); 2896 host->save_para.emmc50_pad_ds_tune = 2897 readl(host->top_base + EMMC50_PAD_DS_TUNE); 2898 } else { 2899 host->save_para.pad_tune = readl(host->base + tune_reg); 2900 } 2901 } 2902 2903 static void msdc_restore_reg(struct msdc_host *host) 2904 { 2905 struct mmc_host *mmc = mmc_from_priv(host); 2906 u32 tune_reg = host->dev_comp->pad_tune_reg; 2907 2908 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 2909 writel(host->save_para.iocon, host->base + MSDC_IOCON); 2910 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 2911 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 2912 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 2913 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); 2914 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 2915 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 2916 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 2917 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); 2918 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); 2919 if (host->top_base) { 2920 writel(host->save_para.emmc_top_control, 2921 host->top_base + EMMC_TOP_CONTROL); 2922 writel(host->save_para.emmc_top_cmd, 2923 host->top_base + EMMC_TOP_CMD); 2924 writel(host->save_para.emmc50_pad_ds_tune, 2925 host->top_base + EMMC50_PAD_DS_TUNE); 2926 } else { 2927 writel(host->save_para.pad_tune, host->base + tune_reg); 2928 } 2929 2930 if (sdio_irq_claimed(mmc)) 2931 __msdc_enable_sdio_irq(host, 1); 2932 } 2933 2934 static int __maybe_unused msdc_runtime_suspend(struct device *dev) 2935 { 2936 struct mmc_host *mmc = dev_get_drvdata(dev); 2937 struct msdc_host *host = mmc_priv(mmc); 2938 2939 msdc_save_reg(host); 2940 2941 if (sdio_irq_claimed(mmc)) { 2942 if (host->pins_eint) { 2943 disable_irq(host->irq); 2944 pinctrl_select_state(host->pinctrl, host->pins_eint); 2945 } 2946 2947 __msdc_enable_sdio_irq(host, 0); 2948 } 2949 msdc_gate_clock(host); 2950 return 0; 2951 } 2952 2953 static int __maybe_unused msdc_runtime_resume(struct device *dev) 2954 { 2955 struct mmc_host *mmc = dev_get_drvdata(dev); 2956 struct msdc_host *host = mmc_priv(mmc); 2957 int ret; 2958 2959 ret = msdc_ungate_clock(host); 2960 if (ret) 2961 return ret; 2962 2963 msdc_restore_reg(host); 2964 2965 if (sdio_irq_claimed(mmc) && host->pins_eint) { 2966 pinctrl_select_state(host->pinctrl, host->pins_uhs); 2967 enable_irq(host->irq); 2968 } 2969 return 0; 2970 } 2971 2972 static int __maybe_unused msdc_suspend(struct device *dev) 2973 { 2974 struct mmc_host *mmc = dev_get_drvdata(dev); 2975 struct msdc_host *host = mmc_priv(mmc); 2976 int ret; 2977 u32 val; 2978 2979 if (mmc->caps2 & MMC_CAP2_CQE) { 2980 ret = cqhci_suspend(mmc); 2981 if (ret) 2982 return ret; 2983 val = readl(host->base + MSDC_INT); 2984 writel(val, host->base + MSDC_INT); 2985 } 2986 2987 /* 2988 * Bump up runtime PM usage counter otherwise dev->power.needs_force_resume will 2989 * not be marked as 1, pm_runtime_force_resume() will go out directly. 2990 */ 2991 if (sdio_irq_claimed(mmc) && host->pins_eint) 2992 pm_runtime_get_noresume(dev); 2993 2994 return pm_runtime_force_suspend(dev); 2995 } 2996 2997 static int __maybe_unused msdc_resume(struct device *dev) 2998 { 2999 struct mmc_host *mmc = dev_get_drvdata(dev); 3000 struct msdc_host *host = mmc_priv(mmc); 3001 3002 if (sdio_irq_claimed(mmc) && host->pins_eint) 3003 pm_runtime_put_noidle(dev); 3004 3005 return pm_runtime_force_resume(dev); 3006 } 3007 3008 static const struct dev_pm_ops msdc_dev_pm_ops = { 3009 SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume) 3010 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 3011 }; 3012 3013 static struct platform_driver mt_msdc_driver = { 3014 .probe = msdc_drv_probe, 3015 .remove = msdc_drv_remove, 3016 .driver = { 3017 .name = "mtk-msdc", 3018 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 3019 .of_match_table = msdc_of_ids, 3020 .pm = &msdc_dev_pm_ops, 3021 }, 3022 }; 3023 3024 module_platform_driver(mt_msdc_driver); 3025 MODULE_LICENSE("GPL v2"); 3026 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 3027