1 /* 2 * Copyright (c) 2014-2015 MediaTek Inc. 3 * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/ioport.h> 20 #include <linux/irq.h> 21 #include <linux/of_address.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_gpio.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/regulator/consumer.h> 29 #include <linux/spinlock.h> 30 31 #include <linux/mmc/card.h> 32 #include <linux/mmc/core.h> 33 #include <linux/mmc/host.h> 34 #include <linux/mmc/mmc.h> 35 #include <linux/mmc/sd.h> 36 #include <linux/mmc/sdio.h> 37 38 #define MAX_BD_NUM 1024 39 40 /*--------------------------------------------------------------------------*/ 41 /* Common Definition */ 42 /*--------------------------------------------------------------------------*/ 43 #define MSDC_BUS_1BITS 0x0 44 #define MSDC_BUS_4BITS 0x1 45 #define MSDC_BUS_8BITS 0x2 46 47 #define MSDC_BURST_64B 0x6 48 49 /*--------------------------------------------------------------------------*/ 50 /* Register Offset */ 51 /*--------------------------------------------------------------------------*/ 52 #define MSDC_CFG 0x0 53 #define MSDC_IOCON 0x04 54 #define MSDC_PS 0x08 55 #define MSDC_INT 0x0c 56 #define MSDC_INTEN 0x10 57 #define MSDC_FIFOCS 0x14 58 #define SDC_CFG 0x30 59 #define SDC_CMD 0x34 60 #define SDC_ARG 0x38 61 #define SDC_STS 0x3c 62 #define SDC_RESP0 0x40 63 #define SDC_RESP1 0x44 64 #define SDC_RESP2 0x48 65 #define SDC_RESP3 0x4c 66 #define SDC_BLK_NUM 0x50 67 #define SDC_ACMD_RESP 0x80 68 #define MSDC_DMA_SA 0x90 69 #define MSDC_DMA_CTRL 0x98 70 #define MSDC_DMA_CFG 0x9c 71 #define MSDC_PATCH_BIT 0xb0 72 #define MSDC_PATCH_BIT1 0xb4 73 #define MSDC_PAD_TUNE 0xec 74 75 /*--------------------------------------------------------------------------*/ 76 /* Register Mask */ 77 /*--------------------------------------------------------------------------*/ 78 79 /* MSDC_CFG mask */ 80 #define MSDC_CFG_MODE (0x1 << 0) /* RW */ 81 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ 82 #define MSDC_CFG_RST (0x1 << 2) /* RW */ 83 #define MSDC_CFG_PIO (0x1 << 3) /* RW */ 84 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ 85 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ 86 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ 87 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ 88 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ 89 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ 90 91 /* MSDC_IOCON mask */ 92 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ 93 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ 94 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ 95 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ 96 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ 97 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ 98 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ 99 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ 100 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ 101 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ 102 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ 103 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ 104 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ 105 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ 106 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ 107 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ 108 109 /* MSDC_PS mask */ 110 #define MSDC_PS_CDEN (0x1 << 0) /* RW */ 111 #define MSDC_PS_CDSTS (0x1 << 1) /* R */ 112 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ 113 #define MSDC_PS_DAT (0xff << 16) /* R */ 114 #define MSDC_PS_CMD (0x1 << 24) /* R */ 115 #define MSDC_PS_WP (0x1 << 31) /* R */ 116 117 /* MSDC_INT mask */ 118 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ 119 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ 120 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ 121 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ 122 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ 123 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ 124 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ 125 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ 126 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ 127 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ 128 #define MSDC_INT_CSTA (0x1 << 11) /* R */ 129 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ 130 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ 131 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ 132 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ 133 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ 134 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ 135 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ 136 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ 137 138 /* MSDC_INTEN mask */ 139 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ 140 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ 141 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ 142 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ 143 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ 144 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ 145 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ 146 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ 147 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ 148 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ 149 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ 150 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ 151 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ 152 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ 153 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ 154 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ 155 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ 156 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ 157 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ 158 159 /* MSDC_FIFOCS mask */ 160 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 161 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 162 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ 163 164 /* SDC_CFG mask */ 165 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ 166 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ 167 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 168 #define SDC_CFG_SDIO (0x1 << 19) /* RW */ 169 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 170 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ 171 #define SDC_CFG_DTOC (0xff << 24) /* RW */ 172 173 /* SDC_STS mask */ 174 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ 175 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 176 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ 177 178 /* MSDC_DMA_CTRL mask */ 179 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ 180 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ 181 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ 182 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ 183 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ 184 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ 185 186 /* MSDC_DMA_CFG mask */ 187 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ 188 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ 189 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ 190 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ 191 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ 192 193 /* MSDC_PATCH_BIT mask */ 194 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ 195 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) 196 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) 197 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ 198 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ 199 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ 200 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ 201 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ 202 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ 203 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ 204 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ 205 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ 206 207 #define REQ_CMD_EIO (0x1 << 0) 208 #define REQ_CMD_TMO (0x1 << 1) 209 #define REQ_DAT_ERR (0x1 << 2) 210 #define REQ_STOP_EIO (0x1 << 3) 211 #define REQ_STOP_TMO (0x1 << 4) 212 #define REQ_CMD_BUSY (0x1 << 5) 213 214 #define MSDC_PREPARE_FLAG (0x1 << 0) 215 #define MSDC_ASYNC_FLAG (0x1 << 1) 216 #define MSDC_MMAP_FLAG (0x1 << 2) 217 218 #define MTK_MMC_AUTOSUSPEND_DELAY 50 219 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 220 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 221 222 /*--------------------------------------------------------------------------*/ 223 /* Descriptor Structure */ 224 /*--------------------------------------------------------------------------*/ 225 struct mt_gpdma_desc { 226 u32 gpd_info; 227 #define GPDMA_DESC_HWO (0x1 << 0) 228 #define GPDMA_DESC_BDP (0x1 << 1) 229 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 230 #define GPDMA_DESC_INT (0x1 << 16) 231 u32 next; 232 u32 ptr; 233 u32 gpd_data_len; 234 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 235 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ 236 u32 arg; 237 u32 blknum; 238 u32 cmd; 239 }; 240 241 struct mt_bdma_desc { 242 u32 bd_info; 243 #define BDMA_DESC_EOL (0x1 << 0) 244 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 245 #define BDMA_DESC_BLKPAD (0x1 << 17) 246 #define BDMA_DESC_DWPAD (0x1 << 18) 247 u32 next; 248 u32 ptr; 249 u32 bd_data_len; 250 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 251 }; 252 253 struct msdc_dma { 254 struct scatterlist *sg; /* I/O scatter list */ 255 struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 256 struct mt_bdma_desc *bd; /* pointer to bd array */ 257 dma_addr_t gpd_addr; /* the physical address of gpd array */ 258 dma_addr_t bd_addr; /* the physical address of bd array */ 259 }; 260 261 struct msdc_save_para { 262 u32 msdc_cfg; 263 u32 iocon; 264 u32 sdc_cfg; 265 u32 pad_tune; 266 u32 patch_bit0; 267 u32 patch_bit1; 268 }; 269 270 struct msdc_host { 271 struct device *dev; 272 struct mmc_host *mmc; /* mmc structure */ 273 int cmd_rsp; 274 275 spinlock_t lock; 276 struct mmc_request *mrq; 277 struct mmc_command *cmd; 278 struct mmc_data *data; 279 int error; 280 281 void __iomem *base; /* host base address */ 282 283 struct msdc_dma dma; /* dma channel */ 284 u64 dma_mask; 285 286 u32 timeout_ns; /* data timeout ns */ 287 u32 timeout_clks; /* data timeout clks */ 288 289 struct pinctrl *pinctrl; 290 struct pinctrl_state *pins_default; 291 struct pinctrl_state *pins_uhs; 292 struct delayed_work req_timeout; 293 int irq; /* host interrupt */ 294 295 struct clk *src_clk; /* msdc source clock */ 296 struct clk *h_clk; /* msdc h_clk */ 297 u32 mclk; /* mmc subsystem clock frequency */ 298 u32 src_clk_freq; /* source clock frequency */ 299 u32 sclk; /* SD/MS bus clock frequency */ 300 unsigned char timing; 301 bool vqmmc_enabled; 302 struct msdc_save_para save_para; /* used when gate HCLK */ 303 }; 304 305 static void sdr_set_bits(void __iomem *reg, u32 bs) 306 { 307 u32 val = readl(reg); 308 309 val |= bs; 310 writel(val, reg); 311 } 312 313 static void sdr_clr_bits(void __iomem *reg, u32 bs) 314 { 315 u32 val = readl(reg); 316 317 val &= ~bs; 318 writel(val, reg); 319 } 320 321 static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 322 { 323 unsigned int tv = readl(reg); 324 325 tv &= ~field; 326 tv |= ((val) << (ffs((unsigned int)field) - 1)); 327 writel(tv, reg); 328 } 329 330 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 331 { 332 unsigned int tv = readl(reg); 333 334 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 335 } 336 337 static void msdc_reset_hw(struct msdc_host *host) 338 { 339 u32 val; 340 341 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 342 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) 343 cpu_relax(); 344 345 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 346 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) 347 cpu_relax(); 348 349 val = readl(host->base + MSDC_INT); 350 writel(val, host->base + MSDC_INT); 351 } 352 353 static void msdc_cmd_next(struct msdc_host *host, 354 struct mmc_request *mrq, struct mmc_command *cmd); 355 356 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 357 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 358 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 359 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 360 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 361 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 362 363 static u8 msdc_dma_calcs(u8 *buf, u32 len) 364 { 365 u32 i, sum = 0; 366 367 for (i = 0; i < len; i++) 368 sum += buf[i]; 369 return 0xff - (u8) sum; 370 } 371 372 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 373 struct mmc_data *data) 374 { 375 unsigned int j, dma_len; 376 dma_addr_t dma_address; 377 u32 dma_ctrl; 378 struct scatterlist *sg; 379 struct mt_gpdma_desc *gpd; 380 struct mt_bdma_desc *bd; 381 382 sg = data->sg; 383 384 gpd = dma->gpd; 385 bd = dma->bd; 386 387 /* modify gpd */ 388 gpd->gpd_info |= GPDMA_DESC_HWO; 389 gpd->gpd_info |= GPDMA_DESC_BDP; 390 /* need to clear first. use these bits to calc checksum */ 391 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 392 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 393 394 /* modify bd */ 395 for_each_sg(data->sg, sg, data->sg_count, j) { 396 dma_address = sg_dma_address(sg); 397 dma_len = sg_dma_len(sg); 398 399 /* init bd */ 400 bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 401 bd[j].bd_info &= ~BDMA_DESC_DWPAD; 402 bd[j].ptr = (u32)dma_address; 403 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 404 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 405 406 if (j == data->sg_count - 1) /* the last bd */ 407 bd[j].bd_info |= BDMA_DESC_EOL; 408 else 409 bd[j].bd_info &= ~BDMA_DESC_EOL; 410 411 /* checksume need to clear first */ 412 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 413 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 414 } 415 416 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 417 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 418 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 419 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); 420 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 421 writel((u32)dma->gpd_addr, host->base + MSDC_DMA_SA); 422 } 423 424 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq) 425 { 426 struct mmc_data *data = mrq->data; 427 428 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 429 bool read = (data->flags & MMC_DATA_READ) != 0; 430 431 data->host_cookie |= MSDC_PREPARE_FLAG; 432 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 433 read ? DMA_FROM_DEVICE : DMA_TO_DEVICE); 434 } 435 } 436 437 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) 438 { 439 struct mmc_data *data = mrq->data; 440 441 if (data->host_cookie & MSDC_ASYNC_FLAG) 442 return; 443 444 if (data->host_cookie & MSDC_PREPARE_FLAG) { 445 bool read = (data->flags & MMC_DATA_READ) != 0; 446 447 dma_unmap_sg(host->dev, data->sg, data->sg_len, 448 read ? DMA_FROM_DEVICE : DMA_TO_DEVICE); 449 data->host_cookie &= ~MSDC_PREPARE_FLAG; 450 } 451 } 452 453 /* clock control primitives */ 454 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) 455 { 456 u32 timeout, clk_ns; 457 u32 mode = 0; 458 459 host->timeout_ns = ns; 460 host->timeout_clks = clks; 461 if (host->sclk == 0) { 462 timeout = 0; 463 } else { 464 clk_ns = 1000000000UL / host->sclk; 465 timeout = (ns + clk_ns - 1) / clk_ns + clks; 466 /* in 1048576 sclk cycle unit */ 467 timeout = (timeout + (0x1 << 20) - 1) >> 20; 468 sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode); 469 /*DDR mode will double the clk cycles for data timeout */ 470 timeout = mode >= 2 ? timeout * 2 : timeout; 471 timeout = timeout > 1 ? timeout - 1 : 0; 472 timeout = timeout > 255 ? 255 : timeout; 473 } 474 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout); 475 } 476 477 static void msdc_gate_clock(struct msdc_host *host) 478 { 479 clk_disable_unprepare(host->src_clk); 480 clk_disable_unprepare(host->h_clk); 481 } 482 483 static void msdc_ungate_clock(struct msdc_host *host) 484 { 485 clk_prepare_enable(host->h_clk); 486 clk_prepare_enable(host->src_clk); 487 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 488 cpu_relax(); 489 } 490 491 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 492 { 493 u32 mode; 494 u32 flags; 495 u32 div; 496 u32 sclk; 497 498 if (!hz) { 499 dev_dbg(host->dev, "set mclk to 0\n"); 500 host->mclk = 0; 501 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 502 return; 503 } 504 505 flags = readl(host->base + MSDC_INTEN); 506 sdr_clr_bits(host->base + MSDC_INTEN, flags); 507 if (timing == MMC_TIMING_UHS_DDR50 || 508 timing == MMC_TIMING_MMC_DDR52) { 509 mode = 0x2; /* ddr mode and use divisor */ 510 if (hz >= (host->src_clk_freq >> 2)) { 511 div = 0; /* mean div = 1/4 */ 512 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 513 } else { 514 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 515 sclk = (host->src_clk_freq >> 2) / div; 516 div = (div >> 1); 517 } 518 } else if (hz >= host->src_clk_freq) { 519 mode = 0x1; /* no divisor */ 520 div = 0; 521 sclk = host->src_clk_freq; 522 } else { 523 mode = 0x0; /* use divisor */ 524 if (hz >= (host->src_clk_freq >> 1)) { 525 div = 0; /* mean div = 1/2 */ 526 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 527 } else { 528 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 529 sclk = (host->src_clk_freq >> 2) / div; 530 } 531 } 532 sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 533 (mode << 8) | (div % 0xff)); 534 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 535 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 536 cpu_relax(); 537 host->sclk = sclk; 538 host->mclk = hz; 539 host->timing = timing; 540 /* need because clk changed. */ 541 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 542 sdr_set_bits(host->base + MSDC_INTEN, flags); 543 544 dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->sclk, timing); 545 } 546 547 static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 548 struct mmc_request *mrq, struct mmc_command *cmd) 549 { 550 u32 resp; 551 552 switch (mmc_resp_type(cmd)) { 553 /* Actually, R1, R5, R6, R7 are the same */ 554 case MMC_RSP_R1: 555 resp = 0x1; 556 break; 557 case MMC_RSP_R1B: 558 resp = 0x7; 559 break; 560 case MMC_RSP_R2: 561 resp = 0x2; 562 break; 563 case MMC_RSP_R3: 564 resp = 0x3; 565 break; 566 case MMC_RSP_NONE: 567 default: 568 resp = 0x0; 569 break; 570 } 571 572 return resp; 573 } 574 575 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 576 struct mmc_request *mrq, struct mmc_command *cmd) 577 { 578 /* rawcmd : 579 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 580 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 581 */ 582 u32 opcode = cmd->opcode; 583 u32 resp = msdc_cmd_find_resp(host, mrq, cmd); 584 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 585 586 host->cmd_rsp = resp; 587 588 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 589 opcode == MMC_STOP_TRANSMISSION) 590 rawcmd |= (0x1 << 14); 591 else if (opcode == SD_SWITCH_VOLTAGE) 592 rawcmd |= (0x1 << 30); 593 else if (opcode == SD_APP_SEND_SCR || 594 opcode == SD_APP_SEND_NUM_WR_BLKS || 595 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 596 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 597 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 598 rawcmd |= (0x1 << 11); 599 600 if (cmd->data) { 601 struct mmc_data *data = cmd->data; 602 603 if (mmc_op_multi(opcode)) { 604 if (mmc_card_mmc(host->mmc->card) && mrq->sbc && 605 !(mrq->sbc->arg & 0xFFFF0000)) 606 rawcmd |= 0x2 << 28; /* AutoCMD23 */ 607 } 608 609 rawcmd |= ((data->blksz & 0xFFF) << 16); 610 if (data->flags & MMC_DATA_WRITE) 611 rawcmd |= (0x1 << 13); 612 if (data->blocks > 1) 613 rawcmd |= (0x2 << 11); 614 else 615 rawcmd |= (0x1 << 11); 616 /* Always use dma mode */ 617 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 618 619 if (host->timeout_ns != data->timeout_ns || 620 host->timeout_clks != data->timeout_clks) 621 msdc_set_timeout(host, data->timeout_ns, 622 data->timeout_clks); 623 624 writel(data->blocks, host->base + SDC_BLK_NUM); 625 } 626 return rawcmd; 627 } 628 629 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, 630 struct mmc_command *cmd, struct mmc_data *data) 631 { 632 bool read; 633 634 WARN_ON(host->data); 635 host->data = data; 636 read = data->flags & MMC_DATA_READ; 637 638 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 639 msdc_dma_setup(host, &host->dma, data); 640 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 641 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 642 dev_dbg(host->dev, "DMA start\n"); 643 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 644 __func__, cmd->opcode, data->blocks, read); 645 } 646 647 static int msdc_auto_cmd_done(struct msdc_host *host, int events, 648 struct mmc_command *cmd) 649 { 650 u32 *rsp = cmd->resp; 651 652 rsp[0] = readl(host->base + SDC_ACMD_RESP); 653 654 if (events & MSDC_INT_ACMDRDY) { 655 cmd->error = 0; 656 } else { 657 msdc_reset_hw(host); 658 if (events & MSDC_INT_ACMDCRCERR) { 659 cmd->error = -EILSEQ; 660 host->error |= REQ_STOP_EIO; 661 } else if (events & MSDC_INT_ACMDTMO) { 662 cmd->error = -ETIMEDOUT; 663 host->error |= REQ_STOP_TMO; 664 } 665 dev_err(host->dev, 666 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 667 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 668 } 669 return cmd->error; 670 } 671 672 static void msdc_track_cmd_data(struct msdc_host *host, 673 struct mmc_command *cmd, struct mmc_data *data) 674 { 675 if (host->error) 676 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 677 __func__, cmd->opcode, cmd->arg, host->error); 678 } 679 680 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 681 { 682 unsigned long flags; 683 bool ret; 684 685 ret = cancel_delayed_work(&host->req_timeout); 686 if (!ret) { 687 /* delay work already running */ 688 return; 689 } 690 spin_lock_irqsave(&host->lock, flags); 691 host->mrq = NULL; 692 spin_unlock_irqrestore(&host->lock, flags); 693 694 msdc_track_cmd_data(host, mrq->cmd, mrq->data); 695 if (mrq->data) 696 msdc_unprepare_data(host, mrq); 697 mmc_request_done(host->mmc, mrq); 698 699 pm_runtime_mark_last_busy(host->dev); 700 pm_runtime_put_autosuspend(host->dev); 701 } 702 703 /* returns true if command is fully handled; returns false otherwise */ 704 static bool msdc_cmd_done(struct msdc_host *host, int events, 705 struct mmc_request *mrq, struct mmc_command *cmd) 706 { 707 bool done = false; 708 bool sbc_error; 709 unsigned long flags; 710 u32 *rsp = cmd->resp; 711 712 if (mrq->sbc && cmd == mrq->cmd && 713 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 714 | MSDC_INT_ACMDTMO))) 715 msdc_auto_cmd_done(host, events, mrq->sbc); 716 717 sbc_error = mrq->sbc && mrq->sbc->error; 718 719 if (!sbc_error && !(events & (MSDC_INT_CMDRDY 720 | MSDC_INT_RSPCRCERR 721 | MSDC_INT_CMDTMO))) 722 return done; 723 724 spin_lock_irqsave(&host->lock, flags); 725 done = !host->cmd; 726 host->cmd = NULL; 727 spin_unlock_irqrestore(&host->lock, flags); 728 729 if (done) 730 return true; 731 732 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 733 734 if (cmd->flags & MMC_RSP_PRESENT) { 735 if (cmd->flags & MMC_RSP_136) { 736 rsp[0] = readl(host->base + SDC_RESP3); 737 rsp[1] = readl(host->base + SDC_RESP2); 738 rsp[2] = readl(host->base + SDC_RESP1); 739 rsp[3] = readl(host->base + SDC_RESP0); 740 } else { 741 rsp[0] = readl(host->base + SDC_RESP0); 742 } 743 } 744 745 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 746 msdc_reset_hw(host); 747 if (events & MSDC_INT_RSPCRCERR) { 748 cmd->error = -EILSEQ; 749 host->error |= REQ_CMD_EIO; 750 } else if (events & MSDC_INT_CMDTMO) { 751 cmd->error = -ETIMEDOUT; 752 host->error |= REQ_CMD_TMO; 753 } 754 } 755 if (cmd->error) 756 dev_dbg(host->dev, 757 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 758 __func__, cmd->opcode, cmd->arg, rsp[0], 759 cmd->error); 760 761 msdc_cmd_next(host, mrq, cmd); 762 return true; 763 } 764 765 /* It is the core layer's responsibility to ensure card status 766 * is correct before issue a request. but host design do below 767 * checks recommended. 768 */ 769 static inline bool msdc_cmd_is_ready(struct msdc_host *host, 770 struct mmc_request *mrq, struct mmc_command *cmd) 771 { 772 /* The max busy time we can endure is 20ms */ 773 unsigned long tmo = jiffies + msecs_to_jiffies(20); 774 775 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && 776 time_before(jiffies, tmo)) 777 cpu_relax(); 778 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { 779 dev_err(host->dev, "CMD bus busy detected\n"); 780 host->error |= REQ_CMD_BUSY; 781 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 782 return false; 783 } 784 785 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 786 tmo = jiffies + msecs_to_jiffies(20); 787 /* R1B or with data, should check SDCBUSY */ 788 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && 789 time_before(jiffies, tmo)) 790 cpu_relax(); 791 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { 792 dev_err(host->dev, "Controller busy detected\n"); 793 host->error |= REQ_CMD_BUSY; 794 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 795 return false; 796 } 797 } 798 return true; 799 } 800 801 static void msdc_start_command(struct msdc_host *host, 802 struct mmc_request *mrq, struct mmc_command *cmd) 803 { 804 u32 rawcmd; 805 806 WARN_ON(host->cmd); 807 host->cmd = cmd; 808 809 if (!msdc_cmd_is_ready(host, mrq, cmd)) 810 return; 811 812 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 813 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 814 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 815 msdc_reset_hw(host); 816 } 817 818 cmd->error = 0; 819 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 820 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 821 822 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 823 writel(cmd->arg, host->base + SDC_ARG); 824 writel(rawcmd, host->base + SDC_CMD); 825 } 826 827 static void msdc_cmd_next(struct msdc_host *host, 828 struct mmc_request *mrq, struct mmc_command *cmd) 829 { 830 if (cmd->error || (mrq->sbc && mrq->sbc->error)) 831 msdc_request_done(host, mrq); 832 else if (cmd == mrq->sbc) 833 msdc_start_command(host, mrq, mrq->cmd); 834 else if (!cmd->data) 835 msdc_request_done(host, mrq); 836 else 837 msdc_start_data(host, mrq, cmd, cmd->data); 838 } 839 840 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 841 { 842 struct msdc_host *host = mmc_priv(mmc); 843 844 host->error = 0; 845 WARN_ON(host->mrq); 846 host->mrq = mrq; 847 848 pm_runtime_get_sync(host->dev); 849 850 if (mrq->data) 851 msdc_prepare_data(host, mrq); 852 853 /* if SBC is required, we have HW option and SW option. 854 * if HW option is enabled, and SBC does not have "special" flags, 855 * use HW option, otherwise use SW option 856 */ 857 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 858 (mrq->sbc->arg & 0xFFFF0000))) 859 msdc_start_command(host, mrq, mrq->sbc); 860 else 861 msdc_start_command(host, mrq, mrq->cmd); 862 } 863 864 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 865 bool is_first_req) 866 { 867 struct msdc_host *host = mmc_priv(mmc); 868 struct mmc_data *data = mrq->data; 869 870 if (!data) 871 return; 872 873 msdc_prepare_data(host, mrq); 874 data->host_cookie |= MSDC_ASYNC_FLAG; 875 } 876 877 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 878 int err) 879 { 880 struct msdc_host *host = mmc_priv(mmc); 881 struct mmc_data *data; 882 883 data = mrq->data; 884 if (!data) 885 return; 886 if (data->host_cookie) { 887 data->host_cookie &= ~MSDC_ASYNC_FLAG; 888 msdc_unprepare_data(host, mrq); 889 } 890 } 891 892 static void msdc_data_xfer_next(struct msdc_host *host, 893 struct mmc_request *mrq, struct mmc_data *data) 894 { 895 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 896 (!data->bytes_xfered || !mrq->sbc)) 897 msdc_start_command(host, mrq, mrq->stop); 898 else 899 msdc_request_done(host, mrq); 900 } 901 902 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 903 struct mmc_request *mrq, struct mmc_data *data) 904 { 905 struct mmc_command *stop = data->stop; 906 unsigned long flags; 907 bool done; 908 unsigned int check_data = events & 909 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 910 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 911 | MSDC_INT_DMA_PROTECT); 912 913 spin_lock_irqsave(&host->lock, flags); 914 done = !host->data; 915 if (check_data) 916 host->data = NULL; 917 spin_unlock_irqrestore(&host->lock, flags); 918 919 if (done) 920 return true; 921 922 if (check_data || (stop && stop->error)) { 923 dev_dbg(host->dev, "DMA status: 0x%8X\n", 924 readl(host->base + MSDC_DMA_CFG)); 925 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 926 1); 927 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) 928 cpu_relax(); 929 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 930 dev_dbg(host->dev, "DMA stop\n"); 931 932 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 933 data->bytes_xfered = data->blocks * data->blksz; 934 } else { 935 dev_err(host->dev, "interrupt events: %x\n", events); 936 msdc_reset_hw(host); 937 host->error |= REQ_DAT_ERR; 938 data->bytes_xfered = 0; 939 940 if (events & MSDC_INT_DATTMO) 941 data->error = -ETIMEDOUT; 942 943 dev_err(host->dev, "%s: cmd=%d; blocks=%d", 944 __func__, mrq->cmd->opcode, data->blocks); 945 dev_err(host->dev, "data_error=%d xfer_size=%d\n", 946 (int)data->error, data->bytes_xfered); 947 } 948 949 msdc_data_xfer_next(host, mrq, data); 950 done = true; 951 } 952 return done; 953 } 954 955 static void msdc_set_buswidth(struct msdc_host *host, u32 width) 956 { 957 u32 val = readl(host->base + SDC_CFG); 958 959 val &= ~SDC_CFG_BUSWIDTH; 960 961 switch (width) { 962 default: 963 case MMC_BUS_WIDTH_1: 964 val |= (MSDC_BUS_1BITS << 16); 965 break; 966 case MMC_BUS_WIDTH_4: 967 val |= (MSDC_BUS_4BITS << 16); 968 break; 969 case MMC_BUS_WIDTH_8: 970 val |= (MSDC_BUS_8BITS << 16); 971 break; 972 } 973 974 writel(val, host->base + SDC_CFG); 975 dev_dbg(host->dev, "Bus Width = %d", width); 976 } 977 978 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 979 { 980 struct msdc_host *host = mmc_priv(mmc); 981 int min_uv, max_uv; 982 int ret = 0; 983 984 if (!IS_ERR(mmc->supply.vqmmc)) { 985 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 986 min_uv = 3300000; 987 max_uv = 3300000; 988 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 989 min_uv = 1800000; 990 max_uv = 1800000; 991 } else { 992 dev_err(host->dev, "Unsupported signal voltage!\n"); 993 return -EINVAL; 994 } 995 996 ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv); 997 if (ret) { 998 dev_err(host->dev, 999 "Regulator set error %d: %d - %d\n", 1000 ret, min_uv, max_uv); 1001 } else { 1002 /* Apply different pinctrl settings for different signal voltage */ 1003 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 1004 pinctrl_select_state(host->pinctrl, host->pins_uhs); 1005 else 1006 pinctrl_select_state(host->pinctrl, host->pins_default); 1007 } 1008 } 1009 return ret; 1010 } 1011 1012 static int msdc_card_busy(struct mmc_host *mmc) 1013 { 1014 struct msdc_host *host = mmc_priv(mmc); 1015 u32 status = readl(host->base + MSDC_PS); 1016 1017 /* check if any pin between dat[0:3] is low */ 1018 if (((status >> 16) & 0xf) != 0xf) 1019 return 1; 1020 1021 return 0; 1022 } 1023 1024 static void msdc_request_timeout(struct work_struct *work) 1025 { 1026 struct msdc_host *host = container_of(work, struct msdc_host, 1027 req_timeout.work); 1028 1029 /* simulate HW timeout status */ 1030 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 1031 if (host->mrq) { 1032 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 1033 host->mrq, host->mrq->cmd->opcode); 1034 if (host->cmd) { 1035 dev_err(host->dev, "%s: aborting cmd=%d\n", 1036 __func__, host->cmd->opcode); 1037 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 1038 host->cmd); 1039 } else if (host->data) { 1040 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 1041 __func__, host->mrq->cmd->opcode, 1042 host->data->blocks); 1043 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 1044 host->data); 1045 } 1046 } 1047 } 1048 1049 static irqreturn_t msdc_irq(int irq, void *dev_id) 1050 { 1051 struct msdc_host *host = (struct msdc_host *) dev_id; 1052 1053 while (true) { 1054 unsigned long flags; 1055 struct mmc_request *mrq; 1056 struct mmc_command *cmd; 1057 struct mmc_data *data; 1058 u32 events, event_mask; 1059 1060 spin_lock_irqsave(&host->lock, flags); 1061 events = readl(host->base + MSDC_INT); 1062 event_mask = readl(host->base + MSDC_INTEN); 1063 /* clear interrupts */ 1064 writel(events & event_mask, host->base + MSDC_INT); 1065 1066 mrq = host->mrq; 1067 cmd = host->cmd; 1068 data = host->data; 1069 spin_unlock_irqrestore(&host->lock, flags); 1070 1071 if (!(events & event_mask)) 1072 break; 1073 1074 if (!mrq) { 1075 dev_err(host->dev, 1076 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 1077 __func__, events, event_mask); 1078 WARN_ON(1); 1079 break; 1080 } 1081 1082 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 1083 1084 if (cmd) 1085 msdc_cmd_done(host, events, mrq, cmd); 1086 else if (data) 1087 msdc_data_xfer_done(host, events, mrq, data); 1088 } 1089 1090 return IRQ_HANDLED; 1091 } 1092 1093 static void msdc_init_hw(struct msdc_host *host) 1094 { 1095 u32 val; 1096 1097 /* Configure to MMC/SD mode, clock free running */ 1098 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 1099 1100 /* Reset */ 1101 msdc_reset_hw(host); 1102 1103 /* Disable card detection */ 1104 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1105 1106 /* Disable and clear all interrupts */ 1107 writel(0, host->base + MSDC_INTEN); 1108 val = readl(host->base + MSDC_INT); 1109 writel(val, host->base + MSDC_INT); 1110 1111 writel(0, host->base + MSDC_PAD_TUNE); 1112 writel(0, host->base + MSDC_IOCON); 1113 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 1); 1114 writel(0x403c004f, host->base + MSDC_PATCH_BIT); 1115 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 1116 writel(0xffff0089, host->base + MSDC_PATCH_BIT1); 1117 /* Configure to enable SDIO mode. 1118 * it's must otherwise sdio cmd5 failed 1119 */ 1120 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1121 1122 /* disable detect SDIO device interrupt function */ 1123 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1124 1125 /* Configure to default data timeout */ 1126 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 1127 1128 dev_dbg(host->dev, "init hardware done!"); 1129 } 1130 1131 static void msdc_deinit_hw(struct msdc_host *host) 1132 { 1133 u32 val; 1134 /* Disable and clear all interrupts */ 1135 writel(0, host->base + MSDC_INTEN); 1136 1137 val = readl(host->base + MSDC_INT); 1138 writel(val, host->base + MSDC_INT); 1139 } 1140 1141 /* init gpd and bd list in msdc_drv_probe */ 1142 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 1143 { 1144 struct mt_gpdma_desc *gpd = dma->gpd; 1145 struct mt_bdma_desc *bd = dma->bd; 1146 int i; 1147 1148 memset(gpd, 0, sizeof(struct mt_gpdma_desc)); 1149 1150 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 1151 gpd->ptr = (u32)dma->bd_addr; /* physical address */ 1152 1153 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 1154 for (i = 0; i < (MAX_BD_NUM - 1); i++) 1155 bd[i].next = (u32)dma->bd_addr + sizeof(*bd) * (i + 1); 1156 } 1157 1158 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1159 { 1160 struct msdc_host *host = mmc_priv(mmc); 1161 int ret; 1162 1163 pm_runtime_get_sync(host->dev); 1164 1165 msdc_set_buswidth(host, ios->bus_width); 1166 1167 /* Suspend/Resume will do power off/on */ 1168 switch (ios->power_mode) { 1169 case MMC_POWER_UP: 1170 if (!IS_ERR(mmc->supply.vmmc)) { 1171 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1172 ios->vdd); 1173 if (ret) { 1174 dev_err(host->dev, "Failed to set vmmc power!\n"); 1175 goto end; 1176 } 1177 } 1178 break; 1179 case MMC_POWER_ON: 1180 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1181 ret = regulator_enable(mmc->supply.vqmmc); 1182 if (ret) 1183 dev_err(host->dev, "Failed to set vqmmc power!\n"); 1184 else 1185 host->vqmmc_enabled = true; 1186 } 1187 break; 1188 case MMC_POWER_OFF: 1189 if (!IS_ERR(mmc->supply.vmmc)) 1190 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1191 1192 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1193 regulator_disable(mmc->supply.vqmmc); 1194 host->vqmmc_enabled = false; 1195 } 1196 break; 1197 default: 1198 break; 1199 } 1200 1201 if (host->mclk != ios->clock || host->timing != ios->timing) 1202 msdc_set_mclk(host, ios->timing, ios->clock); 1203 1204 end: 1205 pm_runtime_mark_last_busy(host->dev); 1206 pm_runtime_put_autosuspend(host->dev); 1207 } 1208 1209 static struct mmc_host_ops mt_msdc_ops = { 1210 .post_req = msdc_post_req, 1211 .pre_req = msdc_pre_req, 1212 .request = msdc_ops_request, 1213 .set_ios = msdc_ops_set_ios, 1214 .start_signal_voltage_switch = msdc_ops_switch_volt, 1215 .card_busy = msdc_card_busy, 1216 }; 1217 1218 static int msdc_drv_probe(struct platform_device *pdev) 1219 { 1220 struct mmc_host *mmc; 1221 struct msdc_host *host; 1222 struct resource *res; 1223 int ret; 1224 1225 if (!pdev->dev.of_node) { 1226 dev_err(&pdev->dev, "No DT found\n"); 1227 return -EINVAL; 1228 } 1229 /* Allocate MMC host for this device */ 1230 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 1231 if (!mmc) 1232 return -ENOMEM; 1233 1234 host = mmc_priv(mmc); 1235 ret = mmc_of_parse(mmc); 1236 if (ret) 1237 goto host_free; 1238 1239 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1240 host->base = devm_ioremap_resource(&pdev->dev, res); 1241 if (IS_ERR(host->base)) { 1242 ret = PTR_ERR(host->base); 1243 goto host_free; 1244 } 1245 1246 ret = mmc_regulator_get_supply(mmc); 1247 if (ret == -EPROBE_DEFER) 1248 goto host_free; 1249 1250 host->src_clk = devm_clk_get(&pdev->dev, "source"); 1251 if (IS_ERR(host->src_clk)) { 1252 ret = PTR_ERR(host->src_clk); 1253 goto host_free; 1254 } 1255 1256 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 1257 if (IS_ERR(host->h_clk)) { 1258 ret = PTR_ERR(host->h_clk); 1259 goto host_free; 1260 } 1261 1262 host->irq = platform_get_irq(pdev, 0); 1263 if (host->irq < 0) { 1264 ret = -EINVAL; 1265 goto host_free; 1266 } 1267 1268 host->pinctrl = devm_pinctrl_get(&pdev->dev); 1269 if (IS_ERR(host->pinctrl)) { 1270 ret = PTR_ERR(host->pinctrl); 1271 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 1272 goto host_free; 1273 } 1274 1275 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 1276 if (IS_ERR(host->pins_default)) { 1277 ret = PTR_ERR(host->pins_default); 1278 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 1279 goto host_free; 1280 } 1281 1282 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 1283 if (IS_ERR(host->pins_uhs)) { 1284 ret = PTR_ERR(host->pins_uhs); 1285 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 1286 goto host_free; 1287 } 1288 1289 host->dev = &pdev->dev; 1290 host->mmc = mmc; 1291 host->src_clk_freq = clk_get_rate(host->src_clk); 1292 /* Set host parameters to mmc */ 1293 mmc->ops = &mt_msdc_ops; 1294 mmc->f_min = host->src_clk_freq / (4 * 255); 1295 1296 mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; 1297 mmc->caps |= MMC_CAP_RUNTIME_RESUME; 1298 /* MMC core transfer sizes tunable parameters */ 1299 mmc->max_segs = MAX_BD_NUM; 1300 mmc->max_seg_size = BDMA_DESC_BUFLEN; 1301 mmc->max_blk_size = 2048; 1302 mmc->max_req_size = 512 * 1024; 1303 mmc->max_blk_count = mmc->max_req_size / 512; 1304 host->dma_mask = DMA_BIT_MASK(32); 1305 mmc_dev(mmc)->dma_mask = &host->dma_mask; 1306 1307 host->timeout_clks = 3 * 1048576; 1308 host->dma.gpd = dma_alloc_coherent(&pdev->dev, 1309 sizeof(struct mt_gpdma_desc), 1310 &host->dma.gpd_addr, GFP_KERNEL); 1311 host->dma.bd = dma_alloc_coherent(&pdev->dev, 1312 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 1313 &host->dma.bd_addr, GFP_KERNEL); 1314 if (!host->dma.gpd || !host->dma.bd) { 1315 ret = -ENOMEM; 1316 goto release_mem; 1317 } 1318 msdc_init_gpd_bd(host, &host->dma); 1319 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 1320 spin_lock_init(&host->lock); 1321 1322 platform_set_drvdata(pdev, mmc); 1323 msdc_ungate_clock(host); 1324 msdc_init_hw(host); 1325 1326 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 1327 IRQF_TRIGGER_LOW | IRQF_ONESHOT, pdev->name, host); 1328 if (ret) 1329 goto release; 1330 1331 pm_runtime_set_active(host->dev); 1332 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 1333 pm_runtime_use_autosuspend(host->dev); 1334 pm_runtime_enable(host->dev); 1335 ret = mmc_add_host(mmc); 1336 1337 if (ret) 1338 goto end; 1339 1340 return 0; 1341 end: 1342 pm_runtime_disable(host->dev); 1343 release: 1344 platform_set_drvdata(pdev, NULL); 1345 msdc_deinit_hw(host); 1346 msdc_gate_clock(host); 1347 release_mem: 1348 if (host->dma.gpd) 1349 dma_free_coherent(&pdev->dev, 1350 sizeof(struct mt_gpdma_desc), 1351 host->dma.gpd, host->dma.gpd_addr); 1352 if (host->dma.bd) 1353 dma_free_coherent(&pdev->dev, 1354 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 1355 host->dma.bd, host->dma.bd_addr); 1356 host_free: 1357 mmc_free_host(mmc); 1358 1359 return ret; 1360 } 1361 1362 static int msdc_drv_remove(struct platform_device *pdev) 1363 { 1364 struct mmc_host *mmc; 1365 struct msdc_host *host; 1366 1367 mmc = platform_get_drvdata(pdev); 1368 host = mmc_priv(mmc); 1369 1370 pm_runtime_get_sync(host->dev); 1371 1372 platform_set_drvdata(pdev, NULL); 1373 mmc_remove_host(host->mmc); 1374 msdc_deinit_hw(host); 1375 msdc_gate_clock(host); 1376 1377 pm_runtime_disable(host->dev); 1378 pm_runtime_put_noidle(host->dev); 1379 dma_free_coherent(&pdev->dev, 1380 sizeof(struct mt_gpdma_desc), 1381 host->dma.gpd, host->dma.gpd_addr); 1382 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 1383 host->dma.bd, host->dma.bd_addr); 1384 1385 mmc_free_host(host->mmc); 1386 1387 return 0; 1388 } 1389 1390 #ifdef CONFIG_PM 1391 static void msdc_save_reg(struct msdc_host *host) 1392 { 1393 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 1394 host->save_para.iocon = readl(host->base + MSDC_IOCON); 1395 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 1396 host->save_para.pad_tune = readl(host->base + MSDC_PAD_TUNE); 1397 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 1398 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 1399 } 1400 1401 static void msdc_restore_reg(struct msdc_host *host) 1402 { 1403 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 1404 writel(host->save_para.iocon, host->base + MSDC_IOCON); 1405 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 1406 writel(host->save_para.pad_tune, host->base + MSDC_PAD_TUNE); 1407 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 1408 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 1409 } 1410 1411 static int msdc_runtime_suspend(struct device *dev) 1412 { 1413 struct mmc_host *mmc = dev_get_drvdata(dev); 1414 struct msdc_host *host = mmc_priv(mmc); 1415 1416 msdc_save_reg(host); 1417 msdc_gate_clock(host); 1418 return 0; 1419 } 1420 1421 static int msdc_runtime_resume(struct device *dev) 1422 { 1423 struct mmc_host *mmc = dev_get_drvdata(dev); 1424 struct msdc_host *host = mmc_priv(mmc); 1425 1426 msdc_ungate_clock(host); 1427 msdc_restore_reg(host); 1428 return 0; 1429 } 1430 #endif 1431 1432 static const struct dev_pm_ops msdc_dev_pm_ops = { 1433 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1434 pm_runtime_force_resume) 1435 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 1436 }; 1437 1438 static const struct of_device_id msdc_of_ids[] = { 1439 { .compatible = "mediatek,mt8135-mmc", }, 1440 {} 1441 }; 1442 1443 static struct platform_driver mt_msdc_driver = { 1444 .probe = msdc_drv_probe, 1445 .remove = msdc_drv_remove, 1446 .driver = { 1447 .name = "mtk-msdc", 1448 .of_match_table = msdc_of_ids, 1449 .pm = &msdc_dev_pm_ops, 1450 }, 1451 }; 1452 1453 module_platform_driver(mt_msdc_driver); 1454 MODULE_LICENSE("GPL v2"); 1455 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 1456