1 /* 2 * Copyright (c) 2014-2015 MediaTek Inc. 3 * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/ioport.h> 20 #include <linux/irq.h> 21 #include <linux/of_address.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_gpio.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/regulator/consumer.h> 29 #include <linux/slab.h> 30 #include <linux/spinlock.h> 31 #include <linux/interrupt.h> 32 33 #include <linux/mmc/card.h> 34 #include <linux/mmc/core.h> 35 #include <linux/mmc/host.h> 36 #include <linux/mmc/mmc.h> 37 #include <linux/mmc/sd.h> 38 #include <linux/mmc/sdio.h> 39 #include <linux/mmc/slot-gpio.h> 40 41 #define MAX_BD_NUM 1024 42 43 /*--------------------------------------------------------------------------*/ 44 /* Common Definition */ 45 /*--------------------------------------------------------------------------*/ 46 #define MSDC_BUS_1BITS 0x0 47 #define MSDC_BUS_4BITS 0x1 48 #define MSDC_BUS_8BITS 0x2 49 50 #define MSDC_BURST_64B 0x6 51 52 /*--------------------------------------------------------------------------*/ 53 /* Register Offset */ 54 /*--------------------------------------------------------------------------*/ 55 #define MSDC_CFG 0x0 56 #define MSDC_IOCON 0x04 57 #define MSDC_PS 0x08 58 #define MSDC_INT 0x0c 59 #define MSDC_INTEN 0x10 60 #define MSDC_FIFOCS 0x14 61 #define SDC_CFG 0x30 62 #define SDC_CMD 0x34 63 #define SDC_ARG 0x38 64 #define SDC_STS 0x3c 65 #define SDC_RESP0 0x40 66 #define SDC_RESP1 0x44 67 #define SDC_RESP2 0x48 68 #define SDC_RESP3 0x4c 69 #define SDC_BLK_NUM 0x50 70 #define EMMC_IOCON 0x7c 71 #define SDC_ACMD_RESP 0x80 72 #define MSDC_DMA_SA 0x90 73 #define MSDC_DMA_CTRL 0x98 74 #define MSDC_DMA_CFG 0x9c 75 #define MSDC_PATCH_BIT 0xb0 76 #define MSDC_PATCH_BIT1 0xb4 77 #define MSDC_PAD_TUNE 0xec 78 #define PAD_DS_TUNE 0x188 79 #define EMMC50_CFG0 0x208 80 81 /*--------------------------------------------------------------------------*/ 82 /* Register Mask */ 83 /*--------------------------------------------------------------------------*/ 84 85 /* MSDC_CFG mask */ 86 #define MSDC_CFG_MODE (0x1 << 0) /* RW */ 87 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ 88 #define MSDC_CFG_RST (0x1 << 2) /* RW */ 89 #define MSDC_CFG_PIO (0x1 << 3) /* RW */ 90 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ 91 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ 92 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ 93 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ 94 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ 95 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ 96 #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */ 97 98 /* MSDC_IOCON mask */ 99 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ 100 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ 101 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ 102 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ 103 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ 104 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ 105 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ 106 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ 107 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ 108 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ 109 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ 110 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ 111 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ 112 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ 113 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ 114 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ 115 116 /* MSDC_PS mask */ 117 #define MSDC_PS_CDEN (0x1 << 0) /* RW */ 118 #define MSDC_PS_CDSTS (0x1 << 1) /* R */ 119 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ 120 #define MSDC_PS_DAT (0xff << 16) /* R */ 121 #define MSDC_PS_CMD (0x1 << 24) /* R */ 122 #define MSDC_PS_WP (0x1 << 31) /* R */ 123 124 /* MSDC_INT mask */ 125 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ 126 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ 127 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ 128 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ 129 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ 130 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ 131 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ 132 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ 133 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ 134 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ 135 #define MSDC_INT_CSTA (0x1 << 11) /* R */ 136 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ 137 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ 138 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ 139 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ 140 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ 141 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ 142 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ 143 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ 144 145 /* MSDC_INTEN mask */ 146 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ 147 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ 148 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ 149 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ 150 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ 151 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ 152 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ 153 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ 154 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ 155 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ 156 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ 157 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ 158 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ 159 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ 160 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ 161 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ 162 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ 163 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ 164 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ 165 166 /* MSDC_FIFOCS mask */ 167 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 168 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 169 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ 170 171 /* SDC_CFG mask */ 172 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ 173 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ 174 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 175 #define SDC_CFG_SDIO (0x1 << 19) /* RW */ 176 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 177 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ 178 #define SDC_CFG_DTOC (0xff << 24) /* RW */ 179 180 /* SDC_STS mask */ 181 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ 182 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 183 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ 184 185 /* MSDC_DMA_CTRL mask */ 186 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ 187 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ 188 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ 189 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ 190 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ 191 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ 192 193 /* MSDC_DMA_CFG mask */ 194 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ 195 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ 196 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ 197 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ 198 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ 199 200 /* MSDC_PATCH_BIT mask */ 201 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ 202 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) 203 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) 204 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ 205 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ 206 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ 207 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ 208 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ 209 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ 210 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ 211 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ 212 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ 213 214 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */ 215 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */ 216 217 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */ 218 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */ 219 #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */ 220 221 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */ 222 #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ 223 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ 224 225 #define REQ_CMD_EIO (0x1 << 0) 226 #define REQ_CMD_TMO (0x1 << 1) 227 #define REQ_DAT_ERR (0x1 << 2) 228 #define REQ_STOP_EIO (0x1 << 3) 229 #define REQ_STOP_TMO (0x1 << 4) 230 #define REQ_CMD_BUSY (0x1 << 5) 231 232 #define MSDC_PREPARE_FLAG (0x1 << 0) 233 #define MSDC_ASYNC_FLAG (0x1 << 1) 234 #define MSDC_MMAP_FLAG (0x1 << 2) 235 236 #define MTK_MMC_AUTOSUSPEND_DELAY 50 237 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 238 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 239 240 #define PAD_DELAY_MAX 32 /* PAD delay cells */ 241 /*--------------------------------------------------------------------------*/ 242 /* Descriptor Structure */ 243 /*--------------------------------------------------------------------------*/ 244 struct mt_gpdma_desc { 245 u32 gpd_info; 246 #define GPDMA_DESC_HWO (0x1 << 0) 247 #define GPDMA_DESC_BDP (0x1 << 1) 248 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 249 #define GPDMA_DESC_INT (0x1 << 16) 250 u32 next; 251 u32 ptr; 252 u32 gpd_data_len; 253 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 254 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ 255 u32 arg; 256 u32 blknum; 257 u32 cmd; 258 }; 259 260 struct mt_bdma_desc { 261 u32 bd_info; 262 #define BDMA_DESC_EOL (0x1 << 0) 263 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 264 #define BDMA_DESC_BLKPAD (0x1 << 17) 265 #define BDMA_DESC_DWPAD (0x1 << 18) 266 u32 next; 267 u32 ptr; 268 u32 bd_data_len; 269 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 270 }; 271 272 struct msdc_dma { 273 struct scatterlist *sg; /* I/O scatter list */ 274 struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 275 struct mt_bdma_desc *bd; /* pointer to bd array */ 276 dma_addr_t gpd_addr; /* the physical address of gpd array */ 277 dma_addr_t bd_addr; /* the physical address of bd array */ 278 }; 279 280 struct msdc_save_para { 281 u32 msdc_cfg; 282 u32 iocon; 283 u32 sdc_cfg; 284 u32 pad_tune; 285 u32 patch_bit0; 286 u32 patch_bit1; 287 u32 pad_ds_tune; 288 u32 emmc50_cfg0; 289 }; 290 291 struct msdc_tune_para { 292 u32 iocon; 293 u32 pad_tune; 294 }; 295 296 struct msdc_delay_phase { 297 u8 maxlen; 298 u8 start; 299 u8 final_phase; 300 }; 301 302 struct msdc_host { 303 struct device *dev; 304 struct mmc_host *mmc; /* mmc structure */ 305 int cmd_rsp; 306 307 spinlock_t lock; 308 struct mmc_request *mrq; 309 struct mmc_command *cmd; 310 struct mmc_data *data; 311 int error; 312 313 void __iomem *base; /* host base address */ 314 315 struct msdc_dma dma; /* dma channel */ 316 u64 dma_mask; 317 318 u32 timeout_ns; /* data timeout ns */ 319 u32 timeout_clks; /* data timeout clks */ 320 321 struct pinctrl *pinctrl; 322 struct pinctrl_state *pins_default; 323 struct pinctrl_state *pins_uhs; 324 struct delayed_work req_timeout; 325 int irq; /* host interrupt */ 326 327 struct clk *src_clk; /* msdc source clock */ 328 struct clk *h_clk; /* msdc h_clk */ 329 u32 mclk; /* mmc subsystem clock frequency */ 330 u32 src_clk_freq; /* source clock frequency */ 331 u32 sclk; /* SD/MS bus clock frequency */ 332 unsigned char timing; 333 bool vqmmc_enabled; 334 u32 hs400_ds_delay; 335 bool hs400_mode; /* current eMMC will run at hs400 mode */ 336 struct msdc_save_para save_para; /* used when gate HCLK */ 337 struct msdc_tune_para def_tune_para; /* default tune setting */ 338 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 339 }; 340 341 static void sdr_set_bits(void __iomem *reg, u32 bs) 342 { 343 u32 val = readl(reg); 344 345 val |= bs; 346 writel(val, reg); 347 } 348 349 static void sdr_clr_bits(void __iomem *reg, u32 bs) 350 { 351 u32 val = readl(reg); 352 353 val &= ~bs; 354 writel(val, reg); 355 } 356 357 static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 358 { 359 unsigned int tv = readl(reg); 360 361 tv &= ~field; 362 tv |= ((val) << (ffs((unsigned int)field) - 1)); 363 writel(tv, reg); 364 } 365 366 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 367 { 368 unsigned int tv = readl(reg); 369 370 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 371 } 372 373 static void msdc_reset_hw(struct msdc_host *host) 374 { 375 u32 val; 376 377 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 378 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) 379 cpu_relax(); 380 381 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 382 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) 383 cpu_relax(); 384 385 val = readl(host->base + MSDC_INT); 386 writel(val, host->base + MSDC_INT); 387 } 388 389 static void msdc_cmd_next(struct msdc_host *host, 390 struct mmc_request *mrq, struct mmc_command *cmd); 391 392 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 393 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 394 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 395 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 396 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 397 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 398 399 static u8 msdc_dma_calcs(u8 *buf, u32 len) 400 { 401 u32 i, sum = 0; 402 403 for (i = 0; i < len; i++) 404 sum += buf[i]; 405 return 0xff - (u8) sum; 406 } 407 408 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 409 struct mmc_data *data) 410 { 411 unsigned int j, dma_len; 412 dma_addr_t dma_address; 413 u32 dma_ctrl; 414 struct scatterlist *sg; 415 struct mt_gpdma_desc *gpd; 416 struct mt_bdma_desc *bd; 417 418 sg = data->sg; 419 420 gpd = dma->gpd; 421 bd = dma->bd; 422 423 /* modify gpd */ 424 gpd->gpd_info |= GPDMA_DESC_HWO; 425 gpd->gpd_info |= GPDMA_DESC_BDP; 426 /* need to clear first. use these bits to calc checksum */ 427 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 428 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 429 430 /* modify bd */ 431 for_each_sg(data->sg, sg, data->sg_count, j) { 432 dma_address = sg_dma_address(sg); 433 dma_len = sg_dma_len(sg); 434 435 /* init bd */ 436 bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 437 bd[j].bd_info &= ~BDMA_DESC_DWPAD; 438 bd[j].ptr = (u32)dma_address; 439 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 440 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 441 442 if (j == data->sg_count - 1) /* the last bd */ 443 bd[j].bd_info |= BDMA_DESC_EOL; 444 else 445 bd[j].bd_info &= ~BDMA_DESC_EOL; 446 447 /* checksume need to clear first */ 448 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 449 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 450 } 451 452 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 453 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 454 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 455 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); 456 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 457 writel((u32)dma->gpd_addr, host->base + MSDC_DMA_SA); 458 } 459 460 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq) 461 { 462 struct mmc_data *data = mrq->data; 463 464 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 465 bool read = (data->flags & MMC_DATA_READ) != 0; 466 467 data->host_cookie |= MSDC_PREPARE_FLAG; 468 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 469 read ? DMA_FROM_DEVICE : DMA_TO_DEVICE); 470 } 471 } 472 473 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) 474 { 475 struct mmc_data *data = mrq->data; 476 477 if (data->host_cookie & MSDC_ASYNC_FLAG) 478 return; 479 480 if (data->host_cookie & MSDC_PREPARE_FLAG) { 481 bool read = (data->flags & MMC_DATA_READ) != 0; 482 483 dma_unmap_sg(host->dev, data->sg, data->sg_len, 484 read ? DMA_FROM_DEVICE : DMA_TO_DEVICE); 485 data->host_cookie &= ~MSDC_PREPARE_FLAG; 486 } 487 } 488 489 /* clock control primitives */ 490 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) 491 { 492 u32 timeout, clk_ns; 493 u32 mode = 0; 494 495 host->timeout_ns = ns; 496 host->timeout_clks = clks; 497 if (host->sclk == 0) { 498 timeout = 0; 499 } else { 500 clk_ns = 1000000000UL / host->sclk; 501 timeout = (ns + clk_ns - 1) / clk_ns + clks; 502 /* in 1048576 sclk cycle unit */ 503 timeout = (timeout + (0x1 << 20) - 1) >> 20; 504 sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode); 505 /*DDR mode will double the clk cycles for data timeout */ 506 timeout = mode >= 2 ? timeout * 2 : timeout; 507 timeout = timeout > 1 ? timeout - 1 : 0; 508 timeout = timeout > 255 ? 255 : timeout; 509 } 510 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout); 511 } 512 513 static void msdc_gate_clock(struct msdc_host *host) 514 { 515 clk_disable_unprepare(host->src_clk); 516 clk_disable_unprepare(host->h_clk); 517 } 518 519 static void msdc_ungate_clock(struct msdc_host *host) 520 { 521 clk_prepare_enable(host->h_clk); 522 clk_prepare_enable(host->src_clk); 523 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 524 cpu_relax(); 525 } 526 527 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 528 { 529 u32 mode; 530 u32 flags; 531 u32 div; 532 u32 sclk; 533 534 if (!hz) { 535 dev_dbg(host->dev, "set mclk to 0\n"); 536 host->mclk = 0; 537 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 538 return; 539 } 540 541 flags = readl(host->base + MSDC_INTEN); 542 sdr_clr_bits(host->base + MSDC_INTEN, flags); 543 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 544 if (timing == MMC_TIMING_UHS_DDR50 || 545 timing == MMC_TIMING_MMC_DDR52 || 546 timing == MMC_TIMING_MMC_HS400) { 547 if (timing == MMC_TIMING_MMC_HS400) 548 mode = 0x3; 549 else 550 mode = 0x2; /* ddr mode and use divisor */ 551 552 if (hz >= (host->src_clk_freq >> 2)) { 553 div = 0; /* mean div = 1/4 */ 554 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 555 } else { 556 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 557 sclk = (host->src_clk_freq >> 2) / div; 558 div = (div >> 1); 559 } 560 561 if (timing == MMC_TIMING_MMC_HS400 && 562 hz >= (host->src_clk_freq >> 1)) { 563 sdr_set_bits(host->base + MSDC_CFG, 564 MSDC_CFG_HS400_CK_MODE); 565 sclk = host->src_clk_freq >> 1; 566 div = 0; /* div is ignore when bit18 is set */ 567 } 568 } else if (hz >= host->src_clk_freq) { 569 mode = 0x1; /* no divisor */ 570 div = 0; 571 sclk = host->src_clk_freq; 572 } else { 573 mode = 0x0; /* use divisor */ 574 if (hz >= (host->src_clk_freq >> 1)) { 575 div = 0; /* mean div = 1/2 */ 576 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 577 } else { 578 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 579 sclk = (host->src_clk_freq >> 2) / div; 580 } 581 } 582 sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 583 (mode << 8) | div); 584 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 585 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 586 cpu_relax(); 587 host->sclk = sclk; 588 host->mclk = hz; 589 host->timing = timing; 590 /* need because clk changed. */ 591 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 592 sdr_set_bits(host->base + MSDC_INTEN, flags); 593 594 /* 595 * mmc_select_hs400() will drop to 50Mhz and High speed mode, 596 * tune result of hs200/200Mhz is not suitable for 50Mhz 597 */ 598 if (host->sclk <= 52000000) { 599 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 600 writel(host->def_tune_para.pad_tune, host->base + MSDC_PAD_TUNE); 601 } else { 602 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 603 writel(host->saved_tune_para.pad_tune, host->base + MSDC_PAD_TUNE); 604 } 605 606 dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->sclk, timing); 607 } 608 609 static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 610 struct mmc_request *mrq, struct mmc_command *cmd) 611 { 612 u32 resp; 613 614 switch (mmc_resp_type(cmd)) { 615 /* Actually, R1, R5, R6, R7 are the same */ 616 case MMC_RSP_R1: 617 resp = 0x1; 618 break; 619 case MMC_RSP_R1B: 620 resp = 0x7; 621 break; 622 case MMC_RSP_R2: 623 resp = 0x2; 624 break; 625 case MMC_RSP_R3: 626 resp = 0x3; 627 break; 628 case MMC_RSP_NONE: 629 default: 630 resp = 0x0; 631 break; 632 } 633 634 return resp; 635 } 636 637 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 638 struct mmc_request *mrq, struct mmc_command *cmd) 639 { 640 /* rawcmd : 641 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 642 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 643 */ 644 u32 opcode = cmd->opcode; 645 u32 resp = msdc_cmd_find_resp(host, mrq, cmd); 646 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 647 648 host->cmd_rsp = resp; 649 650 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 651 opcode == MMC_STOP_TRANSMISSION) 652 rawcmd |= (0x1 << 14); 653 else if (opcode == SD_SWITCH_VOLTAGE) 654 rawcmd |= (0x1 << 30); 655 else if (opcode == SD_APP_SEND_SCR || 656 opcode == SD_APP_SEND_NUM_WR_BLKS || 657 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 658 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 659 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 660 rawcmd |= (0x1 << 11); 661 662 if (cmd->data) { 663 struct mmc_data *data = cmd->data; 664 665 if (mmc_op_multi(opcode)) { 666 if (mmc_card_mmc(host->mmc->card) && mrq->sbc && 667 !(mrq->sbc->arg & 0xFFFF0000)) 668 rawcmd |= 0x2 << 28; /* AutoCMD23 */ 669 } 670 671 rawcmd |= ((data->blksz & 0xFFF) << 16); 672 if (data->flags & MMC_DATA_WRITE) 673 rawcmd |= (0x1 << 13); 674 if (data->blocks > 1) 675 rawcmd |= (0x2 << 11); 676 else 677 rawcmd |= (0x1 << 11); 678 /* Always use dma mode */ 679 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 680 681 if (host->timeout_ns != data->timeout_ns || 682 host->timeout_clks != data->timeout_clks) 683 msdc_set_timeout(host, data->timeout_ns, 684 data->timeout_clks); 685 686 writel(data->blocks, host->base + SDC_BLK_NUM); 687 } 688 return rawcmd; 689 } 690 691 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, 692 struct mmc_command *cmd, struct mmc_data *data) 693 { 694 bool read; 695 696 WARN_ON(host->data); 697 host->data = data; 698 read = data->flags & MMC_DATA_READ; 699 700 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 701 msdc_dma_setup(host, &host->dma, data); 702 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 703 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 704 dev_dbg(host->dev, "DMA start\n"); 705 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 706 __func__, cmd->opcode, data->blocks, read); 707 } 708 709 static int msdc_auto_cmd_done(struct msdc_host *host, int events, 710 struct mmc_command *cmd) 711 { 712 u32 *rsp = cmd->resp; 713 714 rsp[0] = readl(host->base + SDC_ACMD_RESP); 715 716 if (events & MSDC_INT_ACMDRDY) { 717 cmd->error = 0; 718 } else { 719 msdc_reset_hw(host); 720 if (events & MSDC_INT_ACMDCRCERR) { 721 cmd->error = -EILSEQ; 722 host->error |= REQ_STOP_EIO; 723 } else if (events & MSDC_INT_ACMDTMO) { 724 cmd->error = -ETIMEDOUT; 725 host->error |= REQ_STOP_TMO; 726 } 727 dev_err(host->dev, 728 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 729 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 730 } 731 return cmd->error; 732 } 733 734 static void msdc_track_cmd_data(struct msdc_host *host, 735 struct mmc_command *cmd, struct mmc_data *data) 736 { 737 if (host->error) 738 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 739 __func__, cmd->opcode, cmd->arg, host->error); 740 } 741 742 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 743 { 744 unsigned long flags; 745 bool ret; 746 747 ret = cancel_delayed_work(&host->req_timeout); 748 if (!ret) { 749 /* delay work already running */ 750 return; 751 } 752 spin_lock_irqsave(&host->lock, flags); 753 host->mrq = NULL; 754 spin_unlock_irqrestore(&host->lock, flags); 755 756 msdc_track_cmd_data(host, mrq->cmd, mrq->data); 757 if (mrq->data) 758 msdc_unprepare_data(host, mrq); 759 mmc_request_done(host->mmc, mrq); 760 } 761 762 /* returns true if command is fully handled; returns false otherwise */ 763 static bool msdc_cmd_done(struct msdc_host *host, int events, 764 struct mmc_request *mrq, struct mmc_command *cmd) 765 { 766 bool done = false; 767 bool sbc_error; 768 unsigned long flags; 769 u32 *rsp = cmd->resp; 770 771 if (mrq->sbc && cmd == mrq->cmd && 772 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 773 | MSDC_INT_ACMDTMO))) 774 msdc_auto_cmd_done(host, events, mrq->sbc); 775 776 sbc_error = mrq->sbc && mrq->sbc->error; 777 778 if (!sbc_error && !(events & (MSDC_INT_CMDRDY 779 | MSDC_INT_RSPCRCERR 780 | MSDC_INT_CMDTMO))) 781 return done; 782 783 spin_lock_irqsave(&host->lock, flags); 784 done = !host->cmd; 785 host->cmd = NULL; 786 spin_unlock_irqrestore(&host->lock, flags); 787 788 if (done) 789 return true; 790 791 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 792 793 if (cmd->flags & MMC_RSP_PRESENT) { 794 if (cmd->flags & MMC_RSP_136) { 795 rsp[0] = readl(host->base + SDC_RESP3); 796 rsp[1] = readl(host->base + SDC_RESP2); 797 rsp[2] = readl(host->base + SDC_RESP1); 798 rsp[3] = readl(host->base + SDC_RESP0); 799 } else { 800 rsp[0] = readl(host->base + SDC_RESP0); 801 } 802 } 803 804 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 805 if (cmd->opcode != MMC_SEND_TUNING_BLOCK && 806 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200) 807 /* 808 * should not clear fifo/interrupt as the tune data 809 * may have alreay come. 810 */ 811 msdc_reset_hw(host); 812 if (events & MSDC_INT_RSPCRCERR) { 813 cmd->error = -EILSEQ; 814 host->error |= REQ_CMD_EIO; 815 } else if (events & MSDC_INT_CMDTMO) { 816 cmd->error = -ETIMEDOUT; 817 host->error |= REQ_CMD_TMO; 818 } 819 } 820 if (cmd->error) 821 dev_dbg(host->dev, 822 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 823 __func__, cmd->opcode, cmd->arg, rsp[0], 824 cmd->error); 825 826 msdc_cmd_next(host, mrq, cmd); 827 return true; 828 } 829 830 /* It is the core layer's responsibility to ensure card status 831 * is correct before issue a request. but host design do below 832 * checks recommended. 833 */ 834 static inline bool msdc_cmd_is_ready(struct msdc_host *host, 835 struct mmc_request *mrq, struct mmc_command *cmd) 836 { 837 /* The max busy time we can endure is 20ms */ 838 unsigned long tmo = jiffies + msecs_to_jiffies(20); 839 840 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && 841 time_before(jiffies, tmo)) 842 cpu_relax(); 843 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { 844 dev_err(host->dev, "CMD bus busy detected\n"); 845 host->error |= REQ_CMD_BUSY; 846 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 847 return false; 848 } 849 850 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 851 tmo = jiffies + msecs_to_jiffies(20); 852 /* R1B or with data, should check SDCBUSY */ 853 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && 854 time_before(jiffies, tmo)) 855 cpu_relax(); 856 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { 857 dev_err(host->dev, "Controller busy detected\n"); 858 host->error |= REQ_CMD_BUSY; 859 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 860 return false; 861 } 862 } 863 return true; 864 } 865 866 static void msdc_start_command(struct msdc_host *host, 867 struct mmc_request *mrq, struct mmc_command *cmd) 868 { 869 u32 rawcmd; 870 871 WARN_ON(host->cmd); 872 host->cmd = cmd; 873 874 if (!msdc_cmd_is_ready(host, mrq, cmd)) 875 return; 876 877 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 878 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 879 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 880 msdc_reset_hw(host); 881 } 882 883 cmd->error = 0; 884 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 885 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 886 887 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 888 writel(cmd->arg, host->base + SDC_ARG); 889 writel(rawcmd, host->base + SDC_CMD); 890 } 891 892 static void msdc_cmd_next(struct msdc_host *host, 893 struct mmc_request *mrq, struct mmc_command *cmd) 894 { 895 if ((cmd->error && 896 !(cmd->error == -EILSEQ && 897 (cmd->opcode == MMC_SEND_TUNING_BLOCK || 898 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) || 899 (mrq->sbc && mrq->sbc->error)) 900 msdc_request_done(host, mrq); 901 else if (cmd == mrq->sbc) 902 msdc_start_command(host, mrq, mrq->cmd); 903 else if (!cmd->data) 904 msdc_request_done(host, mrq); 905 else 906 msdc_start_data(host, mrq, cmd, cmd->data); 907 } 908 909 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 910 { 911 struct msdc_host *host = mmc_priv(mmc); 912 913 host->error = 0; 914 WARN_ON(host->mrq); 915 host->mrq = mrq; 916 917 if (mrq->data) 918 msdc_prepare_data(host, mrq); 919 920 /* if SBC is required, we have HW option and SW option. 921 * if HW option is enabled, and SBC does not have "special" flags, 922 * use HW option, otherwise use SW option 923 */ 924 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 925 (mrq->sbc->arg & 0xFFFF0000))) 926 msdc_start_command(host, mrq, mrq->sbc); 927 else 928 msdc_start_command(host, mrq, mrq->cmd); 929 } 930 931 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 932 { 933 struct msdc_host *host = mmc_priv(mmc); 934 struct mmc_data *data = mrq->data; 935 936 if (!data) 937 return; 938 939 msdc_prepare_data(host, mrq); 940 data->host_cookie |= MSDC_ASYNC_FLAG; 941 } 942 943 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 944 int err) 945 { 946 struct msdc_host *host = mmc_priv(mmc); 947 struct mmc_data *data; 948 949 data = mrq->data; 950 if (!data) 951 return; 952 if (data->host_cookie) { 953 data->host_cookie &= ~MSDC_ASYNC_FLAG; 954 msdc_unprepare_data(host, mrq); 955 } 956 } 957 958 static void msdc_data_xfer_next(struct msdc_host *host, 959 struct mmc_request *mrq, struct mmc_data *data) 960 { 961 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 962 !mrq->sbc) 963 msdc_start_command(host, mrq, mrq->stop); 964 else 965 msdc_request_done(host, mrq); 966 } 967 968 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 969 struct mmc_request *mrq, struct mmc_data *data) 970 { 971 struct mmc_command *stop = data->stop; 972 unsigned long flags; 973 bool done; 974 unsigned int check_data = events & 975 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 976 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 977 | MSDC_INT_DMA_PROTECT); 978 979 spin_lock_irqsave(&host->lock, flags); 980 done = !host->data; 981 if (check_data) 982 host->data = NULL; 983 spin_unlock_irqrestore(&host->lock, flags); 984 985 if (done) 986 return true; 987 988 if (check_data || (stop && stop->error)) { 989 dev_dbg(host->dev, "DMA status: 0x%8X\n", 990 readl(host->base + MSDC_DMA_CFG)); 991 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 992 1); 993 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) 994 cpu_relax(); 995 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 996 dev_dbg(host->dev, "DMA stop\n"); 997 998 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 999 data->bytes_xfered = data->blocks * data->blksz; 1000 } else { 1001 dev_dbg(host->dev, "interrupt events: %x\n", events); 1002 msdc_reset_hw(host); 1003 host->error |= REQ_DAT_ERR; 1004 data->bytes_xfered = 0; 1005 1006 if (events & MSDC_INT_DATTMO) 1007 data->error = -ETIMEDOUT; 1008 else if (events & MSDC_INT_DATCRCERR) 1009 data->error = -EILSEQ; 1010 1011 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 1012 __func__, mrq->cmd->opcode, data->blocks); 1013 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 1014 (int)data->error, data->bytes_xfered); 1015 } 1016 1017 msdc_data_xfer_next(host, mrq, data); 1018 done = true; 1019 } 1020 return done; 1021 } 1022 1023 static void msdc_set_buswidth(struct msdc_host *host, u32 width) 1024 { 1025 u32 val = readl(host->base + SDC_CFG); 1026 1027 val &= ~SDC_CFG_BUSWIDTH; 1028 1029 switch (width) { 1030 default: 1031 case MMC_BUS_WIDTH_1: 1032 val |= (MSDC_BUS_1BITS << 16); 1033 break; 1034 case MMC_BUS_WIDTH_4: 1035 val |= (MSDC_BUS_4BITS << 16); 1036 break; 1037 case MMC_BUS_WIDTH_8: 1038 val |= (MSDC_BUS_8BITS << 16); 1039 break; 1040 } 1041 1042 writel(val, host->base + SDC_CFG); 1043 dev_dbg(host->dev, "Bus Width = %d", width); 1044 } 1045 1046 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 1047 { 1048 struct msdc_host *host = mmc_priv(mmc); 1049 int ret = 0; 1050 1051 if (!IS_ERR(mmc->supply.vqmmc)) { 1052 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1053 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 1054 dev_err(host->dev, "Unsupported signal voltage!\n"); 1055 return -EINVAL; 1056 } 1057 1058 ret = mmc_regulator_set_vqmmc(mmc, ios); 1059 if (ret) { 1060 dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1061 ret, ios->signal_voltage); 1062 } else { 1063 /* Apply different pinctrl settings for different signal voltage */ 1064 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 1065 pinctrl_select_state(host->pinctrl, host->pins_uhs); 1066 else 1067 pinctrl_select_state(host->pinctrl, host->pins_default); 1068 } 1069 } 1070 return ret; 1071 } 1072 1073 static int msdc_card_busy(struct mmc_host *mmc) 1074 { 1075 struct msdc_host *host = mmc_priv(mmc); 1076 u32 status = readl(host->base + MSDC_PS); 1077 1078 /* only check if data0 is low */ 1079 return !(status & BIT(16)); 1080 } 1081 1082 static void msdc_request_timeout(struct work_struct *work) 1083 { 1084 struct msdc_host *host = container_of(work, struct msdc_host, 1085 req_timeout.work); 1086 1087 /* simulate HW timeout status */ 1088 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 1089 if (host->mrq) { 1090 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 1091 host->mrq, host->mrq->cmd->opcode); 1092 if (host->cmd) { 1093 dev_err(host->dev, "%s: aborting cmd=%d\n", 1094 __func__, host->cmd->opcode); 1095 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 1096 host->cmd); 1097 } else if (host->data) { 1098 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 1099 __func__, host->mrq->cmd->opcode, 1100 host->data->blocks); 1101 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 1102 host->data); 1103 } 1104 } 1105 } 1106 1107 static irqreturn_t msdc_irq(int irq, void *dev_id) 1108 { 1109 struct msdc_host *host = (struct msdc_host *) dev_id; 1110 1111 while (true) { 1112 unsigned long flags; 1113 struct mmc_request *mrq; 1114 struct mmc_command *cmd; 1115 struct mmc_data *data; 1116 u32 events, event_mask; 1117 1118 spin_lock_irqsave(&host->lock, flags); 1119 events = readl(host->base + MSDC_INT); 1120 event_mask = readl(host->base + MSDC_INTEN); 1121 /* clear interrupts */ 1122 writel(events & event_mask, host->base + MSDC_INT); 1123 1124 mrq = host->mrq; 1125 cmd = host->cmd; 1126 data = host->data; 1127 spin_unlock_irqrestore(&host->lock, flags); 1128 1129 if (!(events & event_mask)) 1130 break; 1131 1132 if (!mrq) { 1133 dev_err(host->dev, 1134 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 1135 __func__, events, event_mask); 1136 WARN_ON(1); 1137 break; 1138 } 1139 1140 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 1141 1142 if (cmd) 1143 msdc_cmd_done(host, events, mrq, cmd); 1144 else if (data) 1145 msdc_data_xfer_done(host, events, mrq, data); 1146 } 1147 1148 return IRQ_HANDLED; 1149 } 1150 1151 static void msdc_init_hw(struct msdc_host *host) 1152 { 1153 u32 val; 1154 1155 /* Configure to MMC/SD mode, clock free running */ 1156 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 1157 1158 /* Reset */ 1159 msdc_reset_hw(host); 1160 1161 /* Disable card detection */ 1162 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1163 1164 /* Disable and clear all interrupts */ 1165 writel(0, host->base + MSDC_INTEN); 1166 val = readl(host->base + MSDC_INT); 1167 writel(val, host->base + MSDC_INT); 1168 1169 writel(0, host->base + MSDC_PAD_TUNE); 1170 writel(0, host->base + MSDC_IOCON); 1171 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 1172 writel(0x403c0046, host->base + MSDC_PATCH_BIT); 1173 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 1174 writel(0xffff0089, host->base + MSDC_PATCH_BIT1); 1175 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1176 1177 /* Configure to enable SDIO mode. 1178 * it's must otherwise sdio cmd5 failed 1179 */ 1180 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1181 1182 /* disable detect SDIO device interrupt function */ 1183 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1184 1185 /* Configure to default data timeout */ 1186 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 1187 1188 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 1189 host->def_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE); 1190 dev_dbg(host->dev, "init hardware done!"); 1191 } 1192 1193 static void msdc_deinit_hw(struct msdc_host *host) 1194 { 1195 u32 val; 1196 /* Disable and clear all interrupts */ 1197 writel(0, host->base + MSDC_INTEN); 1198 1199 val = readl(host->base + MSDC_INT); 1200 writel(val, host->base + MSDC_INT); 1201 } 1202 1203 /* init gpd and bd list in msdc_drv_probe */ 1204 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 1205 { 1206 struct mt_gpdma_desc *gpd = dma->gpd; 1207 struct mt_bdma_desc *bd = dma->bd; 1208 int i; 1209 1210 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 1211 1212 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 1213 gpd->ptr = (u32)dma->bd_addr; /* physical address */ 1214 /* gpd->next is must set for desc DMA 1215 * That's why must alloc 2 gpd structure. 1216 */ 1217 gpd->next = (u32)dma->gpd_addr + sizeof(struct mt_gpdma_desc); 1218 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 1219 for (i = 0; i < (MAX_BD_NUM - 1); i++) 1220 bd[i].next = (u32)dma->bd_addr + sizeof(*bd) * (i + 1); 1221 } 1222 1223 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1224 { 1225 struct msdc_host *host = mmc_priv(mmc); 1226 int ret; 1227 1228 msdc_set_buswidth(host, ios->bus_width); 1229 1230 /* Suspend/Resume will do power off/on */ 1231 switch (ios->power_mode) { 1232 case MMC_POWER_UP: 1233 if (!IS_ERR(mmc->supply.vmmc)) { 1234 msdc_init_hw(host); 1235 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1236 ios->vdd); 1237 if (ret) { 1238 dev_err(host->dev, "Failed to set vmmc power!\n"); 1239 return; 1240 } 1241 } 1242 break; 1243 case MMC_POWER_ON: 1244 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1245 ret = regulator_enable(mmc->supply.vqmmc); 1246 if (ret) 1247 dev_err(host->dev, "Failed to set vqmmc power!\n"); 1248 else 1249 host->vqmmc_enabled = true; 1250 } 1251 break; 1252 case MMC_POWER_OFF: 1253 if (!IS_ERR(mmc->supply.vmmc)) 1254 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1255 1256 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1257 regulator_disable(mmc->supply.vqmmc); 1258 host->vqmmc_enabled = false; 1259 } 1260 break; 1261 default: 1262 break; 1263 } 1264 1265 if (host->mclk != ios->clock || host->timing != ios->timing) 1266 msdc_set_mclk(host, ios->timing, ios->clock); 1267 } 1268 1269 static u32 test_delay_bit(u32 delay, u32 bit) 1270 { 1271 bit %= PAD_DELAY_MAX; 1272 return delay & (1 << bit); 1273 } 1274 1275 static int get_delay_len(u32 delay, u32 start_bit) 1276 { 1277 int i; 1278 1279 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 1280 if (test_delay_bit(delay, start_bit + i) == 0) 1281 return i; 1282 } 1283 return PAD_DELAY_MAX - start_bit; 1284 } 1285 1286 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 1287 { 1288 int start = 0, len = 0; 1289 int start_final = 0, len_final = 0; 1290 u8 final_phase = 0xff; 1291 struct msdc_delay_phase delay_phase = { 0, }; 1292 1293 if (delay == 0) { 1294 dev_err(host->dev, "phase error: [map:%x]\n", delay); 1295 delay_phase.final_phase = final_phase; 1296 return delay_phase; 1297 } 1298 1299 while (start < PAD_DELAY_MAX) { 1300 len = get_delay_len(delay, start); 1301 if (len_final < len) { 1302 start_final = start; 1303 len_final = len; 1304 } 1305 start += len ? len : 1; 1306 if (len >= 8 && start_final < 4) 1307 break; 1308 } 1309 1310 /* The rule is that to find the smallest delay cell */ 1311 if (start_final == 0) 1312 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 1313 else 1314 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 1315 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 1316 delay, len_final, final_phase); 1317 1318 delay_phase.maxlen = len_final; 1319 delay_phase.start = start_final; 1320 delay_phase.final_phase = final_phase; 1321 return delay_phase; 1322 } 1323 1324 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 1325 { 1326 struct msdc_host *host = mmc_priv(mmc); 1327 u32 rise_delay = 0, fall_delay = 0; 1328 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1329 u8 final_delay, final_maxlen; 1330 int cmd_err; 1331 int i; 1332 1333 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1334 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1335 sdr_set_field(host->base + MSDC_PAD_TUNE, 1336 MSDC_PAD_TUNE_CMDRDLY, i); 1337 mmc_send_tuning(mmc, opcode, &cmd_err); 1338 if (!cmd_err) 1339 rise_delay |= (1 << i); 1340 } 1341 final_rise_delay = get_best_delay(host, rise_delay); 1342 /* if rising edge has enough margin, then do not scan falling edge */ 1343 if (final_rise_delay.maxlen >= 10 || 1344 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1345 goto skip_fall; 1346 1347 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1348 for (i = 0; i < PAD_DELAY_MAX; i++) { 1349 sdr_set_field(host->base + MSDC_PAD_TUNE, 1350 MSDC_PAD_TUNE_CMDRDLY, i); 1351 mmc_send_tuning(mmc, opcode, &cmd_err); 1352 if (!cmd_err) 1353 fall_delay |= (1 << i); 1354 } 1355 final_fall_delay = get_best_delay(host, fall_delay); 1356 1357 skip_fall: 1358 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1359 if (final_maxlen == final_rise_delay.maxlen) { 1360 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1361 sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY, 1362 final_rise_delay.final_phase); 1363 final_delay = final_rise_delay.final_phase; 1364 } else { 1365 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1366 sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY, 1367 final_fall_delay.final_phase); 1368 final_delay = final_fall_delay.final_phase; 1369 } 1370 1371 return final_delay == 0xff ? -EIO : 0; 1372 } 1373 1374 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 1375 { 1376 struct msdc_host *host = mmc_priv(mmc); 1377 u32 rise_delay = 0, fall_delay = 0; 1378 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1379 u8 final_delay, final_maxlen; 1380 int i, ret; 1381 1382 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1383 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1384 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1385 sdr_set_field(host->base + MSDC_PAD_TUNE, 1386 MSDC_PAD_TUNE_DATRRDLY, i); 1387 ret = mmc_send_tuning(mmc, opcode, NULL); 1388 if (!ret) 1389 rise_delay |= (1 << i); 1390 } 1391 final_rise_delay = get_best_delay(host, rise_delay); 1392 /* if rising edge has enough margin, then do not scan falling edge */ 1393 if (final_rise_delay.maxlen >= 10 || 1394 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1395 goto skip_fall; 1396 1397 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1398 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1399 for (i = 0; i < PAD_DELAY_MAX; i++) { 1400 sdr_set_field(host->base + MSDC_PAD_TUNE, 1401 MSDC_PAD_TUNE_DATRRDLY, i); 1402 ret = mmc_send_tuning(mmc, opcode, NULL); 1403 if (!ret) 1404 fall_delay |= (1 << i); 1405 } 1406 final_fall_delay = get_best_delay(host, fall_delay); 1407 1408 skip_fall: 1409 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1410 if (final_maxlen == final_rise_delay.maxlen) { 1411 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1412 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1413 sdr_set_field(host->base + MSDC_PAD_TUNE, 1414 MSDC_PAD_TUNE_DATRRDLY, 1415 final_rise_delay.final_phase); 1416 final_delay = final_rise_delay.final_phase; 1417 } else { 1418 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1419 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1420 sdr_set_field(host->base + MSDC_PAD_TUNE, 1421 MSDC_PAD_TUNE_DATRRDLY, 1422 final_fall_delay.final_phase); 1423 final_delay = final_fall_delay.final_phase; 1424 } 1425 1426 return final_delay == 0xff ? -EIO : 0; 1427 } 1428 1429 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1430 { 1431 struct msdc_host *host = mmc_priv(mmc); 1432 int ret; 1433 1434 ret = msdc_tune_response(mmc, opcode); 1435 if (ret == -EIO) { 1436 dev_err(host->dev, "Tune response fail!\n"); 1437 return ret; 1438 } 1439 if (host->hs400_mode == false) { 1440 ret = msdc_tune_data(mmc, opcode); 1441 if (ret == -EIO) 1442 dev_err(host->dev, "Tune data fail!\n"); 1443 } 1444 1445 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1446 host->saved_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE); 1447 return ret; 1448 } 1449 1450 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 1451 { 1452 struct msdc_host *host = mmc_priv(mmc); 1453 host->hs400_mode = true; 1454 1455 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 1456 return 0; 1457 } 1458 1459 static void msdc_hw_reset(struct mmc_host *mmc) 1460 { 1461 struct msdc_host *host = mmc_priv(mmc); 1462 1463 sdr_set_bits(host->base + EMMC_IOCON, 1); 1464 udelay(10); /* 10us is enough */ 1465 sdr_clr_bits(host->base + EMMC_IOCON, 1); 1466 } 1467 1468 static struct mmc_host_ops mt_msdc_ops = { 1469 .post_req = msdc_post_req, 1470 .pre_req = msdc_pre_req, 1471 .request = msdc_ops_request, 1472 .set_ios = msdc_ops_set_ios, 1473 .get_ro = mmc_gpio_get_ro, 1474 .start_signal_voltage_switch = msdc_ops_switch_volt, 1475 .card_busy = msdc_card_busy, 1476 .execute_tuning = msdc_execute_tuning, 1477 .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 1478 .hw_reset = msdc_hw_reset, 1479 }; 1480 1481 static int msdc_drv_probe(struct platform_device *pdev) 1482 { 1483 struct mmc_host *mmc; 1484 struct msdc_host *host; 1485 struct resource *res; 1486 int ret; 1487 1488 if (!pdev->dev.of_node) { 1489 dev_err(&pdev->dev, "No DT found\n"); 1490 return -EINVAL; 1491 } 1492 /* Allocate MMC host for this device */ 1493 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 1494 if (!mmc) 1495 return -ENOMEM; 1496 1497 host = mmc_priv(mmc); 1498 ret = mmc_of_parse(mmc); 1499 if (ret) 1500 goto host_free; 1501 1502 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1503 host->base = devm_ioremap_resource(&pdev->dev, res); 1504 if (IS_ERR(host->base)) { 1505 ret = PTR_ERR(host->base); 1506 goto host_free; 1507 } 1508 1509 ret = mmc_regulator_get_supply(mmc); 1510 if (ret == -EPROBE_DEFER) 1511 goto host_free; 1512 1513 host->src_clk = devm_clk_get(&pdev->dev, "source"); 1514 if (IS_ERR(host->src_clk)) { 1515 ret = PTR_ERR(host->src_clk); 1516 goto host_free; 1517 } 1518 1519 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 1520 if (IS_ERR(host->h_clk)) { 1521 ret = PTR_ERR(host->h_clk); 1522 goto host_free; 1523 } 1524 1525 host->irq = platform_get_irq(pdev, 0); 1526 if (host->irq < 0) { 1527 ret = -EINVAL; 1528 goto host_free; 1529 } 1530 1531 host->pinctrl = devm_pinctrl_get(&pdev->dev); 1532 if (IS_ERR(host->pinctrl)) { 1533 ret = PTR_ERR(host->pinctrl); 1534 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 1535 goto host_free; 1536 } 1537 1538 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 1539 if (IS_ERR(host->pins_default)) { 1540 ret = PTR_ERR(host->pins_default); 1541 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 1542 goto host_free; 1543 } 1544 1545 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 1546 if (IS_ERR(host->pins_uhs)) { 1547 ret = PTR_ERR(host->pins_uhs); 1548 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 1549 goto host_free; 1550 } 1551 1552 if (!of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 1553 &host->hs400_ds_delay)) 1554 dev_dbg(&pdev->dev, "hs400-ds-delay: %x\n", 1555 host->hs400_ds_delay); 1556 1557 host->dev = &pdev->dev; 1558 host->mmc = mmc; 1559 host->src_clk_freq = clk_get_rate(host->src_clk); 1560 /* Set host parameters to mmc */ 1561 mmc->ops = &mt_msdc_ops; 1562 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 1563 1564 mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; 1565 /* MMC core transfer sizes tunable parameters */ 1566 mmc->max_segs = MAX_BD_NUM; 1567 mmc->max_seg_size = BDMA_DESC_BUFLEN; 1568 mmc->max_blk_size = 2048; 1569 mmc->max_req_size = 512 * 1024; 1570 mmc->max_blk_count = mmc->max_req_size / 512; 1571 host->dma_mask = DMA_BIT_MASK(32); 1572 mmc_dev(mmc)->dma_mask = &host->dma_mask; 1573 1574 host->timeout_clks = 3 * 1048576; 1575 host->dma.gpd = dma_alloc_coherent(&pdev->dev, 1576 2 * sizeof(struct mt_gpdma_desc), 1577 &host->dma.gpd_addr, GFP_KERNEL); 1578 host->dma.bd = dma_alloc_coherent(&pdev->dev, 1579 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 1580 &host->dma.bd_addr, GFP_KERNEL); 1581 if (!host->dma.gpd || !host->dma.bd) { 1582 ret = -ENOMEM; 1583 goto release_mem; 1584 } 1585 msdc_init_gpd_bd(host, &host->dma); 1586 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 1587 spin_lock_init(&host->lock); 1588 1589 platform_set_drvdata(pdev, mmc); 1590 msdc_ungate_clock(host); 1591 msdc_init_hw(host); 1592 1593 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 1594 IRQF_TRIGGER_LOW | IRQF_ONESHOT, pdev->name, host); 1595 if (ret) 1596 goto release; 1597 1598 pm_runtime_set_active(host->dev); 1599 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 1600 pm_runtime_use_autosuspend(host->dev); 1601 pm_runtime_enable(host->dev); 1602 ret = mmc_add_host(mmc); 1603 1604 if (ret) 1605 goto end; 1606 1607 return 0; 1608 end: 1609 pm_runtime_disable(host->dev); 1610 release: 1611 platform_set_drvdata(pdev, NULL); 1612 msdc_deinit_hw(host); 1613 msdc_gate_clock(host); 1614 release_mem: 1615 if (host->dma.gpd) 1616 dma_free_coherent(&pdev->dev, 1617 2 * sizeof(struct mt_gpdma_desc), 1618 host->dma.gpd, host->dma.gpd_addr); 1619 if (host->dma.bd) 1620 dma_free_coherent(&pdev->dev, 1621 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 1622 host->dma.bd, host->dma.bd_addr); 1623 host_free: 1624 mmc_free_host(mmc); 1625 1626 return ret; 1627 } 1628 1629 static int msdc_drv_remove(struct platform_device *pdev) 1630 { 1631 struct mmc_host *mmc; 1632 struct msdc_host *host; 1633 1634 mmc = platform_get_drvdata(pdev); 1635 host = mmc_priv(mmc); 1636 1637 pm_runtime_get_sync(host->dev); 1638 1639 platform_set_drvdata(pdev, NULL); 1640 mmc_remove_host(host->mmc); 1641 msdc_deinit_hw(host); 1642 msdc_gate_clock(host); 1643 1644 pm_runtime_disable(host->dev); 1645 pm_runtime_put_noidle(host->dev); 1646 dma_free_coherent(&pdev->dev, 1647 sizeof(struct mt_gpdma_desc), 1648 host->dma.gpd, host->dma.gpd_addr); 1649 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 1650 host->dma.bd, host->dma.bd_addr); 1651 1652 mmc_free_host(host->mmc); 1653 1654 return 0; 1655 } 1656 1657 #ifdef CONFIG_PM 1658 static void msdc_save_reg(struct msdc_host *host) 1659 { 1660 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 1661 host->save_para.iocon = readl(host->base + MSDC_IOCON); 1662 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 1663 host->save_para.pad_tune = readl(host->base + MSDC_PAD_TUNE); 1664 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 1665 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 1666 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 1667 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 1668 } 1669 1670 static void msdc_restore_reg(struct msdc_host *host) 1671 { 1672 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 1673 writel(host->save_para.iocon, host->base + MSDC_IOCON); 1674 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 1675 writel(host->save_para.pad_tune, host->base + MSDC_PAD_TUNE); 1676 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 1677 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 1678 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 1679 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 1680 } 1681 1682 static int msdc_runtime_suspend(struct device *dev) 1683 { 1684 struct mmc_host *mmc = dev_get_drvdata(dev); 1685 struct msdc_host *host = mmc_priv(mmc); 1686 1687 msdc_save_reg(host); 1688 msdc_gate_clock(host); 1689 return 0; 1690 } 1691 1692 static int msdc_runtime_resume(struct device *dev) 1693 { 1694 struct mmc_host *mmc = dev_get_drvdata(dev); 1695 struct msdc_host *host = mmc_priv(mmc); 1696 1697 msdc_ungate_clock(host); 1698 msdc_restore_reg(host); 1699 return 0; 1700 } 1701 #endif 1702 1703 static const struct dev_pm_ops msdc_dev_pm_ops = { 1704 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1705 pm_runtime_force_resume) 1706 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 1707 }; 1708 1709 static const struct of_device_id msdc_of_ids[] = { 1710 { .compatible = "mediatek,mt8135-mmc", }, 1711 {} 1712 }; 1713 MODULE_DEVICE_TABLE(of, msdc_of_ids); 1714 1715 static struct platform_driver mt_msdc_driver = { 1716 .probe = msdc_drv_probe, 1717 .remove = msdc_drv_remove, 1718 .driver = { 1719 .name = "mtk-msdc", 1720 .of_match_table = msdc_of_ids, 1721 .pm = &msdc_dev_pm_ops, 1722 }, 1723 }; 1724 1725 module_platform_driver(mt_msdc_driver); 1726 MODULE_LICENSE("GPL v2"); 1727 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 1728