1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2015 MediaTek Inc. 4 * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 5 */ 6 7 #include <linux/module.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/ioport.h> 12 #include <linux/irq.h> 13 #include <linux/of_address.h> 14 #include <linux/of_device.h> 15 #include <linux/of_irq.h> 16 #include <linux/of_gpio.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/slab.h> 23 #include <linux/spinlock.h> 24 #include <linux/interrupt.h> 25 #include <linux/reset.h> 26 27 #include <linux/mmc/card.h> 28 #include <linux/mmc/core.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/mmc.h> 31 #include <linux/mmc/sd.h> 32 #include <linux/mmc/sdio.h> 33 #include <linux/mmc/slot-gpio.h> 34 35 #include "cqhci.h" 36 37 #define MAX_BD_NUM 1024 38 #define MSDC_NR_CLOCKS 3 39 40 /*--------------------------------------------------------------------------*/ 41 /* Common Definition */ 42 /*--------------------------------------------------------------------------*/ 43 #define MSDC_BUS_1BITS 0x0 44 #define MSDC_BUS_4BITS 0x1 45 #define MSDC_BUS_8BITS 0x2 46 47 #define MSDC_BURST_64B 0x6 48 49 /*--------------------------------------------------------------------------*/ 50 /* Register Offset */ 51 /*--------------------------------------------------------------------------*/ 52 #define MSDC_CFG 0x0 53 #define MSDC_IOCON 0x04 54 #define MSDC_PS 0x08 55 #define MSDC_INT 0x0c 56 #define MSDC_INTEN 0x10 57 #define MSDC_FIFOCS 0x14 58 #define SDC_CFG 0x30 59 #define SDC_CMD 0x34 60 #define SDC_ARG 0x38 61 #define SDC_STS 0x3c 62 #define SDC_RESP0 0x40 63 #define SDC_RESP1 0x44 64 #define SDC_RESP2 0x48 65 #define SDC_RESP3 0x4c 66 #define SDC_BLK_NUM 0x50 67 #define SDC_ADV_CFG0 0x64 68 #define EMMC_IOCON 0x7c 69 #define SDC_ACMD_RESP 0x80 70 #define DMA_SA_H4BIT 0x8c 71 #define MSDC_DMA_SA 0x90 72 #define MSDC_DMA_CTRL 0x98 73 #define MSDC_DMA_CFG 0x9c 74 #define MSDC_PATCH_BIT 0xb0 75 #define MSDC_PATCH_BIT1 0xb4 76 #define MSDC_PATCH_BIT2 0xb8 77 #define MSDC_PAD_TUNE 0xec 78 #define MSDC_PAD_TUNE0 0xf0 79 #define PAD_DS_TUNE 0x188 80 #define PAD_CMD_TUNE 0x18c 81 #define EMMC51_CFG0 0x204 82 #define EMMC50_CFG0 0x208 83 #define EMMC50_CFG1 0x20c 84 #define EMMC50_CFG3 0x220 85 #define SDC_FIFO_CFG 0x228 86 #define CQHCI_SETTING 0x7fc 87 88 /*--------------------------------------------------------------------------*/ 89 /* Top Pad Register Offset */ 90 /*--------------------------------------------------------------------------*/ 91 #define EMMC_TOP_CONTROL 0x00 92 #define EMMC_TOP_CMD 0x04 93 #define EMMC50_PAD_DS_TUNE 0x0c 94 95 /*--------------------------------------------------------------------------*/ 96 /* Register Mask */ 97 /*--------------------------------------------------------------------------*/ 98 99 /* MSDC_CFG mask */ 100 #define MSDC_CFG_MODE (0x1 << 0) /* RW */ 101 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ 102 #define MSDC_CFG_RST (0x1 << 2) /* RW */ 103 #define MSDC_CFG_PIO (0x1 << 3) /* RW */ 104 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ 105 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ 106 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ 107 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ 108 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ 109 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ 110 #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */ 111 #define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */ 112 #define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */ 113 #define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */ 114 115 /* MSDC_IOCON mask */ 116 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ 117 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ 118 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ 119 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ 120 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ 121 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ 122 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ 123 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ 124 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ 125 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ 126 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ 127 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ 128 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ 129 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ 130 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ 131 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ 132 133 /* MSDC_PS mask */ 134 #define MSDC_PS_CDEN (0x1 << 0) /* RW */ 135 #define MSDC_PS_CDSTS (0x1 << 1) /* R */ 136 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ 137 #define MSDC_PS_DAT (0xff << 16) /* R */ 138 #define MSDC_PS_DATA1 (0x1 << 17) /* R */ 139 #define MSDC_PS_CMD (0x1 << 24) /* R */ 140 #define MSDC_PS_WP (0x1 << 31) /* R */ 141 142 /* MSDC_INT mask */ 143 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ 144 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ 145 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ 146 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ 147 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ 148 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ 149 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ 150 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ 151 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ 152 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ 153 #define MSDC_INT_CSTA (0x1 << 11) /* R */ 154 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ 155 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ 156 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ 157 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ 158 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ 159 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ 160 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ 161 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ 162 #define MSDC_INT_CMDQ (0x1 << 28) /* W1C */ 163 164 /* MSDC_INTEN mask */ 165 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ 166 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ 167 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ 168 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ 169 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ 170 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ 171 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ 172 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ 173 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ 174 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ 175 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ 176 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ 177 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ 178 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ 179 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ 180 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ 181 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ 182 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ 183 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ 184 185 /* MSDC_FIFOCS mask */ 186 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 187 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 188 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ 189 190 /* SDC_CFG mask */ 191 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ 192 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ 193 #define SDC_CFG_WRDTOC (0x1fff << 2) /* RW */ 194 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 195 #define SDC_CFG_SDIO (0x1 << 19) /* RW */ 196 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 197 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ 198 #define SDC_CFG_DTOC (0xff << 24) /* RW */ 199 200 /* SDC_STS mask */ 201 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ 202 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 203 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ 204 205 #define SDC_DAT1_IRQ_TRIGGER (0x1 << 19) /* RW */ 206 /* SDC_ADV_CFG0 mask */ 207 #define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */ 208 209 /* DMA_SA_H4BIT mask */ 210 #define DMA_ADDR_HIGH_4BIT (0xf << 0) /* RW */ 211 212 /* MSDC_DMA_CTRL mask */ 213 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ 214 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ 215 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ 216 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ 217 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ 218 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ 219 220 /* MSDC_DMA_CFG mask */ 221 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ 222 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ 223 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ 224 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ 225 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ 226 227 /* MSDC_PATCH_BIT mask */ 228 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ 229 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) 230 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) 231 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ 232 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ 233 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ 234 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ 235 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ 236 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ 237 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ 238 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ 239 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ 240 241 #define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */ 242 #define MSDC_PB1_BUSY_CHECK_SEL (0x1 << 7) /* RW */ 243 #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ 244 245 #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ 246 #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */ 247 #define MSDC_PB2_SUPPORT_64G (0x1 << 1) /* RW */ 248 #define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */ 249 #define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */ 250 #define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */ 251 252 #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */ 253 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */ 254 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */ 255 #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */ 256 #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */ 257 #define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */ 258 #define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */ 259 #define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */ 260 261 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */ 262 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */ 263 #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */ 264 265 #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */ 266 267 /* EMMC51_CFG0 mask */ 268 #define CMDQ_RDAT_CNT (0x3ff << 12) /* RW */ 269 270 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */ 271 #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ 272 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ 273 #define EMMC50_CFG_CMD_RESP_SEL (0x1 << 9) /* RW */ 274 275 /* EMMC50_CFG1 mask */ 276 #define EMMC50_CFG1_DS_CFG (0x1 << 28) /* RW */ 277 278 #define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */ 279 280 #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */ 281 #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */ 282 283 /* CQHCI_SETTING */ 284 #define CQHCI_RD_CMD_WND_SEL (0x1 << 14) /* RW */ 285 #define CQHCI_WR_CMD_WND_SEL (0x1 << 15) /* RW */ 286 287 /* EMMC_TOP_CONTROL mask */ 288 #define PAD_RXDLY_SEL (0x1 << 0) /* RW */ 289 #define DELAY_EN (0x1 << 1) /* RW */ 290 #define PAD_DAT_RD_RXDLY2 (0x1f << 2) /* RW */ 291 #define PAD_DAT_RD_RXDLY (0x1f << 7) /* RW */ 292 #define PAD_DAT_RD_RXDLY2_SEL (0x1 << 12) /* RW */ 293 #define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */ 294 #define DATA_K_VALUE_SEL (0x1 << 14) /* RW */ 295 #define SDC_RX_ENH_EN (0x1 << 15) /* TW */ 296 297 /* EMMC_TOP_CMD mask */ 298 #define PAD_CMD_RXDLY2 (0x1f << 0) /* RW */ 299 #define PAD_CMD_RXDLY (0x1f << 5) /* RW */ 300 #define PAD_CMD_RD_RXDLY2_SEL (0x1 << 10) /* RW */ 301 #define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */ 302 #define PAD_CMD_TX_DLY (0x1f << 12) /* RW */ 303 304 #define REQ_CMD_EIO (0x1 << 0) 305 #define REQ_CMD_TMO (0x1 << 1) 306 #define REQ_DAT_ERR (0x1 << 2) 307 #define REQ_STOP_EIO (0x1 << 3) 308 #define REQ_STOP_TMO (0x1 << 4) 309 #define REQ_CMD_BUSY (0x1 << 5) 310 311 #define MSDC_PREPARE_FLAG (0x1 << 0) 312 #define MSDC_ASYNC_FLAG (0x1 << 1) 313 #define MSDC_MMAP_FLAG (0x1 << 2) 314 315 #define MTK_MMC_AUTOSUSPEND_DELAY 50 316 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 317 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 318 319 #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */ 320 321 #define PAD_DELAY_MAX 32 /* PAD delay cells */ 322 /*--------------------------------------------------------------------------*/ 323 /* Descriptor Structure */ 324 /*--------------------------------------------------------------------------*/ 325 struct mt_gpdma_desc { 326 u32 gpd_info; 327 #define GPDMA_DESC_HWO (0x1 << 0) 328 #define GPDMA_DESC_BDP (0x1 << 1) 329 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 330 #define GPDMA_DESC_INT (0x1 << 16) 331 #define GPDMA_DESC_NEXT_H4 (0xf << 24) 332 #define GPDMA_DESC_PTR_H4 (0xf << 28) 333 u32 next; 334 u32 ptr; 335 u32 gpd_data_len; 336 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 337 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ 338 u32 arg; 339 u32 blknum; 340 u32 cmd; 341 }; 342 343 struct mt_bdma_desc { 344 u32 bd_info; 345 #define BDMA_DESC_EOL (0x1 << 0) 346 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 347 #define BDMA_DESC_BLKPAD (0x1 << 17) 348 #define BDMA_DESC_DWPAD (0x1 << 18) 349 #define BDMA_DESC_NEXT_H4 (0xf << 24) 350 #define BDMA_DESC_PTR_H4 (0xf << 28) 351 u32 next; 352 u32 ptr; 353 u32 bd_data_len; 354 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 355 #define BDMA_DESC_BUFLEN_EXT (0xffffff) /* bit0 ~ bit23 */ 356 }; 357 358 struct msdc_dma { 359 struct scatterlist *sg; /* I/O scatter list */ 360 struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 361 struct mt_bdma_desc *bd; /* pointer to bd array */ 362 dma_addr_t gpd_addr; /* the physical address of gpd array */ 363 dma_addr_t bd_addr; /* the physical address of bd array */ 364 }; 365 366 struct msdc_save_para { 367 u32 msdc_cfg; 368 u32 iocon; 369 u32 sdc_cfg; 370 u32 pad_tune; 371 u32 patch_bit0; 372 u32 patch_bit1; 373 u32 patch_bit2; 374 u32 pad_ds_tune; 375 u32 pad_cmd_tune; 376 u32 emmc50_cfg0; 377 u32 emmc50_cfg3; 378 u32 sdc_fifo_cfg; 379 u32 emmc_top_control; 380 u32 emmc_top_cmd; 381 u32 emmc50_pad_ds_tune; 382 }; 383 384 struct mtk_mmc_compatible { 385 u8 clk_div_bits; 386 bool recheck_sdio_irq; 387 bool hs400_tune; /* only used for MT8173 */ 388 u32 pad_tune_reg; 389 bool async_fifo; 390 bool data_tune; 391 bool busy_check; 392 bool stop_clk_fix; 393 bool enhance_rx; 394 bool support_64g; 395 bool use_internal_cd; 396 }; 397 398 struct msdc_tune_para { 399 u32 iocon; 400 u32 pad_tune; 401 u32 pad_cmd_tune; 402 u32 emmc_top_control; 403 u32 emmc_top_cmd; 404 }; 405 406 struct msdc_delay_phase { 407 u8 maxlen; 408 u8 start; 409 u8 final_phase; 410 }; 411 412 struct msdc_host { 413 struct device *dev; 414 const struct mtk_mmc_compatible *dev_comp; 415 int cmd_rsp; 416 417 spinlock_t lock; 418 struct mmc_request *mrq; 419 struct mmc_command *cmd; 420 struct mmc_data *data; 421 int error; 422 423 void __iomem *base; /* host base address */ 424 void __iomem *top_base; /* host top register base address */ 425 426 struct msdc_dma dma; /* dma channel */ 427 u64 dma_mask; 428 429 u32 timeout_ns; /* data timeout ns */ 430 u32 timeout_clks; /* data timeout clks */ 431 432 struct pinctrl *pinctrl; 433 struct pinctrl_state *pins_default; 434 struct pinctrl_state *pins_uhs; 435 struct delayed_work req_timeout; 436 int irq; /* host interrupt */ 437 struct reset_control *reset; 438 439 struct clk *src_clk; /* msdc source clock */ 440 struct clk *h_clk; /* msdc h_clk */ 441 struct clk *bus_clk; /* bus clock which used to access register */ 442 struct clk *src_clk_cg; /* msdc source clock control gate */ 443 struct clk *sys_clk_cg; /* msdc subsys clock control gate */ 444 struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS]; 445 u32 mclk; /* mmc subsystem clock frequency */ 446 u32 src_clk_freq; /* source clock frequency */ 447 unsigned char timing; 448 bool vqmmc_enabled; 449 u32 latch_ck; 450 u32 hs400_ds_delay; 451 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 452 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 453 bool hs400_cmd_resp_sel_rising; 454 /* cmd response sample selection for HS400 */ 455 bool hs400_mode; /* current eMMC will run at hs400 mode */ 456 bool internal_cd; /* Use internal card-detect logic */ 457 bool cqhci; /* support eMMC hw cmdq */ 458 struct msdc_save_para save_para; /* used when gate HCLK */ 459 struct msdc_tune_para def_tune_para; /* default tune setting */ 460 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 461 struct cqhci_host *cq_host; 462 }; 463 464 static const struct mtk_mmc_compatible mt8135_compat = { 465 .clk_div_bits = 8, 466 .recheck_sdio_irq = true, 467 .hs400_tune = false, 468 .pad_tune_reg = MSDC_PAD_TUNE, 469 .async_fifo = false, 470 .data_tune = false, 471 .busy_check = false, 472 .stop_clk_fix = false, 473 .enhance_rx = false, 474 .support_64g = false, 475 }; 476 477 static const struct mtk_mmc_compatible mt8173_compat = { 478 .clk_div_bits = 8, 479 .recheck_sdio_irq = true, 480 .hs400_tune = true, 481 .pad_tune_reg = MSDC_PAD_TUNE, 482 .async_fifo = false, 483 .data_tune = false, 484 .busy_check = false, 485 .stop_clk_fix = false, 486 .enhance_rx = false, 487 .support_64g = false, 488 }; 489 490 static const struct mtk_mmc_compatible mt8183_compat = { 491 .clk_div_bits = 12, 492 .recheck_sdio_irq = false, 493 .hs400_tune = false, 494 .pad_tune_reg = MSDC_PAD_TUNE0, 495 .async_fifo = true, 496 .data_tune = true, 497 .busy_check = true, 498 .stop_clk_fix = true, 499 .enhance_rx = true, 500 .support_64g = true, 501 }; 502 503 static const struct mtk_mmc_compatible mt2701_compat = { 504 .clk_div_bits = 12, 505 .recheck_sdio_irq = true, 506 .hs400_tune = false, 507 .pad_tune_reg = MSDC_PAD_TUNE0, 508 .async_fifo = true, 509 .data_tune = true, 510 .busy_check = false, 511 .stop_clk_fix = false, 512 .enhance_rx = false, 513 .support_64g = false, 514 }; 515 516 static const struct mtk_mmc_compatible mt2712_compat = { 517 .clk_div_bits = 12, 518 .recheck_sdio_irq = false, 519 .hs400_tune = false, 520 .pad_tune_reg = MSDC_PAD_TUNE0, 521 .async_fifo = true, 522 .data_tune = true, 523 .busy_check = true, 524 .stop_clk_fix = true, 525 .enhance_rx = true, 526 .support_64g = true, 527 }; 528 529 static const struct mtk_mmc_compatible mt7622_compat = { 530 .clk_div_bits = 12, 531 .recheck_sdio_irq = true, 532 .hs400_tune = false, 533 .pad_tune_reg = MSDC_PAD_TUNE0, 534 .async_fifo = true, 535 .data_tune = true, 536 .busy_check = true, 537 .stop_clk_fix = true, 538 .enhance_rx = true, 539 .support_64g = false, 540 }; 541 542 static const struct mtk_mmc_compatible mt8516_compat = { 543 .clk_div_bits = 12, 544 .recheck_sdio_irq = true, 545 .hs400_tune = false, 546 .pad_tune_reg = MSDC_PAD_TUNE0, 547 .async_fifo = true, 548 .data_tune = true, 549 .busy_check = true, 550 .stop_clk_fix = true, 551 }; 552 553 static const struct mtk_mmc_compatible mt7620_compat = { 554 .clk_div_bits = 8, 555 .recheck_sdio_irq = true, 556 .hs400_tune = false, 557 .pad_tune_reg = MSDC_PAD_TUNE, 558 .async_fifo = false, 559 .data_tune = false, 560 .busy_check = false, 561 .stop_clk_fix = false, 562 .enhance_rx = false, 563 .use_internal_cd = true, 564 }; 565 566 static const struct mtk_mmc_compatible mt6779_compat = { 567 .clk_div_bits = 12, 568 .recheck_sdio_irq = false, 569 .hs400_tune = false, 570 .pad_tune_reg = MSDC_PAD_TUNE0, 571 .async_fifo = true, 572 .data_tune = true, 573 .busy_check = true, 574 .stop_clk_fix = true, 575 .enhance_rx = true, 576 .support_64g = true, 577 }; 578 579 static const struct of_device_id msdc_of_ids[] = { 580 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, 581 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, 582 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, 583 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, 584 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, 585 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, 586 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, 587 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, 588 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, 589 {} 590 }; 591 MODULE_DEVICE_TABLE(of, msdc_of_ids); 592 593 static void sdr_set_bits(void __iomem *reg, u32 bs) 594 { 595 u32 val = readl(reg); 596 597 val |= bs; 598 writel(val, reg); 599 } 600 601 static void sdr_clr_bits(void __iomem *reg, u32 bs) 602 { 603 u32 val = readl(reg); 604 605 val &= ~bs; 606 writel(val, reg); 607 } 608 609 static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 610 { 611 unsigned int tv = readl(reg); 612 613 tv &= ~field; 614 tv |= ((val) << (ffs((unsigned int)field) - 1)); 615 writel(tv, reg); 616 } 617 618 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 619 { 620 unsigned int tv = readl(reg); 621 622 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 623 } 624 625 static void msdc_reset_hw(struct msdc_host *host) 626 { 627 u32 val; 628 629 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 630 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) 631 cpu_relax(); 632 633 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 634 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) 635 cpu_relax(); 636 637 val = readl(host->base + MSDC_INT); 638 writel(val, host->base + MSDC_INT); 639 } 640 641 static void msdc_cmd_next(struct msdc_host *host, 642 struct mmc_request *mrq, struct mmc_command *cmd); 643 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb); 644 645 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 646 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 647 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 648 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 649 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 650 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 651 652 static u8 msdc_dma_calcs(u8 *buf, u32 len) 653 { 654 u32 i, sum = 0; 655 656 for (i = 0; i < len; i++) 657 sum += buf[i]; 658 return 0xff - (u8) sum; 659 } 660 661 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 662 struct mmc_data *data) 663 { 664 unsigned int j, dma_len; 665 dma_addr_t dma_address; 666 u32 dma_ctrl; 667 struct scatterlist *sg; 668 struct mt_gpdma_desc *gpd; 669 struct mt_bdma_desc *bd; 670 671 sg = data->sg; 672 673 gpd = dma->gpd; 674 bd = dma->bd; 675 676 /* modify gpd */ 677 gpd->gpd_info |= GPDMA_DESC_HWO; 678 gpd->gpd_info |= GPDMA_DESC_BDP; 679 /* need to clear first. use these bits to calc checksum */ 680 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 681 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 682 683 /* modify bd */ 684 for_each_sg(data->sg, sg, data->sg_count, j) { 685 dma_address = sg_dma_address(sg); 686 dma_len = sg_dma_len(sg); 687 688 /* init bd */ 689 bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 690 bd[j].bd_info &= ~BDMA_DESC_DWPAD; 691 bd[j].ptr = lower_32_bits(dma_address); 692 if (host->dev_comp->support_64g) { 693 bd[j].bd_info &= ~BDMA_DESC_PTR_H4; 694 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf) 695 << 28; 696 } 697 698 if (host->dev_comp->support_64g) { 699 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT; 700 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT); 701 } else { 702 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 703 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 704 } 705 706 if (j == data->sg_count - 1) /* the last bd */ 707 bd[j].bd_info |= BDMA_DESC_EOL; 708 else 709 bd[j].bd_info &= ~BDMA_DESC_EOL; 710 711 /* checksume need to clear first */ 712 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 713 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 714 } 715 716 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 717 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 718 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 719 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); 720 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 721 if (host->dev_comp->support_64g) 722 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, 723 upper_32_bits(dma->gpd_addr) & 0xf); 724 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); 725 } 726 727 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq) 728 { 729 struct mmc_data *data = mrq->data; 730 731 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 732 data->host_cookie |= MSDC_PREPARE_FLAG; 733 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 734 mmc_get_dma_dir(data)); 735 } 736 } 737 738 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) 739 { 740 struct mmc_data *data = mrq->data; 741 742 if (data->host_cookie & MSDC_ASYNC_FLAG) 743 return; 744 745 if (data->host_cookie & MSDC_PREPARE_FLAG) { 746 dma_unmap_sg(host->dev, data->sg, data->sg_len, 747 mmc_get_dma_dir(data)); 748 data->host_cookie &= ~MSDC_PREPARE_FLAG; 749 } 750 } 751 752 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) 753 { 754 struct mmc_host *mmc = mmc_from_priv(host); 755 u64 timeout, clk_ns; 756 u32 mode = 0; 757 758 if (mmc->actual_clock == 0) { 759 timeout = 0; 760 } else { 761 clk_ns = 1000000000ULL; 762 do_div(clk_ns, mmc->actual_clock); 763 timeout = ns + clk_ns - 1; 764 do_div(timeout, clk_ns); 765 timeout += clks; 766 /* in 1048576 sclk cycle unit */ 767 timeout = DIV_ROUND_UP(timeout, (0x1 << 20)); 768 if (host->dev_comp->clk_div_bits == 8) 769 sdr_get_field(host->base + MSDC_CFG, 770 MSDC_CFG_CKMOD, &mode); 771 else 772 sdr_get_field(host->base + MSDC_CFG, 773 MSDC_CFG_CKMOD_EXTRA, &mode); 774 /*DDR mode will double the clk cycles for data timeout */ 775 timeout = mode >= 2 ? timeout * 2 : timeout; 776 timeout = timeout > 1 ? timeout - 1 : 0; 777 } 778 return timeout; 779 } 780 781 /* clock control primitives */ 782 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) 783 { 784 u64 timeout; 785 786 host->timeout_ns = ns; 787 host->timeout_clks = clks; 788 789 timeout = msdc_timeout_cal(host, ns, clks); 790 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 791 (u32)(timeout > 255 ? 255 : timeout)); 792 } 793 794 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) 795 { 796 u64 timeout; 797 798 timeout = msdc_timeout_cal(host, ns, clks); 799 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, 800 (u32)(timeout > 8191 ? 8191 : timeout)); 801 } 802 803 static void msdc_gate_clock(struct msdc_host *host) 804 { 805 clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); 806 clk_disable_unprepare(host->src_clk_cg); 807 clk_disable_unprepare(host->src_clk); 808 clk_disable_unprepare(host->bus_clk); 809 clk_disable_unprepare(host->h_clk); 810 } 811 812 static void msdc_ungate_clock(struct msdc_host *host) 813 { 814 int ret; 815 816 clk_prepare_enable(host->h_clk); 817 clk_prepare_enable(host->bus_clk); 818 clk_prepare_enable(host->src_clk); 819 clk_prepare_enable(host->src_clk_cg); 820 ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); 821 if (ret) { 822 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); 823 return; 824 } 825 826 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 827 cpu_relax(); 828 } 829 830 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 831 { 832 struct mmc_host *mmc = mmc_from_priv(host); 833 u32 mode; 834 u32 flags; 835 u32 div; 836 u32 sclk; 837 u32 tune_reg = host->dev_comp->pad_tune_reg; 838 839 if (!hz) { 840 dev_dbg(host->dev, "set mclk to 0\n"); 841 host->mclk = 0; 842 mmc->actual_clock = 0; 843 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 844 return; 845 } 846 847 flags = readl(host->base + MSDC_INTEN); 848 sdr_clr_bits(host->base + MSDC_INTEN, flags); 849 if (host->dev_comp->clk_div_bits == 8) 850 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 851 else 852 sdr_clr_bits(host->base + MSDC_CFG, 853 MSDC_CFG_HS400_CK_MODE_EXTRA); 854 if (timing == MMC_TIMING_UHS_DDR50 || 855 timing == MMC_TIMING_MMC_DDR52 || 856 timing == MMC_TIMING_MMC_HS400) { 857 if (timing == MMC_TIMING_MMC_HS400) 858 mode = 0x3; 859 else 860 mode = 0x2; /* ddr mode and use divisor */ 861 862 if (hz >= (host->src_clk_freq >> 2)) { 863 div = 0; /* mean div = 1/4 */ 864 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 865 } else { 866 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 867 sclk = (host->src_clk_freq >> 2) / div; 868 div = (div >> 1); 869 } 870 871 if (timing == MMC_TIMING_MMC_HS400 && 872 hz >= (host->src_clk_freq >> 1)) { 873 if (host->dev_comp->clk_div_bits == 8) 874 sdr_set_bits(host->base + MSDC_CFG, 875 MSDC_CFG_HS400_CK_MODE); 876 else 877 sdr_set_bits(host->base + MSDC_CFG, 878 MSDC_CFG_HS400_CK_MODE_EXTRA); 879 sclk = host->src_clk_freq >> 1; 880 div = 0; /* div is ignore when bit18 is set */ 881 } 882 } else if (hz >= host->src_clk_freq) { 883 mode = 0x1; /* no divisor */ 884 div = 0; 885 sclk = host->src_clk_freq; 886 } else { 887 mode = 0x0; /* use divisor */ 888 if (hz >= (host->src_clk_freq >> 1)) { 889 div = 0; /* mean div = 1/2 */ 890 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 891 } else { 892 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 893 sclk = (host->src_clk_freq >> 2) / div; 894 } 895 } 896 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 897 /* 898 * As src_clk/HCLK use the same bit to gate/ungate, 899 * So if want to only gate src_clk, need gate its parent(mux). 900 */ 901 if (host->src_clk_cg) 902 clk_disable_unprepare(host->src_clk_cg); 903 else 904 clk_disable_unprepare(clk_get_parent(host->src_clk)); 905 if (host->dev_comp->clk_div_bits == 8) 906 sdr_set_field(host->base + MSDC_CFG, 907 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 908 (mode << 8) | div); 909 else 910 sdr_set_field(host->base + MSDC_CFG, 911 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, 912 (mode << 12) | div); 913 if (host->src_clk_cg) 914 clk_prepare_enable(host->src_clk_cg); 915 else 916 clk_prepare_enable(clk_get_parent(host->src_clk)); 917 918 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 919 cpu_relax(); 920 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 921 mmc->actual_clock = sclk; 922 host->mclk = hz; 923 host->timing = timing; 924 /* need because clk changed. */ 925 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 926 sdr_set_bits(host->base + MSDC_INTEN, flags); 927 928 /* 929 * mmc_select_hs400() will drop to 50Mhz and High speed mode, 930 * tune result of hs200/200Mhz is not suitable for 50Mhz 931 */ 932 if (mmc->actual_clock <= 52000000) { 933 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 934 if (host->top_base) { 935 writel(host->def_tune_para.emmc_top_control, 936 host->top_base + EMMC_TOP_CONTROL); 937 writel(host->def_tune_para.emmc_top_cmd, 938 host->top_base + EMMC_TOP_CMD); 939 } else { 940 writel(host->def_tune_para.pad_tune, 941 host->base + tune_reg); 942 } 943 } else { 944 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 945 writel(host->saved_tune_para.pad_cmd_tune, 946 host->base + PAD_CMD_TUNE); 947 if (host->top_base) { 948 writel(host->saved_tune_para.emmc_top_control, 949 host->top_base + EMMC_TOP_CONTROL); 950 writel(host->saved_tune_para.emmc_top_cmd, 951 host->top_base + EMMC_TOP_CMD); 952 } else { 953 writel(host->saved_tune_para.pad_tune, 954 host->base + tune_reg); 955 } 956 } 957 958 if (timing == MMC_TIMING_MMC_HS400 && 959 host->dev_comp->hs400_tune) 960 sdr_set_field(host->base + tune_reg, 961 MSDC_PAD_TUNE_CMDRRDLY, 962 host->hs400_cmd_int_delay); 963 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock, 964 timing); 965 } 966 967 static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 968 struct mmc_request *mrq, struct mmc_command *cmd) 969 { 970 u32 resp; 971 972 switch (mmc_resp_type(cmd)) { 973 /* Actually, R1, R5, R6, R7 are the same */ 974 case MMC_RSP_R1: 975 resp = 0x1; 976 break; 977 case MMC_RSP_R1B: 978 resp = 0x7; 979 break; 980 case MMC_RSP_R2: 981 resp = 0x2; 982 break; 983 case MMC_RSP_R3: 984 resp = 0x3; 985 break; 986 case MMC_RSP_NONE: 987 default: 988 resp = 0x0; 989 break; 990 } 991 992 return resp; 993 } 994 995 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 996 struct mmc_request *mrq, struct mmc_command *cmd) 997 { 998 struct mmc_host *mmc = mmc_from_priv(host); 999 /* rawcmd : 1000 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 1001 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 1002 */ 1003 u32 opcode = cmd->opcode; 1004 u32 resp = msdc_cmd_find_resp(host, mrq, cmd); 1005 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 1006 1007 host->cmd_rsp = resp; 1008 1009 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 1010 opcode == MMC_STOP_TRANSMISSION) 1011 rawcmd |= (0x1 << 14); 1012 else if (opcode == SD_SWITCH_VOLTAGE) 1013 rawcmd |= (0x1 << 30); 1014 else if (opcode == SD_APP_SEND_SCR || 1015 opcode == SD_APP_SEND_NUM_WR_BLKS || 1016 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 1017 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 1018 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 1019 rawcmd |= (0x1 << 11); 1020 1021 if (cmd->data) { 1022 struct mmc_data *data = cmd->data; 1023 1024 if (mmc_op_multi(opcode)) { 1025 if (mmc_card_mmc(mmc->card) && mrq->sbc && 1026 !(mrq->sbc->arg & 0xFFFF0000)) 1027 rawcmd |= 0x2 << 28; /* AutoCMD23 */ 1028 } 1029 1030 rawcmd |= ((data->blksz & 0xFFF) << 16); 1031 if (data->flags & MMC_DATA_WRITE) 1032 rawcmd |= (0x1 << 13); 1033 if (data->blocks > 1) 1034 rawcmd |= (0x2 << 11); 1035 else 1036 rawcmd |= (0x1 << 11); 1037 /* Always use dma mode */ 1038 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 1039 1040 if (host->timeout_ns != data->timeout_ns || 1041 host->timeout_clks != data->timeout_clks) 1042 msdc_set_timeout(host, data->timeout_ns, 1043 data->timeout_clks); 1044 1045 writel(data->blocks, host->base + SDC_BLK_NUM); 1046 } 1047 return rawcmd; 1048 } 1049 1050 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, 1051 struct mmc_command *cmd, struct mmc_data *data) 1052 { 1053 bool read; 1054 1055 WARN_ON(host->data); 1056 host->data = data; 1057 read = data->flags & MMC_DATA_READ; 1058 1059 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1060 msdc_dma_setup(host, &host->dma, data); 1061 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 1062 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 1063 dev_dbg(host->dev, "DMA start\n"); 1064 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 1065 __func__, cmd->opcode, data->blocks, read); 1066 } 1067 1068 static int msdc_auto_cmd_done(struct msdc_host *host, int events, 1069 struct mmc_command *cmd) 1070 { 1071 u32 *rsp = cmd->resp; 1072 1073 rsp[0] = readl(host->base + SDC_ACMD_RESP); 1074 1075 if (events & MSDC_INT_ACMDRDY) { 1076 cmd->error = 0; 1077 } else { 1078 msdc_reset_hw(host); 1079 if (events & MSDC_INT_ACMDCRCERR) { 1080 cmd->error = -EILSEQ; 1081 host->error |= REQ_STOP_EIO; 1082 } else if (events & MSDC_INT_ACMDTMO) { 1083 cmd->error = -ETIMEDOUT; 1084 host->error |= REQ_STOP_TMO; 1085 } 1086 dev_err(host->dev, 1087 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 1088 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 1089 } 1090 return cmd->error; 1091 } 1092 1093 /* 1094 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost 1095 * 1096 * Host controller may lost interrupt in some special case. 1097 * Add SDIO irq recheck mechanism to make sure all interrupts 1098 * can be processed immediately 1099 */ 1100 static void msdc_recheck_sdio_irq(struct msdc_host *host) 1101 { 1102 struct mmc_host *mmc = mmc_from_priv(host); 1103 u32 reg_int, reg_inten, reg_ps; 1104 1105 if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1106 reg_inten = readl(host->base + MSDC_INTEN); 1107 if (reg_inten & MSDC_INTEN_SDIOIRQ) { 1108 reg_int = readl(host->base + MSDC_INT); 1109 reg_ps = readl(host->base + MSDC_PS); 1110 if (!(reg_int & MSDC_INT_SDIOIRQ || 1111 reg_ps & MSDC_PS_DATA1)) { 1112 __msdc_enable_sdio_irq(host, 0); 1113 sdio_signal_irq(mmc); 1114 } 1115 } 1116 } 1117 } 1118 1119 static void msdc_track_cmd_data(struct msdc_host *host, 1120 struct mmc_command *cmd, struct mmc_data *data) 1121 { 1122 if (host->error) 1123 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 1124 __func__, cmd->opcode, cmd->arg, host->error); 1125 } 1126 1127 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 1128 { 1129 unsigned long flags; 1130 bool ret; 1131 1132 ret = cancel_delayed_work(&host->req_timeout); 1133 if (!ret) { 1134 /* delay work already running */ 1135 return; 1136 } 1137 spin_lock_irqsave(&host->lock, flags); 1138 host->mrq = NULL; 1139 spin_unlock_irqrestore(&host->lock, flags); 1140 1141 msdc_track_cmd_data(host, mrq->cmd, mrq->data); 1142 if (mrq->data) 1143 msdc_unprepare_data(host, mrq); 1144 if (host->error) 1145 msdc_reset_hw(host); 1146 mmc_request_done(mmc_from_priv(host), mrq); 1147 if (host->dev_comp->recheck_sdio_irq) 1148 msdc_recheck_sdio_irq(host); 1149 } 1150 1151 /* returns true if command is fully handled; returns false otherwise */ 1152 static bool msdc_cmd_done(struct msdc_host *host, int events, 1153 struct mmc_request *mrq, struct mmc_command *cmd) 1154 { 1155 bool done = false; 1156 bool sbc_error; 1157 unsigned long flags; 1158 u32 *rsp = cmd->resp; 1159 1160 if (mrq->sbc && cmd == mrq->cmd && 1161 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 1162 | MSDC_INT_ACMDTMO))) 1163 msdc_auto_cmd_done(host, events, mrq->sbc); 1164 1165 sbc_error = mrq->sbc && mrq->sbc->error; 1166 1167 if (!sbc_error && !(events & (MSDC_INT_CMDRDY 1168 | MSDC_INT_RSPCRCERR 1169 | MSDC_INT_CMDTMO))) 1170 return done; 1171 1172 spin_lock_irqsave(&host->lock, flags); 1173 done = !host->cmd; 1174 host->cmd = NULL; 1175 spin_unlock_irqrestore(&host->lock, flags); 1176 1177 if (done) 1178 return true; 1179 1180 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1181 1182 if (cmd->flags & MMC_RSP_PRESENT) { 1183 if (cmd->flags & MMC_RSP_136) { 1184 rsp[0] = readl(host->base + SDC_RESP3); 1185 rsp[1] = readl(host->base + SDC_RESP2); 1186 rsp[2] = readl(host->base + SDC_RESP1); 1187 rsp[3] = readl(host->base + SDC_RESP0); 1188 } else { 1189 rsp[0] = readl(host->base + SDC_RESP0); 1190 } 1191 } 1192 1193 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 1194 if (events & MSDC_INT_CMDTMO || 1195 (cmd->opcode != MMC_SEND_TUNING_BLOCK && 1196 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)) 1197 /* 1198 * should not clear fifo/interrupt as the tune data 1199 * may have alreay come when cmd19/cmd21 gets response 1200 * CRC error. 1201 */ 1202 msdc_reset_hw(host); 1203 if (events & MSDC_INT_RSPCRCERR) { 1204 cmd->error = -EILSEQ; 1205 host->error |= REQ_CMD_EIO; 1206 } else if (events & MSDC_INT_CMDTMO) { 1207 cmd->error = -ETIMEDOUT; 1208 host->error |= REQ_CMD_TMO; 1209 } 1210 } 1211 if (cmd->error) 1212 dev_dbg(host->dev, 1213 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 1214 __func__, cmd->opcode, cmd->arg, rsp[0], 1215 cmd->error); 1216 1217 msdc_cmd_next(host, mrq, cmd); 1218 return true; 1219 } 1220 1221 /* It is the core layer's responsibility to ensure card status 1222 * is correct before issue a request. but host design do below 1223 * checks recommended. 1224 */ 1225 static inline bool msdc_cmd_is_ready(struct msdc_host *host, 1226 struct mmc_request *mrq, struct mmc_command *cmd) 1227 { 1228 /* The max busy time we can endure is 20ms */ 1229 unsigned long tmo = jiffies + msecs_to_jiffies(20); 1230 1231 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && 1232 time_before(jiffies, tmo)) 1233 cpu_relax(); 1234 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { 1235 dev_err(host->dev, "CMD bus busy detected\n"); 1236 host->error |= REQ_CMD_BUSY; 1237 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1238 return false; 1239 } 1240 1241 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 1242 tmo = jiffies + msecs_to_jiffies(20); 1243 /* R1B or with data, should check SDCBUSY */ 1244 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && 1245 time_before(jiffies, tmo)) 1246 cpu_relax(); 1247 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { 1248 dev_err(host->dev, "Controller busy detected\n"); 1249 host->error |= REQ_CMD_BUSY; 1250 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1251 return false; 1252 } 1253 } 1254 return true; 1255 } 1256 1257 static void msdc_start_command(struct msdc_host *host, 1258 struct mmc_request *mrq, struct mmc_command *cmd) 1259 { 1260 u32 rawcmd; 1261 unsigned long flags; 1262 1263 WARN_ON(host->cmd); 1264 host->cmd = cmd; 1265 1266 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1267 if (!msdc_cmd_is_ready(host, mrq, cmd)) 1268 return; 1269 1270 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 1271 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 1272 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 1273 msdc_reset_hw(host); 1274 } 1275 1276 cmd->error = 0; 1277 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 1278 1279 spin_lock_irqsave(&host->lock, flags); 1280 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1281 spin_unlock_irqrestore(&host->lock, flags); 1282 1283 writel(cmd->arg, host->base + SDC_ARG); 1284 writel(rawcmd, host->base + SDC_CMD); 1285 } 1286 1287 static void msdc_cmd_next(struct msdc_host *host, 1288 struct mmc_request *mrq, struct mmc_command *cmd) 1289 { 1290 if ((cmd->error && 1291 !(cmd->error == -EILSEQ && 1292 (cmd->opcode == MMC_SEND_TUNING_BLOCK || 1293 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) || 1294 (mrq->sbc && mrq->sbc->error)) 1295 msdc_request_done(host, mrq); 1296 else if (cmd == mrq->sbc) 1297 msdc_start_command(host, mrq, mrq->cmd); 1298 else if (!cmd->data) 1299 msdc_request_done(host, mrq); 1300 else 1301 msdc_start_data(host, mrq, cmd, cmd->data); 1302 } 1303 1304 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 1305 { 1306 struct msdc_host *host = mmc_priv(mmc); 1307 1308 host->error = 0; 1309 WARN_ON(host->mrq); 1310 host->mrq = mrq; 1311 1312 if (mrq->data) 1313 msdc_prepare_data(host, mrq); 1314 1315 /* if SBC is required, we have HW option and SW option. 1316 * if HW option is enabled, and SBC does not have "special" flags, 1317 * use HW option, otherwise use SW option 1318 */ 1319 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 1320 (mrq->sbc->arg & 0xFFFF0000))) 1321 msdc_start_command(host, mrq, mrq->sbc); 1322 else 1323 msdc_start_command(host, mrq, mrq->cmd); 1324 } 1325 1326 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 1327 { 1328 struct msdc_host *host = mmc_priv(mmc); 1329 struct mmc_data *data = mrq->data; 1330 1331 if (!data) 1332 return; 1333 1334 msdc_prepare_data(host, mrq); 1335 data->host_cookie |= MSDC_ASYNC_FLAG; 1336 } 1337 1338 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1339 int err) 1340 { 1341 struct msdc_host *host = mmc_priv(mmc); 1342 struct mmc_data *data; 1343 1344 data = mrq->data; 1345 if (!data) 1346 return; 1347 if (data->host_cookie) { 1348 data->host_cookie &= ~MSDC_ASYNC_FLAG; 1349 msdc_unprepare_data(host, mrq); 1350 } 1351 } 1352 1353 static void msdc_data_xfer_next(struct msdc_host *host, 1354 struct mmc_request *mrq, struct mmc_data *data) 1355 { 1356 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 1357 !mrq->sbc) 1358 msdc_start_command(host, mrq, mrq->stop); 1359 else 1360 msdc_request_done(host, mrq); 1361 } 1362 1363 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 1364 struct mmc_request *mrq, struct mmc_data *data) 1365 { 1366 struct mmc_command *stop = data->stop; 1367 unsigned long flags; 1368 bool done; 1369 unsigned int check_data = events & 1370 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 1371 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 1372 | MSDC_INT_DMA_PROTECT); 1373 1374 spin_lock_irqsave(&host->lock, flags); 1375 done = !host->data; 1376 if (check_data) 1377 host->data = NULL; 1378 spin_unlock_irqrestore(&host->lock, flags); 1379 1380 if (done) 1381 return true; 1382 1383 if (check_data || (stop && stop->error)) { 1384 dev_dbg(host->dev, "DMA status: 0x%8X\n", 1385 readl(host->base + MSDC_DMA_CFG)); 1386 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1387 1); 1388 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) 1389 cpu_relax(); 1390 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 1391 dev_dbg(host->dev, "DMA stop\n"); 1392 1393 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 1394 data->bytes_xfered = data->blocks * data->blksz; 1395 } else { 1396 dev_dbg(host->dev, "interrupt events: %x\n", events); 1397 msdc_reset_hw(host); 1398 host->error |= REQ_DAT_ERR; 1399 data->bytes_xfered = 0; 1400 1401 if (events & MSDC_INT_DATTMO) 1402 data->error = -ETIMEDOUT; 1403 else if (events & MSDC_INT_DATCRCERR) 1404 data->error = -EILSEQ; 1405 1406 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 1407 __func__, mrq->cmd->opcode, data->blocks); 1408 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 1409 (int)data->error, data->bytes_xfered); 1410 } 1411 1412 msdc_data_xfer_next(host, mrq, data); 1413 done = true; 1414 } 1415 return done; 1416 } 1417 1418 static void msdc_set_buswidth(struct msdc_host *host, u32 width) 1419 { 1420 u32 val = readl(host->base + SDC_CFG); 1421 1422 val &= ~SDC_CFG_BUSWIDTH; 1423 1424 switch (width) { 1425 default: 1426 case MMC_BUS_WIDTH_1: 1427 val |= (MSDC_BUS_1BITS << 16); 1428 break; 1429 case MMC_BUS_WIDTH_4: 1430 val |= (MSDC_BUS_4BITS << 16); 1431 break; 1432 case MMC_BUS_WIDTH_8: 1433 val |= (MSDC_BUS_8BITS << 16); 1434 break; 1435 } 1436 1437 writel(val, host->base + SDC_CFG); 1438 dev_dbg(host->dev, "Bus Width = %d", width); 1439 } 1440 1441 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 1442 { 1443 struct msdc_host *host = mmc_priv(mmc); 1444 int ret; 1445 1446 if (!IS_ERR(mmc->supply.vqmmc)) { 1447 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1448 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 1449 dev_err(host->dev, "Unsupported signal voltage!\n"); 1450 return -EINVAL; 1451 } 1452 1453 ret = mmc_regulator_set_vqmmc(mmc, ios); 1454 if (ret < 0) { 1455 dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1456 ret, ios->signal_voltage); 1457 return ret; 1458 } 1459 1460 /* Apply different pinctrl settings for different signal voltage */ 1461 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 1462 pinctrl_select_state(host->pinctrl, host->pins_uhs); 1463 else 1464 pinctrl_select_state(host->pinctrl, host->pins_default); 1465 } 1466 return 0; 1467 } 1468 1469 static int msdc_card_busy(struct mmc_host *mmc) 1470 { 1471 struct msdc_host *host = mmc_priv(mmc); 1472 u32 status = readl(host->base + MSDC_PS); 1473 1474 /* only check if data0 is low */ 1475 return !(status & BIT(16)); 1476 } 1477 1478 static void msdc_request_timeout(struct work_struct *work) 1479 { 1480 struct msdc_host *host = container_of(work, struct msdc_host, 1481 req_timeout.work); 1482 1483 /* simulate HW timeout status */ 1484 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 1485 if (host->mrq) { 1486 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 1487 host->mrq, host->mrq->cmd->opcode); 1488 if (host->cmd) { 1489 dev_err(host->dev, "%s: aborting cmd=%d\n", 1490 __func__, host->cmd->opcode); 1491 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 1492 host->cmd); 1493 } else if (host->data) { 1494 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 1495 __func__, host->mrq->cmd->opcode, 1496 host->data->blocks); 1497 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 1498 host->data); 1499 } 1500 } 1501 } 1502 1503 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb) 1504 { 1505 if (enb) { 1506 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1507 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1508 if (host->dev_comp->recheck_sdio_irq) 1509 msdc_recheck_sdio_irq(host); 1510 } else { 1511 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1512 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1513 } 1514 } 1515 1516 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) 1517 { 1518 unsigned long flags; 1519 struct msdc_host *host = mmc_priv(mmc); 1520 1521 spin_lock_irqsave(&host->lock, flags); 1522 __msdc_enable_sdio_irq(host, enb); 1523 spin_unlock_irqrestore(&host->lock, flags); 1524 1525 if (enb) 1526 pm_runtime_get_noresume(host->dev); 1527 else 1528 pm_runtime_put_noidle(host->dev); 1529 } 1530 1531 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) 1532 { 1533 struct mmc_host *mmc = mmc_from_priv(host); 1534 int cmd_err = 0, dat_err = 0; 1535 1536 if (intsts & MSDC_INT_RSPCRCERR) { 1537 cmd_err = -EILSEQ; 1538 dev_err(host->dev, "%s: CMD CRC ERR", __func__); 1539 } else if (intsts & MSDC_INT_CMDTMO) { 1540 cmd_err = -ETIMEDOUT; 1541 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); 1542 } 1543 1544 if (intsts & MSDC_INT_DATCRCERR) { 1545 dat_err = -EILSEQ; 1546 dev_err(host->dev, "%s: DATA CRC ERR", __func__); 1547 } else if (intsts & MSDC_INT_DATTMO) { 1548 dat_err = -ETIMEDOUT; 1549 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); 1550 } 1551 1552 if (cmd_err || dat_err) { 1553 dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", 1554 cmd_err, dat_err, intsts); 1555 } 1556 1557 return cqhci_irq(mmc, 0, cmd_err, dat_err); 1558 } 1559 1560 static irqreturn_t msdc_irq(int irq, void *dev_id) 1561 { 1562 struct msdc_host *host = (struct msdc_host *) dev_id; 1563 struct mmc_host *mmc = mmc_from_priv(host); 1564 1565 while (true) { 1566 struct mmc_request *mrq; 1567 struct mmc_command *cmd; 1568 struct mmc_data *data; 1569 u32 events, event_mask; 1570 1571 spin_lock(&host->lock); 1572 events = readl(host->base + MSDC_INT); 1573 event_mask = readl(host->base + MSDC_INTEN); 1574 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1575 __msdc_enable_sdio_irq(host, 0); 1576 /* clear interrupts */ 1577 writel(events & event_mask, host->base + MSDC_INT); 1578 1579 mrq = host->mrq; 1580 cmd = host->cmd; 1581 data = host->data; 1582 spin_unlock(&host->lock); 1583 1584 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1585 sdio_signal_irq(mmc); 1586 1587 if ((events & event_mask) & MSDC_INT_CDSC) { 1588 if (host->internal_cd) 1589 mmc_detect_change(mmc, msecs_to_jiffies(20)); 1590 events &= ~MSDC_INT_CDSC; 1591 } 1592 1593 if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) 1594 break; 1595 1596 if ((mmc->caps2 & MMC_CAP2_CQE) && 1597 (events & MSDC_INT_CMDQ)) { 1598 msdc_cmdq_irq(host, events); 1599 /* clear interrupts */ 1600 writel(events, host->base + MSDC_INT); 1601 return IRQ_HANDLED; 1602 } 1603 1604 if (!mrq) { 1605 dev_err(host->dev, 1606 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 1607 __func__, events, event_mask); 1608 WARN_ON(1); 1609 break; 1610 } 1611 1612 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 1613 1614 if (cmd) 1615 msdc_cmd_done(host, events, mrq, cmd); 1616 else if (data) 1617 msdc_data_xfer_done(host, events, mrq, data); 1618 } 1619 1620 return IRQ_HANDLED; 1621 } 1622 1623 static void msdc_init_hw(struct msdc_host *host) 1624 { 1625 u32 val; 1626 u32 tune_reg = host->dev_comp->pad_tune_reg; 1627 1628 if (host->reset) { 1629 reset_control_assert(host->reset); 1630 usleep_range(10, 50); 1631 reset_control_deassert(host->reset); 1632 } 1633 1634 /* Configure to MMC/SD mode, clock free running */ 1635 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 1636 1637 /* Reset */ 1638 msdc_reset_hw(host); 1639 1640 /* Disable and clear all interrupts */ 1641 writel(0, host->base + MSDC_INTEN); 1642 val = readl(host->base + MSDC_INT); 1643 writel(val, host->base + MSDC_INT); 1644 1645 /* Configure card detection */ 1646 if (host->internal_cd) { 1647 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, 1648 DEFAULT_DEBOUNCE); 1649 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1650 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1651 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1652 } else { 1653 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1654 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1655 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1656 } 1657 1658 if (host->top_base) { 1659 writel(0, host->top_base + EMMC_TOP_CONTROL); 1660 writel(0, host->top_base + EMMC_TOP_CMD); 1661 } else { 1662 writel(0, host->base + tune_reg); 1663 } 1664 writel(0, host->base + MSDC_IOCON); 1665 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 1666 writel(0x403c0046, host->base + MSDC_PATCH_BIT); 1667 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 1668 writel(0xffff4089, host->base + MSDC_PATCH_BIT1); 1669 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1670 1671 if (host->dev_comp->stop_clk_fix) { 1672 sdr_set_field(host->base + MSDC_PATCH_BIT1, 1673 MSDC_PATCH_BIT1_STOP_DLY, 3); 1674 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1675 SDC_FIFO_CFG_WRVALIDSEL); 1676 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1677 SDC_FIFO_CFG_RDVALIDSEL); 1678 } 1679 1680 if (host->dev_comp->busy_check) 1681 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7)); 1682 1683 if (host->dev_comp->async_fifo) { 1684 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1685 MSDC_PB2_RESPWAIT, 3); 1686 if (host->dev_comp->enhance_rx) { 1687 if (host->top_base) 1688 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1689 SDC_RX_ENH_EN); 1690 else 1691 sdr_set_bits(host->base + SDC_ADV_CFG0, 1692 SDC_RX_ENHANCE_EN); 1693 } else { 1694 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1695 MSDC_PB2_RESPSTSENSEL, 2); 1696 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1697 MSDC_PB2_CRCSTSENSEL, 2); 1698 } 1699 /* use async fifo, then no need tune internal delay */ 1700 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, 1701 MSDC_PATCH_BIT2_CFGRESP); 1702 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1703 MSDC_PATCH_BIT2_CFGCRCSTS); 1704 } 1705 1706 if (host->dev_comp->support_64g) 1707 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1708 MSDC_PB2_SUPPORT_64G); 1709 if (host->dev_comp->data_tune) { 1710 if (host->top_base) { 1711 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1712 PAD_DAT_RD_RXDLY_SEL); 1713 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, 1714 DATA_K_VALUE_SEL); 1715 sdr_set_bits(host->top_base + EMMC_TOP_CMD, 1716 PAD_CMD_RD_RXDLY_SEL); 1717 } else { 1718 sdr_set_bits(host->base + tune_reg, 1719 MSDC_PAD_TUNE_RD_SEL | 1720 MSDC_PAD_TUNE_CMD_SEL); 1721 } 1722 } else { 1723 /* choose clock tune */ 1724 if (host->top_base) 1725 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1726 PAD_RXDLY_SEL); 1727 else 1728 sdr_set_bits(host->base + tune_reg, 1729 MSDC_PAD_TUNE_RXDLYSEL); 1730 } 1731 1732 /* Configure to enable SDIO mode. 1733 * it's must otherwise sdio cmd5 failed 1734 */ 1735 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1736 1737 /* Config SDIO device detect interrupt function */ 1738 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1739 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 1740 1741 /* Configure to default data timeout */ 1742 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 1743 1744 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 1745 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1746 if (host->top_base) { 1747 host->def_tune_para.emmc_top_control = 1748 readl(host->top_base + EMMC_TOP_CONTROL); 1749 host->def_tune_para.emmc_top_cmd = 1750 readl(host->top_base + EMMC_TOP_CMD); 1751 host->saved_tune_para.emmc_top_control = 1752 readl(host->top_base + EMMC_TOP_CONTROL); 1753 host->saved_tune_para.emmc_top_cmd = 1754 readl(host->top_base + EMMC_TOP_CMD); 1755 } else { 1756 host->def_tune_para.pad_tune = readl(host->base + tune_reg); 1757 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 1758 } 1759 dev_dbg(host->dev, "init hardware done!"); 1760 } 1761 1762 static void msdc_deinit_hw(struct msdc_host *host) 1763 { 1764 u32 val; 1765 1766 if (host->internal_cd) { 1767 /* Disabled card-detect */ 1768 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1769 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1770 } 1771 1772 /* Disable and clear all interrupts */ 1773 writel(0, host->base + MSDC_INTEN); 1774 1775 val = readl(host->base + MSDC_INT); 1776 writel(val, host->base + MSDC_INT); 1777 } 1778 1779 /* init gpd and bd list in msdc_drv_probe */ 1780 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 1781 { 1782 struct mt_gpdma_desc *gpd = dma->gpd; 1783 struct mt_bdma_desc *bd = dma->bd; 1784 dma_addr_t dma_addr; 1785 int i; 1786 1787 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 1788 1789 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); 1790 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 1791 /* gpd->next is must set for desc DMA 1792 * That's why must alloc 2 gpd structure. 1793 */ 1794 gpd->next = lower_32_bits(dma_addr); 1795 if (host->dev_comp->support_64g) 1796 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1797 1798 dma_addr = dma->bd_addr; 1799 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ 1800 if (host->dev_comp->support_64g) 1801 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; 1802 1803 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 1804 for (i = 0; i < (MAX_BD_NUM - 1); i++) { 1805 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); 1806 bd[i].next = lower_32_bits(dma_addr); 1807 if (host->dev_comp->support_64g) 1808 bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1809 } 1810 } 1811 1812 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1813 { 1814 struct msdc_host *host = mmc_priv(mmc); 1815 int ret; 1816 1817 msdc_set_buswidth(host, ios->bus_width); 1818 1819 /* Suspend/Resume will do power off/on */ 1820 switch (ios->power_mode) { 1821 case MMC_POWER_UP: 1822 if (!IS_ERR(mmc->supply.vmmc)) { 1823 msdc_init_hw(host); 1824 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1825 ios->vdd); 1826 if (ret) { 1827 dev_err(host->dev, "Failed to set vmmc power!\n"); 1828 return; 1829 } 1830 } 1831 break; 1832 case MMC_POWER_ON: 1833 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1834 ret = regulator_enable(mmc->supply.vqmmc); 1835 if (ret) 1836 dev_err(host->dev, "Failed to set vqmmc power!\n"); 1837 else 1838 host->vqmmc_enabled = true; 1839 } 1840 break; 1841 case MMC_POWER_OFF: 1842 if (!IS_ERR(mmc->supply.vmmc)) 1843 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1844 1845 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1846 regulator_disable(mmc->supply.vqmmc); 1847 host->vqmmc_enabled = false; 1848 } 1849 break; 1850 default: 1851 break; 1852 } 1853 1854 if (host->mclk != ios->clock || host->timing != ios->timing) 1855 msdc_set_mclk(host, ios->timing, ios->clock); 1856 } 1857 1858 static u32 test_delay_bit(u32 delay, u32 bit) 1859 { 1860 bit %= PAD_DELAY_MAX; 1861 return delay & (1 << bit); 1862 } 1863 1864 static int get_delay_len(u32 delay, u32 start_bit) 1865 { 1866 int i; 1867 1868 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 1869 if (test_delay_bit(delay, start_bit + i) == 0) 1870 return i; 1871 } 1872 return PAD_DELAY_MAX - start_bit; 1873 } 1874 1875 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 1876 { 1877 int start = 0, len = 0; 1878 int start_final = 0, len_final = 0; 1879 u8 final_phase = 0xff; 1880 struct msdc_delay_phase delay_phase = { 0, }; 1881 1882 if (delay == 0) { 1883 dev_err(host->dev, "phase error: [map:%x]\n", delay); 1884 delay_phase.final_phase = final_phase; 1885 return delay_phase; 1886 } 1887 1888 while (start < PAD_DELAY_MAX) { 1889 len = get_delay_len(delay, start); 1890 if (len_final < len) { 1891 start_final = start; 1892 len_final = len; 1893 } 1894 start += len ? len : 1; 1895 if (len >= 12 && start_final < 4) 1896 break; 1897 } 1898 1899 /* The rule is that to find the smallest delay cell */ 1900 if (start_final == 0) 1901 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 1902 else 1903 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 1904 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 1905 delay, len_final, final_phase); 1906 1907 delay_phase.maxlen = len_final; 1908 delay_phase.start = start_final; 1909 delay_phase.final_phase = final_phase; 1910 return delay_phase; 1911 } 1912 1913 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) 1914 { 1915 u32 tune_reg = host->dev_comp->pad_tune_reg; 1916 1917 if (host->top_base) 1918 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, 1919 value); 1920 else 1921 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1922 value); 1923 } 1924 1925 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) 1926 { 1927 u32 tune_reg = host->dev_comp->pad_tune_reg; 1928 1929 if (host->top_base) 1930 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, 1931 PAD_DAT_RD_RXDLY, value); 1932 else 1933 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, 1934 value); 1935 } 1936 1937 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 1938 { 1939 struct msdc_host *host = mmc_priv(mmc); 1940 u32 rise_delay = 0, fall_delay = 0; 1941 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1942 struct msdc_delay_phase internal_delay_phase; 1943 u8 final_delay, final_maxlen; 1944 u32 internal_delay = 0; 1945 u32 tune_reg = host->dev_comp->pad_tune_reg; 1946 int cmd_err; 1947 int i, j; 1948 1949 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 1950 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 1951 sdr_set_field(host->base + tune_reg, 1952 MSDC_PAD_TUNE_CMDRRDLY, 1953 host->hs200_cmd_int_delay); 1954 1955 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1956 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1957 msdc_set_cmd_delay(host, i); 1958 /* 1959 * Using the same parameters, it may sometimes pass the test, 1960 * but sometimes it may fail. To make sure the parameters are 1961 * more stable, we test each set of parameters 3 times. 1962 */ 1963 for (j = 0; j < 3; j++) { 1964 mmc_send_tuning(mmc, opcode, &cmd_err); 1965 if (!cmd_err) { 1966 rise_delay |= (1 << i); 1967 } else { 1968 rise_delay &= ~(1 << i); 1969 break; 1970 } 1971 } 1972 } 1973 final_rise_delay = get_best_delay(host, rise_delay); 1974 /* if rising edge has enough margin, then do not scan falling edge */ 1975 if (final_rise_delay.maxlen >= 12 || 1976 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1977 goto skip_fall; 1978 1979 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1980 for (i = 0; i < PAD_DELAY_MAX; i++) { 1981 msdc_set_cmd_delay(host, i); 1982 /* 1983 * Using the same parameters, it may sometimes pass the test, 1984 * but sometimes it may fail. To make sure the parameters are 1985 * more stable, we test each set of parameters 3 times. 1986 */ 1987 for (j = 0; j < 3; j++) { 1988 mmc_send_tuning(mmc, opcode, &cmd_err); 1989 if (!cmd_err) { 1990 fall_delay |= (1 << i); 1991 } else { 1992 fall_delay &= ~(1 << i); 1993 break; 1994 } 1995 } 1996 } 1997 final_fall_delay = get_best_delay(host, fall_delay); 1998 1999 skip_fall: 2000 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2001 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 2002 final_maxlen = final_fall_delay.maxlen; 2003 if (final_maxlen == final_rise_delay.maxlen) { 2004 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2005 final_delay = final_rise_delay.final_phase; 2006 } else { 2007 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2008 final_delay = final_fall_delay.final_phase; 2009 } 2010 msdc_set_cmd_delay(host, final_delay); 2011 2012 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) 2013 goto skip_internal; 2014 2015 for (i = 0; i < PAD_DELAY_MAX; i++) { 2016 sdr_set_field(host->base + tune_reg, 2017 MSDC_PAD_TUNE_CMDRRDLY, i); 2018 mmc_send_tuning(mmc, opcode, &cmd_err); 2019 if (!cmd_err) 2020 internal_delay |= (1 << i); 2021 } 2022 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 2023 internal_delay_phase = get_best_delay(host, internal_delay); 2024 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 2025 internal_delay_phase.final_phase); 2026 skip_internal: 2027 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 2028 return final_delay == 0xff ? -EIO : 0; 2029 } 2030 2031 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 2032 { 2033 struct msdc_host *host = mmc_priv(mmc); 2034 u32 cmd_delay = 0; 2035 struct msdc_delay_phase final_cmd_delay = { 0,}; 2036 u8 final_delay; 2037 int cmd_err; 2038 int i, j; 2039 2040 /* select EMMC50 PAD CMD tune */ 2041 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 2042 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); 2043 2044 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 2045 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 2046 sdr_set_field(host->base + MSDC_PAD_TUNE, 2047 MSDC_PAD_TUNE_CMDRRDLY, 2048 host->hs200_cmd_int_delay); 2049 2050 if (host->hs400_cmd_resp_sel_rising) 2051 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2052 else 2053 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2054 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2055 sdr_set_field(host->base + PAD_CMD_TUNE, 2056 PAD_CMD_TUNE_RX_DLY3, i); 2057 /* 2058 * Using the same parameters, it may sometimes pass the test, 2059 * but sometimes it may fail. To make sure the parameters are 2060 * more stable, we test each set of parameters 3 times. 2061 */ 2062 for (j = 0; j < 3; j++) { 2063 mmc_send_tuning(mmc, opcode, &cmd_err); 2064 if (!cmd_err) { 2065 cmd_delay |= (1 << i); 2066 } else { 2067 cmd_delay &= ~(1 << i); 2068 break; 2069 } 2070 } 2071 } 2072 final_cmd_delay = get_best_delay(host, cmd_delay); 2073 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 2074 final_cmd_delay.final_phase); 2075 final_delay = final_cmd_delay.final_phase; 2076 2077 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 2078 return final_delay == 0xff ? -EIO : 0; 2079 } 2080 2081 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 2082 { 2083 struct msdc_host *host = mmc_priv(mmc); 2084 u32 rise_delay = 0, fall_delay = 0; 2085 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2086 u8 final_delay, final_maxlen; 2087 int i, ret; 2088 2089 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2090 host->latch_ck); 2091 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2092 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2093 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2094 msdc_set_data_delay(host, i); 2095 ret = mmc_send_tuning(mmc, opcode, NULL); 2096 if (!ret) 2097 rise_delay |= (1 << i); 2098 } 2099 final_rise_delay = get_best_delay(host, rise_delay); 2100 /* if rising edge has enough margin, then do not scan falling edge */ 2101 if (final_rise_delay.maxlen >= 12 || 2102 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2103 goto skip_fall; 2104 2105 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2106 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2107 for (i = 0; i < PAD_DELAY_MAX; i++) { 2108 msdc_set_data_delay(host, i); 2109 ret = mmc_send_tuning(mmc, opcode, NULL); 2110 if (!ret) 2111 fall_delay |= (1 << i); 2112 } 2113 final_fall_delay = get_best_delay(host, fall_delay); 2114 2115 skip_fall: 2116 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2117 if (final_maxlen == final_rise_delay.maxlen) { 2118 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2119 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2120 final_delay = final_rise_delay.final_phase; 2121 } else { 2122 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2123 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2124 final_delay = final_fall_delay.final_phase; 2125 } 2126 msdc_set_data_delay(host, final_delay); 2127 2128 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 2129 return final_delay == 0xff ? -EIO : 0; 2130 } 2131 2132 /* 2133 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune 2134 * together, which can save the tuning time. 2135 */ 2136 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode) 2137 { 2138 struct msdc_host *host = mmc_priv(mmc); 2139 u32 rise_delay = 0, fall_delay = 0; 2140 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2141 u8 final_delay, final_maxlen; 2142 int i, ret; 2143 2144 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2145 host->latch_ck); 2146 2147 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2148 sdr_clr_bits(host->base + MSDC_IOCON, 2149 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2150 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2151 msdc_set_cmd_delay(host, i); 2152 msdc_set_data_delay(host, i); 2153 ret = mmc_send_tuning(mmc, opcode, NULL); 2154 if (!ret) 2155 rise_delay |= (1 << i); 2156 } 2157 final_rise_delay = get_best_delay(host, rise_delay); 2158 /* if rising edge has enough margin, then do not scan falling edge */ 2159 if (final_rise_delay.maxlen >= 12 || 2160 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2161 goto skip_fall; 2162 2163 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2164 sdr_set_bits(host->base + MSDC_IOCON, 2165 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2166 for (i = 0; i < PAD_DELAY_MAX; i++) { 2167 msdc_set_cmd_delay(host, i); 2168 msdc_set_data_delay(host, i); 2169 ret = mmc_send_tuning(mmc, opcode, NULL); 2170 if (!ret) 2171 fall_delay |= (1 << i); 2172 } 2173 final_fall_delay = get_best_delay(host, fall_delay); 2174 2175 skip_fall: 2176 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2177 if (final_maxlen == final_rise_delay.maxlen) { 2178 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2179 sdr_clr_bits(host->base + MSDC_IOCON, 2180 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2181 final_delay = final_rise_delay.final_phase; 2182 } else { 2183 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2184 sdr_set_bits(host->base + MSDC_IOCON, 2185 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2186 final_delay = final_fall_delay.final_phase; 2187 } 2188 2189 msdc_set_cmd_delay(host, final_delay); 2190 msdc_set_data_delay(host, final_delay); 2191 2192 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); 2193 return final_delay == 0xff ? -EIO : 0; 2194 } 2195 2196 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 2197 { 2198 struct msdc_host *host = mmc_priv(mmc); 2199 int ret; 2200 u32 tune_reg = host->dev_comp->pad_tune_reg; 2201 2202 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { 2203 ret = msdc_tune_together(mmc, opcode); 2204 if (host->hs400_mode) { 2205 sdr_clr_bits(host->base + MSDC_IOCON, 2206 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2207 msdc_set_data_delay(host, 0); 2208 } 2209 goto tune_done; 2210 } 2211 if (host->hs400_mode && 2212 host->dev_comp->hs400_tune) 2213 ret = hs400_tune_response(mmc, opcode); 2214 else 2215 ret = msdc_tune_response(mmc, opcode); 2216 if (ret == -EIO) { 2217 dev_err(host->dev, "Tune response fail!\n"); 2218 return ret; 2219 } 2220 if (host->hs400_mode == false) { 2221 ret = msdc_tune_data(mmc, opcode); 2222 if (ret == -EIO) 2223 dev_err(host->dev, "Tune data fail!\n"); 2224 } 2225 2226 tune_done: 2227 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 2228 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 2229 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2230 if (host->top_base) { 2231 host->saved_tune_para.emmc_top_control = readl(host->top_base + 2232 EMMC_TOP_CONTROL); 2233 host->saved_tune_para.emmc_top_cmd = readl(host->top_base + 2234 EMMC_TOP_CMD); 2235 } 2236 return ret; 2237 } 2238 2239 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 2240 { 2241 struct msdc_host *host = mmc_priv(mmc); 2242 host->hs400_mode = true; 2243 2244 if (host->top_base) 2245 writel(host->hs400_ds_delay, 2246 host->top_base + EMMC50_PAD_DS_TUNE); 2247 else 2248 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 2249 /* hs400 mode must set it to 0 */ 2250 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); 2251 /* to improve read performance, set outstanding to 2 */ 2252 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); 2253 2254 return 0; 2255 } 2256 2257 static void msdc_hw_reset(struct mmc_host *mmc) 2258 { 2259 struct msdc_host *host = mmc_priv(mmc); 2260 2261 sdr_set_bits(host->base + EMMC_IOCON, 1); 2262 udelay(10); /* 10us is enough */ 2263 sdr_clr_bits(host->base + EMMC_IOCON, 1); 2264 } 2265 2266 static void msdc_ack_sdio_irq(struct mmc_host *mmc) 2267 { 2268 unsigned long flags; 2269 struct msdc_host *host = mmc_priv(mmc); 2270 2271 spin_lock_irqsave(&host->lock, flags); 2272 __msdc_enable_sdio_irq(host, 1); 2273 spin_unlock_irqrestore(&host->lock, flags); 2274 } 2275 2276 static int msdc_get_cd(struct mmc_host *mmc) 2277 { 2278 struct msdc_host *host = mmc_priv(mmc); 2279 int val; 2280 2281 if (mmc->caps & MMC_CAP_NONREMOVABLE) 2282 return 1; 2283 2284 if (!host->internal_cd) 2285 return mmc_gpio_get_cd(mmc); 2286 2287 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; 2288 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) 2289 return !!val; 2290 else 2291 return !val; 2292 } 2293 2294 static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc, 2295 struct mmc_ios *ios) 2296 { 2297 struct msdc_host *host = mmc_priv(mmc); 2298 2299 if (ios->enhanced_strobe) { 2300 msdc_prepare_hs400_tuning(mmc, ios); 2301 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1); 2302 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1); 2303 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1); 2304 2305 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); 2306 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); 2307 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT); 2308 } else { 2309 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0); 2310 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0); 2311 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0); 2312 2313 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); 2314 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); 2315 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4); 2316 } 2317 } 2318 2319 static void msdc_cqe_enable(struct mmc_host *mmc) 2320 { 2321 struct msdc_host *host = mmc_priv(mmc); 2322 2323 /* enable cmdq irq */ 2324 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); 2325 /* enable busy check */ 2326 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 2327 /* default write data / busy timeout 20s */ 2328 msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); 2329 /* default read data timeout 1s */ 2330 msdc_set_timeout(host, 1000000000ULL, 0); 2331 } 2332 2333 static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) 2334 { 2335 struct msdc_host *host = mmc_priv(mmc); 2336 2337 /* disable cmdq irq */ 2338 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); 2339 /* disable busy check */ 2340 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 2341 2342 if (recovery) { 2343 sdr_set_field(host->base + MSDC_DMA_CTRL, 2344 MSDC_DMA_CTRL_STOP, 1); 2345 msdc_reset_hw(host); 2346 } 2347 } 2348 2349 static void msdc_cqe_pre_enable(struct mmc_host *mmc) 2350 { 2351 struct cqhci_host *cq_host = mmc->cqe_private; 2352 u32 reg; 2353 2354 reg = cqhci_readl(cq_host, CQHCI_CFG); 2355 reg |= CQHCI_ENABLE; 2356 cqhci_writel(cq_host, reg, CQHCI_CFG); 2357 } 2358 2359 static void msdc_cqe_post_disable(struct mmc_host *mmc) 2360 { 2361 struct cqhci_host *cq_host = mmc->cqe_private; 2362 u32 reg; 2363 2364 reg = cqhci_readl(cq_host, CQHCI_CFG); 2365 reg &= ~CQHCI_ENABLE; 2366 cqhci_writel(cq_host, reg, CQHCI_CFG); 2367 } 2368 2369 static const struct mmc_host_ops mt_msdc_ops = { 2370 .post_req = msdc_post_req, 2371 .pre_req = msdc_pre_req, 2372 .request = msdc_ops_request, 2373 .set_ios = msdc_ops_set_ios, 2374 .get_ro = mmc_gpio_get_ro, 2375 .get_cd = msdc_get_cd, 2376 .hs400_enhanced_strobe = msdc_hs400_enhanced_strobe, 2377 .enable_sdio_irq = msdc_enable_sdio_irq, 2378 .ack_sdio_irq = msdc_ack_sdio_irq, 2379 .start_signal_voltage_switch = msdc_ops_switch_volt, 2380 .card_busy = msdc_card_busy, 2381 .execute_tuning = msdc_execute_tuning, 2382 .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 2383 .hw_reset = msdc_hw_reset, 2384 }; 2385 2386 static const struct cqhci_host_ops msdc_cmdq_ops = { 2387 .enable = msdc_cqe_enable, 2388 .disable = msdc_cqe_disable, 2389 .pre_enable = msdc_cqe_pre_enable, 2390 .post_disable = msdc_cqe_post_disable, 2391 }; 2392 2393 static void msdc_of_property_parse(struct platform_device *pdev, 2394 struct msdc_host *host) 2395 { 2396 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", 2397 &host->latch_ck); 2398 2399 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 2400 &host->hs400_ds_delay); 2401 2402 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 2403 &host->hs200_cmd_int_delay); 2404 2405 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 2406 &host->hs400_cmd_int_delay); 2407 2408 if (of_property_read_bool(pdev->dev.of_node, 2409 "mediatek,hs400-cmd-resp-sel-rising")) 2410 host->hs400_cmd_resp_sel_rising = true; 2411 else 2412 host->hs400_cmd_resp_sel_rising = false; 2413 2414 if (of_property_read_bool(pdev->dev.of_node, 2415 "supports-cqe")) 2416 host->cqhci = true; 2417 else 2418 host->cqhci = false; 2419 } 2420 2421 static int msdc_of_clock_parse(struct platform_device *pdev, 2422 struct msdc_host *host) 2423 { 2424 int ret; 2425 2426 host->src_clk = devm_clk_get(&pdev->dev, "source"); 2427 if (IS_ERR(host->src_clk)) 2428 return PTR_ERR(host->src_clk); 2429 2430 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 2431 if (IS_ERR(host->h_clk)) 2432 return PTR_ERR(host->h_clk); 2433 2434 host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk"); 2435 if (IS_ERR(host->bus_clk)) 2436 host->bus_clk = NULL; 2437 2438 /*source clock control gate is optional clock*/ 2439 host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg"); 2440 if (IS_ERR(host->src_clk_cg)) 2441 host->src_clk_cg = NULL; 2442 2443 host->sys_clk_cg = devm_clk_get_optional(&pdev->dev, "sys_cg"); 2444 if (IS_ERR(host->sys_clk_cg)) 2445 host->sys_clk_cg = NULL; 2446 2447 /* If present, always enable for this clock gate */ 2448 clk_prepare_enable(host->sys_clk_cg); 2449 2450 host->bulk_clks[0].id = "pclk_cg"; 2451 host->bulk_clks[1].id = "axi_cg"; 2452 host->bulk_clks[2].id = "ahb_cg"; 2453 ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS, 2454 host->bulk_clks); 2455 if (ret) { 2456 dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n"); 2457 return ret; 2458 } 2459 2460 return 0; 2461 } 2462 2463 static int msdc_drv_probe(struct platform_device *pdev) 2464 { 2465 struct mmc_host *mmc; 2466 struct msdc_host *host; 2467 struct resource *res; 2468 int ret; 2469 2470 if (!pdev->dev.of_node) { 2471 dev_err(&pdev->dev, "No DT found\n"); 2472 return -EINVAL; 2473 } 2474 2475 /* Allocate MMC host for this device */ 2476 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 2477 if (!mmc) 2478 return -ENOMEM; 2479 2480 host = mmc_priv(mmc); 2481 ret = mmc_of_parse(mmc); 2482 if (ret) 2483 goto host_free; 2484 2485 host->base = devm_platform_ioremap_resource(pdev, 0); 2486 if (IS_ERR(host->base)) { 2487 ret = PTR_ERR(host->base); 2488 goto host_free; 2489 } 2490 2491 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2492 if (res) { 2493 host->top_base = devm_ioremap_resource(&pdev->dev, res); 2494 if (IS_ERR(host->top_base)) 2495 host->top_base = NULL; 2496 } 2497 2498 ret = mmc_regulator_get_supply(mmc); 2499 if (ret) 2500 goto host_free; 2501 2502 ret = msdc_of_clock_parse(pdev, host); 2503 if (ret) 2504 goto host_free; 2505 2506 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 2507 "hrst"); 2508 if (IS_ERR(host->reset)) { 2509 ret = PTR_ERR(host->reset); 2510 goto host_free; 2511 } 2512 2513 host->irq = platform_get_irq(pdev, 0); 2514 if (host->irq < 0) { 2515 ret = -EINVAL; 2516 goto host_free; 2517 } 2518 2519 host->pinctrl = devm_pinctrl_get(&pdev->dev); 2520 if (IS_ERR(host->pinctrl)) { 2521 ret = PTR_ERR(host->pinctrl); 2522 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 2523 goto host_free; 2524 } 2525 2526 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 2527 if (IS_ERR(host->pins_default)) { 2528 ret = PTR_ERR(host->pins_default); 2529 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 2530 goto host_free; 2531 } 2532 2533 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 2534 if (IS_ERR(host->pins_uhs)) { 2535 ret = PTR_ERR(host->pins_uhs); 2536 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 2537 goto host_free; 2538 } 2539 2540 msdc_of_property_parse(pdev, host); 2541 2542 host->dev = &pdev->dev; 2543 host->dev_comp = of_device_get_match_data(&pdev->dev); 2544 host->src_clk_freq = clk_get_rate(host->src_clk); 2545 /* Set host parameters to mmc */ 2546 mmc->ops = &mt_msdc_ops; 2547 if (host->dev_comp->clk_div_bits == 8) 2548 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 2549 else 2550 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); 2551 2552 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && 2553 !mmc_can_gpio_cd(mmc) && 2554 host->dev_comp->use_internal_cd) { 2555 /* 2556 * Is removable but no GPIO declared, so 2557 * use internal functionality. 2558 */ 2559 host->internal_cd = true; 2560 } 2561 2562 if (mmc->caps & MMC_CAP_SDIO_IRQ) 2563 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2564 2565 mmc->caps |= MMC_CAP_CMD23; 2566 if (host->cqhci) 2567 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 2568 /* MMC core transfer sizes tunable parameters */ 2569 mmc->max_segs = MAX_BD_NUM; 2570 if (host->dev_comp->support_64g) 2571 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; 2572 else 2573 mmc->max_seg_size = BDMA_DESC_BUFLEN; 2574 mmc->max_blk_size = 2048; 2575 mmc->max_req_size = 512 * 1024; 2576 mmc->max_blk_count = mmc->max_req_size / 512; 2577 if (host->dev_comp->support_64g) 2578 host->dma_mask = DMA_BIT_MASK(36); 2579 else 2580 host->dma_mask = DMA_BIT_MASK(32); 2581 mmc_dev(mmc)->dma_mask = &host->dma_mask; 2582 2583 if (mmc->caps2 & MMC_CAP2_CQE) { 2584 host->cq_host = devm_kzalloc(mmc->parent, 2585 sizeof(*host->cq_host), 2586 GFP_KERNEL); 2587 if (!host->cq_host) { 2588 ret = -ENOMEM; 2589 goto host_free; 2590 } 2591 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 2592 host->cq_host->mmio = host->base + 0x800; 2593 host->cq_host->ops = &msdc_cmdq_ops; 2594 ret = cqhci_init(host->cq_host, mmc, true); 2595 if (ret) 2596 goto host_free; 2597 mmc->max_segs = 128; 2598 /* cqhci 16bit length */ 2599 /* 0 size, means 65536 so we don't have to -1 here */ 2600 mmc->max_seg_size = 64 * 1024; 2601 } 2602 2603 host->timeout_clks = 3 * 1048576; 2604 host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2605 2 * sizeof(struct mt_gpdma_desc), 2606 &host->dma.gpd_addr, GFP_KERNEL); 2607 host->dma.bd = dma_alloc_coherent(&pdev->dev, 2608 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2609 &host->dma.bd_addr, GFP_KERNEL); 2610 if (!host->dma.gpd || !host->dma.bd) { 2611 ret = -ENOMEM; 2612 goto release_mem; 2613 } 2614 msdc_init_gpd_bd(host, &host->dma); 2615 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 2616 spin_lock_init(&host->lock); 2617 2618 platform_set_drvdata(pdev, mmc); 2619 msdc_ungate_clock(host); 2620 msdc_init_hw(host); 2621 2622 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 2623 IRQF_TRIGGER_NONE, pdev->name, host); 2624 if (ret) 2625 goto release; 2626 2627 pm_runtime_set_active(host->dev); 2628 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 2629 pm_runtime_use_autosuspend(host->dev); 2630 pm_runtime_enable(host->dev); 2631 ret = mmc_add_host(mmc); 2632 2633 if (ret) 2634 goto end; 2635 2636 return 0; 2637 end: 2638 pm_runtime_disable(host->dev); 2639 release: 2640 platform_set_drvdata(pdev, NULL); 2641 msdc_deinit_hw(host); 2642 msdc_gate_clock(host); 2643 release_mem: 2644 if (host->dma.gpd) 2645 dma_free_coherent(&pdev->dev, 2646 2 * sizeof(struct mt_gpdma_desc), 2647 host->dma.gpd, host->dma.gpd_addr); 2648 if (host->dma.bd) 2649 dma_free_coherent(&pdev->dev, 2650 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2651 host->dma.bd, host->dma.bd_addr); 2652 host_free: 2653 mmc_free_host(mmc); 2654 2655 return ret; 2656 } 2657 2658 static int msdc_drv_remove(struct platform_device *pdev) 2659 { 2660 struct mmc_host *mmc; 2661 struct msdc_host *host; 2662 2663 mmc = platform_get_drvdata(pdev); 2664 host = mmc_priv(mmc); 2665 2666 pm_runtime_get_sync(host->dev); 2667 2668 platform_set_drvdata(pdev, NULL); 2669 mmc_remove_host(mmc); 2670 msdc_deinit_hw(host); 2671 msdc_gate_clock(host); 2672 2673 pm_runtime_disable(host->dev); 2674 pm_runtime_put_noidle(host->dev); 2675 dma_free_coherent(&pdev->dev, 2676 2 * sizeof(struct mt_gpdma_desc), 2677 host->dma.gpd, host->dma.gpd_addr); 2678 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2679 host->dma.bd, host->dma.bd_addr); 2680 2681 mmc_free_host(mmc); 2682 2683 return 0; 2684 } 2685 2686 static void msdc_save_reg(struct msdc_host *host) 2687 { 2688 u32 tune_reg = host->dev_comp->pad_tune_reg; 2689 2690 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 2691 host->save_para.iocon = readl(host->base + MSDC_IOCON); 2692 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 2693 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 2694 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 2695 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); 2696 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 2697 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2698 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 2699 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); 2700 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); 2701 if (host->top_base) { 2702 host->save_para.emmc_top_control = 2703 readl(host->top_base + EMMC_TOP_CONTROL); 2704 host->save_para.emmc_top_cmd = 2705 readl(host->top_base + EMMC_TOP_CMD); 2706 host->save_para.emmc50_pad_ds_tune = 2707 readl(host->top_base + EMMC50_PAD_DS_TUNE); 2708 } else { 2709 host->save_para.pad_tune = readl(host->base + tune_reg); 2710 } 2711 } 2712 2713 static void msdc_restore_reg(struct msdc_host *host) 2714 { 2715 struct mmc_host *mmc = mmc_from_priv(host); 2716 u32 tune_reg = host->dev_comp->pad_tune_reg; 2717 2718 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 2719 writel(host->save_para.iocon, host->base + MSDC_IOCON); 2720 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 2721 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 2722 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 2723 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); 2724 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 2725 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 2726 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 2727 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); 2728 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); 2729 if (host->top_base) { 2730 writel(host->save_para.emmc_top_control, 2731 host->top_base + EMMC_TOP_CONTROL); 2732 writel(host->save_para.emmc_top_cmd, 2733 host->top_base + EMMC_TOP_CMD); 2734 writel(host->save_para.emmc50_pad_ds_tune, 2735 host->top_base + EMMC50_PAD_DS_TUNE); 2736 } else { 2737 writel(host->save_para.pad_tune, host->base + tune_reg); 2738 } 2739 2740 if (sdio_irq_claimed(mmc)) 2741 __msdc_enable_sdio_irq(host, 1); 2742 } 2743 2744 static int __maybe_unused msdc_runtime_suspend(struct device *dev) 2745 { 2746 struct mmc_host *mmc = dev_get_drvdata(dev); 2747 struct msdc_host *host = mmc_priv(mmc); 2748 2749 msdc_save_reg(host); 2750 msdc_gate_clock(host); 2751 return 0; 2752 } 2753 2754 static int __maybe_unused msdc_runtime_resume(struct device *dev) 2755 { 2756 struct mmc_host *mmc = dev_get_drvdata(dev); 2757 struct msdc_host *host = mmc_priv(mmc); 2758 2759 msdc_ungate_clock(host); 2760 msdc_restore_reg(host); 2761 return 0; 2762 } 2763 2764 static int __maybe_unused msdc_suspend(struct device *dev) 2765 { 2766 struct mmc_host *mmc = dev_get_drvdata(dev); 2767 int ret; 2768 2769 if (mmc->caps2 & MMC_CAP2_CQE) { 2770 ret = cqhci_suspend(mmc); 2771 if (ret) 2772 return ret; 2773 } 2774 2775 return pm_runtime_force_suspend(dev); 2776 } 2777 2778 static int __maybe_unused msdc_resume(struct device *dev) 2779 { 2780 return pm_runtime_force_resume(dev); 2781 } 2782 2783 static const struct dev_pm_ops msdc_dev_pm_ops = { 2784 SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume) 2785 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 2786 }; 2787 2788 static struct platform_driver mt_msdc_driver = { 2789 .probe = msdc_drv_probe, 2790 .remove = msdc_drv_remove, 2791 .driver = { 2792 .name = "mtk-msdc", 2793 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 2794 .of_match_table = msdc_of_ids, 2795 .pm = &msdc_dev_pm_ops, 2796 }, 2797 }; 2798 2799 module_platform_driver(mt_msdc_driver); 2800 MODULE_LICENSE("GPL v2"); 2801 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 2802