xref: /openbmc/linux/drivers/mmc/host/mtk-sd.c (revision 2a12187d)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2014-2015, 2022 MediaTek Inc.
4  * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
5  */
6 
7 #include <linux/module.h>
8 #include <linux/bitops.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/iopoll.h>
13 #include <linux/ioport.h>
14 #include <linux/irq.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/of_irq.h>
18 #include <linux/of_gpio.h>
19 #include <linux/pinctrl/consumer.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/pm_wakeirq.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/interrupt.h>
28 #include <linux/reset.h>
29 
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/core.h>
32 #include <linux/mmc/host.h>
33 #include <linux/mmc/mmc.h>
34 #include <linux/mmc/sd.h>
35 #include <linux/mmc/sdio.h>
36 #include <linux/mmc/slot-gpio.h>
37 
38 #include "cqhci.h"
39 
40 #define MAX_BD_NUM          1024
41 #define MSDC_NR_CLOCKS      3
42 
43 /*--------------------------------------------------------------------------*/
44 /* Common Definition                                                        */
45 /*--------------------------------------------------------------------------*/
46 #define MSDC_BUS_1BITS          0x0
47 #define MSDC_BUS_4BITS          0x1
48 #define MSDC_BUS_8BITS          0x2
49 
50 #define MSDC_BURST_64B          0x6
51 
52 /*--------------------------------------------------------------------------*/
53 /* Register Offset                                                          */
54 /*--------------------------------------------------------------------------*/
55 #define MSDC_CFG         0x0
56 #define MSDC_IOCON       0x04
57 #define MSDC_PS          0x08
58 #define MSDC_INT         0x0c
59 #define MSDC_INTEN       0x10
60 #define MSDC_FIFOCS      0x14
61 #define SDC_CFG          0x30
62 #define SDC_CMD          0x34
63 #define SDC_ARG          0x38
64 #define SDC_STS          0x3c
65 #define SDC_RESP0        0x40
66 #define SDC_RESP1        0x44
67 #define SDC_RESP2        0x48
68 #define SDC_RESP3        0x4c
69 #define SDC_BLK_NUM      0x50
70 #define SDC_ADV_CFG0     0x64
71 #define EMMC_IOCON       0x7c
72 #define SDC_ACMD_RESP    0x80
73 #define DMA_SA_H4BIT     0x8c
74 #define MSDC_DMA_SA      0x90
75 #define MSDC_DMA_CTRL    0x98
76 #define MSDC_DMA_CFG     0x9c
77 #define MSDC_PATCH_BIT   0xb0
78 #define MSDC_PATCH_BIT1  0xb4
79 #define MSDC_PATCH_BIT2  0xb8
80 #define MSDC_PAD_TUNE    0xec
81 #define MSDC_PAD_TUNE0   0xf0
82 #define PAD_DS_TUNE      0x188
83 #define PAD_CMD_TUNE     0x18c
84 #define EMMC51_CFG0	 0x204
85 #define EMMC50_CFG0      0x208
86 #define EMMC50_CFG1      0x20c
87 #define EMMC50_CFG3      0x220
88 #define SDC_FIFO_CFG     0x228
89 #define CQHCI_SETTING	 0x7fc
90 
91 /*--------------------------------------------------------------------------*/
92 /* Top Pad Register Offset                                                  */
93 /*--------------------------------------------------------------------------*/
94 #define EMMC_TOP_CONTROL	0x00
95 #define EMMC_TOP_CMD		0x04
96 #define EMMC50_PAD_DS_TUNE	0x0c
97 
98 /*--------------------------------------------------------------------------*/
99 /* Register Mask                                                            */
100 /*--------------------------------------------------------------------------*/
101 
102 /* MSDC_CFG mask */
103 #define MSDC_CFG_MODE           BIT(0)	/* RW */
104 #define MSDC_CFG_CKPDN          BIT(1)	/* RW */
105 #define MSDC_CFG_RST            BIT(2)	/* RW */
106 #define MSDC_CFG_PIO            BIT(3)	/* RW */
107 #define MSDC_CFG_CKDRVEN        BIT(4)	/* RW */
108 #define MSDC_CFG_BV18SDT        BIT(5)	/* RW */
109 #define MSDC_CFG_BV18PSS        BIT(6)	/* R  */
110 #define MSDC_CFG_CKSTB          BIT(7)	/* R  */
111 #define MSDC_CFG_CKDIV          GENMASK(15, 8)	/* RW */
112 #define MSDC_CFG_CKMOD          GENMASK(17, 16)	/* RW */
113 #define MSDC_CFG_HS400_CK_MODE  BIT(18)	/* RW */
114 #define MSDC_CFG_HS400_CK_MODE_EXTRA  BIT(22)	/* RW */
115 #define MSDC_CFG_CKDIV_EXTRA    GENMASK(19, 8)	/* RW */
116 #define MSDC_CFG_CKMOD_EXTRA    GENMASK(21, 20)	/* RW */
117 
118 /* MSDC_IOCON mask */
119 #define MSDC_IOCON_SDR104CKS    BIT(0)	/* RW */
120 #define MSDC_IOCON_RSPL         BIT(1)	/* RW */
121 #define MSDC_IOCON_DSPL         BIT(2)	/* RW */
122 #define MSDC_IOCON_DDLSEL       BIT(3)	/* RW */
123 #define MSDC_IOCON_DDR50CKD     BIT(4)	/* RW */
124 #define MSDC_IOCON_DSPLSEL      BIT(5)	/* RW */
125 #define MSDC_IOCON_W_DSPL       BIT(8)	/* RW */
126 #define MSDC_IOCON_D0SPL        BIT(16)	/* RW */
127 #define MSDC_IOCON_D1SPL        BIT(17)	/* RW */
128 #define MSDC_IOCON_D2SPL        BIT(18)	/* RW */
129 #define MSDC_IOCON_D3SPL        BIT(19)	/* RW */
130 #define MSDC_IOCON_D4SPL        BIT(20)	/* RW */
131 #define MSDC_IOCON_D5SPL        BIT(21)	/* RW */
132 #define MSDC_IOCON_D6SPL        BIT(22)	/* RW */
133 #define MSDC_IOCON_D7SPL        BIT(23)	/* RW */
134 #define MSDC_IOCON_RISCSZ       GENMASK(25, 24)	/* RW */
135 
136 /* MSDC_PS mask */
137 #define MSDC_PS_CDEN            BIT(0)	/* RW */
138 #define MSDC_PS_CDSTS           BIT(1)	/* R  */
139 #define MSDC_PS_CDDEBOUNCE      GENMASK(15, 12)	/* RW */
140 #define MSDC_PS_DAT             GENMASK(23, 16)	/* R  */
141 #define MSDC_PS_DATA1           BIT(17)	/* R  */
142 #define MSDC_PS_CMD             BIT(24)	/* R  */
143 #define MSDC_PS_WP              BIT(31)	/* R  */
144 
145 /* MSDC_INT mask */
146 #define MSDC_INT_MMCIRQ         BIT(0)	/* W1C */
147 #define MSDC_INT_CDSC           BIT(1)	/* W1C */
148 #define MSDC_INT_ACMDRDY        BIT(3)	/* W1C */
149 #define MSDC_INT_ACMDTMO        BIT(4)	/* W1C */
150 #define MSDC_INT_ACMDCRCERR     BIT(5)	/* W1C */
151 #define MSDC_INT_DMAQ_EMPTY     BIT(6)	/* W1C */
152 #define MSDC_INT_SDIOIRQ        BIT(7)	/* W1C */
153 #define MSDC_INT_CMDRDY         BIT(8)	/* W1C */
154 #define MSDC_INT_CMDTMO         BIT(9)	/* W1C */
155 #define MSDC_INT_RSPCRCERR      BIT(10)	/* W1C */
156 #define MSDC_INT_CSTA           BIT(11)	/* R */
157 #define MSDC_INT_XFER_COMPL     BIT(12)	/* W1C */
158 #define MSDC_INT_DXFER_DONE     BIT(13)	/* W1C */
159 #define MSDC_INT_DATTMO         BIT(14)	/* W1C */
160 #define MSDC_INT_DATCRCERR      BIT(15)	/* W1C */
161 #define MSDC_INT_ACMD19_DONE    BIT(16)	/* W1C */
162 #define MSDC_INT_DMA_BDCSERR    BIT(17)	/* W1C */
163 #define MSDC_INT_DMA_GPDCSERR   BIT(18)	/* W1C */
164 #define MSDC_INT_DMA_PROTECT    BIT(19)	/* W1C */
165 #define MSDC_INT_CMDQ           BIT(28)	/* W1C */
166 
167 /* MSDC_INTEN mask */
168 #define MSDC_INTEN_MMCIRQ       BIT(0)	/* RW */
169 #define MSDC_INTEN_CDSC         BIT(1)	/* RW */
170 #define MSDC_INTEN_ACMDRDY      BIT(3)	/* RW */
171 #define MSDC_INTEN_ACMDTMO      BIT(4)	/* RW */
172 #define MSDC_INTEN_ACMDCRCERR   BIT(5)	/* RW */
173 #define MSDC_INTEN_DMAQ_EMPTY   BIT(6)	/* RW */
174 #define MSDC_INTEN_SDIOIRQ      BIT(7)	/* RW */
175 #define MSDC_INTEN_CMDRDY       BIT(8)	/* RW */
176 #define MSDC_INTEN_CMDTMO       BIT(9)	/* RW */
177 #define MSDC_INTEN_RSPCRCERR    BIT(10)	/* RW */
178 #define MSDC_INTEN_CSTA         BIT(11)	/* RW */
179 #define MSDC_INTEN_XFER_COMPL   BIT(12)	/* RW */
180 #define MSDC_INTEN_DXFER_DONE   BIT(13)	/* RW */
181 #define MSDC_INTEN_DATTMO       BIT(14)	/* RW */
182 #define MSDC_INTEN_DATCRCERR    BIT(15)	/* RW */
183 #define MSDC_INTEN_ACMD19_DONE  BIT(16)	/* RW */
184 #define MSDC_INTEN_DMA_BDCSERR  BIT(17)	/* RW */
185 #define MSDC_INTEN_DMA_GPDCSERR BIT(18)	/* RW */
186 #define MSDC_INTEN_DMA_PROTECT  BIT(19)	/* RW */
187 
188 /* MSDC_FIFOCS mask */
189 #define MSDC_FIFOCS_RXCNT       GENMASK(7, 0)	/* R */
190 #define MSDC_FIFOCS_TXCNT       GENMASK(23, 16)	/* R */
191 #define MSDC_FIFOCS_CLR         BIT(31)	/* RW */
192 
193 /* SDC_CFG mask */
194 #define SDC_CFG_SDIOINTWKUP     BIT(0)	/* RW */
195 #define SDC_CFG_INSWKUP         BIT(1)	/* RW */
196 #define SDC_CFG_WRDTOC          GENMASK(14, 2)  /* RW */
197 #define SDC_CFG_BUSWIDTH        GENMASK(17, 16)	/* RW */
198 #define SDC_CFG_SDIO            BIT(19)	/* RW */
199 #define SDC_CFG_SDIOIDE         BIT(20)	/* RW */
200 #define SDC_CFG_INTATGAP        BIT(21)	/* RW */
201 #define SDC_CFG_DTOC            GENMASK(31, 24)	/* RW */
202 
203 /* SDC_STS mask */
204 #define SDC_STS_SDCBUSY         BIT(0)	/* RW */
205 #define SDC_STS_CMDBUSY         BIT(1)	/* RW */
206 #define SDC_STS_SWR_COMPL       BIT(31)	/* RW */
207 
208 #define SDC_DAT1_IRQ_TRIGGER	BIT(19)	/* RW */
209 /* SDC_ADV_CFG0 mask */
210 #define SDC_RX_ENHANCE_EN	BIT(20)	/* RW */
211 
212 /* DMA_SA_H4BIT mask */
213 #define DMA_ADDR_HIGH_4BIT      GENMASK(3, 0)	/* RW */
214 
215 /* MSDC_DMA_CTRL mask */
216 #define MSDC_DMA_CTRL_START     BIT(0)	/* W */
217 #define MSDC_DMA_CTRL_STOP      BIT(1)	/* W */
218 #define MSDC_DMA_CTRL_RESUME    BIT(2)	/* W */
219 #define MSDC_DMA_CTRL_MODE      BIT(8)	/* RW */
220 #define MSDC_DMA_CTRL_LASTBUF   BIT(10)	/* RW */
221 #define MSDC_DMA_CTRL_BRUSTSZ   GENMASK(14, 12)	/* RW */
222 
223 /* MSDC_DMA_CFG mask */
224 #define MSDC_DMA_CFG_STS        BIT(0)	/* R */
225 #define MSDC_DMA_CFG_DECSEN     BIT(1)	/* RW */
226 #define MSDC_DMA_CFG_AHBHPROT2  BIT(9)	/* RW */
227 #define MSDC_DMA_CFG_ACTIVEEN   BIT(13)	/* RW */
228 #define MSDC_DMA_CFG_CS12B16B   BIT(16)	/* RW */
229 
230 /* MSDC_PATCH_BIT mask */
231 #define MSDC_PATCH_BIT_ODDSUPP    BIT(1)	/* RW */
232 #define MSDC_INT_DAT_LATCH_CK_SEL GENMASK(9, 7)
233 #define MSDC_CKGEN_MSDC_DLY_SEL   GENMASK(14, 10)
234 #define MSDC_PATCH_BIT_IODSSEL    BIT(16)	/* RW */
235 #define MSDC_PATCH_BIT_IOINTSEL   BIT(17)	/* RW */
236 #define MSDC_PATCH_BIT_BUSYDLY    GENMASK(21, 18)	/* RW */
237 #define MSDC_PATCH_BIT_WDOD       GENMASK(25, 22)	/* RW */
238 #define MSDC_PATCH_BIT_IDRTSEL    BIT(26)	/* RW */
239 #define MSDC_PATCH_BIT_CMDFSEL    BIT(27)	/* RW */
240 #define MSDC_PATCH_BIT_INTDLSEL   BIT(28)	/* RW */
241 #define MSDC_PATCH_BIT_SPCPUSH    BIT(29)	/* RW */
242 #define MSDC_PATCH_BIT_DECRCTMO   BIT(30)	/* RW */
243 
244 #define MSDC_PATCH_BIT1_CMDTA     GENMASK(5, 3)    /* RW */
245 #define MSDC_PB1_BUSY_CHECK_SEL   BIT(7)    /* RW */
246 #define MSDC_PATCH_BIT1_STOP_DLY  GENMASK(11, 8)    /* RW */
247 
248 #define MSDC_PATCH_BIT2_CFGRESP   BIT(15)   /* RW */
249 #define MSDC_PATCH_BIT2_CFGCRCSTS BIT(28)   /* RW */
250 #define MSDC_PB2_SUPPORT_64G      BIT(1)    /* RW */
251 #define MSDC_PB2_RESPWAIT         GENMASK(3, 2)   /* RW */
252 #define MSDC_PB2_RESPSTSENSEL     GENMASK(18, 16) /* RW */
253 #define MSDC_PB2_CRCSTSENSEL      GENMASK(31, 29) /* RW */
254 
255 #define MSDC_PAD_TUNE_DATWRDLY	  GENMASK(4, 0)		/* RW */
256 #define MSDC_PAD_TUNE_DATRRDLY	  GENMASK(12, 8)	/* RW */
257 #define MSDC_PAD_TUNE_CMDRDLY	  GENMASK(20, 16)	/* RW */
258 #define MSDC_PAD_TUNE_CMDRRDLY	  GENMASK(26, 22)	/* RW */
259 #define MSDC_PAD_TUNE_CLKTDLY	  GENMASK(31, 27)	/* RW */
260 #define MSDC_PAD_TUNE_RXDLYSEL	  BIT(15)   /* RW */
261 #define MSDC_PAD_TUNE_RD_SEL	  BIT(13)   /* RW */
262 #define MSDC_PAD_TUNE_CMD_SEL	  BIT(21)   /* RW */
263 
264 #define PAD_DS_TUNE_DLY_SEL       BIT(0)	  /* RW */
265 #define PAD_DS_TUNE_DLY1	  GENMASK(6, 2)   /* RW */
266 #define PAD_DS_TUNE_DLY2	  GENMASK(11, 7)  /* RW */
267 #define PAD_DS_TUNE_DLY3	  GENMASK(16, 12) /* RW */
268 
269 #define PAD_CMD_TUNE_RX_DLY3	  GENMASK(5, 1)   /* RW */
270 
271 /* EMMC51_CFG0 mask */
272 #define CMDQ_RDAT_CNT		  GENMASK(21, 12) /* RW */
273 
274 #define EMMC50_CFG_PADCMD_LATCHCK BIT(0)   /* RW */
275 #define EMMC50_CFG_CRCSTS_EDGE    BIT(3)   /* RW */
276 #define EMMC50_CFG_CFCSTS_SEL     BIT(4)   /* RW */
277 #define EMMC50_CFG_CMD_RESP_SEL   BIT(9)   /* RW */
278 
279 /* EMMC50_CFG1 mask */
280 #define EMMC50_CFG1_DS_CFG        BIT(28)  /* RW */
281 
282 #define EMMC50_CFG3_OUTS_WR       GENMASK(4, 0)  /* RW */
283 
284 #define SDC_FIFO_CFG_WRVALIDSEL   BIT(24)  /* RW */
285 #define SDC_FIFO_CFG_RDVALIDSEL   BIT(25)  /* RW */
286 
287 /* CQHCI_SETTING */
288 #define CQHCI_RD_CMD_WND_SEL	  BIT(14) /* RW */
289 #define CQHCI_WR_CMD_WND_SEL	  BIT(15) /* RW */
290 
291 /* EMMC_TOP_CONTROL mask */
292 #define PAD_RXDLY_SEL           BIT(0)      /* RW */
293 #define DELAY_EN                BIT(1)      /* RW */
294 #define PAD_DAT_RD_RXDLY2       GENMASK(6, 2)     /* RW */
295 #define PAD_DAT_RD_RXDLY        GENMASK(11, 7)    /* RW */
296 #define PAD_DAT_RD_RXDLY2_SEL   BIT(12)     /* RW */
297 #define PAD_DAT_RD_RXDLY_SEL    BIT(13)     /* RW */
298 #define DATA_K_VALUE_SEL        BIT(14)     /* RW */
299 #define SDC_RX_ENH_EN           BIT(15)     /* TW */
300 
301 /* EMMC_TOP_CMD mask */
302 #define PAD_CMD_RXDLY2          GENMASK(4, 0)	/* RW */
303 #define PAD_CMD_RXDLY           GENMASK(9, 5)	/* RW */
304 #define PAD_CMD_RD_RXDLY2_SEL   BIT(10)		/* RW */
305 #define PAD_CMD_RD_RXDLY_SEL    BIT(11)		/* RW */
306 #define PAD_CMD_TX_DLY          GENMASK(16, 12)	/* RW */
307 
308 /* EMMC50_PAD_DS_TUNE mask */
309 #define PAD_DS_DLY_SEL		BIT(16)	/* RW */
310 #define PAD_DS_DLY1		GENMASK(14, 10)	/* RW */
311 #define PAD_DS_DLY3		GENMASK(4, 0)	/* RW */
312 
313 #define REQ_CMD_EIO  BIT(0)
314 #define REQ_CMD_TMO  BIT(1)
315 #define REQ_DAT_ERR  BIT(2)
316 #define REQ_STOP_EIO BIT(3)
317 #define REQ_STOP_TMO BIT(4)
318 #define REQ_CMD_BUSY BIT(5)
319 
320 #define MSDC_PREPARE_FLAG BIT(0)
321 #define MSDC_ASYNC_FLAG BIT(1)
322 #define MSDC_MMAP_FLAG BIT(2)
323 
324 #define MTK_MMC_AUTOSUSPEND_DELAY	50
325 #define CMD_TIMEOUT         (HZ/10 * 5)	/* 100ms x5 */
326 #define DAT_TIMEOUT         (HZ    * 5)	/* 1000ms x5 */
327 
328 #define DEFAULT_DEBOUNCE	(8)	/* 8 cycles CD debounce */
329 
330 #define PAD_DELAY_MAX	32 /* PAD delay cells */
331 /*--------------------------------------------------------------------------*/
332 /* Descriptor Structure                                                     */
333 /*--------------------------------------------------------------------------*/
334 struct mt_gpdma_desc {
335 	u32 gpd_info;
336 #define GPDMA_DESC_HWO		BIT(0)
337 #define GPDMA_DESC_BDP		BIT(1)
338 #define GPDMA_DESC_CHECKSUM	GENMASK(15, 8)
339 #define GPDMA_DESC_INT		BIT(16)
340 #define GPDMA_DESC_NEXT_H4	GENMASK(27, 24)
341 #define GPDMA_DESC_PTR_H4	GENMASK(31, 28)
342 	u32 next;
343 	u32 ptr;
344 	u32 gpd_data_len;
345 #define GPDMA_DESC_BUFLEN	GENMASK(15, 0)
346 #define GPDMA_DESC_EXTLEN	GENMASK(23, 16)
347 	u32 arg;
348 	u32 blknum;
349 	u32 cmd;
350 };
351 
352 struct mt_bdma_desc {
353 	u32 bd_info;
354 #define BDMA_DESC_EOL		BIT(0)
355 #define BDMA_DESC_CHECKSUM	GENMASK(15, 8)
356 #define BDMA_DESC_BLKPAD	BIT(17)
357 #define BDMA_DESC_DWPAD		BIT(18)
358 #define BDMA_DESC_NEXT_H4	GENMASK(27, 24)
359 #define BDMA_DESC_PTR_H4	GENMASK(31, 28)
360 	u32 next;
361 	u32 ptr;
362 	u32 bd_data_len;
363 #define BDMA_DESC_BUFLEN	GENMASK(15, 0)
364 #define BDMA_DESC_BUFLEN_EXT	GENMASK(23, 0)
365 };
366 
367 struct msdc_dma {
368 	struct scatterlist *sg;	/* I/O scatter list */
369 	struct mt_gpdma_desc *gpd;		/* pointer to gpd array */
370 	struct mt_bdma_desc *bd;		/* pointer to bd array */
371 	dma_addr_t gpd_addr;	/* the physical address of gpd array */
372 	dma_addr_t bd_addr;	/* the physical address of bd array */
373 };
374 
375 struct msdc_save_para {
376 	u32 msdc_cfg;
377 	u32 iocon;
378 	u32 sdc_cfg;
379 	u32 pad_tune;
380 	u32 patch_bit0;
381 	u32 patch_bit1;
382 	u32 patch_bit2;
383 	u32 pad_ds_tune;
384 	u32 pad_cmd_tune;
385 	u32 emmc50_cfg0;
386 	u32 emmc50_cfg3;
387 	u32 sdc_fifo_cfg;
388 	u32 emmc_top_control;
389 	u32 emmc_top_cmd;
390 	u32 emmc50_pad_ds_tune;
391 };
392 
393 struct mtk_mmc_compatible {
394 	u8 clk_div_bits;
395 	bool recheck_sdio_irq;
396 	bool hs400_tune; /* only used for MT8173 */
397 	u32 pad_tune_reg;
398 	bool async_fifo;
399 	bool data_tune;
400 	bool busy_check;
401 	bool stop_clk_fix;
402 	bool enhance_rx;
403 	bool support_64g;
404 	bool use_internal_cd;
405 };
406 
407 struct msdc_tune_para {
408 	u32 iocon;
409 	u32 pad_tune;
410 	u32 pad_cmd_tune;
411 	u32 emmc_top_control;
412 	u32 emmc_top_cmd;
413 };
414 
415 struct msdc_delay_phase {
416 	u8 maxlen;
417 	u8 start;
418 	u8 final_phase;
419 };
420 
421 struct msdc_host {
422 	struct device *dev;
423 	const struct mtk_mmc_compatible *dev_comp;
424 	int cmd_rsp;
425 
426 	spinlock_t lock;
427 	struct mmc_request *mrq;
428 	struct mmc_command *cmd;
429 	struct mmc_data *data;
430 	int error;
431 
432 	void __iomem *base;		/* host base address */
433 	void __iomem *top_base;		/* host top register base address */
434 
435 	struct msdc_dma dma;	/* dma channel */
436 	u64 dma_mask;
437 
438 	u32 timeout_ns;		/* data timeout ns */
439 	u32 timeout_clks;	/* data timeout clks */
440 
441 	struct pinctrl *pinctrl;
442 	struct pinctrl_state *pins_default;
443 	struct pinctrl_state *pins_uhs;
444 	struct pinctrl_state *pins_eint;
445 	struct delayed_work req_timeout;
446 	int irq;		/* host interrupt */
447 	int eint_irq;		/* interrupt from sdio device for waking up system */
448 	struct reset_control *reset;
449 
450 	struct clk *src_clk;	/* msdc source clock */
451 	struct clk *h_clk;      /* msdc h_clk */
452 	struct clk *bus_clk;	/* bus clock which used to access register */
453 	struct clk *src_clk_cg; /* msdc source clock control gate */
454 	struct clk *sys_clk_cg;	/* msdc subsys clock control gate */
455 	struct clk *crypto_clk; /* msdc crypto clock control gate */
456 	struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS];
457 	u32 mclk;		/* mmc subsystem clock frequency */
458 	u32 src_clk_freq;	/* source clock frequency */
459 	unsigned char timing;
460 	bool vqmmc_enabled;
461 	u32 latch_ck;
462 	u32 hs400_ds_delay;
463 	u32 hs400_ds_dly3;
464 	u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
465 	u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
466 	bool hs400_cmd_resp_sel_rising;
467 				 /* cmd response sample selection for HS400 */
468 	bool hs400_mode;	/* current eMMC will run at hs400 mode */
469 	bool hs400_tuning;	/* hs400 mode online tuning */
470 	bool internal_cd;	/* Use internal card-detect logic */
471 	bool cqhci;		/* support eMMC hw cmdq */
472 	struct msdc_save_para save_para; /* used when gate HCLK */
473 	struct msdc_tune_para def_tune_para; /* default tune setting */
474 	struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
475 	struct cqhci_host *cq_host;
476 };
477 
478 static const struct mtk_mmc_compatible mt2701_compat = {
479 	.clk_div_bits = 12,
480 	.recheck_sdio_irq = true,
481 	.hs400_tune = false,
482 	.pad_tune_reg = MSDC_PAD_TUNE0,
483 	.async_fifo = true,
484 	.data_tune = true,
485 	.busy_check = false,
486 	.stop_clk_fix = false,
487 	.enhance_rx = false,
488 	.support_64g = false,
489 };
490 
491 static const struct mtk_mmc_compatible mt2712_compat = {
492 	.clk_div_bits = 12,
493 	.recheck_sdio_irq = false,
494 	.hs400_tune = false,
495 	.pad_tune_reg = MSDC_PAD_TUNE0,
496 	.async_fifo = true,
497 	.data_tune = true,
498 	.busy_check = true,
499 	.stop_clk_fix = true,
500 	.enhance_rx = true,
501 	.support_64g = true,
502 };
503 
504 static const struct mtk_mmc_compatible mt6779_compat = {
505 	.clk_div_bits = 12,
506 	.recheck_sdio_irq = false,
507 	.hs400_tune = false,
508 	.pad_tune_reg = MSDC_PAD_TUNE0,
509 	.async_fifo = true,
510 	.data_tune = true,
511 	.busy_check = true,
512 	.stop_clk_fix = true,
513 	.enhance_rx = true,
514 	.support_64g = true,
515 };
516 
517 static const struct mtk_mmc_compatible mt6795_compat = {
518 	.clk_div_bits = 8,
519 	.recheck_sdio_irq = false,
520 	.hs400_tune = true,
521 	.pad_tune_reg = MSDC_PAD_TUNE,
522 	.async_fifo = false,
523 	.data_tune = false,
524 	.busy_check = false,
525 	.stop_clk_fix = false,
526 	.enhance_rx = false,
527 	.support_64g = false,
528 };
529 
530 static const struct mtk_mmc_compatible mt7620_compat = {
531 	.clk_div_bits = 8,
532 	.recheck_sdio_irq = true,
533 	.hs400_tune = false,
534 	.pad_tune_reg = MSDC_PAD_TUNE,
535 	.async_fifo = false,
536 	.data_tune = false,
537 	.busy_check = false,
538 	.stop_clk_fix = false,
539 	.enhance_rx = false,
540 	.use_internal_cd = true,
541 };
542 
543 static const struct mtk_mmc_compatible mt7622_compat = {
544 	.clk_div_bits = 12,
545 	.recheck_sdio_irq = true,
546 	.hs400_tune = false,
547 	.pad_tune_reg = MSDC_PAD_TUNE0,
548 	.async_fifo = true,
549 	.data_tune = true,
550 	.busy_check = true,
551 	.stop_clk_fix = true,
552 	.enhance_rx = true,
553 	.support_64g = false,
554 };
555 
556 static const struct mtk_mmc_compatible mt7986_compat = {
557 	.clk_div_bits = 12,
558 	.recheck_sdio_irq = true,
559 	.hs400_tune = false,
560 	.pad_tune_reg = MSDC_PAD_TUNE0,
561 	.async_fifo = true,
562 	.data_tune = true,
563 	.busy_check = true,
564 	.stop_clk_fix = true,
565 	.enhance_rx = true,
566 	.support_64g = true,
567 };
568 
569 static const struct mtk_mmc_compatible mt8135_compat = {
570 	.clk_div_bits = 8,
571 	.recheck_sdio_irq = true,
572 	.hs400_tune = false,
573 	.pad_tune_reg = MSDC_PAD_TUNE,
574 	.async_fifo = false,
575 	.data_tune = false,
576 	.busy_check = false,
577 	.stop_clk_fix = false,
578 	.enhance_rx = false,
579 	.support_64g = false,
580 };
581 
582 static const struct mtk_mmc_compatible mt8173_compat = {
583 	.clk_div_bits = 8,
584 	.recheck_sdio_irq = true,
585 	.hs400_tune = true,
586 	.pad_tune_reg = MSDC_PAD_TUNE,
587 	.async_fifo = false,
588 	.data_tune = false,
589 	.busy_check = false,
590 	.stop_clk_fix = false,
591 	.enhance_rx = false,
592 	.support_64g = false,
593 };
594 
595 static const struct mtk_mmc_compatible mt8183_compat = {
596 	.clk_div_bits = 12,
597 	.recheck_sdio_irq = false,
598 	.hs400_tune = false,
599 	.pad_tune_reg = MSDC_PAD_TUNE0,
600 	.async_fifo = true,
601 	.data_tune = true,
602 	.busy_check = true,
603 	.stop_clk_fix = true,
604 	.enhance_rx = true,
605 	.support_64g = true,
606 };
607 
608 static const struct mtk_mmc_compatible mt8516_compat = {
609 	.clk_div_bits = 12,
610 	.recheck_sdio_irq = true,
611 	.hs400_tune = false,
612 	.pad_tune_reg = MSDC_PAD_TUNE0,
613 	.async_fifo = true,
614 	.data_tune = true,
615 	.busy_check = true,
616 	.stop_clk_fix = true,
617 };
618 
619 static const struct of_device_id msdc_of_ids[] = {
620 	{ .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
621 	{ .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
622 	{ .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
623 	{ .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat},
624 	{ .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
625 	{ .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
626 	{ .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat},
627 	{ .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
628 	{ .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
629 	{ .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
630 	{ .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
631 
632 	{}
633 };
634 MODULE_DEVICE_TABLE(of, msdc_of_ids);
635 
636 static void sdr_set_bits(void __iomem *reg, u32 bs)
637 {
638 	u32 val = readl(reg);
639 
640 	val |= bs;
641 	writel(val, reg);
642 }
643 
644 static void sdr_clr_bits(void __iomem *reg, u32 bs)
645 {
646 	u32 val = readl(reg);
647 
648 	val &= ~bs;
649 	writel(val, reg);
650 }
651 
652 static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
653 {
654 	unsigned int tv = readl(reg);
655 
656 	tv &= ~field;
657 	tv |= ((val) << (ffs((unsigned int)field) - 1));
658 	writel(tv, reg);
659 }
660 
661 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
662 {
663 	unsigned int tv = readl(reg);
664 
665 	*val = ((tv & field) >> (ffs((unsigned int)field) - 1));
666 }
667 
668 static void msdc_reset_hw(struct msdc_host *host)
669 {
670 	u32 val;
671 
672 	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
673 	readl_poll_timeout(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0);
674 
675 	sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
676 	readl_poll_timeout(host->base + MSDC_FIFOCS, val,
677 			   !(val & MSDC_FIFOCS_CLR), 0, 0);
678 
679 	val = readl(host->base + MSDC_INT);
680 	writel(val, host->base + MSDC_INT);
681 }
682 
683 static void msdc_cmd_next(struct msdc_host *host,
684 		struct mmc_request *mrq, struct mmc_command *cmd);
685 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb);
686 
687 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
688 			MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
689 			MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
690 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
691 			MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
692 			MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
693 
694 static u8 msdc_dma_calcs(u8 *buf, u32 len)
695 {
696 	u32 i, sum = 0;
697 
698 	for (i = 0; i < len; i++)
699 		sum += buf[i];
700 	return 0xff - (u8) sum;
701 }
702 
703 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
704 		struct mmc_data *data)
705 {
706 	unsigned int j, dma_len;
707 	dma_addr_t dma_address;
708 	u32 dma_ctrl;
709 	struct scatterlist *sg;
710 	struct mt_gpdma_desc *gpd;
711 	struct mt_bdma_desc *bd;
712 
713 	sg = data->sg;
714 
715 	gpd = dma->gpd;
716 	bd = dma->bd;
717 
718 	/* modify gpd */
719 	gpd->gpd_info |= GPDMA_DESC_HWO;
720 	gpd->gpd_info |= GPDMA_DESC_BDP;
721 	/* need to clear first. use these bits to calc checksum */
722 	gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
723 	gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
724 
725 	/* modify bd */
726 	for_each_sg(data->sg, sg, data->sg_count, j) {
727 		dma_address = sg_dma_address(sg);
728 		dma_len = sg_dma_len(sg);
729 
730 		/* init bd */
731 		bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
732 		bd[j].bd_info &= ~BDMA_DESC_DWPAD;
733 		bd[j].ptr = lower_32_bits(dma_address);
734 		if (host->dev_comp->support_64g) {
735 			bd[j].bd_info &= ~BDMA_DESC_PTR_H4;
736 			bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf)
737 					 << 28;
738 		}
739 
740 		if (host->dev_comp->support_64g) {
741 			bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT;
742 			bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT);
743 		} else {
744 			bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
745 			bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
746 		}
747 
748 		if (j == data->sg_count - 1) /* the last bd */
749 			bd[j].bd_info |= BDMA_DESC_EOL;
750 		else
751 			bd[j].bd_info &= ~BDMA_DESC_EOL;
752 
753 		/* checksum need to clear first */
754 		bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
755 		bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
756 	}
757 
758 	sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
759 	dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
760 	dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
761 	dma_ctrl |= (MSDC_BURST_64B << 12 | BIT(8));
762 	writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
763 	if (host->dev_comp->support_64g)
764 		sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT,
765 			      upper_32_bits(dma->gpd_addr) & 0xf);
766 	writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
767 }
768 
769 static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data)
770 {
771 	if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
772 		data->host_cookie |= MSDC_PREPARE_FLAG;
773 		data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
774 					    mmc_get_dma_dir(data));
775 	}
776 }
777 
778 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data)
779 {
780 	if (data->host_cookie & MSDC_ASYNC_FLAG)
781 		return;
782 
783 	if (data->host_cookie & MSDC_PREPARE_FLAG) {
784 		dma_unmap_sg(host->dev, data->sg, data->sg_len,
785 			     mmc_get_dma_dir(data));
786 		data->host_cookie &= ~MSDC_PREPARE_FLAG;
787 	}
788 }
789 
790 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks)
791 {
792 	struct mmc_host *mmc = mmc_from_priv(host);
793 	u64 timeout, clk_ns;
794 	u32 mode = 0;
795 
796 	if (mmc->actual_clock == 0) {
797 		timeout = 0;
798 	} else {
799 		clk_ns  = 1000000000ULL;
800 		do_div(clk_ns, mmc->actual_clock);
801 		timeout = ns + clk_ns - 1;
802 		do_div(timeout, clk_ns);
803 		timeout += clks;
804 		/* in 1048576 sclk cycle unit */
805 		timeout = DIV_ROUND_UP(timeout, BIT(20));
806 		if (host->dev_comp->clk_div_bits == 8)
807 			sdr_get_field(host->base + MSDC_CFG,
808 				      MSDC_CFG_CKMOD, &mode);
809 		else
810 			sdr_get_field(host->base + MSDC_CFG,
811 				      MSDC_CFG_CKMOD_EXTRA, &mode);
812 		/*DDR mode will double the clk cycles for data timeout */
813 		timeout = mode >= 2 ? timeout * 2 : timeout;
814 		timeout = timeout > 1 ? timeout - 1 : 0;
815 	}
816 	return timeout;
817 }
818 
819 /* clock control primitives */
820 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks)
821 {
822 	u64 timeout;
823 
824 	host->timeout_ns = ns;
825 	host->timeout_clks = clks;
826 
827 	timeout = msdc_timeout_cal(host, ns, clks);
828 	sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC,
829 		      (u32)(timeout > 255 ? 255 : timeout));
830 }
831 
832 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks)
833 {
834 	u64 timeout;
835 
836 	timeout = msdc_timeout_cal(host, ns, clks);
837 	sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC,
838 		      (u32)(timeout > 8191 ? 8191 : timeout));
839 }
840 
841 static void msdc_gate_clock(struct msdc_host *host)
842 {
843 	clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks);
844 	clk_disable_unprepare(host->crypto_clk);
845 	clk_disable_unprepare(host->src_clk_cg);
846 	clk_disable_unprepare(host->src_clk);
847 	clk_disable_unprepare(host->bus_clk);
848 	clk_disable_unprepare(host->h_clk);
849 }
850 
851 static int msdc_ungate_clock(struct msdc_host *host)
852 {
853 	u32 val;
854 	int ret;
855 
856 	clk_prepare_enable(host->h_clk);
857 	clk_prepare_enable(host->bus_clk);
858 	clk_prepare_enable(host->src_clk);
859 	clk_prepare_enable(host->src_clk_cg);
860 	clk_prepare_enable(host->crypto_clk);
861 	ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks);
862 	if (ret) {
863 		dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n");
864 		return ret;
865 	}
866 
867 	return readl_poll_timeout(host->base + MSDC_CFG, val,
868 				  (val & MSDC_CFG_CKSTB), 1, 20000);
869 }
870 
871 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
872 {
873 	struct mmc_host *mmc = mmc_from_priv(host);
874 	u32 mode;
875 	u32 flags;
876 	u32 div;
877 	u32 sclk;
878 	u32 tune_reg = host->dev_comp->pad_tune_reg;
879 	u32 val;
880 
881 	if (!hz) {
882 		dev_dbg(host->dev, "set mclk to 0\n");
883 		host->mclk = 0;
884 		mmc->actual_clock = 0;
885 		sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
886 		return;
887 	}
888 
889 	flags = readl(host->base + MSDC_INTEN);
890 	sdr_clr_bits(host->base + MSDC_INTEN, flags);
891 	if (host->dev_comp->clk_div_bits == 8)
892 		sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
893 	else
894 		sdr_clr_bits(host->base + MSDC_CFG,
895 			     MSDC_CFG_HS400_CK_MODE_EXTRA);
896 	if (timing == MMC_TIMING_UHS_DDR50 ||
897 	    timing == MMC_TIMING_MMC_DDR52 ||
898 	    timing == MMC_TIMING_MMC_HS400) {
899 		if (timing == MMC_TIMING_MMC_HS400)
900 			mode = 0x3;
901 		else
902 			mode = 0x2; /* ddr mode and use divisor */
903 
904 		if (hz >= (host->src_clk_freq >> 2)) {
905 			div = 0; /* mean div = 1/4 */
906 			sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
907 		} else {
908 			div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
909 			sclk = (host->src_clk_freq >> 2) / div;
910 			div = (div >> 1);
911 		}
912 
913 		if (timing == MMC_TIMING_MMC_HS400 &&
914 		    hz >= (host->src_clk_freq >> 1)) {
915 			if (host->dev_comp->clk_div_bits == 8)
916 				sdr_set_bits(host->base + MSDC_CFG,
917 					     MSDC_CFG_HS400_CK_MODE);
918 			else
919 				sdr_set_bits(host->base + MSDC_CFG,
920 					     MSDC_CFG_HS400_CK_MODE_EXTRA);
921 			sclk = host->src_clk_freq >> 1;
922 			div = 0; /* div is ignore when bit18 is set */
923 		}
924 	} else if (hz >= host->src_clk_freq) {
925 		mode = 0x1; /* no divisor */
926 		div = 0;
927 		sclk = host->src_clk_freq;
928 	} else {
929 		mode = 0x0; /* use divisor */
930 		if (hz >= (host->src_clk_freq >> 1)) {
931 			div = 0; /* mean div = 1/2 */
932 			sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
933 		} else {
934 			div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
935 			sclk = (host->src_clk_freq >> 2) / div;
936 		}
937 	}
938 	sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
939 
940 	clk_disable_unprepare(host->src_clk_cg);
941 	if (host->dev_comp->clk_div_bits == 8)
942 		sdr_set_field(host->base + MSDC_CFG,
943 			      MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
944 			      (mode << 8) | div);
945 	else
946 		sdr_set_field(host->base + MSDC_CFG,
947 			      MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
948 			      (mode << 12) | div);
949 
950 	clk_prepare_enable(host->src_clk_cg);
951 	readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0);
952 	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
953 	mmc->actual_clock = sclk;
954 	host->mclk = hz;
955 	host->timing = timing;
956 	/* need because clk changed. */
957 	msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
958 	sdr_set_bits(host->base + MSDC_INTEN, flags);
959 
960 	/*
961 	 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
962 	 * tune result of hs200/200Mhz is not suitable for 50Mhz
963 	 */
964 	if (mmc->actual_clock <= 52000000) {
965 		writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
966 		if (host->top_base) {
967 			writel(host->def_tune_para.emmc_top_control,
968 			       host->top_base + EMMC_TOP_CONTROL);
969 			writel(host->def_tune_para.emmc_top_cmd,
970 			       host->top_base + EMMC_TOP_CMD);
971 		} else {
972 			writel(host->def_tune_para.pad_tune,
973 			       host->base + tune_reg);
974 		}
975 	} else {
976 		writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
977 		writel(host->saved_tune_para.pad_cmd_tune,
978 		       host->base + PAD_CMD_TUNE);
979 		if (host->top_base) {
980 			writel(host->saved_tune_para.emmc_top_control,
981 			       host->top_base + EMMC_TOP_CONTROL);
982 			writel(host->saved_tune_para.emmc_top_cmd,
983 			       host->top_base + EMMC_TOP_CMD);
984 		} else {
985 			writel(host->saved_tune_para.pad_tune,
986 			       host->base + tune_reg);
987 		}
988 	}
989 
990 	if (timing == MMC_TIMING_MMC_HS400 &&
991 	    host->dev_comp->hs400_tune)
992 		sdr_set_field(host->base + tune_reg,
993 			      MSDC_PAD_TUNE_CMDRRDLY,
994 			      host->hs400_cmd_int_delay);
995 	dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock,
996 		timing);
997 }
998 
999 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
1000 		struct mmc_command *cmd)
1001 {
1002 	u32 resp;
1003 
1004 	switch (mmc_resp_type(cmd)) {
1005 		/* Actually, R1, R5, R6, R7 are the same */
1006 	case MMC_RSP_R1:
1007 		resp = 0x1;
1008 		break;
1009 	case MMC_RSP_R1B:
1010 		resp = 0x7;
1011 		break;
1012 	case MMC_RSP_R2:
1013 		resp = 0x2;
1014 		break;
1015 	case MMC_RSP_R3:
1016 		resp = 0x3;
1017 		break;
1018 	case MMC_RSP_NONE:
1019 	default:
1020 		resp = 0x0;
1021 		break;
1022 	}
1023 
1024 	return resp;
1025 }
1026 
1027 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
1028 		struct mmc_request *mrq, struct mmc_command *cmd)
1029 {
1030 	struct mmc_host *mmc = mmc_from_priv(host);
1031 	/* rawcmd :
1032 	 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
1033 	 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
1034 	 */
1035 	u32 opcode = cmd->opcode;
1036 	u32 resp = msdc_cmd_find_resp(host, cmd);
1037 	u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
1038 
1039 	host->cmd_rsp = resp;
1040 
1041 	if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
1042 	    opcode == MMC_STOP_TRANSMISSION)
1043 		rawcmd |= BIT(14);
1044 	else if (opcode == SD_SWITCH_VOLTAGE)
1045 		rawcmd |= BIT(30);
1046 	else if (opcode == SD_APP_SEND_SCR ||
1047 		 opcode == SD_APP_SEND_NUM_WR_BLKS ||
1048 		 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
1049 		 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
1050 		 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
1051 		rawcmd |= BIT(11);
1052 
1053 	if (cmd->data) {
1054 		struct mmc_data *data = cmd->data;
1055 
1056 		if (mmc_op_multi(opcode)) {
1057 			if (mmc_card_mmc(mmc->card) && mrq->sbc &&
1058 			    !(mrq->sbc->arg & 0xFFFF0000))
1059 				rawcmd |= BIT(29); /* AutoCMD23 */
1060 		}
1061 
1062 		rawcmd |= ((data->blksz & 0xFFF) << 16);
1063 		if (data->flags & MMC_DATA_WRITE)
1064 			rawcmd |= BIT(13);
1065 		if (data->blocks > 1)
1066 			rawcmd |= BIT(12);
1067 		else
1068 			rawcmd |= BIT(11);
1069 		/* Always use dma mode */
1070 		sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
1071 
1072 		if (host->timeout_ns != data->timeout_ns ||
1073 		    host->timeout_clks != data->timeout_clks)
1074 			msdc_set_timeout(host, data->timeout_ns,
1075 					data->timeout_clks);
1076 
1077 		writel(data->blocks, host->base + SDC_BLK_NUM);
1078 	}
1079 	return rawcmd;
1080 }
1081 
1082 static void msdc_start_data(struct msdc_host *host, struct mmc_command *cmd,
1083 		struct mmc_data *data)
1084 {
1085 	bool read;
1086 
1087 	WARN_ON(host->data);
1088 	host->data = data;
1089 	read = data->flags & MMC_DATA_READ;
1090 
1091 	mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1092 	msdc_dma_setup(host, &host->dma, data);
1093 	sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
1094 	sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
1095 	dev_dbg(host->dev, "DMA start\n");
1096 	dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
1097 			__func__, cmd->opcode, data->blocks, read);
1098 }
1099 
1100 static int msdc_auto_cmd_done(struct msdc_host *host, int events,
1101 		struct mmc_command *cmd)
1102 {
1103 	u32 *rsp = cmd->resp;
1104 
1105 	rsp[0] = readl(host->base + SDC_ACMD_RESP);
1106 
1107 	if (events & MSDC_INT_ACMDRDY) {
1108 		cmd->error = 0;
1109 	} else {
1110 		msdc_reset_hw(host);
1111 		if (events & MSDC_INT_ACMDCRCERR) {
1112 			cmd->error = -EILSEQ;
1113 			host->error |= REQ_STOP_EIO;
1114 		} else if (events & MSDC_INT_ACMDTMO) {
1115 			cmd->error = -ETIMEDOUT;
1116 			host->error |= REQ_STOP_TMO;
1117 		}
1118 		dev_err(host->dev,
1119 			"%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
1120 			__func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
1121 	}
1122 	return cmd->error;
1123 }
1124 
1125 /*
1126  * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost
1127  *
1128  * Host controller may lost interrupt in some special case.
1129  * Add SDIO irq recheck mechanism to make sure all interrupts
1130  * can be processed immediately
1131  */
1132 static void msdc_recheck_sdio_irq(struct msdc_host *host)
1133 {
1134 	struct mmc_host *mmc = mmc_from_priv(host);
1135 	u32 reg_int, reg_inten, reg_ps;
1136 
1137 	if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1138 		reg_inten = readl(host->base + MSDC_INTEN);
1139 		if (reg_inten & MSDC_INTEN_SDIOIRQ) {
1140 			reg_int = readl(host->base + MSDC_INT);
1141 			reg_ps = readl(host->base + MSDC_PS);
1142 			if (!(reg_int & MSDC_INT_SDIOIRQ ||
1143 			      reg_ps & MSDC_PS_DATA1)) {
1144 				__msdc_enable_sdio_irq(host, 0);
1145 				sdio_signal_irq(mmc);
1146 			}
1147 		}
1148 	}
1149 }
1150 
1151 static void msdc_track_cmd_data(struct msdc_host *host, struct mmc_command *cmd)
1152 {
1153 	if (host->error)
1154 		dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
1155 			__func__, cmd->opcode, cmd->arg, host->error);
1156 }
1157 
1158 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
1159 {
1160 	unsigned long flags;
1161 
1162 	/*
1163 	 * No need check the return value of cancel_delayed_work, as only ONE
1164 	 * path will go here!
1165 	 */
1166 	cancel_delayed_work(&host->req_timeout);
1167 
1168 	spin_lock_irqsave(&host->lock, flags);
1169 	host->mrq = NULL;
1170 	spin_unlock_irqrestore(&host->lock, flags);
1171 
1172 	msdc_track_cmd_data(host, mrq->cmd);
1173 	if (mrq->data)
1174 		msdc_unprepare_data(host, mrq->data);
1175 	if (host->error)
1176 		msdc_reset_hw(host);
1177 	mmc_request_done(mmc_from_priv(host), mrq);
1178 	if (host->dev_comp->recheck_sdio_irq)
1179 		msdc_recheck_sdio_irq(host);
1180 }
1181 
1182 /* returns true if command is fully handled; returns false otherwise */
1183 static bool msdc_cmd_done(struct msdc_host *host, int events,
1184 			  struct mmc_request *mrq, struct mmc_command *cmd)
1185 {
1186 	bool done = false;
1187 	bool sbc_error;
1188 	unsigned long flags;
1189 	u32 *rsp;
1190 
1191 	if (mrq->sbc && cmd == mrq->cmd &&
1192 	    (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
1193 				   | MSDC_INT_ACMDTMO)))
1194 		msdc_auto_cmd_done(host, events, mrq->sbc);
1195 
1196 	sbc_error = mrq->sbc && mrq->sbc->error;
1197 
1198 	if (!sbc_error && !(events & (MSDC_INT_CMDRDY
1199 					| MSDC_INT_RSPCRCERR
1200 					| MSDC_INT_CMDTMO)))
1201 		return done;
1202 
1203 	spin_lock_irqsave(&host->lock, flags);
1204 	done = !host->cmd;
1205 	host->cmd = NULL;
1206 	spin_unlock_irqrestore(&host->lock, flags);
1207 
1208 	if (done)
1209 		return true;
1210 	rsp = cmd->resp;
1211 
1212 	sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1213 
1214 	if (cmd->flags & MMC_RSP_PRESENT) {
1215 		if (cmd->flags & MMC_RSP_136) {
1216 			rsp[0] = readl(host->base + SDC_RESP3);
1217 			rsp[1] = readl(host->base + SDC_RESP2);
1218 			rsp[2] = readl(host->base + SDC_RESP1);
1219 			rsp[3] = readl(host->base + SDC_RESP0);
1220 		} else {
1221 			rsp[0] = readl(host->base + SDC_RESP0);
1222 		}
1223 	}
1224 
1225 	if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
1226 		if (events & MSDC_INT_CMDTMO ||
1227 		    (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning))
1228 			/*
1229 			 * should not clear fifo/interrupt as the tune data
1230 			 * may have already come when cmd19/cmd21 gets response
1231 			 * CRC error.
1232 			 */
1233 			msdc_reset_hw(host);
1234 		if (events & MSDC_INT_RSPCRCERR) {
1235 			cmd->error = -EILSEQ;
1236 			host->error |= REQ_CMD_EIO;
1237 		} else if (events & MSDC_INT_CMDTMO) {
1238 			cmd->error = -ETIMEDOUT;
1239 			host->error |= REQ_CMD_TMO;
1240 		}
1241 	}
1242 	if (cmd->error)
1243 		dev_dbg(host->dev,
1244 				"%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
1245 				__func__, cmd->opcode, cmd->arg, rsp[0],
1246 				cmd->error);
1247 
1248 	msdc_cmd_next(host, mrq, cmd);
1249 	return true;
1250 }
1251 
1252 /* It is the core layer's responsibility to ensure card status
1253  * is correct before issue a request. but host design do below
1254  * checks recommended.
1255  */
1256 static inline bool msdc_cmd_is_ready(struct msdc_host *host,
1257 		struct mmc_request *mrq, struct mmc_command *cmd)
1258 {
1259 	u32 val;
1260 	int ret;
1261 
1262 	/* The max busy time we can endure is 20ms */
1263 	ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1264 					!(val & SDC_STS_CMDBUSY), 1, 20000);
1265 	if (ret) {
1266 		dev_err(host->dev, "CMD bus busy detected\n");
1267 		host->error |= REQ_CMD_BUSY;
1268 		msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1269 		return false;
1270 	}
1271 
1272 	if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
1273 		/* R1B or with data, should check SDCBUSY */
1274 		ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1275 						!(val & SDC_STS_SDCBUSY), 1, 20000);
1276 		if (ret) {
1277 			dev_err(host->dev, "Controller busy detected\n");
1278 			host->error |= REQ_CMD_BUSY;
1279 			msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1280 			return false;
1281 		}
1282 	}
1283 	return true;
1284 }
1285 
1286 static void msdc_start_command(struct msdc_host *host,
1287 		struct mmc_request *mrq, struct mmc_command *cmd)
1288 {
1289 	u32 rawcmd;
1290 	unsigned long flags;
1291 
1292 	WARN_ON(host->cmd);
1293 	host->cmd = cmd;
1294 
1295 	mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1296 	if (!msdc_cmd_is_ready(host, mrq, cmd))
1297 		return;
1298 
1299 	if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
1300 	    readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
1301 		dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
1302 		msdc_reset_hw(host);
1303 	}
1304 
1305 	cmd->error = 0;
1306 	rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
1307 
1308 	spin_lock_irqsave(&host->lock, flags);
1309 	sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1310 	spin_unlock_irqrestore(&host->lock, flags);
1311 
1312 	writel(cmd->arg, host->base + SDC_ARG);
1313 	writel(rawcmd, host->base + SDC_CMD);
1314 }
1315 
1316 static void msdc_cmd_next(struct msdc_host *host,
1317 		struct mmc_request *mrq, struct mmc_command *cmd)
1318 {
1319 	if ((cmd->error &&
1320 	    !(cmd->error == -EILSEQ &&
1321 	      (mmc_op_tuning(cmd->opcode) || host->hs400_tuning))) ||
1322 	    (mrq->sbc && mrq->sbc->error))
1323 		msdc_request_done(host, mrq);
1324 	else if (cmd == mrq->sbc)
1325 		msdc_start_command(host, mrq, mrq->cmd);
1326 	else if (!cmd->data)
1327 		msdc_request_done(host, mrq);
1328 	else
1329 		msdc_start_data(host, cmd, cmd->data);
1330 }
1331 
1332 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
1333 {
1334 	struct msdc_host *host = mmc_priv(mmc);
1335 
1336 	host->error = 0;
1337 	WARN_ON(host->mrq);
1338 	host->mrq = mrq;
1339 
1340 	if (mrq->data)
1341 		msdc_prepare_data(host, mrq->data);
1342 
1343 	/* if SBC is required, we have HW option and SW option.
1344 	 * if HW option is enabled, and SBC does not have "special" flags,
1345 	 * use HW option,  otherwise use SW option
1346 	 */
1347 	if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
1348 	    (mrq->sbc->arg & 0xFFFF0000)))
1349 		msdc_start_command(host, mrq, mrq->sbc);
1350 	else
1351 		msdc_start_command(host, mrq, mrq->cmd);
1352 }
1353 
1354 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1355 {
1356 	struct msdc_host *host = mmc_priv(mmc);
1357 	struct mmc_data *data = mrq->data;
1358 
1359 	if (!data)
1360 		return;
1361 
1362 	msdc_prepare_data(host, data);
1363 	data->host_cookie |= MSDC_ASYNC_FLAG;
1364 }
1365 
1366 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1367 		int err)
1368 {
1369 	struct msdc_host *host = mmc_priv(mmc);
1370 	struct mmc_data *data = mrq->data;
1371 
1372 	if (!data)
1373 		return;
1374 
1375 	if (data->host_cookie) {
1376 		data->host_cookie &= ~MSDC_ASYNC_FLAG;
1377 		msdc_unprepare_data(host, data);
1378 	}
1379 }
1380 
1381 static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq)
1382 {
1383 	if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
1384 	    !mrq->sbc)
1385 		msdc_start_command(host, mrq, mrq->stop);
1386 	else
1387 		msdc_request_done(host, mrq);
1388 }
1389 
1390 static void msdc_data_xfer_done(struct msdc_host *host, u32 events,
1391 				struct mmc_request *mrq, struct mmc_data *data)
1392 {
1393 	struct mmc_command *stop;
1394 	unsigned long flags;
1395 	bool done;
1396 	unsigned int check_data = events &
1397 	    (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
1398 	     | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
1399 	     | MSDC_INT_DMA_PROTECT);
1400 	u32 val;
1401 	int ret;
1402 
1403 	spin_lock_irqsave(&host->lock, flags);
1404 	done = !host->data;
1405 	if (check_data)
1406 		host->data = NULL;
1407 	spin_unlock_irqrestore(&host->lock, flags);
1408 
1409 	if (done)
1410 		return;
1411 	stop = data->stop;
1412 
1413 	if (check_data || (stop && stop->error)) {
1414 		dev_dbg(host->dev, "DMA status: 0x%8X\n",
1415 				readl(host->base + MSDC_DMA_CFG));
1416 		sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
1417 				1);
1418 
1419 		ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val,
1420 						!(val & MSDC_DMA_CTRL_STOP), 1, 20000);
1421 		if (ret)
1422 			dev_dbg(host->dev, "DMA stop timed out\n");
1423 
1424 		ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val,
1425 						!(val & MSDC_DMA_CFG_STS), 1, 20000);
1426 		if (ret)
1427 			dev_dbg(host->dev, "DMA inactive timed out\n");
1428 
1429 		sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
1430 		dev_dbg(host->dev, "DMA stop\n");
1431 
1432 		if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
1433 			data->bytes_xfered = data->blocks * data->blksz;
1434 		} else {
1435 			dev_dbg(host->dev, "interrupt events: %x\n", events);
1436 			msdc_reset_hw(host);
1437 			host->error |= REQ_DAT_ERR;
1438 			data->bytes_xfered = 0;
1439 
1440 			if (events & MSDC_INT_DATTMO)
1441 				data->error = -ETIMEDOUT;
1442 			else if (events & MSDC_INT_DATCRCERR)
1443 				data->error = -EILSEQ;
1444 
1445 			dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
1446 				__func__, mrq->cmd->opcode, data->blocks);
1447 			dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
1448 				(int)data->error, data->bytes_xfered);
1449 		}
1450 
1451 		msdc_data_xfer_next(host, mrq);
1452 	}
1453 }
1454 
1455 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1456 {
1457 	u32 val = readl(host->base + SDC_CFG);
1458 
1459 	val &= ~SDC_CFG_BUSWIDTH;
1460 
1461 	switch (width) {
1462 	default:
1463 	case MMC_BUS_WIDTH_1:
1464 		val |= (MSDC_BUS_1BITS << 16);
1465 		break;
1466 	case MMC_BUS_WIDTH_4:
1467 		val |= (MSDC_BUS_4BITS << 16);
1468 		break;
1469 	case MMC_BUS_WIDTH_8:
1470 		val |= (MSDC_BUS_8BITS << 16);
1471 		break;
1472 	}
1473 
1474 	writel(val, host->base + SDC_CFG);
1475 	dev_dbg(host->dev, "Bus Width = %d", width);
1476 }
1477 
1478 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
1479 {
1480 	struct msdc_host *host = mmc_priv(mmc);
1481 	int ret;
1482 
1483 	if (!IS_ERR(mmc->supply.vqmmc)) {
1484 		if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 &&
1485 		    ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) {
1486 			dev_err(host->dev, "Unsupported signal voltage!\n");
1487 			return -EINVAL;
1488 		}
1489 
1490 		ret = mmc_regulator_set_vqmmc(mmc, ios);
1491 		if (ret < 0) {
1492 			dev_dbg(host->dev, "Regulator set error %d (%d)\n",
1493 				ret, ios->signal_voltage);
1494 			return ret;
1495 		}
1496 
1497 		/* Apply different pinctrl settings for different signal voltage */
1498 		if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1499 			pinctrl_select_state(host->pinctrl, host->pins_uhs);
1500 		else
1501 			pinctrl_select_state(host->pinctrl, host->pins_default);
1502 	}
1503 	return 0;
1504 }
1505 
1506 static int msdc_card_busy(struct mmc_host *mmc)
1507 {
1508 	struct msdc_host *host = mmc_priv(mmc);
1509 	u32 status = readl(host->base + MSDC_PS);
1510 
1511 	/* only check if data0 is low */
1512 	return !(status & BIT(16));
1513 }
1514 
1515 static void msdc_request_timeout(struct work_struct *work)
1516 {
1517 	struct msdc_host *host = container_of(work, struct msdc_host,
1518 			req_timeout.work);
1519 
1520 	/* simulate HW timeout status */
1521 	dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1522 	if (host->mrq) {
1523 		dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1524 				host->mrq, host->mrq->cmd->opcode);
1525 		if (host->cmd) {
1526 			dev_err(host->dev, "%s: aborting cmd=%d\n",
1527 					__func__, host->cmd->opcode);
1528 			msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1529 					host->cmd);
1530 		} else if (host->data) {
1531 			dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1532 					__func__, host->mrq->cmd->opcode,
1533 					host->data->blocks);
1534 			msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1535 					host->data);
1536 		}
1537 	}
1538 }
1539 
1540 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb)
1541 {
1542 	if (enb) {
1543 		sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1544 		sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1545 		if (host->dev_comp->recheck_sdio_irq)
1546 			msdc_recheck_sdio_irq(host);
1547 	} else {
1548 		sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1549 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1550 	}
1551 }
1552 
1553 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb)
1554 {
1555 	struct msdc_host *host = mmc_priv(mmc);
1556 	unsigned long flags;
1557 	int ret;
1558 
1559 	spin_lock_irqsave(&host->lock, flags);
1560 	__msdc_enable_sdio_irq(host, enb);
1561 	spin_unlock_irqrestore(&host->lock, flags);
1562 
1563 	if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) {
1564 		if (enb) {
1565 			/*
1566 			 * In dev_pm_set_dedicated_wake_irq_reverse(), eint pin will be set to
1567 			 * GPIO mode. We need to restore it to SDIO DAT1 mode after that.
1568 			 * Since the current pinstate is pins_uhs, to ensure pinctrl select take
1569 			 * affect successfully, we change the pinstate to pins_eint firstly.
1570 			 */
1571 			pinctrl_select_state(host->pinctrl, host->pins_eint);
1572 			ret = dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq);
1573 
1574 			if (ret) {
1575 				dev_err(host->dev, "Failed to register SDIO wakeup irq!\n");
1576 				host->pins_eint = NULL;
1577 				pm_runtime_get_noresume(host->dev);
1578 			} else {
1579 				dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq);
1580 			}
1581 
1582 			pinctrl_select_state(host->pinctrl, host->pins_uhs);
1583 		} else {
1584 			dev_pm_clear_wake_irq(host->dev);
1585 		}
1586 	} else {
1587 		if (enb) {
1588 			/* Ensure host->pins_eint is NULL */
1589 			host->pins_eint = NULL;
1590 			pm_runtime_get_noresume(host->dev);
1591 		} else {
1592 			pm_runtime_put_noidle(host->dev);
1593 		}
1594 	}
1595 }
1596 
1597 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts)
1598 {
1599 	struct mmc_host *mmc = mmc_from_priv(host);
1600 	int cmd_err = 0, dat_err = 0;
1601 
1602 	if (intsts & MSDC_INT_RSPCRCERR) {
1603 		cmd_err = -EILSEQ;
1604 		dev_err(host->dev, "%s: CMD CRC ERR", __func__);
1605 	} else if (intsts & MSDC_INT_CMDTMO) {
1606 		cmd_err = -ETIMEDOUT;
1607 		dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__);
1608 	}
1609 
1610 	if (intsts & MSDC_INT_DATCRCERR) {
1611 		dat_err = -EILSEQ;
1612 		dev_err(host->dev, "%s: DATA CRC ERR", __func__);
1613 	} else if (intsts & MSDC_INT_DATTMO) {
1614 		dat_err = -ETIMEDOUT;
1615 		dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__);
1616 	}
1617 
1618 	if (cmd_err || dat_err) {
1619 		dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x",
1620 			cmd_err, dat_err, intsts);
1621 	}
1622 
1623 	return cqhci_irq(mmc, 0, cmd_err, dat_err);
1624 }
1625 
1626 static irqreturn_t msdc_irq(int irq, void *dev_id)
1627 {
1628 	struct msdc_host *host = (struct msdc_host *) dev_id;
1629 	struct mmc_host *mmc = mmc_from_priv(host);
1630 
1631 	while (true) {
1632 		struct mmc_request *mrq;
1633 		struct mmc_command *cmd;
1634 		struct mmc_data *data;
1635 		u32 events, event_mask;
1636 
1637 		spin_lock(&host->lock);
1638 		events = readl(host->base + MSDC_INT);
1639 		event_mask = readl(host->base + MSDC_INTEN);
1640 		if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1641 			__msdc_enable_sdio_irq(host, 0);
1642 		/* clear interrupts */
1643 		writel(events & event_mask, host->base + MSDC_INT);
1644 
1645 		mrq = host->mrq;
1646 		cmd = host->cmd;
1647 		data = host->data;
1648 		spin_unlock(&host->lock);
1649 
1650 		if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1651 			sdio_signal_irq(mmc);
1652 
1653 		if ((events & event_mask) & MSDC_INT_CDSC) {
1654 			if (host->internal_cd)
1655 				mmc_detect_change(mmc, msecs_to_jiffies(20));
1656 			events &= ~MSDC_INT_CDSC;
1657 		}
1658 
1659 		if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ)))
1660 			break;
1661 
1662 		if ((mmc->caps2 & MMC_CAP2_CQE) &&
1663 		    (events & MSDC_INT_CMDQ)) {
1664 			msdc_cmdq_irq(host, events);
1665 			/* clear interrupts */
1666 			writel(events, host->base + MSDC_INT);
1667 			return IRQ_HANDLED;
1668 		}
1669 
1670 		if (!mrq) {
1671 			dev_err(host->dev,
1672 				"%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1673 				__func__, events, event_mask);
1674 			WARN_ON(1);
1675 			break;
1676 		}
1677 
1678 		dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1679 
1680 		if (cmd)
1681 			msdc_cmd_done(host, events, mrq, cmd);
1682 		else if (data)
1683 			msdc_data_xfer_done(host, events, mrq, data);
1684 	}
1685 
1686 	return IRQ_HANDLED;
1687 }
1688 
1689 static void msdc_init_hw(struct msdc_host *host)
1690 {
1691 	u32 val;
1692 	u32 tune_reg = host->dev_comp->pad_tune_reg;
1693 	struct mmc_host *mmc = mmc_from_priv(host);
1694 
1695 	if (host->reset) {
1696 		reset_control_assert(host->reset);
1697 		usleep_range(10, 50);
1698 		reset_control_deassert(host->reset);
1699 	}
1700 
1701 	/* Configure to MMC/SD mode, clock free running */
1702 	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1703 
1704 	/* Reset */
1705 	msdc_reset_hw(host);
1706 
1707 	/* Disable and clear all interrupts */
1708 	writel(0, host->base + MSDC_INTEN);
1709 	val = readl(host->base + MSDC_INT);
1710 	writel(val, host->base + MSDC_INT);
1711 
1712 	/* Configure card detection */
1713 	if (host->internal_cd) {
1714 		sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE,
1715 			      DEFAULT_DEBOUNCE);
1716 		sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1717 		sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1718 		sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1719 	} else {
1720 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1721 		sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1722 		sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1723 	}
1724 
1725 	if (host->top_base) {
1726 		writel(0, host->top_base + EMMC_TOP_CONTROL);
1727 		writel(0, host->top_base + EMMC_TOP_CMD);
1728 	} else {
1729 		writel(0, host->base + tune_reg);
1730 	}
1731 	writel(0, host->base + MSDC_IOCON);
1732 	sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1733 	writel(0x403c0046, host->base + MSDC_PATCH_BIT);
1734 	sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1735 	writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
1736 	sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1737 
1738 	if (host->dev_comp->stop_clk_fix) {
1739 		sdr_set_field(host->base + MSDC_PATCH_BIT1,
1740 			      MSDC_PATCH_BIT1_STOP_DLY, 3);
1741 		sdr_clr_bits(host->base + SDC_FIFO_CFG,
1742 			     SDC_FIFO_CFG_WRVALIDSEL);
1743 		sdr_clr_bits(host->base + SDC_FIFO_CFG,
1744 			     SDC_FIFO_CFG_RDVALIDSEL);
1745 	}
1746 
1747 	if (host->dev_comp->busy_check)
1748 		sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7));
1749 
1750 	if (host->dev_comp->async_fifo) {
1751 		sdr_set_field(host->base + MSDC_PATCH_BIT2,
1752 			      MSDC_PB2_RESPWAIT, 3);
1753 		if (host->dev_comp->enhance_rx) {
1754 			if (host->top_base)
1755 				sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1756 					     SDC_RX_ENH_EN);
1757 			else
1758 				sdr_set_bits(host->base + SDC_ADV_CFG0,
1759 					     SDC_RX_ENHANCE_EN);
1760 		} else {
1761 			sdr_set_field(host->base + MSDC_PATCH_BIT2,
1762 				      MSDC_PB2_RESPSTSENSEL, 2);
1763 			sdr_set_field(host->base + MSDC_PATCH_BIT2,
1764 				      MSDC_PB2_CRCSTSENSEL, 2);
1765 		}
1766 		/* use async fifo, then no need tune internal delay */
1767 		sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
1768 			     MSDC_PATCH_BIT2_CFGRESP);
1769 		sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1770 			     MSDC_PATCH_BIT2_CFGCRCSTS);
1771 	}
1772 
1773 	if (host->dev_comp->support_64g)
1774 		sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1775 			     MSDC_PB2_SUPPORT_64G);
1776 	if (host->dev_comp->data_tune) {
1777 		if (host->top_base) {
1778 			sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1779 				     PAD_DAT_RD_RXDLY_SEL);
1780 			sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL,
1781 				     DATA_K_VALUE_SEL);
1782 			sdr_set_bits(host->top_base + EMMC_TOP_CMD,
1783 				     PAD_CMD_RD_RXDLY_SEL);
1784 		} else {
1785 			sdr_set_bits(host->base + tune_reg,
1786 				     MSDC_PAD_TUNE_RD_SEL |
1787 				     MSDC_PAD_TUNE_CMD_SEL);
1788 		}
1789 	} else {
1790 		/* choose clock tune */
1791 		if (host->top_base)
1792 			sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1793 				     PAD_RXDLY_SEL);
1794 		else
1795 			sdr_set_bits(host->base + tune_reg,
1796 				     MSDC_PAD_TUNE_RXDLYSEL);
1797 	}
1798 
1799 	if (mmc->caps2 & MMC_CAP2_NO_SDIO) {
1800 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1801 		sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1802 		sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1803 	} else {
1804 		/* Configure to enable SDIO mode, otherwise SDIO CMD5 fails */
1805 		sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1806 
1807 		/* Config SDIO device detect interrupt function */
1808 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1809 		sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1810 	}
1811 
1812 	/* Configure to default data timeout */
1813 	sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1814 
1815 	host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
1816 	host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1817 	if (host->top_base) {
1818 		host->def_tune_para.emmc_top_control =
1819 			readl(host->top_base + EMMC_TOP_CONTROL);
1820 		host->def_tune_para.emmc_top_cmd =
1821 			readl(host->top_base + EMMC_TOP_CMD);
1822 		host->saved_tune_para.emmc_top_control =
1823 			readl(host->top_base + EMMC_TOP_CONTROL);
1824 		host->saved_tune_para.emmc_top_cmd =
1825 			readl(host->top_base + EMMC_TOP_CMD);
1826 	} else {
1827 		host->def_tune_para.pad_tune = readl(host->base + tune_reg);
1828 		host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
1829 	}
1830 	dev_dbg(host->dev, "init hardware done!");
1831 }
1832 
1833 static void msdc_deinit_hw(struct msdc_host *host)
1834 {
1835 	u32 val;
1836 
1837 	if (host->internal_cd) {
1838 		/* Disabled card-detect */
1839 		sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1840 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1841 	}
1842 
1843 	/* Disable and clear all interrupts */
1844 	writel(0, host->base + MSDC_INTEN);
1845 
1846 	val = readl(host->base + MSDC_INT);
1847 	writel(val, host->base + MSDC_INT);
1848 }
1849 
1850 /* init gpd and bd list in msdc_drv_probe */
1851 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1852 {
1853 	struct mt_gpdma_desc *gpd = dma->gpd;
1854 	struct mt_bdma_desc *bd = dma->bd;
1855 	dma_addr_t dma_addr;
1856 	int i;
1857 
1858 	memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
1859 
1860 	dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc);
1861 	gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
1862 	/* gpd->next is must set for desc DMA
1863 	 * That's why must alloc 2 gpd structure.
1864 	 */
1865 	gpd->next = lower_32_bits(dma_addr);
1866 	if (host->dev_comp->support_64g)
1867 		gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1868 
1869 	dma_addr = dma->bd_addr;
1870 	gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */
1871 	if (host->dev_comp->support_64g)
1872 		gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28;
1873 
1874 	memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
1875 	for (i = 0; i < (MAX_BD_NUM - 1); i++) {
1876 		dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1);
1877 		bd[i].next = lower_32_bits(dma_addr);
1878 		if (host->dev_comp->support_64g)
1879 			bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1880 	}
1881 }
1882 
1883 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1884 {
1885 	struct msdc_host *host = mmc_priv(mmc);
1886 	int ret;
1887 
1888 	msdc_set_buswidth(host, ios->bus_width);
1889 
1890 	/* Suspend/Resume will do power off/on */
1891 	switch (ios->power_mode) {
1892 	case MMC_POWER_UP:
1893 		if (!IS_ERR(mmc->supply.vmmc)) {
1894 			msdc_init_hw(host);
1895 			ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1896 					ios->vdd);
1897 			if (ret) {
1898 				dev_err(host->dev, "Failed to set vmmc power!\n");
1899 				return;
1900 			}
1901 		}
1902 		break;
1903 	case MMC_POWER_ON:
1904 		if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1905 			ret = regulator_enable(mmc->supply.vqmmc);
1906 			if (ret)
1907 				dev_err(host->dev, "Failed to set vqmmc power!\n");
1908 			else
1909 				host->vqmmc_enabled = true;
1910 		}
1911 		break;
1912 	case MMC_POWER_OFF:
1913 		if (!IS_ERR(mmc->supply.vmmc))
1914 			mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1915 
1916 		if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1917 			regulator_disable(mmc->supply.vqmmc);
1918 			host->vqmmc_enabled = false;
1919 		}
1920 		break;
1921 	default:
1922 		break;
1923 	}
1924 
1925 	if (host->mclk != ios->clock || host->timing != ios->timing)
1926 		msdc_set_mclk(host, ios->timing, ios->clock);
1927 }
1928 
1929 static u32 test_delay_bit(u32 delay, u32 bit)
1930 {
1931 	bit %= PAD_DELAY_MAX;
1932 	return delay & BIT(bit);
1933 }
1934 
1935 static int get_delay_len(u32 delay, u32 start_bit)
1936 {
1937 	int i;
1938 
1939 	for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
1940 		if (test_delay_bit(delay, start_bit + i) == 0)
1941 			return i;
1942 	}
1943 	return PAD_DELAY_MAX - start_bit;
1944 }
1945 
1946 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
1947 {
1948 	int start = 0, len = 0;
1949 	int start_final = 0, len_final = 0;
1950 	u8 final_phase = 0xff;
1951 	struct msdc_delay_phase delay_phase = { 0, };
1952 
1953 	if (delay == 0) {
1954 		dev_err(host->dev, "phase error: [map:%x]\n", delay);
1955 		delay_phase.final_phase = final_phase;
1956 		return delay_phase;
1957 	}
1958 
1959 	while (start < PAD_DELAY_MAX) {
1960 		len = get_delay_len(delay, start);
1961 		if (len_final < len) {
1962 			start_final = start;
1963 			len_final = len;
1964 		}
1965 		start += len ? len : 1;
1966 		if (len >= 12 && start_final < 4)
1967 			break;
1968 	}
1969 
1970 	/* The rule is that to find the smallest delay cell */
1971 	if (start_final == 0)
1972 		final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
1973 	else
1974 		final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
1975 	dev_dbg(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
1976 		delay, len_final, final_phase);
1977 
1978 	delay_phase.maxlen = len_final;
1979 	delay_phase.start = start_final;
1980 	delay_phase.final_phase = final_phase;
1981 	return delay_phase;
1982 }
1983 
1984 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
1985 {
1986 	u32 tune_reg = host->dev_comp->pad_tune_reg;
1987 
1988 	if (host->top_base)
1989 		sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
1990 			      value);
1991 	else
1992 		sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
1993 			      value);
1994 }
1995 
1996 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
1997 {
1998 	u32 tune_reg = host->dev_comp->pad_tune_reg;
1999 
2000 	if (host->top_base)
2001 		sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
2002 			      PAD_DAT_RD_RXDLY, value);
2003 	else
2004 		sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,
2005 			      value);
2006 }
2007 
2008 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
2009 {
2010 	struct msdc_host *host = mmc_priv(mmc);
2011 	u32 rise_delay = 0, fall_delay = 0;
2012 	struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2013 	struct msdc_delay_phase internal_delay_phase;
2014 	u8 final_delay, final_maxlen;
2015 	u32 internal_delay = 0;
2016 	u32 tune_reg = host->dev_comp->pad_tune_reg;
2017 	int cmd_err;
2018 	int i, j;
2019 
2020 	if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
2021 	    mmc->ios.timing == MMC_TIMING_UHS_SDR104)
2022 		sdr_set_field(host->base + tune_reg,
2023 			      MSDC_PAD_TUNE_CMDRRDLY,
2024 			      host->hs200_cmd_int_delay);
2025 
2026 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2027 	for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2028 		msdc_set_cmd_delay(host, i);
2029 		/*
2030 		 * Using the same parameters, it may sometimes pass the test,
2031 		 * but sometimes it may fail. To make sure the parameters are
2032 		 * more stable, we test each set of parameters 3 times.
2033 		 */
2034 		for (j = 0; j < 3; j++) {
2035 			mmc_send_tuning(mmc, opcode, &cmd_err);
2036 			if (!cmd_err) {
2037 				rise_delay |= BIT(i);
2038 			} else {
2039 				rise_delay &= ~BIT(i);
2040 				break;
2041 			}
2042 		}
2043 	}
2044 	final_rise_delay = get_best_delay(host, rise_delay);
2045 	/* if rising edge has enough margin, then do not scan falling edge */
2046 	if (final_rise_delay.maxlen >= 12 ||
2047 	    (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2048 		goto skip_fall;
2049 
2050 	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2051 	for (i = 0; i < PAD_DELAY_MAX; i++) {
2052 		msdc_set_cmd_delay(host, i);
2053 		/*
2054 		 * Using the same parameters, it may sometimes pass the test,
2055 		 * but sometimes it may fail. To make sure the parameters are
2056 		 * more stable, we test each set of parameters 3 times.
2057 		 */
2058 		for (j = 0; j < 3; j++) {
2059 			mmc_send_tuning(mmc, opcode, &cmd_err);
2060 			if (!cmd_err) {
2061 				fall_delay |= BIT(i);
2062 			} else {
2063 				fall_delay &= ~BIT(i);
2064 				break;
2065 			}
2066 		}
2067 	}
2068 	final_fall_delay = get_best_delay(host, fall_delay);
2069 
2070 skip_fall:
2071 	final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2072 	if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4)
2073 		final_maxlen = final_fall_delay.maxlen;
2074 	if (final_maxlen == final_rise_delay.maxlen) {
2075 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2076 		final_delay = final_rise_delay.final_phase;
2077 	} else {
2078 		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2079 		final_delay = final_fall_delay.final_phase;
2080 	}
2081 	msdc_set_cmd_delay(host, final_delay);
2082 
2083 	if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
2084 		goto skip_internal;
2085 
2086 	for (i = 0; i < PAD_DELAY_MAX; i++) {
2087 		sdr_set_field(host->base + tune_reg,
2088 			      MSDC_PAD_TUNE_CMDRRDLY, i);
2089 		mmc_send_tuning(mmc, opcode, &cmd_err);
2090 		if (!cmd_err)
2091 			internal_delay |= BIT(i);
2092 	}
2093 	dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
2094 	internal_delay_phase = get_best_delay(host, internal_delay);
2095 	sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
2096 		      internal_delay_phase.final_phase);
2097 skip_internal:
2098 	dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2099 	return final_delay == 0xff ? -EIO : 0;
2100 }
2101 
2102 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)
2103 {
2104 	struct msdc_host *host = mmc_priv(mmc);
2105 	u32 cmd_delay = 0;
2106 	struct msdc_delay_phase final_cmd_delay = { 0,};
2107 	u8 final_delay;
2108 	int cmd_err;
2109 	int i, j;
2110 
2111 	/* select EMMC50 PAD CMD tune */
2112 	sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
2113 	sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
2114 
2115 	if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
2116 	    mmc->ios.timing == MMC_TIMING_UHS_SDR104)
2117 		sdr_set_field(host->base + MSDC_PAD_TUNE,
2118 			      MSDC_PAD_TUNE_CMDRRDLY,
2119 			      host->hs200_cmd_int_delay);
2120 
2121 	if (host->hs400_cmd_resp_sel_rising)
2122 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2123 	else
2124 		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2125 	for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2126 		sdr_set_field(host->base + PAD_CMD_TUNE,
2127 			      PAD_CMD_TUNE_RX_DLY3, i);
2128 		/*
2129 		 * Using the same parameters, it may sometimes pass the test,
2130 		 * but sometimes it may fail. To make sure the parameters are
2131 		 * more stable, we test each set of parameters 3 times.
2132 		 */
2133 		for (j = 0; j < 3; j++) {
2134 			mmc_send_tuning(mmc, opcode, &cmd_err);
2135 			if (!cmd_err) {
2136 				cmd_delay |= BIT(i);
2137 			} else {
2138 				cmd_delay &= ~BIT(i);
2139 				break;
2140 			}
2141 		}
2142 	}
2143 	final_cmd_delay = get_best_delay(host, cmd_delay);
2144 	sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
2145 		      final_cmd_delay.final_phase);
2146 	final_delay = final_cmd_delay.final_phase;
2147 
2148 	dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2149 	return final_delay == 0xff ? -EIO : 0;
2150 }
2151 
2152 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
2153 {
2154 	struct msdc_host *host = mmc_priv(mmc);
2155 	u32 rise_delay = 0, fall_delay = 0;
2156 	struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2157 	u8 final_delay, final_maxlen;
2158 	int i, ret;
2159 
2160 	sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2161 		      host->latch_ck);
2162 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2163 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2164 	for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2165 		msdc_set_data_delay(host, i);
2166 		ret = mmc_send_tuning(mmc, opcode, NULL);
2167 		if (!ret)
2168 			rise_delay |= BIT(i);
2169 	}
2170 	final_rise_delay = get_best_delay(host, rise_delay);
2171 	/* if rising edge has enough margin, then do not scan falling edge */
2172 	if (final_rise_delay.maxlen >= 12 ||
2173 	    (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2174 		goto skip_fall;
2175 
2176 	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2177 	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2178 	for (i = 0; i < PAD_DELAY_MAX; i++) {
2179 		msdc_set_data_delay(host, i);
2180 		ret = mmc_send_tuning(mmc, opcode, NULL);
2181 		if (!ret)
2182 			fall_delay |= BIT(i);
2183 	}
2184 	final_fall_delay = get_best_delay(host, fall_delay);
2185 
2186 skip_fall:
2187 	final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2188 	if (final_maxlen == final_rise_delay.maxlen) {
2189 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2190 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2191 		final_delay = final_rise_delay.final_phase;
2192 	} else {
2193 		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2194 		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2195 		final_delay = final_fall_delay.final_phase;
2196 	}
2197 	msdc_set_data_delay(host, final_delay);
2198 
2199 	dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
2200 	return final_delay == 0xff ? -EIO : 0;
2201 }
2202 
2203 /*
2204  * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
2205  * together, which can save the tuning time.
2206  */
2207 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
2208 {
2209 	struct msdc_host *host = mmc_priv(mmc);
2210 	u32 rise_delay = 0, fall_delay = 0;
2211 	struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2212 	u8 final_delay, final_maxlen;
2213 	int i, ret;
2214 
2215 	sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2216 		      host->latch_ck);
2217 
2218 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2219 	sdr_clr_bits(host->base + MSDC_IOCON,
2220 		     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2221 	for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2222 		msdc_set_cmd_delay(host, i);
2223 		msdc_set_data_delay(host, i);
2224 		ret = mmc_send_tuning(mmc, opcode, NULL);
2225 		if (!ret)
2226 			rise_delay |= BIT(i);
2227 	}
2228 	final_rise_delay = get_best_delay(host, rise_delay);
2229 	/* if rising edge has enough margin, then do not scan falling edge */
2230 	if (final_rise_delay.maxlen >= 12 ||
2231 	    (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2232 		goto skip_fall;
2233 
2234 	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2235 	sdr_set_bits(host->base + MSDC_IOCON,
2236 		     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2237 	for (i = 0; i < PAD_DELAY_MAX; i++) {
2238 		msdc_set_cmd_delay(host, i);
2239 		msdc_set_data_delay(host, i);
2240 		ret = mmc_send_tuning(mmc, opcode, NULL);
2241 		if (!ret)
2242 			fall_delay |= BIT(i);
2243 	}
2244 	final_fall_delay = get_best_delay(host, fall_delay);
2245 
2246 skip_fall:
2247 	final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2248 	if (final_maxlen == final_rise_delay.maxlen) {
2249 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2250 		sdr_clr_bits(host->base + MSDC_IOCON,
2251 			     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2252 		final_delay = final_rise_delay.final_phase;
2253 	} else {
2254 		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2255 		sdr_set_bits(host->base + MSDC_IOCON,
2256 			     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2257 		final_delay = final_fall_delay.final_phase;
2258 	}
2259 
2260 	msdc_set_cmd_delay(host, final_delay);
2261 	msdc_set_data_delay(host, final_delay);
2262 
2263 	dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
2264 	return final_delay == 0xff ? -EIO : 0;
2265 }
2266 
2267 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
2268 {
2269 	struct msdc_host *host = mmc_priv(mmc);
2270 	int ret;
2271 	u32 tune_reg = host->dev_comp->pad_tune_reg;
2272 
2273 	if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
2274 		ret = msdc_tune_together(mmc, opcode);
2275 		if (host->hs400_mode) {
2276 			sdr_clr_bits(host->base + MSDC_IOCON,
2277 				     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2278 			msdc_set_data_delay(host, 0);
2279 		}
2280 		goto tune_done;
2281 	}
2282 	if (host->hs400_mode &&
2283 	    host->dev_comp->hs400_tune)
2284 		ret = hs400_tune_response(mmc, opcode);
2285 	else
2286 		ret = msdc_tune_response(mmc, opcode);
2287 	if (ret == -EIO) {
2288 		dev_err(host->dev, "Tune response fail!\n");
2289 		return ret;
2290 	}
2291 	if (host->hs400_mode == false) {
2292 		ret = msdc_tune_data(mmc, opcode);
2293 		if (ret == -EIO)
2294 			dev_err(host->dev, "Tune data fail!\n");
2295 	}
2296 
2297 tune_done:
2298 	host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
2299 	host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
2300 	host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2301 	if (host->top_base) {
2302 		host->saved_tune_para.emmc_top_control = readl(host->top_base +
2303 				EMMC_TOP_CONTROL);
2304 		host->saved_tune_para.emmc_top_cmd = readl(host->top_base +
2305 				EMMC_TOP_CMD);
2306 	}
2307 	return ret;
2308 }
2309 
2310 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2311 {
2312 	struct msdc_host *host = mmc_priv(mmc);
2313 	host->hs400_mode = true;
2314 
2315 	if (host->top_base)
2316 		writel(host->hs400_ds_delay,
2317 		       host->top_base + EMMC50_PAD_DS_TUNE);
2318 	else
2319 		writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
2320 	/* hs400 mode must set it to 0 */
2321 	sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
2322 	/* to improve read performance, set outstanding to 2 */
2323 	sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
2324 
2325 	return 0;
2326 }
2327 
2328 static int msdc_execute_hs400_tuning(struct mmc_host *mmc, struct mmc_card *card)
2329 {
2330 	struct msdc_host *host = mmc_priv(mmc);
2331 	struct msdc_delay_phase dly1_delay;
2332 	u32 val, result_dly1 = 0;
2333 	u8 *ext_csd;
2334 	int i, ret;
2335 
2336 	if (host->top_base) {
2337 		sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE,
2338 			     PAD_DS_DLY_SEL);
2339 		if (host->hs400_ds_dly3)
2340 			sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2341 				      PAD_DS_DLY3, host->hs400_ds_dly3);
2342 	} else {
2343 		sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL);
2344 		if (host->hs400_ds_dly3)
2345 			sdr_set_field(host->base + PAD_DS_TUNE,
2346 				      PAD_DS_TUNE_DLY3, host->hs400_ds_dly3);
2347 	}
2348 
2349 	host->hs400_tuning = true;
2350 	for (i = 0; i < PAD_DELAY_MAX; i++) {
2351 		if (host->top_base)
2352 			sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2353 				      PAD_DS_DLY1, i);
2354 		else
2355 			sdr_set_field(host->base + PAD_DS_TUNE,
2356 				      PAD_DS_TUNE_DLY1, i);
2357 		ret = mmc_get_ext_csd(card, &ext_csd);
2358 		if (!ret) {
2359 			result_dly1 |= BIT(i);
2360 			kfree(ext_csd);
2361 		}
2362 	}
2363 	host->hs400_tuning = false;
2364 
2365 	dly1_delay = get_best_delay(host, result_dly1);
2366 	if (dly1_delay.maxlen == 0) {
2367 		dev_err(host->dev, "Failed to get DLY1 delay!\n");
2368 		goto fail;
2369 	}
2370 	if (host->top_base)
2371 		sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2372 			      PAD_DS_DLY1, dly1_delay.final_phase);
2373 	else
2374 		sdr_set_field(host->base + PAD_DS_TUNE,
2375 			      PAD_DS_TUNE_DLY1, dly1_delay.final_phase);
2376 
2377 	if (host->top_base)
2378 		val = readl(host->top_base + EMMC50_PAD_DS_TUNE);
2379 	else
2380 		val = readl(host->base + PAD_DS_TUNE);
2381 
2382 	dev_info(host->dev, "Final PAD_DS_TUNE: 0x%x\n", val);
2383 
2384 	return 0;
2385 
2386 fail:
2387 	dev_err(host->dev, "Failed to tuning DS pin delay!\n");
2388 	return -EIO;
2389 }
2390 
2391 static void msdc_hw_reset(struct mmc_host *mmc)
2392 {
2393 	struct msdc_host *host = mmc_priv(mmc);
2394 
2395 	sdr_set_bits(host->base + EMMC_IOCON, 1);
2396 	udelay(10); /* 10us is enough */
2397 	sdr_clr_bits(host->base + EMMC_IOCON, 1);
2398 }
2399 
2400 static void msdc_ack_sdio_irq(struct mmc_host *mmc)
2401 {
2402 	unsigned long flags;
2403 	struct msdc_host *host = mmc_priv(mmc);
2404 
2405 	spin_lock_irqsave(&host->lock, flags);
2406 	__msdc_enable_sdio_irq(host, 1);
2407 	spin_unlock_irqrestore(&host->lock, flags);
2408 }
2409 
2410 static int msdc_get_cd(struct mmc_host *mmc)
2411 {
2412 	struct msdc_host *host = mmc_priv(mmc);
2413 	int val;
2414 
2415 	if (mmc->caps & MMC_CAP_NONREMOVABLE)
2416 		return 1;
2417 
2418 	if (!host->internal_cd)
2419 		return mmc_gpio_get_cd(mmc);
2420 
2421 	val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS;
2422 	if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH)
2423 		return !!val;
2424 	else
2425 		return !val;
2426 }
2427 
2428 static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc,
2429 				       struct mmc_ios *ios)
2430 {
2431 	struct msdc_host *host = mmc_priv(mmc);
2432 
2433 	if (ios->enhanced_strobe) {
2434 		msdc_prepare_hs400_tuning(mmc, ios);
2435 		sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1);
2436 		sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1);
2437 		sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1);
2438 
2439 		sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2440 		sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2441 		sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT);
2442 	} else {
2443 		sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0);
2444 		sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0);
2445 		sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0);
2446 
2447 		sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2448 		sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2449 		sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4);
2450 	}
2451 }
2452 
2453 static void msdc_cqe_enable(struct mmc_host *mmc)
2454 {
2455 	struct msdc_host *host = mmc_priv(mmc);
2456 
2457 	/* enable cmdq irq */
2458 	writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN);
2459 	/* enable busy check */
2460 	sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2461 	/* default write data / busy timeout 20s */
2462 	msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0);
2463 	/* default read data timeout 1s */
2464 	msdc_set_timeout(host, 1000000000ULL, 0);
2465 }
2466 
2467 static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery)
2468 {
2469 	struct msdc_host *host = mmc_priv(mmc);
2470 	unsigned int val = 0;
2471 
2472 	/* disable cmdq irq */
2473 	sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ);
2474 	/* disable busy check */
2475 	sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2476 
2477 	val = readl(host->base + MSDC_INT);
2478 	writel(val, host->base + MSDC_INT);
2479 
2480 	if (recovery) {
2481 		sdr_set_field(host->base + MSDC_DMA_CTRL,
2482 			      MSDC_DMA_CTRL_STOP, 1);
2483 		if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val,
2484 			!(val & MSDC_DMA_CTRL_STOP), 1, 3000)))
2485 			return;
2486 		if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val,
2487 			!(val & MSDC_DMA_CFG_STS), 1, 3000)))
2488 			return;
2489 		msdc_reset_hw(host);
2490 	}
2491 }
2492 
2493 static void msdc_cqe_pre_enable(struct mmc_host *mmc)
2494 {
2495 	struct cqhci_host *cq_host = mmc->cqe_private;
2496 	u32 reg;
2497 
2498 	reg = cqhci_readl(cq_host, CQHCI_CFG);
2499 	reg |= CQHCI_ENABLE;
2500 	cqhci_writel(cq_host, reg, CQHCI_CFG);
2501 }
2502 
2503 static void msdc_cqe_post_disable(struct mmc_host *mmc)
2504 {
2505 	struct cqhci_host *cq_host = mmc->cqe_private;
2506 	u32 reg;
2507 
2508 	reg = cqhci_readl(cq_host, CQHCI_CFG);
2509 	reg &= ~CQHCI_ENABLE;
2510 	cqhci_writel(cq_host, reg, CQHCI_CFG);
2511 }
2512 
2513 static const struct mmc_host_ops mt_msdc_ops = {
2514 	.post_req = msdc_post_req,
2515 	.pre_req = msdc_pre_req,
2516 	.request = msdc_ops_request,
2517 	.set_ios = msdc_ops_set_ios,
2518 	.get_ro = mmc_gpio_get_ro,
2519 	.get_cd = msdc_get_cd,
2520 	.hs400_enhanced_strobe = msdc_hs400_enhanced_strobe,
2521 	.enable_sdio_irq = msdc_enable_sdio_irq,
2522 	.ack_sdio_irq = msdc_ack_sdio_irq,
2523 	.start_signal_voltage_switch = msdc_ops_switch_volt,
2524 	.card_busy = msdc_card_busy,
2525 	.execute_tuning = msdc_execute_tuning,
2526 	.prepare_hs400_tuning = msdc_prepare_hs400_tuning,
2527 	.execute_hs400_tuning = msdc_execute_hs400_tuning,
2528 	.card_hw_reset = msdc_hw_reset,
2529 };
2530 
2531 static const struct cqhci_host_ops msdc_cmdq_ops = {
2532 	.enable         = msdc_cqe_enable,
2533 	.disable        = msdc_cqe_disable,
2534 	.pre_enable = msdc_cqe_pre_enable,
2535 	.post_disable = msdc_cqe_post_disable,
2536 };
2537 
2538 static void msdc_of_property_parse(struct platform_device *pdev,
2539 				   struct msdc_host *host)
2540 {
2541 	of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck",
2542 			     &host->latch_ck);
2543 
2544 	of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
2545 			     &host->hs400_ds_delay);
2546 
2547 	of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3",
2548 			     &host->hs400_ds_dly3);
2549 
2550 	of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay",
2551 			     &host->hs200_cmd_int_delay);
2552 
2553 	of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay",
2554 			     &host->hs400_cmd_int_delay);
2555 
2556 	if (of_property_read_bool(pdev->dev.of_node,
2557 				  "mediatek,hs400-cmd-resp-sel-rising"))
2558 		host->hs400_cmd_resp_sel_rising = true;
2559 	else
2560 		host->hs400_cmd_resp_sel_rising = false;
2561 
2562 	if (of_property_read_bool(pdev->dev.of_node,
2563 				  "supports-cqe"))
2564 		host->cqhci = true;
2565 	else
2566 		host->cqhci = false;
2567 }
2568 
2569 static int msdc_of_clock_parse(struct platform_device *pdev,
2570 			       struct msdc_host *host)
2571 {
2572 	int ret;
2573 
2574 	host->src_clk = devm_clk_get(&pdev->dev, "source");
2575 	if (IS_ERR(host->src_clk))
2576 		return PTR_ERR(host->src_clk);
2577 
2578 	host->h_clk = devm_clk_get(&pdev->dev, "hclk");
2579 	if (IS_ERR(host->h_clk))
2580 		return PTR_ERR(host->h_clk);
2581 
2582 	host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk");
2583 	if (IS_ERR(host->bus_clk))
2584 		host->bus_clk = NULL;
2585 
2586 	/*source clock control gate is optional clock*/
2587 	host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg");
2588 	if (IS_ERR(host->src_clk_cg))
2589 		return PTR_ERR(host->src_clk_cg);
2590 
2591 	/*
2592 	 * Fallback for legacy device-trees: src_clk and HCLK use the same
2593 	 * bit to control gating but they are parented to a different mux,
2594 	 * hence if our intention is to gate only the source, required
2595 	 * during a clk mode switch to avoid hw hangs, we need to gate
2596 	 * its parent (specified as a different clock only on new DTs).
2597 	 */
2598 	if (!host->src_clk_cg) {
2599 		host->src_clk_cg = clk_get_parent(host->src_clk);
2600 		if (IS_ERR(host->src_clk_cg))
2601 			return PTR_ERR(host->src_clk_cg);
2602 	}
2603 
2604 	/* If present, always enable for this clock gate */
2605 	host->sys_clk_cg = devm_clk_get_optional_enabled(&pdev->dev, "sys_cg");
2606 	if (IS_ERR(host->sys_clk_cg))
2607 		host->sys_clk_cg = NULL;
2608 
2609 	host->bulk_clks[0].id = "pclk_cg";
2610 	host->bulk_clks[1].id = "axi_cg";
2611 	host->bulk_clks[2].id = "ahb_cg";
2612 	ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS,
2613 					 host->bulk_clks);
2614 	if (ret) {
2615 		dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n");
2616 		return ret;
2617 	}
2618 
2619 	return 0;
2620 }
2621 
2622 static int msdc_drv_probe(struct platform_device *pdev)
2623 {
2624 	struct mmc_host *mmc;
2625 	struct msdc_host *host;
2626 	struct resource *res;
2627 	int ret;
2628 
2629 	if (!pdev->dev.of_node) {
2630 		dev_err(&pdev->dev, "No DT found\n");
2631 		return -EINVAL;
2632 	}
2633 
2634 	/* Allocate MMC host for this device */
2635 	mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
2636 	if (!mmc)
2637 		return -ENOMEM;
2638 
2639 	host = mmc_priv(mmc);
2640 	ret = mmc_of_parse(mmc);
2641 	if (ret)
2642 		goto host_free;
2643 
2644 	host->base = devm_platform_ioremap_resource(pdev, 0);
2645 	if (IS_ERR(host->base)) {
2646 		ret = PTR_ERR(host->base);
2647 		goto host_free;
2648 	}
2649 
2650 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2651 	if (res) {
2652 		host->top_base = devm_ioremap_resource(&pdev->dev, res);
2653 		if (IS_ERR(host->top_base))
2654 			host->top_base = NULL;
2655 	}
2656 
2657 	ret = mmc_regulator_get_supply(mmc);
2658 	if (ret)
2659 		goto host_free;
2660 
2661 	ret = msdc_of_clock_parse(pdev, host);
2662 	if (ret)
2663 		goto host_free;
2664 
2665 	host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
2666 								"hrst");
2667 	if (IS_ERR(host->reset)) {
2668 		ret = PTR_ERR(host->reset);
2669 		goto host_free;
2670 	}
2671 
2672 	/* only eMMC has crypto property */
2673 	if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) {
2674 		host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto");
2675 		if (IS_ERR(host->crypto_clk))
2676 			host->crypto_clk = NULL;
2677 		else
2678 			mmc->caps2 |= MMC_CAP2_CRYPTO;
2679 	}
2680 
2681 	host->irq = platform_get_irq(pdev, 0);
2682 	if (host->irq < 0) {
2683 		ret = -EINVAL;
2684 		goto host_free;
2685 	}
2686 
2687 	host->pinctrl = devm_pinctrl_get(&pdev->dev);
2688 	if (IS_ERR(host->pinctrl)) {
2689 		ret = PTR_ERR(host->pinctrl);
2690 		dev_err(&pdev->dev, "Cannot find pinctrl!\n");
2691 		goto host_free;
2692 	}
2693 
2694 	host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
2695 	if (IS_ERR(host->pins_default)) {
2696 		ret = PTR_ERR(host->pins_default);
2697 		dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
2698 		goto host_free;
2699 	}
2700 
2701 	host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
2702 	if (IS_ERR(host->pins_uhs)) {
2703 		ret = PTR_ERR(host->pins_uhs);
2704 		dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
2705 		goto host_free;
2706 	}
2707 
2708 	/* Support for SDIO eint irq ? */
2709 	if ((mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) && (mmc->pm_caps & MMC_PM_KEEP_POWER)) {
2710 		host->eint_irq = platform_get_irq_byname(pdev, "sdio_wakeup");
2711 		if (host->eint_irq > 0) {
2712 			host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint");
2713 			if (IS_ERR(host->pins_eint)) {
2714 				dev_err(&pdev->dev, "Cannot find pinctrl eint!\n");
2715 				host->pins_eint = NULL;
2716 			} else {
2717 				device_init_wakeup(&pdev->dev, true);
2718 			}
2719 		}
2720 	}
2721 
2722 	msdc_of_property_parse(pdev, host);
2723 
2724 	host->dev = &pdev->dev;
2725 	host->dev_comp = of_device_get_match_data(&pdev->dev);
2726 	host->src_clk_freq = clk_get_rate(host->src_clk);
2727 	/* Set host parameters to mmc */
2728 	mmc->ops = &mt_msdc_ops;
2729 	if (host->dev_comp->clk_div_bits == 8)
2730 		mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
2731 	else
2732 		mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
2733 
2734 	if (!(mmc->caps & MMC_CAP_NONREMOVABLE) &&
2735 	    !mmc_can_gpio_cd(mmc) &&
2736 	    host->dev_comp->use_internal_cd) {
2737 		/*
2738 		 * Is removable but no GPIO declared, so
2739 		 * use internal functionality.
2740 		 */
2741 		host->internal_cd = true;
2742 	}
2743 
2744 	if (mmc->caps & MMC_CAP_SDIO_IRQ)
2745 		mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2746 
2747 	mmc->caps |= MMC_CAP_CMD23;
2748 	if (host->cqhci)
2749 		mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
2750 	/* MMC core transfer sizes tunable parameters */
2751 	mmc->max_segs = MAX_BD_NUM;
2752 	if (host->dev_comp->support_64g)
2753 		mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT;
2754 	else
2755 		mmc->max_seg_size = BDMA_DESC_BUFLEN;
2756 	mmc->max_blk_size = 2048;
2757 	mmc->max_req_size = 512 * 1024;
2758 	mmc->max_blk_count = mmc->max_req_size / 512;
2759 	if (host->dev_comp->support_64g)
2760 		host->dma_mask = DMA_BIT_MASK(36);
2761 	else
2762 		host->dma_mask = DMA_BIT_MASK(32);
2763 	mmc_dev(mmc)->dma_mask = &host->dma_mask;
2764 
2765 	host->timeout_clks = 3 * 1048576;
2766 	host->dma.gpd = dma_alloc_coherent(&pdev->dev,
2767 				2 * sizeof(struct mt_gpdma_desc),
2768 				&host->dma.gpd_addr, GFP_KERNEL);
2769 	host->dma.bd = dma_alloc_coherent(&pdev->dev,
2770 				MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2771 				&host->dma.bd_addr, GFP_KERNEL);
2772 	if (!host->dma.gpd || !host->dma.bd) {
2773 		ret = -ENOMEM;
2774 		goto release_mem;
2775 	}
2776 	msdc_init_gpd_bd(host, &host->dma);
2777 	INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
2778 	spin_lock_init(&host->lock);
2779 
2780 	platform_set_drvdata(pdev, mmc);
2781 	ret = msdc_ungate_clock(host);
2782 	if (ret) {
2783 		dev_err(&pdev->dev, "Cannot ungate clocks!\n");
2784 		goto release_mem;
2785 	}
2786 	msdc_init_hw(host);
2787 
2788 	if (mmc->caps2 & MMC_CAP2_CQE) {
2789 		host->cq_host = devm_kzalloc(mmc->parent,
2790 					     sizeof(*host->cq_host),
2791 					     GFP_KERNEL);
2792 		if (!host->cq_host) {
2793 			ret = -ENOMEM;
2794 			goto host_free;
2795 		}
2796 		host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
2797 		host->cq_host->mmio = host->base + 0x800;
2798 		host->cq_host->ops = &msdc_cmdq_ops;
2799 		ret = cqhci_init(host->cq_host, mmc, true);
2800 		if (ret)
2801 			goto host_free;
2802 		mmc->max_segs = 128;
2803 		/* cqhci 16bit length */
2804 		/* 0 size, means 65536 so we don't have to -1 here */
2805 		mmc->max_seg_size = 64 * 1024;
2806 	}
2807 
2808 	ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
2809 			       IRQF_TRIGGER_NONE, pdev->name, host);
2810 	if (ret)
2811 		goto release;
2812 
2813 	pm_runtime_set_active(host->dev);
2814 	pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
2815 	pm_runtime_use_autosuspend(host->dev);
2816 	pm_runtime_enable(host->dev);
2817 	ret = mmc_add_host(mmc);
2818 
2819 	if (ret)
2820 		goto end;
2821 
2822 	return 0;
2823 end:
2824 	pm_runtime_disable(host->dev);
2825 release:
2826 	platform_set_drvdata(pdev, NULL);
2827 	msdc_deinit_hw(host);
2828 	msdc_gate_clock(host);
2829 release_mem:
2830 	if (host->dma.gpd)
2831 		dma_free_coherent(&pdev->dev,
2832 			2 * sizeof(struct mt_gpdma_desc),
2833 			host->dma.gpd, host->dma.gpd_addr);
2834 	if (host->dma.bd)
2835 		dma_free_coherent(&pdev->dev,
2836 			MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2837 			host->dma.bd, host->dma.bd_addr);
2838 host_free:
2839 	mmc_free_host(mmc);
2840 
2841 	return ret;
2842 }
2843 
2844 static int msdc_drv_remove(struct platform_device *pdev)
2845 {
2846 	struct mmc_host *mmc;
2847 	struct msdc_host *host;
2848 
2849 	mmc = platform_get_drvdata(pdev);
2850 	host = mmc_priv(mmc);
2851 
2852 	pm_runtime_get_sync(host->dev);
2853 
2854 	platform_set_drvdata(pdev, NULL);
2855 	mmc_remove_host(mmc);
2856 	msdc_deinit_hw(host);
2857 	msdc_gate_clock(host);
2858 
2859 	pm_runtime_disable(host->dev);
2860 	pm_runtime_put_noidle(host->dev);
2861 	dma_free_coherent(&pdev->dev,
2862 			2 * sizeof(struct mt_gpdma_desc),
2863 			host->dma.gpd, host->dma.gpd_addr);
2864 	dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2865 			host->dma.bd, host->dma.bd_addr);
2866 
2867 	mmc_free_host(mmc);
2868 
2869 	return 0;
2870 }
2871 
2872 static void msdc_save_reg(struct msdc_host *host)
2873 {
2874 	u32 tune_reg = host->dev_comp->pad_tune_reg;
2875 
2876 	host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
2877 	host->save_para.iocon = readl(host->base + MSDC_IOCON);
2878 	host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
2879 	host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
2880 	host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
2881 	host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
2882 	host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
2883 	host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2884 	host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
2885 	host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
2886 	host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
2887 	if (host->top_base) {
2888 		host->save_para.emmc_top_control =
2889 			readl(host->top_base + EMMC_TOP_CONTROL);
2890 		host->save_para.emmc_top_cmd =
2891 			readl(host->top_base + EMMC_TOP_CMD);
2892 		host->save_para.emmc50_pad_ds_tune =
2893 			readl(host->top_base + EMMC50_PAD_DS_TUNE);
2894 	} else {
2895 		host->save_para.pad_tune = readl(host->base + tune_reg);
2896 	}
2897 }
2898 
2899 static void msdc_restore_reg(struct msdc_host *host)
2900 {
2901 	struct mmc_host *mmc = mmc_from_priv(host);
2902 	u32 tune_reg = host->dev_comp->pad_tune_reg;
2903 
2904 	writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
2905 	writel(host->save_para.iocon, host->base + MSDC_IOCON);
2906 	writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
2907 	writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
2908 	writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
2909 	writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
2910 	writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
2911 	writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
2912 	writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
2913 	writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
2914 	writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
2915 	if (host->top_base) {
2916 		writel(host->save_para.emmc_top_control,
2917 		       host->top_base + EMMC_TOP_CONTROL);
2918 		writel(host->save_para.emmc_top_cmd,
2919 		       host->top_base + EMMC_TOP_CMD);
2920 		writel(host->save_para.emmc50_pad_ds_tune,
2921 		       host->top_base + EMMC50_PAD_DS_TUNE);
2922 	} else {
2923 		writel(host->save_para.pad_tune, host->base + tune_reg);
2924 	}
2925 
2926 	if (sdio_irq_claimed(mmc))
2927 		__msdc_enable_sdio_irq(host, 1);
2928 }
2929 
2930 static int __maybe_unused msdc_runtime_suspend(struct device *dev)
2931 {
2932 	struct mmc_host *mmc = dev_get_drvdata(dev);
2933 	struct msdc_host *host = mmc_priv(mmc);
2934 
2935 	msdc_save_reg(host);
2936 
2937 	if (sdio_irq_claimed(mmc)) {
2938 		if (host->pins_eint) {
2939 			disable_irq(host->irq);
2940 			pinctrl_select_state(host->pinctrl, host->pins_eint);
2941 		}
2942 
2943 		__msdc_enable_sdio_irq(host, 0);
2944 	}
2945 	msdc_gate_clock(host);
2946 	return 0;
2947 }
2948 
2949 static int __maybe_unused msdc_runtime_resume(struct device *dev)
2950 {
2951 	struct mmc_host *mmc = dev_get_drvdata(dev);
2952 	struct msdc_host *host = mmc_priv(mmc);
2953 	int ret;
2954 
2955 	ret = msdc_ungate_clock(host);
2956 	if (ret)
2957 		return ret;
2958 
2959 	msdc_restore_reg(host);
2960 
2961 	if (sdio_irq_claimed(mmc) && host->pins_eint) {
2962 		pinctrl_select_state(host->pinctrl, host->pins_uhs);
2963 		enable_irq(host->irq);
2964 	}
2965 	return 0;
2966 }
2967 
2968 static int __maybe_unused msdc_suspend(struct device *dev)
2969 {
2970 	struct mmc_host *mmc = dev_get_drvdata(dev);
2971 	struct msdc_host *host = mmc_priv(mmc);
2972 	int ret;
2973 	u32 val;
2974 
2975 	if (mmc->caps2 & MMC_CAP2_CQE) {
2976 		ret = cqhci_suspend(mmc);
2977 		if (ret)
2978 			return ret;
2979 		val = readl(host->base + MSDC_INT);
2980 		writel(val, host->base + MSDC_INT);
2981 	}
2982 
2983 	/*
2984 	 * Bump up runtime PM usage counter otherwise dev->power.needs_force_resume will
2985 	 * not be marked as 1, pm_runtime_force_resume() will go out directly.
2986 	 */
2987 	if (sdio_irq_claimed(mmc) && host->pins_eint)
2988 		pm_runtime_get_noresume(dev);
2989 
2990 	return pm_runtime_force_suspend(dev);
2991 }
2992 
2993 static int __maybe_unused msdc_resume(struct device *dev)
2994 {
2995 	struct mmc_host *mmc = dev_get_drvdata(dev);
2996 	struct msdc_host *host = mmc_priv(mmc);
2997 
2998 	if (sdio_irq_claimed(mmc) && host->pins_eint)
2999 		pm_runtime_put_noidle(dev);
3000 
3001 	return pm_runtime_force_resume(dev);
3002 }
3003 
3004 static const struct dev_pm_ops msdc_dev_pm_ops = {
3005 	SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume)
3006 	SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
3007 };
3008 
3009 static struct platform_driver mt_msdc_driver = {
3010 	.probe = msdc_drv_probe,
3011 	.remove = msdc_drv_remove,
3012 	.driver = {
3013 		.name = "mtk-msdc",
3014 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
3015 		.of_match_table = msdc_of_ids,
3016 		.pm = &msdc_dev_pm_ops,
3017 	},
3018 };
3019 
3020 module_platform_driver(mt_msdc_driver);
3021 MODULE_LICENSE("GPL v2");
3022 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");
3023