1 /* 2 * Copyright (c) 2014-2015 MediaTek Inc. 3 * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/ioport.h> 20 #include <linux/irq.h> 21 #include <linux/of_address.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_gpio.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/regulator/consumer.h> 29 #include <linux/slab.h> 30 #include <linux/spinlock.h> 31 #include <linux/interrupt.h> 32 33 #include <linux/mmc/card.h> 34 #include <linux/mmc/core.h> 35 #include <linux/mmc/host.h> 36 #include <linux/mmc/mmc.h> 37 #include <linux/mmc/sd.h> 38 #include <linux/mmc/sdio.h> 39 #include <linux/mmc/slot-gpio.h> 40 41 #define MAX_BD_NUM 1024 42 43 /*--------------------------------------------------------------------------*/ 44 /* Common Definition */ 45 /*--------------------------------------------------------------------------*/ 46 #define MSDC_BUS_1BITS 0x0 47 #define MSDC_BUS_4BITS 0x1 48 #define MSDC_BUS_8BITS 0x2 49 50 #define MSDC_BURST_64B 0x6 51 52 /*--------------------------------------------------------------------------*/ 53 /* Register Offset */ 54 /*--------------------------------------------------------------------------*/ 55 #define MSDC_CFG 0x0 56 #define MSDC_IOCON 0x04 57 #define MSDC_PS 0x08 58 #define MSDC_INT 0x0c 59 #define MSDC_INTEN 0x10 60 #define MSDC_FIFOCS 0x14 61 #define SDC_CFG 0x30 62 #define SDC_CMD 0x34 63 #define SDC_ARG 0x38 64 #define SDC_STS 0x3c 65 #define SDC_RESP0 0x40 66 #define SDC_RESP1 0x44 67 #define SDC_RESP2 0x48 68 #define SDC_RESP3 0x4c 69 #define SDC_BLK_NUM 0x50 70 #define SDC_ADV_CFG0 0x64 71 #define EMMC_IOCON 0x7c 72 #define SDC_ACMD_RESP 0x80 73 #define MSDC_DMA_SA 0x90 74 #define MSDC_DMA_CTRL 0x98 75 #define MSDC_DMA_CFG 0x9c 76 #define MSDC_PATCH_BIT 0xb0 77 #define MSDC_PATCH_BIT1 0xb4 78 #define MSDC_PATCH_BIT2 0xb8 79 #define MSDC_PAD_TUNE 0xec 80 #define MSDC_PAD_TUNE0 0xf0 81 #define PAD_DS_TUNE 0x188 82 #define PAD_CMD_TUNE 0x18c 83 #define EMMC50_CFG0 0x208 84 #define EMMC50_CFG3 0x220 85 #define SDC_FIFO_CFG 0x228 86 87 /*--------------------------------------------------------------------------*/ 88 /* Register Mask */ 89 /*--------------------------------------------------------------------------*/ 90 91 /* MSDC_CFG mask */ 92 #define MSDC_CFG_MODE (0x1 << 0) /* RW */ 93 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ 94 #define MSDC_CFG_RST (0x1 << 2) /* RW */ 95 #define MSDC_CFG_PIO (0x1 << 3) /* RW */ 96 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ 97 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ 98 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ 99 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ 100 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ 101 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ 102 #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */ 103 #define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */ 104 #define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */ 105 #define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */ 106 107 /* MSDC_IOCON mask */ 108 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ 109 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ 110 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ 111 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ 112 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ 113 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ 114 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ 115 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ 116 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ 117 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ 118 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ 119 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ 120 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ 121 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ 122 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ 123 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ 124 125 /* MSDC_PS mask */ 126 #define MSDC_PS_CDEN (0x1 << 0) /* RW */ 127 #define MSDC_PS_CDSTS (0x1 << 1) /* R */ 128 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ 129 #define MSDC_PS_DAT (0xff << 16) /* R */ 130 #define MSDC_PS_CMD (0x1 << 24) /* R */ 131 #define MSDC_PS_WP (0x1 << 31) /* R */ 132 133 /* MSDC_INT mask */ 134 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ 135 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ 136 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ 137 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ 138 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ 139 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ 140 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ 141 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ 142 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ 143 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ 144 #define MSDC_INT_CSTA (0x1 << 11) /* R */ 145 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ 146 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ 147 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ 148 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ 149 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ 150 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ 151 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ 152 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ 153 154 /* MSDC_INTEN mask */ 155 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ 156 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ 157 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ 158 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ 159 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ 160 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ 161 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ 162 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ 163 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ 164 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ 165 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ 166 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ 167 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ 168 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ 169 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ 170 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ 171 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ 172 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ 173 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ 174 175 /* MSDC_FIFOCS mask */ 176 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 177 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 178 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ 179 180 /* SDC_CFG mask */ 181 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ 182 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ 183 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 184 #define SDC_CFG_SDIO (0x1 << 19) /* RW */ 185 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 186 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ 187 #define SDC_CFG_DTOC (0xff << 24) /* RW */ 188 189 /* SDC_STS mask */ 190 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ 191 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 192 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ 193 194 /* SDC_ADV_CFG0 mask */ 195 #define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */ 196 197 /* MSDC_DMA_CTRL mask */ 198 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ 199 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ 200 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ 201 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ 202 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ 203 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ 204 205 /* MSDC_DMA_CFG mask */ 206 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ 207 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ 208 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ 209 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ 210 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ 211 212 /* MSDC_PATCH_BIT mask */ 213 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ 214 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) 215 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) 216 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ 217 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ 218 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ 219 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ 220 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ 221 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ 222 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ 223 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ 224 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ 225 226 #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ 227 228 #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ 229 #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */ 230 #define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */ 231 #define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */ 232 #define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */ 233 234 #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */ 235 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */ 236 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */ 237 #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */ 238 #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */ 239 #define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */ 240 #define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */ 241 #define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */ 242 243 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */ 244 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */ 245 #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */ 246 247 #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */ 248 249 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */ 250 #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ 251 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ 252 253 #define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */ 254 255 #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */ 256 #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */ 257 258 #define REQ_CMD_EIO (0x1 << 0) 259 #define REQ_CMD_TMO (0x1 << 1) 260 #define REQ_DAT_ERR (0x1 << 2) 261 #define REQ_STOP_EIO (0x1 << 3) 262 #define REQ_STOP_TMO (0x1 << 4) 263 #define REQ_CMD_BUSY (0x1 << 5) 264 265 #define MSDC_PREPARE_FLAG (0x1 << 0) 266 #define MSDC_ASYNC_FLAG (0x1 << 1) 267 #define MSDC_MMAP_FLAG (0x1 << 2) 268 269 #define MTK_MMC_AUTOSUSPEND_DELAY 50 270 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 271 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 272 273 #define PAD_DELAY_MAX 32 /* PAD delay cells */ 274 /*--------------------------------------------------------------------------*/ 275 /* Descriptor Structure */ 276 /*--------------------------------------------------------------------------*/ 277 struct mt_gpdma_desc { 278 u32 gpd_info; 279 #define GPDMA_DESC_HWO (0x1 << 0) 280 #define GPDMA_DESC_BDP (0x1 << 1) 281 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 282 #define GPDMA_DESC_INT (0x1 << 16) 283 u32 next; 284 u32 ptr; 285 u32 gpd_data_len; 286 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 287 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ 288 u32 arg; 289 u32 blknum; 290 u32 cmd; 291 }; 292 293 struct mt_bdma_desc { 294 u32 bd_info; 295 #define BDMA_DESC_EOL (0x1 << 0) 296 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 297 #define BDMA_DESC_BLKPAD (0x1 << 17) 298 #define BDMA_DESC_DWPAD (0x1 << 18) 299 u32 next; 300 u32 ptr; 301 u32 bd_data_len; 302 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 303 }; 304 305 struct msdc_dma { 306 struct scatterlist *sg; /* I/O scatter list */ 307 struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 308 struct mt_bdma_desc *bd; /* pointer to bd array */ 309 dma_addr_t gpd_addr; /* the physical address of gpd array */ 310 dma_addr_t bd_addr; /* the physical address of bd array */ 311 }; 312 313 struct msdc_save_para { 314 u32 msdc_cfg; 315 u32 iocon; 316 u32 sdc_cfg; 317 u32 pad_tune; 318 u32 patch_bit0; 319 u32 patch_bit1; 320 u32 patch_bit2; 321 u32 pad_ds_tune; 322 u32 pad_cmd_tune; 323 u32 emmc50_cfg0; 324 u32 emmc50_cfg3; 325 u32 sdc_fifo_cfg; 326 }; 327 328 struct mtk_mmc_compatible { 329 u8 clk_div_bits; 330 bool hs400_tune; /* only used for MT8173 */ 331 u32 pad_tune_reg; 332 bool async_fifo; 333 bool data_tune; 334 bool busy_check; 335 bool stop_clk_fix; 336 bool enhance_rx; 337 }; 338 339 struct msdc_tune_para { 340 u32 iocon; 341 u32 pad_tune; 342 u32 pad_cmd_tune; 343 }; 344 345 struct msdc_delay_phase { 346 u8 maxlen; 347 u8 start; 348 u8 final_phase; 349 }; 350 351 struct msdc_host { 352 struct device *dev; 353 const struct mtk_mmc_compatible *dev_comp; 354 struct mmc_host *mmc; /* mmc structure */ 355 int cmd_rsp; 356 357 spinlock_t lock; 358 struct mmc_request *mrq; 359 struct mmc_command *cmd; 360 struct mmc_data *data; 361 int error; 362 363 void __iomem *base; /* host base address */ 364 365 struct msdc_dma dma; /* dma channel */ 366 u64 dma_mask; 367 368 u32 timeout_ns; /* data timeout ns */ 369 u32 timeout_clks; /* data timeout clks */ 370 371 struct pinctrl *pinctrl; 372 struct pinctrl_state *pins_default; 373 struct pinctrl_state *pins_uhs; 374 struct delayed_work req_timeout; 375 int irq; /* host interrupt */ 376 377 struct clk *src_clk; /* msdc source clock */ 378 struct clk *h_clk; /* msdc h_clk */ 379 struct clk *src_clk_cg; /* msdc source clock control gate */ 380 u32 mclk; /* mmc subsystem clock frequency */ 381 u32 src_clk_freq; /* source clock frequency */ 382 u32 sclk; /* SD/MS bus clock frequency */ 383 unsigned char timing; 384 bool vqmmc_enabled; 385 u32 latch_ck; 386 u32 hs400_ds_delay; 387 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 388 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 389 bool hs400_cmd_resp_sel_rising; 390 /* cmd response sample selection for HS400 */ 391 bool hs400_mode; /* current eMMC will run at hs400 mode */ 392 struct msdc_save_para save_para; /* used when gate HCLK */ 393 struct msdc_tune_para def_tune_para; /* default tune setting */ 394 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 395 }; 396 397 static const struct mtk_mmc_compatible mt8135_compat = { 398 .clk_div_bits = 8, 399 .hs400_tune = false, 400 .pad_tune_reg = MSDC_PAD_TUNE, 401 .async_fifo = false, 402 .data_tune = false, 403 .busy_check = false, 404 .stop_clk_fix = false, 405 .enhance_rx = false, 406 }; 407 408 static const struct mtk_mmc_compatible mt8173_compat = { 409 .clk_div_bits = 8, 410 .hs400_tune = true, 411 .pad_tune_reg = MSDC_PAD_TUNE, 412 .async_fifo = false, 413 .data_tune = false, 414 .busy_check = false, 415 .stop_clk_fix = false, 416 .enhance_rx = false, 417 }; 418 419 static const struct mtk_mmc_compatible mt2701_compat = { 420 .clk_div_bits = 12, 421 .hs400_tune = false, 422 .pad_tune_reg = MSDC_PAD_TUNE0, 423 .async_fifo = true, 424 .data_tune = true, 425 .busy_check = false, 426 .stop_clk_fix = false, 427 .enhance_rx = false, 428 }; 429 430 static const struct mtk_mmc_compatible mt2712_compat = { 431 .clk_div_bits = 12, 432 .hs400_tune = false, 433 .pad_tune_reg = MSDC_PAD_TUNE0, 434 .async_fifo = true, 435 .data_tune = true, 436 .busy_check = true, 437 .stop_clk_fix = true, 438 .enhance_rx = true, 439 }; 440 441 static const struct mtk_mmc_compatible mt7622_compat = { 442 .clk_div_bits = 12, 443 .hs400_tune = false, 444 .pad_tune_reg = MSDC_PAD_TUNE0, 445 .async_fifo = true, 446 .data_tune = true, 447 .busy_check = true, 448 .stop_clk_fix = true, 449 .enhance_rx = true, 450 }; 451 452 static const struct of_device_id msdc_of_ids[] = { 453 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, 454 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, 455 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, 456 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, 457 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, 458 {} 459 }; 460 MODULE_DEVICE_TABLE(of, msdc_of_ids); 461 462 static void sdr_set_bits(void __iomem *reg, u32 bs) 463 { 464 u32 val = readl(reg); 465 466 val |= bs; 467 writel(val, reg); 468 } 469 470 static void sdr_clr_bits(void __iomem *reg, u32 bs) 471 { 472 u32 val = readl(reg); 473 474 val &= ~bs; 475 writel(val, reg); 476 } 477 478 static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 479 { 480 unsigned int tv = readl(reg); 481 482 tv &= ~field; 483 tv |= ((val) << (ffs((unsigned int)field) - 1)); 484 writel(tv, reg); 485 } 486 487 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 488 { 489 unsigned int tv = readl(reg); 490 491 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 492 } 493 494 static void msdc_reset_hw(struct msdc_host *host) 495 { 496 u32 val; 497 498 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 499 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) 500 cpu_relax(); 501 502 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 503 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) 504 cpu_relax(); 505 506 val = readl(host->base + MSDC_INT); 507 writel(val, host->base + MSDC_INT); 508 } 509 510 static void msdc_cmd_next(struct msdc_host *host, 511 struct mmc_request *mrq, struct mmc_command *cmd); 512 513 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 514 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 515 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 516 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 517 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 518 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 519 520 static u8 msdc_dma_calcs(u8 *buf, u32 len) 521 { 522 u32 i, sum = 0; 523 524 for (i = 0; i < len; i++) 525 sum += buf[i]; 526 return 0xff - (u8) sum; 527 } 528 529 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 530 struct mmc_data *data) 531 { 532 unsigned int j, dma_len; 533 dma_addr_t dma_address; 534 u32 dma_ctrl; 535 struct scatterlist *sg; 536 struct mt_gpdma_desc *gpd; 537 struct mt_bdma_desc *bd; 538 539 sg = data->sg; 540 541 gpd = dma->gpd; 542 bd = dma->bd; 543 544 /* modify gpd */ 545 gpd->gpd_info |= GPDMA_DESC_HWO; 546 gpd->gpd_info |= GPDMA_DESC_BDP; 547 /* need to clear first. use these bits to calc checksum */ 548 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 549 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 550 551 /* modify bd */ 552 for_each_sg(data->sg, sg, data->sg_count, j) { 553 dma_address = sg_dma_address(sg); 554 dma_len = sg_dma_len(sg); 555 556 /* init bd */ 557 bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 558 bd[j].bd_info &= ~BDMA_DESC_DWPAD; 559 bd[j].ptr = (u32)dma_address; 560 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 561 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 562 563 if (j == data->sg_count - 1) /* the last bd */ 564 bd[j].bd_info |= BDMA_DESC_EOL; 565 else 566 bd[j].bd_info &= ~BDMA_DESC_EOL; 567 568 /* checksume need to clear first */ 569 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 570 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 571 } 572 573 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 574 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 575 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 576 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); 577 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 578 writel((u32)dma->gpd_addr, host->base + MSDC_DMA_SA); 579 } 580 581 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq) 582 { 583 struct mmc_data *data = mrq->data; 584 585 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 586 data->host_cookie |= MSDC_PREPARE_FLAG; 587 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 588 mmc_get_dma_dir(data)); 589 } 590 } 591 592 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) 593 { 594 struct mmc_data *data = mrq->data; 595 596 if (data->host_cookie & MSDC_ASYNC_FLAG) 597 return; 598 599 if (data->host_cookie & MSDC_PREPARE_FLAG) { 600 dma_unmap_sg(host->dev, data->sg, data->sg_len, 601 mmc_get_dma_dir(data)); 602 data->host_cookie &= ~MSDC_PREPARE_FLAG; 603 } 604 } 605 606 /* clock control primitives */ 607 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) 608 { 609 u32 timeout, clk_ns; 610 u32 mode = 0; 611 612 host->timeout_ns = ns; 613 host->timeout_clks = clks; 614 if (host->sclk == 0) { 615 timeout = 0; 616 } else { 617 clk_ns = 1000000000UL / host->sclk; 618 timeout = (ns + clk_ns - 1) / clk_ns + clks; 619 /* in 1048576 sclk cycle unit */ 620 timeout = (timeout + (0x1 << 20) - 1) >> 20; 621 if (host->dev_comp->clk_div_bits == 8) 622 sdr_get_field(host->base + MSDC_CFG, 623 MSDC_CFG_CKMOD, &mode); 624 else 625 sdr_get_field(host->base + MSDC_CFG, 626 MSDC_CFG_CKMOD_EXTRA, &mode); 627 /*DDR mode will double the clk cycles for data timeout */ 628 timeout = mode >= 2 ? timeout * 2 : timeout; 629 timeout = timeout > 1 ? timeout - 1 : 0; 630 timeout = timeout > 255 ? 255 : timeout; 631 } 632 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout); 633 } 634 635 static void msdc_gate_clock(struct msdc_host *host) 636 { 637 clk_disable_unprepare(host->src_clk_cg); 638 clk_disable_unprepare(host->src_clk); 639 clk_disable_unprepare(host->h_clk); 640 } 641 642 static void msdc_ungate_clock(struct msdc_host *host) 643 { 644 clk_prepare_enable(host->h_clk); 645 clk_prepare_enable(host->src_clk); 646 clk_prepare_enable(host->src_clk_cg); 647 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 648 cpu_relax(); 649 } 650 651 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 652 { 653 u32 mode; 654 u32 flags; 655 u32 div; 656 u32 sclk; 657 u32 tune_reg = host->dev_comp->pad_tune_reg; 658 659 if (!hz) { 660 dev_dbg(host->dev, "set mclk to 0\n"); 661 host->mclk = 0; 662 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 663 return; 664 } 665 666 flags = readl(host->base + MSDC_INTEN); 667 sdr_clr_bits(host->base + MSDC_INTEN, flags); 668 if (host->dev_comp->clk_div_bits == 8) 669 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 670 else 671 sdr_clr_bits(host->base + MSDC_CFG, 672 MSDC_CFG_HS400_CK_MODE_EXTRA); 673 if (timing == MMC_TIMING_UHS_DDR50 || 674 timing == MMC_TIMING_MMC_DDR52 || 675 timing == MMC_TIMING_MMC_HS400) { 676 if (timing == MMC_TIMING_MMC_HS400) 677 mode = 0x3; 678 else 679 mode = 0x2; /* ddr mode and use divisor */ 680 681 if (hz >= (host->src_clk_freq >> 2)) { 682 div = 0; /* mean div = 1/4 */ 683 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 684 } else { 685 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 686 sclk = (host->src_clk_freq >> 2) / div; 687 div = (div >> 1); 688 } 689 690 if (timing == MMC_TIMING_MMC_HS400 && 691 hz >= (host->src_clk_freq >> 1)) { 692 if (host->dev_comp->clk_div_bits == 8) 693 sdr_set_bits(host->base + MSDC_CFG, 694 MSDC_CFG_HS400_CK_MODE); 695 else 696 sdr_set_bits(host->base + MSDC_CFG, 697 MSDC_CFG_HS400_CK_MODE_EXTRA); 698 sclk = host->src_clk_freq >> 1; 699 div = 0; /* div is ignore when bit18 is set */ 700 } 701 } else if (hz >= host->src_clk_freq) { 702 mode = 0x1; /* no divisor */ 703 div = 0; 704 sclk = host->src_clk_freq; 705 } else { 706 mode = 0x0; /* use divisor */ 707 if (hz >= (host->src_clk_freq >> 1)) { 708 div = 0; /* mean div = 1/2 */ 709 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 710 } else { 711 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 712 sclk = (host->src_clk_freq >> 2) / div; 713 } 714 } 715 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 716 /* 717 * As src_clk/HCLK use the same bit to gate/ungate, 718 * So if want to only gate src_clk, need gate its parent(mux). 719 */ 720 if (host->src_clk_cg) 721 clk_disable_unprepare(host->src_clk_cg); 722 else 723 clk_disable_unprepare(clk_get_parent(host->src_clk)); 724 if (host->dev_comp->clk_div_bits == 8) 725 sdr_set_field(host->base + MSDC_CFG, 726 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 727 (mode << 8) | div); 728 else 729 sdr_set_field(host->base + MSDC_CFG, 730 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, 731 (mode << 12) | div); 732 if (host->src_clk_cg) 733 clk_prepare_enable(host->src_clk_cg); 734 else 735 clk_prepare_enable(clk_get_parent(host->src_clk)); 736 737 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 738 cpu_relax(); 739 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 740 host->sclk = sclk; 741 host->mclk = hz; 742 host->timing = timing; 743 /* need because clk changed. */ 744 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 745 sdr_set_bits(host->base + MSDC_INTEN, flags); 746 747 /* 748 * mmc_select_hs400() will drop to 50Mhz and High speed mode, 749 * tune result of hs200/200Mhz is not suitable for 50Mhz 750 */ 751 if (host->sclk <= 52000000) { 752 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 753 writel(host->def_tune_para.pad_tune, host->base + tune_reg); 754 } else { 755 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 756 writel(host->saved_tune_para.pad_tune, host->base + tune_reg); 757 writel(host->saved_tune_para.pad_cmd_tune, 758 host->base + PAD_CMD_TUNE); 759 } 760 761 if (timing == MMC_TIMING_MMC_HS400 && 762 host->dev_comp->hs400_tune) 763 sdr_set_field(host->base + PAD_CMD_TUNE, 764 MSDC_PAD_TUNE_CMDRRDLY, 765 host->hs400_cmd_int_delay); 766 dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->sclk, timing); 767 } 768 769 static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 770 struct mmc_request *mrq, struct mmc_command *cmd) 771 { 772 u32 resp; 773 774 switch (mmc_resp_type(cmd)) { 775 /* Actually, R1, R5, R6, R7 are the same */ 776 case MMC_RSP_R1: 777 resp = 0x1; 778 break; 779 case MMC_RSP_R1B: 780 resp = 0x7; 781 break; 782 case MMC_RSP_R2: 783 resp = 0x2; 784 break; 785 case MMC_RSP_R3: 786 resp = 0x3; 787 break; 788 case MMC_RSP_NONE: 789 default: 790 resp = 0x0; 791 break; 792 } 793 794 return resp; 795 } 796 797 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 798 struct mmc_request *mrq, struct mmc_command *cmd) 799 { 800 /* rawcmd : 801 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 802 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 803 */ 804 u32 opcode = cmd->opcode; 805 u32 resp = msdc_cmd_find_resp(host, mrq, cmd); 806 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 807 808 host->cmd_rsp = resp; 809 810 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 811 opcode == MMC_STOP_TRANSMISSION) 812 rawcmd |= (0x1 << 14); 813 else if (opcode == SD_SWITCH_VOLTAGE) 814 rawcmd |= (0x1 << 30); 815 else if (opcode == SD_APP_SEND_SCR || 816 opcode == SD_APP_SEND_NUM_WR_BLKS || 817 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 818 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 819 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 820 rawcmd |= (0x1 << 11); 821 822 if (cmd->data) { 823 struct mmc_data *data = cmd->data; 824 825 if (mmc_op_multi(opcode)) { 826 if (mmc_card_mmc(host->mmc->card) && mrq->sbc && 827 !(mrq->sbc->arg & 0xFFFF0000)) 828 rawcmd |= 0x2 << 28; /* AutoCMD23 */ 829 } 830 831 rawcmd |= ((data->blksz & 0xFFF) << 16); 832 if (data->flags & MMC_DATA_WRITE) 833 rawcmd |= (0x1 << 13); 834 if (data->blocks > 1) 835 rawcmd |= (0x2 << 11); 836 else 837 rawcmd |= (0x1 << 11); 838 /* Always use dma mode */ 839 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 840 841 if (host->timeout_ns != data->timeout_ns || 842 host->timeout_clks != data->timeout_clks) 843 msdc_set_timeout(host, data->timeout_ns, 844 data->timeout_clks); 845 846 writel(data->blocks, host->base + SDC_BLK_NUM); 847 } 848 return rawcmd; 849 } 850 851 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, 852 struct mmc_command *cmd, struct mmc_data *data) 853 { 854 bool read; 855 856 WARN_ON(host->data); 857 host->data = data; 858 read = data->flags & MMC_DATA_READ; 859 860 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 861 msdc_dma_setup(host, &host->dma, data); 862 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 863 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 864 dev_dbg(host->dev, "DMA start\n"); 865 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 866 __func__, cmd->opcode, data->blocks, read); 867 } 868 869 static int msdc_auto_cmd_done(struct msdc_host *host, int events, 870 struct mmc_command *cmd) 871 { 872 u32 *rsp = cmd->resp; 873 874 rsp[0] = readl(host->base + SDC_ACMD_RESP); 875 876 if (events & MSDC_INT_ACMDRDY) { 877 cmd->error = 0; 878 } else { 879 msdc_reset_hw(host); 880 if (events & MSDC_INT_ACMDCRCERR) { 881 cmd->error = -EILSEQ; 882 host->error |= REQ_STOP_EIO; 883 } else if (events & MSDC_INT_ACMDTMO) { 884 cmd->error = -ETIMEDOUT; 885 host->error |= REQ_STOP_TMO; 886 } 887 dev_err(host->dev, 888 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 889 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 890 } 891 return cmd->error; 892 } 893 894 static void msdc_track_cmd_data(struct msdc_host *host, 895 struct mmc_command *cmd, struct mmc_data *data) 896 { 897 if (host->error) 898 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 899 __func__, cmd->opcode, cmd->arg, host->error); 900 } 901 902 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 903 { 904 unsigned long flags; 905 bool ret; 906 907 ret = cancel_delayed_work(&host->req_timeout); 908 if (!ret) { 909 /* delay work already running */ 910 return; 911 } 912 spin_lock_irqsave(&host->lock, flags); 913 host->mrq = NULL; 914 spin_unlock_irqrestore(&host->lock, flags); 915 916 msdc_track_cmd_data(host, mrq->cmd, mrq->data); 917 if (mrq->data) 918 msdc_unprepare_data(host, mrq); 919 mmc_request_done(host->mmc, mrq); 920 } 921 922 /* returns true if command is fully handled; returns false otherwise */ 923 static bool msdc_cmd_done(struct msdc_host *host, int events, 924 struct mmc_request *mrq, struct mmc_command *cmd) 925 { 926 bool done = false; 927 bool sbc_error; 928 unsigned long flags; 929 u32 *rsp = cmd->resp; 930 931 if (mrq->sbc && cmd == mrq->cmd && 932 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 933 | MSDC_INT_ACMDTMO))) 934 msdc_auto_cmd_done(host, events, mrq->sbc); 935 936 sbc_error = mrq->sbc && mrq->sbc->error; 937 938 if (!sbc_error && !(events & (MSDC_INT_CMDRDY 939 | MSDC_INT_RSPCRCERR 940 | MSDC_INT_CMDTMO))) 941 return done; 942 943 spin_lock_irqsave(&host->lock, flags); 944 done = !host->cmd; 945 host->cmd = NULL; 946 spin_unlock_irqrestore(&host->lock, flags); 947 948 if (done) 949 return true; 950 951 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 952 953 if (cmd->flags & MMC_RSP_PRESENT) { 954 if (cmd->flags & MMC_RSP_136) { 955 rsp[0] = readl(host->base + SDC_RESP3); 956 rsp[1] = readl(host->base + SDC_RESP2); 957 rsp[2] = readl(host->base + SDC_RESP1); 958 rsp[3] = readl(host->base + SDC_RESP0); 959 } else { 960 rsp[0] = readl(host->base + SDC_RESP0); 961 } 962 } 963 964 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 965 if (cmd->opcode != MMC_SEND_TUNING_BLOCK && 966 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200) 967 /* 968 * should not clear fifo/interrupt as the tune data 969 * may have alreay come. 970 */ 971 msdc_reset_hw(host); 972 if (events & MSDC_INT_RSPCRCERR) { 973 cmd->error = -EILSEQ; 974 host->error |= REQ_CMD_EIO; 975 } else if (events & MSDC_INT_CMDTMO) { 976 cmd->error = -ETIMEDOUT; 977 host->error |= REQ_CMD_TMO; 978 } 979 } 980 if (cmd->error) 981 dev_dbg(host->dev, 982 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 983 __func__, cmd->opcode, cmd->arg, rsp[0], 984 cmd->error); 985 986 msdc_cmd_next(host, mrq, cmd); 987 return true; 988 } 989 990 /* It is the core layer's responsibility to ensure card status 991 * is correct before issue a request. but host design do below 992 * checks recommended. 993 */ 994 static inline bool msdc_cmd_is_ready(struct msdc_host *host, 995 struct mmc_request *mrq, struct mmc_command *cmd) 996 { 997 /* The max busy time we can endure is 20ms */ 998 unsigned long tmo = jiffies + msecs_to_jiffies(20); 999 1000 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && 1001 time_before(jiffies, tmo)) 1002 cpu_relax(); 1003 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { 1004 dev_err(host->dev, "CMD bus busy detected\n"); 1005 host->error |= REQ_CMD_BUSY; 1006 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1007 return false; 1008 } 1009 1010 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 1011 tmo = jiffies + msecs_to_jiffies(20); 1012 /* R1B or with data, should check SDCBUSY */ 1013 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && 1014 time_before(jiffies, tmo)) 1015 cpu_relax(); 1016 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { 1017 dev_err(host->dev, "Controller busy detected\n"); 1018 host->error |= REQ_CMD_BUSY; 1019 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1020 return false; 1021 } 1022 } 1023 return true; 1024 } 1025 1026 static void msdc_start_command(struct msdc_host *host, 1027 struct mmc_request *mrq, struct mmc_command *cmd) 1028 { 1029 u32 rawcmd; 1030 1031 WARN_ON(host->cmd); 1032 host->cmd = cmd; 1033 1034 if (!msdc_cmd_is_ready(host, mrq, cmd)) 1035 return; 1036 1037 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 1038 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 1039 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 1040 msdc_reset_hw(host); 1041 } 1042 1043 cmd->error = 0; 1044 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 1045 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1046 1047 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1048 writel(cmd->arg, host->base + SDC_ARG); 1049 writel(rawcmd, host->base + SDC_CMD); 1050 } 1051 1052 static void msdc_cmd_next(struct msdc_host *host, 1053 struct mmc_request *mrq, struct mmc_command *cmd) 1054 { 1055 if ((cmd->error && 1056 !(cmd->error == -EILSEQ && 1057 (cmd->opcode == MMC_SEND_TUNING_BLOCK || 1058 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) || 1059 (mrq->sbc && mrq->sbc->error)) 1060 msdc_request_done(host, mrq); 1061 else if (cmd == mrq->sbc) 1062 msdc_start_command(host, mrq, mrq->cmd); 1063 else if (!cmd->data) 1064 msdc_request_done(host, mrq); 1065 else 1066 msdc_start_data(host, mrq, cmd, cmd->data); 1067 } 1068 1069 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 1070 { 1071 struct msdc_host *host = mmc_priv(mmc); 1072 1073 host->error = 0; 1074 WARN_ON(host->mrq); 1075 host->mrq = mrq; 1076 1077 if (mrq->data) 1078 msdc_prepare_data(host, mrq); 1079 1080 /* if SBC is required, we have HW option and SW option. 1081 * if HW option is enabled, and SBC does not have "special" flags, 1082 * use HW option, otherwise use SW option 1083 */ 1084 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 1085 (mrq->sbc->arg & 0xFFFF0000))) 1086 msdc_start_command(host, mrq, mrq->sbc); 1087 else 1088 msdc_start_command(host, mrq, mrq->cmd); 1089 } 1090 1091 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 1092 { 1093 struct msdc_host *host = mmc_priv(mmc); 1094 struct mmc_data *data = mrq->data; 1095 1096 if (!data) 1097 return; 1098 1099 msdc_prepare_data(host, mrq); 1100 data->host_cookie |= MSDC_ASYNC_FLAG; 1101 } 1102 1103 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1104 int err) 1105 { 1106 struct msdc_host *host = mmc_priv(mmc); 1107 struct mmc_data *data; 1108 1109 data = mrq->data; 1110 if (!data) 1111 return; 1112 if (data->host_cookie) { 1113 data->host_cookie &= ~MSDC_ASYNC_FLAG; 1114 msdc_unprepare_data(host, mrq); 1115 } 1116 } 1117 1118 static void msdc_data_xfer_next(struct msdc_host *host, 1119 struct mmc_request *mrq, struct mmc_data *data) 1120 { 1121 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 1122 !mrq->sbc) 1123 msdc_start_command(host, mrq, mrq->stop); 1124 else 1125 msdc_request_done(host, mrq); 1126 } 1127 1128 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 1129 struct mmc_request *mrq, struct mmc_data *data) 1130 { 1131 struct mmc_command *stop = data->stop; 1132 unsigned long flags; 1133 bool done; 1134 unsigned int check_data = events & 1135 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 1136 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 1137 | MSDC_INT_DMA_PROTECT); 1138 1139 spin_lock_irqsave(&host->lock, flags); 1140 done = !host->data; 1141 if (check_data) 1142 host->data = NULL; 1143 spin_unlock_irqrestore(&host->lock, flags); 1144 1145 if (done) 1146 return true; 1147 1148 if (check_data || (stop && stop->error)) { 1149 dev_dbg(host->dev, "DMA status: 0x%8X\n", 1150 readl(host->base + MSDC_DMA_CFG)); 1151 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1152 1); 1153 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) 1154 cpu_relax(); 1155 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 1156 dev_dbg(host->dev, "DMA stop\n"); 1157 1158 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 1159 data->bytes_xfered = data->blocks * data->blksz; 1160 } else { 1161 dev_dbg(host->dev, "interrupt events: %x\n", events); 1162 msdc_reset_hw(host); 1163 host->error |= REQ_DAT_ERR; 1164 data->bytes_xfered = 0; 1165 1166 if (events & MSDC_INT_DATTMO) 1167 data->error = -ETIMEDOUT; 1168 else if (events & MSDC_INT_DATCRCERR) 1169 data->error = -EILSEQ; 1170 1171 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 1172 __func__, mrq->cmd->opcode, data->blocks); 1173 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 1174 (int)data->error, data->bytes_xfered); 1175 } 1176 1177 msdc_data_xfer_next(host, mrq, data); 1178 done = true; 1179 } 1180 return done; 1181 } 1182 1183 static void msdc_set_buswidth(struct msdc_host *host, u32 width) 1184 { 1185 u32 val = readl(host->base + SDC_CFG); 1186 1187 val &= ~SDC_CFG_BUSWIDTH; 1188 1189 switch (width) { 1190 default: 1191 case MMC_BUS_WIDTH_1: 1192 val |= (MSDC_BUS_1BITS << 16); 1193 break; 1194 case MMC_BUS_WIDTH_4: 1195 val |= (MSDC_BUS_4BITS << 16); 1196 break; 1197 case MMC_BUS_WIDTH_8: 1198 val |= (MSDC_BUS_8BITS << 16); 1199 break; 1200 } 1201 1202 writel(val, host->base + SDC_CFG); 1203 dev_dbg(host->dev, "Bus Width = %d", width); 1204 } 1205 1206 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 1207 { 1208 struct msdc_host *host = mmc_priv(mmc); 1209 int ret = 0; 1210 1211 if (!IS_ERR(mmc->supply.vqmmc)) { 1212 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1213 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 1214 dev_err(host->dev, "Unsupported signal voltage!\n"); 1215 return -EINVAL; 1216 } 1217 1218 ret = mmc_regulator_set_vqmmc(mmc, ios); 1219 if (ret) { 1220 dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1221 ret, ios->signal_voltage); 1222 } else { 1223 /* Apply different pinctrl settings for different signal voltage */ 1224 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 1225 pinctrl_select_state(host->pinctrl, host->pins_uhs); 1226 else 1227 pinctrl_select_state(host->pinctrl, host->pins_default); 1228 } 1229 } 1230 return ret; 1231 } 1232 1233 static int msdc_card_busy(struct mmc_host *mmc) 1234 { 1235 struct msdc_host *host = mmc_priv(mmc); 1236 u32 status = readl(host->base + MSDC_PS); 1237 1238 /* only check if data0 is low */ 1239 return !(status & BIT(16)); 1240 } 1241 1242 static void msdc_request_timeout(struct work_struct *work) 1243 { 1244 struct msdc_host *host = container_of(work, struct msdc_host, 1245 req_timeout.work); 1246 1247 /* simulate HW timeout status */ 1248 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 1249 if (host->mrq) { 1250 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 1251 host->mrq, host->mrq->cmd->opcode); 1252 if (host->cmd) { 1253 dev_err(host->dev, "%s: aborting cmd=%d\n", 1254 __func__, host->cmd->opcode); 1255 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 1256 host->cmd); 1257 } else if (host->data) { 1258 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 1259 __func__, host->mrq->cmd->opcode, 1260 host->data->blocks); 1261 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 1262 host->data); 1263 } 1264 } 1265 } 1266 1267 static irqreturn_t msdc_irq(int irq, void *dev_id) 1268 { 1269 struct msdc_host *host = (struct msdc_host *) dev_id; 1270 1271 while (true) { 1272 unsigned long flags; 1273 struct mmc_request *mrq; 1274 struct mmc_command *cmd; 1275 struct mmc_data *data; 1276 u32 events, event_mask; 1277 1278 spin_lock_irqsave(&host->lock, flags); 1279 events = readl(host->base + MSDC_INT); 1280 event_mask = readl(host->base + MSDC_INTEN); 1281 /* clear interrupts */ 1282 writel(events & event_mask, host->base + MSDC_INT); 1283 1284 mrq = host->mrq; 1285 cmd = host->cmd; 1286 data = host->data; 1287 spin_unlock_irqrestore(&host->lock, flags); 1288 1289 if (!(events & event_mask)) 1290 break; 1291 1292 if (!mrq) { 1293 dev_err(host->dev, 1294 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 1295 __func__, events, event_mask); 1296 WARN_ON(1); 1297 break; 1298 } 1299 1300 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 1301 1302 if (cmd) 1303 msdc_cmd_done(host, events, mrq, cmd); 1304 else if (data) 1305 msdc_data_xfer_done(host, events, mrq, data); 1306 } 1307 1308 return IRQ_HANDLED; 1309 } 1310 1311 static void msdc_init_hw(struct msdc_host *host) 1312 { 1313 u32 val; 1314 u32 tune_reg = host->dev_comp->pad_tune_reg; 1315 1316 /* Configure to MMC/SD mode, clock free running */ 1317 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 1318 1319 /* Reset */ 1320 msdc_reset_hw(host); 1321 1322 /* Disable card detection */ 1323 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1324 1325 /* Disable and clear all interrupts */ 1326 writel(0, host->base + MSDC_INTEN); 1327 val = readl(host->base + MSDC_INT); 1328 writel(val, host->base + MSDC_INT); 1329 1330 writel(0, host->base + tune_reg); 1331 writel(0, host->base + MSDC_IOCON); 1332 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 1333 writel(0x403c0046, host->base + MSDC_PATCH_BIT); 1334 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 1335 writel(0xffff4089, host->base + MSDC_PATCH_BIT1); 1336 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1337 1338 if (host->dev_comp->stop_clk_fix) { 1339 sdr_set_field(host->base + MSDC_PATCH_BIT1, 1340 MSDC_PATCH_BIT1_STOP_DLY, 3); 1341 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1342 SDC_FIFO_CFG_WRVALIDSEL); 1343 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1344 SDC_FIFO_CFG_RDVALIDSEL); 1345 } 1346 1347 if (host->dev_comp->busy_check) 1348 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7)); 1349 1350 if (host->dev_comp->async_fifo) { 1351 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1352 MSDC_PB2_RESPWAIT, 3); 1353 if (host->dev_comp->enhance_rx) { 1354 sdr_set_bits(host->base + SDC_ADV_CFG0, 1355 SDC_RX_ENHANCE_EN); 1356 } else { 1357 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1358 MSDC_PB2_RESPSTSENSEL, 2); 1359 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1360 MSDC_PB2_CRCSTSENSEL, 2); 1361 } 1362 /* use async fifo, then no need tune internal delay */ 1363 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, 1364 MSDC_PATCH_BIT2_CFGRESP); 1365 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1366 MSDC_PATCH_BIT2_CFGCRCSTS); 1367 } 1368 1369 if (host->dev_comp->data_tune) { 1370 sdr_set_bits(host->base + tune_reg, 1371 MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL); 1372 } else { 1373 /* choose clock tune */ 1374 sdr_set_bits(host->base + tune_reg, MSDC_PAD_TUNE_RXDLYSEL); 1375 } 1376 1377 /* Configure to enable SDIO mode. 1378 * it's must otherwise sdio cmd5 failed 1379 */ 1380 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1381 1382 /* disable detect SDIO device interrupt function */ 1383 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1384 1385 /* Configure to default data timeout */ 1386 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 1387 1388 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 1389 host->def_tune_para.pad_tune = readl(host->base + tune_reg); 1390 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1391 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 1392 dev_dbg(host->dev, "init hardware done!"); 1393 } 1394 1395 static void msdc_deinit_hw(struct msdc_host *host) 1396 { 1397 u32 val; 1398 /* Disable and clear all interrupts */ 1399 writel(0, host->base + MSDC_INTEN); 1400 1401 val = readl(host->base + MSDC_INT); 1402 writel(val, host->base + MSDC_INT); 1403 } 1404 1405 /* init gpd and bd list in msdc_drv_probe */ 1406 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 1407 { 1408 struct mt_gpdma_desc *gpd = dma->gpd; 1409 struct mt_bdma_desc *bd = dma->bd; 1410 int i; 1411 1412 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 1413 1414 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 1415 gpd->ptr = (u32)dma->bd_addr; /* physical address */ 1416 /* gpd->next is must set for desc DMA 1417 * That's why must alloc 2 gpd structure. 1418 */ 1419 gpd->next = (u32)dma->gpd_addr + sizeof(struct mt_gpdma_desc); 1420 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 1421 for (i = 0; i < (MAX_BD_NUM - 1); i++) 1422 bd[i].next = (u32)dma->bd_addr + sizeof(*bd) * (i + 1); 1423 } 1424 1425 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1426 { 1427 struct msdc_host *host = mmc_priv(mmc); 1428 int ret; 1429 1430 msdc_set_buswidth(host, ios->bus_width); 1431 1432 /* Suspend/Resume will do power off/on */ 1433 switch (ios->power_mode) { 1434 case MMC_POWER_UP: 1435 if (!IS_ERR(mmc->supply.vmmc)) { 1436 msdc_init_hw(host); 1437 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1438 ios->vdd); 1439 if (ret) { 1440 dev_err(host->dev, "Failed to set vmmc power!\n"); 1441 return; 1442 } 1443 } 1444 break; 1445 case MMC_POWER_ON: 1446 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1447 ret = regulator_enable(mmc->supply.vqmmc); 1448 if (ret) 1449 dev_err(host->dev, "Failed to set vqmmc power!\n"); 1450 else 1451 host->vqmmc_enabled = true; 1452 } 1453 break; 1454 case MMC_POWER_OFF: 1455 if (!IS_ERR(mmc->supply.vmmc)) 1456 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1457 1458 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1459 regulator_disable(mmc->supply.vqmmc); 1460 host->vqmmc_enabled = false; 1461 } 1462 break; 1463 default: 1464 break; 1465 } 1466 1467 if (host->mclk != ios->clock || host->timing != ios->timing) 1468 msdc_set_mclk(host, ios->timing, ios->clock); 1469 } 1470 1471 static u32 test_delay_bit(u32 delay, u32 bit) 1472 { 1473 bit %= PAD_DELAY_MAX; 1474 return delay & (1 << bit); 1475 } 1476 1477 static int get_delay_len(u32 delay, u32 start_bit) 1478 { 1479 int i; 1480 1481 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 1482 if (test_delay_bit(delay, start_bit + i) == 0) 1483 return i; 1484 } 1485 return PAD_DELAY_MAX - start_bit; 1486 } 1487 1488 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 1489 { 1490 int start = 0, len = 0; 1491 int start_final = 0, len_final = 0; 1492 u8 final_phase = 0xff; 1493 struct msdc_delay_phase delay_phase = { 0, }; 1494 1495 if (delay == 0) { 1496 dev_err(host->dev, "phase error: [map:%x]\n", delay); 1497 delay_phase.final_phase = final_phase; 1498 return delay_phase; 1499 } 1500 1501 while (start < PAD_DELAY_MAX) { 1502 len = get_delay_len(delay, start); 1503 if (len_final < len) { 1504 start_final = start; 1505 len_final = len; 1506 } 1507 start += len ? len : 1; 1508 if (len >= 12 && start_final < 4) 1509 break; 1510 } 1511 1512 /* The rule is that to find the smallest delay cell */ 1513 if (start_final == 0) 1514 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 1515 else 1516 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 1517 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 1518 delay, len_final, final_phase); 1519 1520 delay_phase.maxlen = len_final; 1521 delay_phase.start = start_final; 1522 delay_phase.final_phase = final_phase; 1523 return delay_phase; 1524 } 1525 1526 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 1527 { 1528 struct msdc_host *host = mmc_priv(mmc); 1529 u32 rise_delay = 0, fall_delay = 0; 1530 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1531 struct msdc_delay_phase internal_delay_phase; 1532 u8 final_delay, final_maxlen; 1533 u32 internal_delay = 0; 1534 u32 tune_reg = host->dev_comp->pad_tune_reg; 1535 int cmd_err; 1536 int i, j; 1537 1538 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 1539 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 1540 sdr_set_field(host->base + tune_reg, 1541 MSDC_PAD_TUNE_CMDRRDLY, 1542 host->hs200_cmd_int_delay); 1543 1544 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1545 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1546 sdr_set_field(host->base + tune_reg, 1547 MSDC_PAD_TUNE_CMDRDLY, i); 1548 /* 1549 * Using the same parameters, it may sometimes pass the test, 1550 * but sometimes it may fail. To make sure the parameters are 1551 * more stable, we test each set of parameters 3 times. 1552 */ 1553 for (j = 0; j < 3; j++) { 1554 mmc_send_tuning(mmc, opcode, &cmd_err); 1555 if (!cmd_err) { 1556 rise_delay |= (1 << i); 1557 } else { 1558 rise_delay &= ~(1 << i); 1559 break; 1560 } 1561 } 1562 } 1563 final_rise_delay = get_best_delay(host, rise_delay); 1564 /* if rising edge has enough margin, then do not scan falling edge */ 1565 if (final_rise_delay.maxlen >= 12 || 1566 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1567 goto skip_fall; 1568 1569 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1570 for (i = 0; i < PAD_DELAY_MAX; i++) { 1571 sdr_set_field(host->base + tune_reg, 1572 MSDC_PAD_TUNE_CMDRDLY, i); 1573 /* 1574 * Using the same parameters, it may sometimes pass the test, 1575 * but sometimes it may fail. To make sure the parameters are 1576 * more stable, we test each set of parameters 3 times. 1577 */ 1578 for (j = 0; j < 3; j++) { 1579 mmc_send_tuning(mmc, opcode, &cmd_err); 1580 if (!cmd_err) { 1581 fall_delay |= (1 << i); 1582 } else { 1583 fall_delay &= ~(1 << i); 1584 break; 1585 } 1586 } 1587 } 1588 final_fall_delay = get_best_delay(host, fall_delay); 1589 1590 skip_fall: 1591 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1592 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 1593 final_maxlen = final_fall_delay.maxlen; 1594 if (final_maxlen == final_rise_delay.maxlen) { 1595 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1596 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1597 final_rise_delay.final_phase); 1598 final_delay = final_rise_delay.final_phase; 1599 } else { 1600 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1601 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1602 final_fall_delay.final_phase); 1603 final_delay = final_fall_delay.final_phase; 1604 } 1605 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) 1606 goto skip_internal; 1607 1608 for (i = 0; i < PAD_DELAY_MAX; i++) { 1609 sdr_set_field(host->base + tune_reg, 1610 MSDC_PAD_TUNE_CMDRRDLY, i); 1611 mmc_send_tuning(mmc, opcode, &cmd_err); 1612 if (!cmd_err) 1613 internal_delay |= (1 << i); 1614 } 1615 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 1616 internal_delay_phase = get_best_delay(host, internal_delay); 1617 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 1618 internal_delay_phase.final_phase); 1619 skip_internal: 1620 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 1621 return final_delay == 0xff ? -EIO : 0; 1622 } 1623 1624 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 1625 { 1626 struct msdc_host *host = mmc_priv(mmc); 1627 u32 cmd_delay = 0; 1628 struct msdc_delay_phase final_cmd_delay = { 0,}; 1629 u8 final_delay; 1630 int cmd_err; 1631 int i, j; 1632 1633 /* select EMMC50 PAD CMD tune */ 1634 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 1635 1636 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 1637 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 1638 sdr_set_field(host->base + MSDC_PAD_TUNE, 1639 MSDC_PAD_TUNE_CMDRRDLY, 1640 host->hs200_cmd_int_delay); 1641 1642 if (host->hs400_cmd_resp_sel_rising) 1643 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1644 else 1645 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1646 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1647 sdr_set_field(host->base + PAD_CMD_TUNE, 1648 PAD_CMD_TUNE_RX_DLY3, i); 1649 /* 1650 * Using the same parameters, it may sometimes pass the test, 1651 * but sometimes it may fail. To make sure the parameters are 1652 * more stable, we test each set of parameters 3 times. 1653 */ 1654 for (j = 0; j < 3; j++) { 1655 mmc_send_tuning(mmc, opcode, &cmd_err); 1656 if (!cmd_err) { 1657 cmd_delay |= (1 << i); 1658 } else { 1659 cmd_delay &= ~(1 << i); 1660 break; 1661 } 1662 } 1663 } 1664 final_cmd_delay = get_best_delay(host, cmd_delay); 1665 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 1666 final_cmd_delay.final_phase); 1667 final_delay = final_cmd_delay.final_phase; 1668 1669 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 1670 return final_delay == 0xff ? -EIO : 0; 1671 } 1672 1673 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 1674 { 1675 struct msdc_host *host = mmc_priv(mmc); 1676 u32 rise_delay = 0, fall_delay = 0; 1677 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1678 u8 final_delay, final_maxlen; 1679 u32 tune_reg = host->dev_comp->pad_tune_reg; 1680 int i, ret; 1681 1682 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 1683 host->latch_ck); 1684 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1685 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1686 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1687 sdr_set_field(host->base + tune_reg, 1688 MSDC_PAD_TUNE_DATRRDLY, i); 1689 ret = mmc_send_tuning(mmc, opcode, NULL); 1690 if (!ret) 1691 rise_delay |= (1 << i); 1692 } 1693 final_rise_delay = get_best_delay(host, rise_delay); 1694 /* if rising edge has enough margin, then do not scan falling edge */ 1695 if (final_rise_delay.maxlen >= 12 || 1696 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1697 goto skip_fall; 1698 1699 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1700 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1701 for (i = 0; i < PAD_DELAY_MAX; i++) { 1702 sdr_set_field(host->base + tune_reg, 1703 MSDC_PAD_TUNE_DATRRDLY, i); 1704 ret = mmc_send_tuning(mmc, opcode, NULL); 1705 if (!ret) 1706 fall_delay |= (1 << i); 1707 } 1708 final_fall_delay = get_best_delay(host, fall_delay); 1709 1710 skip_fall: 1711 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1712 if (final_maxlen == final_rise_delay.maxlen) { 1713 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1714 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1715 sdr_set_field(host->base + tune_reg, 1716 MSDC_PAD_TUNE_DATRRDLY, 1717 final_rise_delay.final_phase); 1718 final_delay = final_rise_delay.final_phase; 1719 } else { 1720 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1721 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1722 sdr_set_field(host->base + tune_reg, 1723 MSDC_PAD_TUNE_DATRRDLY, 1724 final_fall_delay.final_phase); 1725 final_delay = final_fall_delay.final_phase; 1726 } 1727 1728 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 1729 return final_delay == 0xff ? -EIO : 0; 1730 } 1731 1732 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1733 { 1734 struct msdc_host *host = mmc_priv(mmc); 1735 int ret; 1736 u32 tune_reg = host->dev_comp->pad_tune_reg; 1737 1738 if (host->hs400_mode && 1739 host->dev_comp->hs400_tune) 1740 ret = hs400_tune_response(mmc, opcode); 1741 else 1742 ret = msdc_tune_response(mmc, opcode); 1743 if (ret == -EIO) { 1744 dev_err(host->dev, "Tune response fail!\n"); 1745 return ret; 1746 } 1747 if (host->hs400_mode == false) { 1748 ret = msdc_tune_data(mmc, opcode); 1749 if (ret == -EIO) 1750 dev_err(host->dev, "Tune data fail!\n"); 1751 } 1752 1753 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1754 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 1755 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 1756 return ret; 1757 } 1758 1759 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 1760 { 1761 struct msdc_host *host = mmc_priv(mmc); 1762 host->hs400_mode = true; 1763 1764 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 1765 /* hs400 mode must set it to 0 */ 1766 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); 1767 /* to improve read performance, set outstanding to 2 */ 1768 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); 1769 1770 return 0; 1771 } 1772 1773 static void msdc_hw_reset(struct mmc_host *mmc) 1774 { 1775 struct msdc_host *host = mmc_priv(mmc); 1776 1777 sdr_set_bits(host->base + EMMC_IOCON, 1); 1778 udelay(10); /* 10us is enough */ 1779 sdr_clr_bits(host->base + EMMC_IOCON, 1); 1780 } 1781 1782 static const struct mmc_host_ops mt_msdc_ops = { 1783 .post_req = msdc_post_req, 1784 .pre_req = msdc_pre_req, 1785 .request = msdc_ops_request, 1786 .set_ios = msdc_ops_set_ios, 1787 .get_ro = mmc_gpio_get_ro, 1788 .get_cd = mmc_gpio_get_cd, 1789 .start_signal_voltage_switch = msdc_ops_switch_volt, 1790 .card_busy = msdc_card_busy, 1791 .execute_tuning = msdc_execute_tuning, 1792 .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 1793 .hw_reset = msdc_hw_reset, 1794 }; 1795 1796 static void msdc_of_property_parse(struct platform_device *pdev, 1797 struct msdc_host *host) 1798 { 1799 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", 1800 &host->latch_ck); 1801 1802 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 1803 &host->hs400_ds_delay); 1804 1805 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 1806 &host->hs200_cmd_int_delay); 1807 1808 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 1809 &host->hs400_cmd_int_delay); 1810 1811 if (of_property_read_bool(pdev->dev.of_node, 1812 "mediatek,hs400-cmd-resp-sel-rising")) 1813 host->hs400_cmd_resp_sel_rising = true; 1814 else 1815 host->hs400_cmd_resp_sel_rising = false; 1816 } 1817 1818 static int msdc_drv_probe(struct platform_device *pdev) 1819 { 1820 struct mmc_host *mmc; 1821 struct msdc_host *host; 1822 struct resource *res; 1823 const struct of_device_id *of_id; 1824 int ret; 1825 1826 if (!pdev->dev.of_node) { 1827 dev_err(&pdev->dev, "No DT found\n"); 1828 return -EINVAL; 1829 } 1830 1831 of_id = of_match_node(msdc_of_ids, pdev->dev.of_node); 1832 if (!of_id) 1833 return -EINVAL; 1834 /* Allocate MMC host for this device */ 1835 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 1836 if (!mmc) 1837 return -ENOMEM; 1838 1839 host = mmc_priv(mmc); 1840 ret = mmc_of_parse(mmc); 1841 if (ret) 1842 goto host_free; 1843 1844 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1845 host->base = devm_ioremap_resource(&pdev->dev, res); 1846 if (IS_ERR(host->base)) { 1847 ret = PTR_ERR(host->base); 1848 goto host_free; 1849 } 1850 1851 ret = mmc_regulator_get_supply(mmc); 1852 if (ret) 1853 goto host_free; 1854 1855 host->src_clk = devm_clk_get(&pdev->dev, "source"); 1856 if (IS_ERR(host->src_clk)) { 1857 ret = PTR_ERR(host->src_clk); 1858 goto host_free; 1859 } 1860 1861 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 1862 if (IS_ERR(host->h_clk)) { 1863 ret = PTR_ERR(host->h_clk); 1864 goto host_free; 1865 } 1866 1867 /*source clock control gate is optional clock*/ 1868 host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg"); 1869 if (IS_ERR(host->src_clk_cg)) 1870 host->src_clk_cg = NULL; 1871 1872 host->irq = platform_get_irq(pdev, 0); 1873 if (host->irq < 0) { 1874 ret = -EINVAL; 1875 goto host_free; 1876 } 1877 1878 host->pinctrl = devm_pinctrl_get(&pdev->dev); 1879 if (IS_ERR(host->pinctrl)) { 1880 ret = PTR_ERR(host->pinctrl); 1881 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 1882 goto host_free; 1883 } 1884 1885 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 1886 if (IS_ERR(host->pins_default)) { 1887 ret = PTR_ERR(host->pins_default); 1888 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 1889 goto host_free; 1890 } 1891 1892 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 1893 if (IS_ERR(host->pins_uhs)) { 1894 ret = PTR_ERR(host->pins_uhs); 1895 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 1896 goto host_free; 1897 } 1898 1899 msdc_of_property_parse(pdev, host); 1900 1901 host->dev = &pdev->dev; 1902 host->dev_comp = of_id->data; 1903 host->mmc = mmc; 1904 host->src_clk_freq = clk_get_rate(host->src_clk); 1905 /* Set host parameters to mmc */ 1906 mmc->ops = &mt_msdc_ops; 1907 if (host->dev_comp->clk_div_bits == 8) 1908 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 1909 else 1910 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); 1911 1912 mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; 1913 /* MMC core transfer sizes tunable parameters */ 1914 mmc->max_segs = MAX_BD_NUM; 1915 mmc->max_seg_size = BDMA_DESC_BUFLEN; 1916 mmc->max_blk_size = 2048; 1917 mmc->max_req_size = 512 * 1024; 1918 mmc->max_blk_count = mmc->max_req_size / 512; 1919 host->dma_mask = DMA_BIT_MASK(32); 1920 mmc_dev(mmc)->dma_mask = &host->dma_mask; 1921 1922 host->timeout_clks = 3 * 1048576; 1923 host->dma.gpd = dma_alloc_coherent(&pdev->dev, 1924 2 * sizeof(struct mt_gpdma_desc), 1925 &host->dma.gpd_addr, GFP_KERNEL); 1926 host->dma.bd = dma_alloc_coherent(&pdev->dev, 1927 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 1928 &host->dma.bd_addr, GFP_KERNEL); 1929 if (!host->dma.gpd || !host->dma.bd) { 1930 ret = -ENOMEM; 1931 goto release_mem; 1932 } 1933 msdc_init_gpd_bd(host, &host->dma); 1934 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 1935 spin_lock_init(&host->lock); 1936 1937 platform_set_drvdata(pdev, mmc); 1938 msdc_ungate_clock(host); 1939 msdc_init_hw(host); 1940 1941 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 1942 IRQF_TRIGGER_LOW | IRQF_ONESHOT, pdev->name, host); 1943 if (ret) 1944 goto release; 1945 1946 pm_runtime_set_active(host->dev); 1947 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 1948 pm_runtime_use_autosuspend(host->dev); 1949 pm_runtime_enable(host->dev); 1950 ret = mmc_add_host(mmc); 1951 1952 if (ret) 1953 goto end; 1954 1955 return 0; 1956 end: 1957 pm_runtime_disable(host->dev); 1958 release: 1959 platform_set_drvdata(pdev, NULL); 1960 msdc_deinit_hw(host); 1961 msdc_gate_clock(host); 1962 release_mem: 1963 if (host->dma.gpd) 1964 dma_free_coherent(&pdev->dev, 1965 2 * sizeof(struct mt_gpdma_desc), 1966 host->dma.gpd, host->dma.gpd_addr); 1967 if (host->dma.bd) 1968 dma_free_coherent(&pdev->dev, 1969 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 1970 host->dma.bd, host->dma.bd_addr); 1971 host_free: 1972 mmc_free_host(mmc); 1973 1974 return ret; 1975 } 1976 1977 static int msdc_drv_remove(struct platform_device *pdev) 1978 { 1979 struct mmc_host *mmc; 1980 struct msdc_host *host; 1981 1982 mmc = platform_get_drvdata(pdev); 1983 host = mmc_priv(mmc); 1984 1985 pm_runtime_get_sync(host->dev); 1986 1987 platform_set_drvdata(pdev, NULL); 1988 mmc_remove_host(host->mmc); 1989 msdc_deinit_hw(host); 1990 msdc_gate_clock(host); 1991 1992 pm_runtime_disable(host->dev); 1993 pm_runtime_put_noidle(host->dev); 1994 dma_free_coherent(&pdev->dev, 1995 2 * sizeof(struct mt_gpdma_desc), 1996 host->dma.gpd, host->dma.gpd_addr); 1997 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 1998 host->dma.bd, host->dma.bd_addr); 1999 2000 mmc_free_host(host->mmc); 2001 2002 return 0; 2003 } 2004 2005 #ifdef CONFIG_PM 2006 static void msdc_save_reg(struct msdc_host *host) 2007 { 2008 u32 tune_reg = host->dev_comp->pad_tune_reg; 2009 2010 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 2011 host->save_para.iocon = readl(host->base + MSDC_IOCON); 2012 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 2013 host->save_para.pad_tune = readl(host->base + tune_reg); 2014 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 2015 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 2016 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); 2017 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 2018 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2019 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 2020 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); 2021 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); 2022 } 2023 2024 static void msdc_restore_reg(struct msdc_host *host) 2025 { 2026 u32 tune_reg = host->dev_comp->pad_tune_reg; 2027 2028 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 2029 writel(host->save_para.iocon, host->base + MSDC_IOCON); 2030 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 2031 writel(host->save_para.pad_tune, host->base + tune_reg); 2032 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 2033 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 2034 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); 2035 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 2036 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 2037 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 2038 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); 2039 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); 2040 } 2041 2042 static int msdc_runtime_suspend(struct device *dev) 2043 { 2044 struct mmc_host *mmc = dev_get_drvdata(dev); 2045 struct msdc_host *host = mmc_priv(mmc); 2046 2047 msdc_save_reg(host); 2048 msdc_gate_clock(host); 2049 return 0; 2050 } 2051 2052 static int msdc_runtime_resume(struct device *dev) 2053 { 2054 struct mmc_host *mmc = dev_get_drvdata(dev); 2055 struct msdc_host *host = mmc_priv(mmc); 2056 2057 msdc_ungate_clock(host); 2058 msdc_restore_reg(host); 2059 return 0; 2060 } 2061 #endif 2062 2063 static const struct dev_pm_ops msdc_dev_pm_ops = { 2064 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2065 pm_runtime_force_resume) 2066 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 2067 }; 2068 2069 static struct platform_driver mt_msdc_driver = { 2070 .probe = msdc_drv_probe, 2071 .remove = msdc_drv_remove, 2072 .driver = { 2073 .name = "mtk-msdc", 2074 .of_match_table = msdc_of_ids, 2075 .pm = &msdc_dev_pm_ops, 2076 }, 2077 }; 2078 2079 module_platform_driver(mt_msdc_driver); 2080 MODULE_LICENSE("GPL v2"); 2081 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 2082