1 /* 2 * Copyright (c) 2014-2015 MediaTek Inc. 3 * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/ioport.h> 20 #include <linux/irq.h> 21 #include <linux/of_address.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_gpio.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/platform_device.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/spinlock.h> 28 29 #include <linux/mmc/card.h> 30 #include <linux/mmc/core.h> 31 #include <linux/mmc/host.h> 32 #include <linux/mmc/mmc.h> 33 #include <linux/mmc/sd.h> 34 #include <linux/mmc/sdio.h> 35 36 #define MAX_BD_NUM 1024 37 38 /*--------------------------------------------------------------------------*/ 39 /* Common Definition */ 40 /*--------------------------------------------------------------------------*/ 41 #define MSDC_BUS_1BITS 0x0 42 #define MSDC_BUS_4BITS 0x1 43 #define MSDC_BUS_8BITS 0x2 44 45 #define MSDC_BURST_64B 0x6 46 47 /*--------------------------------------------------------------------------*/ 48 /* Register Offset */ 49 /*--------------------------------------------------------------------------*/ 50 #define MSDC_CFG 0x0 51 #define MSDC_IOCON 0x04 52 #define MSDC_PS 0x08 53 #define MSDC_INT 0x0c 54 #define MSDC_INTEN 0x10 55 #define MSDC_FIFOCS 0x14 56 #define SDC_CFG 0x30 57 #define SDC_CMD 0x34 58 #define SDC_ARG 0x38 59 #define SDC_STS 0x3c 60 #define SDC_RESP0 0x40 61 #define SDC_RESP1 0x44 62 #define SDC_RESP2 0x48 63 #define SDC_RESP3 0x4c 64 #define SDC_BLK_NUM 0x50 65 #define SDC_ACMD_RESP 0x80 66 #define MSDC_DMA_SA 0x90 67 #define MSDC_DMA_CTRL 0x98 68 #define MSDC_DMA_CFG 0x9c 69 #define MSDC_PATCH_BIT 0xb0 70 #define MSDC_PATCH_BIT1 0xb4 71 #define MSDC_PAD_TUNE 0xec 72 73 /*--------------------------------------------------------------------------*/ 74 /* Register Mask */ 75 /*--------------------------------------------------------------------------*/ 76 77 /* MSDC_CFG mask */ 78 #define MSDC_CFG_MODE (0x1 << 0) /* RW */ 79 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ 80 #define MSDC_CFG_RST (0x1 << 2) /* RW */ 81 #define MSDC_CFG_PIO (0x1 << 3) /* RW */ 82 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ 83 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ 84 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ 85 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ 86 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ 87 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ 88 89 /* MSDC_IOCON mask */ 90 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ 91 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ 92 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ 93 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ 94 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ 95 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ 96 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ 97 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ 98 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ 99 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ 100 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ 101 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ 102 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ 103 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ 104 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ 105 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ 106 107 /* MSDC_PS mask */ 108 #define MSDC_PS_CDEN (0x1 << 0) /* RW */ 109 #define MSDC_PS_CDSTS (0x1 << 1) /* R */ 110 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ 111 #define MSDC_PS_DAT (0xff << 16) /* R */ 112 #define MSDC_PS_CMD (0x1 << 24) /* R */ 113 #define MSDC_PS_WP (0x1 << 31) /* R */ 114 115 /* MSDC_INT mask */ 116 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ 117 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ 118 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ 119 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ 120 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ 121 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ 122 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ 123 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ 124 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ 125 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ 126 #define MSDC_INT_CSTA (0x1 << 11) /* R */ 127 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ 128 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ 129 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ 130 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ 131 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ 132 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ 133 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ 134 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ 135 136 /* MSDC_INTEN mask */ 137 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ 138 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ 139 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ 140 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ 141 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ 142 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ 143 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ 144 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ 145 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ 146 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ 147 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ 148 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ 149 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ 150 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ 151 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ 152 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ 153 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ 154 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ 155 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ 156 157 /* MSDC_FIFOCS mask */ 158 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 159 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 160 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ 161 162 /* SDC_CFG mask */ 163 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ 164 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ 165 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 166 #define SDC_CFG_SDIO (0x1 << 19) /* RW */ 167 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 168 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ 169 #define SDC_CFG_DTOC (0xff << 24) /* RW */ 170 171 /* SDC_STS mask */ 172 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ 173 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 174 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ 175 176 /* MSDC_DMA_CTRL mask */ 177 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ 178 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ 179 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ 180 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ 181 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ 182 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ 183 184 /* MSDC_DMA_CFG mask */ 185 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ 186 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ 187 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ 188 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ 189 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ 190 191 /* MSDC_PATCH_BIT mask */ 192 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ 193 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) 194 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) 195 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ 196 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ 197 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ 198 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ 199 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ 200 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ 201 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ 202 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ 203 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ 204 205 #define REQ_CMD_EIO (0x1 << 0) 206 #define REQ_CMD_TMO (0x1 << 1) 207 #define REQ_DAT_ERR (0x1 << 2) 208 #define REQ_STOP_EIO (0x1 << 3) 209 #define REQ_STOP_TMO (0x1 << 4) 210 #define REQ_CMD_BUSY (0x1 << 5) 211 212 #define MSDC_PREPARE_FLAG (0x1 << 0) 213 #define MSDC_ASYNC_FLAG (0x1 << 1) 214 #define MSDC_MMAP_FLAG (0x1 << 2) 215 216 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 217 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 218 219 /*--------------------------------------------------------------------------*/ 220 /* Descriptor Structure */ 221 /*--------------------------------------------------------------------------*/ 222 struct mt_gpdma_desc { 223 u32 gpd_info; 224 #define GPDMA_DESC_HWO (0x1 << 0) 225 #define GPDMA_DESC_BDP (0x1 << 1) 226 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 227 #define GPDMA_DESC_INT (0x1 << 16) 228 u32 next; 229 u32 ptr; 230 u32 gpd_data_len; 231 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 232 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ 233 u32 arg; 234 u32 blknum; 235 u32 cmd; 236 }; 237 238 struct mt_bdma_desc { 239 u32 bd_info; 240 #define BDMA_DESC_EOL (0x1 << 0) 241 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 242 #define BDMA_DESC_BLKPAD (0x1 << 17) 243 #define BDMA_DESC_DWPAD (0x1 << 18) 244 u32 next; 245 u32 ptr; 246 u32 bd_data_len; 247 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 248 }; 249 250 struct msdc_dma { 251 struct scatterlist *sg; /* I/O scatter list */ 252 struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 253 struct mt_bdma_desc *bd; /* pointer to bd array */ 254 dma_addr_t gpd_addr; /* the physical address of gpd array */ 255 dma_addr_t bd_addr; /* the physical address of bd array */ 256 }; 257 258 struct msdc_host { 259 struct device *dev; 260 struct mmc_host *mmc; /* mmc structure */ 261 int cmd_rsp; 262 263 spinlock_t lock; 264 struct mmc_request *mrq; 265 struct mmc_command *cmd; 266 struct mmc_data *data; 267 int error; 268 269 void __iomem *base; /* host base address */ 270 271 struct msdc_dma dma; /* dma channel */ 272 u64 dma_mask; 273 274 u32 timeout_ns; /* data timeout ns */ 275 u32 timeout_clks; /* data timeout clks */ 276 277 struct pinctrl *pinctrl; 278 struct pinctrl_state *pins_default; 279 struct pinctrl_state *pins_uhs; 280 struct delayed_work req_timeout; 281 int irq; /* host interrupt */ 282 283 struct clk *src_clk; /* msdc source clock */ 284 struct clk *h_clk; /* msdc h_clk */ 285 u32 mclk; /* mmc subsystem clock frequency */ 286 u32 src_clk_freq; /* source clock frequency */ 287 u32 sclk; /* SD/MS bus clock frequency */ 288 bool ddr; 289 bool vqmmc_enabled; 290 }; 291 292 static void sdr_set_bits(void __iomem *reg, u32 bs) 293 { 294 u32 val = readl(reg); 295 296 val |= bs; 297 writel(val, reg); 298 } 299 300 static void sdr_clr_bits(void __iomem *reg, u32 bs) 301 { 302 u32 val = readl(reg); 303 304 val &= ~bs; 305 writel(val, reg); 306 } 307 308 static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 309 { 310 unsigned int tv = readl(reg); 311 312 tv &= ~field; 313 tv |= ((val) << (ffs((unsigned int)field) - 1)); 314 writel(tv, reg); 315 } 316 317 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 318 { 319 unsigned int tv = readl(reg); 320 321 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 322 } 323 324 static void msdc_reset_hw(struct msdc_host *host) 325 { 326 u32 val; 327 328 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 329 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) 330 cpu_relax(); 331 332 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 333 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) 334 cpu_relax(); 335 336 val = readl(host->base + MSDC_INT); 337 writel(val, host->base + MSDC_INT); 338 } 339 340 static void msdc_cmd_next(struct msdc_host *host, 341 struct mmc_request *mrq, struct mmc_command *cmd); 342 343 static u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 344 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 345 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 346 347 static u8 msdc_dma_calcs(u8 *buf, u32 len) 348 { 349 u32 i, sum = 0; 350 351 for (i = 0; i < len; i++) 352 sum += buf[i]; 353 return 0xff - (u8) sum; 354 } 355 356 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 357 struct mmc_data *data) 358 { 359 unsigned int j, dma_len; 360 dma_addr_t dma_address; 361 u32 dma_ctrl; 362 struct scatterlist *sg; 363 struct mt_gpdma_desc *gpd; 364 struct mt_bdma_desc *bd; 365 366 sg = data->sg; 367 368 gpd = dma->gpd; 369 bd = dma->bd; 370 371 /* modify gpd */ 372 gpd->gpd_info |= GPDMA_DESC_HWO; 373 gpd->gpd_info |= GPDMA_DESC_BDP; 374 /* need to clear first. use these bits to calc checksum */ 375 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 376 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 377 378 /* modify bd */ 379 for_each_sg(data->sg, sg, data->sg_count, j) { 380 dma_address = sg_dma_address(sg); 381 dma_len = sg_dma_len(sg); 382 383 /* init bd */ 384 bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 385 bd[j].bd_info &= ~BDMA_DESC_DWPAD; 386 bd[j].ptr = (u32)dma_address; 387 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 388 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 389 390 if (j == data->sg_count - 1) /* the last bd */ 391 bd[j].bd_info |= BDMA_DESC_EOL; 392 else 393 bd[j].bd_info &= ~BDMA_DESC_EOL; 394 395 /* checksume need to clear first */ 396 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 397 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 398 } 399 400 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 401 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 402 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 403 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); 404 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 405 writel((u32)dma->gpd_addr, host->base + MSDC_DMA_SA); 406 } 407 408 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq) 409 { 410 struct mmc_data *data = mrq->data; 411 412 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 413 bool read = (data->flags & MMC_DATA_READ) != 0; 414 415 data->host_cookie |= MSDC_PREPARE_FLAG; 416 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 417 read ? DMA_FROM_DEVICE : DMA_TO_DEVICE); 418 } 419 } 420 421 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) 422 { 423 struct mmc_data *data = mrq->data; 424 425 if (data->host_cookie & MSDC_ASYNC_FLAG) 426 return; 427 428 if (data->host_cookie & MSDC_PREPARE_FLAG) { 429 bool read = (data->flags & MMC_DATA_READ) != 0; 430 431 dma_unmap_sg(host->dev, data->sg, data->sg_len, 432 read ? DMA_FROM_DEVICE : DMA_TO_DEVICE); 433 data->host_cookie &= ~MSDC_PREPARE_FLAG; 434 } 435 } 436 437 /* clock control primitives */ 438 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) 439 { 440 u32 timeout, clk_ns; 441 u32 mode = 0; 442 443 host->timeout_ns = ns; 444 host->timeout_clks = clks; 445 if (host->sclk == 0) { 446 timeout = 0; 447 } else { 448 clk_ns = 1000000000UL / host->sclk; 449 timeout = (ns + clk_ns - 1) / clk_ns + clks; 450 /* in 1048576 sclk cycle unit */ 451 timeout = (timeout + (0x1 << 20) - 1) >> 20; 452 sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode); 453 /*DDR mode will double the clk cycles for data timeout */ 454 timeout = mode >= 2 ? timeout * 2 : timeout; 455 timeout = timeout > 1 ? timeout - 1 : 0; 456 timeout = timeout > 255 ? 255 : timeout; 457 } 458 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout); 459 } 460 461 static void msdc_gate_clock(struct msdc_host *host) 462 { 463 clk_disable_unprepare(host->src_clk); 464 clk_disable_unprepare(host->h_clk); 465 } 466 467 static void msdc_ungate_clock(struct msdc_host *host) 468 { 469 clk_prepare_enable(host->h_clk); 470 clk_prepare_enable(host->src_clk); 471 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 472 cpu_relax(); 473 } 474 475 static void msdc_set_mclk(struct msdc_host *host, int ddr, u32 hz) 476 { 477 u32 mode; 478 u32 flags; 479 u32 div; 480 u32 sclk; 481 482 if (!hz) { 483 dev_dbg(host->dev, "set mclk to 0\n"); 484 host->mclk = 0; 485 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 486 return; 487 } 488 489 flags = readl(host->base + MSDC_INTEN); 490 sdr_clr_bits(host->base + MSDC_INTEN, flags); 491 if (ddr) { /* may need to modify later */ 492 mode = 0x2; /* ddr mode and use divisor */ 493 if (hz >= (host->src_clk_freq >> 2)) { 494 div = 0; /* mean div = 1/4 */ 495 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 496 } else { 497 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 498 sclk = (host->src_clk_freq >> 2) / div; 499 div = (div >> 1); 500 } 501 } else if (hz >= host->src_clk_freq) { 502 mode = 0x1; /* no divisor */ 503 div = 0; 504 sclk = host->src_clk_freq; 505 } else { 506 mode = 0x0; /* use divisor */ 507 if (hz >= (host->src_clk_freq >> 1)) { 508 div = 0; /* mean div = 1/2 */ 509 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 510 } else { 511 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 512 sclk = (host->src_clk_freq >> 2) / div; 513 } 514 } 515 sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 516 (mode << 8) | (div % 0xff)); 517 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 518 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 519 cpu_relax(); 520 host->sclk = sclk; 521 host->mclk = hz; 522 host->ddr = ddr; 523 /* need because clk changed. */ 524 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 525 sdr_set_bits(host->base + MSDC_INTEN, flags); 526 527 dev_dbg(host->dev, "sclk: %d, ddr: %d\n", host->sclk, ddr); 528 } 529 530 static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 531 struct mmc_request *mrq, struct mmc_command *cmd) 532 { 533 u32 resp; 534 535 switch (mmc_resp_type(cmd)) { 536 /* Actually, R1, R5, R6, R7 are the same */ 537 case MMC_RSP_R1: 538 resp = 0x1; 539 break; 540 case MMC_RSP_R1B: 541 resp = 0x7; 542 break; 543 case MMC_RSP_R2: 544 resp = 0x2; 545 break; 546 case MMC_RSP_R3: 547 resp = 0x3; 548 break; 549 case MMC_RSP_NONE: 550 default: 551 resp = 0x0; 552 break; 553 } 554 555 return resp; 556 } 557 558 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 559 struct mmc_request *mrq, struct mmc_command *cmd) 560 { 561 /* rawcmd : 562 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 563 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 564 */ 565 u32 opcode = cmd->opcode; 566 u32 resp = msdc_cmd_find_resp(host, mrq, cmd); 567 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 568 569 host->cmd_rsp = resp; 570 571 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 572 opcode == MMC_STOP_TRANSMISSION) 573 rawcmd |= (0x1 << 14); 574 else if (opcode == SD_SWITCH_VOLTAGE) 575 rawcmd |= (0x1 << 30); 576 else if (opcode == SD_APP_SEND_SCR || 577 opcode == SD_APP_SEND_NUM_WR_BLKS || 578 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 579 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 580 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 581 rawcmd |= (0x1 << 11); 582 583 if (cmd->data) { 584 struct mmc_data *data = cmd->data; 585 586 if (mmc_op_multi(opcode)) { 587 if (mmc_card_mmc(host->mmc->card) && mrq->sbc && 588 !(mrq->sbc->arg & 0xFFFF0000)) 589 rawcmd |= 0x2 << 28; /* AutoCMD23 */ 590 } 591 592 rawcmd |= ((data->blksz & 0xFFF) << 16); 593 if (data->flags & MMC_DATA_WRITE) 594 rawcmd |= (0x1 << 13); 595 if (data->blocks > 1) 596 rawcmd |= (0x2 << 11); 597 else 598 rawcmd |= (0x1 << 11); 599 /* Always use dma mode */ 600 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 601 602 if (host->timeout_ns != data->timeout_ns || 603 host->timeout_clks != data->timeout_clks) 604 msdc_set_timeout(host, data->timeout_ns, 605 data->timeout_clks); 606 607 writel(data->blocks, host->base + SDC_BLK_NUM); 608 } 609 return rawcmd; 610 } 611 612 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, 613 struct mmc_command *cmd, struct mmc_data *data) 614 { 615 bool read; 616 617 WARN_ON(host->data); 618 host->data = data; 619 read = data->flags & MMC_DATA_READ; 620 621 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 622 msdc_dma_setup(host, &host->dma, data); 623 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 624 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 625 dev_dbg(host->dev, "DMA start\n"); 626 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 627 __func__, cmd->opcode, data->blocks, read); 628 } 629 630 static int msdc_auto_cmd_done(struct msdc_host *host, int events, 631 struct mmc_command *cmd) 632 { 633 u32 *rsp = cmd->resp; 634 635 rsp[0] = readl(host->base + SDC_ACMD_RESP); 636 637 if (events & MSDC_INT_ACMDRDY) { 638 cmd->error = 0; 639 } else { 640 msdc_reset_hw(host); 641 if (events & MSDC_INT_ACMDCRCERR) { 642 cmd->error = -EILSEQ; 643 host->error |= REQ_STOP_EIO; 644 } else if (events & MSDC_INT_ACMDTMO) { 645 cmd->error = -ETIMEDOUT; 646 host->error |= REQ_STOP_TMO; 647 } 648 dev_err(host->dev, 649 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 650 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 651 } 652 return cmd->error; 653 } 654 655 static void msdc_track_cmd_data(struct msdc_host *host, 656 struct mmc_command *cmd, struct mmc_data *data) 657 { 658 if (host->error) 659 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 660 __func__, cmd->opcode, cmd->arg, host->error); 661 } 662 663 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 664 { 665 unsigned long flags; 666 bool ret; 667 668 ret = cancel_delayed_work(&host->req_timeout); 669 if (!ret) { 670 /* delay work already running */ 671 return; 672 } 673 spin_lock_irqsave(&host->lock, flags); 674 host->mrq = NULL; 675 spin_unlock_irqrestore(&host->lock, flags); 676 677 msdc_track_cmd_data(host, mrq->cmd, mrq->data); 678 if (mrq->data) 679 msdc_unprepare_data(host, mrq); 680 mmc_request_done(host->mmc, mrq); 681 } 682 683 /* returns true if command is fully handled; returns false otherwise */ 684 static bool msdc_cmd_done(struct msdc_host *host, int events, 685 struct mmc_request *mrq, struct mmc_command *cmd) 686 { 687 bool done = false; 688 bool sbc_error; 689 unsigned long flags; 690 u32 *rsp = cmd->resp; 691 692 if (mrq->sbc && cmd == mrq->cmd && 693 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 694 | MSDC_INT_ACMDTMO))) 695 msdc_auto_cmd_done(host, events, mrq->sbc); 696 697 sbc_error = mrq->sbc && mrq->sbc->error; 698 699 if (!sbc_error && !(events & (MSDC_INT_CMDRDY 700 | MSDC_INT_RSPCRCERR 701 | MSDC_INT_CMDTMO))) 702 return done; 703 704 spin_lock_irqsave(&host->lock, flags); 705 done = !host->cmd; 706 host->cmd = NULL; 707 spin_unlock_irqrestore(&host->lock, flags); 708 709 if (done) 710 return true; 711 712 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CMDRDY | 713 MSDC_INTEN_RSPCRCERR | MSDC_INTEN_CMDTMO | 714 MSDC_INTEN_ACMDRDY | MSDC_INTEN_ACMDCRCERR | 715 MSDC_INTEN_ACMDTMO); 716 writel(cmd->arg, host->base + SDC_ARG); 717 718 if (cmd->flags & MMC_RSP_PRESENT) { 719 if (cmd->flags & MMC_RSP_136) { 720 rsp[0] = readl(host->base + SDC_RESP3); 721 rsp[1] = readl(host->base + SDC_RESP2); 722 rsp[2] = readl(host->base + SDC_RESP1); 723 rsp[3] = readl(host->base + SDC_RESP0); 724 } else { 725 rsp[0] = readl(host->base + SDC_RESP0); 726 } 727 } 728 729 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 730 msdc_reset_hw(host); 731 if (events & MSDC_INT_RSPCRCERR) { 732 cmd->error = -EILSEQ; 733 host->error |= REQ_CMD_EIO; 734 } else if (events & MSDC_INT_CMDTMO) { 735 cmd->error = -ETIMEDOUT; 736 host->error |= REQ_CMD_TMO; 737 } 738 } 739 if (cmd->error) 740 dev_dbg(host->dev, 741 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 742 __func__, cmd->opcode, cmd->arg, rsp[0], 743 cmd->error); 744 745 msdc_cmd_next(host, mrq, cmd); 746 return true; 747 } 748 749 /* It is the core layer's responsibility to ensure card status 750 * is correct before issue a request. but host design do below 751 * checks recommended. 752 */ 753 static inline bool msdc_cmd_is_ready(struct msdc_host *host, 754 struct mmc_request *mrq, struct mmc_command *cmd) 755 { 756 /* The max busy time we can endure is 20ms */ 757 unsigned long tmo = jiffies + msecs_to_jiffies(20); 758 759 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && 760 time_before(jiffies, tmo)) 761 cpu_relax(); 762 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { 763 dev_err(host->dev, "CMD bus busy detected\n"); 764 host->error |= REQ_CMD_BUSY; 765 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 766 return false; 767 } 768 769 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 770 tmo = jiffies + msecs_to_jiffies(20); 771 /* R1B or with data, should check SDCBUSY */ 772 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && 773 time_before(jiffies, tmo)) 774 cpu_relax(); 775 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { 776 dev_err(host->dev, "Controller busy detected\n"); 777 host->error |= REQ_CMD_BUSY; 778 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 779 return false; 780 } 781 } 782 return true; 783 } 784 785 static void msdc_start_command(struct msdc_host *host, 786 struct mmc_request *mrq, struct mmc_command *cmd) 787 { 788 u32 rawcmd; 789 790 WARN_ON(host->cmd); 791 host->cmd = cmd; 792 793 if (!msdc_cmd_is_ready(host, mrq, cmd)) 794 return; 795 796 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 797 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 798 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 799 msdc_reset_hw(host); 800 } 801 802 cmd->error = 0; 803 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 804 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 805 806 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CMDRDY | 807 MSDC_INTEN_RSPCRCERR | MSDC_INTEN_CMDTMO | 808 MSDC_INTEN_ACMDRDY | MSDC_INTEN_ACMDCRCERR | 809 MSDC_INTEN_ACMDTMO); 810 writel(cmd->arg, host->base + SDC_ARG); 811 writel(rawcmd, host->base + SDC_CMD); 812 } 813 814 static void msdc_cmd_next(struct msdc_host *host, 815 struct mmc_request *mrq, struct mmc_command *cmd) 816 { 817 if (cmd->error || (mrq->sbc && mrq->sbc->error)) 818 msdc_request_done(host, mrq); 819 else if (cmd == mrq->sbc) 820 msdc_start_command(host, mrq, mrq->cmd); 821 else if (!cmd->data) 822 msdc_request_done(host, mrq); 823 else 824 msdc_start_data(host, mrq, cmd, cmd->data); 825 } 826 827 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 828 { 829 struct msdc_host *host = mmc_priv(mmc); 830 831 host->error = 0; 832 WARN_ON(host->mrq); 833 host->mrq = mrq; 834 835 if (mrq->data) 836 msdc_prepare_data(host, mrq); 837 838 /* if SBC is required, we have HW option and SW option. 839 * if HW option is enabled, and SBC does not have "special" flags, 840 * use HW option, otherwise use SW option 841 */ 842 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 843 (mrq->sbc->arg & 0xFFFF0000))) 844 msdc_start_command(host, mrq, mrq->sbc); 845 else 846 msdc_start_command(host, mrq, mrq->cmd); 847 } 848 849 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 850 bool is_first_req) 851 { 852 struct msdc_host *host = mmc_priv(mmc); 853 struct mmc_data *data = mrq->data; 854 855 if (!data) 856 return; 857 858 msdc_prepare_data(host, mrq); 859 data->host_cookie |= MSDC_ASYNC_FLAG; 860 } 861 862 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 863 int err) 864 { 865 struct msdc_host *host = mmc_priv(mmc); 866 struct mmc_data *data; 867 868 data = mrq->data; 869 if (!data) 870 return; 871 if (data->host_cookie) { 872 data->host_cookie &= ~MSDC_ASYNC_FLAG; 873 msdc_unprepare_data(host, mrq); 874 } 875 } 876 877 static void msdc_data_xfer_next(struct msdc_host *host, 878 struct mmc_request *mrq, struct mmc_data *data) 879 { 880 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 881 (!data->bytes_xfered || !mrq->sbc)) 882 msdc_start_command(host, mrq, mrq->stop); 883 else 884 msdc_request_done(host, mrq); 885 } 886 887 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 888 struct mmc_request *mrq, struct mmc_data *data) 889 { 890 struct mmc_command *stop = data->stop; 891 unsigned long flags; 892 bool done; 893 unsigned int check_data = events & 894 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 895 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 896 | MSDC_INT_DMA_PROTECT); 897 898 spin_lock_irqsave(&host->lock, flags); 899 done = !host->data; 900 if (check_data) 901 host->data = NULL; 902 spin_unlock_irqrestore(&host->lock, flags); 903 904 if (done) 905 return true; 906 907 if (check_data || (stop && stop->error)) { 908 dev_dbg(host->dev, "DMA status: 0x%8X\n", 909 readl(host->base + MSDC_DMA_CFG)); 910 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 911 1); 912 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) 913 cpu_relax(); 914 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 915 dev_dbg(host->dev, "DMA stop\n"); 916 917 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 918 data->bytes_xfered = data->blocks * data->blksz; 919 } else { 920 dev_err(host->dev, "interrupt events: %x\n", events); 921 msdc_reset_hw(host); 922 host->error |= REQ_DAT_ERR; 923 data->bytes_xfered = 0; 924 925 if (events & MSDC_INT_DATTMO) 926 data->error = -ETIMEDOUT; 927 928 dev_err(host->dev, "%s: cmd=%d; blocks=%d", 929 __func__, mrq->cmd->opcode, data->blocks); 930 dev_err(host->dev, "data_error=%d xfer_size=%d\n", 931 (int)data->error, data->bytes_xfered); 932 } 933 934 msdc_data_xfer_next(host, mrq, data); 935 done = true; 936 } 937 return done; 938 } 939 940 static void msdc_set_buswidth(struct msdc_host *host, u32 width) 941 { 942 u32 val = readl(host->base + SDC_CFG); 943 944 val &= ~SDC_CFG_BUSWIDTH; 945 946 switch (width) { 947 default: 948 case MMC_BUS_WIDTH_1: 949 val |= (MSDC_BUS_1BITS << 16); 950 break; 951 case MMC_BUS_WIDTH_4: 952 val |= (MSDC_BUS_4BITS << 16); 953 break; 954 case MMC_BUS_WIDTH_8: 955 val |= (MSDC_BUS_8BITS << 16); 956 break; 957 } 958 959 writel(val, host->base + SDC_CFG); 960 dev_dbg(host->dev, "Bus Width = %d", width); 961 } 962 963 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 964 { 965 struct msdc_host *host = mmc_priv(mmc); 966 int min_uv, max_uv; 967 int ret = 0; 968 969 if (!IS_ERR(mmc->supply.vqmmc)) { 970 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { 971 min_uv = 3300000; 972 max_uv = 3300000; 973 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { 974 min_uv = 1800000; 975 max_uv = 1800000; 976 } else { 977 dev_err(host->dev, "Unsupported signal voltage!\n"); 978 return -EINVAL; 979 } 980 981 ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv); 982 if (ret) { 983 dev_err(host->dev, 984 "Regulator set error %d: %d - %d\n", 985 ret, min_uv, max_uv); 986 } else { 987 /* Apply different pinctrl settings for different signal voltage */ 988 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 989 pinctrl_select_state(host->pinctrl, host->pins_uhs); 990 else 991 pinctrl_select_state(host->pinctrl, host->pins_default); 992 } 993 } 994 return ret; 995 } 996 997 static int msdc_card_busy(struct mmc_host *mmc) 998 { 999 struct msdc_host *host = mmc_priv(mmc); 1000 u32 status = readl(host->base + MSDC_PS); 1001 1002 /* check if any pin between dat[0:3] is low */ 1003 if (((status >> 16) & 0xf) != 0xf) 1004 return 1; 1005 1006 return 0; 1007 } 1008 1009 static void msdc_request_timeout(struct work_struct *work) 1010 { 1011 struct msdc_host *host = container_of(work, struct msdc_host, 1012 req_timeout.work); 1013 1014 /* simulate HW timeout status */ 1015 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 1016 if (host->mrq) { 1017 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 1018 host->mrq, host->mrq->cmd->opcode); 1019 if (host->cmd) { 1020 dev_err(host->dev, "%s: aborting cmd=%d\n", 1021 __func__, host->cmd->opcode); 1022 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 1023 host->cmd); 1024 } else if (host->data) { 1025 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 1026 __func__, host->mrq->cmd->opcode, 1027 host->data->blocks); 1028 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 1029 host->data); 1030 } 1031 } 1032 } 1033 1034 static irqreturn_t msdc_irq(int irq, void *dev_id) 1035 { 1036 struct msdc_host *host = (struct msdc_host *) dev_id; 1037 1038 while (true) { 1039 unsigned long flags; 1040 struct mmc_request *mrq; 1041 struct mmc_command *cmd; 1042 struct mmc_data *data; 1043 u32 events, event_mask; 1044 1045 spin_lock_irqsave(&host->lock, flags); 1046 events = readl(host->base + MSDC_INT); 1047 event_mask = readl(host->base + MSDC_INTEN); 1048 /* clear interrupts */ 1049 writel(events & event_mask, host->base + MSDC_INT); 1050 1051 mrq = host->mrq; 1052 cmd = host->cmd; 1053 data = host->data; 1054 spin_unlock_irqrestore(&host->lock, flags); 1055 1056 if (!(events & event_mask)) 1057 break; 1058 1059 if (!mrq) { 1060 dev_err(host->dev, 1061 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 1062 __func__, events, event_mask); 1063 WARN_ON(1); 1064 break; 1065 } 1066 1067 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 1068 1069 if (cmd) 1070 msdc_cmd_done(host, events, mrq, cmd); 1071 else if (data) 1072 msdc_data_xfer_done(host, events, mrq, data); 1073 } 1074 1075 return IRQ_HANDLED; 1076 } 1077 1078 static void msdc_init_hw(struct msdc_host *host) 1079 { 1080 u32 val; 1081 1082 /* Configure to MMC/SD mode, clock free running */ 1083 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 1084 1085 /* Reset */ 1086 msdc_reset_hw(host); 1087 1088 /* Disable card detection */ 1089 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1090 1091 /* Disable and clear all interrupts */ 1092 writel(0, host->base + MSDC_INTEN); 1093 val = readl(host->base + MSDC_INT); 1094 writel(val, host->base + MSDC_INT); 1095 1096 writel(0, host->base + MSDC_PAD_TUNE); 1097 writel(0, host->base + MSDC_IOCON); 1098 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 1); 1099 writel(0x403c004f, host->base + MSDC_PATCH_BIT); 1100 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 1101 writel(0xffff0089, host->base + MSDC_PATCH_BIT1); 1102 /* Configure to enable SDIO mode. 1103 * it's must otherwise sdio cmd5 failed 1104 */ 1105 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1106 1107 /* disable detect SDIO device interrupt function */ 1108 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1109 1110 /* Configure to default data timeout */ 1111 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 1112 1113 dev_dbg(host->dev, "init hardware done!"); 1114 } 1115 1116 static void msdc_deinit_hw(struct msdc_host *host) 1117 { 1118 u32 val; 1119 /* Disable and clear all interrupts */ 1120 writel(0, host->base + MSDC_INTEN); 1121 1122 val = readl(host->base + MSDC_INT); 1123 writel(val, host->base + MSDC_INT); 1124 } 1125 1126 /* init gpd and bd list in msdc_drv_probe */ 1127 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 1128 { 1129 struct mt_gpdma_desc *gpd = dma->gpd; 1130 struct mt_bdma_desc *bd = dma->bd; 1131 int i; 1132 1133 memset(gpd, 0, sizeof(struct mt_gpdma_desc)); 1134 1135 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 1136 gpd->ptr = (u32)dma->bd_addr; /* physical address */ 1137 1138 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 1139 for (i = 0; i < (MAX_BD_NUM - 1); i++) 1140 bd[i].next = (u32)dma->bd_addr + sizeof(*bd) * (i + 1); 1141 } 1142 1143 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1144 { 1145 struct msdc_host *host = mmc_priv(mmc); 1146 int ret; 1147 u32 ddr = 0; 1148 1149 if (ios->timing == MMC_TIMING_UHS_DDR50 || 1150 ios->timing == MMC_TIMING_MMC_DDR52) 1151 ddr = 1; 1152 1153 msdc_set_buswidth(host, ios->bus_width); 1154 1155 /* Suspend/Resume will do power off/on */ 1156 switch (ios->power_mode) { 1157 case MMC_POWER_UP: 1158 if (!IS_ERR(mmc->supply.vmmc)) { 1159 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1160 ios->vdd); 1161 if (ret) { 1162 dev_err(host->dev, "Failed to set vmmc power!\n"); 1163 return; 1164 } 1165 } 1166 break; 1167 case MMC_POWER_ON: 1168 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1169 ret = regulator_enable(mmc->supply.vqmmc); 1170 if (ret) 1171 dev_err(host->dev, "Failed to set vqmmc power!\n"); 1172 else 1173 host->vqmmc_enabled = true; 1174 } 1175 break; 1176 case MMC_POWER_OFF: 1177 if (!IS_ERR(mmc->supply.vmmc)) 1178 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1179 1180 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1181 regulator_disable(mmc->supply.vqmmc); 1182 host->vqmmc_enabled = false; 1183 } 1184 break; 1185 default: 1186 break; 1187 } 1188 1189 if (host->mclk != ios->clock || host->ddr != ddr) 1190 msdc_set_mclk(host, ddr, ios->clock); 1191 } 1192 1193 static struct mmc_host_ops mt_msdc_ops = { 1194 .post_req = msdc_post_req, 1195 .pre_req = msdc_pre_req, 1196 .request = msdc_ops_request, 1197 .set_ios = msdc_ops_set_ios, 1198 .start_signal_voltage_switch = msdc_ops_switch_volt, 1199 .card_busy = msdc_card_busy, 1200 }; 1201 1202 static int msdc_drv_probe(struct platform_device *pdev) 1203 { 1204 struct mmc_host *mmc; 1205 struct msdc_host *host; 1206 struct resource *res; 1207 int ret; 1208 1209 if (!pdev->dev.of_node) { 1210 dev_err(&pdev->dev, "No DT found\n"); 1211 return -EINVAL; 1212 } 1213 /* Allocate MMC host for this device */ 1214 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 1215 if (!mmc) 1216 return -ENOMEM; 1217 1218 host = mmc_priv(mmc); 1219 ret = mmc_of_parse(mmc); 1220 if (ret) 1221 goto host_free; 1222 1223 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1224 host->base = devm_ioremap_resource(&pdev->dev, res); 1225 if (IS_ERR(host->base)) { 1226 ret = PTR_ERR(host->base); 1227 goto host_free; 1228 } 1229 1230 ret = mmc_regulator_get_supply(mmc); 1231 if (ret == -EPROBE_DEFER) 1232 goto host_free; 1233 1234 host->src_clk = devm_clk_get(&pdev->dev, "source"); 1235 if (IS_ERR(host->src_clk)) { 1236 ret = PTR_ERR(host->src_clk); 1237 goto host_free; 1238 } 1239 1240 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 1241 if (IS_ERR(host->h_clk)) { 1242 ret = PTR_ERR(host->h_clk); 1243 goto host_free; 1244 } 1245 1246 host->irq = platform_get_irq(pdev, 0); 1247 if (host->irq < 0) { 1248 ret = -EINVAL; 1249 goto host_free; 1250 } 1251 1252 host->pinctrl = devm_pinctrl_get(&pdev->dev); 1253 if (IS_ERR(host->pinctrl)) { 1254 ret = PTR_ERR(host->pinctrl); 1255 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 1256 goto host_free; 1257 } 1258 1259 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 1260 if (IS_ERR(host->pins_default)) { 1261 ret = PTR_ERR(host->pins_default); 1262 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 1263 goto host_free; 1264 } 1265 1266 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 1267 if (IS_ERR(host->pins_uhs)) { 1268 ret = PTR_ERR(host->pins_uhs); 1269 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 1270 goto host_free; 1271 } 1272 1273 host->dev = &pdev->dev; 1274 host->mmc = mmc; 1275 host->src_clk_freq = clk_get_rate(host->src_clk); 1276 /* Set host parameters to mmc */ 1277 mmc->ops = &mt_msdc_ops; 1278 mmc->f_min = host->src_clk_freq / (4 * 255); 1279 1280 mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; 1281 /* MMC core transfer sizes tunable parameters */ 1282 mmc->max_segs = MAX_BD_NUM; 1283 mmc->max_seg_size = BDMA_DESC_BUFLEN; 1284 mmc->max_blk_size = 2048; 1285 mmc->max_req_size = 512 * 1024; 1286 mmc->max_blk_count = mmc->max_req_size / 512; 1287 host->dma_mask = DMA_BIT_MASK(32); 1288 mmc_dev(mmc)->dma_mask = &host->dma_mask; 1289 1290 host->timeout_clks = 3 * 1048576; 1291 host->dma.gpd = dma_alloc_coherent(&pdev->dev, 1292 sizeof(struct mt_gpdma_desc), 1293 &host->dma.gpd_addr, GFP_KERNEL); 1294 host->dma.bd = dma_alloc_coherent(&pdev->dev, 1295 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 1296 &host->dma.bd_addr, GFP_KERNEL); 1297 if (!host->dma.gpd || !host->dma.bd) { 1298 ret = -ENOMEM; 1299 goto release_mem; 1300 } 1301 msdc_init_gpd_bd(host, &host->dma); 1302 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 1303 spin_lock_init(&host->lock); 1304 1305 platform_set_drvdata(pdev, mmc); 1306 msdc_ungate_clock(host); 1307 msdc_init_hw(host); 1308 1309 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 1310 IRQF_TRIGGER_LOW | IRQF_ONESHOT, pdev->name, host); 1311 if (ret) 1312 goto release; 1313 1314 ret = mmc_add_host(mmc); 1315 if (ret) 1316 goto release; 1317 1318 return 0; 1319 1320 release: 1321 platform_set_drvdata(pdev, NULL); 1322 msdc_deinit_hw(host); 1323 msdc_gate_clock(host); 1324 release_mem: 1325 if (host->dma.gpd) 1326 dma_free_coherent(&pdev->dev, 1327 sizeof(struct mt_gpdma_desc), 1328 host->dma.gpd, host->dma.gpd_addr); 1329 if (host->dma.bd) 1330 dma_free_coherent(&pdev->dev, 1331 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 1332 host->dma.bd, host->dma.bd_addr); 1333 host_free: 1334 mmc_free_host(mmc); 1335 1336 return ret; 1337 } 1338 1339 static int msdc_drv_remove(struct platform_device *pdev) 1340 { 1341 struct mmc_host *mmc; 1342 struct msdc_host *host; 1343 1344 mmc = platform_get_drvdata(pdev); 1345 host = mmc_priv(mmc); 1346 1347 platform_set_drvdata(pdev, NULL); 1348 mmc_remove_host(host->mmc); 1349 msdc_deinit_hw(host); 1350 msdc_gate_clock(host); 1351 1352 dma_free_coherent(&pdev->dev, 1353 sizeof(struct mt_gpdma_desc), 1354 host->dma.gpd, host->dma.gpd_addr); 1355 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 1356 host->dma.bd, host->dma.bd_addr); 1357 1358 mmc_free_host(host->mmc); 1359 1360 return 0; 1361 } 1362 1363 static const struct of_device_id msdc_of_ids[] = { 1364 { .compatible = "mediatek,mt8135-mmc", }, 1365 {} 1366 }; 1367 1368 static struct platform_driver mt_msdc_driver = { 1369 .probe = msdc_drv_probe, 1370 .remove = msdc_drv_remove, 1371 .driver = { 1372 .name = "mtk-msdc", 1373 .of_match_table = msdc_of_ids, 1374 }, 1375 }; 1376 1377 module_platform_driver(mt_msdc_driver); 1378 MODULE_LICENSE("GPL v2"); 1379 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 1380