1 /* 2 * Copyright (c) 2014-2015 MediaTek Inc. 3 * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/ioport.h> 20 #include <linux/irq.h> 21 #include <linux/of_address.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_gpio.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/regulator/consumer.h> 29 #include <linux/slab.h> 30 #include <linux/spinlock.h> 31 #include <linux/interrupt.h> 32 33 #include <linux/mmc/card.h> 34 #include <linux/mmc/core.h> 35 #include <linux/mmc/host.h> 36 #include <linux/mmc/mmc.h> 37 #include <linux/mmc/sd.h> 38 #include <linux/mmc/sdio.h> 39 #include <linux/mmc/slot-gpio.h> 40 41 #define MAX_BD_NUM 1024 42 43 /*--------------------------------------------------------------------------*/ 44 /* Common Definition */ 45 /*--------------------------------------------------------------------------*/ 46 #define MSDC_BUS_1BITS 0x0 47 #define MSDC_BUS_4BITS 0x1 48 #define MSDC_BUS_8BITS 0x2 49 50 #define MSDC_BURST_64B 0x6 51 52 /*--------------------------------------------------------------------------*/ 53 /* Register Offset */ 54 /*--------------------------------------------------------------------------*/ 55 #define MSDC_CFG 0x0 56 #define MSDC_IOCON 0x04 57 #define MSDC_PS 0x08 58 #define MSDC_INT 0x0c 59 #define MSDC_INTEN 0x10 60 #define MSDC_FIFOCS 0x14 61 #define SDC_CFG 0x30 62 #define SDC_CMD 0x34 63 #define SDC_ARG 0x38 64 #define SDC_STS 0x3c 65 #define SDC_RESP0 0x40 66 #define SDC_RESP1 0x44 67 #define SDC_RESP2 0x48 68 #define SDC_RESP3 0x4c 69 #define SDC_BLK_NUM 0x50 70 #define EMMC_IOCON 0x7c 71 #define SDC_ACMD_RESP 0x80 72 #define MSDC_DMA_SA 0x90 73 #define MSDC_DMA_CTRL 0x98 74 #define MSDC_DMA_CFG 0x9c 75 #define MSDC_PATCH_BIT 0xb0 76 #define MSDC_PATCH_BIT1 0xb4 77 #define MSDC_PAD_TUNE 0xec 78 #define PAD_DS_TUNE 0x188 79 #define PAD_CMD_TUNE 0x18c 80 #define EMMC50_CFG0 0x208 81 82 /*--------------------------------------------------------------------------*/ 83 /* Register Mask */ 84 /*--------------------------------------------------------------------------*/ 85 86 /* MSDC_CFG mask */ 87 #define MSDC_CFG_MODE (0x1 << 0) /* RW */ 88 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ 89 #define MSDC_CFG_RST (0x1 << 2) /* RW */ 90 #define MSDC_CFG_PIO (0x1 << 3) /* RW */ 91 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ 92 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ 93 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ 94 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ 95 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ 96 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ 97 #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */ 98 99 /* MSDC_IOCON mask */ 100 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ 101 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ 102 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ 103 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ 104 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ 105 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ 106 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ 107 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ 108 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ 109 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ 110 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ 111 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ 112 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ 113 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ 114 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ 115 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ 116 117 /* MSDC_PS mask */ 118 #define MSDC_PS_CDEN (0x1 << 0) /* RW */ 119 #define MSDC_PS_CDSTS (0x1 << 1) /* R */ 120 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ 121 #define MSDC_PS_DAT (0xff << 16) /* R */ 122 #define MSDC_PS_CMD (0x1 << 24) /* R */ 123 #define MSDC_PS_WP (0x1 << 31) /* R */ 124 125 /* MSDC_INT mask */ 126 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ 127 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ 128 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ 129 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ 130 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ 131 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ 132 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ 133 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ 134 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ 135 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ 136 #define MSDC_INT_CSTA (0x1 << 11) /* R */ 137 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ 138 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ 139 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ 140 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ 141 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ 142 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ 143 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ 144 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ 145 146 /* MSDC_INTEN mask */ 147 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ 148 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ 149 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ 150 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ 151 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ 152 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ 153 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ 154 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ 155 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ 156 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ 157 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ 158 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ 159 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ 160 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ 161 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ 162 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ 163 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ 164 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ 165 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ 166 167 /* MSDC_FIFOCS mask */ 168 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 169 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 170 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ 171 172 /* SDC_CFG mask */ 173 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ 174 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ 175 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 176 #define SDC_CFG_SDIO (0x1 << 19) /* RW */ 177 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 178 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ 179 #define SDC_CFG_DTOC (0xff << 24) /* RW */ 180 181 /* SDC_STS mask */ 182 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ 183 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 184 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ 185 186 /* MSDC_DMA_CTRL mask */ 187 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ 188 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ 189 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ 190 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ 191 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ 192 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ 193 194 /* MSDC_DMA_CFG mask */ 195 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ 196 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ 197 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ 198 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ 199 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ 200 201 /* MSDC_PATCH_BIT mask */ 202 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ 203 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) 204 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) 205 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ 206 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ 207 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ 208 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ 209 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ 210 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ 211 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ 212 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ 213 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ 214 215 #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */ 216 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */ 217 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */ 218 #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */ 219 #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */ 220 221 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */ 222 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */ 223 #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */ 224 225 #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */ 226 227 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */ 228 #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ 229 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ 230 231 #define REQ_CMD_EIO (0x1 << 0) 232 #define REQ_CMD_TMO (0x1 << 1) 233 #define REQ_DAT_ERR (0x1 << 2) 234 #define REQ_STOP_EIO (0x1 << 3) 235 #define REQ_STOP_TMO (0x1 << 4) 236 #define REQ_CMD_BUSY (0x1 << 5) 237 238 #define MSDC_PREPARE_FLAG (0x1 << 0) 239 #define MSDC_ASYNC_FLAG (0x1 << 1) 240 #define MSDC_MMAP_FLAG (0x1 << 2) 241 242 #define MTK_MMC_AUTOSUSPEND_DELAY 50 243 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 244 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 245 246 #define PAD_DELAY_MAX 32 /* PAD delay cells */ 247 /*--------------------------------------------------------------------------*/ 248 /* Descriptor Structure */ 249 /*--------------------------------------------------------------------------*/ 250 struct mt_gpdma_desc { 251 u32 gpd_info; 252 #define GPDMA_DESC_HWO (0x1 << 0) 253 #define GPDMA_DESC_BDP (0x1 << 1) 254 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 255 #define GPDMA_DESC_INT (0x1 << 16) 256 u32 next; 257 u32 ptr; 258 u32 gpd_data_len; 259 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 260 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ 261 u32 arg; 262 u32 blknum; 263 u32 cmd; 264 }; 265 266 struct mt_bdma_desc { 267 u32 bd_info; 268 #define BDMA_DESC_EOL (0x1 << 0) 269 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 270 #define BDMA_DESC_BLKPAD (0x1 << 17) 271 #define BDMA_DESC_DWPAD (0x1 << 18) 272 u32 next; 273 u32 ptr; 274 u32 bd_data_len; 275 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 276 }; 277 278 struct msdc_dma { 279 struct scatterlist *sg; /* I/O scatter list */ 280 struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 281 struct mt_bdma_desc *bd; /* pointer to bd array */ 282 dma_addr_t gpd_addr; /* the physical address of gpd array */ 283 dma_addr_t bd_addr; /* the physical address of bd array */ 284 }; 285 286 struct msdc_save_para { 287 u32 msdc_cfg; 288 u32 iocon; 289 u32 sdc_cfg; 290 u32 pad_tune; 291 u32 patch_bit0; 292 u32 patch_bit1; 293 u32 pad_ds_tune; 294 u32 pad_cmd_tune; 295 u32 emmc50_cfg0; 296 }; 297 298 struct msdc_tune_para { 299 u32 iocon; 300 u32 pad_tune; 301 u32 pad_cmd_tune; 302 }; 303 304 struct msdc_delay_phase { 305 u8 maxlen; 306 u8 start; 307 u8 final_phase; 308 }; 309 310 struct msdc_host { 311 struct device *dev; 312 struct mmc_host *mmc; /* mmc structure */ 313 int cmd_rsp; 314 315 spinlock_t lock; 316 struct mmc_request *mrq; 317 struct mmc_command *cmd; 318 struct mmc_data *data; 319 int error; 320 321 void __iomem *base; /* host base address */ 322 323 struct msdc_dma dma; /* dma channel */ 324 u64 dma_mask; 325 326 u32 timeout_ns; /* data timeout ns */ 327 u32 timeout_clks; /* data timeout clks */ 328 329 struct pinctrl *pinctrl; 330 struct pinctrl_state *pins_default; 331 struct pinctrl_state *pins_uhs; 332 struct delayed_work req_timeout; 333 int irq; /* host interrupt */ 334 335 struct clk *src_clk; /* msdc source clock */ 336 struct clk *h_clk; /* msdc h_clk */ 337 u32 mclk; /* mmc subsystem clock frequency */ 338 u32 src_clk_freq; /* source clock frequency */ 339 u32 sclk; /* SD/MS bus clock frequency */ 340 unsigned char timing; 341 bool vqmmc_enabled; 342 u32 hs400_ds_delay; 343 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 344 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 345 bool hs400_cmd_resp_sel_rising; 346 /* cmd response sample selection for HS400 */ 347 bool hs400_mode; /* current eMMC will run at hs400 mode */ 348 struct msdc_save_para save_para; /* used when gate HCLK */ 349 struct msdc_tune_para def_tune_para; /* default tune setting */ 350 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 351 }; 352 353 static void sdr_set_bits(void __iomem *reg, u32 bs) 354 { 355 u32 val = readl(reg); 356 357 val |= bs; 358 writel(val, reg); 359 } 360 361 static void sdr_clr_bits(void __iomem *reg, u32 bs) 362 { 363 u32 val = readl(reg); 364 365 val &= ~bs; 366 writel(val, reg); 367 } 368 369 static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 370 { 371 unsigned int tv = readl(reg); 372 373 tv &= ~field; 374 tv |= ((val) << (ffs((unsigned int)field) - 1)); 375 writel(tv, reg); 376 } 377 378 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 379 { 380 unsigned int tv = readl(reg); 381 382 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 383 } 384 385 static void msdc_reset_hw(struct msdc_host *host) 386 { 387 u32 val; 388 389 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 390 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) 391 cpu_relax(); 392 393 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 394 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) 395 cpu_relax(); 396 397 val = readl(host->base + MSDC_INT); 398 writel(val, host->base + MSDC_INT); 399 } 400 401 static void msdc_cmd_next(struct msdc_host *host, 402 struct mmc_request *mrq, struct mmc_command *cmd); 403 404 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 405 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 406 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 407 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 408 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 409 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 410 411 static u8 msdc_dma_calcs(u8 *buf, u32 len) 412 { 413 u32 i, sum = 0; 414 415 for (i = 0; i < len; i++) 416 sum += buf[i]; 417 return 0xff - (u8) sum; 418 } 419 420 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 421 struct mmc_data *data) 422 { 423 unsigned int j, dma_len; 424 dma_addr_t dma_address; 425 u32 dma_ctrl; 426 struct scatterlist *sg; 427 struct mt_gpdma_desc *gpd; 428 struct mt_bdma_desc *bd; 429 430 sg = data->sg; 431 432 gpd = dma->gpd; 433 bd = dma->bd; 434 435 /* modify gpd */ 436 gpd->gpd_info |= GPDMA_DESC_HWO; 437 gpd->gpd_info |= GPDMA_DESC_BDP; 438 /* need to clear first. use these bits to calc checksum */ 439 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 440 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 441 442 /* modify bd */ 443 for_each_sg(data->sg, sg, data->sg_count, j) { 444 dma_address = sg_dma_address(sg); 445 dma_len = sg_dma_len(sg); 446 447 /* init bd */ 448 bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 449 bd[j].bd_info &= ~BDMA_DESC_DWPAD; 450 bd[j].ptr = (u32)dma_address; 451 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 452 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 453 454 if (j == data->sg_count - 1) /* the last bd */ 455 bd[j].bd_info |= BDMA_DESC_EOL; 456 else 457 bd[j].bd_info &= ~BDMA_DESC_EOL; 458 459 /* checksume need to clear first */ 460 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 461 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 462 } 463 464 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 465 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 466 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 467 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); 468 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 469 writel((u32)dma->gpd_addr, host->base + MSDC_DMA_SA); 470 } 471 472 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq) 473 { 474 struct mmc_data *data = mrq->data; 475 476 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 477 bool read = (data->flags & MMC_DATA_READ) != 0; 478 479 data->host_cookie |= MSDC_PREPARE_FLAG; 480 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 481 read ? DMA_FROM_DEVICE : DMA_TO_DEVICE); 482 } 483 } 484 485 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) 486 { 487 struct mmc_data *data = mrq->data; 488 489 if (data->host_cookie & MSDC_ASYNC_FLAG) 490 return; 491 492 if (data->host_cookie & MSDC_PREPARE_FLAG) { 493 bool read = (data->flags & MMC_DATA_READ) != 0; 494 495 dma_unmap_sg(host->dev, data->sg, data->sg_len, 496 read ? DMA_FROM_DEVICE : DMA_TO_DEVICE); 497 data->host_cookie &= ~MSDC_PREPARE_FLAG; 498 } 499 } 500 501 /* clock control primitives */ 502 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) 503 { 504 u32 timeout, clk_ns; 505 u32 mode = 0; 506 507 host->timeout_ns = ns; 508 host->timeout_clks = clks; 509 if (host->sclk == 0) { 510 timeout = 0; 511 } else { 512 clk_ns = 1000000000UL / host->sclk; 513 timeout = (ns + clk_ns - 1) / clk_ns + clks; 514 /* in 1048576 sclk cycle unit */ 515 timeout = (timeout + (0x1 << 20) - 1) >> 20; 516 sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode); 517 /*DDR mode will double the clk cycles for data timeout */ 518 timeout = mode >= 2 ? timeout * 2 : timeout; 519 timeout = timeout > 1 ? timeout - 1 : 0; 520 timeout = timeout > 255 ? 255 : timeout; 521 } 522 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout); 523 } 524 525 static void msdc_gate_clock(struct msdc_host *host) 526 { 527 clk_disable_unprepare(host->src_clk); 528 clk_disable_unprepare(host->h_clk); 529 } 530 531 static void msdc_ungate_clock(struct msdc_host *host) 532 { 533 clk_prepare_enable(host->h_clk); 534 clk_prepare_enable(host->src_clk); 535 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 536 cpu_relax(); 537 } 538 539 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 540 { 541 u32 mode; 542 u32 flags; 543 u32 div; 544 u32 sclk; 545 546 if (!hz) { 547 dev_dbg(host->dev, "set mclk to 0\n"); 548 host->mclk = 0; 549 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 550 return; 551 } 552 553 flags = readl(host->base + MSDC_INTEN); 554 sdr_clr_bits(host->base + MSDC_INTEN, flags); 555 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 556 if (timing == MMC_TIMING_UHS_DDR50 || 557 timing == MMC_TIMING_MMC_DDR52 || 558 timing == MMC_TIMING_MMC_HS400) { 559 if (timing == MMC_TIMING_MMC_HS400) 560 mode = 0x3; 561 else 562 mode = 0x2; /* ddr mode and use divisor */ 563 564 if (hz >= (host->src_clk_freq >> 2)) { 565 div = 0; /* mean div = 1/4 */ 566 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 567 } else { 568 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 569 sclk = (host->src_clk_freq >> 2) / div; 570 div = (div >> 1); 571 } 572 573 if (timing == MMC_TIMING_MMC_HS400 && 574 hz >= (host->src_clk_freq >> 1)) { 575 sdr_set_bits(host->base + MSDC_CFG, 576 MSDC_CFG_HS400_CK_MODE); 577 sclk = host->src_clk_freq >> 1; 578 div = 0; /* div is ignore when bit18 is set */ 579 } 580 } else if (hz >= host->src_clk_freq) { 581 mode = 0x1; /* no divisor */ 582 div = 0; 583 sclk = host->src_clk_freq; 584 } else { 585 mode = 0x0; /* use divisor */ 586 if (hz >= (host->src_clk_freq >> 1)) { 587 div = 0; /* mean div = 1/2 */ 588 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 589 } else { 590 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 591 sclk = (host->src_clk_freq >> 2) / div; 592 } 593 } 594 sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 595 (mode << 8) | div); 596 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 597 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 598 cpu_relax(); 599 host->sclk = sclk; 600 host->mclk = hz; 601 host->timing = timing; 602 /* need because clk changed. */ 603 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 604 sdr_set_bits(host->base + MSDC_INTEN, flags); 605 606 /* 607 * mmc_select_hs400() will drop to 50Mhz and High speed mode, 608 * tune result of hs200/200Mhz is not suitable for 50Mhz 609 */ 610 if (host->sclk <= 52000000) { 611 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 612 writel(host->def_tune_para.pad_tune, host->base + MSDC_PAD_TUNE); 613 } else { 614 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 615 writel(host->saved_tune_para.pad_tune, host->base + MSDC_PAD_TUNE); 616 writel(host->saved_tune_para.pad_cmd_tune, 617 host->base + PAD_CMD_TUNE); 618 } 619 620 if (timing == MMC_TIMING_MMC_HS400) 621 sdr_set_field(host->base + PAD_CMD_TUNE, 622 MSDC_PAD_TUNE_CMDRRDLY, 623 host->hs400_cmd_int_delay); 624 dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->sclk, timing); 625 } 626 627 static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 628 struct mmc_request *mrq, struct mmc_command *cmd) 629 { 630 u32 resp; 631 632 switch (mmc_resp_type(cmd)) { 633 /* Actually, R1, R5, R6, R7 are the same */ 634 case MMC_RSP_R1: 635 resp = 0x1; 636 break; 637 case MMC_RSP_R1B: 638 resp = 0x7; 639 break; 640 case MMC_RSP_R2: 641 resp = 0x2; 642 break; 643 case MMC_RSP_R3: 644 resp = 0x3; 645 break; 646 case MMC_RSP_NONE: 647 default: 648 resp = 0x0; 649 break; 650 } 651 652 return resp; 653 } 654 655 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 656 struct mmc_request *mrq, struct mmc_command *cmd) 657 { 658 /* rawcmd : 659 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 660 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 661 */ 662 u32 opcode = cmd->opcode; 663 u32 resp = msdc_cmd_find_resp(host, mrq, cmd); 664 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 665 666 host->cmd_rsp = resp; 667 668 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 669 opcode == MMC_STOP_TRANSMISSION) 670 rawcmd |= (0x1 << 14); 671 else if (opcode == SD_SWITCH_VOLTAGE) 672 rawcmd |= (0x1 << 30); 673 else if (opcode == SD_APP_SEND_SCR || 674 opcode == SD_APP_SEND_NUM_WR_BLKS || 675 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 676 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 677 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 678 rawcmd |= (0x1 << 11); 679 680 if (cmd->data) { 681 struct mmc_data *data = cmd->data; 682 683 if (mmc_op_multi(opcode)) { 684 if (mmc_card_mmc(host->mmc->card) && mrq->sbc && 685 !(mrq->sbc->arg & 0xFFFF0000)) 686 rawcmd |= 0x2 << 28; /* AutoCMD23 */ 687 } 688 689 rawcmd |= ((data->blksz & 0xFFF) << 16); 690 if (data->flags & MMC_DATA_WRITE) 691 rawcmd |= (0x1 << 13); 692 if (data->blocks > 1) 693 rawcmd |= (0x2 << 11); 694 else 695 rawcmd |= (0x1 << 11); 696 /* Always use dma mode */ 697 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 698 699 if (host->timeout_ns != data->timeout_ns || 700 host->timeout_clks != data->timeout_clks) 701 msdc_set_timeout(host, data->timeout_ns, 702 data->timeout_clks); 703 704 writel(data->blocks, host->base + SDC_BLK_NUM); 705 } 706 return rawcmd; 707 } 708 709 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, 710 struct mmc_command *cmd, struct mmc_data *data) 711 { 712 bool read; 713 714 WARN_ON(host->data); 715 host->data = data; 716 read = data->flags & MMC_DATA_READ; 717 718 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 719 msdc_dma_setup(host, &host->dma, data); 720 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 721 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 722 dev_dbg(host->dev, "DMA start\n"); 723 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 724 __func__, cmd->opcode, data->blocks, read); 725 } 726 727 static int msdc_auto_cmd_done(struct msdc_host *host, int events, 728 struct mmc_command *cmd) 729 { 730 u32 *rsp = cmd->resp; 731 732 rsp[0] = readl(host->base + SDC_ACMD_RESP); 733 734 if (events & MSDC_INT_ACMDRDY) { 735 cmd->error = 0; 736 } else { 737 msdc_reset_hw(host); 738 if (events & MSDC_INT_ACMDCRCERR) { 739 cmd->error = -EILSEQ; 740 host->error |= REQ_STOP_EIO; 741 } else if (events & MSDC_INT_ACMDTMO) { 742 cmd->error = -ETIMEDOUT; 743 host->error |= REQ_STOP_TMO; 744 } 745 dev_err(host->dev, 746 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 747 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 748 } 749 return cmd->error; 750 } 751 752 static void msdc_track_cmd_data(struct msdc_host *host, 753 struct mmc_command *cmd, struct mmc_data *data) 754 { 755 if (host->error) 756 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 757 __func__, cmd->opcode, cmd->arg, host->error); 758 } 759 760 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 761 { 762 unsigned long flags; 763 bool ret; 764 765 ret = cancel_delayed_work(&host->req_timeout); 766 if (!ret) { 767 /* delay work already running */ 768 return; 769 } 770 spin_lock_irqsave(&host->lock, flags); 771 host->mrq = NULL; 772 spin_unlock_irqrestore(&host->lock, flags); 773 774 msdc_track_cmd_data(host, mrq->cmd, mrq->data); 775 if (mrq->data) 776 msdc_unprepare_data(host, mrq); 777 mmc_request_done(host->mmc, mrq); 778 } 779 780 /* returns true if command is fully handled; returns false otherwise */ 781 static bool msdc_cmd_done(struct msdc_host *host, int events, 782 struct mmc_request *mrq, struct mmc_command *cmd) 783 { 784 bool done = false; 785 bool sbc_error; 786 unsigned long flags; 787 u32 *rsp = cmd->resp; 788 789 if (mrq->sbc && cmd == mrq->cmd && 790 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 791 | MSDC_INT_ACMDTMO))) 792 msdc_auto_cmd_done(host, events, mrq->sbc); 793 794 sbc_error = mrq->sbc && mrq->sbc->error; 795 796 if (!sbc_error && !(events & (MSDC_INT_CMDRDY 797 | MSDC_INT_RSPCRCERR 798 | MSDC_INT_CMDTMO))) 799 return done; 800 801 spin_lock_irqsave(&host->lock, flags); 802 done = !host->cmd; 803 host->cmd = NULL; 804 spin_unlock_irqrestore(&host->lock, flags); 805 806 if (done) 807 return true; 808 809 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 810 811 if (cmd->flags & MMC_RSP_PRESENT) { 812 if (cmd->flags & MMC_RSP_136) { 813 rsp[0] = readl(host->base + SDC_RESP3); 814 rsp[1] = readl(host->base + SDC_RESP2); 815 rsp[2] = readl(host->base + SDC_RESP1); 816 rsp[3] = readl(host->base + SDC_RESP0); 817 } else { 818 rsp[0] = readl(host->base + SDC_RESP0); 819 } 820 } 821 822 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 823 if (cmd->opcode != MMC_SEND_TUNING_BLOCK && 824 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200) 825 /* 826 * should not clear fifo/interrupt as the tune data 827 * may have alreay come. 828 */ 829 msdc_reset_hw(host); 830 if (events & MSDC_INT_RSPCRCERR) { 831 cmd->error = -EILSEQ; 832 host->error |= REQ_CMD_EIO; 833 } else if (events & MSDC_INT_CMDTMO) { 834 cmd->error = -ETIMEDOUT; 835 host->error |= REQ_CMD_TMO; 836 } 837 } 838 if (cmd->error) 839 dev_dbg(host->dev, 840 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 841 __func__, cmd->opcode, cmd->arg, rsp[0], 842 cmd->error); 843 844 msdc_cmd_next(host, mrq, cmd); 845 return true; 846 } 847 848 /* It is the core layer's responsibility to ensure card status 849 * is correct before issue a request. but host design do below 850 * checks recommended. 851 */ 852 static inline bool msdc_cmd_is_ready(struct msdc_host *host, 853 struct mmc_request *mrq, struct mmc_command *cmd) 854 { 855 /* The max busy time we can endure is 20ms */ 856 unsigned long tmo = jiffies + msecs_to_jiffies(20); 857 858 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && 859 time_before(jiffies, tmo)) 860 cpu_relax(); 861 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { 862 dev_err(host->dev, "CMD bus busy detected\n"); 863 host->error |= REQ_CMD_BUSY; 864 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 865 return false; 866 } 867 868 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 869 tmo = jiffies + msecs_to_jiffies(20); 870 /* R1B or with data, should check SDCBUSY */ 871 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && 872 time_before(jiffies, tmo)) 873 cpu_relax(); 874 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { 875 dev_err(host->dev, "Controller busy detected\n"); 876 host->error |= REQ_CMD_BUSY; 877 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 878 return false; 879 } 880 } 881 return true; 882 } 883 884 static void msdc_start_command(struct msdc_host *host, 885 struct mmc_request *mrq, struct mmc_command *cmd) 886 { 887 u32 rawcmd; 888 889 WARN_ON(host->cmd); 890 host->cmd = cmd; 891 892 if (!msdc_cmd_is_ready(host, mrq, cmd)) 893 return; 894 895 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 896 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 897 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 898 msdc_reset_hw(host); 899 } 900 901 cmd->error = 0; 902 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 903 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 904 905 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 906 writel(cmd->arg, host->base + SDC_ARG); 907 writel(rawcmd, host->base + SDC_CMD); 908 } 909 910 static void msdc_cmd_next(struct msdc_host *host, 911 struct mmc_request *mrq, struct mmc_command *cmd) 912 { 913 if ((cmd->error && 914 !(cmd->error == -EILSEQ && 915 (cmd->opcode == MMC_SEND_TUNING_BLOCK || 916 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) || 917 (mrq->sbc && mrq->sbc->error)) 918 msdc_request_done(host, mrq); 919 else if (cmd == mrq->sbc) 920 msdc_start_command(host, mrq, mrq->cmd); 921 else if (!cmd->data) 922 msdc_request_done(host, mrq); 923 else 924 msdc_start_data(host, mrq, cmd, cmd->data); 925 } 926 927 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 928 { 929 struct msdc_host *host = mmc_priv(mmc); 930 931 host->error = 0; 932 WARN_ON(host->mrq); 933 host->mrq = mrq; 934 935 if (mrq->data) 936 msdc_prepare_data(host, mrq); 937 938 /* if SBC is required, we have HW option and SW option. 939 * if HW option is enabled, and SBC does not have "special" flags, 940 * use HW option, otherwise use SW option 941 */ 942 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 943 (mrq->sbc->arg & 0xFFFF0000))) 944 msdc_start_command(host, mrq, mrq->sbc); 945 else 946 msdc_start_command(host, mrq, mrq->cmd); 947 } 948 949 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 950 { 951 struct msdc_host *host = mmc_priv(mmc); 952 struct mmc_data *data = mrq->data; 953 954 if (!data) 955 return; 956 957 msdc_prepare_data(host, mrq); 958 data->host_cookie |= MSDC_ASYNC_FLAG; 959 } 960 961 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 962 int err) 963 { 964 struct msdc_host *host = mmc_priv(mmc); 965 struct mmc_data *data; 966 967 data = mrq->data; 968 if (!data) 969 return; 970 if (data->host_cookie) { 971 data->host_cookie &= ~MSDC_ASYNC_FLAG; 972 msdc_unprepare_data(host, mrq); 973 } 974 } 975 976 static void msdc_data_xfer_next(struct msdc_host *host, 977 struct mmc_request *mrq, struct mmc_data *data) 978 { 979 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 980 !mrq->sbc) 981 msdc_start_command(host, mrq, mrq->stop); 982 else 983 msdc_request_done(host, mrq); 984 } 985 986 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 987 struct mmc_request *mrq, struct mmc_data *data) 988 { 989 struct mmc_command *stop = data->stop; 990 unsigned long flags; 991 bool done; 992 unsigned int check_data = events & 993 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 994 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 995 | MSDC_INT_DMA_PROTECT); 996 997 spin_lock_irqsave(&host->lock, flags); 998 done = !host->data; 999 if (check_data) 1000 host->data = NULL; 1001 spin_unlock_irqrestore(&host->lock, flags); 1002 1003 if (done) 1004 return true; 1005 1006 if (check_data || (stop && stop->error)) { 1007 dev_dbg(host->dev, "DMA status: 0x%8X\n", 1008 readl(host->base + MSDC_DMA_CFG)); 1009 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1010 1); 1011 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) 1012 cpu_relax(); 1013 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 1014 dev_dbg(host->dev, "DMA stop\n"); 1015 1016 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 1017 data->bytes_xfered = data->blocks * data->blksz; 1018 } else { 1019 dev_dbg(host->dev, "interrupt events: %x\n", events); 1020 msdc_reset_hw(host); 1021 host->error |= REQ_DAT_ERR; 1022 data->bytes_xfered = 0; 1023 1024 if (events & MSDC_INT_DATTMO) 1025 data->error = -ETIMEDOUT; 1026 else if (events & MSDC_INT_DATCRCERR) 1027 data->error = -EILSEQ; 1028 1029 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 1030 __func__, mrq->cmd->opcode, data->blocks); 1031 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 1032 (int)data->error, data->bytes_xfered); 1033 } 1034 1035 msdc_data_xfer_next(host, mrq, data); 1036 done = true; 1037 } 1038 return done; 1039 } 1040 1041 static void msdc_set_buswidth(struct msdc_host *host, u32 width) 1042 { 1043 u32 val = readl(host->base + SDC_CFG); 1044 1045 val &= ~SDC_CFG_BUSWIDTH; 1046 1047 switch (width) { 1048 default: 1049 case MMC_BUS_WIDTH_1: 1050 val |= (MSDC_BUS_1BITS << 16); 1051 break; 1052 case MMC_BUS_WIDTH_4: 1053 val |= (MSDC_BUS_4BITS << 16); 1054 break; 1055 case MMC_BUS_WIDTH_8: 1056 val |= (MSDC_BUS_8BITS << 16); 1057 break; 1058 } 1059 1060 writel(val, host->base + SDC_CFG); 1061 dev_dbg(host->dev, "Bus Width = %d", width); 1062 } 1063 1064 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 1065 { 1066 struct msdc_host *host = mmc_priv(mmc); 1067 int ret = 0; 1068 1069 if (!IS_ERR(mmc->supply.vqmmc)) { 1070 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1071 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 1072 dev_err(host->dev, "Unsupported signal voltage!\n"); 1073 return -EINVAL; 1074 } 1075 1076 ret = mmc_regulator_set_vqmmc(mmc, ios); 1077 if (ret) { 1078 dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1079 ret, ios->signal_voltage); 1080 } else { 1081 /* Apply different pinctrl settings for different signal voltage */ 1082 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 1083 pinctrl_select_state(host->pinctrl, host->pins_uhs); 1084 else 1085 pinctrl_select_state(host->pinctrl, host->pins_default); 1086 } 1087 } 1088 return ret; 1089 } 1090 1091 static int msdc_card_busy(struct mmc_host *mmc) 1092 { 1093 struct msdc_host *host = mmc_priv(mmc); 1094 u32 status = readl(host->base + MSDC_PS); 1095 1096 /* only check if data0 is low */ 1097 return !(status & BIT(16)); 1098 } 1099 1100 static void msdc_request_timeout(struct work_struct *work) 1101 { 1102 struct msdc_host *host = container_of(work, struct msdc_host, 1103 req_timeout.work); 1104 1105 /* simulate HW timeout status */ 1106 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 1107 if (host->mrq) { 1108 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 1109 host->mrq, host->mrq->cmd->opcode); 1110 if (host->cmd) { 1111 dev_err(host->dev, "%s: aborting cmd=%d\n", 1112 __func__, host->cmd->opcode); 1113 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 1114 host->cmd); 1115 } else if (host->data) { 1116 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 1117 __func__, host->mrq->cmd->opcode, 1118 host->data->blocks); 1119 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 1120 host->data); 1121 } 1122 } 1123 } 1124 1125 static irqreturn_t msdc_irq(int irq, void *dev_id) 1126 { 1127 struct msdc_host *host = (struct msdc_host *) dev_id; 1128 1129 while (true) { 1130 unsigned long flags; 1131 struct mmc_request *mrq; 1132 struct mmc_command *cmd; 1133 struct mmc_data *data; 1134 u32 events, event_mask; 1135 1136 spin_lock_irqsave(&host->lock, flags); 1137 events = readl(host->base + MSDC_INT); 1138 event_mask = readl(host->base + MSDC_INTEN); 1139 /* clear interrupts */ 1140 writel(events & event_mask, host->base + MSDC_INT); 1141 1142 mrq = host->mrq; 1143 cmd = host->cmd; 1144 data = host->data; 1145 spin_unlock_irqrestore(&host->lock, flags); 1146 1147 if (!(events & event_mask)) 1148 break; 1149 1150 if (!mrq) { 1151 dev_err(host->dev, 1152 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 1153 __func__, events, event_mask); 1154 WARN_ON(1); 1155 break; 1156 } 1157 1158 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 1159 1160 if (cmd) 1161 msdc_cmd_done(host, events, mrq, cmd); 1162 else if (data) 1163 msdc_data_xfer_done(host, events, mrq, data); 1164 } 1165 1166 return IRQ_HANDLED; 1167 } 1168 1169 static void msdc_init_hw(struct msdc_host *host) 1170 { 1171 u32 val; 1172 1173 /* Configure to MMC/SD mode, clock free running */ 1174 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 1175 1176 /* Reset */ 1177 msdc_reset_hw(host); 1178 1179 /* Disable card detection */ 1180 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1181 1182 /* Disable and clear all interrupts */ 1183 writel(0, host->base + MSDC_INTEN); 1184 val = readl(host->base + MSDC_INT); 1185 writel(val, host->base + MSDC_INT); 1186 1187 writel(0, host->base + MSDC_PAD_TUNE); 1188 writel(0, host->base + MSDC_IOCON); 1189 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 1190 writel(0x403c0046, host->base + MSDC_PATCH_BIT); 1191 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 1192 writel(0xffff0089, host->base + MSDC_PATCH_BIT1); 1193 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1194 1195 /* Configure to enable SDIO mode. 1196 * it's must otherwise sdio cmd5 failed 1197 */ 1198 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1199 1200 /* disable detect SDIO device interrupt function */ 1201 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1202 1203 /* Configure to default data timeout */ 1204 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 1205 1206 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 1207 host->def_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE); 1208 dev_dbg(host->dev, "init hardware done!"); 1209 } 1210 1211 static void msdc_deinit_hw(struct msdc_host *host) 1212 { 1213 u32 val; 1214 /* Disable and clear all interrupts */ 1215 writel(0, host->base + MSDC_INTEN); 1216 1217 val = readl(host->base + MSDC_INT); 1218 writel(val, host->base + MSDC_INT); 1219 } 1220 1221 /* init gpd and bd list in msdc_drv_probe */ 1222 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 1223 { 1224 struct mt_gpdma_desc *gpd = dma->gpd; 1225 struct mt_bdma_desc *bd = dma->bd; 1226 int i; 1227 1228 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 1229 1230 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 1231 gpd->ptr = (u32)dma->bd_addr; /* physical address */ 1232 /* gpd->next is must set for desc DMA 1233 * That's why must alloc 2 gpd structure. 1234 */ 1235 gpd->next = (u32)dma->gpd_addr + sizeof(struct mt_gpdma_desc); 1236 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 1237 for (i = 0; i < (MAX_BD_NUM - 1); i++) 1238 bd[i].next = (u32)dma->bd_addr + sizeof(*bd) * (i + 1); 1239 } 1240 1241 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1242 { 1243 struct msdc_host *host = mmc_priv(mmc); 1244 int ret; 1245 1246 msdc_set_buswidth(host, ios->bus_width); 1247 1248 /* Suspend/Resume will do power off/on */ 1249 switch (ios->power_mode) { 1250 case MMC_POWER_UP: 1251 if (!IS_ERR(mmc->supply.vmmc)) { 1252 msdc_init_hw(host); 1253 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1254 ios->vdd); 1255 if (ret) { 1256 dev_err(host->dev, "Failed to set vmmc power!\n"); 1257 return; 1258 } 1259 } 1260 break; 1261 case MMC_POWER_ON: 1262 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1263 ret = regulator_enable(mmc->supply.vqmmc); 1264 if (ret) 1265 dev_err(host->dev, "Failed to set vqmmc power!\n"); 1266 else 1267 host->vqmmc_enabled = true; 1268 } 1269 break; 1270 case MMC_POWER_OFF: 1271 if (!IS_ERR(mmc->supply.vmmc)) 1272 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1273 1274 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1275 regulator_disable(mmc->supply.vqmmc); 1276 host->vqmmc_enabled = false; 1277 } 1278 break; 1279 default: 1280 break; 1281 } 1282 1283 if (host->mclk != ios->clock || host->timing != ios->timing) 1284 msdc_set_mclk(host, ios->timing, ios->clock); 1285 } 1286 1287 static u32 test_delay_bit(u32 delay, u32 bit) 1288 { 1289 bit %= PAD_DELAY_MAX; 1290 return delay & (1 << bit); 1291 } 1292 1293 static int get_delay_len(u32 delay, u32 start_bit) 1294 { 1295 int i; 1296 1297 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 1298 if (test_delay_bit(delay, start_bit + i) == 0) 1299 return i; 1300 } 1301 return PAD_DELAY_MAX - start_bit; 1302 } 1303 1304 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 1305 { 1306 int start = 0, len = 0; 1307 int start_final = 0, len_final = 0; 1308 u8 final_phase = 0xff; 1309 struct msdc_delay_phase delay_phase = { 0, }; 1310 1311 if (delay == 0) { 1312 dev_err(host->dev, "phase error: [map:%x]\n", delay); 1313 delay_phase.final_phase = final_phase; 1314 return delay_phase; 1315 } 1316 1317 while (start < PAD_DELAY_MAX) { 1318 len = get_delay_len(delay, start); 1319 if (len_final < len) { 1320 start_final = start; 1321 len_final = len; 1322 } 1323 start += len ? len : 1; 1324 if (len >= 12 && start_final < 4) 1325 break; 1326 } 1327 1328 /* The rule is that to find the smallest delay cell */ 1329 if (start_final == 0) 1330 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 1331 else 1332 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 1333 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 1334 delay, len_final, final_phase); 1335 1336 delay_phase.maxlen = len_final; 1337 delay_phase.start = start_final; 1338 delay_phase.final_phase = final_phase; 1339 return delay_phase; 1340 } 1341 1342 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 1343 { 1344 struct msdc_host *host = mmc_priv(mmc); 1345 u32 rise_delay = 0, fall_delay = 0; 1346 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1347 struct msdc_delay_phase internal_delay_phase; 1348 u8 final_delay, final_maxlen; 1349 u32 internal_delay = 0; 1350 int cmd_err; 1351 int i, j; 1352 1353 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 1354 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 1355 sdr_set_field(host->base + MSDC_PAD_TUNE, 1356 MSDC_PAD_TUNE_CMDRRDLY, 1357 host->hs200_cmd_int_delay); 1358 1359 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1360 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1361 sdr_set_field(host->base + MSDC_PAD_TUNE, 1362 MSDC_PAD_TUNE_CMDRDLY, i); 1363 /* 1364 * Using the same parameters, it may sometimes pass the test, 1365 * but sometimes it may fail. To make sure the parameters are 1366 * more stable, we test each set of parameters 3 times. 1367 */ 1368 for (j = 0; j < 3; j++) { 1369 mmc_send_tuning(mmc, opcode, &cmd_err); 1370 if (!cmd_err) { 1371 rise_delay |= (1 << i); 1372 } else { 1373 rise_delay &= ~(1 << i); 1374 break; 1375 } 1376 } 1377 } 1378 final_rise_delay = get_best_delay(host, rise_delay); 1379 /* if rising edge has enough margin, then do not scan falling edge */ 1380 if (final_rise_delay.maxlen >= 12 && final_rise_delay.start < 4) 1381 goto skip_fall; 1382 1383 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1384 for (i = 0; i < PAD_DELAY_MAX; i++) { 1385 sdr_set_field(host->base + MSDC_PAD_TUNE, 1386 MSDC_PAD_TUNE_CMDRDLY, i); 1387 /* 1388 * Using the same parameters, it may sometimes pass the test, 1389 * but sometimes it may fail. To make sure the parameters are 1390 * more stable, we test each set of parameters 3 times. 1391 */ 1392 for (j = 0; j < 3; j++) { 1393 mmc_send_tuning(mmc, opcode, &cmd_err); 1394 if (!cmd_err) { 1395 fall_delay |= (1 << i); 1396 } else { 1397 fall_delay &= ~(1 << i); 1398 break; 1399 } 1400 } 1401 } 1402 final_fall_delay = get_best_delay(host, fall_delay); 1403 1404 skip_fall: 1405 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1406 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 1407 final_maxlen = final_fall_delay.maxlen; 1408 if (final_maxlen == final_rise_delay.maxlen) { 1409 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1410 sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY, 1411 final_rise_delay.final_phase); 1412 final_delay = final_rise_delay.final_phase; 1413 } else { 1414 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1415 sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY, 1416 final_fall_delay.final_phase); 1417 final_delay = final_fall_delay.final_phase; 1418 } 1419 if (host->hs200_cmd_int_delay) 1420 goto skip_internal; 1421 1422 for (i = 0; i < PAD_DELAY_MAX; i++) { 1423 sdr_set_field(host->base + MSDC_PAD_TUNE, 1424 MSDC_PAD_TUNE_CMDRRDLY, i); 1425 mmc_send_tuning(mmc, opcode, &cmd_err); 1426 if (!cmd_err) 1427 internal_delay |= (1 << i); 1428 } 1429 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 1430 internal_delay_phase = get_best_delay(host, internal_delay); 1431 sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, 1432 internal_delay_phase.final_phase); 1433 skip_internal: 1434 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 1435 return final_delay == 0xff ? -EIO : 0; 1436 } 1437 1438 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 1439 { 1440 struct msdc_host *host = mmc_priv(mmc); 1441 u32 cmd_delay = 0; 1442 struct msdc_delay_phase final_cmd_delay = { 0,}; 1443 u8 final_delay; 1444 int cmd_err; 1445 int i, j; 1446 1447 /* select EMMC50 PAD CMD tune */ 1448 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 1449 1450 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 1451 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 1452 sdr_set_field(host->base + MSDC_PAD_TUNE, 1453 MSDC_PAD_TUNE_CMDRRDLY, 1454 host->hs200_cmd_int_delay); 1455 1456 if (host->hs400_cmd_resp_sel_rising) 1457 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1458 else 1459 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1460 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1461 sdr_set_field(host->base + PAD_CMD_TUNE, 1462 PAD_CMD_TUNE_RX_DLY3, i); 1463 /* 1464 * Using the same parameters, it may sometimes pass the test, 1465 * but sometimes it may fail. To make sure the parameters are 1466 * more stable, we test each set of parameters 3 times. 1467 */ 1468 for (j = 0; j < 3; j++) { 1469 mmc_send_tuning(mmc, opcode, &cmd_err); 1470 if (!cmd_err) { 1471 cmd_delay |= (1 << i); 1472 } else { 1473 cmd_delay &= ~(1 << i); 1474 break; 1475 } 1476 } 1477 } 1478 final_cmd_delay = get_best_delay(host, cmd_delay); 1479 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 1480 final_cmd_delay.final_phase); 1481 final_delay = final_cmd_delay.final_phase; 1482 1483 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 1484 return final_delay == 0xff ? -EIO : 0; 1485 } 1486 1487 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 1488 { 1489 struct msdc_host *host = mmc_priv(mmc); 1490 u32 rise_delay = 0, fall_delay = 0; 1491 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1492 u8 final_delay, final_maxlen; 1493 int i, ret; 1494 1495 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1496 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1497 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1498 sdr_set_field(host->base + MSDC_PAD_TUNE, 1499 MSDC_PAD_TUNE_DATRRDLY, i); 1500 ret = mmc_send_tuning(mmc, opcode, NULL); 1501 if (!ret) 1502 rise_delay |= (1 << i); 1503 } 1504 final_rise_delay = get_best_delay(host, rise_delay); 1505 /* if rising edge has enough margin, then do not scan falling edge */ 1506 if (final_rise_delay.maxlen >= 12 || 1507 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1508 goto skip_fall; 1509 1510 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1511 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1512 for (i = 0; i < PAD_DELAY_MAX; i++) { 1513 sdr_set_field(host->base + MSDC_PAD_TUNE, 1514 MSDC_PAD_TUNE_DATRRDLY, i); 1515 ret = mmc_send_tuning(mmc, opcode, NULL); 1516 if (!ret) 1517 fall_delay |= (1 << i); 1518 } 1519 final_fall_delay = get_best_delay(host, fall_delay); 1520 1521 skip_fall: 1522 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1523 if (final_maxlen == final_rise_delay.maxlen) { 1524 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1525 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1526 sdr_set_field(host->base + MSDC_PAD_TUNE, 1527 MSDC_PAD_TUNE_DATRRDLY, 1528 final_rise_delay.final_phase); 1529 final_delay = final_rise_delay.final_phase; 1530 } else { 1531 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1532 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1533 sdr_set_field(host->base + MSDC_PAD_TUNE, 1534 MSDC_PAD_TUNE_DATRRDLY, 1535 final_fall_delay.final_phase); 1536 final_delay = final_fall_delay.final_phase; 1537 } 1538 1539 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 1540 return final_delay == 0xff ? -EIO : 0; 1541 } 1542 1543 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1544 { 1545 struct msdc_host *host = mmc_priv(mmc); 1546 int ret; 1547 1548 if (host->hs400_mode) 1549 ret = hs400_tune_response(mmc, opcode); 1550 else 1551 ret = msdc_tune_response(mmc, opcode); 1552 if (ret == -EIO) { 1553 dev_err(host->dev, "Tune response fail!\n"); 1554 return ret; 1555 } 1556 if (host->hs400_mode == false) { 1557 ret = msdc_tune_data(mmc, opcode); 1558 if (ret == -EIO) 1559 dev_err(host->dev, "Tune data fail!\n"); 1560 } 1561 1562 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1563 host->saved_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE); 1564 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 1565 return ret; 1566 } 1567 1568 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 1569 { 1570 struct msdc_host *host = mmc_priv(mmc); 1571 host->hs400_mode = true; 1572 1573 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 1574 return 0; 1575 } 1576 1577 static void msdc_hw_reset(struct mmc_host *mmc) 1578 { 1579 struct msdc_host *host = mmc_priv(mmc); 1580 1581 sdr_set_bits(host->base + EMMC_IOCON, 1); 1582 udelay(10); /* 10us is enough */ 1583 sdr_clr_bits(host->base + EMMC_IOCON, 1); 1584 } 1585 1586 static struct mmc_host_ops mt_msdc_ops = { 1587 .post_req = msdc_post_req, 1588 .pre_req = msdc_pre_req, 1589 .request = msdc_ops_request, 1590 .set_ios = msdc_ops_set_ios, 1591 .get_ro = mmc_gpio_get_ro, 1592 .start_signal_voltage_switch = msdc_ops_switch_volt, 1593 .card_busy = msdc_card_busy, 1594 .execute_tuning = msdc_execute_tuning, 1595 .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 1596 .hw_reset = msdc_hw_reset, 1597 }; 1598 1599 static void msdc_of_property_parse(struct platform_device *pdev, 1600 struct msdc_host *host) 1601 { 1602 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 1603 &host->hs400_ds_delay); 1604 1605 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 1606 &host->hs200_cmd_int_delay); 1607 1608 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 1609 &host->hs400_cmd_int_delay); 1610 1611 if (of_property_read_bool(pdev->dev.of_node, 1612 "mediatek,hs400-cmd-resp-sel-rising")) 1613 host->hs400_cmd_resp_sel_rising = true; 1614 else 1615 host->hs400_cmd_resp_sel_rising = false; 1616 } 1617 1618 static int msdc_drv_probe(struct platform_device *pdev) 1619 { 1620 struct mmc_host *mmc; 1621 struct msdc_host *host; 1622 struct resource *res; 1623 int ret; 1624 1625 if (!pdev->dev.of_node) { 1626 dev_err(&pdev->dev, "No DT found\n"); 1627 return -EINVAL; 1628 } 1629 /* Allocate MMC host for this device */ 1630 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 1631 if (!mmc) 1632 return -ENOMEM; 1633 1634 host = mmc_priv(mmc); 1635 ret = mmc_of_parse(mmc); 1636 if (ret) 1637 goto host_free; 1638 1639 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1640 host->base = devm_ioremap_resource(&pdev->dev, res); 1641 if (IS_ERR(host->base)) { 1642 ret = PTR_ERR(host->base); 1643 goto host_free; 1644 } 1645 1646 ret = mmc_regulator_get_supply(mmc); 1647 if (ret == -EPROBE_DEFER) 1648 goto host_free; 1649 1650 host->src_clk = devm_clk_get(&pdev->dev, "source"); 1651 if (IS_ERR(host->src_clk)) { 1652 ret = PTR_ERR(host->src_clk); 1653 goto host_free; 1654 } 1655 1656 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 1657 if (IS_ERR(host->h_clk)) { 1658 ret = PTR_ERR(host->h_clk); 1659 goto host_free; 1660 } 1661 1662 host->irq = platform_get_irq(pdev, 0); 1663 if (host->irq < 0) { 1664 ret = -EINVAL; 1665 goto host_free; 1666 } 1667 1668 host->pinctrl = devm_pinctrl_get(&pdev->dev); 1669 if (IS_ERR(host->pinctrl)) { 1670 ret = PTR_ERR(host->pinctrl); 1671 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 1672 goto host_free; 1673 } 1674 1675 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 1676 if (IS_ERR(host->pins_default)) { 1677 ret = PTR_ERR(host->pins_default); 1678 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 1679 goto host_free; 1680 } 1681 1682 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 1683 if (IS_ERR(host->pins_uhs)) { 1684 ret = PTR_ERR(host->pins_uhs); 1685 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 1686 goto host_free; 1687 } 1688 1689 msdc_of_property_parse(pdev, host); 1690 1691 host->dev = &pdev->dev; 1692 host->mmc = mmc; 1693 host->src_clk_freq = clk_get_rate(host->src_clk); 1694 /* Set host parameters to mmc */ 1695 mmc->ops = &mt_msdc_ops; 1696 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 1697 1698 mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; 1699 /* MMC core transfer sizes tunable parameters */ 1700 mmc->max_segs = MAX_BD_NUM; 1701 mmc->max_seg_size = BDMA_DESC_BUFLEN; 1702 mmc->max_blk_size = 2048; 1703 mmc->max_req_size = 512 * 1024; 1704 mmc->max_blk_count = mmc->max_req_size / 512; 1705 host->dma_mask = DMA_BIT_MASK(32); 1706 mmc_dev(mmc)->dma_mask = &host->dma_mask; 1707 1708 host->timeout_clks = 3 * 1048576; 1709 host->dma.gpd = dma_alloc_coherent(&pdev->dev, 1710 2 * sizeof(struct mt_gpdma_desc), 1711 &host->dma.gpd_addr, GFP_KERNEL); 1712 host->dma.bd = dma_alloc_coherent(&pdev->dev, 1713 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 1714 &host->dma.bd_addr, GFP_KERNEL); 1715 if (!host->dma.gpd || !host->dma.bd) { 1716 ret = -ENOMEM; 1717 goto release_mem; 1718 } 1719 msdc_init_gpd_bd(host, &host->dma); 1720 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 1721 spin_lock_init(&host->lock); 1722 1723 platform_set_drvdata(pdev, mmc); 1724 msdc_ungate_clock(host); 1725 msdc_init_hw(host); 1726 1727 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 1728 IRQF_TRIGGER_LOW | IRQF_ONESHOT, pdev->name, host); 1729 if (ret) 1730 goto release; 1731 1732 pm_runtime_set_active(host->dev); 1733 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 1734 pm_runtime_use_autosuspend(host->dev); 1735 pm_runtime_enable(host->dev); 1736 ret = mmc_add_host(mmc); 1737 1738 if (ret) 1739 goto end; 1740 1741 return 0; 1742 end: 1743 pm_runtime_disable(host->dev); 1744 release: 1745 platform_set_drvdata(pdev, NULL); 1746 msdc_deinit_hw(host); 1747 msdc_gate_clock(host); 1748 release_mem: 1749 if (host->dma.gpd) 1750 dma_free_coherent(&pdev->dev, 1751 2 * sizeof(struct mt_gpdma_desc), 1752 host->dma.gpd, host->dma.gpd_addr); 1753 if (host->dma.bd) 1754 dma_free_coherent(&pdev->dev, 1755 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 1756 host->dma.bd, host->dma.bd_addr); 1757 host_free: 1758 mmc_free_host(mmc); 1759 1760 return ret; 1761 } 1762 1763 static int msdc_drv_remove(struct platform_device *pdev) 1764 { 1765 struct mmc_host *mmc; 1766 struct msdc_host *host; 1767 1768 mmc = platform_get_drvdata(pdev); 1769 host = mmc_priv(mmc); 1770 1771 pm_runtime_get_sync(host->dev); 1772 1773 platform_set_drvdata(pdev, NULL); 1774 mmc_remove_host(host->mmc); 1775 msdc_deinit_hw(host); 1776 msdc_gate_clock(host); 1777 1778 pm_runtime_disable(host->dev); 1779 pm_runtime_put_noidle(host->dev); 1780 dma_free_coherent(&pdev->dev, 1781 sizeof(struct mt_gpdma_desc), 1782 host->dma.gpd, host->dma.gpd_addr); 1783 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 1784 host->dma.bd, host->dma.bd_addr); 1785 1786 mmc_free_host(host->mmc); 1787 1788 return 0; 1789 } 1790 1791 #ifdef CONFIG_PM 1792 static void msdc_save_reg(struct msdc_host *host) 1793 { 1794 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 1795 host->save_para.iocon = readl(host->base + MSDC_IOCON); 1796 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 1797 host->save_para.pad_tune = readl(host->base + MSDC_PAD_TUNE); 1798 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 1799 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 1800 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 1801 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 1802 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 1803 } 1804 1805 static void msdc_restore_reg(struct msdc_host *host) 1806 { 1807 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 1808 writel(host->save_para.iocon, host->base + MSDC_IOCON); 1809 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 1810 writel(host->save_para.pad_tune, host->base + MSDC_PAD_TUNE); 1811 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 1812 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 1813 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 1814 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 1815 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 1816 } 1817 1818 static int msdc_runtime_suspend(struct device *dev) 1819 { 1820 struct mmc_host *mmc = dev_get_drvdata(dev); 1821 struct msdc_host *host = mmc_priv(mmc); 1822 1823 msdc_save_reg(host); 1824 msdc_gate_clock(host); 1825 return 0; 1826 } 1827 1828 static int msdc_runtime_resume(struct device *dev) 1829 { 1830 struct mmc_host *mmc = dev_get_drvdata(dev); 1831 struct msdc_host *host = mmc_priv(mmc); 1832 1833 msdc_ungate_clock(host); 1834 msdc_restore_reg(host); 1835 return 0; 1836 } 1837 #endif 1838 1839 static const struct dev_pm_ops msdc_dev_pm_ops = { 1840 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1841 pm_runtime_force_resume) 1842 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 1843 }; 1844 1845 static const struct of_device_id msdc_of_ids[] = { 1846 { .compatible = "mediatek,mt8135-mmc", }, 1847 {} 1848 }; 1849 MODULE_DEVICE_TABLE(of, msdc_of_ids); 1850 1851 static struct platform_driver mt_msdc_driver = { 1852 .probe = msdc_drv_probe, 1853 .remove = msdc_drv_remove, 1854 .driver = { 1855 .name = "mtk-msdc", 1856 .of_match_table = msdc_of_ids, 1857 .pm = &msdc_dev_pm_ops, 1858 }, 1859 }; 1860 1861 module_platform_driver(mt_msdc_driver); 1862 MODULE_LICENSE("GPL v2"); 1863 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 1864