xref: /openbmc/linux/drivers/mmc/host/mtk-sd.c (revision 151f4e2b)
1 /*
2  * Copyright (c) 2014-2015 MediaTek Inc.
3  * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License version 2 as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  */
14 
15 #include <linux/module.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/ioport.h>
20 #include <linux/irq.h>
21 #include <linux/of_address.h>
22 #include <linux/of_device.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_gpio.h>
25 #include <linux/pinctrl/consumer.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/regulator/consumer.h>
30 #include <linux/slab.h>
31 #include <linux/spinlock.h>
32 #include <linux/interrupt.h>
33 
34 #include <linux/mmc/card.h>
35 #include <linux/mmc/core.h>
36 #include <linux/mmc/host.h>
37 #include <linux/mmc/mmc.h>
38 #include <linux/mmc/sd.h>
39 #include <linux/mmc/sdio.h>
40 #include <linux/mmc/slot-gpio.h>
41 
42 #define MAX_BD_NUM          1024
43 
44 /*--------------------------------------------------------------------------*/
45 /* Common Definition                                                        */
46 /*--------------------------------------------------------------------------*/
47 #define MSDC_BUS_1BITS          0x0
48 #define MSDC_BUS_4BITS          0x1
49 #define MSDC_BUS_8BITS          0x2
50 
51 #define MSDC_BURST_64B          0x6
52 
53 /*--------------------------------------------------------------------------*/
54 /* Register Offset                                                          */
55 /*--------------------------------------------------------------------------*/
56 #define MSDC_CFG         0x0
57 #define MSDC_IOCON       0x04
58 #define MSDC_PS          0x08
59 #define MSDC_INT         0x0c
60 #define MSDC_INTEN       0x10
61 #define MSDC_FIFOCS      0x14
62 #define SDC_CFG          0x30
63 #define SDC_CMD          0x34
64 #define SDC_ARG          0x38
65 #define SDC_STS          0x3c
66 #define SDC_RESP0        0x40
67 #define SDC_RESP1        0x44
68 #define SDC_RESP2        0x48
69 #define SDC_RESP3        0x4c
70 #define SDC_BLK_NUM      0x50
71 #define SDC_ADV_CFG0     0x64
72 #define EMMC_IOCON       0x7c
73 #define SDC_ACMD_RESP    0x80
74 #define DMA_SA_H4BIT     0x8c
75 #define MSDC_DMA_SA      0x90
76 #define MSDC_DMA_CTRL    0x98
77 #define MSDC_DMA_CFG     0x9c
78 #define MSDC_PATCH_BIT   0xb0
79 #define MSDC_PATCH_BIT1  0xb4
80 #define MSDC_PATCH_BIT2  0xb8
81 #define MSDC_PAD_TUNE    0xec
82 #define MSDC_PAD_TUNE0   0xf0
83 #define PAD_DS_TUNE      0x188
84 #define PAD_CMD_TUNE     0x18c
85 #define EMMC50_CFG0      0x208
86 #define EMMC50_CFG3      0x220
87 #define SDC_FIFO_CFG     0x228
88 
89 /*--------------------------------------------------------------------------*/
90 /* Top Pad Register Offset                                                  */
91 /*--------------------------------------------------------------------------*/
92 #define EMMC_TOP_CONTROL	0x00
93 #define EMMC_TOP_CMD		0x04
94 #define EMMC50_PAD_DS_TUNE	0x0c
95 
96 /*--------------------------------------------------------------------------*/
97 /* Register Mask                                                            */
98 /*--------------------------------------------------------------------------*/
99 
100 /* MSDC_CFG mask */
101 #define MSDC_CFG_MODE           (0x1 << 0)	/* RW */
102 #define MSDC_CFG_CKPDN          (0x1 << 1)	/* RW */
103 #define MSDC_CFG_RST            (0x1 << 2)	/* RW */
104 #define MSDC_CFG_PIO            (0x1 << 3)	/* RW */
105 #define MSDC_CFG_CKDRVEN        (0x1 << 4)	/* RW */
106 #define MSDC_CFG_BV18SDT        (0x1 << 5)	/* RW */
107 #define MSDC_CFG_BV18PSS        (0x1 << 6)	/* R  */
108 #define MSDC_CFG_CKSTB          (0x1 << 7)	/* R  */
109 #define MSDC_CFG_CKDIV          (0xff << 8)	/* RW */
110 #define MSDC_CFG_CKMOD          (0x3 << 16)	/* RW */
111 #define MSDC_CFG_HS400_CK_MODE  (0x1 << 18)	/* RW */
112 #define MSDC_CFG_HS400_CK_MODE_EXTRA  (0x1 << 22)	/* RW */
113 #define MSDC_CFG_CKDIV_EXTRA    (0xfff << 8)	/* RW */
114 #define MSDC_CFG_CKMOD_EXTRA    (0x3 << 20)	/* RW */
115 
116 /* MSDC_IOCON mask */
117 #define MSDC_IOCON_SDR104CKS    (0x1 << 0)	/* RW */
118 #define MSDC_IOCON_RSPL         (0x1 << 1)	/* RW */
119 #define MSDC_IOCON_DSPL         (0x1 << 2)	/* RW */
120 #define MSDC_IOCON_DDLSEL       (0x1 << 3)	/* RW */
121 #define MSDC_IOCON_DDR50CKD     (0x1 << 4)	/* RW */
122 #define MSDC_IOCON_DSPLSEL      (0x1 << 5)	/* RW */
123 #define MSDC_IOCON_W_DSPL       (0x1 << 8)	/* RW */
124 #define MSDC_IOCON_D0SPL        (0x1 << 16)	/* RW */
125 #define MSDC_IOCON_D1SPL        (0x1 << 17)	/* RW */
126 #define MSDC_IOCON_D2SPL        (0x1 << 18)	/* RW */
127 #define MSDC_IOCON_D3SPL        (0x1 << 19)	/* RW */
128 #define MSDC_IOCON_D4SPL        (0x1 << 20)	/* RW */
129 #define MSDC_IOCON_D5SPL        (0x1 << 21)	/* RW */
130 #define MSDC_IOCON_D6SPL        (0x1 << 22)	/* RW */
131 #define MSDC_IOCON_D7SPL        (0x1 << 23)	/* RW */
132 #define MSDC_IOCON_RISCSZ       (0x3 << 24)	/* RW */
133 
134 /* MSDC_PS mask */
135 #define MSDC_PS_CDEN            (0x1 << 0)	/* RW */
136 #define MSDC_PS_CDSTS           (0x1 << 1)	/* R  */
137 #define MSDC_PS_CDDEBOUNCE      (0xf << 12)	/* RW */
138 #define MSDC_PS_DAT             (0xff << 16)	/* R  */
139 #define MSDC_PS_CMD             (0x1 << 24)	/* R  */
140 #define MSDC_PS_WP              (0x1 << 31)	/* R  */
141 
142 /* MSDC_INT mask */
143 #define MSDC_INT_MMCIRQ         (0x1 << 0)	/* W1C */
144 #define MSDC_INT_CDSC           (0x1 << 1)	/* W1C */
145 #define MSDC_INT_ACMDRDY        (0x1 << 3)	/* W1C */
146 #define MSDC_INT_ACMDTMO        (0x1 << 4)	/* W1C */
147 #define MSDC_INT_ACMDCRCERR     (0x1 << 5)	/* W1C */
148 #define MSDC_INT_DMAQ_EMPTY     (0x1 << 6)	/* W1C */
149 #define MSDC_INT_SDIOIRQ        (0x1 << 7)	/* W1C */
150 #define MSDC_INT_CMDRDY         (0x1 << 8)	/* W1C */
151 #define MSDC_INT_CMDTMO         (0x1 << 9)	/* W1C */
152 #define MSDC_INT_RSPCRCERR      (0x1 << 10)	/* W1C */
153 #define MSDC_INT_CSTA           (0x1 << 11)	/* R */
154 #define MSDC_INT_XFER_COMPL     (0x1 << 12)	/* W1C */
155 #define MSDC_INT_DXFER_DONE     (0x1 << 13)	/* W1C */
156 #define MSDC_INT_DATTMO         (0x1 << 14)	/* W1C */
157 #define MSDC_INT_DATCRCERR      (0x1 << 15)	/* W1C */
158 #define MSDC_INT_ACMD19_DONE    (0x1 << 16)	/* W1C */
159 #define MSDC_INT_DMA_BDCSERR    (0x1 << 17)	/* W1C */
160 #define MSDC_INT_DMA_GPDCSERR   (0x1 << 18)	/* W1C */
161 #define MSDC_INT_DMA_PROTECT    (0x1 << 19)	/* W1C */
162 
163 /* MSDC_INTEN mask */
164 #define MSDC_INTEN_MMCIRQ       (0x1 << 0)	/* RW */
165 #define MSDC_INTEN_CDSC         (0x1 << 1)	/* RW */
166 #define MSDC_INTEN_ACMDRDY      (0x1 << 3)	/* RW */
167 #define MSDC_INTEN_ACMDTMO      (0x1 << 4)	/* RW */
168 #define MSDC_INTEN_ACMDCRCERR   (0x1 << 5)	/* RW */
169 #define MSDC_INTEN_DMAQ_EMPTY   (0x1 << 6)	/* RW */
170 #define MSDC_INTEN_SDIOIRQ      (0x1 << 7)	/* RW */
171 #define MSDC_INTEN_CMDRDY       (0x1 << 8)	/* RW */
172 #define MSDC_INTEN_CMDTMO       (0x1 << 9)	/* RW */
173 #define MSDC_INTEN_RSPCRCERR    (0x1 << 10)	/* RW */
174 #define MSDC_INTEN_CSTA         (0x1 << 11)	/* RW */
175 #define MSDC_INTEN_XFER_COMPL   (0x1 << 12)	/* RW */
176 #define MSDC_INTEN_DXFER_DONE   (0x1 << 13)	/* RW */
177 #define MSDC_INTEN_DATTMO       (0x1 << 14)	/* RW */
178 #define MSDC_INTEN_DATCRCERR    (0x1 << 15)	/* RW */
179 #define MSDC_INTEN_ACMD19_DONE  (0x1 << 16)	/* RW */
180 #define MSDC_INTEN_DMA_BDCSERR  (0x1 << 17)	/* RW */
181 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18)	/* RW */
182 #define MSDC_INTEN_DMA_PROTECT  (0x1 << 19)	/* RW */
183 
184 /* MSDC_FIFOCS mask */
185 #define MSDC_FIFOCS_RXCNT       (0xff << 0)	/* R */
186 #define MSDC_FIFOCS_TXCNT       (0xff << 16)	/* R */
187 #define MSDC_FIFOCS_CLR         (0x1 << 31)	/* RW */
188 
189 /* SDC_CFG mask */
190 #define SDC_CFG_SDIOINTWKUP     (0x1 << 0)	/* RW */
191 #define SDC_CFG_INSWKUP         (0x1 << 1)	/* RW */
192 #define SDC_CFG_BUSWIDTH        (0x3 << 16)	/* RW */
193 #define SDC_CFG_SDIO            (0x1 << 19)	/* RW */
194 #define SDC_CFG_SDIOIDE         (0x1 << 20)	/* RW */
195 #define SDC_CFG_INTATGAP        (0x1 << 21)	/* RW */
196 #define SDC_CFG_DTOC            (0xff << 24)	/* RW */
197 
198 /* SDC_STS mask */
199 #define SDC_STS_SDCBUSY         (0x1 << 0)	/* RW */
200 #define SDC_STS_CMDBUSY         (0x1 << 1)	/* RW */
201 #define SDC_STS_SWR_COMPL       (0x1 << 31)	/* RW */
202 
203 /* SDC_ADV_CFG0 mask */
204 #define SDC_RX_ENHANCE_EN	(0x1 << 20)	/* RW */
205 
206 /* DMA_SA_H4BIT mask */
207 #define DMA_ADDR_HIGH_4BIT      (0xf << 0)      /* RW */
208 
209 /* MSDC_DMA_CTRL mask */
210 #define MSDC_DMA_CTRL_START     (0x1 << 0)	/* W */
211 #define MSDC_DMA_CTRL_STOP      (0x1 << 1)	/* W */
212 #define MSDC_DMA_CTRL_RESUME    (0x1 << 2)	/* W */
213 #define MSDC_DMA_CTRL_MODE      (0x1 << 8)	/* RW */
214 #define MSDC_DMA_CTRL_LASTBUF   (0x1 << 10)	/* RW */
215 #define MSDC_DMA_CTRL_BRUSTSZ   (0x7 << 12)	/* RW */
216 
217 /* MSDC_DMA_CFG mask */
218 #define MSDC_DMA_CFG_STS        (0x1 << 0)	/* R */
219 #define MSDC_DMA_CFG_DECSEN     (0x1 << 1)	/* RW */
220 #define MSDC_DMA_CFG_AHBHPROT2  (0x2 << 8)	/* RW */
221 #define MSDC_DMA_CFG_ACTIVEEN   (0x2 << 12)	/* RW */
222 #define MSDC_DMA_CFG_CS12B16B   (0x1 << 16)	/* RW */
223 
224 /* MSDC_PATCH_BIT mask */
225 #define MSDC_PATCH_BIT_ODDSUPP    (0x1 <<  1)	/* RW */
226 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 <<  7)
227 #define MSDC_CKGEN_MSDC_DLY_SEL   (0x1f << 10)
228 #define MSDC_PATCH_BIT_IODSSEL    (0x1 << 16)	/* RW */
229 #define MSDC_PATCH_BIT_IOINTSEL   (0x1 << 17)	/* RW */
230 #define MSDC_PATCH_BIT_BUSYDLY    (0xf << 18)	/* RW */
231 #define MSDC_PATCH_BIT_WDOD       (0xf << 22)	/* RW */
232 #define MSDC_PATCH_BIT_IDRTSEL    (0x1 << 26)	/* RW */
233 #define MSDC_PATCH_BIT_CMDFSEL    (0x1 << 27)	/* RW */
234 #define MSDC_PATCH_BIT_INTDLSEL   (0x1 << 28)	/* RW */
235 #define MSDC_PATCH_BIT_SPCPUSH    (0x1 << 29)	/* RW */
236 #define MSDC_PATCH_BIT_DECRCTMO   (0x1 << 30)	/* RW */
237 
238 #define MSDC_PATCH_BIT1_STOP_DLY  (0xf << 8)    /* RW */
239 
240 #define MSDC_PATCH_BIT2_CFGRESP   (0x1 << 15)   /* RW */
241 #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28)   /* RW */
242 #define MSDC_PB2_SUPPORT_64G      (0x1 << 1)    /* RW */
243 #define MSDC_PB2_RESPWAIT         (0x3 << 2)    /* RW */
244 #define MSDC_PB2_RESPSTSENSEL     (0x7 << 16)   /* RW */
245 #define MSDC_PB2_CRCSTSENSEL      (0x7 << 29)   /* RW */
246 
247 #define MSDC_PAD_TUNE_DATWRDLY	  (0x1f <<  0)	/* RW */
248 #define MSDC_PAD_TUNE_DATRRDLY	  (0x1f <<  8)	/* RW */
249 #define MSDC_PAD_TUNE_CMDRDLY	  (0x1f << 16)  /* RW */
250 #define MSDC_PAD_TUNE_CMDRRDLY	  (0x1f << 22)	/* RW */
251 #define MSDC_PAD_TUNE_CLKTDLY	  (0x1f << 27)  /* RW */
252 #define MSDC_PAD_TUNE_RXDLYSEL	  (0x1 << 15)   /* RW */
253 #define MSDC_PAD_TUNE_RD_SEL	  (0x1 << 13)   /* RW */
254 #define MSDC_PAD_TUNE_CMD_SEL	  (0x1 << 21)   /* RW */
255 
256 #define PAD_DS_TUNE_DLY1	  (0x1f << 2)   /* RW */
257 #define PAD_DS_TUNE_DLY2	  (0x1f << 7)   /* RW */
258 #define PAD_DS_TUNE_DLY3	  (0x1f << 12)  /* RW */
259 
260 #define PAD_CMD_TUNE_RX_DLY3	  (0x1f << 1)  /* RW */
261 
262 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0)   /* RW */
263 #define EMMC50_CFG_CRCSTS_EDGE    (0x1 << 3)   /* RW */
264 #define EMMC50_CFG_CFCSTS_SEL     (0x1 << 4)   /* RW */
265 
266 #define EMMC50_CFG3_OUTS_WR       (0x1f << 0)  /* RW */
267 
268 #define SDC_FIFO_CFG_WRVALIDSEL   (0x1 << 24)  /* RW */
269 #define SDC_FIFO_CFG_RDVALIDSEL   (0x1 << 25)  /* RW */
270 
271 /* EMMC_TOP_CONTROL mask */
272 #define PAD_RXDLY_SEL           (0x1 << 0)      /* RW */
273 #define DELAY_EN                (0x1 << 1)      /* RW */
274 #define PAD_DAT_RD_RXDLY2       (0x1f << 2)     /* RW */
275 #define PAD_DAT_RD_RXDLY        (0x1f << 7)     /* RW */
276 #define PAD_DAT_RD_RXDLY2_SEL   (0x1 << 12)     /* RW */
277 #define PAD_DAT_RD_RXDLY_SEL    (0x1 << 13)     /* RW */
278 #define DATA_K_VALUE_SEL        (0x1 << 14)     /* RW */
279 #define SDC_RX_ENH_EN           (0x1 << 15)     /* TW */
280 
281 /* EMMC_TOP_CMD mask */
282 #define PAD_CMD_RXDLY2          (0x1f << 0)     /* RW */
283 #define PAD_CMD_RXDLY           (0x1f << 5)     /* RW */
284 #define PAD_CMD_RD_RXDLY2_SEL   (0x1 << 10)     /* RW */
285 #define PAD_CMD_RD_RXDLY_SEL    (0x1 << 11)     /* RW */
286 #define PAD_CMD_TX_DLY          (0x1f << 12)    /* RW */
287 
288 #define REQ_CMD_EIO  (0x1 << 0)
289 #define REQ_CMD_TMO  (0x1 << 1)
290 #define REQ_DAT_ERR  (0x1 << 2)
291 #define REQ_STOP_EIO (0x1 << 3)
292 #define REQ_STOP_TMO (0x1 << 4)
293 #define REQ_CMD_BUSY (0x1 << 5)
294 
295 #define MSDC_PREPARE_FLAG (0x1 << 0)
296 #define MSDC_ASYNC_FLAG (0x1 << 1)
297 #define MSDC_MMAP_FLAG (0x1 << 2)
298 
299 #define MTK_MMC_AUTOSUSPEND_DELAY	50
300 #define CMD_TIMEOUT         (HZ/10 * 5)	/* 100ms x5 */
301 #define DAT_TIMEOUT         (HZ    * 5)	/* 1000ms x5 */
302 
303 #define DEFAULT_DEBOUNCE	(8)	/* 8 cycles CD debounce */
304 
305 #define PAD_DELAY_MAX	32 /* PAD delay cells */
306 /*--------------------------------------------------------------------------*/
307 /* Descriptor Structure                                                     */
308 /*--------------------------------------------------------------------------*/
309 struct mt_gpdma_desc {
310 	u32 gpd_info;
311 #define GPDMA_DESC_HWO		(0x1 << 0)
312 #define GPDMA_DESC_BDP		(0x1 << 1)
313 #define GPDMA_DESC_CHECKSUM	(0xff << 8) /* bit8 ~ bit15 */
314 #define GPDMA_DESC_INT		(0x1 << 16)
315 #define GPDMA_DESC_NEXT_H4	(0xf << 24)
316 #define GPDMA_DESC_PTR_H4	(0xf << 28)
317 	u32 next;
318 	u32 ptr;
319 	u32 gpd_data_len;
320 #define GPDMA_DESC_BUFLEN	(0xffff) /* bit0 ~ bit15 */
321 #define GPDMA_DESC_EXTLEN	(0xff << 16) /* bit16 ~ bit23 */
322 	u32 arg;
323 	u32 blknum;
324 	u32 cmd;
325 };
326 
327 struct mt_bdma_desc {
328 	u32 bd_info;
329 #define BDMA_DESC_EOL		(0x1 << 0)
330 #define BDMA_DESC_CHECKSUM	(0xff << 8) /* bit8 ~ bit15 */
331 #define BDMA_DESC_BLKPAD	(0x1 << 17)
332 #define BDMA_DESC_DWPAD		(0x1 << 18)
333 #define BDMA_DESC_NEXT_H4	(0xf << 24)
334 #define BDMA_DESC_PTR_H4	(0xf << 28)
335 	u32 next;
336 	u32 ptr;
337 	u32 bd_data_len;
338 #define BDMA_DESC_BUFLEN	(0xffff) /* bit0 ~ bit15 */
339 };
340 
341 struct msdc_dma {
342 	struct scatterlist *sg;	/* I/O scatter list */
343 	struct mt_gpdma_desc *gpd;		/* pointer to gpd array */
344 	struct mt_bdma_desc *bd;		/* pointer to bd array */
345 	dma_addr_t gpd_addr;	/* the physical address of gpd array */
346 	dma_addr_t bd_addr;	/* the physical address of bd array */
347 };
348 
349 struct msdc_save_para {
350 	u32 msdc_cfg;
351 	u32 iocon;
352 	u32 sdc_cfg;
353 	u32 pad_tune;
354 	u32 patch_bit0;
355 	u32 patch_bit1;
356 	u32 patch_bit2;
357 	u32 pad_ds_tune;
358 	u32 pad_cmd_tune;
359 	u32 emmc50_cfg0;
360 	u32 emmc50_cfg3;
361 	u32 sdc_fifo_cfg;
362 	u32 emmc_top_control;
363 	u32 emmc_top_cmd;
364 	u32 emmc50_pad_ds_tune;
365 };
366 
367 struct mtk_mmc_compatible {
368 	u8 clk_div_bits;
369 	bool hs400_tune; /* only used for MT8173 */
370 	u32 pad_tune_reg;
371 	bool async_fifo;
372 	bool data_tune;
373 	bool busy_check;
374 	bool stop_clk_fix;
375 	bool enhance_rx;
376 	bool support_64g;
377 	bool use_internal_cd;
378 };
379 
380 struct msdc_tune_para {
381 	u32 iocon;
382 	u32 pad_tune;
383 	u32 pad_cmd_tune;
384 	u32 emmc_top_control;
385 	u32 emmc_top_cmd;
386 };
387 
388 struct msdc_delay_phase {
389 	u8 maxlen;
390 	u8 start;
391 	u8 final_phase;
392 };
393 
394 struct msdc_host {
395 	struct device *dev;
396 	const struct mtk_mmc_compatible *dev_comp;
397 	struct mmc_host *mmc;	/* mmc structure */
398 	int cmd_rsp;
399 
400 	spinlock_t lock;
401 	struct mmc_request *mrq;
402 	struct mmc_command *cmd;
403 	struct mmc_data *data;
404 	int error;
405 
406 	void __iomem *base;		/* host base address */
407 	void __iomem *top_base;		/* host top register base address */
408 
409 	struct msdc_dma dma;	/* dma channel */
410 	u64 dma_mask;
411 
412 	u32 timeout_ns;		/* data timeout ns */
413 	u32 timeout_clks;	/* data timeout clks */
414 
415 	struct pinctrl *pinctrl;
416 	struct pinctrl_state *pins_default;
417 	struct pinctrl_state *pins_uhs;
418 	struct delayed_work req_timeout;
419 	int irq;		/* host interrupt */
420 
421 	struct clk *src_clk;	/* msdc source clock */
422 	struct clk *h_clk;      /* msdc h_clk */
423 	struct clk *bus_clk;	/* bus clock which used to access register */
424 	struct clk *src_clk_cg; /* msdc source clock control gate */
425 	u32 mclk;		/* mmc subsystem clock frequency */
426 	u32 src_clk_freq;	/* source clock frequency */
427 	unsigned char timing;
428 	bool vqmmc_enabled;
429 	u32 latch_ck;
430 	u32 hs400_ds_delay;
431 	u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
432 	u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
433 	bool hs400_cmd_resp_sel_rising;
434 				 /* cmd response sample selection for HS400 */
435 	bool hs400_mode;	/* current eMMC will run at hs400 mode */
436 	bool internal_cd;	/* Use internal card-detect logic */
437 	struct msdc_save_para save_para; /* used when gate HCLK */
438 	struct msdc_tune_para def_tune_para; /* default tune setting */
439 	struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
440 };
441 
442 static const struct mtk_mmc_compatible mt8135_compat = {
443 	.clk_div_bits = 8,
444 	.hs400_tune = false,
445 	.pad_tune_reg = MSDC_PAD_TUNE,
446 	.async_fifo = false,
447 	.data_tune = false,
448 	.busy_check = false,
449 	.stop_clk_fix = false,
450 	.enhance_rx = false,
451 	.support_64g = false,
452 };
453 
454 static const struct mtk_mmc_compatible mt8173_compat = {
455 	.clk_div_bits = 8,
456 	.hs400_tune = true,
457 	.pad_tune_reg = MSDC_PAD_TUNE,
458 	.async_fifo = false,
459 	.data_tune = false,
460 	.busy_check = false,
461 	.stop_clk_fix = false,
462 	.enhance_rx = false,
463 	.support_64g = false,
464 };
465 
466 static const struct mtk_mmc_compatible mt8183_compat = {
467 	.clk_div_bits = 12,
468 	.hs400_tune = false,
469 	.pad_tune_reg = MSDC_PAD_TUNE0,
470 	.async_fifo = true,
471 	.data_tune = true,
472 	.busy_check = true,
473 	.stop_clk_fix = true,
474 	.enhance_rx = true,
475 	.support_64g = true,
476 };
477 
478 static const struct mtk_mmc_compatible mt2701_compat = {
479 	.clk_div_bits = 12,
480 	.hs400_tune = false,
481 	.pad_tune_reg = MSDC_PAD_TUNE0,
482 	.async_fifo = true,
483 	.data_tune = true,
484 	.busy_check = false,
485 	.stop_clk_fix = false,
486 	.enhance_rx = false,
487 	.support_64g = false,
488 };
489 
490 static const struct mtk_mmc_compatible mt2712_compat = {
491 	.clk_div_bits = 12,
492 	.hs400_tune = false,
493 	.pad_tune_reg = MSDC_PAD_TUNE0,
494 	.async_fifo = true,
495 	.data_tune = true,
496 	.busy_check = true,
497 	.stop_clk_fix = true,
498 	.enhance_rx = true,
499 	.support_64g = true,
500 };
501 
502 static const struct mtk_mmc_compatible mt7622_compat = {
503 	.clk_div_bits = 12,
504 	.hs400_tune = false,
505 	.pad_tune_reg = MSDC_PAD_TUNE0,
506 	.async_fifo = true,
507 	.data_tune = true,
508 	.busy_check = true,
509 	.stop_clk_fix = true,
510 	.enhance_rx = true,
511 	.support_64g = false,
512 };
513 
514 static const struct mtk_mmc_compatible mt8516_compat = {
515 	.clk_div_bits = 12,
516 	.hs400_tune = false,
517 	.pad_tune_reg = MSDC_PAD_TUNE0,
518 	.async_fifo = true,
519 	.data_tune = true,
520 	.busy_check = true,
521 	.stop_clk_fix = true,
522 };
523 
524 static const struct mtk_mmc_compatible mt7620_compat = {
525 	.clk_div_bits = 8,
526 	.hs400_tune = false,
527 	.pad_tune_reg = MSDC_PAD_TUNE,
528 	.async_fifo = false,
529 	.data_tune = false,
530 	.busy_check = false,
531 	.stop_clk_fix = false,
532 	.enhance_rx = false,
533 	.use_internal_cd = true,
534 };
535 
536 static const struct of_device_id msdc_of_ids[] = {
537 	{ .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
538 	{ .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
539 	{ .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
540 	{ .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
541 	{ .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
542 	{ .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
543 	{ .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
544 	{ .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
545 	{}
546 };
547 MODULE_DEVICE_TABLE(of, msdc_of_ids);
548 
549 static void sdr_set_bits(void __iomem *reg, u32 bs)
550 {
551 	u32 val = readl(reg);
552 
553 	val |= bs;
554 	writel(val, reg);
555 }
556 
557 static void sdr_clr_bits(void __iomem *reg, u32 bs)
558 {
559 	u32 val = readl(reg);
560 
561 	val &= ~bs;
562 	writel(val, reg);
563 }
564 
565 static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
566 {
567 	unsigned int tv = readl(reg);
568 
569 	tv &= ~field;
570 	tv |= ((val) << (ffs((unsigned int)field) - 1));
571 	writel(tv, reg);
572 }
573 
574 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
575 {
576 	unsigned int tv = readl(reg);
577 
578 	*val = ((tv & field) >> (ffs((unsigned int)field) - 1));
579 }
580 
581 static void msdc_reset_hw(struct msdc_host *host)
582 {
583 	u32 val;
584 
585 	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
586 	while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST)
587 		cpu_relax();
588 
589 	sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
590 	while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR)
591 		cpu_relax();
592 
593 	val = readl(host->base + MSDC_INT);
594 	writel(val, host->base + MSDC_INT);
595 }
596 
597 static void msdc_cmd_next(struct msdc_host *host,
598 		struct mmc_request *mrq, struct mmc_command *cmd);
599 
600 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
601 			MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
602 			MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
603 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
604 			MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
605 			MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
606 
607 static u8 msdc_dma_calcs(u8 *buf, u32 len)
608 {
609 	u32 i, sum = 0;
610 
611 	for (i = 0; i < len; i++)
612 		sum += buf[i];
613 	return 0xff - (u8) sum;
614 }
615 
616 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
617 		struct mmc_data *data)
618 {
619 	unsigned int j, dma_len;
620 	dma_addr_t dma_address;
621 	u32 dma_ctrl;
622 	struct scatterlist *sg;
623 	struct mt_gpdma_desc *gpd;
624 	struct mt_bdma_desc *bd;
625 
626 	sg = data->sg;
627 
628 	gpd = dma->gpd;
629 	bd = dma->bd;
630 
631 	/* modify gpd */
632 	gpd->gpd_info |= GPDMA_DESC_HWO;
633 	gpd->gpd_info |= GPDMA_DESC_BDP;
634 	/* need to clear first. use these bits to calc checksum */
635 	gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
636 	gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
637 
638 	/* modify bd */
639 	for_each_sg(data->sg, sg, data->sg_count, j) {
640 		dma_address = sg_dma_address(sg);
641 		dma_len = sg_dma_len(sg);
642 
643 		/* init bd */
644 		bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
645 		bd[j].bd_info &= ~BDMA_DESC_DWPAD;
646 		bd[j].ptr = lower_32_bits(dma_address);
647 		if (host->dev_comp->support_64g) {
648 			bd[j].bd_info &= ~BDMA_DESC_PTR_H4;
649 			bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf)
650 					 << 28;
651 		}
652 		bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
653 		bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
654 
655 		if (j == data->sg_count - 1) /* the last bd */
656 			bd[j].bd_info |= BDMA_DESC_EOL;
657 		else
658 			bd[j].bd_info &= ~BDMA_DESC_EOL;
659 
660 		/* checksume need to clear first */
661 		bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
662 		bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
663 	}
664 
665 	sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
666 	dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
667 	dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
668 	dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8);
669 	writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
670 	if (host->dev_comp->support_64g)
671 		sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT,
672 			      upper_32_bits(dma->gpd_addr) & 0xf);
673 	writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
674 }
675 
676 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq)
677 {
678 	struct mmc_data *data = mrq->data;
679 
680 	if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
681 		data->host_cookie |= MSDC_PREPARE_FLAG;
682 		data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
683 					    mmc_get_dma_dir(data));
684 	}
685 }
686 
687 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq)
688 {
689 	struct mmc_data *data = mrq->data;
690 
691 	if (data->host_cookie & MSDC_ASYNC_FLAG)
692 		return;
693 
694 	if (data->host_cookie & MSDC_PREPARE_FLAG) {
695 		dma_unmap_sg(host->dev, data->sg, data->sg_len,
696 			     mmc_get_dma_dir(data));
697 		data->host_cookie &= ~MSDC_PREPARE_FLAG;
698 	}
699 }
700 
701 /* clock control primitives */
702 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
703 {
704 	u32 timeout, clk_ns;
705 	u32 mode = 0;
706 
707 	host->timeout_ns = ns;
708 	host->timeout_clks = clks;
709 	if (host->mmc->actual_clock == 0) {
710 		timeout = 0;
711 	} else {
712 		clk_ns  = 1000000000UL / host->mmc->actual_clock;
713 		timeout = (ns + clk_ns - 1) / clk_ns + clks;
714 		/* in 1048576 sclk cycle unit */
715 		timeout = (timeout + (0x1 << 20) - 1) >> 20;
716 		if (host->dev_comp->clk_div_bits == 8)
717 			sdr_get_field(host->base + MSDC_CFG,
718 				      MSDC_CFG_CKMOD, &mode);
719 		else
720 			sdr_get_field(host->base + MSDC_CFG,
721 				      MSDC_CFG_CKMOD_EXTRA, &mode);
722 		/*DDR mode will double the clk cycles for data timeout */
723 		timeout = mode >= 2 ? timeout * 2 : timeout;
724 		timeout = timeout > 1 ? timeout - 1 : 0;
725 		timeout = timeout > 255 ? 255 : timeout;
726 	}
727 	sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout);
728 }
729 
730 static void msdc_gate_clock(struct msdc_host *host)
731 {
732 	clk_disable_unprepare(host->src_clk_cg);
733 	clk_disable_unprepare(host->src_clk);
734 	clk_disable_unprepare(host->bus_clk);
735 	clk_disable_unprepare(host->h_clk);
736 }
737 
738 static void msdc_ungate_clock(struct msdc_host *host)
739 {
740 	clk_prepare_enable(host->h_clk);
741 	clk_prepare_enable(host->bus_clk);
742 	clk_prepare_enable(host->src_clk);
743 	clk_prepare_enable(host->src_clk_cg);
744 	while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
745 		cpu_relax();
746 }
747 
748 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
749 {
750 	u32 mode;
751 	u32 flags;
752 	u32 div;
753 	u32 sclk;
754 	u32 tune_reg = host->dev_comp->pad_tune_reg;
755 
756 	if (!hz) {
757 		dev_dbg(host->dev, "set mclk to 0\n");
758 		host->mclk = 0;
759 		host->mmc->actual_clock = 0;
760 		sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
761 		return;
762 	}
763 
764 	flags = readl(host->base + MSDC_INTEN);
765 	sdr_clr_bits(host->base + MSDC_INTEN, flags);
766 	if (host->dev_comp->clk_div_bits == 8)
767 		sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
768 	else
769 		sdr_clr_bits(host->base + MSDC_CFG,
770 			     MSDC_CFG_HS400_CK_MODE_EXTRA);
771 	if (timing == MMC_TIMING_UHS_DDR50 ||
772 	    timing == MMC_TIMING_MMC_DDR52 ||
773 	    timing == MMC_TIMING_MMC_HS400) {
774 		if (timing == MMC_TIMING_MMC_HS400)
775 			mode = 0x3;
776 		else
777 			mode = 0x2; /* ddr mode and use divisor */
778 
779 		if (hz >= (host->src_clk_freq >> 2)) {
780 			div = 0; /* mean div = 1/4 */
781 			sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
782 		} else {
783 			div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
784 			sclk = (host->src_clk_freq >> 2) / div;
785 			div = (div >> 1);
786 		}
787 
788 		if (timing == MMC_TIMING_MMC_HS400 &&
789 		    hz >= (host->src_clk_freq >> 1)) {
790 			if (host->dev_comp->clk_div_bits == 8)
791 				sdr_set_bits(host->base + MSDC_CFG,
792 					     MSDC_CFG_HS400_CK_MODE);
793 			else
794 				sdr_set_bits(host->base + MSDC_CFG,
795 					     MSDC_CFG_HS400_CK_MODE_EXTRA);
796 			sclk = host->src_clk_freq >> 1;
797 			div = 0; /* div is ignore when bit18 is set */
798 		}
799 	} else if (hz >= host->src_clk_freq) {
800 		mode = 0x1; /* no divisor */
801 		div = 0;
802 		sclk = host->src_clk_freq;
803 	} else {
804 		mode = 0x0; /* use divisor */
805 		if (hz >= (host->src_clk_freq >> 1)) {
806 			div = 0; /* mean div = 1/2 */
807 			sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
808 		} else {
809 			div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
810 			sclk = (host->src_clk_freq >> 2) / div;
811 		}
812 	}
813 	sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
814 	/*
815 	 * As src_clk/HCLK use the same bit to gate/ungate,
816 	 * So if want to only gate src_clk, need gate its parent(mux).
817 	 */
818 	if (host->src_clk_cg)
819 		clk_disable_unprepare(host->src_clk_cg);
820 	else
821 		clk_disable_unprepare(clk_get_parent(host->src_clk));
822 	if (host->dev_comp->clk_div_bits == 8)
823 		sdr_set_field(host->base + MSDC_CFG,
824 			      MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
825 			      (mode << 8) | div);
826 	else
827 		sdr_set_field(host->base + MSDC_CFG,
828 			      MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
829 			      (mode << 12) | div);
830 	if (host->src_clk_cg)
831 		clk_prepare_enable(host->src_clk_cg);
832 	else
833 		clk_prepare_enable(clk_get_parent(host->src_clk));
834 
835 	while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
836 		cpu_relax();
837 	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
838 	host->mmc->actual_clock = sclk;
839 	host->mclk = hz;
840 	host->timing = timing;
841 	/* need because clk changed. */
842 	msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
843 	sdr_set_bits(host->base + MSDC_INTEN, flags);
844 
845 	/*
846 	 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
847 	 * tune result of hs200/200Mhz is not suitable for 50Mhz
848 	 */
849 	if (host->mmc->actual_clock <= 52000000) {
850 		writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
851 		if (host->top_base) {
852 			writel(host->def_tune_para.emmc_top_control,
853 			       host->top_base + EMMC_TOP_CONTROL);
854 			writel(host->def_tune_para.emmc_top_cmd,
855 			       host->top_base + EMMC_TOP_CMD);
856 		} else {
857 			writel(host->def_tune_para.pad_tune,
858 			       host->base + tune_reg);
859 		}
860 	} else {
861 		writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
862 		writel(host->saved_tune_para.pad_cmd_tune,
863 		       host->base + PAD_CMD_TUNE);
864 		if (host->top_base) {
865 			writel(host->saved_tune_para.emmc_top_control,
866 			       host->top_base + EMMC_TOP_CONTROL);
867 			writel(host->saved_tune_para.emmc_top_cmd,
868 			       host->top_base + EMMC_TOP_CMD);
869 		} else {
870 			writel(host->saved_tune_para.pad_tune,
871 			       host->base + tune_reg);
872 		}
873 	}
874 
875 	if (timing == MMC_TIMING_MMC_HS400 &&
876 	    host->dev_comp->hs400_tune)
877 		sdr_set_field(host->base + tune_reg,
878 			      MSDC_PAD_TUNE_CMDRRDLY,
879 			      host->hs400_cmd_int_delay);
880 	dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->mmc->actual_clock,
881 		timing);
882 }
883 
884 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
885 		struct mmc_request *mrq, struct mmc_command *cmd)
886 {
887 	u32 resp;
888 
889 	switch (mmc_resp_type(cmd)) {
890 		/* Actually, R1, R5, R6, R7 are the same */
891 	case MMC_RSP_R1:
892 		resp = 0x1;
893 		break;
894 	case MMC_RSP_R1B:
895 		resp = 0x7;
896 		break;
897 	case MMC_RSP_R2:
898 		resp = 0x2;
899 		break;
900 	case MMC_RSP_R3:
901 		resp = 0x3;
902 		break;
903 	case MMC_RSP_NONE:
904 	default:
905 		resp = 0x0;
906 		break;
907 	}
908 
909 	return resp;
910 }
911 
912 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
913 		struct mmc_request *mrq, struct mmc_command *cmd)
914 {
915 	/* rawcmd :
916 	 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
917 	 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
918 	 */
919 	u32 opcode = cmd->opcode;
920 	u32 resp = msdc_cmd_find_resp(host, mrq, cmd);
921 	u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
922 
923 	host->cmd_rsp = resp;
924 
925 	if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
926 	    opcode == MMC_STOP_TRANSMISSION)
927 		rawcmd |= (0x1 << 14);
928 	else if (opcode == SD_SWITCH_VOLTAGE)
929 		rawcmd |= (0x1 << 30);
930 	else if (opcode == SD_APP_SEND_SCR ||
931 		 opcode == SD_APP_SEND_NUM_WR_BLKS ||
932 		 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
933 		 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
934 		 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
935 		rawcmd |= (0x1 << 11);
936 
937 	if (cmd->data) {
938 		struct mmc_data *data = cmd->data;
939 
940 		if (mmc_op_multi(opcode)) {
941 			if (mmc_card_mmc(host->mmc->card) && mrq->sbc &&
942 			    !(mrq->sbc->arg & 0xFFFF0000))
943 				rawcmd |= 0x2 << 28; /* AutoCMD23 */
944 		}
945 
946 		rawcmd |= ((data->blksz & 0xFFF) << 16);
947 		if (data->flags & MMC_DATA_WRITE)
948 			rawcmd |= (0x1 << 13);
949 		if (data->blocks > 1)
950 			rawcmd |= (0x2 << 11);
951 		else
952 			rawcmd |= (0x1 << 11);
953 		/* Always use dma mode */
954 		sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
955 
956 		if (host->timeout_ns != data->timeout_ns ||
957 		    host->timeout_clks != data->timeout_clks)
958 			msdc_set_timeout(host, data->timeout_ns,
959 					data->timeout_clks);
960 
961 		writel(data->blocks, host->base + SDC_BLK_NUM);
962 	}
963 	return rawcmd;
964 }
965 
966 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq,
967 			    struct mmc_command *cmd, struct mmc_data *data)
968 {
969 	bool read;
970 
971 	WARN_ON(host->data);
972 	host->data = data;
973 	read = data->flags & MMC_DATA_READ;
974 
975 	mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
976 	msdc_dma_setup(host, &host->dma, data);
977 	sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
978 	sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
979 	dev_dbg(host->dev, "DMA start\n");
980 	dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
981 			__func__, cmd->opcode, data->blocks, read);
982 }
983 
984 static int msdc_auto_cmd_done(struct msdc_host *host, int events,
985 		struct mmc_command *cmd)
986 {
987 	u32 *rsp = cmd->resp;
988 
989 	rsp[0] = readl(host->base + SDC_ACMD_RESP);
990 
991 	if (events & MSDC_INT_ACMDRDY) {
992 		cmd->error = 0;
993 	} else {
994 		msdc_reset_hw(host);
995 		if (events & MSDC_INT_ACMDCRCERR) {
996 			cmd->error = -EILSEQ;
997 			host->error |= REQ_STOP_EIO;
998 		} else if (events & MSDC_INT_ACMDTMO) {
999 			cmd->error = -ETIMEDOUT;
1000 			host->error |= REQ_STOP_TMO;
1001 		}
1002 		dev_err(host->dev,
1003 			"%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
1004 			__func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
1005 	}
1006 	return cmd->error;
1007 }
1008 
1009 static void msdc_track_cmd_data(struct msdc_host *host,
1010 				struct mmc_command *cmd, struct mmc_data *data)
1011 {
1012 	if (host->error)
1013 		dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
1014 			__func__, cmd->opcode, cmd->arg, host->error);
1015 }
1016 
1017 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
1018 {
1019 	unsigned long flags;
1020 	bool ret;
1021 
1022 	ret = cancel_delayed_work(&host->req_timeout);
1023 	if (!ret) {
1024 		/* delay work already running */
1025 		return;
1026 	}
1027 	spin_lock_irqsave(&host->lock, flags);
1028 	host->mrq = NULL;
1029 	spin_unlock_irqrestore(&host->lock, flags);
1030 
1031 	msdc_track_cmd_data(host, mrq->cmd, mrq->data);
1032 	if (mrq->data)
1033 		msdc_unprepare_data(host, mrq);
1034 	mmc_request_done(host->mmc, mrq);
1035 }
1036 
1037 /* returns true if command is fully handled; returns false otherwise */
1038 static bool msdc_cmd_done(struct msdc_host *host, int events,
1039 			  struct mmc_request *mrq, struct mmc_command *cmd)
1040 {
1041 	bool done = false;
1042 	bool sbc_error;
1043 	unsigned long flags;
1044 	u32 *rsp = cmd->resp;
1045 
1046 	if (mrq->sbc && cmd == mrq->cmd &&
1047 	    (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
1048 				   | MSDC_INT_ACMDTMO)))
1049 		msdc_auto_cmd_done(host, events, mrq->sbc);
1050 
1051 	sbc_error = mrq->sbc && mrq->sbc->error;
1052 
1053 	if (!sbc_error && !(events & (MSDC_INT_CMDRDY
1054 					| MSDC_INT_RSPCRCERR
1055 					| MSDC_INT_CMDTMO)))
1056 		return done;
1057 
1058 	spin_lock_irqsave(&host->lock, flags);
1059 	done = !host->cmd;
1060 	host->cmd = NULL;
1061 	spin_unlock_irqrestore(&host->lock, flags);
1062 
1063 	if (done)
1064 		return true;
1065 
1066 	sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1067 
1068 	if (cmd->flags & MMC_RSP_PRESENT) {
1069 		if (cmd->flags & MMC_RSP_136) {
1070 			rsp[0] = readl(host->base + SDC_RESP3);
1071 			rsp[1] = readl(host->base + SDC_RESP2);
1072 			rsp[2] = readl(host->base + SDC_RESP1);
1073 			rsp[3] = readl(host->base + SDC_RESP0);
1074 		} else {
1075 			rsp[0] = readl(host->base + SDC_RESP0);
1076 		}
1077 	}
1078 
1079 	if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
1080 		if (cmd->opcode != MMC_SEND_TUNING_BLOCK &&
1081 		    cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)
1082 			/*
1083 			 * should not clear fifo/interrupt as the tune data
1084 			 * may have alreay come.
1085 			 */
1086 			msdc_reset_hw(host);
1087 		if (events & MSDC_INT_RSPCRCERR) {
1088 			cmd->error = -EILSEQ;
1089 			host->error |= REQ_CMD_EIO;
1090 		} else if (events & MSDC_INT_CMDTMO) {
1091 			cmd->error = -ETIMEDOUT;
1092 			host->error |= REQ_CMD_TMO;
1093 		}
1094 	}
1095 	if (cmd->error)
1096 		dev_dbg(host->dev,
1097 				"%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
1098 				__func__, cmd->opcode, cmd->arg, rsp[0],
1099 				cmd->error);
1100 
1101 	msdc_cmd_next(host, mrq, cmd);
1102 	return true;
1103 }
1104 
1105 /* It is the core layer's responsibility to ensure card status
1106  * is correct before issue a request. but host design do below
1107  * checks recommended.
1108  */
1109 static inline bool msdc_cmd_is_ready(struct msdc_host *host,
1110 		struct mmc_request *mrq, struct mmc_command *cmd)
1111 {
1112 	/* The max busy time we can endure is 20ms */
1113 	unsigned long tmo = jiffies + msecs_to_jiffies(20);
1114 
1115 	while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) &&
1116 			time_before(jiffies, tmo))
1117 		cpu_relax();
1118 	if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) {
1119 		dev_err(host->dev, "CMD bus busy detected\n");
1120 		host->error |= REQ_CMD_BUSY;
1121 		msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1122 		return false;
1123 	}
1124 
1125 	if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
1126 		tmo = jiffies + msecs_to_jiffies(20);
1127 		/* R1B or with data, should check SDCBUSY */
1128 		while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) &&
1129 				time_before(jiffies, tmo))
1130 			cpu_relax();
1131 		if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) {
1132 			dev_err(host->dev, "Controller busy detected\n");
1133 			host->error |= REQ_CMD_BUSY;
1134 			msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1135 			return false;
1136 		}
1137 	}
1138 	return true;
1139 }
1140 
1141 static void msdc_start_command(struct msdc_host *host,
1142 		struct mmc_request *mrq, struct mmc_command *cmd)
1143 {
1144 	u32 rawcmd;
1145 	unsigned long flags;
1146 
1147 	WARN_ON(host->cmd);
1148 	host->cmd = cmd;
1149 
1150 	mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1151 	if (!msdc_cmd_is_ready(host, mrq, cmd))
1152 		return;
1153 
1154 	if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
1155 	    readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
1156 		dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
1157 		msdc_reset_hw(host);
1158 	}
1159 
1160 	cmd->error = 0;
1161 	rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
1162 
1163 	spin_lock_irqsave(&host->lock, flags);
1164 	sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1165 	spin_unlock_irqrestore(&host->lock, flags);
1166 
1167 	writel(cmd->arg, host->base + SDC_ARG);
1168 	writel(rawcmd, host->base + SDC_CMD);
1169 }
1170 
1171 static void msdc_cmd_next(struct msdc_host *host,
1172 		struct mmc_request *mrq, struct mmc_command *cmd)
1173 {
1174 	if ((cmd->error &&
1175 	    !(cmd->error == -EILSEQ &&
1176 	      (cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1177 	       cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) ||
1178 	    (mrq->sbc && mrq->sbc->error))
1179 		msdc_request_done(host, mrq);
1180 	else if (cmd == mrq->sbc)
1181 		msdc_start_command(host, mrq, mrq->cmd);
1182 	else if (!cmd->data)
1183 		msdc_request_done(host, mrq);
1184 	else
1185 		msdc_start_data(host, mrq, cmd, cmd->data);
1186 }
1187 
1188 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
1189 {
1190 	struct msdc_host *host = mmc_priv(mmc);
1191 
1192 	host->error = 0;
1193 	WARN_ON(host->mrq);
1194 	host->mrq = mrq;
1195 
1196 	if (mrq->data)
1197 		msdc_prepare_data(host, mrq);
1198 
1199 	/* if SBC is required, we have HW option and SW option.
1200 	 * if HW option is enabled, and SBC does not have "special" flags,
1201 	 * use HW option,  otherwise use SW option
1202 	 */
1203 	if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
1204 	    (mrq->sbc->arg & 0xFFFF0000)))
1205 		msdc_start_command(host, mrq, mrq->sbc);
1206 	else
1207 		msdc_start_command(host, mrq, mrq->cmd);
1208 }
1209 
1210 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1211 {
1212 	struct msdc_host *host = mmc_priv(mmc);
1213 	struct mmc_data *data = mrq->data;
1214 
1215 	if (!data)
1216 		return;
1217 
1218 	msdc_prepare_data(host, mrq);
1219 	data->host_cookie |= MSDC_ASYNC_FLAG;
1220 }
1221 
1222 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1223 		int err)
1224 {
1225 	struct msdc_host *host = mmc_priv(mmc);
1226 	struct mmc_data *data;
1227 
1228 	data = mrq->data;
1229 	if (!data)
1230 		return;
1231 	if (data->host_cookie) {
1232 		data->host_cookie &= ~MSDC_ASYNC_FLAG;
1233 		msdc_unprepare_data(host, mrq);
1234 	}
1235 }
1236 
1237 static void msdc_data_xfer_next(struct msdc_host *host,
1238 				struct mmc_request *mrq, struct mmc_data *data)
1239 {
1240 	if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
1241 	    !mrq->sbc)
1242 		msdc_start_command(host, mrq, mrq->stop);
1243 	else
1244 		msdc_request_done(host, mrq);
1245 }
1246 
1247 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events,
1248 				struct mmc_request *mrq, struct mmc_data *data)
1249 {
1250 	struct mmc_command *stop = data->stop;
1251 	unsigned long flags;
1252 	bool done;
1253 	unsigned int check_data = events &
1254 	    (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
1255 	     | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
1256 	     | MSDC_INT_DMA_PROTECT);
1257 
1258 	spin_lock_irqsave(&host->lock, flags);
1259 	done = !host->data;
1260 	if (check_data)
1261 		host->data = NULL;
1262 	spin_unlock_irqrestore(&host->lock, flags);
1263 
1264 	if (done)
1265 		return true;
1266 
1267 	if (check_data || (stop && stop->error)) {
1268 		dev_dbg(host->dev, "DMA status: 0x%8X\n",
1269 				readl(host->base + MSDC_DMA_CFG));
1270 		sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
1271 				1);
1272 		while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS)
1273 			cpu_relax();
1274 		sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
1275 		dev_dbg(host->dev, "DMA stop\n");
1276 
1277 		if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
1278 			data->bytes_xfered = data->blocks * data->blksz;
1279 		} else {
1280 			dev_dbg(host->dev, "interrupt events: %x\n", events);
1281 			msdc_reset_hw(host);
1282 			host->error |= REQ_DAT_ERR;
1283 			data->bytes_xfered = 0;
1284 
1285 			if (events & MSDC_INT_DATTMO)
1286 				data->error = -ETIMEDOUT;
1287 			else if (events & MSDC_INT_DATCRCERR)
1288 				data->error = -EILSEQ;
1289 
1290 			dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
1291 				__func__, mrq->cmd->opcode, data->blocks);
1292 			dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
1293 				(int)data->error, data->bytes_xfered);
1294 		}
1295 
1296 		msdc_data_xfer_next(host, mrq, data);
1297 		done = true;
1298 	}
1299 	return done;
1300 }
1301 
1302 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1303 {
1304 	u32 val = readl(host->base + SDC_CFG);
1305 
1306 	val &= ~SDC_CFG_BUSWIDTH;
1307 
1308 	switch (width) {
1309 	default:
1310 	case MMC_BUS_WIDTH_1:
1311 		val |= (MSDC_BUS_1BITS << 16);
1312 		break;
1313 	case MMC_BUS_WIDTH_4:
1314 		val |= (MSDC_BUS_4BITS << 16);
1315 		break;
1316 	case MMC_BUS_WIDTH_8:
1317 		val |= (MSDC_BUS_8BITS << 16);
1318 		break;
1319 	}
1320 
1321 	writel(val, host->base + SDC_CFG);
1322 	dev_dbg(host->dev, "Bus Width = %d", width);
1323 }
1324 
1325 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
1326 {
1327 	struct msdc_host *host = mmc_priv(mmc);
1328 	int ret = 0;
1329 
1330 	if (!IS_ERR(mmc->supply.vqmmc)) {
1331 		if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 &&
1332 		    ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) {
1333 			dev_err(host->dev, "Unsupported signal voltage!\n");
1334 			return -EINVAL;
1335 		}
1336 
1337 		ret = mmc_regulator_set_vqmmc(mmc, ios);
1338 		if (ret) {
1339 			dev_dbg(host->dev, "Regulator set error %d (%d)\n",
1340 				ret, ios->signal_voltage);
1341 		} else {
1342 			/* Apply different pinctrl settings for different signal voltage */
1343 			if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1344 				pinctrl_select_state(host->pinctrl, host->pins_uhs);
1345 			else
1346 				pinctrl_select_state(host->pinctrl, host->pins_default);
1347 		}
1348 	}
1349 	return ret;
1350 }
1351 
1352 static int msdc_card_busy(struct mmc_host *mmc)
1353 {
1354 	struct msdc_host *host = mmc_priv(mmc);
1355 	u32 status = readl(host->base + MSDC_PS);
1356 
1357 	/* only check if data0 is low */
1358 	return !(status & BIT(16));
1359 }
1360 
1361 static void msdc_request_timeout(struct work_struct *work)
1362 {
1363 	struct msdc_host *host = container_of(work, struct msdc_host,
1364 			req_timeout.work);
1365 
1366 	/* simulate HW timeout status */
1367 	dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1368 	if (host->mrq) {
1369 		dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1370 				host->mrq, host->mrq->cmd->opcode);
1371 		if (host->cmd) {
1372 			dev_err(host->dev, "%s: aborting cmd=%d\n",
1373 					__func__, host->cmd->opcode);
1374 			msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1375 					host->cmd);
1376 		} else if (host->data) {
1377 			dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1378 					__func__, host->mrq->cmd->opcode,
1379 					host->data->blocks);
1380 			msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1381 					host->data);
1382 		}
1383 	}
1384 }
1385 
1386 static void __msdc_enable_sdio_irq(struct mmc_host *mmc, int enb)
1387 {
1388 	unsigned long flags;
1389 	struct msdc_host *host = mmc_priv(mmc);
1390 
1391 	spin_lock_irqsave(&host->lock, flags);
1392 	if (enb)
1393 		sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1394 	else
1395 		sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1396 	spin_unlock_irqrestore(&host->lock, flags);
1397 }
1398 
1399 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb)
1400 {
1401 	struct msdc_host *host = mmc_priv(mmc);
1402 
1403 	__msdc_enable_sdio_irq(mmc, enb);
1404 
1405 	if (enb)
1406 		pm_runtime_get_noresume(host->dev);
1407 	else
1408 		pm_runtime_put_noidle(host->dev);
1409 }
1410 
1411 static irqreturn_t msdc_irq(int irq, void *dev_id)
1412 {
1413 	struct msdc_host *host = (struct msdc_host *) dev_id;
1414 
1415 	while (true) {
1416 		unsigned long flags;
1417 		struct mmc_request *mrq;
1418 		struct mmc_command *cmd;
1419 		struct mmc_data *data;
1420 		u32 events, event_mask;
1421 
1422 		spin_lock_irqsave(&host->lock, flags);
1423 		events = readl(host->base + MSDC_INT);
1424 		event_mask = readl(host->base + MSDC_INTEN);
1425 		/* clear interrupts */
1426 		writel(events & event_mask, host->base + MSDC_INT);
1427 
1428 		mrq = host->mrq;
1429 		cmd = host->cmd;
1430 		data = host->data;
1431 		spin_unlock_irqrestore(&host->lock, flags);
1432 
1433 		if ((events & event_mask) & MSDC_INT_SDIOIRQ) {
1434 			__msdc_enable_sdio_irq(host->mmc, 0);
1435 			sdio_signal_irq(host->mmc);
1436 		}
1437 
1438 		if ((events & event_mask) & MSDC_INT_CDSC) {
1439 			if (host->internal_cd)
1440 				mmc_detect_change(host->mmc, msecs_to_jiffies(20));
1441 			events &= ~MSDC_INT_CDSC;
1442 		}
1443 
1444 		if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ)))
1445 			break;
1446 
1447 		if (!mrq) {
1448 			dev_err(host->dev,
1449 				"%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1450 				__func__, events, event_mask);
1451 			WARN_ON(1);
1452 			break;
1453 		}
1454 
1455 		dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1456 
1457 		if (cmd)
1458 			msdc_cmd_done(host, events, mrq, cmd);
1459 		else if (data)
1460 			msdc_data_xfer_done(host, events, mrq, data);
1461 	}
1462 
1463 	return IRQ_HANDLED;
1464 }
1465 
1466 static void msdc_init_hw(struct msdc_host *host)
1467 {
1468 	u32 val;
1469 	u32 tune_reg = host->dev_comp->pad_tune_reg;
1470 
1471 	/* Configure to MMC/SD mode, clock free running */
1472 	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1473 
1474 	/* Reset */
1475 	msdc_reset_hw(host);
1476 
1477 	/* Disable and clear all interrupts */
1478 	writel(0, host->base + MSDC_INTEN);
1479 	val = readl(host->base + MSDC_INT);
1480 	writel(val, host->base + MSDC_INT);
1481 
1482 	/* Configure card detection */
1483 	if (host->internal_cd) {
1484 		sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE,
1485 			      DEFAULT_DEBOUNCE);
1486 		sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1487 		sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1488 		sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1489 	} else {
1490 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1491 		sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1492 		sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1493 	}
1494 
1495 	if (host->top_base) {
1496 		writel(0, host->top_base + EMMC_TOP_CONTROL);
1497 		writel(0, host->top_base + EMMC_TOP_CMD);
1498 	} else {
1499 		writel(0, host->base + tune_reg);
1500 	}
1501 	writel(0, host->base + MSDC_IOCON);
1502 	sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1503 	writel(0x403c0046, host->base + MSDC_PATCH_BIT);
1504 	sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1505 	writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
1506 	sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1507 
1508 	if (host->dev_comp->stop_clk_fix) {
1509 		sdr_set_field(host->base + MSDC_PATCH_BIT1,
1510 			      MSDC_PATCH_BIT1_STOP_DLY, 3);
1511 		sdr_clr_bits(host->base + SDC_FIFO_CFG,
1512 			     SDC_FIFO_CFG_WRVALIDSEL);
1513 		sdr_clr_bits(host->base + SDC_FIFO_CFG,
1514 			     SDC_FIFO_CFG_RDVALIDSEL);
1515 	}
1516 
1517 	if (host->dev_comp->busy_check)
1518 		sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7));
1519 
1520 	if (host->dev_comp->async_fifo) {
1521 		sdr_set_field(host->base + MSDC_PATCH_BIT2,
1522 			      MSDC_PB2_RESPWAIT, 3);
1523 		if (host->dev_comp->enhance_rx) {
1524 			if (host->top_base)
1525 				sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1526 					     SDC_RX_ENH_EN);
1527 			else
1528 				sdr_set_bits(host->base + SDC_ADV_CFG0,
1529 					     SDC_RX_ENHANCE_EN);
1530 		} else {
1531 			sdr_set_field(host->base + MSDC_PATCH_BIT2,
1532 				      MSDC_PB2_RESPSTSENSEL, 2);
1533 			sdr_set_field(host->base + MSDC_PATCH_BIT2,
1534 				      MSDC_PB2_CRCSTSENSEL, 2);
1535 		}
1536 		/* use async fifo, then no need tune internal delay */
1537 		sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
1538 			     MSDC_PATCH_BIT2_CFGRESP);
1539 		sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1540 			     MSDC_PATCH_BIT2_CFGCRCSTS);
1541 	}
1542 
1543 	if (host->dev_comp->support_64g)
1544 		sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1545 			     MSDC_PB2_SUPPORT_64G);
1546 	if (host->dev_comp->data_tune) {
1547 		if (host->top_base) {
1548 			sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1549 				     PAD_DAT_RD_RXDLY_SEL);
1550 			sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL,
1551 				     DATA_K_VALUE_SEL);
1552 			sdr_set_bits(host->top_base + EMMC_TOP_CMD,
1553 				     PAD_CMD_RD_RXDLY_SEL);
1554 		} else {
1555 			sdr_set_bits(host->base + tune_reg,
1556 				     MSDC_PAD_TUNE_RD_SEL |
1557 				     MSDC_PAD_TUNE_CMD_SEL);
1558 		}
1559 	} else {
1560 		/* choose clock tune */
1561 		if (host->top_base)
1562 			sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1563 				     PAD_RXDLY_SEL);
1564 		else
1565 			sdr_set_bits(host->base + tune_reg,
1566 				     MSDC_PAD_TUNE_RXDLYSEL);
1567 	}
1568 
1569 	/* Configure to enable SDIO mode.
1570 	 * it's must otherwise sdio cmd5 failed
1571 	 */
1572 	sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1573 
1574 	/* Config SDIO device detect interrupt function */
1575 	if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
1576 		sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1577 	else
1578 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1579 
1580 	/* Configure to default data timeout */
1581 	sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1582 
1583 	host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
1584 	host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1585 	if (host->top_base) {
1586 		host->def_tune_para.emmc_top_control =
1587 			readl(host->top_base + EMMC_TOP_CONTROL);
1588 		host->def_tune_para.emmc_top_cmd =
1589 			readl(host->top_base + EMMC_TOP_CMD);
1590 		host->saved_tune_para.emmc_top_control =
1591 			readl(host->top_base + EMMC_TOP_CONTROL);
1592 		host->saved_tune_para.emmc_top_cmd =
1593 			readl(host->top_base + EMMC_TOP_CMD);
1594 	} else {
1595 		host->def_tune_para.pad_tune = readl(host->base + tune_reg);
1596 		host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
1597 	}
1598 	dev_dbg(host->dev, "init hardware done!");
1599 }
1600 
1601 static void msdc_deinit_hw(struct msdc_host *host)
1602 {
1603 	u32 val;
1604 
1605 	if (host->internal_cd) {
1606 		/* Disabled card-detect */
1607 		sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1608 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1609 	}
1610 
1611 	/* Disable and clear all interrupts */
1612 	writel(0, host->base + MSDC_INTEN);
1613 
1614 	val = readl(host->base + MSDC_INT);
1615 	writel(val, host->base + MSDC_INT);
1616 }
1617 
1618 /* init gpd and bd list in msdc_drv_probe */
1619 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1620 {
1621 	struct mt_gpdma_desc *gpd = dma->gpd;
1622 	struct mt_bdma_desc *bd = dma->bd;
1623 	dma_addr_t dma_addr;
1624 	int i;
1625 
1626 	memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
1627 
1628 	dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc);
1629 	gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
1630 	/* gpd->next is must set for desc DMA
1631 	 * That's why must alloc 2 gpd structure.
1632 	 */
1633 	gpd->next = lower_32_bits(dma_addr);
1634 	if (host->dev_comp->support_64g)
1635 		gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1636 
1637 	dma_addr = dma->bd_addr;
1638 	gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */
1639 	if (host->dev_comp->support_64g)
1640 		gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28;
1641 
1642 	memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
1643 	for (i = 0; i < (MAX_BD_NUM - 1); i++) {
1644 		dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1);
1645 		bd[i].next = lower_32_bits(dma_addr);
1646 		if (host->dev_comp->support_64g)
1647 			bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1648 	}
1649 }
1650 
1651 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1652 {
1653 	struct msdc_host *host = mmc_priv(mmc);
1654 	int ret;
1655 
1656 	msdc_set_buswidth(host, ios->bus_width);
1657 
1658 	/* Suspend/Resume will do power off/on */
1659 	switch (ios->power_mode) {
1660 	case MMC_POWER_UP:
1661 		if (!IS_ERR(mmc->supply.vmmc)) {
1662 			msdc_init_hw(host);
1663 			ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1664 					ios->vdd);
1665 			if (ret) {
1666 				dev_err(host->dev, "Failed to set vmmc power!\n");
1667 				return;
1668 			}
1669 		}
1670 		break;
1671 	case MMC_POWER_ON:
1672 		if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1673 			ret = regulator_enable(mmc->supply.vqmmc);
1674 			if (ret)
1675 				dev_err(host->dev, "Failed to set vqmmc power!\n");
1676 			else
1677 				host->vqmmc_enabled = true;
1678 		}
1679 		break;
1680 	case MMC_POWER_OFF:
1681 		if (!IS_ERR(mmc->supply.vmmc))
1682 			mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1683 
1684 		if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1685 			regulator_disable(mmc->supply.vqmmc);
1686 			host->vqmmc_enabled = false;
1687 		}
1688 		break;
1689 	default:
1690 		break;
1691 	}
1692 
1693 	if (host->mclk != ios->clock || host->timing != ios->timing)
1694 		msdc_set_mclk(host, ios->timing, ios->clock);
1695 }
1696 
1697 static u32 test_delay_bit(u32 delay, u32 bit)
1698 {
1699 	bit %= PAD_DELAY_MAX;
1700 	return delay & (1 << bit);
1701 }
1702 
1703 static int get_delay_len(u32 delay, u32 start_bit)
1704 {
1705 	int i;
1706 
1707 	for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
1708 		if (test_delay_bit(delay, start_bit + i) == 0)
1709 			return i;
1710 	}
1711 	return PAD_DELAY_MAX - start_bit;
1712 }
1713 
1714 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
1715 {
1716 	int start = 0, len = 0;
1717 	int start_final = 0, len_final = 0;
1718 	u8 final_phase = 0xff;
1719 	struct msdc_delay_phase delay_phase = { 0, };
1720 
1721 	if (delay == 0) {
1722 		dev_err(host->dev, "phase error: [map:%x]\n", delay);
1723 		delay_phase.final_phase = final_phase;
1724 		return delay_phase;
1725 	}
1726 
1727 	while (start < PAD_DELAY_MAX) {
1728 		len = get_delay_len(delay, start);
1729 		if (len_final < len) {
1730 			start_final = start;
1731 			len_final = len;
1732 		}
1733 		start += len ? len : 1;
1734 		if (len >= 12 && start_final < 4)
1735 			break;
1736 	}
1737 
1738 	/* The rule is that to find the smallest delay cell */
1739 	if (start_final == 0)
1740 		final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
1741 	else
1742 		final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
1743 	dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
1744 		 delay, len_final, final_phase);
1745 
1746 	delay_phase.maxlen = len_final;
1747 	delay_phase.start = start_final;
1748 	delay_phase.final_phase = final_phase;
1749 	return delay_phase;
1750 }
1751 
1752 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
1753 {
1754 	u32 tune_reg = host->dev_comp->pad_tune_reg;
1755 
1756 	if (host->top_base)
1757 		sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
1758 			      value);
1759 	else
1760 		sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
1761 			      value);
1762 }
1763 
1764 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
1765 {
1766 	u32 tune_reg = host->dev_comp->pad_tune_reg;
1767 
1768 	if (host->top_base)
1769 		sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
1770 			      PAD_DAT_RD_RXDLY, value);
1771 	else
1772 		sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,
1773 			      value);
1774 }
1775 
1776 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
1777 {
1778 	struct msdc_host *host = mmc_priv(mmc);
1779 	u32 rise_delay = 0, fall_delay = 0;
1780 	struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
1781 	struct msdc_delay_phase internal_delay_phase;
1782 	u8 final_delay, final_maxlen;
1783 	u32 internal_delay = 0;
1784 	u32 tune_reg = host->dev_comp->pad_tune_reg;
1785 	int cmd_err;
1786 	int i, j;
1787 
1788 	if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
1789 	    mmc->ios.timing == MMC_TIMING_UHS_SDR104)
1790 		sdr_set_field(host->base + tune_reg,
1791 			      MSDC_PAD_TUNE_CMDRRDLY,
1792 			      host->hs200_cmd_int_delay);
1793 
1794 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1795 	for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1796 		msdc_set_cmd_delay(host, i);
1797 		/*
1798 		 * Using the same parameters, it may sometimes pass the test,
1799 		 * but sometimes it may fail. To make sure the parameters are
1800 		 * more stable, we test each set of parameters 3 times.
1801 		 */
1802 		for (j = 0; j < 3; j++) {
1803 			mmc_send_tuning(mmc, opcode, &cmd_err);
1804 			if (!cmd_err) {
1805 				rise_delay |= (1 << i);
1806 			} else {
1807 				rise_delay &= ~(1 << i);
1808 				break;
1809 			}
1810 		}
1811 	}
1812 	final_rise_delay = get_best_delay(host, rise_delay);
1813 	/* if rising edge has enough margin, then do not scan falling edge */
1814 	if (final_rise_delay.maxlen >= 12 ||
1815 	    (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1816 		goto skip_fall;
1817 
1818 	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1819 	for (i = 0; i < PAD_DELAY_MAX; i++) {
1820 		msdc_set_cmd_delay(host, i);
1821 		/*
1822 		 * Using the same parameters, it may sometimes pass the test,
1823 		 * but sometimes it may fail. To make sure the parameters are
1824 		 * more stable, we test each set of parameters 3 times.
1825 		 */
1826 		for (j = 0; j < 3; j++) {
1827 			mmc_send_tuning(mmc, opcode, &cmd_err);
1828 			if (!cmd_err) {
1829 				fall_delay |= (1 << i);
1830 			} else {
1831 				fall_delay &= ~(1 << i);
1832 				break;
1833 			}
1834 		}
1835 	}
1836 	final_fall_delay = get_best_delay(host, fall_delay);
1837 
1838 skip_fall:
1839 	final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1840 	if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4)
1841 		final_maxlen = final_fall_delay.maxlen;
1842 	if (final_maxlen == final_rise_delay.maxlen) {
1843 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1844 		final_delay = final_rise_delay.final_phase;
1845 	} else {
1846 		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1847 		final_delay = final_fall_delay.final_phase;
1848 	}
1849 	msdc_set_cmd_delay(host, final_delay);
1850 
1851 	if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
1852 		goto skip_internal;
1853 
1854 	for (i = 0; i < PAD_DELAY_MAX; i++) {
1855 		sdr_set_field(host->base + tune_reg,
1856 			      MSDC_PAD_TUNE_CMDRRDLY, i);
1857 		mmc_send_tuning(mmc, opcode, &cmd_err);
1858 		if (!cmd_err)
1859 			internal_delay |= (1 << i);
1860 	}
1861 	dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
1862 	internal_delay_phase = get_best_delay(host, internal_delay);
1863 	sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
1864 		      internal_delay_phase.final_phase);
1865 skip_internal:
1866 	dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
1867 	return final_delay == 0xff ? -EIO : 0;
1868 }
1869 
1870 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)
1871 {
1872 	struct msdc_host *host = mmc_priv(mmc);
1873 	u32 cmd_delay = 0;
1874 	struct msdc_delay_phase final_cmd_delay = { 0,};
1875 	u8 final_delay;
1876 	int cmd_err;
1877 	int i, j;
1878 
1879 	/* select EMMC50 PAD CMD tune */
1880 	sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
1881 
1882 	if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
1883 	    mmc->ios.timing == MMC_TIMING_UHS_SDR104)
1884 		sdr_set_field(host->base + MSDC_PAD_TUNE,
1885 			      MSDC_PAD_TUNE_CMDRRDLY,
1886 			      host->hs200_cmd_int_delay);
1887 
1888 	if (host->hs400_cmd_resp_sel_rising)
1889 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1890 	else
1891 		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1892 	for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1893 		sdr_set_field(host->base + PAD_CMD_TUNE,
1894 			      PAD_CMD_TUNE_RX_DLY3, i);
1895 		/*
1896 		 * Using the same parameters, it may sometimes pass the test,
1897 		 * but sometimes it may fail. To make sure the parameters are
1898 		 * more stable, we test each set of parameters 3 times.
1899 		 */
1900 		for (j = 0; j < 3; j++) {
1901 			mmc_send_tuning(mmc, opcode, &cmd_err);
1902 			if (!cmd_err) {
1903 				cmd_delay |= (1 << i);
1904 			} else {
1905 				cmd_delay &= ~(1 << i);
1906 				break;
1907 			}
1908 		}
1909 	}
1910 	final_cmd_delay = get_best_delay(host, cmd_delay);
1911 	sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
1912 		      final_cmd_delay.final_phase);
1913 	final_delay = final_cmd_delay.final_phase;
1914 
1915 	dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
1916 	return final_delay == 0xff ? -EIO : 0;
1917 }
1918 
1919 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
1920 {
1921 	struct msdc_host *host = mmc_priv(mmc);
1922 	u32 rise_delay = 0, fall_delay = 0;
1923 	struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
1924 	u8 final_delay, final_maxlen;
1925 	int i, ret;
1926 
1927 	sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
1928 		      host->latch_ck);
1929 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1930 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1931 	for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1932 		msdc_set_data_delay(host, i);
1933 		ret = mmc_send_tuning(mmc, opcode, NULL);
1934 		if (!ret)
1935 			rise_delay |= (1 << i);
1936 	}
1937 	final_rise_delay = get_best_delay(host, rise_delay);
1938 	/* if rising edge has enough margin, then do not scan falling edge */
1939 	if (final_rise_delay.maxlen >= 12 ||
1940 	    (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1941 		goto skip_fall;
1942 
1943 	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1944 	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1945 	for (i = 0; i < PAD_DELAY_MAX; i++) {
1946 		msdc_set_data_delay(host, i);
1947 		ret = mmc_send_tuning(mmc, opcode, NULL);
1948 		if (!ret)
1949 			fall_delay |= (1 << i);
1950 	}
1951 	final_fall_delay = get_best_delay(host, fall_delay);
1952 
1953 skip_fall:
1954 	final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
1955 	if (final_maxlen == final_rise_delay.maxlen) {
1956 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1957 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1958 		final_delay = final_rise_delay.final_phase;
1959 	} else {
1960 		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
1961 		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
1962 		final_delay = final_fall_delay.final_phase;
1963 	}
1964 	msdc_set_data_delay(host, final_delay);
1965 
1966 	dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
1967 	return final_delay == 0xff ? -EIO : 0;
1968 }
1969 
1970 /*
1971  * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
1972  * together, which can save the tuning time.
1973  */
1974 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
1975 {
1976 	struct msdc_host *host = mmc_priv(mmc);
1977 	u32 rise_delay = 0, fall_delay = 0;
1978 	struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
1979 	u8 final_delay, final_maxlen;
1980 	int i, ret;
1981 
1982 	sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
1983 		      host->latch_ck);
1984 
1985 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1986 	sdr_clr_bits(host->base + MSDC_IOCON,
1987 		     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
1988 	for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1989 		msdc_set_cmd_delay(host, i);
1990 		msdc_set_data_delay(host, i);
1991 		ret = mmc_send_tuning(mmc, opcode, NULL);
1992 		if (!ret)
1993 			rise_delay |= (1 << i);
1994 	}
1995 	final_rise_delay = get_best_delay(host, rise_delay);
1996 	/* if rising edge has enough margin, then do not scan falling edge */
1997 	if (final_rise_delay.maxlen >= 12 ||
1998 	    (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1999 		goto skip_fall;
2000 
2001 	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2002 	sdr_set_bits(host->base + MSDC_IOCON,
2003 		     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2004 	for (i = 0; i < PAD_DELAY_MAX; i++) {
2005 		msdc_set_cmd_delay(host, i);
2006 		msdc_set_data_delay(host, i);
2007 		ret = mmc_send_tuning(mmc, opcode, NULL);
2008 		if (!ret)
2009 			fall_delay |= (1 << i);
2010 	}
2011 	final_fall_delay = get_best_delay(host, fall_delay);
2012 
2013 skip_fall:
2014 	final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2015 	if (final_maxlen == final_rise_delay.maxlen) {
2016 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2017 		sdr_clr_bits(host->base + MSDC_IOCON,
2018 			     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2019 		final_delay = final_rise_delay.final_phase;
2020 	} else {
2021 		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2022 		sdr_set_bits(host->base + MSDC_IOCON,
2023 			     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2024 		final_delay = final_fall_delay.final_phase;
2025 	}
2026 
2027 	msdc_set_cmd_delay(host, final_delay);
2028 	msdc_set_data_delay(host, final_delay);
2029 
2030 	dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
2031 	return final_delay == 0xff ? -EIO : 0;
2032 }
2033 
2034 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
2035 {
2036 	struct msdc_host *host = mmc_priv(mmc);
2037 	int ret;
2038 	u32 tune_reg = host->dev_comp->pad_tune_reg;
2039 
2040 	if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
2041 		ret = msdc_tune_together(mmc, opcode);
2042 		if (host->hs400_mode) {
2043 			sdr_clr_bits(host->base + MSDC_IOCON,
2044 				     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2045 			msdc_set_data_delay(host, 0);
2046 		}
2047 		goto tune_done;
2048 	}
2049 	if (host->hs400_mode &&
2050 	    host->dev_comp->hs400_tune)
2051 		ret = hs400_tune_response(mmc, opcode);
2052 	else
2053 		ret = msdc_tune_response(mmc, opcode);
2054 	if (ret == -EIO) {
2055 		dev_err(host->dev, "Tune response fail!\n");
2056 		return ret;
2057 	}
2058 	if (host->hs400_mode == false) {
2059 		ret = msdc_tune_data(mmc, opcode);
2060 		if (ret == -EIO)
2061 			dev_err(host->dev, "Tune data fail!\n");
2062 	}
2063 
2064 tune_done:
2065 	host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
2066 	host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
2067 	host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2068 	if (host->top_base) {
2069 		host->saved_tune_para.emmc_top_control = readl(host->top_base +
2070 				EMMC_TOP_CONTROL);
2071 		host->saved_tune_para.emmc_top_cmd = readl(host->top_base +
2072 				EMMC_TOP_CMD);
2073 	}
2074 	return ret;
2075 }
2076 
2077 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2078 {
2079 	struct msdc_host *host = mmc_priv(mmc);
2080 	host->hs400_mode = true;
2081 
2082 	if (host->top_base)
2083 		writel(host->hs400_ds_delay,
2084 		       host->top_base + EMMC50_PAD_DS_TUNE);
2085 	else
2086 		writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
2087 	/* hs400 mode must set it to 0 */
2088 	sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
2089 	/* to improve read performance, set outstanding to 2 */
2090 	sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
2091 
2092 	return 0;
2093 }
2094 
2095 static void msdc_hw_reset(struct mmc_host *mmc)
2096 {
2097 	struct msdc_host *host = mmc_priv(mmc);
2098 
2099 	sdr_set_bits(host->base + EMMC_IOCON, 1);
2100 	udelay(10); /* 10us is enough */
2101 	sdr_clr_bits(host->base + EMMC_IOCON, 1);
2102 }
2103 
2104 static void msdc_ack_sdio_irq(struct mmc_host *mmc)
2105 {
2106 	__msdc_enable_sdio_irq(mmc, 1);
2107 }
2108 
2109 static int msdc_get_cd(struct mmc_host *mmc)
2110 {
2111 	struct msdc_host *host = mmc_priv(mmc);
2112 	int val;
2113 
2114 	if (mmc->caps & MMC_CAP_NONREMOVABLE)
2115 		return 1;
2116 
2117 	if (!host->internal_cd)
2118 		return mmc_gpio_get_cd(mmc);
2119 
2120 	val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS;
2121 	if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH)
2122 		return !!val;
2123 	else
2124 		return !val;
2125 }
2126 
2127 static const struct mmc_host_ops mt_msdc_ops = {
2128 	.post_req = msdc_post_req,
2129 	.pre_req = msdc_pre_req,
2130 	.request = msdc_ops_request,
2131 	.set_ios = msdc_ops_set_ios,
2132 	.get_ro = mmc_gpio_get_ro,
2133 	.get_cd = msdc_get_cd,
2134 	.enable_sdio_irq = msdc_enable_sdio_irq,
2135 	.ack_sdio_irq = msdc_ack_sdio_irq,
2136 	.start_signal_voltage_switch = msdc_ops_switch_volt,
2137 	.card_busy = msdc_card_busy,
2138 	.execute_tuning = msdc_execute_tuning,
2139 	.prepare_hs400_tuning = msdc_prepare_hs400_tuning,
2140 	.hw_reset = msdc_hw_reset,
2141 };
2142 
2143 static void msdc_of_property_parse(struct platform_device *pdev,
2144 				   struct msdc_host *host)
2145 {
2146 	of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck",
2147 			     &host->latch_ck);
2148 
2149 	of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
2150 			     &host->hs400_ds_delay);
2151 
2152 	of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay",
2153 			     &host->hs200_cmd_int_delay);
2154 
2155 	of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay",
2156 			     &host->hs400_cmd_int_delay);
2157 
2158 	if (of_property_read_bool(pdev->dev.of_node,
2159 				  "mediatek,hs400-cmd-resp-sel-rising"))
2160 		host->hs400_cmd_resp_sel_rising = true;
2161 	else
2162 		host->hs400_cmd_resp_sel_rising = false;
2163 }
2164 
2165 static int msdc_drv_probe(struct platform_device *pdev)
2166 {
2167 	struct mmc_host *mmc;
2168 	struct msdc_host *host;
2169 	struct resource *res;
2170 	int ret;
2171 
2172 	if (!pdev->dev.of_node) {
2173 		dev_err(&pdev->dev, "No DT found\n");
2174 		return -EINVAL;
2175 	}
2176 
2177 	/* Allocate MMC host for this device */
2178 	mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
2179 	if (!mmc)
2180 		return -ENOMEM;
2181 
2182 	host = mmc_priv(mmc);
2183 	ret = mmc_of_parse(mmc);
2184 	if (ret)
2185 		goto host_free;
2186 
2187 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2188 	host->base = devm_ioremap_resource(&pdev->dev, res);
2189 	if (IS_ERR(host->base)) {
2190 		ret = PTR_ERR(host->base);
2191 		goto host_free;
2192 	}
2193 
2194 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2195 	if (res) {
2196 		host->top_base = devm_ioremap_resource(&pdev->dev, res);
2197 		if (IS_ERR(host->top_base))
2198 			host->top_base = NULL;
2199 	}
2200 
2201 	ret = mmc_regulator_get_supply(mmc);
2202 	if (ret)
2203 		goto host_free;
2204 
2205 	host->src_clk = devm_clk_get(&pdev->dev, "source");
2206 	if (IS_ERR(host->src_clk)) {
2207 		ret = PTR_ERR(host->src_clk);
2208 		goto host_free;
2209 	}
2210 
2211 	host->h_clk = devm_clk_get(&pdev->dev, "hclk");
2212 	if (IS_ERR(host->h_clk)) {
2213 		ret = PTR_ERR(host->h_clk);
2214 		goto host_free;
2215 	}
2216 
2217 	host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
2218 	if (IS_ERR(host->bus_clk))
2219 		host->bus_clk = NULL;
2220 	/*source clock control gate is optional clock*/
2221 	host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg");
2222 	if (IS_ERR(host->src_clk_cg))
2223 		host->src_clk_cg = NULL;
2224 
2225 	host->irq = platform_get_irq(pdev, 0);
2226 	if (host->irq < 0) {
2227 		ret = -EINVAL;
2228 		goto host_free;
2229 	}
2230 
2231 	host->pinctrl = devm_pinctrl_get(&pdev->dev);
2232 	if (IS_ERR(host->pinctrl)) {
2233 		ret = PTR_ERR(host->pinctrl);
2234 		dev_err(&pdev->dev, "Cannot find pinctrl!\n");
2235 		goto host_free;
2236 	}
2237 
2238 	host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
2239 	if (IS_ERR(host->pins_default)) {
2240 		ret = PTR_ERR(host->pins_default);
2241 		dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
2242 		goto host_free;
2243 	}
2244 
2245 	host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
2246 	if (IS_ERR(host->pins_uhs)) {
2247 		ret = PTR_ERR(host->pins_uhs);
2248 		dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
2249 		goto host_free;
2250 	}
2251 
2252 	msdc_of_property_parse(pdev, host);
2253 
2254 	host->dev = &pdev->dev;
2255 	host->dev_comp = of_device_get_match_data(&pdev->dev);
2256 	host->mmc = mmc;
2257 	host->src_clk_freq = clk_get_rate(host->src_clk);
2258 	/* Set host parameters to mmc */
2259 	mmc->ops = &mt_msdc_ops;
2260 	if (host->dev_comp->clk_div_bits == 8)
2261 		mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
2262 	else
2263 		mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
2264 
2265 	if (!(mmc->caps & MMC_CAP_NONREMOVABLE) &&
2266 	    !mmc_can_gpio_cd(mmc) &&
2267 	    host->dev_comp->use_internal_cd) {
2268 		/*
2269 		 * Is removable but no GPIO declared, so
2270 		 * use internal functionality.
2271 		 */
2272 		host->internal_cd = true;
2273 	}
2274 
2275 	if (mmc->caps & MMC_CAP_SDIO_IRQ)
2276 		mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2277 
2278 	mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23;
2279 	/* MMC core transfer sizes tunable parameters */
2280 	mmc->max_segs = MAX_BD_NUM;
2281 	mmc->max_seg_size = BDMA_DESC_BUFLEN;
2282 	mmc->max_blk_size = 2048;
2283 	mmc->max_req_size = 512 * 1024;
2284 	mmc->max_blk_count = mmc->max_req_size / 512;
2285 	if (host->dev_comp->support_64g)
2286 		host->dma_mask = DMA_BIT_MASK(36);
2287 	else
2288 		host->dma_mask = DMA_BIT_MASK(32);
2289 	mmc_dev(mmc)->dma_mask = &host->dma_mask;
2290 
2291 	host->timeout_clks = 3 * 1048576;
2292 	host->dma.gpd = dma_alloc_coherent(&pdev->dev,
2293 				2 * sizeof(struct mt_gpdma_desc),
2294 				&host->dma.gpd_addr, GFP_KERNEL);
2295 	host->dma.bd = dma_alloc_coherent(&pdev->dev,
2296 				MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2297 				&host->dma.bd_addr, GFP_KERNEL);
2298 	if (!host->dma.gpd || !host->dma.bd) {
2299 		ret = -ENOMEM;
2300 		goto release_mem;
2301 	}
2302 	msdc_init_gpd_bd(host, &host->dma);
2303 	INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
2304 	spin_lock_init(&host->lock);
2305 
2306 	platform_set_drvdata(pdev, mmc);
2307 	msdc_ungate_clock(host);
2308 	msdc_init_hw(host);
2309 
2310 	ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
2311 			       IRQF_TRIGGER_NONE, pdev->name, host);
2312 	if (ret)
2313 		goto release;
2314 
2315 	pm_runtime_set_active(host->dev);
2316 	pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
2317 	pm_runtime_use_autosuspend(host->dev);
2318 	pm_runtime_enable(host->dev);
2319 	ret = mmc_add_host(mmc);
2320 
2321 	if (ret)
2322 		goto end;
2323 
2324 	return 0;
2325 end:
2326 	pm_runtime_disable(host->dev);
2327 release:
2328 	platform_set_drvdata(pdev, NULL);
2329 	msdc_deinit_hw(host);
2330 	msdc_gate_clock(host);
2331 release_mem:
2332 	if (host->dma.gpd)
2333 		dma_free_coherent(&pdev->dev,
2334 			2 * sizeof(struct mt_gpdma_desc),
2335 			host->dma.gpd, host->dma.gpd_addr);
2336 	if (host->dma.bd)
2337 		dma_free_coherent(&pdev->dev,
2338 			MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2339 			host->dma.bd, host->dma.bd_addr);
2340 host_free:
2341 	mmc_free_host(mmc);
2342 
2343 	return ret;
2344 }
2345 
2346 static int msdc_drv_remove(struct platform_device *pdev)
2347 {
2348 	struct mmc_host *mmc;
2349 	struct msdc_host *host;
2350 
2351 	mmc = platform_get_drvdata(pdev);
2352 	host = mmc_priv(mmc);
2353 
2354 	pm_runtime_get_sync(host->dev);
2355 
2356 	platform_set_drvdata(pdev, NULL);
2357 	mmc_remove_host(host->mmc);
2358 	msdc_deinit_hw(host);
2359 	msdc_gate_clock(host);
2360 
2361 	pm_runtime_disable(host->dev);
2362 	pm_runtime_put_noidle(host->dev);
2363 	dma_free_coherent(&pdev->dev,
2364 			2 * sizeof(struct mt_gpdma_desc),
2365 			host->dma.gpd, host->dma.gpd_addr);
2366 	dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2367 			host->dma.bd, host->dma.bd_addr);
2368 
2369 	mmc_free_host(host->mmc);
2370 
2371 	return 0;
2372 }
2373 
2374 #ifdef CONFIG_PM
2375 static void msdc_save_reg(struct msdc_host *host)
2376 {
2377 	u32 tune_reg = host->dev_comp->pad_tune_reg;
2378 
2379 	host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
2380 	host->save_para.iocon = readl(host->base + MSDC_IOCON);
2381 	host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
2382 	host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
2383 	host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
2384 	host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
2385 	host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
2386 	host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2387 	host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
2388 	host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
2389 	host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
2390 	if (host->top_base) {
2391 		host->save_para.emmc_top_control =
2392 			readl(host->top_base + EMMC_TOP_CONTROL);
2393 		host->save_para.emmc_top_cmd =
2394 			readl(host->top_base + EMMC_TOP_CMD);
2395 		host->save_para.emmc50_pad_ds_tune =
2396 			readl(host->top_base + EMMC50_PAD_DS_TUNE);
2397 	} else {
2398 		host->save_para.pad_tune = readl(host->base + tune_reg);
2399 	}
2400 }
2401 
2402 static void msdc_restore_reg(struct msdc_host *host)
2403 {
2404 	u32 tune_reg = host->dev_comp->pad_tune_reg;
2405 
2406 	writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
2407 	writel(host->save_para.iocon, host->base + MSDC_IOCON);
2408 	writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
2409 	writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
2410 	writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
2411 	writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
2412 	writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
2413 	writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
2414 	writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
2415 	writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
2416 	writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
2417 	if (host->top_base) {
2418 		writel(host->save_para.emmc_top_control,
2419 		       host->top_base + EMMC_TOP_CONTROL);
2420 		writel(host->save_para.emmc_top_cmd,
2421 		       host->top_base + EMMC_TOP_CMD);
2422 		writel(host->save_para.emmc50_pad_ds_tune,
2423 		       host->top_base + EMMC50_PAD_DS_TUNE);
2424 	} else {
2425 		writel(host->save_para.pad_tune, host->base + tune_reg);
2426 	}
2427 }
2428 
2429 static int msdc_runtime_suspend(struct device *dev)
2430 {
2431 	struct mmc_host *mmc = dev_get_drvdata(dev);
2432 	struct msdc_host *host = mmc_priv(mmc);
2433 
2434 	msdc_save_reg(host);
2435 	msdc_gate_clock(host);
2436 	return 0;
2437 }
2438 
2439 static int msdc_runtime_resume(struct device *dev)
2440 {
2441 	struct mmc_host *mmc = dev_get_drvdata(dev);
2442 	struct msdc_host *host = mmc_priv(mmc);
2443 
2444 	msdc_ungate_clock(host);
2445 	msdc_restore_reg(host);
2446 	return 0;
2447 }
2448 #endif
2449 
2450 static const struct dev_pm_ops msdc_dev_pm_ops = {
2451 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2452 				pm_runtime_force_resume)
2453 	SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
2454 };
2455 
2456 static struct platform_driver mt_msdc_driver = {
2457 	.probe = msdc_drv_probe,
2458 	.remove = msdc_drv_remove,
2459 	.driver = {
2460 		.name = "mtk-msdc",
2461 		.of_match_table = msdc_of_ids,
2462 		.pm = &msdc_dev_pm_ops,
2463 	},
2464 };
2465 
2466 module_platform_driver(mt_msdc_driver);
2467 MODULE_LICENSE("GPL v2");
2468 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");
2469