1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2015 MediaTek Inc. 4 * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 5 */ 6 7 #include <linux/module.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/ioport.h> 12 #include <linux/irq.h> 13 #include <linux/of_address.h> 14 #include <linux/of_device.h> 15 #include <linux/of_irq.h> 16 #include <linux/of_gpio.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/slab.h> 23 #include <linux/spinlock.h> 24 #include <linux/interrupt.h> 25 #include <linux/reset.h> 26 27 #include <linux/mmc/card.h> 28 #include <linux/mmc/core.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/mmc.h> 31 #include <linux/mmc/sd.h> 32 #include <linux/mmc/sdio.h> 33 #include <linux/mmc/slot-gpio.h> 34 35 #include "cqhci.h" 36 37 #define MAX_BD_NUM 1024 38 39 /*--------------------------------------------------------------------------*/ 40 /* Common Definition */ 41 /*--------------------------------------------------------------------------*/ 42 #define MSDC_BUS_1BITS 0x0 43 #define MSDC_BUS_4BITS 0x1 44 #define MSDC_BUS_8BITS 0x2 45 46 #define MSDC_BURST_64B 0x6 47 48 /*--------------------------------------------------------------------------*/ 49 /* Register Offset */ 50 /*--------------------------------------------------------------------------*/ 51 #define MSDC_CFG 0x0 52 #define MSDC_IOCON 0x04 53 #define MSDC_PS 0x08 54 #define MSDC_INT 0x0c 55 #define MSDC_INTEN 0x10 56 #define MSDC_FIFOCS 0x14 57 #define SDC_CFG 0x30 58 #define SDC_CMD 0x34 59 #define SDC_ARG 0x38 60 #define SDC_STS 0x3c 61 #define SDC_RESP0 0x40 62 #define SDC_RESP1 0x44 63 #define SDC_RESP2 0x48 64 #define SDC_RESP3 0x4c 65 #define SDC_BLK_NUM 0x50 66 #define SDC_ADV_CFG0 0x64 67 #define EMMC_IOCON 0x7c 68 #define SDC_ACMD_RESP 0x80 69 #define DMA_SA_H4BIT 0x8c 70 #define MSDC_DMA_SA 0x90 71 #define MSDC_DMA_CTRL 0x98 72 #define MSDC_DMA_CFG 0x9c 73 #define MSDC_PATCH_BIT 0xb0 74 #define MSDC_PATCH_BIT1 0xb4 75 #define MSDC_PATCH_BIT2 0xb8 76 #define MSDC_PAD_TUNE 0xec 77 #define MSDC_PAD_TUNE0 0xf0 78 #define PAD_DS_TUNE 0x188 79 #define PAD_CMD_TUNE 0x18c 80 #define EMMC50_CFG0 0x208 81 #define EMMC50_CFG3 0x220 82 #define SDC_FIFO_CFG 0x228 83 84 /*--------------------------------------------------------------------------*/ 85 /* Top Pad Register Offset */ 86 /*--------------------------------------------------------------------------*/ 87 #define EMMC_TOP_CONTROL 0x00 88 #define EMMC_TOP_CMD 0x04 89 #define EMMC50_PAD_DS_TUNE 0x0c 90 91 /*--------------------------------------------------------------------------*/ 92 /* Register Mask */ 93 /*--------------------------------------------------------------------------*/ 94 95 /* MSDC_CFG mask */ 96 #define MSDC_CFG_MODE (0x1 << 0) /* RW */ 97 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ 98 #define MSDC_CFG_RST (0x1 << 2) /* RW */ 99 #define MSDC_CFG_PIO (0x1 << 3) /* RW */ 100 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ 101 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ 102 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ 103 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ 104 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ 105 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ 106 #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */ 107 #define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */ 108 #define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */ 109 #define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */ 110 111 /* MSDC_IOCON mask */ 112 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ 113 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ 114 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ 115 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ 116 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ 117 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ 118 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ 119 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ 120 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ 121 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ 122 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ 123 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ 124 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ 125 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ 126 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ 127 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ 128 129 /* MSDC_PS mask */ 130 #define MSDC_PS_CDEN (0x1 << 0) /* RW */ 131 #define MSDC_PS_CDSTS (0x1 << 1) /* R */ 132 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ 133 #define MSDC_PS_DAT (0xff << 16) /* R */ 134 #define MSDC_PS_DATA1 (0x1 << 17) /* R */ 135 #define MSDC_PS_CMD (0x1 << 24) /* R */ 136 #define MSDC_PS_WP (0x1 << 31) /* R */ 137 138 /* MSDC_INT mask */ 139 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ 140 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ 141 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ 142 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ 143 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ 144 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ 145 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ 146 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ 147 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ 148 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ 149 #define MSDC_INT_CSTA (0x1 << 11) /* R */ 150 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ 151 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ 152 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ 153 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ 154 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ 155 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ 156 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ 157 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ 158 #define MSDC_INT_CMDQ (0x1 << 28) /* W1C */ 159 160 /* MSDC_INTEN mask */ 161 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ 162 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ 163 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ 164 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ 165 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ 166 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ 167 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ 168 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ 169 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ 170 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ 171 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ 172 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ 173 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ 174 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ 175 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ 176 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ 177 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ 178 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ 179 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ 180 181 /* MSDC_FIFOCS mask */ 182 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 183 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 184 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ 185 186 /* SDC_CFG mask */ 187 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ 188 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ 189 #define SDC_CFG_WRDTOC (0x1fff << 2) /* RW */ 190 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 191 #define SDC_CFG_SDIO (0x1 << 19) /* RW */ 192 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 193 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ 194 #define SDC_CFG_DTOC (0xff << 24) /* RW */ 195 196 /* SDC_STS mask */ 197 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ 198 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 199 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ 200 201 #define SDC_DAT1_IRQ_TRIGGER (0x1 << 19) /* RW */ 202 /* SDC_ADV_CFG0 mask */ 203 #define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */ 204 205 /* DMA_SA_H4BIT mask */ 206 #define DMA_ADDR_HIGH_4BIT (0xf << 0) /* RW */ 207 208 /* MSDC_DMA_CTRL mask */ 209 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ 210 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ 211 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ 212 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ 213 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ 214 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ 215 216 /* MSDC_DMA_CFG mask */ 217 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ 218 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ 219 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ 220 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ 221 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ 222 223 /* MSDC_PATCH_BIT mask */ 224 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ 225 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) 226 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) 227 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ 228 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ 229 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ 230 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ 231 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ 232 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ 233 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ 234 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ 235 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ 236 237 #define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */ 238 #define MSDC_PB1_BUSY_CHECK_SEL (0x1 << 7) /* RW */ 239 #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ 240 241 #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ 242 #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */ 243 #define MSDC_PB2_SUPPORT_64G (0x1 << 1) /* RW */ 244 #define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */ 245 #define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */ 246 #define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */ 247 248 #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */ 249 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */ 250 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */ 251 #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */ 252 #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */ 253 #define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */ 254 #define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */ 255 #define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */ 256 257 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */ 258 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */ 259 #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */ 260 261 #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */ 262 263 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */ 264 #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ 265 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ 266 267 #define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */ 268 269 #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */ 270 #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */ 271 272 /* EMMC_TOP_CONTROL mask */ 273 #define PAD_RXDLY_SEL (0x1 << 0) /* RW */ 274 #define DELAY_EN (0x1 << 1) /* RW */ 275 #define PAD_DAT_RD_RXDLY2 (0x1f << 2) /* RW */ 276 #define PAD_DAT_RD_RXDLY (0x1f << 7) /* RW */ 277 #define PAD_DAT_RD_RXDLY2_SEL (0x1 << 12) /* RW */ 278 #define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */ 279 #define DATA_K_VALUE_SEL (0x1 << 14) /* RW */ 280 #define SDC_RX_ENH_EN (0x1 << 15) /* TW */ 281 282 /* EMMC_TOP_CMD mask */ 283 #define PAD_CMD_RXDLY2 (0x1f << 0) /* RW */ 284 #define PAD_CMD_RXDLY (0x1f << 5) /* RW */ 285 #define PAD_CMD_RD_RXDLY2_SEL (0x1 << 10) /* RW */ 286 #define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */ 287 #define PAD_CMD_TX_DLY (0x1f << 12) /* RW */ 288 289 #define REQ_CMD_EIO (0x1 << 0) 290 #define REQ_CMD_TMO (0x1 << 1) 291 #define REQ_DAT_ERR (0x1 << 2) 292 #define REQ_STOP_EIO (0x1 << 3) 293 #define REQ_STOP_TMO (0x1 << 4) 294 #define REQ_CMD_BUSY (0x1 << 5) 295 296 #define MSDC_PREPARE_FLAG (0x1 << 0) 297 #define MSDC_ASYNC_FLAG (0x1 << 1) 298 #define MSDC_MMAP_FLAG (0x1 << 2) 299 300 #define MTK_MMC_AUTOSUSPEND_DELAY 50 301 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 302 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 303 304 #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */ 305 306 #define PAD_DELAY_MAX 32 /* PAD delay cells */ 307 /*--------------------------------------------------------------------------*/ 308 /* Descriptor Structure */ 309 /*--------------------------------------------------------------------------*/ 310 struct mt_gpdma_desc { 311 u32 gpd_info; 312 #define GPDMA_DESC_HWO (0x1 << 0) 313 #define GPDMA_DESC_BDP (0x1 << 1) 314 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 315 #define GPDMA_DESC_INT (0x1 << 16) 316 #define GPDMA_DESC_NEXT_H4 (0xf << 24) 317 #define GPDMA_DESC_PTR_H4 (0xf << 28) 318 u32 next; 319 u32 ptr; 320 u32 gpd_data_len; 321 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 322 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ 323 u32 arg; 324 u32 blknum; 325 u32 cmd; 326 }; 327 328 struct mt_bdma_desc { 329 u32 bd_info; 330 #define BDMA_DESC_EOL (0x1 << 0) 331 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 332 #define BDMA_DESC_BLKPAD (0x1 << 17) 333 #define BDMA_DESC_DWPAD (0x1 << 18) 334 #define BDMA_DESC_NEXT_H4 (0xf << 24) 335 #define BDMA_DESC_PTR_H4 (0xf << 28) 336 u32 next; 337 u32 ptr; 338 u32 bd_data_len; 339 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 340 #define BDMA_DESC_BUFLEN_EXT (0xffffff) /* bit0 ~ bit23 */ 341 }; 342 343 struct msdc_dma { 344 struct scatterlist *sg; /* I/O scatter list */ 345 struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 346 struct mt_bdma_desc *bd; /* pointer to bd array */ 347 dma_addr_t gpd_addr; /* the physical address of gpd array */ 348 dma_addr_t bd_addr; /* the physical address of bd array */ 349 }; 350 351 struct msdc_save_para { 352 u32 msdc_cfg; 353 u32 iocon; 354 u32 sdc_cfg; 355 u32 pad_tune; 356 u32 patch_bit0; 357 u32 patch_bit1; 358 u32 patch_bit2; 359 u32 pad_ds_tune; 360 u32 pad_cmd_tune; 361 u32 emmc50_cfg0; 362 u32 emmc50_cfg3; 363 u32 sdc_fifo_cfg; 364 u32 emmc_top_control; 365 u32 emmc_top_cmd; 366 u32 emmc50_pad_ds_tune; 367 }; 368 369 struct mtk_mmc_compatible { 370 u8 clk_div_bits; 371 bool recheck_sdio_irq; 372 bool hs400_tune; /* only used for MT8173 */ 373 u32 pad_tune_reg; 374 bool async_fifo; 375 bool data_tune; 376 bool busy_check; 377 bool stop_clk_fix; 378 bool enhance_rx; 379 bool support_64g; 380 bool use_internal_cd; 381 }; 382 383 struct msdc_tune_para { 384 u32 iocon; 385 u32 pad_tune; 386 u32 pad_cmd_tune; 387 u32 emmc_top_control; 388 u32 emmc_top_cmd; 389 }; 390 391 struct msdc_delay_phase { 392 u8 maxlen; 393 u8 start; 394 u8 final_phase; 395 }; 396 397 struct msdc_host { 398 struct device *dev; 399 const struct mtk_mmc_compatible *dev_comp; 400 int cmd_rsp; 401 402 spinlock_t lock; 403 struct mmc_request *mrq; 404 struct mmc_command *cmd; 405 struct mmc_data *data; 406 int error; 407 408 void __iomem *base; /* host base address */ 409 void __iomem *top_base; /* host top register base address */ 410 411 struct msdc_dma dma; /* dma channel */ 412 u64 dma_mask; 413 414 u32 timeout_ns; /* data timeout ns */ 415 u32 timeout_clks; /* data timeout clks */ 416 417 struct pinctrl *pinctrl; 418 struct pinctrl_state *pins_default; 419 struct pinctrl_state *pins_uhs; 420 struct delayed_work req_timeout; 421 int irq; /* host interrupt */ 422 struct reset_control *reset; 423 424 struct clk *src_clk; /* msdc source clock */ 425 struct clk *h_clk; /* msdc h_clk */ 426 struct clk *bus_clk; /* bus clock which used to access register */ 427 struct clk *src_clk_cg; /* msdc source clock control gate */ 428 u32 mclk; /* mmc subsystem clock frequency */ 429 u32 src_clk_freq; /* source clock frequency */ 430 unsigned char timing; 431 bool vqmmc_enabled; 432 u32 latch_ck; 433 u32 hs400_ds_delay; 434 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 435 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 436 bool hs400_cmd_resp_sel_rising; 437 /* cmd response sample selection for HS400 */ 438 bool hs400_mode; /* current eMMC will run at hs400 mode */ 439 bool internal_cd; /* Use internal card-detect logic */ 440 bool cqhci; /* support eMMC hw cmdq */ 441 struct msdc_save_para save_para; /* used when gate HCLK */ 442 struct msdc_tune_para def_tune_para; /* default tune setting */ 443 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 444 struct cqhci_host *cq_host; 445 }; 446 447 static const struct mtk_mmc_compatible mt8135_compat = { 448 .clk_div_bits = 8, 449 .recheck_sdio_irq = false, 450 .hs400_tune = false, 451 .pad_tune_reg = MSDC_PAD_TUNE, 452 .async_fifo = false, 453 .data_tune = false, 454 .busy_check = false, 455 .stop_clk_fix = false, 456 .enhance_rx = false, 457 .support_64g = false, 458 }; 459 460 static const struct mtk_mmc_compatible mt8173_compat = { 461 .clk_div_bits = 8, 462 .recheck_sdio_irq = true, 463 .hs400_tune = true, 464 .pad_tune_reg = MSDC_PAD_TUNE, 465 .async_fifo = false, 466 .data_tune = false, 467 .busy_check = false, 468 .stop_clk_fix = false, 469 .enhance_rx = false, 470 .support_64g = false, 471 }; 472 473 static const struct mtk_mmc_compatible mt8183_compat = { 474 .clk_div_bits = 12, 475 .recheck_sdio_irq = false, 476 .hs400_tune = false, 477 .pad_tune_reg = MSDC_PAD_TUNE0, 478 .async_fifo = true, 479 .data_tune = true, 480 .busy_check = true, 481 .stop_clk_fix = true, 482 .enhance_rx = true, 483 .support_64g = true, 484 }; 485 486 static const struct mtk_mmc_compatible mt2701_compat = { 487 .clk_div_bits = 12, 488 .recheck_sdio_irq = false, 489 .hs400_tune = false, 490 .pad_tune_reg = MSDC_PAD_TUNE0, 491 .async_fifo = true, 492 .data_tune = true, 493 .busy_check = false, 494 .stop_clk_fix = false, 495 .enhance_rx = false, 496 .support_64g = false, 497 }; 498 499 static const struct mtk_mmc_compatible mt2712_compat = { 500 .clk_div_bits = 12, 501 .recheck_sdio_irq = false, 502 .hs400_tune = false, 503 .pad_tune_reg = MSDC_PAD_TUNE0, 504 .async_fifo = true, 505 .data_tune = true, 506 .busy_check = true, 507 .stop_clk_fix = true, 508 .enhance_rx = true, 509 .support_64g = true, 510 }; 511 512 static const struct mtk_mmc_compatible mt7622_compat = { 513 .clk_div_bits = 12, 514 .recheck_sdio_irq = false, 515 .hs400_tune = false, 516 .pad_tune_reg = MSDC_PAD_TUNE0, 517 .async_fifo = true, 518 .data_tune = true, 519 .busy_check = true, 520 .stop_clk_fix = true, 521 .enhance_rx = true, 522 .support_64g = false, 523 }; 524 525 static const struct mtk_mmc_compatible mt8516_compat = { 526 .clk_div_bits = 12, 527 .recheck_sdio_irq = false, 528 .hs400_tune = false, 529 .pad_tune_reg = MSDC_PAD_TUNE0, 530 .async_fifo = true, 531 .data_tune = true, 532 .busy_check = true, 533 .stop_clk_fix = true, 534 }; 535 536 static const struct mtk_mmc_compatible mt7620_compat = { 537 .clk_div_bits = 8, 538 .recheck_sdio_irq = false, 539 .hs400_tune = false, 540 .pad_tune_reg = MSDC_PAD_TUNE, 541 .async_fifo = false, 542 .data_tune = false, 543 .busy_check = false, 544 .stop_clk_fix = false, 545 .enhance_rx = false, 546 .use_internal_cd = true, 547 }; 548 549 static const struct mtk_mmc_compatible mt6779_compat = { 550 .clk_div_bits = 12, 551 .hs400_tune = false, 552 .pad_tune_reg = MSDC_PAD_TUNE0, 553 .async_fifo = true, 554 .data_tune = true, 555 .busy_check = true, 556 .stop_clk_fix = true, 557 .enhance_rx = true, 558 .support_64g = true, 559 }; 560 561 static const struct of_device_id msdc_of_ids[] = { 562 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, 563 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, 564 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, 565 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, 566 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, 567 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, 568 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, 569 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, 570 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, 571 {} 572 }; 573 MODULE_DEVICE_TABLE(of, msdc_of_ids); 574 575 static void sdr_set_bits(void __iomem *reg, u32 bs) 576 { 577 u32 val = readl(reg); 578 579 val |= bs; 580 writel(val, reg); 581 } 582 583 static void sdr_clr_bits(void __iomem *reg, u32 bs) 584 { 585 u32 val = readl(reg); 586 587 val &= ~bs; 588 writel(val, reg); 589 } 590 591 static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 592 { 593 unsigned int tv = readl(reg); 594 595 tv &= ~field; 596 tv |= ((val) << (ffs((unsigned int)field) - 1)); 597 writel(tv, reg); 598 } 599 600 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 601 { 602 unsigned int tv = readl(reg); 603 604 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 605 } 606 607 static void msdc_reset_hw(struct msdc_host *host) 608 { 609 u32 val; 610 611 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 612 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) 613 cpu_relax(); 614 615 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 616 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) 617 cpu_relax(); 618 619 val = readl(host->base + MSDC_INT); 620 writel(val, host->base + MSDC_INT); 621 } 622 623 static void msdc_cmd_next(struct msdc_host *host, 624 struct mmc_request *mrq, struct mmc_command *cmd); 625 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb); 626 627 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 628 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 629 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 630 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 631 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 632 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 633 634 static u8 msdc_dma_calcs(u8 *buf, u32 len) 635 { 636 u32 i, sum = 0; 637 638 for (i = 0; i < len; i++) 639 sum += buf[i]; 640 return 0xff - (u8) sum; 641 } 642 643 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 644 struct mmc_data *data) 645 { 646 unsigned int j, dma_len; 647 dma_addr_t dma_address; 648 u32 dma_ctrl; 649 struct scatterlist *sg; 650 struct mt_gpdma_desc *gpd; 651 struct mt_bdma_desc *bd; 652 653 sg = data->sg; 654 655 gpd = dma->gpd; 656 bd = dma->bd; 657 658 /* modify gpd */ 659 gpd->gpd_info |= GPDMA_DESC_HWO; 660 gpd->gpd_info |= GPDMA_DESC_BDP; 661 /* need to clear first. use these bits to calc checksum */ 662 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 663 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 664 665 /* modify bd */ 666 for_each_sg(data->sg, sg, data->sg_count, j) { 667 dma_address = sg_dma_address(sg); 668 dma_len = sg_dma_len(sg); 669 670 /* init bd */ 671 bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 672 bd[j].bd_info &= ~BDMA_DESC_DWPAD; 673 bd[j].ptr = lower_32_bits(dma_address); 674 if (host->dev_comp->support_64g) { 675 bd[j].bd_info &= ~BDMA_DESC_PTR_H4; 676 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf) 677 << 28; 678 } 679 680 if (host->dev_comp->support_64g) { 681 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT; 682 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT); 683 } else { 684 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 685 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 686 } 687 688 if (j == data->sg_count - 1) /* the last bd */ 689 bd[j].bd_info |= BDMA_DESC_EOL; 690 else 691 bd[j].bd_info &= ~BDMA_DESC_EOL; 692 693 /* checksume need to clear first */ 694 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 695 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 696 } 697 698 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 699 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 700 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 701 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); 702 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 703 if (host->dev_comp->support_64g) 704 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, 705 upper_32_bits(dma->gpd_addr) & 0xf); 706 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); 707 } 708 709 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq) 710 { 711 struct mmc_data *data = mrq->data; 712 713 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 714 data->host_cookie |= MSDC_PREPARE_FLAG; 715 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 716 mmc_get_dma_dir(data)); 717 } 718 } 719 720 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) 721 { 722 struct mmc_data *data = mrq->data; 723 724 if (data->host_cookie & MSDC_ASYNC_FLAG) 725 return; 726 727 if (data->host_cookie & MSDC_PREPARE_FLAG) { 728 dma_unmap_sg(host->dev, data->sg, data->sg_len, 729 mmc_get_dma_dir(data)); 730 data->host_cookie &= ~MSDC_PREPARE_FLAG; 731 } 732 } 733 734 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) 735 { 736 struct mmc_host *mmc = mmc_from_priv(host); 737 u64 timeout, clk_ns; 738 u32 mode = 0; 739 740 if (mmc->actual_clock == 0) { 741 timeout = 0; 742 } else { 743 clk_ns = 1000000000ULL; 744 do_div(clk_ns, mmc->actual_clock); 745 timeout = ns + clk_ns - 1; 746 do_div(timeout, clk_ns); 747 timeout += clks; 748 /* in 1048576 sclk cycle unit */ 749 timeout = DIV_ROUND_UP(timeout, (0x1 << 20)); 750 if (host->dev_comp->clk_div_bits == 8) 751 sdr_get_field(host->base + MSDC_CFG, 752 MSDC_CFG_CKMOD, &mode); 753 else 754 sdr_get_field(host->base + MSDC_CFG, 755 MSDC_CFG_CKMOD_EXTRA, &mode); 756 /*DDR mode will double the clk cycles for data timeout */ 757 timeout = mode >= 2 ? timeout * 2 : timeout; 758 timeout = timeout > 1 ? timeout - 1 : 0; 759 } 760 return timeout; 761 } 762 763 /* clock control primitives */ 764 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) 765 { 766 u64 timeout; 767 768 host->timeout_ns = ns; 769 host->timeout_clks = clks; 770 771 timeout = msdc_timeout_cal(host, ns, clks); 772 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 773 (u32)(timeout > 255 ? 255 : timeout)); 774 } 775 776 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) 777 { 778 u64 timeout; 779 780 timeout = msdc_timeout_cal(host, ns, clks); 781 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, 782 (u32)(timeout > 8191 ? 8191 : timeout)); 783 } 784 785 static void msdc_gate_clock(struct msdc_host *host) 786 { 787 clk_disable_unprepare(host->src_clk_cg); 788 clk_disable_unprepare(host->src_clk); 789 clk_disable_unprepare(host->bus_clk); 790 clk_disable_unprepare(host->h_clk); 791 } 792 793 static void msdc_ungate_clock(struct msdc_host *host) 794 { 795 clk_prepare_enable(host->h_clk); 796 clk_prepare_enable(host->bus_clk); 797 clk_prepare_enable(host->src_clk); 798 clk_prepare_enable(host->src_clk_cg); 799 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 800 cpu_relax(); 801 } 802 803 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 804 { 805 struct mmc_host *mmc = mmc_from_priv(host); 806 u32 mode; 807 u32 flags; 808 u32 div; 809 u32 sclk; 810 u32 tune_reg = host->dev_comp->pad_tune_reg; 811 812 if (!hz) { 813 dev_dbg(host->dev, "set mclk to 0\n"); 814 host->mclk = 0; 815 mmc->actual_clock = 0; 816 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 817 return; 818 } 819 820 flags = readl(host->base + MSDC_INTEN); 821 sdr_clr_bits(host->base + MSDC_INTEN, flags); 822 if (host->dev_comp->clk_div_bits == 8) 823 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 824 else 825 sdr_clr_bits(host->base + MSDC_CFG, 826 MSDC_CFG_HS400_CK_MODE_EXTRA); 827 if (timing == MMC_TIMING_UHS_DDR50 || 828 timing == MMC_TIMING_MMC_DDR52 || 829 timing == MMC_TIMING_MMC_HS400) { 830 if (timing == MMC_TIMING_MMC_HS400) 831 mode = 0x3; 832 else 833 mode = 0x2; /* ddr mode and use divisor */ 834 835 if (hz >= (host->src_clk_freq >> 2)) { 836 div = 0; /* mean div = 1/4 */ 837 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 838 } else { 839 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 840 sclk = (host->src_clk_freq >> 2) / div; 841 div = (div >> 1); 842 } 843 844 if (timing == MMC_TIMING_MMC_HS400 && 845 hz >= (host->src_clk_freq >> 1)) { 846 if (host->dev_comp->clk_div_bits == 8) 847 sdr_set_bits(host->base + MSDC_CFG, 848 MSDC_CFG_HS400_CK_MODE); 849 else 850 sdr_set_bits(host->base + MSDC_CFG, 851 MSDC_CFG_HS400_CK_MODE_EXTRA); 852 sclk = host->src_clk_freq >> 1; 853 div = 0; /* div is ignore when bit18 is set */ 854 } 855 } else if (hz >= host->src_clk_freq) { 856 mode = 0x1; /* no divisor */ 857 div = 0; 858 sclk = host->src_clk_freq; 859 } else { 860 mode = 0x0; /* use divisor */ 861 if (hz >= (host->src_clk_freq >> 1)) { 862 div = 0; /* mean div = 1/2 */ 863 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 864 } else { 865 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 866 sclk = (host->src_clk_freq >> 2) / div; 867 } 868 } 869 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 870 /* 871 * As src_clk/HCLK use the same bit to gate/ungate, 872 * So if want to only gate src_clk, need gate its parent(mux). 873 */ 874 if (host->src_clk_cg) 875 clk_disable_unprepare(host->src_clk_cg); 876 else 877 clk_disable_unprepare(clk_get_parent(host->src_clk)); 878 if (host->dev_comp->clk_div_bits == 8) 879 sdr_set_field(host->base + MSDC_CFG, 880 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 881 (mode << 8) | div); 882 else 883 sdr_set_field(host->base + MSDC_CFG, 884 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, 885 (mode << 12) | div); 886 if (host->src_clk_cg) 887 clk_prepare_enable(host->src_clk_cg); 888 else 889 clk_prepare_enable(clk_get_parent(host->src_clk)); 890 891 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 892 cpu_relax(); 893 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 894 mmc->actual_clock = sclk; 895 host->mclk = hz; 896 host->timing = timing; 897 /* need because clk changed. */ 898 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 899 sdr_set_bits(host->base + MSDC_INTEN, flags); 900 901 /* 902 * mmc_select_hs400() will drop to 50Mhz and High speed mode, 903 * tune result of hs200/200Mhz is not suitable for 50Mhz 904 */ 905 if (mmc->actual_clock <= 52000000) { 906 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 907 if (host->top_base) { 908 writel(host->def_tune_para.emmc_top_control, 909 host->top_base + EMMC_TOP_CONTROL); 910 writel(host->def_tune_para.emmc_top_cmd, 911 host->top_base + EMMC_TOP_CMD); 912 } else { 913 writel(host->def_tune_para.pad_tune, 914 host->base + tune_reg); 915 } 916 } else { 917 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 918 writel(host->saved_tune_para.pad_cmd_tune, 919 host->base + PAD_CMD_TUNE); 920 if (host->top_base) { 921 writel(host->saved_tune_para.emmc_top_control, 922 host->top_base + EMMC_TOP_CONTROL); 923 writel(host->saved_tune_para.emmc_top_cmd, 924 host->top_base + EMMC_TOP_CMD); 925 } else { 926 writel(host->saved_tune_para.pad_tune, 927 host->base + tune_reg); 928 } 929 } 930 931 if (timing == MMC_TIMING_MMC_HS400 && 932 host->dev_comp->hs400_tune) 933 sdr_set_field(host->base + tune_reg, 934 MSDC_PAD_TUNE_CMDRRDLY, 935 host->hs400_cmd_int_delay); 936 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock, 937 timing); 938 } 939 940 static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 941 struct mmc_request *mrq, struct mmc_command *cmd) 942 { 943 u32 resp; 944 945 switch (mmc_resp_type(cmd)) { 946 /* Actually, R1, R5, R6, R7 are the same */ 947 case MMC_RSP_R1: 948 resp = 0x1; 949 break; 950 case MMC_RSP_R1B: 951 resp = 0x7; 952 break; 953 case MMC_RSP_R2: 954 resp = 0x2; 955 break; 956 case MMC_RSP_R3: 957 resp = 0x3; 958 break; 959 case MMC_RSP_NONE: 960 default: 961 resp = 0x0; 962 break; 963 } 964 965 return resp; 966 } 967 968 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 969 struct mmc_request *mrq, struct mmc_command *cmd) 970 { 971 struct mmc_host *mmc = mmc_from_priv(host); 972 /* rawcmd : 973 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 974 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 975 */ 976 u32 opcode = cmd->opcode; 977 u32 resp = msdc_cmd_find_resp(host, mrq, cmd); 978 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 979 980 host->cmd_rsp = resp; 981 982 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 983 opcode == MMC_STOP_TRANSMISSION) 984 rawcmd |= (0x1 << 14); 985 else if (opcode == SD_SWITCH_VOLTAGE) 986 rawcmd |= (0x1 << 30); 987 else if (opcode == SD_APP_SEND_SCR || 988 opcode == SD_APP_SEND_NUM_WR_BLKS || 989 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 990 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 991 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 992 rawcmd |= (0x1 << 11); 993 994 if (cmd->data) { 995 struct mmc_data *data = cmd->data; 996 997 if (mmc_op_multi(opcode)) { 998 if (mmc_card_mmc(mmc->card) && mrq->sbc && 999 !(mrq->sbc->arg & 0xFFFF0000)) 1000 rawcmd |= 0x2 << 28; /* AutoCMD23 */ 1001 } 1002 1003 rawcmd |= ((data->blksz & 0xFFF) << 16); 1004 if (data->flags & MMC_DATA_WRITE) 1005 rawcmd |= (0x1 << 13); 1006 if (data->blocks > 1) 1007 rawcmd |= (0x2 << 11); 1008 else 1009 rawcmd |= (0x1 << 11); 1010 /* Always use dma mode */ 1011 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 1012 1013 if (host->timeout_ns != data->timeout_ns || 1014 host->timeout_clks != data->timeout_clks) 1015 msdc_set_timeout(host, data->timeout_ns, 1016 data->timeout_clks); 1017 1018 writel(data->blocks, host->base + SDC_BLK_NUM); 1019 } 1020 return rawcmd; 1021 } 1022 1023 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, 1024 struct mmc_command *cmd, struct mmc_data *data) 1025 { 1026 bool read; 1027 1028 WARN_ON(host->data); 1029 host->data = data; 1030 read = data->flags & MMC_DATA_READ; 1031 1032 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1033 msdc_dma_setup(host, &host->dma, data); 1034 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 1035 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 1036 dev_dbg(host->dev, "DMA start\n"); 1037 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 1038 __func__, cmd->opcode, data->blocks, read); 1039 } 1040 1041 static int msdc_auto_cmd_done(struct msdc_host *host, int events, 1042 struct mmc_command *cmd) 1043 { 1044 u32 *rsp = cmd->resp; 1045 1046 rsp[0] = readl(host->base + SDC_ACMD_RESP); 1047 1048 if (events & MSDC_INT_ACMDRDY) { 1049 cmd->error = 0; 1050 } else { 1051 msdc_reset_hw(host); 1052 if (events & MSDC_INT_ACMDCRCERR) { 1053 cmd->error = -EILSEQ; 1054 host->error |= REQ_STOP_EIO; 1055 } else if (events & MSDC_INT_ACMDTMO) { 1056 cmd->error = -ETIMEDOUT; 1057 host->error |= REQ_STOP_TMO; 1058 } 1059 dev_err(host->dev, 1060 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 1061 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 1062 } 1063 return cmd->error; 1064 } 1065 1066 /* 1067 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost 1068 * 1069 * Host controller may lost interrupt in some special case. 1070 * Add SDIO irq recheck mechanism to make sure all interrupts 1071 * can be processed immediately 1072 */ 1073 static void msdc_recheck_sdio_irq(struct msdc_host *host) 1074 { 1075 struct mmc_host *mmc = mmc_from_priv(host); 1076 u32 reg_int, reg_inten, reg_ps; 1077 1078 if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1079 reg_inten = readl(host->base + MSDC_INTEN); 1080 if (reg_inten & MSDC_INTEN_SDIOIRQ) { 1081 reg_int = readl(host->base + MSDC_INT); 1082 reg_ps = readl(host->base + MSDC_PS); 1083 if (!(reg_int & MSDC_INT_SDIOIRQ || 1084 reg_ps & MSDC_PS_DATA1)) { 1085 __msdc_enable_sdio_irq(host, 0); 1086 sdio_signal_irq(mmc); 1087 } 1088 } 1089 } 1090 } 1091 1092 static void msdc_track_cmd_data(struct msdc_host *host, 1093 struct mmc_command *cmd, struct mmc_data *data) 1094 { 1095 if (host->error) 1096 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 1097 __func__, cmd->opcode, cmd->arg, host->error); 1098 } 1099 1100 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 1101 { 1102 unsigned long flags; 1103 bool ret; 1104 1105 ret = cancel_delayed_work(&host->req_timeout); 1106 if (!ret) { 1107 /* delay work already running */ 1108 return; 1109 } 1110 spin_lock_irqsave(&host->lock, flags); 1111 host->mrq = NULL; 1112 spin_unlock_irqrestore(&host->lock, flags); 1113 1114 msdc_track_cmd_data(host, mrq->cmd, mrq->data); 1115 if (mrq->data) 1116 msdc_unprepare_data(host, mrq); 1117 if (host->error) 1118 msdc_reset_hw(host); 1119 mmc_request_done(mmc_from_priv(host), mrq); 1120 if (host->dev_comp->recheck_sdio_irq) 1121 msdc_recheck_sdio_irq(host); 1122 } 1123 1124 /* returns true if command is fully handled; returns false otherwise */ 1125 static bool msdc_cmd_done(struct msdc_host *host, int events, 1126 struct mmc_request *mrq, struct mmc_command *cmd) 1127 { 1128 bool done = false; 1129 bool sbc_error; 1130 unsigned long flags; 1131 u32 *rsp = cmd->resp; 1132 1133 if (mrq->sbc && cmd == mrq->cmd && 1134 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 1135 | MSDC_INT_ACMDTMO))) 1136 msdc_auto_cmd_done(host, events, mrq->sbc); 1137 1138 sbc_error = mrq->sbc && mrq->sbc->error; 1139 1140 if (!sbc_error && !(events & (MSDC_INT_CMDRDY 1141 | MSDC_INT_RSPCRCERR 1142 | MSDC_INT_CMDTMO))) 1143 return done; 1144 1145 spin_lock_irqsave(&host->lock, flags); 1146 done = !host->cmd; 1147 host->cmd = NULL; 1148 spin_unlock_irqrestore(&host->lock, flags); 1149 1150 if (done) 1151 return true; 1152 1153 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1154 1155 if (cmd->flags & MMC_RSP_PRESENT) { 1156 if (cmd->flags & MMC_RSP_136) { 1157 rsp[0] = readl(host->base + SDC_RESP3); 1158 rsp[1] = readl(host->base + SDC_RESP2); 1159 rsp[2] = readl(host->base + SDC_RESP1); 1160 rsp[3] = readl(host->base + SDC_RESP0); 1161 } else { 1162 rsp[0] = readl(host->base + SDC_RESP0); 1163 } 1164 } 1165 1166 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 1167 if (events & MSDC_INT_CMDTMO || 1168 (cmd->opcode != MMC_SEND_TUNING_BLOCK && 1169 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)) 1170 /* 1171 * should not clear fifo/interrupt as the tune data 1172 * may have alreay come when cmd19/cmd21 gets response 1173 * CRC error. 1174 */ 1175 msdc_reset_hw(host); 1176 if (events & MSDC_INT_RSPCRCERR) { 1177 cmd->error = -EILSEQ; 1178 host->error |= REQ_CMD_EIO; 1179 } else if (events & MSDC_INT_CMDTMO) { 1180 cmd->error = -ETIMEDOUT; 1181 host->error |= REQ_CMD_TMO; 1182 } 1183 } 1184 if (cmd->error) 1185 dev_dbg(host->dev, 1186 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 1187 __func__, cmd->opcode, cmd->arg, rsp[0], 1188 cmd->error); 1189 1190 msdc_cmd_next(host, mrq, cmd); 1191 return true; 1192 } 1193 1194 /* It is the core layer's responsibility to ensure card status 1195 * is correct before issue a request. but host design do below 1196 * checks recommended. 1197 */ 1198 static inline bool msdc_cmd_is_ready(struct msdc_host *host, 1199 struct mmc_request *mrq, struct mmc_command *cmd) 1200 { 1201 /* The max busy time we can endure is 20ms */ 1202 unsigned long tmo = jiffies + msecs_to_jiffies(20); 1203 1204 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && 1205 time_before(jiffies, tmo)) 1206 cpu_relax(); 1207 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { 1208 dev_err(host->dev, "CMD bus busy detected\n"); 1209 host->error |= REQ_CMD_BUSY; 1210 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1211 return false; 1212 } 1213 1214 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 1215 tmo = jiffies + msecs_to_jiffies(20); 1216 /* R1B or with data, should check SDCBUSY */ 1217 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && 1218 time_before(jiffies, tmo)) 1219 cpu_relax(); 1220 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { 1221 dev_err(host->dev, "Controller busy detected\n"); 1222 host->error |= REQ_CMD_BUSY; 1223 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1224 return false; 1225 } 1226 } 1227 return true; 1228 } 1229 1230 static void msdc_start_command(struct msdc_host *host, 1231 struct mmc_request *mrq, struct mmc_command *cmd) 1232 { 1233 u32 rawcmd; 1234 unsigned long flags; 1235 1236 WARN_ON(host->cmd); 1237 host->cmd = cmd; 1238 1239 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1240 if (!msdc_cmd_is_ready(host, mrq, cmd)) 1241 return; 1242 1243 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 1244 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 1245 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 1246 msdc_reset_hw(host); 1247 } 1248 1249 cmd->error = 0; 1250 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 1251 1252 spin_lock_irqsave(&host->lock, flags); 1253 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1254 spin_unlock_irqrestore(&host->lock, flags); 1255 1256 writel(cmd->arg, host->base + SDC_ARG); 1257 writel(rawcmd, host->base + SDC_CMD); 1258 } 1259 1260 static void msdc_cmd_next(struct msdc_host *host, 1261 struct mmc_request *mrq, struct mmc_command *cmd) 1262 { 1263 if ((cmd->error && 1264 !(cmd->error == -EILSEQ && 1265 (cmd->opcode == MMC_SEND_TUNING_BLOCK || 1266 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) || 1267 (mrq->sbc && mrq->sbc->error)) 1268 msdc_request_done(host, mrq); 1269 else if (cmd == mrq->sbc) 1270 msdc_start_command(host, mrq, mrq->cmd); 1271 else if (!cmd->data) 1272 msdc_request_done(host, mrq); 1273 else 1274 msdc_start_data(host, mrq, cmd, cmd->data); 1275 } 1276 1277 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 1278 { 1279 struct msdc_host *host = mmc_priv(mmc); 1280 1281 host->error = 0; 1282 WARN_ON(host->mrq); 1283 host->mrq = mrq; 1284 1285 if (mrq->data) 1286 msdc_prepare_data(host, mrq); 1287 1288 /* if SBC is required, we have HW option and SW option. 1289 * if HW option is enabled, and SBC does not have "special" flags, 1290 * use HW option, otherwise use SW option 1291 */ 1292 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 1293 (mrq->sbc->arg & 0xFFFF0000))) 1294 msdc_start_command(host, mrq, mrq->sbc); 1295 else 1296 msdc_start_command(host, mrq, mrq->cmd); 1297 } 1298 1299 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 1300 { 1301 struct msdc_host *host = mmc_priv(mmc); 1302 struct mmc_data *data = mrq->data; 1303 1304 if (!data) 1305 return; 1306 1307 msdc_prepare_data(host, mrq); 1308 data->host_cookie |= MSDC_ASYNC_FLAG; 1309 } 1310 1311 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1312 int err) 1313 { 1314 struct msdc_host *host = mmc_priv(mmc); 1315 struct mmc_data *data; 1316 1317 data = mrq->data; 1318 if (!data) 1319 return; 1320 if (data->host_cookie) { 1321 data->host_cookie &= ~MSDC_ASYNC_FLAG; 1322 msdc_unprepare_data(host, mrq); 1323 } 1324 } 1325 1326 static void msdc_data_xfer_next(struct msdc_host *host, 1327 struct mmc_request *mrq, struct mmc_data *data) 1328 { 1329 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 1330 !mrq->sbc) 1331 msdc_start_command(host, mrq, mrq->stop); 1332 else 1333 msdc_request_done(host, mrq); 1334 } 1335 1336 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 1337 struct mmc_request *mrq, struct mmc_data *data) 1338 { 1339 struct mmc_command *stop = data->stop; 1340 unsigned long flags; 1341 bool done; 1342 unsigned int check_data = events & 1343 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 1344 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 1345 | MSDC_INT_DMA_PROTECT); 1346 1347 spin_lock_irqsave(&host->lock, flags); 1348 done = !host->data; 1349 if (check_data) 1350 host->data = NULL; 1351 spin_unlock_irqrestore(&host->lock, flags); 1352 1353 if (done) 1354 return true; 1355 1356 if (check_data || (stop && stop->error)) { 1357 dev_dbg(host->dev, "DMA status: 0x%8X\n", 1358 readl(host->base + MSDC_DMA_CFG)); 1359 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1360 1); 1361 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) 1362 cpu_relax(); 1363 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 1364 dev_dbg(host->dev, "DMA stop\n"); 1365 1366 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 1367 data->bytes_xfered = data->blocks * data->blksz; 1368 } else { 1369 dev_dbg(host->dev, "interrupt events: %x\n", events); 1370 msdc_reset_hw(host); 1371 host->error |= REQ_DAT_ERR; 1372 data->bytes_xfered = 0; 1373 1374 if (events & MSDC_INT_DATTMO) 1375 data->error = -ETIMEDOUT; 1376 else if (events & MSDC_INT_DATCRCERR) 1377 data->error = -EILSEQ; 1378 1379 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 1380 __func__, mrq->cmd->opcode, data->blocks); 1381 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 1382 (int)data->error, data->bytes_xfered); 1383 } 1384 1385 msdc_data_xfer_next(host, mrq, data); 1386 done = true; 1387 } 1388 return done; 1389 } 1390 1391 static void msdc_set_buswidth(struct msdc_host *host, u32 width) 1392 { 1393 u32 val = readl(host->base + SDC_CFG); 1394 1395 val &= ~SDC_CFG_BUSWIDTH; 1396 1397 switch (width) { 1398 default: 1399 case MMC_BUS_WIDTH_1: 1400 val |= (MSDC_BUS_1BITS << 16); 1401 break; 1402 case MMC_BUS_WIDTH_4: 1403 val |= (MSDC_BUS_4BITS << 16); 1404 break; 1405 case MMC_BUS_WIDTH_8: 1406 val |= (MSDC_BUS_8BITS << 16); 1407 break; 1408 } 1409 1410 writel(val, host->base + SDC_CFG); 1411 dev_dbg(host->dev, "Bus Width = %d", width); 1412 } 1413 1414 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 1415 { 1416 struct msdc_host *host = mmc_priv(mmc); 1417 int ret; 1418 1419 if (!IS_ERR(mmc->supply.vqmmc)) { 1420 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1421 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 1422 dev_err(host->dev, "Unsupported signal voltage!\n"); 1423 return -EINVAL; 1424 } 1425 1426 ret = mmc_regulator_set_vqmmc(mmc, ios); 1427 if (ret < 0) { 1428 dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1429 ret, ios->signal_voltage); 1430 return ret; 1431 } 1432 1433 /* Apply different pinctrl settings for different signal voltage */ 1434 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 1435 pinctrl_select_state(host->pinctrl, host->pins_uhs); 1436 else 1437 pinctrl_select_state(host->pinctrl, host->pins_default); 1438 } 1439 return 0; 1440 } 1441 1442 static int msdc_card_busy(struct mmc_host *mmc) 1443 { 1444 struct msdc_host *host = mmc_priv(mmc); 1445 u32 status = readl(host->base + MSDC_PS); 1446 1447 /* only check if data0 is low */ 1448 return !(status & BIT(16)); 1449 } 1450 1451 static void msdc_request_timeout(struct work_struct *work) 1452 { 1453 struct msdc_host *host = container_of(work, struct msdc_host, 1454 req_timeout.work); 1455 1456 /* simulate HW timeout status */ 1457 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 1458 if (host->mrq) { 1459 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 1460 host->mrq, host->mrq->cmd->opcode); 1461 if (host->cmd) { 1462 dev_err(host->dev, "%s: aborting cmd=%d\n", 1463 __func__, host->cmd->opcode); 1464 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 1465 host->cmd); 1466 } else if (host->data) { 1467 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 1468 __func__, host->mrq->cmd->opcode, 1469 host->data->blocks); 1470 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 1471 host->data); 1472 } 1473 } 1474 } 1475 1476 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb) 1477 { 1478 if (enb) { 1479 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1480 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1481 if (host->dev_comp->recheck_sdio_irq) 1482 msdc_recheck_sdio_irq(host); 1483 } else { 1484 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1485 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1486 } 1487 } 1488 1489 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) 1490 { 1491 unsigned long flags; 1492 struct msdc_host *host = mmc_priv(mmc); 1493 1494 spin_lock_irqsave(&host->lock, flags); 1495 __msdc_enable_sdio_irq(host, enb); 1496 spin_unlock_irqrestore(&host->lock, flags); 1497 1498 if (enb) 1499 pm_runtime_get_noresume(host->dev); 1500 else 1501 pm_runtime_put_noidle(host->dev); 1502 } 1503 1504 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) 1505 { 1506 struct mmc_host *mmc = mmc_from_priv(host); 1507 int cmd_err = 0, dat_err = 0; 1508 1509 if (intsts & MSDC_INT_RSPCRCERR) { 1510 cmd_err = -EILSEQ; 1511 dev_err(host->dev, "%s: CMD CRC ERR", __func__); 1512 } else if (intsts & MSDC_INT_CMDTMO) { 1513 cmd_err = -ETIMEDOUT; 1514 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); 1515 } 1516 1517 if (intsts & MSDC_INT_DATCRCERR) { 1518 dat_err = -EILSEQ; 1519 dev_err(host->dev, "%s: DATA CRC ERR", __func__); 1520 } else if (intsts & MSDC_INT_DATTMO) { 1521 dat_err = -ETIMEDOUT; 1522 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); 1523 } 1524 1525 if (cmd_err || dat_err) { 1526 dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", 1527 cmd_err, dat_err, intsts); 1528 } 1529 1530 return cqhci_irq(mmc, 0, cmd_err, dat_err); 1531 } 1532 1533 static irqreturn_t msdc_irq(int irq, void *dev_id) 1534 { 1535 struct msdc_host *host = (struct msdc_host *) dev_id; 1536 struct mmc_host *mmc = mmc_from_priv(host); 1537 1538 while (true) { 1539 unsigned long flags; 1540 struct mmc_request *mrq; 1541 struct mmc_command *cmd; 1542 struct mmc_data *data; 1543 u32 events, event_mask; 1544 1545 spin_lock_irqsave(&host->lock, flags); 1546 events = readl(host->base + MSDC_INT); 1547 event_mask = readl(host->base + MSDC_INTEN); 1548 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1549 __msdc_enable_sdio_irq(host, 0); 1550 /* clear interrupts */ 1551 writel(events & event_mask, host->base + MSDC_INT); 1552 1553 mrq = host->mrq; 1554 cmd = host->cmd; 1555 data = host->data; 1556 spin_unlock_irqrestore(&host->lock, flags); 1557 1558 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1559 sdio_signal_irq(mmc); 1560 1561 if ((events & event_mask) & MSDC_INT_CDSC) { 1562 if (host->internal_cd) 1563 mmc_detect_change(mmc, msecs_to_jiffies(20)); 1564 events &= ~MSDC_INT_CDSC; 1565 } 1566 1567 if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) 1568 break; 1569 1570 if ((mmc->caps2 & MMC_CAP2_CQE) && 1571 (events & MSDC_INT_CMDQ)) { 1572 msdc_cmdq_irq(host, events); 1573 /* clear interrupts */ 1574 writel(events, host->base + MSDC_INT); 1575 return IRQ_HANDLED; 1576 } 1577 1578 if (!mrq) { 1579 dev_err(host->dev, 1580 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 1581 __func__, events, event_mask); 1582 WARN_ON(1); 1583 break; 1584 } 1585 1586 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 1587 1588 if (cmd) 1589 msdc_cmd_done(host, events, mrq, cmd); 1590 else if (data) 1591 msdc_data_xfer_done(host, events, mrq, data); 1592 } 1593 1594 return IRQ_HANDLED; 1595 } 1596 1597 static void msdc_init_hw(struct msdc_host *host) 1598 { 1599 u32 val; 1600 u32 tune_reg = host->dev_comp->pad_tune_reg; 1601 1602 if (host->reset) { 1603 reset_control_assert(host->reset); 1604 usleep_range(10, 50); 1605 reset_control_deassert(host->reset); 1606 } 1607 1608 /* Configure to MMC/SD mode, clock free running */ 1609 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 1610 1611 /* Reset */ 1612 msdc_reset_hw(host); 1613 1614 /* Disable and clear all interrupts */ 1615 writel(0, host->base + MSDC_INTEN); 1616 val = readl(host->base + MSDC_INT); 1617 writel(val, host->base + MSDC_INT); 1618 1619 /* Configure card detection */ 1620 if (host->internal_cd) { 1621 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, 1622 DEFAULT_DEBOUNCE); 1623 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1624 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1625 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1626 } else { 1627 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1628 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1629 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1630 } 1631 1632 if (host->top_base) { 1633 writel(0, host->top_base + EMMC_TOP_CONTROL); 1634 writel(0, host->top_base + EMMC_TOP_CMD); 1635 } else { 1636 writel(0, host->base + tune_reg); 1637 } 1638 writel(0, host->base + MSDC_IOCON); 1639 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 1640 writel(0x403c0046, host->base + MSDC_PATCH_BIT); 1641 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 1642 writel(0xffff4089, host->base + MSDC_PATCH_BIT1); 1643 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1644 1645 if (host->dev_comp->stop_clk_fix) { 1646 sdr_set_field(host->base + MSDC_PATCH_BIT1, 1647 MSDC_PATCH_BIT1_STOP_DLY, 3); 1648 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1649 SDC_FIFO_CFG_WRVALIDSEL); 1650 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1651 SDC_FIFO_CFG_RDVALIDSEL); 1652 } 1653 1654 if (host->dev_comp->busy_check) 1655 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7)); 1656 1657 if (host->dev_comp->async_fifo) { 1658 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1659 MSDC_PB2_RESPWAIT, 3); 1660 if (host->dev_comp->enhance_rx) { 1661 if (host->top_base) 1662 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1663 SDC_RX_ENH_EN); 1664 else 1665 sdr_set_bits(host->base + SDC_ADV_CFG0, 1666 SDC_RX_ENHANCE_EN); 1667 } else { 1668 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1669 MSDC_PB2_RESPSTSENSEL, 2); 1670 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1671 MSDC_PB2_CRCSTSENSEL, 2); 1672 } 1673 /* use async fifo, then no need tune internal delay */ 1674 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, 1675 MSDC_PATCH_BIT2_CFGRESP); 1676 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1677 MSDC_PATCH_BIT2_CFGCRCSTS); 1678 } 1679 1680 if (host->dev_comp->support_64g) 1681 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1682 MSDC_PB2_SUPPORT_64G); 1683 if (host->dev_comp->data_tune) { 1684 if (host->top_base) { 1685 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1686 PAD_DAT_RD_RXDLY_SEL); 1687 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, 1688 DATA_K_VALUE_SEL); 1689 sdr_set_bits(host->top_base + EMMC_TOP_CMD, 1690 PAD_CMD_RD_RXDLY_SEL); 1691 } else { 1692 sdr_set_bits(host->base + tune_reg, 1693 MSDC_PAD_TUNE_RD_SEL | 1694 MSDC_PAD_TUNE_CMD_SEL); 1695 } 1696 } else { 1697 /* choose clock tune */ 1698 if (host->top_base) 1699 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1700 PAD_RXDLY_SEL); 1701 else 1702 sdr_set_bits(host->base + tune_reg, 1703 MSDC_PAD_TUNE_RXDLYSEL); 1704 } 1705 1706 /* Configure to enable SDIO mode. 1707 * it's must otherwise sdio cmd5 failed 1708 */ 1709 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1710 1711 /* Config SDIO device detect interrupt function */ 1712 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1713 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 1714 1715 /* Configure to default data timeout */ 1716 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 1717 1718 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 1719 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1720 if (host->top_base) { 1721 host->def_tune_para.emmc_top_control = 1722 readl(host->top_base + EMMC_TOP_CONTROL); 1723 host->def_tune_para.emmc_top_cmd = 1724 readl(host->top_base + EMMC_TOP_CMD); 1725 host->saved_tune_para.emmc_top_control = 1726 readl(host->top_base + EMMC_TOP_CONTROL); 1727 host->saved_tune_para.emmc_top_cmd = 1728 readl(host->top_base + EMMC_TOP_CMD); 1729 } else { 1730 host->def_tune_para.pad_tune = readl(host->base + tune_reg); 1731 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 1732 } 1733 dev_dbg(host->dev, "init hardware done!"); 1734 } 1735 1736 static void msdc_deinit_hw(struct msdc_host *host) 1737 { 1738 u32 val; 1739 1740 if (host->internal_cd) { 1741 /* Disabled card-detect */ 1742 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1743 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1744 } 1745 1746 /* Disable and clear all interrupts */ 1747 writel(0, host->base + MSDC_INTEN); 1748 1749 val = readl(host->base + MSDC_INT); 1750 writel(val, host->base + MSDC_INT); 1751 } 1752 1753 /* init gpd and bd list in msdc_drv_probe */ 1754 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 1755 { 1756 struct mt_gpdma_desc *gpd = dma->gpd; 1757 struct mt_bdma_desc *bd = dma->bd; 1758 dma_addr_t dma_addr; 1759 int i; 1760 1761 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 1762 1763 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); 1764 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 1765 /* gpd->next is must set for desc DMA 1766 * That's why must alloc 2 gpd structure. 1767 */ 1768 gpd->next = lower_32_bits(dma_addr); 1769 if (host->dev_comp->support_64g) 1770 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1771 1772 dma_addr = dma->bd_addr; 1773 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ 1774 if (host->dev_comp->support_64g) 1775 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; 1776 1777 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 1778 for (i = 0; i < (MAX_BD_NUM - 1); i++) { 1779 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); 1780 bd[i].next = lower_32_bits(dma_addr); 1781 if (host->dev_comp->support_64g) 1782 bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1783 } 1784 } 1785 1786 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1787 { 1788 struct msdc_host *host = mmc_priv(mmc); 1789 int ret; 1790 1791 msdc_set_buswidth(host, ios->bus_width); 1792 1793 /* Suspend/Resume will do power off/on */ 1794 switch (ios->power_mode) { 1795 case MMC_POWER_UP: 1796 if (!IS_ERR(mmc->supply.vmmc)) { 1797 msdc_init_hw(host); 1798 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1799 ios->vdd); 1800 if (ret) { 1801 dev_err(host->dev, "Failed to set vmmc power!\n"); 1802 return; 1803 } 1804 } 1805 break; 1806 case MMC_POWER_ON: 1807 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1808 ret = regulator_enable(mmc->supply.vqmmc); 1809 if (ret) 1810 dev_err(host->dev, "Failed to set vqmmc power!\n"); 1811 else 1812 host->vqmmc_enabled = true; 1813 } 1814 break; 1815 case MMC_POWER_OFF: 1816 if (!IS_ERR(mmc->supply.vmmc)) 1817 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1818 1819 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1820 regulator_disable(mmc->supply.vqmmc); 1821 host->vqmmc_enabled = false; 1822 } 1823 break; 1824 default: 1825 break; 1826 } 1827 1828 if (host->mclk != ios->clock || host->timing != ios->timing) 1829 msdc_set_mclk(host, ios->timing, ios->clock); 1830 } 1831 1832 static u32 test_delay_bit(u32 delay, u32 bit) 1833 { 1834 bit %= PAD_DELAY_MAX; 1835 return delay & (1 << bit); 1836 } 1837 1838 static int get_delay_len(u32 delay, u32 start_bit) 1839 { 1840 int i; 1841 1842 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 1843 if (test_delay_bit(delay, start_bit + i) == 0) 1844 return i; 1845 } 1846 return PAD_DELAY_MAX - start_bit; 1847 } 1848 1849 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 1850 { 1851 int start = 0, len = 0; 1852 int start_final = 0, len_final = 0; 1853 u8 final_phase = 0xff; 1854 struct msdc_delay_phase delay_phase = { 0, }; 1855 1856 if (delay == 0) { 1857 dev_err(host->dev, "phase error: [map:%x]\n", delay); 1858 delay_phase.final_phase = final_phase; 1859 return delay_phase; 1860 } 1861 1862 while (start < PAD_DELAY_MAX) { 1863 len = get_delay_len(delay, start); 1864 if (len_final < len) { 1865 start_final = start; 1866 len_final = len; 1867 } 1868 start += len ? len : 1; 1869 if (len >= 12 && start_final < 4) 1870 break; 1871 } 1872 1873 /* The rule is that to find the smallest delay cell */ 1874 if (start_final == 0) 1875 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 1876 else 1877 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 1878 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 1879 delay, len_final, final_phase); 1880 1881 delay_phase.maxlen = len_final; 1882 delay_phase.start = start_final; 1883 delay_phase.final_phase = final_phase; 1884 return delay_phase; 1885 } 1886 1887 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) 1888 { 1889 u32 tune_reg = host->dev_comp->pad_tune_reg; 1890 1891 if (host->top_base) 1892 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, 1893 value); 1894 else 1895 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1896 value); 1897 } 1898 1899 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) 1900 { 1901 u32 tune_reg = host->dev_comp->pad_tune_reg; 1902 1903 if (host->top_base) 1904 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, 1905 PAD_DAT_RD_RXDLY, value); 1906 else 1907 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, 1908 value); 1909 } 1910 1911 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 1912 { 1913 struct msdc_host *host = mmc_priv(mmc); 1914 u32 rise_delay = 0, fall_delay = 0; 1915 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1916 struct msdc_delay_phase internal_delay_phase; 1917 u8 final_delay, final_maxlen; 1918 u32 internal_delay = 0; 1919 u32 tune_reg = host->dev_comp->pad_tune_reg; 1920 int cmd_err; 1921 int i, j; 1922 1923 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 1924 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 1925 sdr_set_field(host->base + tune_reg, 1926 MSDC_PAD_TUNE_CMDRRDLY, 1927 host->hs200_cmd_int_delay); 1928 1929 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1930 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1931 msdc_set_cmd_delay(host, i); 1932 /* 1933 * Using the same parameters, it may sometimes pass the test, 1934 * but sometimes it may fail. To make sure the parameters are 1935 * more stable, we test each set of parameters 3 times. 1936 */ 1937 for (j = 0; j < 3; j++) { 1938 mmc_send_tuning(mmc, opcode, &cmd_err); 1939 if (!cmd_err) { 1940 rise_delay |= (1 << i); 1941 } else { 1942 rise_delay &= ~(1 << i); 1943 break; 1944 } 1945 } 1946 } 1947 final_rise_delay = get_best_delay(host, rise_delay); 1948 /* if rising edge has enough margin, then do not scan falling edge */ 1949 if (final_rise_delay.maxlen >= 12 || 1950 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1951 goto skip_fall; 1952 1953 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1954 for (i = 0; i < PAD_DELAY_MAX; i++) { 1955 msdc_set_cmd_delay(host, i); 1956 /* 1957 * Using the same parameters, it may sometimes pass the test, 1958 * but sometimes it may fail. To make sure the parameters are 1959 * more stable, we test each set of parameters 3 times. 1960 */ 1961 for (j = 0; j < 3; j++) { 1962 mmc_send_tuning(mmc, opcode, &cmd_err); 1963 if (!cmd_err) { 1964 fall_delay |= (1 << i); 1965 } else { 1966 fall_delay &= ~(1 << i); 1967 break; 1968 } 1969 } 1970 } 1971 final_fall_delay = get_best_delay(host, fall_delay); 1972 1973 skip_fall: 1974 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1975 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 1976 final_maxlen = final_fall_delay.maxlen; 1977 if (final_maxlen == final_rise_delay.maxlen) { 1978 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1979 final_delay = final_rise_delay.final_phase; 1980 } else { 1981 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1982 final_delay = final_fall_delay.final_phase; 1983 } 1984 msdc_set_cmd_delay(host, final_delay); 1985 1986 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) 1987 goto skip_internal; 1988 1989 for (i = 0; i < PAD_DELAY_MAX; i++) { 1990 sdr_set_field(host->base + tune_reg, 1991 MSDC_PAD_TUNE_CMDRRDLY, i); 1992 mmc_send_tuning(mmc, opcode, &cmd_err); 1993 if (!cmd_err) 1994 internal_delay |= (1 << i); 1995 } 1996 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 1997 internal_delay_phase = get_best_delay(host, internal_delay); 1998 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 1999 internal_delay_phase.final_phase); 2000 skip_internal: 2001 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 2002 return final_delay == 0xff ? -EIO : 0; 2003 } 2004 2005 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 2006 { 2007 struct msdc_host *host = mmc_priv(mmc); 2008 u32 cmd_delay = 0; 2009 struct msdc_delay_phase final_cmd_delay = { 0,}; 2010 u8 final_delay; 2011 int cmd_err; 2012 int i, j; 2013 2014 /* select EMMC50 PAD CMD tune */ 2015 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 2016 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); 2017 2018 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 2019 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 2020 sdr_set_field(host->base + MSDC_PAD_TUNE, 2021 MSDC_PAD_TUNE_CMDRRDLY, 2022 host->hs200_cmd_int_delay); 2023 2024 if (host->hs400_cmd_resp_sel_rising) 2025 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2026 else 2027 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2028 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2029 sdr_set_field(host->base + PAD_CMD_TUNE, 2030 PAD_CMD_TUNE_RX_DLY3, i); 2031 /* 2032 * Using the same parameters, it may sometimes pass the test, 2033 * but sometimes it may fail. To make sure the parameters are 2034 * more stable, we test each set of parameters 3 times. 2035 */ 2036 for (j = 0; j < 3; j++) { 2037 mmc_send_tuning(mmc, opcode, &cmd_err); 2038 if (!cmd_err) { 2039 cmd_delay |= (1 << i); 2040 } else { 2041 cmd_delay &= ~(1 << i); 2042 break; 2043 } 2044 } 2045 } 2046 final_cmd_delay = get_best_delay(host, cmd_delay); 2047 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 2048 final_cmd_delay.final_phase); 2049 final_delay = final_cmd_delay.final_phase; 2050 2051 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 2052 return final_delay == 0xff ? -EIO : 0; 2053 } 2054 2055 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 2056 { 2057 struct msdc_host *host = mmc_priv(mmc); 2058 u32 rise_delay = 0, fall_delay = 0; 2059 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2060 u8 final_delay, final_maxlen; 2061 int i, ret; 2062 2063 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2064 host->latch_ck); 2065 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2066 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2067 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2068 msdc_set_data_delay(host, i); 2069 ret = mmc_send_tuning(mmc, opcode, NULL); 2070 if (!ret) 2071 rise_delay |= (1 << i); 2072 } 2073 final_rise_delay = get_best_delay(host, rise_delay); 2074 /* if rising edge has enough margin, then do not scan falling edge */ 2075 if (final_rise_delay.maxlen >= 12 || 2076 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2077 goto skip_fall; 2078 2079 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2080 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2081 for (i = 0; i < PAD_DELAY_MAX; i++) { 2082 msdc_set_data_delay(host, i); 2083 ret = mmc_send_tuning(mmc, opcode, NULL); 2084 if (!ret) 2085 fall_delay |= (1 << i); 2086 } 2087 final_fall_delay = get_best_delay(host, fall_delay); 2088 2089 skip_fall: 2090 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2091 if (final_maxlen == final_rise_delay.maxlen) { 2092 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2093 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2094 final_delay = final_rise_delay.final_phase; 2095 } else { 2096 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2097 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2098 final_delay = final_fall_delay.final_phase; 2099 } 2100 msdc_set_data_delay(host, final_delay); 2101 2102 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 2103 return final_delay == 0xff ? -EIO : 0; 2104 } 2105 2106 /* 2107 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune 2108 * together, which can save the tuning time. 2109 */ 2110 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode) 2111 { 2112 struct msdc_host *host = mmc_priv(mmc); 2113 u32 rise_delay = 0, fall_delay = 0; 2114 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2115 u8 final_delay, final_maxlen; 2116 int i, ret; 2117 2118 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2119 host->latch_ck); 2120 2121 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2122 sdr_clr_bits(host->base + MSDC_IOCON, 2123 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2124 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2125 msdc_set_cmd_delay(host, i); 2126 msdc_set_data_delay(host, i); 2127 ret = mmc_send_tuning(mmc, opcode, NULL); 2128 if (!ret) 2129 rise_delay |= (1 << i); 2130 } 2131 final_rise_delay = get_best_delay(host, rise_delay); 2132 /* if rising edge has enough margin, then do not scan falling edge */ 2133 if (final_rise_delay.maxlen >= 12 || 2134 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2135 goto skip_fall; 2136 2137 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2138 sdr_set_bits(host->base + MSDC_IOCON, 2139 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2140 for (i = 0; i < PAD_DELAY_MAX; i++) { 2141 msdc_set_cmd_delay(host, i); 2142 msdc_set_data_delay(host, i); 2143 ret = mmc_send_tuning(mmc, opcode, NULL); 2144 if (!ret) 2145 fall_delay |= (1 << i); 2146 } 2147 final_fall_delay = get_best_delay(host, fall_delay); 2148 2149 skip_fall: 2150 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2151 if (final_maxlen == final_rise_delay.maxlen) { 2152 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2153 sdr_clr_bits(host->base + MSDC_IOCON, 2154 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2155 final_delay = final_rise_delay.final_phase; 2156 } else { 2157 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2158 sdr_set_bits(host->base + MSDC_IOCON, 2159 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2160 final_delay = final_fall_delay.final_phase; 2161 } 2162 2163 msdc_set_cmd_delay(host, final_delay); 2164 msdc_set_data_delay(host, final_delay); 2165 2166 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); 2167 return final_delay == 0xff ? -EIO : 0; 2168 } 2169 2170 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 2171 { 2172 struct msdc_host *host = mmc_priv(mmc); 2173 int ret; 2174 u32 tune_reg = host->dev_comp->pad_tune_reg; 2175 2176 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { 2177 ret = msdc_tune_together(mmc, opcode); 2178 if (host->hs400_mode) { 2179 sdr_clr_bits(host->base + MSDC_IOCON, 2180 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2181 msdc_set_data_delay(host, 0); 2182 } 2183 goto tune_done; 2184 } 2185 if (host->hs400_mode && 2186 host->dev_comp->hs400_tune) 2187 ret = hs400_tune_response(mmc, opcode); 2188 else 2189 ret = msdc_tune_response(mmc, opcode); 2190 if (ret == -EIO) { 2191 dev_err(host->dev, "Tune response fail!\n"); 2192 return ret; 2193 } 2194 if (host->hs400_mode == false) { 2195 ret = msdc_tune_data(mmc, opcode); 2196 if (ret == -EIO) 2197 dev_err(host->dev, "Tune data fail!\n"); 2198 } 2199 2200 tune_done: 2201 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 2202 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 2203 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2204 if (host->top_base) { 2205 host->saved_tune_para.emmc_top_control = readl(host->top_base + 2206 EMMC_TOP_CONTROL); 2207 host->saved_tune_para.emmc_top_cmd = readl(host->top_base + 2208 EMMC_TOP_CMD); 2209 } 2210 return ret; 2211 } 2212 2213 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 2214 { 2215 struct msdc_host *host = mmc_priv(mmc); 2216 host->hs400_mode = true; 2217 2218 if (host->top_base) 2219 writel(host->hs400_ds_delay, 2220 host->top_base + EMMC50_PAD_DS_TUNE); 2221 else 2222 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 2223 /* hs400 mode must set it to 0 */ 2224 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); 2225 /* to improve read performance, set outstanding to 2 */ 2226 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); 2227 2228 return 0; 2229 } 2230 2231 static void msdc_hw_reset(struct mmc_host *mmc) 2232 { 2233 struct msdc_host *host = mmc_priv(mmc); 2234 2235 sdr_set_bits(host->base + EMMC_IOCON, 1); 2236 udelay(10); /* 10us is enough */ 2237 sdr_clr_bits(host->base + EMMC_IOCON, 1); 2238 } 2239 2240 static void msdc_ack_sdio_irq(struct mmc_host *mmc) 2241 { 2242 unsigned long flags; 2243 struct msdc_host *host = mmc_priv(mmc); 2244 2245 spin_lock_irqsave(&host->lock, flags); 2246 __msdc_enable_sdio_irq(host, 1); 2247 spin_unlock_irqrestore(&host->lock, flags); 2248 } 2249 2250 static int msdc_get_cd(struct mmc_host *mmc) 2251 { 2252 struct msdc_host *host = mmc_priv(mmc); 2253 int val; 2254 2255 if (mmc->caps & MMC_CAP_NONREMOVABLE) 2256 return 1; 2257 2258 if (!host->internal_cd) 2259 return mmc_gpio_get_cd(mmc); 2260 2261 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; 2262 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) 2263 return !!val; 2264 else 2265 return !val; 2266 } 2267 2268 static void msdc_cqe_enable(struct mmc_host *mmc) 2269 { 2270 struct msdc_host *host = mmc_priv(mmc); 2271 2272 /* enable cmdq irq */ 2273 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); 2274 /* enable busy check */ 2275 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 2276 /* default write data / busy timeout 20s */ 2277 msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); 2278 /* default read data timeout 1s */ 2279 msdc_set_timeout(host, 1000000000ULL, 0); 2280 } 2281 2282 static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) 2283 { 2284 struct msdc_host *host = mmc_priv(mmc); 2285 2286 /* disable cmdq irq */ 2287 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); 2288 /* disable busy check */ 2289 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 2290 2291 if (recovery) { 2292 sdr_set_field(host->base + MSDC_DMA_CTRL, 2293 MSDC_DMA_CTRL_STOP, 1); 2294 msdc_reset_hw(host); 2295 } 2296 } 2297 2298 static void msdc_cqe_pre_enable(struct mmc_host *mmc) 2299 { 2300 struct cqhci_host *cq_host = mmc->cqe_private; 2301 u32 reg; 2302 2303 reg = cqhci_readl(cq_host, CQHCI_CFG); 2304 reg |= CQHCI_ENABLE; 2305 cqhci_writel(cq_host, reg, CQHCI_CFG); 2306 } 2307 2308 static void msdc_cqe_post_disable(struct mmc_host *mmc) 2309 { 2310 struct cqhci_host *cq_host = mmc->cqe_private; 2311 u32 reg; 2312 2313 reg = cqhci_readl(cq_host, CQHCI_CFG); 2314 reg &= ~CQHCI_ENABLE; 2315 cqhci_writel(cq_host, reg, CQHCI_CFG); 2316 } 2317 2318 static const struct mmc_host_ops mt_msdc_ops = { 2319 .post_req = msdc_post_req, 2320 .pre_req = msdc_pre_req, 2321 .request = msdc_ops_request, 2322 .set_ios = msdc_ops_set_ios, 2323 .get_ro = mmc_gpio_get_ro, 2324 .get_cd = msdc_get_cd, 2325 .enable_sdio_irq = msdc_enable_sdio_irq, 2326 .ack_sdio_irq = msdc_ack_sdio_irq, 2327 .start_signal_voltage_switch = msdc_ops_switch_volt, 2328 .card_busy = msdc_card_busy, 2329 .execute_tuning = msdc_execute_tuning, 2330 .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 2331 .hw_reset = msdc_hw_reset, 2332 }; 2333 2334 static const struct cqhci_host_ops msdc_cmdq_ops = { 2335 .enable = msdc_cqe_enable, 2336 .disable = msdc_cqe_disable, 2337 .pre_enable = msdc_cqe_pre_enable, 2338 .post_disable = msdc_cqe_post_disable, 2339 }; 2340 2341 static void msdc_of_property_parse(struct platform_device *pdev, 2342 struct msdc_host *host) 2343 { 2344 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", 2345 &host->latch_ck); 2346 2347 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 2348 &host->hs400_ds_delay); 2349 2350 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 2351 &host->hs200_cmd_int_delay); 2352 2353 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 2354 &host->hs400_cmd_int_delay); 2355 2356 if (of_property_read_bool(pdev->dev.of_node, 2357 "mediatek,hs400-cmd-resp-sel-rising")) 2358 host->hs400_cmd_resp_sel_rising = true; 2359 else 2360 host->hs400_cmd_resp_sel_rising = false; 2361 2362 if (of_property_read_bool(pdev->dev.of_node, 2363 "supports-cqe")) 2364 host->cqhci = true; 2365 else 2366 host->cqhci = false; 2367 } 2368 2369 static int msdc_drv_probe(struct platform_device *pdev) 2370 { 2371 struct mmc_host *mmc; 2372 struct msdc_host *host; 2373 struct resource *res; 2374 int ret; 2375 2376 if (!pdev->dev.of_node) { 2377 dev_err(&pdev->dev, "No DT found\n"); 2378 return -EINVAL; 2379 } 2380 2381 /* Allocate MMC host for this device */ 2382 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 2383 if (!mmc) 2384 return -ENOMEM; 2385 2386 host = mmc_priv(mmc); 2387 ret = mmc_of_parse(mmc); 2388 if (ret) 2389 goto host_free; 2390 2391 host->base = devm_platform_ioremap_resource(pdev, 0); 2392 if (IS_ERR(host->base)) { 2393 ret = PTR_ERR(host->base); 2394 goto host_free; 2395 } 2396 2397 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2398 if (res) { 2399 host->top_base = devm_ioremap_resource(&pdev->dev, res); 2400 if (IS_ERR(host->top_base)) 2401 host->top_base = NULL; 2402 } 2403 2404 ret = mmc_regulator_get_supply(mmc); 2405 if (ret) 2406 goto host_free; 2407 2408 host->src_clk = devm_clk_get(&pdev->dev, "source"); 2409 if (IS_ERR(host->src_clk)) { 2410 ret = PTR_ERR(host->src_clk); 2411 goto host_free; 2412 } 2413 2414 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 2415 if (IS_ERR(host->h_clk)) { 2416 ret = PTR_ERR(host->h_clk); 2417 goto host_free; 2418 } 2419 2420 host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); 2421 if (IS_ERR(host->bus_clk)) 2422 host->bus_clk = NULL; 2423 /*source clock control gate is optional clock*/ 2424 host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg"); 2425 if (IS_ERR(host->src_clk_cg)) 2426 host->src_clk_cg = NULL; 2427 2428 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 2429 "hrst"); 2430 if (IS_ERR(host->reset)) 2431 return PTR_ERR(host->reset); 2432 2433 host->irq = platform_get_irq(pdev, 0); 2434 if (host->irq < 0) { 2435 ret = -EINVAL; 2436 goto host_free; 2437 } 2438 2439 host->pinctrl = devm_pinctrl_get(&pdev->dev); 2440 if (IS_ERR(host->pinctrl)) { 2441 ret = PTR_ERR(host->pinctrl); 2442 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 2443 goto host_free; 2444 } 2445 2446 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 2447 if (IS_ERR(host->pins_default)) { 2448 ret = PTR_ERR(host->pins_default); 2449 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 2450 goto host_free; 2451 } 2452 2453 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 2454 if (IS_ERR(host->pins_uhs)) { 2455 ret = PTR_ERR(host->pins_uhs); 2456 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 2457 goto host_free; 2458 } 2459 2460 msdc_of_property_parse(pdev, host); 2461 2462 host->dev = &pdev->dev; 2463 host->dev_comp = of_device_get_match_data(&pdev->dev); 2464 host->src_clk_freq = clk_get_rate(host->src_clk); 2465 /* Set host parameters to mmc */ 2466 mmc->ops = &mt_msdc_ops; 2467 if (host->dev_comp->clk_div_bits == 8) 2468 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 2469 else 2470 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); 2471 2472 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && 2473 !mmc_can_gpio_cd(mmc) && 2474 host->dev_comp->use_internal_cd) { 2475 /* 2476 * Is removable but no GPIO declared, so 2477 * use internal functionality. 2478 */ 2479 host->internal_cd = true; 2480 } 2481 2482 if (mmc->caps & MMC_CAP_SDIO_IRQ) 2483 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2484 2485 mmc->caps |= MMC_CAP_CMD23; 2486 if (host->cqhci) 2487 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 2488 /* MMC core transfer sizes tunable parameters */ 2489 mmc->max_segs = MAX_BD_NUM; 2490 if (host->dev_comp->support_64g) 2491 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; 2492 else 2493 mmc->max_seg_size = BDMA_DESC_BUFLEN; 2494 mmc->max_blk_size = 2048; 2495 mmc->max_req_size = 512 * 1024; 2496 mmc->max_blk_count = mmc->max_req_size / 512; 2497 if (host->dev_comp->support_64g) 2498 host->dma_mask = DMA_BIT_MASK(36); 2499 else 2500 host->dma_mask = DMA_BIT_MASK(32); 2501 mmc_dev(mmc)->dma_mask = &host->dma_mask; 2502 2503 if (mmc->caps2 & MMC_CAP2_CQE) { 2504 host->cq_host = devm_kzalloc(mmc->parent, 2505 sizeof(*host->cq_host), 2506 GFP_KERNEL); 2507 if (!host->cq_host) { 2508 ret = -ENOMEM; 2509 goto host_free; 2510 } 2511 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 2512 host->cq_host->mmio = host->base + 0x800; 2513 host->cq_host->ops = &msdc_cmdq_ops; 2514 ret = cqhci_init(host->cq_host, mmc, true); 2515 if (ret) 2516 goto host_free; 2517 mmc->max_segs = 128; 2518 /* cqhci 16bit length */ 2519 /* 0 size, means 65536 so we don't have to -1 here */ 2520 mmc->max_seg_size = 64 * 1024; 2521 } 2522 2523 host->timeout_clks = 3 * 1048576; 2524 host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2525 2 * sizeof(struct mt_gpdma_desc), 2526 &host->dma.gpd_addr, GFP_KERNEL); 2527 host->dma.bd = dma_alloc_coherent(&pdev->dev, 2528 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2529 &host->dma.bd_addr, GFP_KERNEL); 2530 if (!host->dma.gpd || !host->dma.bd) { 2531 ret = -ENOMEM; 2532 goto release_mem; 2533 } 2534 msdc_init_gpd_bd(host, &host->dma); 2535 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 2536 spin_lock_init(&host->lock); 2537 2538 platform_set_drvdata(pdev, mmc); 2539 msdc_ungate_clock(host); 2540 msdc_init_hw(host); 2541 2542 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 2543 IRQF_TRIGGER_NONE, pdev->name, host); 2544 if (ret) 2545 goto release; 2546 2547 pm_runtime_set_active(host->dev); 2548 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 2549 pm_runtime_use_autosuspend(host->dev); 2550 pm_runtime_enable(host->dev); 2551 ret = mmc_add_host(mmc); 2552 2553 if (ret) 2554 goto end; 2555 2556 return 0; 2557 end: 2558 pm_runtime_disable(host->dev); 2559 release: 2560 platform_set_drvdata(pdev, NULL); 2561 msdc_deinit_hw(host); 2562 msdc_gate_clock(host); 2563 release_mem: 2564 if (host->dma.gpd) 2565 dma_free_coherent(&pdev->dev, 2566 2 * sizeof(struct mt_gpdma_desc), 2567 host->dma.gpd, host->dma.gpd_addr); 2568 if (host->dma.bd) 2569 dma_free_coherent(&pdev->dev, 2570 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2571 host->dma.bd, host->dma.bd_addr); 2572 host_free: 2573 mmc_free_host(mmc); 2574 2575 return ret; 2576 } 2577 2578 static int msdc_drv_remove(struct platform_device *pdev) 2579 { 2580 struct mmc_host *mmc; 2581 struct msdc_host *host; 2582 2583 mmc = platform_get_drvdata(pdev); 2584 host = mmc_priv(mmc); 2585 2586 pm_runtime_get_sync(host->dev); 2587 2588 platform_set_drvdata(pdev, NULL); 2589 mmc_remove_host(mmc); 2590 msdc_deinit_hw(host); 2591 msdc_gate_clock(host); 2592 2593 pm_runtime_disable(host->dev); 2594 pm_runtime_put_noidle(host->dev); 2595 dma_free_coherent(&pdev->dev, 2596 2 * sizeof(struct mt_gpdma_desc), 2597 host->dma.gpd, host->dma.gpd_addr); 2598 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2599 host->dma.bd, host->dma.bd_addr); 2600 2601 mmc_free_host(mmc); 2602 2603 return 0; 2604 } 2605 2606 #ifdef CONFIG_PM 2607 static void msdc_save_reg(struct msdc_host *host) 2608 { 2609 u32 tune_reg = host->dev_comp->pad_tune_reg; 2610 2611 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 2612 host->save_para.iocon = readl(host->base + MSDC_IOCON); 2613 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 2614 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 2615 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 2616 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); 2617 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 2618 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2619 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 2620 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); 2621 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); 2622 if (host->top_base) { 2623 host->save_para.emmc_top_control = 2624 readl(host->top_base + EMMC_TOP_CONTROL); 2625 host->save_para.emmc_top_cmd = 2626 readl(host->top_base + EMMC_TOP_CMD); 2627 host->save_para.emmc50_pad_ds_tune = 2628 readl(host->top_base + EMMC50_PAD_DS_TUNE); 2629 } else { 2630 host->save_para.pad_tune = readl(host->base + tune_reg); 2631 } 2632 } 2633 2634 static void msdc_restore_reg(struct msdc_host *host) 2635 { 2636 struct mmc_host *mmc = mmc_from_priv(host); 2637 u32 tune_reg = host->dev_comp->pad_tune_reg; 2638 2639 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 2640 writel(host->save_para.iocon, host->base + MSDC_IOCON); 2641 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 2642 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 2643 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 2644 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); 2645 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 2646 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 2647 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 2648 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); 2649 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); 2650 if (host->top_base) { 2651 writel(host->save_para.emmc_top_control, 2652 host->top_base + EMMC_TOP_CONTROL); 2653 writel(host->save_para.emmc_top_cmd, 2654 host->top_base + EMMC_TOP_CMD); 2655 writel(host->save_para.emmc50_pad_ds_tune, 2656 host->top_base + EMMC50_PAD_DS_TUNE); 2657 } else { 2658 writel(host->save_para.pad_tune, host->base + tune_reg); 2659 } 2660 2661 if (sdio_irq_claimed(mmc)) 2662 __msdc_enable_sdio_irq(host, 1); 2663 } 2664 2665 static int msdc_runtime_suspend(struct device *dev) 2666 { 2667 struct mmc_host *mmc = dev_get_drvdata(dev); 2668 struct msdc_host *host = mmc_priv(mmc); 2669 2670 msdc_save_reg(host); 2671 msdc_gate_clock(host); 2672 return 0; 2673 } 2674 2675 static int msdc_runtime_resume(struct device *dev) 2676 { 2677 struct mmc_host *mmc = dev_get_drvdata(dev); 2678 struct msdc_host *host = mmc_priv(mmc); 2679 2680 msdc_ungate_clock(host); 2681 msdc_restore_reg(host); 2682 return 0; 2683 } 2684 #endif 2685 2686 static const struct dev_pm_ops msdc_dev_pm_ops = { 2687 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2688 pm_runtime_force_resume) 2689 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 2690 }; 2691 2692 static struct platform_driver mt_msdc_driver = { 2693 .probe = msdc_drv_probe, 2694 .remove = msdc_drv_remove, 2695 .driver = { 2696 .name = "mtk-msdc", 2697 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 2698 .of_match_table = msdc_of_ids, 2699 .pm = &msdc_dev_pm_ops, 2700 }, 2701 }; 2702 2703 module_platform_driver(mt_msdc_driver); 2704 MODULE_LICENSE("GPL v2"); 2705 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 2706