120848903SChaotian Jing /* 220848903SChaotian Jing * Copyright (c) 2014-2015 MediaTek Inc. 320848903SChaotian Jing * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 420848903SChaotian Jing * 520848903SChaotian Jing * This program is free software; you can redistribute it and/or modify 620848903SChaotian Jing * it under the terms of the GNU General Public License version 2 as 720848903SChaotian Jing * published by the Free Software Foundation. 820848903SChaotian Jing * 920848903SChaotian Jing * This program is distributed in the hope that it will be useful, 1020848903SChaotian Jing * but WITHOUT ANY WARRANTY; without even the implied warranty of 1120848903SChaotian Jing * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1220848903SChaotian Jing * GNU General Public License for more details. 1320848903SChaotian Jing */ 1420848903SChaotian Jing 1520848903SChaotian Jing #include <linux/module.h> 1620848903SChaotian Jing #include <linux/clk.h> 1720848903SChaotian Jing #include <linux/delay.h> 1820848903SChaotian Jing #include <linux/dma-mapping.h> 1920848903SChaotian Jing #include <linux/ioport.h> 2020848903SChaotian Jing #include <linux/irq.h> 2120848903SChaotian Jing #include <linux/of_address.h> 2220848903SChaotian Jing #include <linux/of_irq.h> 2320848903SChaotian Jing #include <linux/of_gpio.h> 2420848903SChaotian Jing #include <linux/pinctrl/consumer.h> 2520848903SChaotian Jing #include <linux/platform_device.h> 264b8a43e9SChaotian Jing #include <linux/pm.h> 274b8a43e9SChaotian Jing #include <linux/pm_runtime.h> 2820848903SChaotian Jing #include <linux/regulator/consumer.h> 296397b7f5SChaotian Jing #include <linux/slab.h> 3020848903SChaotian Jing #include <linux/spinlock.h> 31b8789ec4SUlf Hansson #include <linux/interrupt.h> 3220848903SChaotian Jing 3320848903SChaotian Jing #include <linux/mmc/card.h> 3420848903SChaotian Jing #include <linux/mmc/core.h> 3520848903SChaotian Jing #include <linux/mmc/host.h> 3620848903SChaotian Jing #include <linux/mmc/mmc.h> 3720848903SChaotian Jing #include <linux/mmc/sd.h> 3820848903SChaotian Jing #include <linux/mmc/sdio.h> 398d53e412SChaotian Jing #include <linux/mmc/slot-gpio.h> 4020848903SChaotian Jing 4120848903SChaotian Jing #define MAX_BD_NUM 1024 4220848903SChaotian Jing 4320848903SChaotian Jing /*--------------------------------------------------------------------------*/ 4420848903SChaotian Jing /* Common Definition */ 4520848903SChaotian Jing /*--------------------------------------------------------------------------*/ 4620848903SChaotian Jing #define MSDC_BUS_1BITS 0x0 4720848903SChaotian Jing #define MSDC_BUS_4BITS 0x1 4820848903SChaotian Jing #define MSDC_BUS_8BITS 0x2 4920848903SChaotian Jing 5020848903SChaotian Jing #define MSDC_BURST_64B 0x6 5120848903SChaotian Jing 5220848903SChaotian Jing /*--------------------------------------------------------------------------*/ 5320848903SChaotian Jing /* Register Offset */ 5420848903SChaotian Jing /*--------------------------------------------------------------------------*/ 5520848903SChaotian Jing #define MSDC_CFG 0x0 5620848903SChaotian Jing #define MSDC_IOCON 0x04 5720848903SChaotian Jing #define MSDC_PS 0x08 5820848903SChaotian Jing #define MSDC_INT 0x0c 5920848903SChaotian Jing #define MSDC_INTEN 0x10 6020848903SChaotian Jing #define MSDC_FIFOCS 0x14 6120848903SChaotian Jing #define SDC_CFG 0x30 6220848903SChaotian Jing #define SDC_CMD 0x34 6320848903SChaotian Jing #define SDC_ARG 0x38 6420848903SChaotian Jing #define SDC_STS 0x3c 6520848903SChaotian Jing #define SDC_RESP0 0x40 6620848903SChaotian Jing #define SDC_RESP1 0x44 6720848903SChaotian Jing #define SDC_RESP2 0x48 6820848903SChaotian Jing #define SDC_RESP3 0x4c 6920848903SChaotian Jing #define SDC_BLK_NUM 0x50 70c9b5061eSChaotian Jing #define EMMC_IOCON 0x7c 7120848903SChaotian Jing #define SDC_ACMD_RESP 0x80 7220848903SChaotian Jing #define MSDC_DMA_SA 0x90 7320848903SChaotian Jing #define MSDC_DMA_CTRL 0x98 7420848903SChaotian Jing #define MSDC_DMA_CFG 0x9c 7520848903SChaotian Jing #define MSDC_PATCH_BIT 0xb0 7620848903SChaotian Jing #define MSDC_PATCH_BIT1 0xb4 7720848903SChaotian Jing #define MSDC_PAD_TUNE 0xec 786397b7f5SChaotian Jing #define PAD_DS_TUNE 0x188 791ede5cb8Syong mao #define PAD_CMD_TUNE 0x18c 806397b7f5SChaotian Jing #define EMMC50_CFG0 0x208 8120848903SChaotian Jing 8220848903SChaotian Jing /*--------------------------------------------------------------------------*/ 8320848903SChaotian Jing /* Register Mask */ 8420848903SChaotian Jing /*--------------------------------------------------------------------------*/ 8520848903SChaotian Jing 8620848903SChaotian Jing /* MSDC_CFG mask */ 8720848903SChaotian Jing #define MSDC_CFG_MODE (0x1 << 0) /* RW */ 8820848903SChaotian Jing #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ 8920848903SChaotian Jing #define MSDC_CFG_RST (0x1 << 2) /* RW */ 9020848903SChaotian Jing #define MSDC_CFG_PIO (0x1 << 3) /* RW */ 9120848903SChaotian Jing #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ 9220848903SChaotian Jing #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ 9320848903SChaotian Jing #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ 9420848903SChaotian Jing #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ 9520848903SChaotian Jing #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ 9620848903SChaotian Jing #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ 976397b7f5SChaotian Jing #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */ 9820848903SChaotian Jing 9920848903SChaotian Jing /* MSDC_IOCON mask */ 10020848903SChaotian Jing #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ 10120848903SChaotian Jing #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ 10220848903SChaotian Jing #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ 10320848903SChaotian Jing #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ 10420848903SChaotian Jing #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ 10520848903SChaotian Jing #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ 10620848903SChaotian Jing #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ 10720848903SChaotian Jing #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ 10820848903SChaotian Jing #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ 10920848903SChaotian Jing #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ 11020848903SChaotian Jing #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ 11120848903SChaotian Jing #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ 11220848903SChaotian Jing #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ 11320848903SChaotian Jing #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ 11420848903SChaotian Jing #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ 11520848903SChaotian Jing #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ 11620848903SChaotian Jing 11720848903SChaotian Jing /* MSDC_PS mask */ 11820848903SChaotian Jing #define MSDC_PS_CDEN (0x1 << 0) /* RW */ 11920848903SChaotian Jing #define MSDC_PS_CDSTS (0x1 << 1) /* R */ 12020848903SChaotian Jing #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ 12120848903SChaotian Jing #define MSDC_PS_DAT (0xff << 16) /* R */ 12220848903SChaotian Jing #define MSDC_PS_CMD (0x1 << 24) /* R */ 12320848903SChaotian Jing #define MSDC_PS_WP (0x1 << 31) /* R */ 12420848903SChaotian Jing 12520848903SChaotian Jing /* MSDC_INT mask */ 12620848903SChaotian Jing #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ 12720848903SChaotian Jing #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ 12820848903SChaotian Jing #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ 12920848903SChaotian Jing #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ 13020848903SChaotian Jing #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ 13120848903SChaotian Jing #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ 13220848903SChaotian Jing #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ 13320848903SChaotian Jing #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ 13420848903SChaotian Jing #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ 13520848903SChaotian Jing #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ 13620848903SChaotian Jing #define MSDC_INT_CSTA (0x1 << 11) /* R */ 13720848903SChaotian Jing #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ 13820848903SChaotian Jing #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ 13920848903SChaotian Jing #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ 14020848903SChaotian Jing #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ 14120848903SChaotian Jing #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ 14220848903SChaotian Jing #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ 14320848903SChaotian Jing #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ 14420848903SChaotian Jing #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ 14520848903SChaotian Jing 14620848903SChaotian Jing /* MSDC_INTEN mask */ 14720848903SChaotian Jing #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ 14820848903SChaotian Jing #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ 14920848903SChaotian Jing #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ 15020848903SChaotian Jing #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ 15120848903SChaotian Jing #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ 15220848903SChaotian Jing #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ 15320848903SChaotian Jing #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ 15420848903SChaotian Jing #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ 15520848903SChaotian Jing #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ 15620848903SChaotian Jing #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ 15720848903SChaotian Jing #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ 15820848903SChaotian Jing #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ 15920848903SChaotian Jing #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ 16020848903SChaotian Jing #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ 16120848903SChaotian Jing #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ 16220848903SChaotian Jing #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ 16320848903SChaotian Jing #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ 16420848903SChaotian Jing #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ 16520848903SChaotian Jing #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ 16620848903SChaotian Jing 16720848903SChaotian Jing /* MSDC_FIFOCS mask */ 16820848903SChaotian Jing #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 16920848903SChaotian Jing #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 17020848903SChaotian Jing #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ 17120848903SChaotian Jing 17220848903SChaotian Jing /* SDC_CFG mask */ 17320848903SChaotian Jing #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ 17420848903SChaotian Jing #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ 17520848903SChaotian Jing #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 17620848903SChaotian Jing #define SDC_CFG_SDIO (0x1 << 19) /* RW */ 17720848903SChaotian Jing #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 17820848903SChaotian Jing #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ 17920848903SChaotian Jing #define SDC_CFG_DTOC (0xff << 24) /* RW */ 18020848903SChaotian Jing 18120848903SChaotian Jing /* SDC_STS mask */ 18220848903SChaotian Jing #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ 18320848903SChaotian Jing #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 18420848903SChaotian Jing #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ 18520848903SChaotian Jing 18620848903SChaotian Jing /* MSDC_DMA_CTRL mask */ 18720848903SChaotian Jing #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ 18820848903SChaotian Jing #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ 18920848903SChaotian Jing #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ 19020848903SChaotian Jing #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ 19120848903SChaotian Jing #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ 19220848903SChaotian Jing #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ 19320848903SChaotian Jing 19420848903SChaotian Jing /* MSDC_DMA_CFG mask */ 19520848903SChaotian Jing #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ 19620848903SChaotian Jing #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ 19720848903SChaotian Jing #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ 19820848903SChaotian Jing #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ 19920848903SChaotian Jing #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ 20020848903SChaotian Jing 20120848903SChaotian Jing /* MSDC_PATCH_BIT mask */ 20220848903SChaotian Jing #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ 20320848903SChaotian Jing #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) 20420848903SChaotian Jing #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) 20520848903SChaotian Jing #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ 20620848903SChaotian Jing #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ 20720848903SChaotian Jing #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ 20820848903SChaotian Jing #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ 20920848903SChaotian Jing #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ 21020848903SChaotian Jing #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ 21120848903SChaotian Jing #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ 21220848903SChaotian Jing #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ 21320848903SChaotian Jing #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ 21420848903SChaotian Jing 2151ede5cb8Syong mao #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */ 2166397b7f5SChaotian Jing #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */ 2176397b7f5SChaotian Jing #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */ 2181ede5cb8Syong mao #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */ 2191ede5cb8Syong mao #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */ 2206397b7f5SChaotian Jing 2216397b7f5SChaotian Jing #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */ 2226397b7f5SChaotian Jing #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */ 2236397b7f5SChaotian Jing #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */ 2246397b7f5SChaotian Jing 2251ede5cb8Syong mao #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */ 2261ede5cb8Syong mao 2276397b7f5SChaotian Jing #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */ 2286397b7f5SChaotian Jing #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ 2296397b7f5SChaotian Jing #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ 2306397b7f5SChaotian Jing 23120848903SChaotian Jing #define REQ_CMD_EIO (0x1 << 0) 23220848903SChaotian Jing #define REQ_CMD_TMO (0x1 << 1) 23320848903SChaotian Jing #define REQ_DAT_ERR (0x1 << 2) 23420848903SChaotian Jing #define REQ_STOP_EIO (0x1 << 3) 23520848903SChaotian Jing #define REQ_STOP_TMO (0x1 << 4) 23620848903SChaotian Jing #define REQ_CMD_BUSY (0x1 << 5) 23720848903SChaotian Jing 23820848903SChaotian Jing #define MSDC_PREPARE_FLAG (0x1 << 0) 23920848903SChaotian Jing #define MSDC_ASYNC_FLAG (0x1 << 1) 24020848903SChaotian Jing #define MSDC_MMAP_FLAG (0x1 << 2) 24120848903SChaotian Jing 2424b8a43e9SChaotian Jing #define MTK_MMC_AUTOSUSPEND_DELAY 50 24320848903SChaotian Jing #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 24420848903SChaotian Jing #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 24520848903SChaotian Jing 2466397b7f5SChaotian Jing #define PAD_DELAY_MAX 32 /* PAD delay cells */ 24720848903SChaotian Jing /*--------------------------------------------------------------------------*/ 24820848903SChaotian Jing /* Descriptor Structure */ 24920848903SChaotian Jing /*--------------------------------------------------------------------------*/ 25020848903SChaotian Jing struct mt_gpdma_desc { 25120848903SChaotian Jing u32 gpd_info; 25220848903SChaotian Jing #define GPDMA_DESC_HWO (0x1 << 0) 25320848903SChaotian Jing #define GPDMA_DESC_BDP (0x1 << 1) 25420848903SChaotian Jing #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 25520848903SChaotian Jing #define GPDMA_DESC_INT (0x1 << 16) 25620848903SChaotian Jing u32 next; 25720848903SChaotian Jing u32 ptr; 25820848903SChaotian Jing u32 gpd_data_len; 25920848903SChaotian Jing #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 26020848903SChaotian Jing #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ 26120848903SChaotian Jing u32 arg; 26220848903SChaotian Jing u32 blknum; 26320848903SChaotian Jing u32 cmd; 26420848903SChaotian Jing }; 26520848903SChaotian Jing 26620848903SChaotian Jing struct mt_bdma_desc { 26720848903SChaotian Jing u32 bd_info; 26820848903SChaotian Jing #define BDMA_DESC_EOL (0x1 << 0) 26920848903SChaotian Jing #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 27020848903SChaotian Jing #define BDMA_DESC_BLKPAD (0x1 << 17) 27120848903SChaotian Jing #define BDMA_DESC_DWPAD (0x1 << 18) 27220848903SChaotian Jing u32 next; 27320848903SChaotian Jing u32 ptr; 27420848903SChaotian Jing u32 bd_data_len; 27520848903SChaotian Jing #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 27620848903SChaotian Jing }; 27720848903SChaotian Jing 27820848903SChaotian Jing struct msdc_dma { 27920848903SChaotian Jing struct scatterlist *sg; /* I/O scatter list */ 28020848903SChaotian Jing struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 28120848903SChaotian Jing struct mt_bdma_desc *bd; /* pointer to bd array */ 28220848903SChaotian Jing dma_addr_t gpd_addr; /* the physical address of gpd array */ 28320848903SChaotian Jing dma_addr_t bd_addr; /* the physical address of bd array */ 28420848903SChaotian Jing }; 28520848903SChaotian Jing 2864b8a43e9SChaotian Jing struct msdc_save_para { 2874b8a43e9SChaotian Jing u32 msdc_cfg; 2884b8a43e9SChaotian Jing u32 iocon; 2894b8a43e9SChaotian Jing u32 sdc_cfg; 2904b8a43e9SChaotian Jing u32 pad_tune; 2914b8a43e9SChaotian Jing u32 patch_bit0; 2924b8a43e9SChaotian Jing u32 patch_bit1; 2936397b7f5SChaotian Jing u32 pad_ds_tune; 2941ede5cb8Syong mao u32 pad_cmd_tune; 2956397b7f5SChaotian Jing u32 emmc50_cfg0; 2966397b7f5SChaotian Jing }; 2976397b7f5SChaotian Jing 29886beac37SChaotian Jing struct msdc_tune_para { 29986beac37SChaotian Jing u32 iocon; 30086beac37SChaotian Jing u32 pad_tune; 3011ede5cb8Syong mao u32 pad_cmd_tune; 30286beac37SChaotian Jing }; 30386beac37SChaotian Jing 3046397b7f5SChaotian Jing struct msdc_delay_phase { 3056397b7f5SChaotian Jing u8 maxlen; 3066397b7f5SChaotian Jing u8 start; 3076397b7f5SChaotian Jing u8 final_phase; 3084b8a43e9SChaotian Jing }; 3094b8a43e9SChaotian Jing 31020848903SChaotian Jing struct msdc_host { 31120848903SChaotian Jing struct device *dev; 31220848903SChaotian Jing struct mmc_host *mmc; /* mmc structure */ 31320848903SChaotian Jing int cmd_rsp; 31420848903SChaotian Jing 31520848903SChaotian Jing spinlock_t lock; 31620848903SChaotian Jing struct mmc_request *mrq; 31720848903SChaotian Jing struct mmc_command *cmd; 31820848903SChaotian Jing struct mmc_data *data; 31920848903SChaotian Jing int error; 32020848903SChaotian Jing 32120848903SChaotian Jing void __iomem *base; /* host base address */ 32220848903SChaotian Jing 32320848903SChaotian Jing struct msdc_dma dma; /* dma channel */ 32420848903SChaotian Jing u64 dma_mask; 32520848903SChaotian Jing 32620848903SChaotian Jing u32 timeout_ns; /* data timeout ns */ 32720848903SChaotian Jing u32 timeout_clks; /* data timeout clks */ 32820848903SChaotian Jing 32920848903SChaotian Jing struct pinctrl *pinctrl; 33020848903SChaotian Jing struct pinctrl_state *pins_default; 33120848903SChaotian Jing struct pinctrl_state *pins_uhs; 33220848903SChaotian Jing struct delayed_work req_timeout; 33320848903SChaotian Jing int irq; /* host interrupt */ 33420848903SChaotian Jing 33520848903SChaotian Jing struct clk *src_clk; /* msdc source clock */ 33620848903SChaotian Jing struct clk *h_clk; /* msdc h_clk */ 33720848903SChaotian Jing u32 mclk; /* mmc subsystem clock frequency */ 33820848903SChaotian Jing u32 src_clk_freq; /* source clock frequency */ 33920848903SChaotian Jing u32 sclk; /* SD/MS bus clock frequency */ 3406e622947SChaotian Jing unsigned char timing; 34120848903SChaotian Jing bool vqmmc_enabled; 3426397b7f5SChaotian Jing u32 hs400_ds_delay; 3431ede5cb8Syong mao u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 3441ede5cb8Syong mao u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 3451ede5cb8Syong mao bool hs400_cmd_resp_sel_rising; 3461ede5cb8Syong mao /* cmd response sample selection for HS400 */ 3475462ff39SChaotian Jing bool hs400_mode; /* current eMMC will run at hs400 mode */ 3484b8a43e9SChaotian Jing struct msdc_save_para save_para; /* used when gate HCLK */ 34986beac37SChaotian Jing struct msdc_tune_para def_tune_para; /* default tune setting */ 35086beac37SChaotian Jing struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 35120848903SChaotian Jing }; 35220848903SChaotian Jing 35320848903SChaotian Jing static void sdr_set_bits(void __iomem *reg, u32 bs) 35420848903SChaotian Jing { 35520848903SChaotian Jing u32 val = readl(reg); 35620848903SChaotian Jing 35720848903SChaotian Jing val |= bs; 35820848903SChaotian Jing writel(val, reg); 35920848903SChaotian Jing } 36020848903SChaotian Jing 36120848903SChaotian Jing static void sdr_clr_bits(void __iomem *reg, u32 bs) 36220848903SChaotian Jing { 36320848903SChaotian Jing u32 val = readl(reg); 36420848903SChaotian Jing 36520848903SChaotian Jing val &= ~bs; 36620848903SChaotian Jing writel(val, reg); 36720848903SChaotian Jing } 36820848903SChaotian Jing 36920848903SChaotian Jing static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 37020848903SChaotian Jing { 37120848903SChaotian Jing unsigned int tv = readl(reg); 37220848903SChaotian Jing 37320848903SChaotian Jing tv &= ~field; 37420848903SChaotian Jing tv |= ((val) << (ffs((unsigned int)field) - 1)); 37520848903SChaotian Jing writel(tv, reg); 37620848903SChaotian Jing } 37720848903SChaotian Jing 37820848903SChaotian Jing static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 37920848903SChaotian Jing { 38020848903SChaotian Jing unsigned int tv = readl(reg); 38120848903SChaotian Jing 38220848903SChaotian Jing *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 38320848903SChaotian Jing } 38420848903SChaotian Jing 38520848903SChaotian Jing static void msdc_reset_hw(struct msdc_host *host) 38620848903SChaotian Jing { 38720848903SChaotian Jing u32 val; 38820848903SChaotian Jing 38920848903SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 39020848903SChaotian Jing while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) 39120848903SChaotian Jing cpu_relax(); 39220848903SChaotian Jing 39320848903SChaotian Jing sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 39420848903SChaotian Jing while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) 39520848903SChaotian Jing cpu_relax(); 39620848903SChaotian Jing 39720848903SChaotian Jing val = readl(host->base + MSDC_INT); 39820848903SChaotian Jing writel(val, host->base + MSDC_INT); 39920848903SChaotian Jing } 40020848903SChaotian Jing 40120848903SChaotian Jing static void msdc_cmd_next(struct msdc_host *host, 40220848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd); 40320848903SChaotian Jing 404726a9aacSChaotian Jing static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 405726a9aacSChaotian Jing MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 406726a9aacSChaotian Jing MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 407726a9aacSChaotian Jing static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 40820848903SChaotian Jing MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 40920848903SChaotian Jing MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 41020848903SChaotian Jing 41120848903SChaotian Jing static u8 msdc_dma_calcs(u8 *buf, u32 len) 41220848903SChaotian Jing { 41320848903SChaotian Jing u32 i, sum = 0; 41420848903SChaotian Jing 41520848903SChaotian Jing for (i = 0; i < len; i++) 41620848903SChaotian Jing sum += buf[i]; 41720848903SChaotian Jing return 0xff - (u8) sum; 41820848903SChaotian Jing } 41920848903SChaotian Jing 42020848903SChaotian Jing static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 42120848903SChaotian Jing struct mmc_data *data) 42220848903SChaotian Jing { 42320848903SChaotian Jing unsigned int j, dma_len; 42420848903SChaotian Jing dma_addr_t dma_address; 42520848903SChaotian Jing u32 dma_ctrl; 42620848903SChaotian Jing struct scatterlist *sg; 42720848903SChaotian Jing struct mt_gpdma_desc *gpd; 42820848903SChaotian Jing struct mt_bdma_desc *bd; 42920848903SChaotian Jing 43020848903SChaotian Jing sg = data->sg; 43120848903SChaotian Jing 43220848903SChaotian Jing gpd = dma->gpd; 43320848903SChaotian Jing bd = dma->bd; 43420848903SChaotian Jing 43520848903SChaotian Jing /* modify gpd */ 43620848903SChaotian Jing gpd->gpd_info |= GPDMA_DESC_HWO; 43720848903SChaotian Jing gpd->gpd_info |= GPDMA_DESC_BDP; 43820848903SChaotian Jing /* need to clear first. use these bits to calc checksum */ 43920848903SChaotian Jing gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 44020848903SChaotian Jing gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 44120848903SChaotian Jing 44220848903SChaotian Jing /* modify bd */ 44320848903SChaotian Jing for_each_sg(data->sg, sg, data->sg_count, j) { 44420848903SChaotian Jing dma_address = sg_dma_address(sg); 44520848903SChaotian Jing dma_len = sg_dma_len(sg); 44620848903SChaotian Jing 44720848903SChaotian Jing /* init bd */ 44820848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 44920848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_DWPAD; 45020848903SChaotian Jing bd[j].ptr = (u32)dma_address; 45120848903SChaotian Jing bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 45220848903SChaotian Jing bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 45320848903SChaotian Jing 45420848903SChaotian Jing if (j == data->sg_count - 1) /* the last bd */ 45520848903SChaotian Jing bd[j].bd_info |= BDMA_DESC_EOL; 45620848903SChaotian Jing else 45720848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_EOL; 45820848903SChaotian Jing 45920848903SChaotian Jing /* checksume need to clear first */ 46020848903SChaotian Jing bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 46120848903SChaotian Jing bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 46220848903SChaotian Jing } 46320848903SChaotian Jing 46420848903SChaotian Jing sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 46520848903SChaotian Jing dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 46620848903SChaotian Jing dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 46720848903SChaotian Jing dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); 46820848903SChaotian Jing writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 46920848903SChaotian Jing writel((u32)dma->gpd_addr, host->base + MSDC_DMA_SA); 47020848903SChaotian Jing } 47120848903SChaotian Jing 47220848903SChaotian Jing static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq) 47320848903SChaotian Jing { 47420848903SChaotian Jing struct mmc_data *data = mrq->data; 47520848903SChaotian Jing 47620848903SChaotian Jing if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 47720848903SChaotian Jing data->host_cookie |= MSDC_PREPARE_FLAG; 47820848903SChaotian Jing data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 479feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 48020848903SChaotian Jing } 48120848903SChaotian Jing } 48220848903SChaotian Jing 48320848903SChaotian Jing static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) 48420848903SChaotian Jing { 48520848903SChaotian Jing struct mmc_data *data = mrq->data; 48620848903SChaotian Jing 48720848903SChaotian Jing if (data->host_cookie & MSDC_ASYNC_FLAG) 48820848903SChaotian Jing return; 48920848903SChaotian Jing 49020848903SChaotian Jing if (data->host_cookie & MSDC_PREPARE_FLAG) { 49120848903SChaotian Jing dma_unmap_sg(host->dev, data->sg, data->sg_len, 492feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 49320848903SChaotian Jing data->host_cookie &= ~MSDC_PREPARE_FLAG; 49420848903SChaotian Jing } 49520848903SChaotian Jing } 49620848903SChaotian Jing 49720848903SChaotian Jing /* clock control primitives */ 49820848903SChaotian Jing static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) 49920848903SChaotian Jing { 50020848903SChaotian Jing u32 timeout, clk_ns; 50120848903SChaotian Jing u32 mode = 0; 50220848903SChaotian Jing 50320848903SChaotian Jing host->timeout_ns = ns; 50420848903SChaotian Jing host->timeout_clks = clks; 50520848903SChaotian Jing if (host->sclk == 0) { 50620848903SChaotian Jing timeout = 0; 50720848903SChaotian Jing } else { 50820848903SChaotian Jing clk_ns = 1000000000UL / host->sclk; 50920848903SChaotian Jing timeout = (ns + clk_ns - 1) / clk_ns + clks; 51020848903SChaotian Jing /* in 1048576 sclk cycle unit */ 51120848903SChaotian Jing timeout = (timeout + (0x1 << 20) - 1) >> 20; 51220848903SChaotian Jing sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode); 51320848903SChaotian Jing /*DDR mode will double the clk cycles for data timeout */ 51420848903SChaotian Jing timeout = mode >= 2 ? timeout * 2 : timeout; 51520848903SChaotian Jing timeout = timeout > 1 ? timeout - 1 : 0; 51620848903SChaotian Jing timeout = timeout > 255 ? 255 : timeout; 51720848903SChaotian Jing } 51820848903SChaotian Jing sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout); 51920848903SChaotian Jing } 52020848903SChaotian Jing 52120848903SChaotian Jing static void msdc_gate_clock(struct msdc_host *host) 52220848903SChaotian Jing { 52320848903SChaotian Jing clk_disable_unprepare(host->src_clk); 52420848903SChaotian Jing clk_disable_unprepare(host->h_clk); 52520848903SChaotian Jing } 52620848903SChaotian Jing 52720848903SChaotian Jing static void msdc_ungate_clock(struct msdc_host *host) 52820848903SChaotian Jing { 52920848903SChaotian Jing clk_prepare_enable(host->h_clk); 53020848903SChaotian Jing clk_prepare_enable(host->src_clk); 53120848903SChaotian Jing while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 53220848903SChaotian Jing cpu_relax(); 53320848903SChaotian Jing } 53420848903SChaotian Jing 5356e622947SChaotian Jing static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 53620848903SChaotian Jing { 53720848903SChaotian Jing u32 mode; 53820848903SChaotian Jing u32 flags; 53920848903SChaotian Jing u32 div; 54020848903SChaotian Jing u32 sclk; 54120848903SChaotian Jing 54220848903SChaotian Jing if (!hz) { 54320848903SChaotian Jing dev_dbg(host->dev, "set mclk to 0\n"); 54420848903SChaotian Jing host->mclk = 0; 54520848903SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 54620848903SChaotian Jing return; 54720848903SChaotian Jing } 54820848903SChaotian Jing 54920848903SChaotian Jing flags = readl(host->base + MSDC_INTEN); 55020848903SChaotian Jing sdr_clr_bits(host->base + MSDC_INTEN, flags); 5516397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 5526e622947SChaotian Jing if (timing == MMC_TIMING_UHS_DDR50 || 5536397b7f5SChaotian Jing timing == MMC_TIMING_MMC_DDR52 || 5546397b7f5SChaotian Jing timing == MMC_TIMING_MMC_HS400) { 5556397b7f5SChaotian Jing if (timing == MMC_TIMING_MMC_HS400) 5566397b7f5SChaotian Jing mode = 0x3; 5576397b7f5SChaotian Jing else 55820848903SChaotian Jing mode = 0x2; /* ddr mode and use divisor */ 5596397b7f5SChaotian Jing 56020848903SChaotian Jing if (hz >= (host->src_clk_freq >> 2)) { 56120848903SChaotian Jing div = 0; /* mean div = 1/4 */ 56220848903SChaotian Jing sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 56320848903SChaotian Jing } else { 56420848903SChaotian Jing div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 56520848903SChaotian Jing sclk = (host->src_clk_freq >> 2) / div; 56620848903SChaotian Jing div = (div >> 1); 56720848903SChaotian Jing } 5686397b7f5SChaotian Jing 5696397b7f5SChaotian Jing if (timing == MMC_TIMING_MMC_HS400 && 5706397b7f5SChaotian Jing hz >= (host->src_clk_freq >> 1)) { 5716397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, 5726397b7f5SChaotian Jing MSDC_CFG_HS400_CK_MODE); 5736397b7f5SChaotian Jing sclk = host->src_clk_freq >> 1; 5746397b7f5SChaotian Jing div = 0; /* div is ignore when bit18 is set */ 5756397b7f5SChaotian Jing } 57620848903SChaotian Jing } else if (hz >= host->src_clk_freq) { 57720848903SChaotian Jing mode = 0x1; /* no divisor */ 57820848903SChaotian Jing div = 0; 57920848903SChaotian Jing sclk = host->src_clk_freq; 58020848903SChaotian Jing } else { 58120848903SChaotian Jing mode = 0x0; /* use divisor */ 58220848903SChaotian Jing if (hz >= (host->src_clk_freq >> 1)) { 58320848903SChaotian Jing div = 0; /* mean div = 1/2 */ 58420848903SChaotian Jing sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 58520848903SChaotian Jing } else { 58620848903SChaotian Jing div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 58720848903SChaotian Jing sclk = (host->src_clk_freq >> 2) / div; 58820848903SChaotian Jing } 58920848903SChaotian Jing } 59020848903SChaotian Jing sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 59140ceda09Syong mao (mode << 8) | div); 59220848903SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 59320848903SChaotian Jing while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 59420848903SChaotian Jing cpu_relax(); 59520848903SChaotian Jing host->sclk = sclk; 59620848903SChaotian Jing host->mclk = hz; 5976e622947SChaotian Jing host->timing = timing; 59820848903SChaotian Jing /* need because clk changed. */ 59920848903SChaotian Jing msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 60020848903SChaotian Jing sdr_set_bits(host->base + MSDC_INTEN, flags); 60120848903SChaotian Jing 60286beac37SChaotian Jing /* 60386beac37SChaotian Jing * mmc_select_hs400() will drop to 50Mhz and High speed mode, 60486beac37SChaotian Jing * tune result of hs200/200Mhz is not suitable for 50Mhz 60586beac37SChaotian Jing */ 60686beac37SChaotian Jing if (host->sclk <= 52000000) { 60786beac37SChaotian Jing writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 60886beac37SChaotian Jing writel(host->def_tune_para.pad_tune, host->base + MSDC_PAD_TUNE); 60986beac37SChaotian Jing } else { 61086beac37SChaotian Jing writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 61186beac37SChaotian Jing writel(host->saved_tune_para.pad_tune, host->base + MSDC_PAD_TUNE); 6121ede5cb8Syong mao writel(host->saved_tune_para.pad_cmd_tune, 6131ede5cb8Syong mao host->base + PAD_CMD_TUNE); 61486beac37SChaotian Jing } 61586beac37SChaotian Jing 6161ede5cb8Syong mao if (timing == MMC_TIMING_MMC_HS400) 6171ede5cb8Syong mao sdr_set_field(host->base + PAD_CMD_TUNE, 6181ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, 6191ede5cb8Syong mao host->hs400_cmd_int_delay); 6206e622947SChaotian Jing dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->sclk, timing); 62120848903SChaotian Jing } 62220848903SChaotian Jing 62320848903SChaotian Jing static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 62420848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 62520848903SChaotian Jing { 62620848903SChaotian Jing u32 resp; 62720848903SChaotian Jing 62820848903SChaotian Jing switch (mmc_resp_type(cmd)) { 62920848903SChaotian Jing /* Actually, R1, R5, R6, R7 are the same */ 63020848903SChaotian Jing case MMC_RSP_R1: 63120848903SChaotian Jing resp = 0x1; 63220848903SChaotian Jing break; 63320848903SChaotian Jing case MMC_RSP_R1B: 63420848903SChaotian Jing resp = 0x7; 63520848903SChaotian Jing break; 63620848903SChaotian Jing case MMC_RSP_R2: 63720848903SChaotian Jing resp = 0x2; 63820848903SChaotian Jing break; 63920848903SChaotian Jing case MMC_RSP_R3: 64020848903SChaotian Jing resp = 0x3; 64120848903SChaotian Jing break; 64220848903SChaotian Jing case MMC_RSP_NONE: 64320848903SChaotian Jing default: 64420848903SChaotian Jing resp = 0x0; 64520848903SChaotian Jing break; 64620848903SChaotian Jing } 64720848903SChaotian Jing 64820848903SChaotian Jing return resp; 64920848903SChaotian Jing } 65020848903SChaotian Jing 65120848903SChaotian Jing static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 65220848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 65320848903SChaotian Jing { 65420848903SChaotian Jing /* rawcmd : 65520848903SChaotian Jing * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 65620848903SChaotian Jing * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 65720848903SChaotian Jing */ 65820848903SChaotian Jing u32 opcode = cmd->opcode; 65920848903SChaotian Jing u32 resp = msdc_cmd_find_resp(host, mrq, cmd); 66020848903SChaotian Jing u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 66120848903SChaotian Jing 66220848903SChaotian Jing host->cmd_rsp = resp; 66320848903SChaotian Jing 66420848903SChaotian Jing if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 66520848903SChaotian Jing opcode == MMC_STOP_TRANSMISSION) 66620848903SChaotian Jing rawcmd |= (0x1 << 14); 66720848903SChaotian Jing else if (opcode == SD_SWITCH_VOLTAGE) 66820848903SChaotian Jing rawcmd |= (0x1 << 30); 66920848903SChaotian Jing else if (opcode == SD_APP_SEND_SCR || 67020848903SChaotian Jing opcode == SD_APP_SEND_NUM_WR_BLKS || 67120848903SChaotian Jing (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 67220848903SChaotian Jing (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 67320848903SChaotian Jing (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 67420848903SChaotian Jing rawcmd |= (0x1 << 11); 67520848903SChaotian Jing 67620848903SChaotian Jing if (cmd->data) { 67720848903SChaotian Jing struct mmc_data *data = cmd->data; 67820848903SChaotian Jing 67920848903SChaotian Jing if (mmc_op_multi(opcode)) { 68020848903SChaotian Jing if (mmc_card_mmc(host->mmc->card) && mrq->sbc && 68120848903SChaotian Jing !(mrq->sbc->arg & 0xFFFF0000)) 68220848903SChaotian Jing rawcmd |= 0x2 << 28; /* AutoCMD23 */ 68320848903SChaotian Jing } 68420848903SChaotian Jing 68520848903SChaotian Jing rawcmd |= ((data->blksz & 0xFFF) << 16); 68620848903SChaotian Jing if (data->flags & MMC_DATA_WRITE) 68720848903SChaotian Jing rawcmd |= (0x1 << 13); 68820848903SChaotian Jing if (data->blocks > 1) 68920848903SChaotian Jing rawcmd |= (0x2 << 11); 69020848903SChaotian Jing else 69120848903SChaotian Jing rawcmd |= (0x1 << 11); 69220848903SChaotian Jing /* Always use dma mode */ 69320848903SChaotian Jing sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 69420848903SChaotian Jing 69520848903SChaotian Jing if (host->timeout_ns != data->timeout_ns || 69620848903SChaotian Jing host->timeout_clks != data->timeout_clks) 69720848903SChaotian Jing msdc_set_timeout(host, data->timeout_ns, 69820848903SChaotian Jing data->timeout_clks); 69920848903SChaotian Jing 70020848903SChaotian Jing writel(data->blocks, host->base + SDC_BLK_NUM); 70120848903SChaotian Jing } 70220848903SChaotian Jing return rawcmd; 70320848903SChaotian Jing } 70420848903SChaotian Jing 70520848903SChaotian Jing static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, 70620848903SChaotian Jing struct mmc_command *cmd, struct mmc_data *data) 70720848903SChaotian Jing { 70820848903SChaotian Jing bool read; 70920848903SChaotian Jing 71020848903SChaotian Jing WARN_ON(host->data); 71120848903SChaotian Jing host->data = data; 71220848903SChaotian Jing read = data->flags & MMC_DATA_READ; 71320848903SChaotian Jing 71420848903SChaotian Jing mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 71520848903SChaotian Jing msdc_dma_setup(host, &host->dma, data); 71620848903SChaotian Jing sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 71720848903SChaotian Jing sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 71820848903SChaotian Jing dev_dbg(host->dev, "DMA start\n"); 71920848903SChaotian Jing dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 72020848903SChaotian Jing __func__, cmd->opcode, data->blocks, read); 72120848903SChaotian Jing } 72220848903SChaotian Jing 72320848903SChaotian Jing static int msdc_auto_cmd_done(struct msdc_host *host, int events, 72420848903SChaotian Jing struct mmc_command *cmd) 72520848903SChaotian Jing { 72620848903SChaotian Jing u32 *rsp = cmd->resp; 72720848903SChaotian Jing 72820848903SChaotian Jing rsp[0] = readl(host->base + SDC_ACMD_RESP); 72920848903SChaotian Jing 73020848903SChaotian Jing if (events & MSDC_INT_ACMDRDY) { 73120848903SChaotian Jing cmd->error = 0; 73220848903SChaotian Jing } else { 73320848903SChaotian Jing msdc_reset_hw(host); 73420848903SChaotian Jing if (events & MSDC_INT_ACMDCRCERR) { 73520848903SChaotian Jing cmd->error = -EILSEQ; 73620848903SChaotian Jing host->error |= REQ_STOP_EIO; 73720848903SChaotian Jing } else if (events & MSDC_INT_ACMDTMO) { 73820848903SChaotian Jing cmd->error = -ETIMEDOUT; 73920848903SChaotian Jing host->error |= REQ_STOP_TMO; 74020848903SChaotian Jing } 74120848903SChaotian Jing dev_err(host->dev, 74220848903SChaotian Jing "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 74320848903SChaotian Jing __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 74420848903SChaotian Jing } 74520848903SChaotian Jing return cmd->error; 74620848903SChaotian Jing } 74720848903SChaotian Jing 74820848903SChaotian Jing static void msdc_track_cmd_data(struct msdc_host *host, 74920848903SChaotian Jing struct mmc_command *cmd, struct mmc_data *data) 75020848903SChaotian Jing { 75120848903SChaotian Jing if (host->error) 75220848903SChaotian Jing dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 75320848903SChaotian Jing __func__, cmd->opcode, cmd->arg, host->error); 75420848903SChaotian Jing } 75520848903SChaotian Jing 75620848903SChaotian Jing static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 75720848903SChaotian Jing { 75820848903SChaotian Jing unsigned long flags; 75920848903SChaotian Jing bool ret; 76020848903SChaotian Jing 76120848903SChaotian Jing ret = cancel_delayed_work(&host->req_timeout); 76220848903SChaotian Jing if (!ret) { 76320848903SChaotian Jing /* delay work already running */ 76420848903SChaotian Jing return; 76520848903SChaotian Jing } 76620848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 76720848903SChaotian Jing host->mrq = NULL; 76820848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 76920848903SChaotian Jing 77020848903SChaotian Jing msdc_track_cmd_data(host, mrq->cmd, mrq->data); 77120848903SChaotian Jing if (mrq->data) 77220848903SChaotian Jing msdc_unprepare_data(host, mrq); 77320848903SChaotian Jing mmc_request_done(host->mmc, mrq); 77420848903SChaotian Jing } 77520848903SChaotian Jing 77620848903SChaotian Jing /* returns true if command is fully handled; returns false otherwise */ 77720848903SChaotian Jing static bool msdc_cmd_done(struct msdc_host *host, int events, 77820848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 77920848903SChaotian Jing { 78020848903SChaotian Jing bool done = false; 78120848903SChaotian Jing bool sbc_error; 78220848903SChaotian Jing unsigned long flags; 78320848903SChaotian Jing u32 *rsp = cmd->resp; 78420848903SChaotian Jing 78520848903SChaotian Jing if (mrq->sbc && cmd == mrq->cmd && 78620848903SChaotian Jing (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 78720848903SChaotian Jing | MSDC_INT_ACMDTMO))) 78820848903SChaotian Jing msdc_auto_cmd_done(host, events, mrq->sbc); 78920848903SChaotian Jing 79020848903SChaotian Jing sbc_error = mrq->sbc && mrq->sbc->error; 79120848903SChaotian Jing 79220848903SChaotian Jing if (!sbc_error && !(events & (MSDC_INT_CMDRDY 79320848903SChaotian Jing | MSDC_INT_RSPCRCERR 79420848903SChaotian Jing | MSDC_INT_CMDTMO))) 79520848903SChaotian Jing return done; 79620848903SChaotian Jing 79720848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 79820848903SChaotian Jing done = !host->cmd; 79920848903SChaotian Jing host->cmd = NULL; 80020848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 80120848903SChaotian Jing 80220848903SChaotian Jing if (done) 80320848903SChaotian Jing return true; 80420848903SChaotian Jing 805726a9aacSChaotian Jing sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 80620848903SChaotian Jing 80720848903SChaotian Jing if (cmd->flags & MMC_RSP_PRESENT) { 80820848903SChaotian Jing if (cmd->flags & MMC_RSP_136) { 80920848903SChaotian Jing rsp[0] = readl(host->base + SDC_RESP3); 81020848903SChaotian Jing rsp[1] = readl(host->base + SDC_RESP2); 81120848903SChaotian Jing rsp[2] = readl(host->base + SDC_RESP1); 81220848903SChaotian Jing rsp[3] = readl(host->base + SDC_RESP0); 81320848903SChaotian Jing } else { 81420848903SChaotian Jing rsp[0] = readl(host->base + SDC_RESP0); 81520848903SChaotian Jing } 81620848903SChaotian Jing } 81720848903SChaotian Jing 81820848903SChaotian Jing if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 819ddc71387SChaotian Jing if (cmd->opcode != MMC_SEND_TUNING_BLOCK && 820ddc71387SChaotian Jing cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200) 821ddc71387SChaotian Jing /* 822ddc71387SChaotian Jing * should not clear fifo/interrupt as the tune data 823ddc71387SChaotian Jing * may have alreay come. 824ddc71387SChaotian Jing */ 82520848903SChaotian Jing msdc_reset_hw(host); 82620848903SChaotian Jing if (events & MSDC_INT_RSPCRCERR) { 82720848903SChaotian Jing cmd->error = -EILSEQ; 82820848903SChaotian Jing host->error |= REQ_CMD_EIO; 82920848903SChaotian Jing } else if (events & MSDC_INT_CMDTMO) { 83020848903SChaotian Jing cmd->error = -ETIMEDOUT; 83120848903SChaotian Jing host->error |= REQ_CMD_TMO; 83220848903SChaotian Jing } 83320848903SChaotian Jing } 83420848903SChaotian Jing if (cmd->error) 83520848903SChaotian Jing dev_dbg(host->dev, 83620848903SChaotian Jing "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 83720848903SChaotian Jing __func__, cmd->opcode, cmd->arg, rsp[0], 83820848903SChaotian Jing cmd->error); 83920848903SChaotian Jing 84020848903SChaotian Jing msdc_cmd_next(host, mrq, cmd); 84120848903SChaotian Jing return true; 84220848903SChaotian Jing } 84320848903SChaotian Jing 84420848903SChaotian Jing /* It is the core layer's responsibility to ensure card status 84520848903SChaotian Jing * is correct before issue a request. but host design do below 84620848903SChaotian Jing * checks recommended. 84720848903SChaotian Jing */ 84820848903SChaotian Jing static inline bool msdc_cmd_is_ready(struct msdc_host *host, 84920848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 85020848903SChaotian Jing { 85120848903SChaotian Jing /* The max busy time we can endure is 20ms */ 85220848903SChaotian Jing unsigned long tmo = jiffies + msecs_to_jiffies(20); 85320848903SChaotian Jing 85420848903SChaotian Jing while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && 85520848903SChaotian Jing time_before(jiffies, tmo)) 85620848903SChaotian Jing cpu_relax(); 85720848903SChaotian Jing if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { 85820848903SChaotian Jing dev_err(host->dev, "CMD bus busy detected\n"); 85920848903SChaotian Jing host->error |= REQ_CMD_BUSY; 86020848903SChaotian Jing msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 86120848903SChaotian Jing return false; 86220848903SChaotian Jing } 86320848903SChaotian Jing 86420848903SChaotian Jing if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 86520848903SChaotian Jing tmo = jiffies + msecs_to_jiffies(20); 86620848903SChaotian Jing /* R1B or with data, should check SDCBUSY */ 86720848903SChaotian Jing while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && 86820848903SChaotian Jing time_before(jiffies, tmo)) 86920848903SChaotian Jing cpu_relax(); 87020848903SChaotian Jing if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { 87120848903SChaotian Jing dev_err(host->dev, "Controller busy detected\n"); 87220848903SChaotian Jing host->error |= REQ_CMD_BUSY; 87320848903SChaotian Jing msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 87420848903SChaotian Jing return false; 87520848903SChaotian Jing } 87620848903SChaotian Jing } 87720848903SChaotian Jing return true; 87820848903SChaotian Jing } 87920848903SChaotian Jing 88020848903SChaotian Jing static void msdc_start_command(struct msdc_host *host, 88120848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 88220848903SChaotian Jing { 88320848903SChaotian Jing u32 rawcmd; 88420848903SChaotian Jing 88520848903SChaotian Jing WARN_ON(host->cmd); 88620848903SChaotian Jing host->cmd = cmd; 88720848903SChaotian Jing 88820848903SChaotian Jing if (!msdc_cmd_is_ready(host, mrq, cmd)) 88920848903SChaotian Jing return; 89020848903SChaotian Jing 89120848903SChaotian Jing if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 89220848903SChaotian Jing readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 89320848903SChaotian Jing dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 89420848903SChaotian Jing msdc_reset_hw(host); 89520848903SChaotian Jing } 89620848903SChaotian Jing 89720848903SChaotian Jing cmd->error = 0; 89820848903SChaotian Jing rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 89920848903SChaotian Jing mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 90020848903SChaotian Jing 901726a9aacSChaotian Jing sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 90220848903SChaotian Jing writel(cmd->arg, host->base + SDC_ARG); 90320848903SChaotian Jing writel(rawcmd, host->base + SDC_CMD); 90420848903SChaotian Jing } 90520848903SChaotian Jing 90620848903SChaotian Jing static void msdc_cmd_next(struct msdc_host *host, 90720848903SChaotian Jing struct mmc_request *mrq, struct mmc_command *cmd) 90820848903SChaotian Jing { 909ddc71387SChaotian Jing if ((cmd->error && 910ddc71387SChaotian Jing !(cmd->error == -EILSEQ && 911ddc71387SChaotian Jing (cmd->opcode == MMC_SEND_TUNING_BLOCK || 912ddc71387SChaotian Jing cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) || 913ddc71387SChaotian Jing (mrq->sbc && mrq->sbc->error)) 91420848903SChaotian Jing msdc_request_done(host, mrq); 91520848903SChaotian Jing else if (cmd == mrq->sbc) 91620848903SChaotian Jing msdc_start_command(host, mrq, mrq->cmd); 91720848903SChaotian Jing else if (!cmd->data) 91820848903SChaotian Jing msdc_request_done(host, mrq); 91920848903SChaotian Jing else 92020848903SChaotian Jing msdc_start_data(host, mrq, cmd, cmd->data); 92120848903SChaotian Jing } 92220848903SChaotian Jing 92320848903SChaotian Jing static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 92420848903SChaotian Jing { 92520848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 92620848903SChaotian Jing 92720848903SChaotian Jing host->error = 0; 92820848903SChaotian Jing WARN_ON(host->mrq); 92920848903SChaotian Jing host->mrq = mrq; 93020848903SChaotian Jing 93120848903SChaotian Jing if (mrq->data) 93220848903SChaotian Jing msdc_prepare_data(host, mrq); 93320848903SChaotian Jing 93420848903SChaotian Jing /* if SBC is required, we have HW option and SW option. 93520848903SChaotian Jing * if HW option is enabled, and SBC does not have "special" flags, 93620848903SChaotian Jing * use HW option, otherwise use SW option 93720848903SChaotian Jing */ 93820848903SChaotian Jing if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 93920848903SChaotian Jing (mrq->sbc->arg & 0xFFFF0000))) 94020848903SChaotian Jing msdc_start_command(host, mrq, mrq->sbc); 94120848903SChaotian Jing else 94220848903SChaotian Jing msdc_start_command(host, mrq, mrq->cmd); 94320848903SChaotian Jing } 94420848903SChaotian Jing 945d3c6aac3SLinus Walleij static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 94620848903SChaotian Jing { 94720848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 94820848903SChaotian Jing struct mmc_data *data = mrq->data; 94920848903SChaotian Jing 95020848903SChaotian Jing if (!data) 95120848903SChaotian Jing return; 95220848903SChaotian Jing 95320848903SChaotian Jing msdc_prepare_data(host, mrq); 95420848903SChaotian Jing data->host_cookie |= MSDC_ASYNC_FLAG; 95520848903SChaotian Jing } 95620848903SChaotian Jing 95720848903SChaotian Jing static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 95820848903SChaotian Jing int err) 95920848903SChaotian Jing { 96020848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 96120848903SChaotian Jing struct mmc_data *data; 96220848903SChaotian Jing 96320848903SChaotian Jing data = mrq->data; 96420848903SChaotian Jing if (!data) 96520848903SChaotian Jing return; 96620848903SChaotian Jing if (data->host_cookie) { 96720848903SChaotian Jing data->host_cookie &= ~MSDC_ASYNC_FLAG; 96820848903SChaotian Jing msdc_unprepare_data(host, mrq); 96920848903SChaotian Jing } 97020848903SChaotian Jing } 97120848903SChaotian Jing 97220848903SChaotian Jing static void msdc_data_xfer_next(struct msdc_host *host, 97320848903SChaotian Jing struct mmc_request *mrq, struct mmc_data *data) 97420848903SChaotian Jing { 97520848903SChaotian Jing if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 9766397b7f5SChaotian Jing !mrq->sbc) 97720848903SChaotian Jing msdc_start_command(host, mrq, mrq->stop); 97820848903SChaotian Jing else 97920848903SChaotian Jing msdc_request_done(host, mrq); 98020848903SChaotian Jing } 98120848903SChaotian Jing 98220848903SChaotian Jing static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 98320848903SChaotian Jing struct mmc_request *mrq, struct mmc_data *data) 98420848903SChaotian Jing { 98520848903SChaotian Jing struct mmc_command *stop = data->stop; 98620848903SChaotian Jing unsigned long flags; 98720848903SChaotian Jing bool done; 98820848903SChaotian Jing unsigned int check_data = events & 98920848903SChaotian Jing (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 99020848903SChaotian Jing | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 99120848903SChaotian Jing | MSDC_INT_DMA_PROTECT); 99220848903SChaotian Jing 99320848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 99420848903SChaotian Jing done = !host->data; 99520848903SChaotian Jing if (check_data) 99620848903SChaotian Jing host->data = NULL; 99720848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 99820848903SChaotian Jing 99920848903SChaotian Jing if (done) 100020848903SChaotian Jing return true; 100120848903SChaotian Jing 100220848903SChaotian Jing if (check_data || (stop && stop->error)) { 100320848903SChaotian Jing dev_dbg(host->dev, "DMA status: 0x%8X\n", 100420848903SChaotian Jing readl(host->base + MSDC_DMA_CFG)); 100520848903SChaotian Jing sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 100620848903SChaotian Jing 1); 100720848903SChaotian Jing while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) 100820848903SChaotian Jing cpu_relax(); 100920848903SChaotian Jing sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 101020848903SChaotian Jing dev_dbg(host->dev, "DMA stop\n"); 101120848903SChaotian Jing 101220848903SChaotian Jing if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 101320848903SChaotian Jing data->bytes_xfered = data->blocks * data->blksz; 101420848903SChaotian Jing } else { 10152066fd28SChaotian Jing dev_dbg(host->dev, "interrupt events: %x\n", events); 101620848903SChaotian Jing msdc_reset_hw(host); 101720848903SChaotian Jing host->error |= REQ_DAT_ERR; 101820848903SChaotian Jing data->bytes_xfered = 0; 101920848903SChaotian Jing 102020848903SChaotian Jing if (events & MSDC_INT_DATTMO) 102120848903SChaotian Jing data->error = -ETIMEDOUT; 10226397b7f5SChaotian Jing else if (events & MSDC_INT_DATCRCERR) 10236397b7f5SChaotian Jing data->error = -EILSEQ; 102420848903SChaotian Jing 10252066fd28SChaotian Jing dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 102620848903SChaotian Jing __func__, mrq->cmd->opcode, data->blocks); 10272066fd28SChaotian Jing dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 102820848903SChaotian Jing (int)data->error, data->bytes_xfered); 102920848903SChaotian Jing } 103020848903SChaotian Jing 103120848903SChaotian Jing msdc_data_xfer_next(host, mrq, data); 103220848903SChaotian Jing done = true; 103320848903SChaotian Jing } 103420848903SChaotian Jing return done; 103520848903SChaotian Jing } 103620848903SChaotian Jing 103720848903SChaotian Jing static void msdc_set_buswidth(struct msdc_host *host, u32 width) 103820848903SChaotian Jing { 103920848903SChaotian Jing u32 val = readl(host->base + SDC_CFG); 104020848903SChaotian Jing 104120848903SChaotian Jing val &= ~SDC_CFG_BUSWIDTH; 104220848903SChaotian Jing 104320848903SChaotian Jing switch (width) { 104420848903SChaotian Jing default: 104520848903SChaotian Jing case MMC_BUS_WIDTH_1: 104620848903SChaotian Jing val |= (MSDC_BUS_1BITS << 16); 104720848903SChaotian Jing break; 104820848903SChaotian Jing case MMC_BUS_WIDTH_4: 104920848903SChaotian Jing val |= (MSDC_BUS_4BITS << 16); 105020848903SChaotian Jing break; 105120848903SChaotian Jing case MMC_BUS_WIDTH_8: 105220848903SChaotian Jing val |= (MSDC_BUS_8BITS << 16); 105320848903SChaotian Jing break; 105420848903SChaotian Jing } 105520848903SChaotian Jing 105620848903SChaotian Jing writel(val, host->base + SDC_CFG); 105720848903SChaotian Jing dev_dbg(host->dev, "Bus Width = %d", width); 105820848903SChaotian Jing } 105920848903SChaotian Jing 106020848903SChaotian Jing static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 106120848903SChaotian Jing { 106220848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 106320848903SChaotian Jing int ret = 0; 106420848903SChaotian Jing 106520848903SChaotian Jing if (!IS_ERR(mmc->supply.vqmmc)) { 1066fac49ce5SNicolas Boichat if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1067fac49ce5SNicolas Boichat ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 106820848903SChaotian Jing dev_err(host->dev, "Unsupported signal voltage!\n"); 106920848903SChaotian Jing return -EINVAL; 107020848903SChaotian Jing } 107120848903SChaotian Jing 1072fac49ce5SNicolas Boichat ret = mmc_regulator_set_vqmmc(mmc, ios); 107320848903SChaotian Jing if (ret) { 1074fac49ce5SNicolas Boichat dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1075fac49ce5SNicolas Boichat ret, ios->signal_voltage); 107620848903SChaotian Jing } else { 107720848903SChaotian Jing /* Apply different pinctrl settings for different signal voltage */ 107820848903SChaotian Jing if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 107920848903SChaotian Jing pinctrl_select_state(host->pinctrl, host->pins_uhs); 108020848903SChaotian Jing else 108120848903SChaotian Jing pinctrl_select_state(host->pinctrl, host->pins_default); 108220848903SChaotian Jing } 108320848903SChaotian Jing } 108420848903SChaotian Jing return ret; 108520848903SChaotian Jing } 108620848903SChaotian Jing 108720848903SChaotian Jing static int msdc_card_busy(struct mmc_host *mmc) 108820848903SChaotian Jing { 108920848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 109020848903SChaotian Jing u32 status = readl(host->base + MSDC_PS); 109120848903SChaotian Jing 10923bc702edSyong mao /* only check if data0 is low */ 10933bc702edSyong mao return !(status & BIT(16)); 109420848903SChaotian Jing } 109520848903SChaotian Jing 109620848903SChaotian Jing static void msdc_request_timeout(struct work_struct *work) 109720848903SChaotian Jing { 109820848903SChaotian Jing struct msdc_host *host = container_of(work, struct msdc_host, 109920848903SChaotian Jing req_timeout.work); 110020848903SChaotian Jing 110120848903SChaotian Jing /* simulate HW timeout status */ 110220848903SChaotian Jing dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 110320848903SChaotian Jing if (host->mrq) { 110420848903SChaotian Jing dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 110520848903SChaotian Jing host->mrq, host->mrq->cmd->opcode); 110620848903SChaotian Jing if (host->cmd) { 110720848903SChaotian Jing dev_err(host->dev, "%s: aborting cmd=%d\n", 110820848903SChaotian Jing __func__, host->cmd->opcode); 110920848903SChaotian Jing msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 111020848903SChaotian Jing host->cmd); 111120848903SChaotian Jing } else if (host->data) { 111220848903SChaotian Jing dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 111320848903SChaotian Jing __func__, host->mrq->cmd->opcode, 111420848903SChaotian Jing host->data->blocks); 111520848903SChaotian Jing msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 111620848903SChaotian Jing host->data); 111720848903SChaotian Jing } 111820848903SChaotian Jing } 111920848903SChaotian Jing } 112020848903SChaotian Jing 112120848903SChaotian Jing static irqreturn_t msdc_irq(int irq, void *dev_id) 112220848903SChaotian Jing { 112320848903SChaotian Jing struct msdc_host *host = (struct msdc_host *) dev_id; 112420848903SChaotian Jing 112520848903SChaotian Jing while (true) { 112620848903SChaotian Jing unsigned long flags; 112720848903SChaotian Jing struct mmc_request *mrq; 112820848903SChaotian Jing struct mmc_command *cmd; 112920848903SChaotian Jing struct mmc_data *data; 113020848903SChaotian Jing u32 events, event_mask; 113120848903SChaotian Jing 113220848903SChaotian Jing spin_lock_irqsave(&host->lock, flags); 113320848903SChaotian Jing events = readl(host->base + MSDC_INT); 113420848903SChaotian Jing event_mask = readl(host->base + MSDC_INTEN); 113520848903SChaotian Jing /* clear interrupts */ 113620848903SChaotian Jing writel(events & event_mask, host->base + MSDC_INT); 113720848903SChaotian Jing 113820848903SChaotian Jing mrq = host->mrq; 113920848903SChaotian Jing cmd = host->cmd; 114020848903SChaotian Jing data = host->data; 114120848903SChaotian Jing spin_unlock_irqrestore(&host->lock, flags); 114220848903SChaotian Jing 114320848903SChaotian Jing if (!(events & event_mask)) 114420848903SChaotian Jing break; 114520848903SChaotian Jing 114620848903SChaotian Jing if (!mrq) { 114720848903SChaotian Jing dev_err(host->dev, 114820848903SChaotian Jing "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 114920848903SChaotian Jing __func__, events, event_mask); 115020848903SChaotian Jing WARN_ON(1); 115120848903SChaotian Jing break; 115220848903SChaotian Jing } 115320848903SChaotian Jing 115420848903SChaotian Jing dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 115520848903SChaotian Jing 115620848903SChaotian Jing if (cmd) 115720848903SChaotian Jing msdc_cmd_done(host, events, mrq, cmd); 115820848903SChaotian Jing else if (data) 115920848903SChaotian Jing msdc_data_xfer_done(host, events, mrq, data); 116020848903SChaotian Jing } 116120848903SChaotian Jing 116220848903SChaotian Jing return IRQ_HANDLED; 116320848903SChaotian Jing } 116420848903SChaotian Jing 116520848903SChaotian Jing static void msdc_init_hw(struct msdc_host *host) 116620848903SChaotian Jing { 116720848903SChaotian Jing u32 val; 116820848903SChaotian Jing 116920848903SChaotian Jing /* Configure to MMC/SD mode, clock free running */ 117020848903SChaotian Jing sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 117120848903SChaotian Jing 117220848903SChaotian Jing /* Reset */ 117320848903SChaotian Jing msdc_reset_hw(host); 117420848903SChaotian Jing 117520848903SChaotian Jing /* Disable card detection */ 117620848903SChaotian Jing sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 117720848903SChaotian Jing 117820848903SChaotian Jing /* Disable and clear all interrupts */ 117920848903SChaotian Jing writel(0, host->base + MSDC_INTEN); 118020848903SChaotian Jing val = readl(host->base + MSDC_INT); 118120848903SChaotian Jing writel(val, host->base + MSDC_INT); 118220848903SChaotian Jing 118320848903SChaotian Jing writel(0, host->base + MSDC_PAD_TUNE); 118420848903SChaotian Jing writel(0, host->base + MSDC_IOCON); 11856397b7f5SChaotian Jing sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 11866397b7f5SChaotian Jing writel(0x403c0046, host->base + MSDC_PATCH_BIT); 118720848903SChaotian Jing sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 118820848903SChaotian Jing writel(0xffff0089, host->base + MSDC_PATCH_BIT1); 11896397b7f5SChaotian Jing sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 11906397b7f5SChaotian Jing 119120848903SChaotian Jing /* Configure to enable SDIO mode. 119220848903SChaotian Jing * it's must otherwise sdio cmd5 failed 119320848903SChaotian Jing */ 119420848903SChaotian Jing sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 119520848903SChaotian Jing 119620848903SChaotian Jing /* disable detect SDIO device interrupt function */ 119720848903SChaotian Jing sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 119820848903SChaotian Jing 119920848903SChaotian Jing /* Configure to default data timeout */ 120020848903SChaotian Jing sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 120120848903SChaotian Jing 120286beac37SChaotian Jing host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 120386beac37SChaotian Jing host->def_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE); 120420848903SChaotian Jing dev_dbg(host->dev, "init hardware done!"); 120520848903SChaotian Jing } 120620848903SChaotian Jing 120720848903SChaotian Jing static void msdc_deinit_hw(struct msdc_host *host) 120820848903SChaotian Jing { 120920848903SChaotian Jing u32 val; 121020848903SChaotian Jing /* Disable and clear all interrupts */ 121120848903SChaotian Jing writel(0, host->base + MSDC_INTEN); 121220848903SChaotian Jing 121320848903SChaotian Jing val = readl(host->base + MSDC_INT); 121420848903SChaotian Jing writel(val, host->base + MSDC_INT); 121520848903SChaotian Jing } 121620848903SChaotian Jing 121720848903SChaotian Jing /* init gpd and bd list in msdc_drv_probe */ 121820848903SChaotian Jing static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 121920848903SChaotian Jing { 122020848903SChaotian Jing struct mt_gpdma_desc *gpd = dma->gpd; 122120848903SChaotian Jing struct mt_bdma_desc *bd = dma->bd; 122220848903SChaotian Jing int i; 122320848903SChaotian Jing 122462b0d27aSChaotian Jing memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 122520848903SChaotian Jing 122620848903SChaotian Jing gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 122720848903SChaotian Jing gpd->ptr = (u32)dma->bd_addr; /* physical address */ 122862b0d27aSChaotian Jing /* gpd->next is must set for desc DMA 122962b0d27aSChaotian Jing * That's why must alloc 2 gpd structure. 123062b0d27aSChaotian Jing */ 123162b0d27aSChaotian Jing gpd->next = (u32)dma->gpd_addr + sizeof(struct mt_gpdma_desc); 123220848903SChaotian Jing memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 123320848903SChaotian Jing for (i = 0; i < (MAX_BD_NUM - 1); i++) 123420848903SChaotian Jing bd[i].next = (u32)dma->bd_addr + sizeof(*bd) * (i + 1); 123520848903SChaotian Jing } 123620848903SChaotian Jing 123720848903SChaotian Jing static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 123820848903SChaotian Jing { 123920848903SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 124020848903SChaotian Jing int ret; 124120848903SChaotian Jing 124220848903SChaotian Jing msdc_set_buswidth(host, ios->bus_width); 124320848903SChaotian Jing 124420848903SChaotian Jing /* Suspend/Resume will do power off/on */ 124520848903SChaotian Jing switch (ios->power_mode) { 124620848903SChaotian Jing case MMC_POWER_UP: 124720848903SChaotian Jing if (!IS_ERR(mmc->supply.vmmc)) { 12486397b7f5SChaotian Jing msdc_init_hw(host); 124920848903SChaotian Jing ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 125020848903SChaotian Jing ios->vdd); 125120848903SChaotian Jing if (ret) { 125220848903SChaotian Jing dev_err(host->dev, "Failed to set vmmc power!\n"); 1253567979fbSUlf Hansson return; 125420848903SChaotian Jing } 125520848903SChaotian Jing } 125620848903SChaotian Jing break; 125720848903SChaotian Jing case MMC_POWER_ON: 125820848903SChaotian Jing if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 125920848903SChaotian Jing ret = regulator_enable(mmc->supply.vqmmc); 126020848903SChaotian Jing if (ret) 126120848903SChaotian Jing dev_err(host->dev, "Failed to set vqmmc power!\n"); 126220848903SChaotian Jing else 126320848903SChaotian Jing host->vqmmc_enabled = true; 126420848903SChaotian Jing } 126520848903SChaotian Jing break; 126620848903SChaotian Jing case MMC_POWER_OFF: 126720848903SChaotian Jing if (!IS_ERR(mmc->supply.vmmc)) 126820848903SChaotian Jing mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 126920848903SChaotian Jing 127020848903SChaotian Jing if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 127120848903SChaotian Jing regulator_disable(mmc->supply.vqmmc); 127220848903SChaotian Jing host->vqmmc_enabled = false; 127320848903SChaotian Jing } 127420848903SChaotian Jing break; 127520848903SChaotian Jing default: 127620848903SChaotian Jing break; 127720848903SChaotian Jing } 127820848903SChaotian Jing 12796e622947SChaotian Jing if (host->mclk != ios->clock || host->timing != ios->timing) 12806e622947SChaotian Jing msdc_set_mclk(host, ios->timing, ios->clock); 128120848903SChaotian Jing } 128220848903SChaotian Jing 12836397b7f5SChaotian Jing static u32 test_delay_bit(u32 delay, u32 bit) 12846397b7f5SChaotian Jing { 12856397b7f5SChaotian Jing bit %= PAD_DELAY_MAX; 12866397b7f5SChaotian Jing return delay & (1 << bit); 12876397b7f5SChaotian Jing } 12886397b7f5SChaotian Jing 12896397b7f5SChaotian Jing static int get_delay_len(u32 delay, u32 start_bit) 12906397b7f5SChaotian Jing { 12916397b7f5SChaotian Jing int i; 12926397b7f5SChaotian Jing 12936397b7f5SChaotian Jing for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 12946397b7f5SChaotian Jing if (test_delay_bit(delay, start_bit + i) == 0) 12956397b7f5SChaotian Jing return i; 12966397b7f5SChaotian Jing } 12976397b7f5SChaotian Jing return PAD_DELAY_MAX - start_bit; 12986397b7f5SChaotian Jing } 12996397b7f5SChaotian Jing 13006397b7f5SChaotian Jing static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 13016397b7f5SChaotian Jing { 13026397b7f5SChaotian Jing int start = 0, len = 0; 13036397b7f5SChaotian Jing int start_final = 0, len_final = 0; 13046397b7f5SChaotian Jing u8 final_phase = 0xff; 130562d494caSGeert Uytterhoeven struct msdc_delay_phase delay_phase = { 0, }; 13066397b7f5SChaotian Jing 13076397b7f5SChaotian Jing if (delay == 0) { 13086397b7f5SChaotian Jing dev_err(host->dev, "phase error: [map:%x]\n", delay); 13096397b7f5SChaotian Jing delay_phase.final_phase = final_phase; 13106397b7f5SChaotian Jing return delay_phase; 13116397b7f5SChaotian Jing } 13126397b7f5SChaotian Jing 13136397b7f5SChaotian Jing while (start < PAD_DELAY_MAX) { 13146397b7f5SChaotian Jing len = get_delay_len(delay, start); 13156397b7f5SChaotian Jing if (len_final < len) { 13166397b7f5SChaotian Jing start_final = start; 13176397b7f5SChaotian Jing len_final = len; 13186397b7f5SChaotian Jing } 13196397b7f5SChaotian Jing start += len ? len : 1; 13201ede5cb8Syong mao if (len >= 12 && start_final < 4) 13216397b7f5SChaotian Jing break; 13226397b7f5SChaotian Jing } 13236397b7f5SChaotian Jing 13246397b7f5SChaotian Jing /* The rule is that to find the smallest delay cell */ 13256397b7f5SChaotian Jing if (start_final == 0) 13266397b7f5SChaotian Jing final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 13276397b7f5SChaotian Jing else 13286397b7f5SChaotian Jing final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 13296397b7f5SChaotian Jing dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 13306397b7f5SChaotian Jing delay, len_final, final_phase); 13316397b7f5SChaotian Jing 13326397b7f5SChaotian Jing delay_phase.maxlen = len_final; 13336397b7f5SChaotian Jing delay_phase.start = start_final; 13346397b7f5SChaotian Jing delay_phase.final_phase = final_phase; 13356397b7f5SChaotian Jing return delay_phase; 13366397b7f5SChaotian Jing } 13376397b7f5SChaotian Jing 13386397b7f5SChaotian Jing static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 13396397b7f5SChaotian Jing { 13406397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 13416397b7f5SChaotian Jing u32 rise_delay = 0, fall_delay = 0; 1342ae9c657eSChaotian Jing struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 13431ede5cb8Syong mao struct msdc_delay_phase internal_delay_phase; 13446397b7f5SChaotian Jing u8 final_delay, final_maxlen; 13451ede5cb8Syong mao u32 internal_delay = 0; 13466397b7f5SChaotian Jing int cmd_err; 13471ede5cb8Syong mao int i, j; 13481ede5cb8Syong mao 13491ede5cb8Syong mao if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 13501ede5cb8Syong mao mmc->ios.timing == MMC_TIMING_UHS_SDR104) 13511ede5cb8Syong mao sdr_set_field(host->base + MSDC_PAD_TUNE, 13521ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, 13531ede5cb8Syong mao host->hs200_cmd_int_delay); 13546397b7f5SChaotian Jing 13556397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 13566397b7f5SChaotian Jing for (i = 0 ; i < PAD_DELAY_MAX; i++) { 13576397b7f5SChaotian Jing sdr_set_field(host->base + MSDC_PAD_TUNE, 13586397b7f5SChaotian Jing MSDC_PAD_TUNE_CMDRDLY, i); 13591ede5cb8Syong mao /* 13601ede5cb8Syong mao * Using the same parameters, it may sometimes pass the test, 13611ede5cb8Syong mao * but sometimes it may fail. To make sure the parameters are 13621ede5cb8Syong mao * more stable, we test each set of parameters 3 times. 13631ede5cb8Syong mao */ 13641ede5cb8Syong mao for (j = 0; j < 3; j++) { 13656397b7f5SChaotian Jing mmc_send_tuning(mmc, opcode, &cmd_err); 13661ede5cb8Syong mao if (!cmd_err) { 13676397b7f5SChaotian Jing rise_delay |= (1 << i); 13681ede5cb8Syong mao } else { 13691ede5cb8Syong mao rise_delay &= ~(1 << i); 13701ede5cb8Syong mao break; 13711ede5cb8Syong mao } 13721ede5cb8Syong mao } 13736397b7f5SChaotian Jing } 1374ae9c657eSChaotian Jing final_rise_delay = get_best_delay(host, rise_delay); 1375ae9c657eSChaotian Jing /* if rising edge has enough margin, then do not scan falling edge */ 13761ede5cb8Syong mao if (final_rise_delay.maxlen >= 12 && final_rise_delay.start < 4) 1377ae9c657eSChaotian Jing goto skip_fall; 13786397b7f5SChaotian Jing 13796397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 13806397b7f5SChaotian Jing for (i = 0; i < PAD_DELAY_MAX; i++) { 13816397b7f5SChaotian Jing sdr_set_field(host->base + MSDC_PAD_TUNE, 13826397b7f5SChaotian Jing MSDC_PAD_TUNE_CMDRDLY, i); 13831ede5cb8Syong mao /* 13841ede5cb8Syong mao * Using the same parameters, it may sometimes pass the test, 13851ede5cb8Syong mao * but sometimes it may fail. To make sure the parameters are 13861ede5cb8Syong mao * more stable, we test each set of parameters 3 times. 13871ede5cb8Syong mao */ 13881ede5cb8Syong mao for (j = 0; j < 3; j++) { 13896397b7f5SChaotian Jing mmc_send_tuning(mmc, opcode, &cmd_err); 13901ede5cb8Syong mao if (!cmd_err) { 13916397b7f5SChaotian Jing fall_delay |= (1 << i); 13921ede5cb8Syong mao } else { 13931ede5cb8Syong mao fall_delay &= ~(1 << i); 13941ede5cb8Syong mao break; 13951ede5cb8Syong mao } 13961ede5cb8Syong mao } 13976397b7f5SChaotian Jing } 13986397b7f5SChaotian Jing final_fall_delay = get_best_delay(host, fall_delay); 13996397b7f5SChaotian Jing 1400ae9c657eSChaotian Jing skip_fall: 14016397b7f5SChaotian Jing final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 14021ede5cb8Syong mao if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 14031ede5cb8Syong mao final_maxlen = final_fall_delay.maxlen; 14046397b7f5SChaotian Jing if (final_maxlen == final_rise_delay.maxlen) { 14056397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 14066397b7f5SChaotian Jing sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY, 14076397b7f5SChaotian Jing final_rise_delay.final_phase); 14086397b7f5SChaotian Jing final_delay = final_rise_delay.final_phase; 14096397b7f5SChaotian Jing } else { 14106397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 14116397b7f5SChaotian Jing sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY, 14126397b7f5SChaotian Jing final_fall_delay.final_phase); 14136397b7f5SChaotian Jing final_delay = final_fall_delay.final_phase; 14146397b7f5SChaotian Jing } 14151ede5cb8Syong mao if (host->hs200_cmd_int_delay) 14161ede5cb8Syong mao goto skip_internal; 14176397b7f5SChaotian Jing 14181ede5cb8Syong mao for (i = 0; i < PAD_DELAY_MAX; i++) { 14191ede5cb8Syong mao sdr_set_field(host->base + MSDC_PAD_TUNE, 14201ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, i); 14211ede5cb8Syong mao mmc_send_tuning(mmc, opcode, &cmd_err); 14221ede5cb8Syong mao if (!cmd_err) 14231ede5cb8Syong mao internal_delay |= (1 << i); 14241ede5cb8Syong mao } 14251ede5cb8Syong mao dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 14261ede5cb8Syong mao internal_delay_phase = get_best_delay(host, internal_delay); 14271ede5cb8Syong mao sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, 14281ede5cb8Syong mao internal_delay_phase.final_phase); 14291ede5cb8Syong mao skip_internal: 14301ede5cb8Syong mao dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 14311ede5cb8Syong mao return final_delay == 0xff ? -EIO : 0; 14321ede5cb8Syong mao } 14331ede5cb8Syong mao 14341ede5cb8Syong mao static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 14351ede5cb8Syong mao { 14361ede5cb8Syong mao struct msdc_host *host = mmc_priv(mmc); 14371ede5cb8Syong mao u32 cmd_delay = 0; 14381ede5cb8Syong mao struct msdc_delay_phase final_cmd_delay = { 0,}; 14391ede5cb8Syong mao u8 final_delay; 14401ede5cb8Syong mao int cmd_err; 14411ede5cb8Syong mao int i, j; 14421ede5cb8Syong mao 14431ede5cb8Syong mao /* select EMMC50 PAD CMD tune */ 14441ede5cb8Syong mao sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 14451ede5cb8Syong mao 14461ede5cb8Syong mao if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 14471ede5cb8Syong mao mmc->ios.timing == MMC_TIMING_UHS_SDR104) 14481ede5cb8Syong mao sdr_set_field(host->base + MSDC_PAD_TUNE, 14491ede5cb8Syong mao MSDC_PAD_TUNE_CMDRRDLY, 14501ede5cb8Syong mao host->hs200_cmd_int_delay); 14511ede5cb8Syong mao 14521ede5cb8Syong mao if (host->hs400_cmd_resp_sel_rising) 14531ede5cb8Syong mao sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 14541ede5cb8Syong mao else 14551ede5cb8Syong mao sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 14561ede5cb8Syong mao for (i = 0 ; i < PAD_DELAY_MAX; i++) { 14571ede5cb8Syong mao sdr_set_field(host->base + PAD_CMD_TUNE, 14581ede5cb8Syong mao PAD_CMD_TUNE_RX_DLY3, i); 14591ede5cb8Syong mao /* 14601ede5cb8Syong mao * Using the same parameters, it may sometimes pass the test, 14611ede5cb8Syong mao * but sometimes it may fail. To make sure the parameters are 14621ede5cb8Syong mao * more stable, we test each set of parameters 3 times. 14631ede5cb8Syong mao */ 14641ede5cb8Syong mao for (j = 0; j < 3; j++) { 14651ede5cb8Syong mao mmc_send_tuning(mmc, opcode, &cmd_err); 14661ede5cb8Syong mao if (!cmd_err) { 14671ede5cb8Syong mao cmd_delay |= (1 << i); 14681ede5cb8Syong mao } else { 14691ede5cb8Syong mao cmd_delay &= ~(1 << i); 14701ede5cb8Syong mao break; 14711ede5cb8Syong mao } 14721ede5cb8Syong mao } 14731ede5cb8Syong mao } 14741ede5cb8Syong mao final_cmd_delay = get_best_delay(host, cmd_delay); 14751ede5cb8Syong mao sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 14761ede5cb8Syong mao final_cmd_delay.final_phase); 14771ede5cb8Syong mao final_delay = final_cmd_delay.final_phase; 14781ede5cb8Syong mao 14791ede5cb8Syong mao dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 14806397b7f5SChaotian Jing return final_delay == 0xff ? -EIO : 0; 14816397b7f5SChaotian Jing } 14826397b7f5SChaotian Jing 14836397b7f5SChaotian Jing static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 14846397b7f5SChaotian Jing { 14856397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 14866397b7f5SChaotian Jing u32 rise_delay = 0, fall_delay = 0; 1487ae9c657eSChaotian Jing struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 14886397b7f5SChaotian Jing u8 final_delay, final_maxlen; 14896397b7f5SChaotian Jing int i, ret; 14906397b7f5SChaotian Jing 14916397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 14926397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 14936397b7f5SChaotian Jing for (i = 0 ; i < PAD_DELAY_MAX; i++) { 14946397b7f5SChaotian Jing sdr_set_field(host->base + MSDC_PAD_TUNE, 14956397b7f5SChaotian Jing MSDC_PAD_TUNE_DATRRDLY, i); 14966397b7f5SChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 14976397b7f5SChaotian Jing if (!ret) 14986397b7f5SChaotian Jing rise_delay |= (1 << i); 14996397b7f5SChaotian Jing } 1500ae9c657eSChaotian Jing final_rise_delay = get_best_delay(host, rise_delay); 1501ae9c657eSChaotian Jing /* if rising edge has enough margin, then do not scan falling edge */ 15021ede5cb8Syong mao if (final_rise_delay.maxlen >= 12 || 1503ae9c657eSChaotian Jing (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1504ae9c657eSChaotian Jing goto skip_fall; 15056397b7f5SChaotian Jing 15066397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 15076397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 15086397b7f5SChaotian Jing for (i = 0; i < PAD_DELAY_MAX; i++) { 15096397b7f5SChaotian Jing sdr_set_field(host->base + MSDC_PAD_TUNE, 15106397b7f5SChaotian Jing MSDC_PAD_TUNE_DATRRDLY, i); 15116397b7f5SChaotian Jing ret = mmc_send_tuning(mmc, opcode, NULL); 15126397b7f5SChaotian Jing if (!ret) 15136397b7f5SChaotian Jing fall_delay |= (1 << i); 15146397b7f5SChaotian Jing } 15156397b7f5SChaotian Jing final_fall_delay = get_best_delay(host, fall_delay); 15166397b7f5SChaotian Jing 1517ae9c657eSChaotian Jing skip_fall: 15186397b7f5SChaotian Jing final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 15196397b7f5SChaotian Jing if (final_maxlen == final_rise_delay.maxlen) { 15206397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 15216397b7f5SChaotian Jing sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 15226397b7f5SChaotian Jing sdr_set_field(host->base + MSDC_PAD_TUNE, 15236397b7f5SChaotian Jing MSDC_PAD_TUNE_DATRRDLY, 15246397b7f5SChaotian Jing final_rise_delay.final_phase); 15256397b7f5SChaotian Jing final_delay = final_rise_delay.final_phase; 15266397b7f5SChaotian Jing } else { 15276397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 15286397b7f5SChaotian Jing sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 15296397b7f5SChaotian Jing sdr_set_field(host->base + MSDC_PAD_TUNE, 15306397b7f5SChaotian Jing MSDC_PAD_TUNE_DATRRDLY, 15316397b7f5SChaotian Jing final_fall_delay.final_phase); 15326397b7f5SChaotian Jing final_delay = final_fall_delay.final_phase; 15336397b7f5SChaotian Jing } 15346397b7f5SChaotian Jing 15351ede5cb8Syong mao dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 15366397b7f5SChaotian Jing return final_delay == 0xff ? -EIO : 0; 15376397b7f5SChaotian Jing } 15386397b7f5SChaotian Jing 15396397b7f5SChaotian Jing static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 15406397b7f5SChaotian Jing { 15416397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 15426397b7f5SChaotian Jing int ret; 15436397b7f5SChaotian Jing 15441ede5cb8Syong mao if (host->hs400_mode) 15451ede5cb8Syong mao ret = hs400_tune_response(mmc, opcode); 15461ede5cb8Syong mao else 15476397b7f5SChaotian Jing ret = msdc_tune_response(mmc, opcode); 15486397b7f5SChaotian Jing if (ret == -EIO) { 15496397b7f5SChaotian Jing dev_err(host->dev, "Tune response fail!\n"); 1550567979fbSUlf Hansson return ret; 15516397b7f5SChaotian Jing } 15525462ff39SChaotian Jing if (host->hs400_mode == false) { 15536397b7f5SChaotian Jing ret = msdc_tune_data(mmc, opcode); 15546397b7f5SChaotian Jing if (ret == -EIO) 15556397b7f5SChaotian Jing dev_err(host->dev, "Tune data fail!\n"); 15565462ff39SChaotian Jing } 15576397b7f5SChaotian Jing 155886beac37SChaotian Jing host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 155986beac37SChaotian Jing host->saved_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE); 15601ede5cb8Syong mao host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 15616397b7f5SChaotian Jing return ret; 15626397b7f5SChaotian Jing } 15636397b7f5SChaotian Jing 15646397b7f5SChaotian Jing static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 15656397b7f5SChaotian Jing { 15666397b7f5SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 15675462ff39SChaotian Jing host->hs400_mode = true; 15686397b7f5SChaotian Jing 15696397b7f5SChaotian Jing writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 15706397b7f5SChaotian Jing return 0; 15716397b7f5SChaotian Jing } 15726397b7f5SChaotian Jing 1573c9b5061eSChaotian Jing static void msdc_hw_reset(struct mmc_host *mmc) 1574c9b5061eSChaotian Jing { 1575c9b5061eSChaotian Jing struct msdc_host *host = mmc_priv(mmc); 1576c9b5061eSChaotian Jing 1577c9b5061eSChaotian Jing sdr_set_bits(host->base + EMMC_IOCON, 1); 1578c9b5061eSChaotian Jing udelay(10); /* 10us is enough */ 1579c9b5061eSChaotian Jing sdr_clr_bits(host->base + EMMC_IOCON, 1); 1580c9b5061eSChaotian Jing } 1581c9b5061eSChaotian Jing 158220848903SChaotian Jing static struct mmc_host_ops mt_msdc_ops = { 158320848903SChaotian Jing .post_req = msdc_post_req, 158420848903SChaotian Jing .pre_req = msdc_pre_req, 158520848903SChaotian Jing .request = msdc_ops_request, 158620848903SChaotian Jing .set_ios = msdc_ops_set_ios, 15878d53e412SChaotian Jing .get_ro = mmc_gpio_get_ro, 158820848903SChaotian Jing .start_signal_voltage_switch = msdc_ops_switch_volt, 158920848903SChaotian Jing .card_busy = msdc_card_busy, 15906397b7f5SChaotian Jing .execute_tuning = msdc_execute_tuning, 15916397b7f5SChaotian Jing .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 1592c9b5061eSChaotian Jing .hw_reset = msdc_hw_reset, 159320848903SChaotian Jing }; 159420848903SChaotian Jing 15951ede5cb8Syong mao static void msdc_of_property_parse(struct platform_device *pdev, 15961ede5cb8Syong mao struct msdc_host *host) 15971ede5cb8Syong mao { 15981ede5cb8Syong mao of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 15991ede5cb8Syong mao &host->hs400_ds_delay); 16001ede5cb8Syong mao 16011ede5cb8Syong mao of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 16021ede5cb8Syong mao &host->hs200_cmd_int_delay); 16031ede5cb8Syong mao 16041ede5cb8Syong mao of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 16051ede5cb8Syong mao &host->hs400_cmd_int_delay); 16061ede5cb8Syong mao 16071ede5cb8Syong mao if (of_property_read_bool(pdev->dev.of_node, 16081ede5cb8Syong mao "mediatek,hs400-cmd-resp-sel-rising")) 16091ede5cb8Syong mao host->hs400_cmd_resp_sel_rising = true; 16101ede5cb8Syong mao else 16111ede5cb8Syong mao host->hs400_cmd_resp_sel_rising = false; 16121ede5cb8Syong mao } 16131ede5cb8Syong mao 161420848903SChaotian Jing static int msdc_drv_probe(struct platform_device *pdev) 161520848903SChaotian Jing { 161620848903SChaotian Jing struct mmc_host *mmc; 161720848903SChaotian Jing struct msdc_host *host; 161820848903SChaotian Jing struct resource *res; 161920848903SChaotian Jing int ret; 162020848903SChaotian Jing 162120848903SChaotian Jing if (!pdev->dev.of_node) { 162220848903SChaotian Jing dev_err(&pdev->dev, "No DT found\n"); 162320848903SChaotian Jing return -EINVAL; 162420848903SChaotian Jing } 162520848903SChaotian Jing /* Allocate MMC host for this device */ 162620848903SChaotian Jing mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 162720848903SChaotian Jing if (!mmc) 162820848903SChaotian Jing return -ENOMEM; 162920848903SChaotian Jing 163020848903SChaotian Jing host = mmc_priv(mmc); 163120848903SChaotian Jing ret = mmc_of_parse(mmc); 163220848903SChaotian Jing if (ret) 163320848903SChaotian Jing goto host_free; 163420848903SChaotian Jing 163520848903SChaotian Jing res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 163620848903SChaotian Jing host->base = devm_ioremap_resource(&pdev->dev, res); 163720848903SChaotian Jing if (IS_ERR(host->base)) { 163820848903SChaotian Jing ret = PTR_ERR(host->base); 163920848903SChaotian Jing goto host_free; 164020848903SChaotian Jing } 164120848903SChaotian Jing 164220848903SChaotian Jing ret = mmc_regulator_get_supply(mmc); 164320848903SChaotian Jing if (ret == -EPROBE_DEFER) 164420848903SChaotian Jing goto host_free; 164520848903SChaotian Jing 164620848903SChaotian Jing host->src_clk = devm_clk_get(&pdev->dev, "source"); 164720848903SChaotian Jing if (IS_ERR(host->src_clk)) { 164820848903SChaotian Jing ret = PTR_ERR(host->src_clk); 164920848903SChaotian Jing goto host_free; 165020848903SChaotian Jing } 165120848903SChaotian Jing 165220848903SChaotian Jing host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 165320848903SChaotian Jing if (IS_ERR(host->h_clk)) { 165420848903SChaotian Jing ret = PTR_ERR(host->h_clk); 165520848903SChaotian Jing goto host_free; 165620848903SChaotian Jing } 165720848903SChaotian Jing 165820848903SChaotian Jing host->irq = platform_get_irq(pdev, 0); 165920848903SChaotian Jing if (host->irq < 0) { 166020848903SChaotian Jing ret = -EINVAL; 166120848903SChaotian Jing goto host_free; 166220848903SChaotian Jing } 166320848903SChaotian Jing 166420848903SChaotian Jing host->pinctrl = devm_pinctrl_get(&pdev->dev); 166520848903SChaotian Jing if (IS_ERR(host->pinctrl)) { 166620848903SChaotian Jing ret = PTR_ERR(host->pinctrl); 166720848903SChaotian Jing dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 166820848903SChaotian Jing goto host_free; 166920848903SChaotian Jing } 167020848903SChaotian Jing 167120848903SChaotian Jing host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 167220848903SChaotian Jing if (IS_ERR(host->pins_default)) { 167320848903SChaotian Jing ret = PTR_ERR(host->pins_default); 167420848903SChaotian Jing dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 167520848903SChaotian Jing goto host_free; 167620848903SChaotian Jing } 167720848903SChaotian Jing 167820848903SChaotian Jing host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 167920848903SChaotian Jing if (IS_ERR(host->pins_uhs)) { 168020848903SChaotian Jing ret = PTR_ERR(host->pins_uhs); 168120848903SChaotian Jing dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 168220848903SChaotian Jing goto host_free; 168320848903SChaotian Jing } 168420848903SChaotian Jing 16851ede5cb8Syong mao msdc_of_property_parse(pdev, host); 16866397b7f5SChaotian Jing 168720848903SChaotian Jing host->dev = &pdev->dev; 168820848903SChaotian Jing host->mmc = mmc; 168920848903SChaotian Jing host->src_clk_freq = clk_get_rate(host->src_clk); 169020848903SChaotian Jing /* Set host parameters to mmc */ 169120848903SChaotian Jing mmc->ops = &mt_msdc_ops; 169240ceda09Syong mao mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 169320848903SChaotian Jing 169420848903SChaotian Jing mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; 169520848903SChaotian Jing /* MMC core transfer sizes tunable parameters */ 169620848903SChaotian Jing mmc->max_segs = MAX_BD_NUM; 169720848903SChaotian Jing mmc->max_seg_size = BDMA_DESC_BUFLEN; 169820848903SChaotian Jing mmc->max_blk_size = 2048; 169920848903SChaotian Jing mmc->max_req_size = 512 * 1024; 170020848903SChaotian Jing mmc->max_blk_count = mmc->max_req_size / 512; 170120848903SChaotian Jing host->dma_mask = DMA_BIT_MASK(32); 170220848903SChaotian Jing mmc_dev(mmc)->dma_mask = &host->dma_mask; 170320848903SChaotian Jing 170420848903SChaotian Jing host->timeout_clks = 3 * 1048576; 170520848903SChaotian Jing host->dma.gpd = dma_alloc_coherent(&pdev->dev, 170662b0d27aSChaotian Jing 2 * sizeof(struct mt_gpdma_desc), 170720848903SChaotian Jing &host->dma.gpd_addr, GFP_KERNEL); 170820848903SChaotian Jing host->dma.bd = dma_alloc_coherent(&pdev->dev, 170920848903SChaotian Jing MAX_BD_NUM * sizeof(struct mt_bdma_desc), 171020848903SChaotian Jing &host->dma.bd_addr, GFP_KERNEL); 171120848903SChaotian Jing if (!host->dma.gpd || !host->dma.bd) { 171220848903SChaotian Jing ret = -ENOMEM; 171320848903SChaotian Jing goto release_mem; 171420848903SChaotian Jing } 171520848903SChaotian Jing msdc_init_gpd_bd(host, &host->dma); 171620848903SChaotian Jing INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 171720848903SChaotian Jing spin_lock_init(&host->lock); 171820848903SChaotian Jing 171920848903SChaotian Jing platform_set_drvdata(pdev, mmc); 172020848903SChaotian Jing msdc_ungate_clock(host); 172120848903SChaotian Jing msdc_init_hw(host); 172220848903SChaotian Jing 172320848903SChaotian Jing ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 172420848903SChaotian Jing IRQF_TRIGGER_LOW | IRQF_ONESHOT, pdev->name, host); 172520848903SChaotian Jing if (ret) 172620848903SChaotian Jing goto release; 172720848903SChaotian Jing 17284b8a43e9SChaotian Jing pm_runtime_set_active(host->dev); 17294b8a43e9SChaotian Jing pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 17304b8a43e9SChaotian Jing pm_runtime_use_autosuspend(host->dev); 17314b8a43e9SChaotian Jing pm_runtime_enable(host->dev); 173220848903SChaotian Jing ret = mmc_add_host(mmc); 17334b8a43e9SChaotian Jing 173420848903SChaotian Jing if (ret) 17354b8a43e9SChaotian Jing goto end; 173620848903SChaotian Jing 173720848903SChaotian Jing return 0; 17384b8a43e9SChaotian Jing end: 17394b8a43e9SChaotian Jing pm_runtime_disable(host->dev); 174020848903SChaotian Jing release: 174120848903SChaotian Jing platform_set_drvdata(pdev, NULL); 174220848903SChaotian Jing msdc_deinit_hw(host); 174320848903SChaotian Jing msdc_gate_clock(host); 174420848903SChaotian Jing release_mem: 174520848903SChaotian Jing if (host->dma.gpd) 174620848903SChaotian Jing dma_free_coherent(&pdev->dev, 174762b0d27aSChaotian Jing 2 * sizeof(struct mt_gpdma_desc), 174820848903SChaotian Jing host->dma.gpd, host->dma.gpd_addr); 174920848903SChaotian Jing if (host->dma.bd) 175020848903SChaotian Jing dma_free_coherent(&pdev->dev, 175120848903SChaotian Jing MAX_BD_NUM * sizeof(struct mt_bdma_desc), 175220848903SChaotian Jing host->dma.bd, host->dma.bd_addr); 175320848903SChaotian Jing host_free: 175420848903SChaotian Jing mmc_free_host(mmc); 175520848903SChaotian Jing 175620848903SChaotian Jing return ret; 175720848903SChaotian Jing } 175820848903SChaotian Jing 175920848903SChaotian Jing static int msdc_drv_remove(struct platform_device *pdev) 176020848903SChaotian Jing { 176120848903SChaotian Jing struct mmc_host *mmc; 176220848903SChaotian Jing struct msdc_host *host; 176320848903SChaotian Jing 176420848903SChaotian Jing mmc = platform_get_drvdata(pdev); 176520848903SChaotian Jing host = mmc_priv(mmc); 176620848903SChaotian Jing 17674b8a43e9SChaotian Jing pm_runtime_get_sync(host->dev); 17684b8a43e9SChaotian Jing 176920848903SChaotian Jing platform_set_drvdata(pdev, NULL); 177020848903SChaotian Jing mmc_remove_host(host->mmc); 177120848903SChaotian Jing msdc_deinit_hw(host); 177220848903SChaotian Jing msdc_gate_clock(host); 177320848903SChaotian Jing 17744b8a43e9SChaotian Jing pm_runtime_disable(host->dev); 17754b8a43e9SChaotian Jing pm_runtime_put_noidle(host->dev); 177620848903SChaotian Jing dma_free_coherent(&pdev->dev, 177720848903SChaotian Jing sizeof(struct mt_gpdma_desc), 177820848903SChaotian Jing host->dma.gpd, host->dma.gpd_addr); 177920848903SChaotian Jing dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 178020848903SChaotian Jing host->dma.bd, host->dma.bd_addr); 178120848903SChaotian Jing 178220848903SChaotian Jing mmc_free_host(host->mmc); 178320848903SChaotian Jing 178420848903SChaotian Jing return 0; 178520848903SChaotian Jing } 178620848903SChaotian Jing 17874b8a43e9SChaotian Jing #ifdef CONFIG_PM 17884b8a43e9SChaotian Jing static void msdc_save_reg(struct msdc_host *host) 17894b8a43e9SChaotian Jing { 17904b8a43e9SChaotian Jing host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 17914b8a43e9SChaotian Jing host->save_para.iocon = readl(host->base + MSDC_IOCON); 17924b8a43e9SChaotian Jing host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 17934b8a43e9SChaotian Jing host->save_para.pad_tune = readl(host->base + MSDC_PAD_TUNE); 17944b8a43e9SChaotian Jing host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 17954b8a43e9SChaotian Jing host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 17966397b7f5SChaotian Jing host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 17971ede5cb8Syong mao host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 17986397b7f5SChaotian Jing host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 17994b8a43e9SChaotian Jing } 18004b8a43e9SChaotian Jing 18014b8a43e9SChaotian Jing static void msdc_restore_reg(struct msdc_host *host) 18024b8a43e9SChaotian Jing { 18034b8a43e9SChaotian Jing writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 18044b8a43e9SChaotian Jing writel(host->save_para.iocon, host->base + MSDC_IOCON); 18054b8a43e9SChaotian Jing writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 18064b8a43e9SChaotian Jing writel(host->save_para.pad_tune, host->base + MSDC_PAD_TUNE); 18074b8a43e9SChaotian Jing writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 18084b8a43e9SChaotian Jing writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 18096397b7f5SChaotian Jing writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 18101ede5cb8Syong mao writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 18116397b7f5SChaotian Jing writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 18124b8a43e9SChaotian Jing } 18134b8a43e9SChaotian Jing 18144b8a43e9SChaotian Jing static int msdc_runtime_suspend(struct device *dev) 18154b8a43e9SChaotian Jing { 18164b8a43e9SChaotian Jing struct mmc_host *mmc = dev_get_drvdata(dev); 18174b8a43e9SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 18184b8a43e9SChaotian Jing 18194b8a43e9SChaotian Jing msdc_save_reg(host); 18204b8a43e9SChaotian Jing msdc_gate_clock(host); 18214b8a43e9SChaotian Jing return 0; 18224b8a43e9SChaotian Jing } 18234b8a43e9SChaotian Jing 18244b8a43e9SChaotian Jing static int msdc_runtime_resume(struct device *dev) 18254b8a43e9SChaotian Jing { 18264b8a43e9SChaotian Jing struct mmc_host *mmc = dev_get_drvdata(dev); 18274b8a43e9SChaotian Jing struct msdc_host *host = mmc_priv(mmc); 18284b8a43e9SChaotian Jing 18294b8a43e9SChaotian Jing msdc_ungate_clock(host); 18304b8a43e9SChaotian Jing msdc_restore_reg(host); 18314b8a43e9SChaotian Jing return 0; 18324b8a43e9SChaotian Jing } 18334b8a43e9SChaotian Jing #endif 18344b8a43e9SChaotian Jing 18354b8a43e9SChaotian Jing static const struct dev_pm_ops msdc_dev_pm_ops = { 18364b8a43e9SChaotian Jing SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 18374b8a43e9SChaotian Jing pm_runtime_force_resume) 18384b8a43e9SChaotian Jing SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 18394b8a43e9SChaotian Jing }; 18404b8a43e9SChaotian Jing 184120848903SChaotian Jing static const struct of_device_id msdc_of_ids[] = { 184220848903SChaotian Jing { .compatible = "mediatek,mt8135-mmc", }, 184320848903SChaotian Jing {} 184420848903SChaotian Jing }; 18459cb02eefSJavier Martinez Canillas MODULE_DEVICE_TABLE(of, msdc_of_ids); 184620848903SChaotian Jing 184720848903SChaotian Jing static struct platform_driver mt_msdc_driver = { 184820848903SChaotian Jing .probe = msdc_drv_probe, 184920848903SChaotian Jing .remove = msdc_drv_remove, 185020848903SChaotian Jing .driver = { 185120848903SChaotian Jing .name = "mtk-msdc", 185220848903SChaotian Jing .of_match_table = msdc_of_ids, 18534b8a43e9SChaotian Jing .pm = &msdc_dev_pm_ops, 185420848903SChaotian Jing }, 185520848903SChaotian Jing }; 185620848903SChaotian Jing 185720848903SChaotian Jing module_platform_driver(mt_msdc_driver); 185820848903SChaotian Jing MODULE_LICENSE("GPL v2"); 185920848903SChaotian Jing MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 1860